[linux-block.git] / drivers / tty / serial / mxs-auart.c

/*
 * Freescale STMP37XX/STMP378X Application UART driver
 *
 * Author: dmitry pervushin <dimka@embeddedalley.com>
 *
 * Copyright 2008-2010 Freescale Semiconductor, Inc.
 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
 *
 * The code contained herein is licensed under the GNU General Public
 * License. You may obtain a copy of the GNU General Public License
 * Version 2 or later at the following locations:
 *
 * http://www.opensource.org/licenses/gpl-license.html
 * http://www.gnu.org/copyleft/gpl.html
 */

#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/init.h>
#include <linux/console.h>
#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/wait.h>
#include <linux/tty.h>
#include <linux/tty_driver.h>
#include <linux/tty_flip.h>
#include <linux/serial.h>
#include <linux/serial_core.h>
#include <linux/platform_device.h>
#include <linux/device.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/io.h>

#include <asm/cacheflush.h>

#define MXS_AUART_PORTS 5

#define AUART_CTRL0			0x00000000
#define AUART_CTRL0_SET			0x00000004
#define AUART_CTRL0_CLR			0x00000008
#define AUART_CTRL0_TOG			0x0000000c
#define AUART_CTRL1			0x00000010
#define AUART_CTRL1_SET			0x00000014
#define AUART_CTRL1_CLR			0x00000018
#define AUART_CTRL1_TOG			0x0000001c
#define AUART_CTRL2			0x00000020
#define AUART_CTRL2_SET			0x00000024
#define AUART_CTRL2_CLR			0x00000028
#define AUART_CTRL2_TOG			0x0000002c
#define AUART_LINECTRL			0x00000030
#define AUART_LINECTRL_SET		0x00000034
#define AUART_LINECTRL_CLR		0x00000038
#define AUART_LINECTRL_TOG		0x0000003c
#define AUART_LINECTRL2			0x00000040
#define AUART_LINECTRL2_SET		0x00000044
#define AUART_LINECTRL2_CLR		0x00000048
#define AUART_LINECTRL2_TOG		0x0000004c
#define AUART_INTR			0x00000050
#define AUART_INTR_SET			0x00000054
#define AUART_INTR_CLR			0x00000058
#define AUART_INTR_TOG			0x0000005c
#define AUART_DATA			0x00000060
#define AUART_STAT			0x00000070
#define AUART_DEBUG			0x00000080
#define AUART_VERSION			0x00000090
#define AUART_AUTOBAUD			0x000000a0

#define AUART_CTRL0_SFTRST			(1 << 31)
#define AUART_CTRL0_CLKGATE			(1 << 30)

#define AUART_CTRL2_CTSEN			(1 << 15)
#define AUART_CTRL2_RTS				(1 << 11)
#define AUART_CTRL2_RXE				(1 << 9)
#define AUART_CTRL2_TXE				(1 << 8)
#define AUART_CTRL2_UARTEN			(1 << 0)

#define AUART_LINECTRL_BAUD_DIVINT_SHIFT	16
#define AUART_LINECTRL_BAUD_DIVINT_MASK		0xffff0000
#define AUART_LINECTRL_BAUD_DIVINT(v)		(((v) & 0xffff) << 16)
#define AUART_LINECTRL_BAUD_DIVFRAC_SHIFT	8
#define AUART_LINECTRL_BAUD_DIVFRAC_MASK	0x00003f00
#define AUART_LINECTRL_BAUD_DIVFRAC(v)		(((v) & 0x3f) << 8)
#define AUART_LINECTRL_WLEN_MASK		0x00000060
#define AUART_LINECTRL_WLEN(v)			(((v) & 0x3) << 5)
#define AUART_LINECTRL_FEN			(1 << 4)
#define AUART_LINECTRL_STP2			(1 << 3)
#define AUART_LINECTRL_EPS			(1 << 2)
#define AUART_LINECTRL_PEN			(1 << 1)
#define AUART_LINECTRL_BRK			(1 << 0)

#define AUART_INTR_RTIEN			(1 << 22)
#define AUART_INTR_TXIEN			(1 << 21)
#define AUART_INTR_RXIEN			(1 << 20)
#define AUART_INTR_CTSMIEN			(1 << 17)
#define AUART_INTR_RTIS				(1 << 6)
#define AUART_INTR_TXIS				(1 << 5)
#define AUART_INTR_RXIS				(1 << 4)
#define AUART_INTR_CTSMIS			(1 << 1)

#define AUART_STAT_BUSY				(1 << 29)
#define AUART_STAT_CTS				(1 << 28)
#define AUART_STAT_TXFE				(1 << 27)
#define AUART_STAT_TXFF				(1 << 25)
#define AUART_STAT_RXFE				(1 << 24)
#define AUART_STAT_OERR				(1 << 19)
#define AUART_STAT_BERR				(1 << 18)
#define AUART_STAT_PERR				(1 << 17)
#define AUART_STAT_FERR				(1 << 16)

static struct uart_driver auart_driver;

struct mxs_auart_port {
	struct uart_port port;

	unsigned int flags;
	unsigned int ctrl;

	unsigned int irq;

	struct clk *clk;
	struct device *dev;
};

static void mxs_auart_stop_tx(struct uart_port *u);

#define to_auart_port(u) container_of(u, struct mxs_auart_port, port)

static inline void mxs_auart_tx_chars(struct mxs_auart_port *s)
{
	struct circ_buf *xmit = &s->port.state->xmit;

	while (!(readl(s->port.membase + AUART_STAT) &
		 AUART_STAT_TXFF)) {
		if (s->port.x_char) {
			s->port.icount.tx++;
			writel(s->port.x_char,
				     s->port.membase + AUART_DATA);
			s->port.x_char = 0;
			continue;
		}
		if (!uart_circ_empty(xmit) && !uart_tx_stopped(&s->port)) {
			s->port.icount.tx++;
			writel(xmit->buf[xmit->tail],
				     s->port.membase + AUART_DATA);
			xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
			if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
				uart_write_wakeup(&s->port);
		} else
			break;
	}
	if (uart_circ_empty(&(s->port.state->xmit)))
		writel(AUART_INTR_TXIEN,
			     s->port.membase + AUART_INTR_CLR);
	else
		writel(AUART_INTR_TXIEN,
			     s->port.membase + AUART_INTR_SET);

	if (uart_tx_stopped(&s->port))
		mxs_auart_stop_tx(&s->port);
}

static void mxs_auart_rx_char(struct mxs_auart_port *s)
{
	int flag;
	u32 stat;
	u8 c;

	c = readl(s->port.membase + AUART_DATA);
	stat = readl(s->port.membase + AUART_STAT);

	flag = TTY_NORMAL;
	s->port.icount.rx++;

	if (stat & AUART_STAT_BERR) {
		s->port.icount.brk++;
		if (uart_handle_break(&s->port))
			goto out;
	} else if (stat & AUART_STAT_PERR) {
		s->port.icount.parity++;
	} else if (stat & AUART_STAT_FERR) {
		s->port.icount.frame++;
	}

	/*
	 * Mask off conditions which should be ingored.
	 */
	stat &= s->port.read_status_mask;

	if (stat & AUART_STAT_BERR) {
		flag = TTY_BREAK;
	} else if (stat & AUART_STAT_PERR)
		flag = TTY_PARITY;
	else if (stat & AUART_STAT_FERR)
		flag = TTY_FRAME;

	if (stat & AUART_STAT_OERR)
		s->port.icount.overrun++;

	if (uart_handle_sysrq_char(&s->port, c))
		goto out;

	uart_insert_char(&s->port, stat, AUART_STAT_OERR, c, flag);
out:
	writel(stat, s->port.membase + AUART_STAT);
}

static void mxs_auart_rx_chars(struct mxs_auart_port *s)
{
	struct tty_struct *tty = s->port.state->port.tty;
	u32 stat = 0;

	for (;;) {
		stat = readl(s->port.membase + AUART_STAT);
		if (stat & AUART_STAT_RXFE)
			break;
		mxs_auart_rx_char(s);
	}

	writel(stat, s->port.membase + AUART_STAT);
	tty_flip_buffer_push(tty);
}

static int mxs_auart_request_port(struct uart_port *u)
{
	return 0;
}

static int mxs_auart_verify_port(struct uart_port *u,
				    struct serial_struct *ser)
{
	if (u->type != PORT_UNKNOWN && u->type != PORT_IMX)
		return -EINVAL;
	return 0;
}

static void mxs_auart_config_port(struct uart_port *u, int flags)
{
}

static const char *mxs_auart_type(struct uart_port *u)
{
	struct mxs_auart_port *s = to_auart_port(u);

	return dev_name(s->dev);
}

static void mxs_auart_release_port(struct uart_port *u)
{
}

static void mxs_auart_set_mctrl(struct uart_port *u, unsigned mctrl)
{
	struct mxs_auart_port *s = to_auart_port(u);

	u32 ctrl = readl(u->membase + AUART_CTRL2);

	ctrl &= ~AUART_CTRL2_RTS;
	if (mctrl & TIOCM_RTS)
		ctrl |= AUART_CTRL2_RTS;
	s->ctrl = mctrl;
	writel(ctrl, u->membase + AUART_CTRL2);
}

static u32 mxs_auart_get_mctrl(struct uart_port *u)
{
	struct mxs_auart_port *s = to_auart_port(u);
	u32 stat = readl(u->membase + AUART_STAT);
	int ctrl2 = readl(u->membase + AUART_CTRL2);
	u32 mctrl = s->ctrl;

	mctrl &= ~TIOCM_CTS;
	if (stat & AUART_STAT_CTS)
		mctrl |= TIOCM_CTS;

	if (ctrl2 & AUART_CTRL2_RTS)
		mctrl |= TIOCM_RTS;

	return mctrl;
}

static void mxs_auart_settermios(struct uart_port *u,
				 struct ktermios *termios,
				 struct ktermios *old)
{
	u32 bm, ctrl, ctrl2, div;
	unsigned int cflag, baud;

	cflag = termios->c_cflag;

	ctrl = AUART_LINECTRL_FEN;
	ctrl2 = readl(u->membase + AUART_CTRL2);

	/* byte size */
	switch (cflag & CSIZE) {
	case CS5:
		bm = 0;
		break;
	case CS6:
		bm = 1;
		break;
	case CS7:
		bm = 2;
		break;
	case CS8:
		bm = 3;
		break;
	default:
		return;
	}

	ctrl |= AUART_LINECTRL_WLEN(bm);

	/* parity */
	if (cflag & PARENB) {
		ctrl |= AUART_LINECTRL_PEN;
		if ((cflag & PARODD) == 0)
			ctrl |= AUART_LINECTRL_EPS;
	}

	u->read_status_mask = 0;

	if (termios->c_iflag & INPCK)
		u->read_status_mask |= AUART_STAT_PERR;
	if (termios->c_iflag & (BRKINT | PARMRK))
		u->read_status_mask |= AUART_STAT_BERR;

	/*
	 * Characters to ignore
	 */
	u->ignore_status_mask = 0;
	if (termios->c_iflag & IGNPAR)
		u->ignore_status_mask |= AUART_STAT_PERR;
	if (termios->c_iflag & IGNBRK) {
		u->ignore_status_mask |= AUART_STAT_BERR;
		/*
		 * If we're ignoring parity and break indicators,
		 * ignore overruns too (for real raw support).
		 */
		if (termios->c_iflag & IGNPAR)
			u->ignore_status_mask |= AUART_STAT_OERR;
	}

	/*
	 * ignore all characters if CREAD is not set
	 */
	if (cflag & CREAD)
		ctrl2 |= AUART_CTRL2_RXE;
	else
		ctrl2 &= ~AUART_CTRL2_RXE;

	/* figure out the stop bits requested */
	if (cflag & CSTOPB)
		ctrl |= AUART_LINECTRL_STP2;

	/* figure out the hardware flow control settings */
	if (cflag & CRTSCTS)
		ctrl2 |= AUART_CTRL2_CTSEN;
	else
		ctrl2 &= ~AUART_CTRL2_CTSEN;

	/* set baud rate */
	baud = uart_get_baud_rate(u, termios, old, 0, u->uartclk);
	div = u->uartclk * 32 / baud;
	ctrl |= AUART_LINECTRL_BAUD_DIVFRAC(div & 0x3F);
	ctrl |= AUART_LINECTRL_BAUD_DIVINT(div >> 6);

	writel(ctrl, u->membase + AUART_LINECTRL);
	writel(ctrl2, u->membase + AUART_CTRL2);
}

static irqreturn_t mxs_auart_irq_handle(int irq, void *context)
{
	u32 istatus, istat;
	struct mxs_auart_port *s = context;
	u32 stat = readl(s->port.membase + AUART_STAT);

	istatus = istat = readl(s->port.membase + AUART_INTR);

	if (istat & AUART_INTR_CTSMIS) {
		uart_handle_cts_change(&s->port, stat & AUART_STAT_CTS);
		writel(AUART_INTR_CTSMIS,
				s->port.membase + AUART_INTR_CLR);
		istat &= ~AUART_INTR_CTSMIS;
	}

	if (istat & (AUART_INTR_RTIS | AUART_INTR_RXIS)) {
		mxs_auart_rx_chars(s);
		istat &= ~(AUART_INTR_RTIS | AUART_INTR_RXIS);
	}

	if (istat & AUART_INTR_TXIS) {
		mxs_auart_tx_chars(s);
		istat &= ~AUART_INTR_TXIS;
	}

	writel(istatus & (AUART_INTR_RTIS
		| AUART_INTR_TXIS
		| AUART_INTR_RXIS
		| AUART_INTR_CTSMIS),
			s->port.membase + AUART_INTR_CLR);

	return IRQ_HANDLED;
}

static void mxs_auart_reset(struct uart_port *u)
{
	int i;
	unsigned int reg;

	writel(AUART_CTRL0_SFTRST, u->membase + AUART_CTRL0_CLR);

	for (i = 0; i < 10000; i++) {
		reg = readl(u->membase + AUART_CTRL0);
		if (!(reg & AUART_CTRL0_SFTRST))
			break;
		udelay(3);
	}
	writel(AUART_CTRL0_CLKGATE, u->membase + AUART_CTRL0_CLR);
}

static int mxs_auart_startup(struct uart_port *u)
{
	struct mxs_auart_port *s = to_auart_port(u);

	clk_enable(s->clk);

	writel(AUART_CTRL0_CLKGATE, u->membase + AUART_CTRL0_CLR);

	writel(AUART_CTRL2_UARTEN, u->membase + AUART_CTRL2_SET);

	writel(AUART_INTR_RXIEN | AUART_INTR_RTIEN | AUART_INTR_CTSMIEN,
			u->membase + AUART_INTR);

	/*
	 * Enable fifo so all four bytes of a DMA word are written to
	 * output (otherwise, only the LSB is written, ie. 1 in 4 bytes)
	 */
	writel(AUART_LINECTRL_FEN, u->membase + AUART_LINECTRL_SET);

	return 0;
}

static void mxs_auart_shutdown(struct uart_port *u)
{
	struct mxs_auart_port *s = to_auart_port(u);

	writel(AUART_CTRL2_UARTEN, u->membase + AUART_CTRL2_CLR);

	writel(AUART_CTRL0_CLKGATE, u->membase + AUART_CTRL0_SET);

	writel(AUART_INTR_RXIEN | AUART_INTR_RTIEN | AUART_INTR_CTSMIEN,
			u->membase + AUART_INTR_CLR);

	clk_disable(s->clk);
}

static unsigned int mxs_auart_tx_empty(struct uart_port *u)
{
	if (readl(u->membase + AUART_STAT) & AUART_STAT_TXFE)
		return TIOCSER_TEMT;
	else
		return 0;
}

static void mxs_auart_start_tx(struct uart_port *u)
{
	struct mxs_auart_port *s = to_auart_port(u);

	/* enable transmitter */
	writel(AUART_CTRL2_TXE, u->membase + AUART_CTRL2_SET);

	mxs_auart_tx_chars(s);
}

static void mxs_auart_stop_tx(struct uart_port *u)
{
	writel(AUART_CTRL2_TXE, u->membase + AUART_CTRL2_CLR);
}

static void mxs_auart_stop_rx(struct uart_port *u)
{
	writel(AUART_CTRL2_RXE, u->membase + AUART_CTRL2_CLR);
}

static void mxs_auart_break_ctl(struct uart_port *u, int ctl)
{
	if (ctl)
		writel(AUART_LINECTRL_BRK,
			     u->membase + AUART_LINECTRL_SET);
	else
		writel(AUART_LINECTRL_BRK,
			     u->membase + AUART_LINECTRL_CLR);
}

static void mxs_auart_enable_ms(struct uart_port *port)
{
	/* just empty */
}

static struct uart_ops mxs_auart_ops = {
	.tx_empty       = mxs_auart_tx_empty,
	.start_tx       = mxs_auart_start_tx,
	.stop_tx	= mxs_auart_stop_tx,
	.stop_rx	= mxs_auart_stop_rx,
	.enable_ms      = mxs_auart_enable_ms,
	.break_ctl      = mxs_auart_break_ctl,
	.set_mctrl	= mxs_auart_set_mctrl,
	.get_mctrl      = mxs_auart_get_mctrl,
	.startup	= mxs_auart_startup,
	.shutdown       = mxs_auart_shutdown,
	.set_termios    = mxs_auart_settermios,
	.type	   	= mxs_auart_type,
	.release_port   = mxs_auart_release_port,
	.request_port   = mxs_auart_request_port,
	.config_port    = mxs_auart_config_port,
	.verify_port    = mxs_auart_verify_port,
};

static struct mxs_auart_port *auart_port[MXS_AUART_PORTS];

#ifdef CONFIG_SERIAL_MXS_AUART_CONSOLE
static void mxs_auart_console_putchar(struct uart_port *port, int ch)
{
	unsigned int to = 1000;

	while (readl(port->membase + AUART_STAT) & AUART_STAT_TXFF) {
		if (!to--)
			break;
		udelay(1);
	}

	writel(ch, port->membase + AUART_DATA);
}

static void
auart_console_write(struct console *co, const char *str, unsigned int count)
{
	struct mxs_auart_port *s;
	struct uart_port *port;
	unsigned int old_ctrl0, old_ctrl2;
	unsigned int to = 1000;

	if (co->index >	MXS_AUART_PORTS || co->index < 0)
		return;

	s = auart_port[co->index];
	port = &s->port;

	clk_enable(s->clk);

	/* First save the CR then disable the interrupts */
	old_ctrl2 = readl(port->membase + AUART_CTRL2);
	old_ctrl0 = readl(port->membase + AUART_CTRL0);

	writel(AUART_CTRL0_CLKGATE,
		     port->membase + AUART_CTRL0_CLR);
	writel(AUART_CTRL2_UARTEN | AUART_CTRL2_TXE,
		     port->membase + AUART_CTRL2_SET);

	uart_console_write(port, str, count, mxs_auart_console_putchar);

	/*
	 * Finally, wait for transmitter to become empty
	 * and restore the TCR
	 */
	while (readl(port->membase + AUART_STAT) & AUART_STAT_BUSY) {
		if (!to--)
			break;
		udelay(1);
	}

	writel(old_ctrl0, port->membase + AUART_CTRL0);
	writel(old_ctrl2, port->membase + AUART_CTRL2);

	clk_disable(s->clk);
}

static void __init
auart_console_get_options(struct uart_port *port, int *baud,
			  int *parity, int *bits)
{
	unsigned int lcr_h, quot;

	if (!(readl(port->membase + AUART_CTRL2) & AUART_CTRL2_UARTEN))
		return;

	lcr_h = readl(port->membase + AUART_LINECTRL);

	*parity = 'n';
	if (lcr_h & AUART_LINECTRL_PEN) {
		if (lcr_h & AUART_LINECTRL_EPS)
			*parity = 'e';
		else
			*parity = 'o';
	}

	if ((lcr_h & AUART_LINECTRL_WLEN_MASK) == AUART_LINECTRL_WLEN(2))
		*bits = 7;
	else
		*bits = 8;

	quot = ((readl(port->membase + AUART_LINECTRL)
			& AUART_LINECTRL_BAUD_DIVINT_MASK))
			    >> (AUART_LINECTRL_BAUD_DIVINT_SHIFT - 6);
	quot |= ((readl(port->membase + AUART_LINECTRL)
			& AUART_LINECTRL_BAUD_DIVFRAC_MASK))
				>> AUART_LINECTRL_BAUD_DIVFRAC_SHIFT;
	if (quot == 0)
		quot = 1;

	*baud = (port->uartclk << 2) / quot;
}

static int __init
auart_console_setup(struct console *co, char *options)
{
	struct mxs_auart_port *s;
	int baud = 9600;
	int bits = 8;
	int parity = 'n';
	int flow = 'n';
	int ret;

	/*
	 * Check whether an invalid uart number has been specified, and
	 * if so, search for the first available port that does have
	 * console support.
	 */
	if (co->index == -1 || co->index >= ARRAY_SIZE(auart_port))
		co->index = 0;
	s = auart_port[co->index];
	if (!s)
		return -ENODEV;

	clk_enable(s->clk);

	if (options)
		uart_parse_options(options, &baud, &parity, &bits, &flow);
	else
		auart_console_get_options(&s->port, &baud, &parity, &bits);

	ret = uart_set_options(&s->port, co, baud, parity, bits, flow);

	clk_disable(s->clk);

	return ret;
}

static struct console auart_console = {
	.name		= "ttyAPP",
	.write		= auart_console_write,
	.device		= uart_console_device,
	.setup		= auart_console_setup,
	.flags		= CON_PRINTBUFFER,
	.index		= -1,
	.data		= &auart_driver,
};
#endif

static struct uart_driver auart_driver = {
	.owner		= THIS_MODULE,
	.driver_name	= "ttyAPP",
	.dev_name	= "ttyAPP",
	.major		= 0,
	.minor		= 0,
	.nr		= MXS_AUART_PORTS,
#ifdef CONFIG_SERIAL_MXS_AUART_CONSOLE
	.cons =		&auart_console,
#endif
};

static int __devinit mxs_auart_probe(struct platform_device *pdev)
{
	struct mxs_auart_port *s;
	u32 version;
	int ret = 0;
	struct resource *r;

	s = kzalloc(sizeof(struct mxs_auart_port), GFP_KERNEL);
	if (!s) {
		ret = -ENOMEM;
		goto out;
	}

	s->clk = clk_get(&pdev->dev, NULL);
	if (IS_ERR(s->clk)) {
		ret = PTR_ERR(s->clk);
		goto out_free;
	}

	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!r) {
		ret = -ENXIO;
		goto out_free_clk;
	}

	s->port.mapbase = r->start;
	s->port.membase = ioremap(r->start, resource_size(r));
	s->port.ops = &mxs_auart_ops;
	s->port.iotype = UPIO_MEM;
	s->port.line = pdev->id < 0 ? 0 : pdev->id;
	s->port.fifosize = 16;
	s->port.uartclk = clk_get_rate(s->clk);
	s->port.type = PORT_IMX;
	s->port.dev = s->dev = get_device(&pdev->dev);

	s->flags = 0;
	s->ctrl = 0;

	s->irq = platform_get_irq(pdev, 0);
	s->port.irq = s->irq;
	ret = request_irq(s->irq, mxs_auart_irq_handle, 0, dev_name(&pdev->dev), s);
	if (ret)
		goto out_free_clk;

	platform_set_drvdata(pdev, s);

	auart_port[pdev->id] = s;

	mxs_auart_reset(&s->port);

	ret = uart_add_one_port(&auart_driver, &s->port);
	if (ret)
		goto out_free_irq;

	version = readl(s->port.membase + AUART_VERSION);
	dev_info(&pdev->dev, "Found APPUART %d.%d.%d\n",
	       (version >> 24) & 0xff,
	       (version >> 16) & 0xff, version & 0xffff);

	return 0;

out_free_irq:
	auart_port[pdev->id] = NULL;
	free_irq(s->irq, s);
out_free_clk:
	clk_put(s->clk);
out_free:
	kfree(s);
out:
	return ret;
}

static int __devexit mxs_auart_remove(struct platform_device *pdev)
{
	struct mxs_auart_port *s = platform_get_drvdata(pdev);

	uart_remove_one_port(&auart_driver, &s->port);

	auart_port[pdev->id] = NULL;

	clk_put(s->clk);
	free_irq(s->irq, s);
	kfree(s);

	return 0;
}

static struct platform_driver mxs_auart_driver = {
	.probe = mxs_auart_probe,
	.remove = __devexit_p(mxs_auart_remove),
	.driver = {
		.name = "mxs-auart",
		.owner = THIS_MODULE,
	},
};

static int __init mxs_auart_init(void)
{
	int r;

	r = uart_register_driver(&auart_driver);
	if (r)
		goto out;

	r = platform_driver_register(&mxs_auart_driver);
	if (r)
		goto out_err;

	return 0;
out_err:
	uart_unregister_driver(&auart_driver);
out:
	return r;
}

static void __exit mxs_auart_exit(void)
{
	platform_driver_unregister(&mxs_auart_driver);
	uart_unregister_driver(&auart_driver);
}

module_init(mxs_auart_init);
module_exit(mxs_auart_exit);
MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("Freescale MXS application uart driver");
Commit	Line	Data
47d37d6f SH	1	/*
	2	* Freescale STMP37XX/STMP378X Application UART driver
	3	*
	4	* Author: dmitry pervushin <dimka@embeddedalley.com>
	5	*
	6	* Copyright 2008-2010 Freescale Semiconductor, Inc.
	7	* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
	8	*
	9	* The code contained herein is licensed under the GNU General Public
	10	* License. You may obtain a copy of the GNU General Public License
	11	* Version 2 or later at the following locations:
	12	*
	13	* http://www.opensource.org/licenses/gpl-license.html
	14	* http://www.gnu.org/copyleft/gpl.html
	15	*/
	16
	17	#include <linux/kernel.h>
47d37d6f SH	18	#include <linux/errno.h>
	19	#include <linux/init.h>
	20	#include <linux/console.h>
	21	#include <linux/interrupt.h>
	22	#include <linux/module.h>
	23	#include <linux/slab.h>
	24	#include <linux/wait.h>
	25	#include <linux/tty.h>
	26	#include <linux/tty_driver.h>
	27	#include <linux/tty_flip.h>
	28	#include <linux/serial.h>
	29	#include <linux/serial_core.h>
	30	#include <linux/platform_device.h>
	31	#include <linux/device.h>
	32	#include <linux/clk.h>
	33	#include <linux/delay.h>
	34	#include <linux/io.h>
	35
	36	#include <asm/cacheflush.h>
	37
	38	#define MXS_AUART_PORTS 5
	39
	40	#define AUART_CTRL0 0x00000000
	41	#define AUART_CTRL0_SET 0x00000004
	42	#define AUART_CTRL0_CLR 0x00000008
	43	#define AUART_CTRL0_TOG 0x0000000c
	44	#define AUART_CTRL1 0x00000010
	45	#define AUART_CTRL1_SET 0x00000014
	46	#define AUART_CTRL1_CLR 0x00000018
	47	#define AUART_CTRL1_TOG 0x0000001c
	48	#define AUART_CTRL2 0x00000020
	49	#define AUART_CTRL2_SET 0x00000024
	50	#define AUART_CTRL2_CLR 0x00000028
	51	#define AUART_CTRL2_TOG 0x0000002c
	52	#define AUART_LINECTRL 0x00000030
	53	#define AUART_LINECTRL_SET 0x00000034
	54	#define AUART_LINECTRL_CLR 0x00000038
	55	#define AUART_LINECTRL_TOG 0x0000003c
	56	#define AUART_LINECTRL2 0x00000040
	57	#define AUART_LINECTRL2_SET 0x00000044
	58	#define AUART_LINECTRL2_CLR 0x00000048
	59	#define AUART_LINECTRL2_TOG 0x0000004c
	60	#define AUART_INTR 0x00000050
	61	#define AUART_INTR_SET 0x00000054
	62	#define AUART_INTR_CLR 0x00000058
	63	#define AUART_INTR_TOG 0x0000005c
	64	#define AUART_DATA 0x00000060
	65	#define AUART_STAT 0x00000070
	66	#define AUART_DEBUG 0x00000080
	67	#define AUART_VERSION 0x00000090
	68	#define AUART_AUTOBAUD 0x000000a0
	69
	70	#define AUART_CTRL0_SFTRST (1 << 31)
	71	#define AUART_CTRL0_CLKGATE (1 << 30)
	72
	73	#define AUART_CTRL2_CTSEN (1 << 15)
	74	#define AUART_CTRL2_RTS (1 << 11)
	75	#define AUART_CTRL2_RXE (1 << 9)
	76	#define AUART_CTRL2_TXE (1 << 8)
	77	#define AUART_CTRL2_UARTEN (1 << 0)
	78
	79	#define AUART_LINECTRL_BAUD_DIVINT_SHIFT 16
	80	#define AUART_LINECTRL_BAUD_DIVINT_MASK 0xffff0000
	81	#define AUART_LINECTRL_BAUD_DIVINT(v) (((v) & 0xffff) << 16)
82	#define AUART_LINECTRL_BAUD_DIVFRAC_SHIFT 8
83	#define AUART_LINECTRL_BAUD_DIVFRAC_MASK 0x00003f00
84	#define AUART_LINECTRL_BAUD_DIVFRAC(v) (((v) & 0x3f) << 8)
85	#define AUART_LINECTRL_WLEN_MASK 0x00000060
86	#define AUART_LINECTRL_WLEN(v) (((v) & 0x3) << 5)
87	#define AUART_LINECTRL_FEN (1 << 4)
88	#define AUART_LINECTRL_STP2 (1 << 3)
89	#define AUART_LINECTRL_EPS (1 << 2)
90	#define AUART_LINECTRL_PEN (1 << 1)
91	#define AUART_LINECTRL_BRK (1 << 0)
92
93	#define AUART_INTR_RTIEN (1 << 22)
94	#define AUART_INTR_TXIEN (1 << 21)
95	#define AUART_INTR_RXIEN (1 << 20)
96	#define AUART_INTR_CTSMIEN (1 << 17)
97	#define AUART_INTR_RTIS (1 << 6)
98	#define AUART_INTR_TXIS (1 << 5)
99	#define AUART_INTR_RXIS (1 << 4)
100	#define AUART_INTR_CTSMIS (1 << 1)
101
102	#define AUART_STAT_BUSY (1 << 29)
103	#define AUART_STAT_CTS (1 << 28)
104	#define AUART_STAT_TXFE (1 << 27)
105	#define AUART_STAT_TXFF (1 << 25)
106	#define AUART_STAT_RXFE (1 << 24)
107	#define AUART_STAT_OERR (1 << 19)
108	#define AUART_STAT_BERR (1 << 18)
109	#define AUART_STAT_PERR (1 << 17)
110	#define AUART_STAT_FERR (1 << 16)
111
112	static struct uart_driver auart_driver;
113
114	struct mxs_auart_port {
115	struct uart_port port;
116
117	unsigned int flags;
118	unsigned int ctrl;
119
120	unsigned int irq;
121
122	struct clk *clk;
123	struct device *dev;
124	};
125
126	static void mxs_auart_stop_tx(struct uart_port *u);
127
128	#define to_auart_port(u) container_of(u, struct mxs_auart_port, port)
129
130	static inline void mxs_auart_tx_chars(struct mxs_auart_port *s)
131	{
132	struct circ_buf *xmit = &s->port.state->xmit;
133
134	while (!(readl(s->port.membase + AUART_STAT) &
135	AUART_STAT_TXFF)) {
136	if (s->port.x_char) {
137	s->port.icount.tx++;
138	writel(s->port.x_char,
139	s->port.membase + AUART_DATA);
140	s->port.x_char = 0;
141	continue;
142	}
143	if (!uart_circ_empty(xmit) && !uart_tx_stopped(&s->port)) {
144	s->port.icount.tx++;
145	writel(xmit->buf[xmit->tail],
146	s->port.membase + AUART_DATA);
147	xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
148	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
149	uart_write_wakeup(&s->port);
150	} else
151	break;
152	}
153	if (uart_circ_empty(&(s->port.state->xmit)))
154	writel(AUART_INTR_TXIEN,
155	s->port.membase + AUART_INTR_CLR);
156	else
157	writel(AUART_INTR_TXIEN,
158	s->port.membase + AUART_INTR_SET);
159
160	if (uart_tx_stopped(&s->port))
161	mxs_auart_stop_tx(&s->port);
162	}
163
164	static void mxs_auart_rx_char(struct mxs_auart_port *s)
165	{
166	int flag;
167	u32 stat;
168	u8 c;
169
170	c = readl(s->port.membase + AUART_DATA);
171	stat = readl(s->port.membase + AUART_STAT);
172
173	flag = TTY_NORMAL;
174	s->port.icount.rx++;
175
176	if (stat & AUART_STAT_BERR) {
177	s->port.icount.brk++;
178	if (uart_handle_break(&s->port))
179	goto out;
180	} else if (stat & AUART_STAT_PERR) {
181	s->port.icount.parity++;
182	} else if (stat & AUART_STAT_FERR) {
183	s->port.icount.frame++;
184	}
185
186	/*
187	* Mask off conditions which should be ingored.
188	*/
189	stat &= s->port.read_status_mask;
190
191	if (stat & AUART_STAT_BERR) {
192	flag = TTY_BREAK;
193	} else if (stat & AUART_STAT_PERR)
194	flag = TTY_PARITY;
195	else if (stat & AUART_STAT_FERR)
196	flag = TTY_FRAME;
197
198	if (stat & AUART_STAT_OERR)
199	s->port.icount.overrun++;
200
201	if (uart_handle_sysrq_char(&s->port, c))
202	goto out;
203
204	uart_insert_char(&s->port, stat, AUART_STAT_OERR, c, flag);
205	out:
206	writel(stat, s->port.membase + AUART_STAT);
207	}
208
209	static void mxs_auart_rx_chars(struct mxs_auart_port *s)
210	{
211	struct tty_struct *tty = s->port.state->port.tty;
212	u32 stat = 0;
213
214	for (;;) {
215	stat = readl(s->port.membase + AUART_STAT);
216	if (stat & AUART_STAT_RXFE)
217	break;
218	mxs_auart_rx_char(s);
219	}
220
221	writel(stat, s->port.membase + AUART_STAT);
222	tty_flip_buffer_push(tty);
223	}
224
225	static int mxs_auart_request_port(struct uart_port *u)
226	{
227	return 0;
228	}
229
230	static int mxs_auart_verify_port(struct uart_port *u,
231	struct serial_struct *ser)
232	{
233	if (u->type != PORT_UNKNOWN && u->type != PORT_IMX)
234	return -EINVAL;
235	return 0;
236	}
237
238	static void mxs_auart_config_port(struct uart_port *u, int flags)
239	{
240	}
241
242	static const char mxs_auart_type(struct uart_port u)
243	{
244	struct mxs_auart_port *s = to_auart_port(u);
245
246	return dev_name(s->dev);
247	}
248
249	static void mxs_auart_release_port(struct uart_port *u)
250	{
251	}
252
253	static void mxs_auart_set_mctrl(struct uart_port *u, unsigned mctrl)
254	{
255	struct mxs_auart_port *s = to_auart_port(u);
256
257	u32 ctrl = readl(u->membase + AUART_CTRL2);
258
259	ctrl &= ~AUART_CTRL2_RTS;
260	if (mctrl & TIOCM_RTS)
261	ctrl \|= AUART_CTRL2_RTS;
262	s->ctrl = mctrl;
263	writel(ctrl, u->membase + AUART_CTRL2);
264	}
265
266	static u32 mxs_auart_get_mctrl(struct uart_port *u)
267	{
268	struct mxs_auart_port *s = to_auart_port(u);
269	u32 stat = readl(u->membase + AUART_STAT);
270	int ctrl2 = readl(u->membase + AUART_CTRL2);
271	u32 mctrl = s->ctrl;
272
273	mctrl &= ~TIOCM_CTS;
274	if (stat & AUART_STAT_CTS)
275	mctrl \|= TIOCM_CTS;
276
277	if (ctrl2 & AUART_CTRL2_RTS)
278	mctrl \|= TIOCM_RTS;
279
280	return mctrl;
281	}
282
283	static void mxs_auart_settermios(struct uart_port *u,
284	struct ktermios *termios,
285	struct ktermios *old)
286	{
287	u32 bm, ctrl, ctrl2, div;
288	unsigned int cflag, baud;
289
290	cflag = termios->c_cflag;
291
292	ctrl = AUART_LINECTRL_FEN;
293	ctrl2 = readl(u->membase + AUART_CTRL2);
294
295	/* byte size */
296	switch (cflag & CSIZE) {
297	case CS5:
298	bm = 0;
299	break;
300	case CS6:
301	bm = 1;
302	break;
303	case CS7:
304	bm = 2;
305	break;
306	case CS8:
307	bm = 3;
308	break;
309	default:
310	return;
311	}
312
313	ctrl \|= AUART_LINECTRL_WLEN(bm);
314
315	/* parity */
316	if (cflag & PARENB) {
317	ctrl \|= AUART_LINECTRL_PEN;
318	if ((cflag & PARODD) == 0)
319	ctrl \|= AUART_LINECTRL_EPS;
320	}
321
322	u->read_status_mask = 0;
323
324	if (termios->c_iflag & INPCK)
325	u->read_status_mask \|= AUART_STAT_PERR;
326	if (termios->c_iflag & (BRKINT \| PARMRK))
327	u->read_status_mask \|= AUART_STAT_BERR;
328
329	/*
330	* Characters to ignore
331	*/
332	u->ignore_status_mask = 0;
333	if (termios->c_iflag & IGNPAR)
334	u->ignore_status_mask \|= AUART_STAT_PERR;
335	if (termios->c_iflag & IGNBRK) {
336	u->ignore_status_mask \|= AUART_STAT_BERR;
337	/*
338	* If we're ignoring parity and break indicators,
339	* ignore overruns too (for real raw support).
340	*/
341	if (termios->c_iflag & IGNPAR)
342	u->ignore_status_mask \|= AUART_STAT_OERR;
343	}
344
345	/*
346	* ignore all characters if CREAD is not set
347	*/
348	if (cflag & CREAD)
349	ctrl2 \|= AUART_CTRL2_RXE;
350	else
351	ctrl2 &= ~AUART_CTRL2_RXE;
352
353	/* figure out the stop bits requested */
354	if (cflag & CSTOPB)
355	ctrl \|= AUART_LINECTRL_STP2;
356
357	/* figure out the hardware flow control settings */
358	if (cflag & CRTSCTS)
359	ctrl2 \|= AUART_CTRL2_CTSEN;
360	else
361	ctrl2 &= ~AUART_CTRL2_CTSEN;
362
363	/* set baud rate */
364	baud = uart_get_baud_rate(u, termios, old, 0, u->uartclk);
365	div = u->uartclk * 32 / baud;
366	ctrl \|= AUART_LINECTRL_BAUD_DIVFRAC(div & 0x3F);
367	ctrl \|= AUART_LINECTRL_BAUD_DIVINT(div >> 6);
368
369	writel(ctrl, u->membase + AUART_LINECTRL);
370	writel(ctrl2, u->membase + AUART_CTRL2);
371	}
372
373	static irqreturn_t mxs_auart_irq_handle(int irq, void *context)
374	{
375	u32 istatus, istat;
376	struct mxs_auart_port *s = context;
377	u32 stat = readl(s->port.membase + AUART_STAT);
378
379	istatus = istat = readl(s->port.membase + AUART_INTR);
380
381	if (istat & AUART_INTR_CTSMIS) {
382	uart_handle_cts_change(&s->port, stat & AUART_STAT_CTS);
383	writel(AUART_INTR_CTSMIS,
384	s->port.membase + AUART_INTR_CLR);
385	istat &= ~AUART_INTR_CTSMIS;
386	}
387
388	if (istat & (AUART_INTR_RTIS \| AUART_INTR_RXIS)) {
389	mxs_auart_rx_chars(s);
390	istat &= ~(AUART_INTR_RTIS \| AUART_INTR_RXIS);
391	}
392
393	if (istat & AUART_INTR_TXIS) {
394	mxs_auart_tx_chars(s);
395	istat &= ~AUART_INTR_TXIS;
396	}
397
398	writel(istatus & (AUART_INTR_RTIS
399	\| AUART_INTR_TXIS
400	\| AUART_INTR_RXIS
401	\| AUART_INTR_CTSMIS),
402	s->port.membase + AUART_INTR_CLR);
403
404	return IRQ_HANDLED;
405	}
406
407	static void mxs_auart_reset(struct uart_port *u)
408	{
409	int i;
410	unsigned int reg;
411
412	writel(AUART_CTRL0_SFTRST, u->membase + AUART_CTRL0_CLR);
413
414	for (i = 0; i < 10000; i++) {
415	reg = readl(u->membase + AUART_CTRL0);
416	if (!(reg & AUART_CTRL0_SFTRST))
417	break;
418	udelay(3);
419	}
420	writel(AUART_CTRL0_CLKGATE, u->membase + AUART_CTRL0_CLR);
421	}
422
423	static int mxs_auart_startup(struct uart_port *u)
424	{
425	struct mxs_auart_port *s = to_auart_port(u);
426
427	clk_enable(s->clk);
428
429	writel(AUART_CTRL0_CLKGATE, u->membase + AUART_CTRL0_CLR);
430
431	writel(AUART_CTRL2_UARTEN, u->membase + AUART_CTRL2_SET);
432
433	writel(AUART_INTR_RXIEN \| AUART_INTR_RTIEN \| AUART_INTR_CTSMIEN,
434	u->membase + AUART_INTR);
435
436	/*
437	* Enable fifo so all four bytes of a DMA word are written to
438	* output (otherwise, only the LSB is written, ie. 1 in 4 bytes)
439	*/
440	writel(AUART_LINECTRL_FEN, u->membase + AUART_LINECTRL_SET);
441
442	return 0;
443	}
444
445	static void mxs_auart_shutdown(struct uart_port *u)
446	{
447	struct mxs_auart_port *s = to_auart_port(u);
448
449	writel(AUART_CTRL2_UARTEN, u->membase + AUART_CTRL2_CLR);
450
451	writel(AUART_CTRL0_CLKGATE, u->membase + AUART_CTRL0_SET);
452
453	writel(AUART_INTR_RXIEN \| AUART_INTR_RTIEN \| AUART_INTR_CTSMIEN,
454	u->membase + AUART_INTR_CLR);
455
456	clk_disable(s->clk);
457	}
458
459	static unsigned int mxs_auart_tx_empty(struct uart_port *u)
460	{
461	if (readl(u->membase + AUART_STAT) & AUART_STAT_TXFE)
462	return TIOCSER_TEMT;
463	else
464	return 0;
465	}
466
467	static void mxs_auart_start_tx(struct uart_port *u)
468	{
469	struct mxs_auart_port *s = to_auart_port(u);
470
471	/* enable transmitter */
472	writel(AUART_CTRL2_TXE, u->membase + AUART_CTRL2_SET);
473
474	mxs_auart_tx_chars(s);
475	}
476
477	static void mxs_auart_stop_tx(struct uart_port *u)
478	{
479	writel(AUART_CTRL2_TXE, u->membase + AUART_CTRL2_CLR);
480	}
481
482	static void mxs_auart_stop_rx(struct uart_port *u)
483	{
484	writel(AUART_CTRL2_RXE, u->membase + AUART_CTRL2_CLR);
485	}
486
487	static void mxs_auart_break_ctl(struct uart_port *u, int ctl)
488	{
489	if (ctl)
490	writel(AUART_LINECTRL_BRK,
491	u->membase + AUART_LINECTRL_SET);
492	else
493	writel(AUART_LINECTRL_BRK,
494	u->membase + AUART_LINECTRL_CLR);
495	}
496
497	static void mxs_auart_enable_ms(struct uart_port *port)
498	{
499	/* just empty */
500	}
501
502	static struct uart_ops mxs_auart_ops = {
503	.tx_empty = mxs_auart_tx_empty,
504	.start_tx = mxs_auart_start_tx,
505	.stop_tx = mxs_auart_stop_tx,
506	.stop_rx = mxs_auart_stop_rx,
507	.enable_ms = mxs_auart_enable_ms,
508	.break_ctl = mxs_auart_break_ctl,
509	.set_mctrl = mxs_auart_set_mctrl,
510	.get_mctrl = mxs_auart_get_mctrl,
511	.startup = mxs_auart_startup,
512	.shutdown = mxs_auart_shutdown,
513	.set_termios = mxs_auart_settermios,
514	.type = mxs_auart_type,
515	.release_port = mxs_auart_release_port,
516	.request_port = mxs_auart_request_port,
517	.config_port = mxs_auart_config_port,
518	.verify_port = mxs_auart_verify_port,
519	};
520
521	static struct mxs_auart_port *auart_port[MXS_AUART_PORTS];
522
523	#ifdef CONFIG_SERIAL_MXS_AUART_CONSOLE
524	static void mxs_auart_console_putchar(struct uart_port *port, int ch)
525	{
526	unsigned int to = 1000;
527
528	while (readl(port->membase + AUART_STAT) & AUART_STAT_TXFF) {
529	if (!to--)
530	break;
531	udelay(1);
532	}
533
534	writel(ch, port->membase + AUART_DATA);
535	}
536
537	static void
538	auart_console_write(struct console co, const char str, unsigned int count)
539	{
540	struct mxs_auart_port *s;
541	struct uart_port *port;
542	unsigned int old_ctrl0, old_ctrl2;
543	unsigned int to = 1000;
544
545	if (co->index > MXS_AUART_PORTS \|\| co->index < 0)
546	return;
547
548	s = auart_port[co->index];
549	port = &s->port;
550
551	clk_enable(s->clk);
552
553	/* First save the CR then disable the interrupts */
554	old_ctrl2 = readl(port->membase + AUART_CTRL2);
555	old_ctrl0 = readl(port->membase + AUART_CTRL0);
556
557	writel(AUART_CTRL0_CLKGATE,
558	port->membase + AUART_CTRL0_CLR);
559	writel(AUART_CTRL2_UARTEN \| AUART_CTRL2_TXE,
560	port->membase + AUART_CTRL2_SET);
561
562	uart_console_write(port, str, count, mxs_auart_console_putchar);
563
564	/*
565	* Finally, wait for transmitter to become empty
566	* and restore the TCR
567	*/
568	while (readl(port->membase + AUART_STAT) & AUART_STAT_BUSY) {
569	if (!to--)
570	break;
571	udelay(1);
572	}
573
574	writel(old_ctrl0, port->membase + AUART_CTRL0);
575	writel(old_ctrl2, port->membase + AUART_CTRL2);
576
577	clk_disable(s->clk);
578	}
579
580	static void __init
581	auart_console_get_options(struct uart_port port, int baud,
582	int parity, int bits)
583	{
584	unsigned int lcr_h, quot;
585
586	if (!(readl(port->membase + AUART_CTRL2) & AUART_CTRL2_UARTEN))
587	return;
588
589	lcr_h = readl(port->membase + AUART_LINECTRL);
590
591	*parity = 'n';
592	if (lcr_h & AUART_LINECTRL_PEN) {
593	if (lcr_h & AUART_LINECTRL_EPS)
594	*parity = 'e';
595	else
596	*parity = 'o';
597	}
598
599	if ((lcr_h & AUART_LINECTRL_WLEN_MASK) == AUART_LINECTRL_WLEN(2))
600	*bits = 7;
601	else
602	*bits = 8;
603
604	quot = ((readl(port->membase + AUART_LINECTRL)
605	& AUART_LINECTRL_BAUD_DIVINT_MASK))
606	>> (AUART_LINECTRL_BAUD_DIVINT_SHIFT - 6);
607	quot \|= ((readl(port->membase + AUART_LINECTRL)
608	& AUART_LINECTRL_BAUD_DIVFRAC_MASK))
609	>> AUART_LINECTRL_BAUD_DIVFRAC_SHIFT;
610	if (quot == 0)
611	quot = 1;
612
613	*baud = (port->uartclk << 2) / quot;
614	}
615
616	static int __init
617	auart_console_setup(struct console co, char options)
618	{
619	struct mxs_auart_port *s;
620	int baud = 9600;
621	int bits = 8;
622	int parity = 'n';
623	int flow = 'n';
624	int ret;
625
626	/*
627	* Check whether an invalid uart number has been specified, and
628	* if so, search for the first available port that does have
629	* console support.
630	*/
631	if (co->index == -1 \|\| co->index >= ARRAY_SIZE(auart_port))
632	co->index = 0;
633	s = auart_port[co->index];
634	if (!s)
635	return -ENODEV;
636
637	clk_enable(s->clk);
638
639	if (options)
640	uart_parse_options(options, &baud, &parity, &bits, &flow);
641	else
642	auart_console_get_options(&s->port, &baud, &parity, &bits);
643
644	ret = uart_set_options(&s->port, co, baud, parity, bits, flow);
645
646	clk_disable(s->clk);
647
648	return ret;
649	}
650
651	static struct console auart_console = {
652	.name = "ttyAPP",
653	.write = auart_console_write,
654	.device = uart_console_device,
655	.setup = auart_console_setup,
656	.flags = CON_PRINTBUFFER,
657	.index = -1,
658	.data = &auart_driver,
659	};
660	#endif
661
662	static struct uart_driver auart_driver = {
663	.owner = THIS_MODULE,
664	.driver_name = "ttyAPP",
665	.dev_name = "ttyAPP",
666	.major = 0,
667	.minor = 0,
668	.nr = MXS_AUART_PORTS,
669	#ifdef CONFIG_SERIAL_MXS_AUART_CONSOLE
670	.cons = &auart_console,
671	#endif
672	};
673
674	static int __devinit mxs_auart_probe(struct platform_device *pdev)
675	{
676	struct mxs_auart_port *s;
677	u32 version;
678	int ret = 0;
679	struct resource *r;
680
681	s = kzalloc(sizeof(struct mxs_auart_port), GFP_KERNEL);
682	if (!s) {
683	ret = -ENOMEM;
684	goto out;
685	}
686
687	s->clk = clk_get(&pdev->dev, NULL);
688	if (IS_ERR(s->clk)) {
689	ret = PTR_ERR(s->clk);
690	goto out_free;
691	}
692
693	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
694	if (!r) {
695	ret = -ENXIO;
696	goto out_free_clk;
697	}
698
699	s->port.mapbase = r->start;
700	s->port.membase = ioremap(r->start, resource_size(r));
701	s->port.ops = &mxs_auart_ops;
702	s->port.iotype = UPIO_MEM;
703	s->port.line = pdev->id < 0 ? 0 : pdev->id;
704	s->port.fifosize = 16;
705	s->port.uartclk = clk_get_rate(s->clk);
706	s->port.type = PORT_IMX;
707	s->port.dev = s->dev = get_device(&pdev->dev);
708
709	s->flags = 0;
710	s->ctrl = 0;
711
712	s->irq = platform_get_irq(pdev, 0);
713	s->port.irq = s->irq;
714	ret = request_irq(s->irq, mxs_auart_irq_handle, 0, dev_name(&pdev->dev), s);
715	if (ret)
716	goto out_free_clk;
717
718	platform_set_drvdata(pdev, s);
719
720	auart_port[pdev->id] = s;
721
722	mxs_auart_reset(&s->port);
723
724	ret = uart_add_one_port(&auart_driver, &s->port);
725	if (ret)
726	goto out_free_irq;
727
728	version = readl(s->port.membase + AUART_VERSION);
729	dev_info(&pdev->dev, "Found APPUART %d.%d.%d\n",
730	(version >> 24) & 0xff,
731	(version >> 16) & 0xff, version & 0xffff);
732
733	return 0;
734
735	out_free_irq:
736	auart_port[pdev->id] = NULL;
737	free_irq(s->irq, s);
738	out_free_clk:
739	clk_put(s->clk);
740	out_free:
741	kfree(s);
742	out:
743	return ret;
744	}
745
746	static int __devexit mxs_auart_remove(struct platform_device *pdev)
747	{
748	struct mxs_auart_port *s = platform_get_drvdata(pdev);
749
750	uart_remove_one_port(&auart_driver, &s->port);
751
752	auart_port[pdev->id] = NULL;
753
754	clk_put(s->clk);
755	free_irq(s->irq, s);
756	kfree(s);
757
758	return 0;
759	}
760
761	static struct platform_driver mxs_auart_driver = {
762	.probe = mxs_auart_probe,
763	.remove = __devexit_p(mxs_auart_remove),
764	.driver = {
765	.name = "mxs-auart",
766	.owner = THIS_MODULE,
767	},
768	};
769
770	static int __init mxs_auart_init(void)
771	{
772	int r;
773
774	r = uart_register_driver(&auart_driver);
775	if (r)
776	goto out;
777
778	r = platform_driver_register(&mxs_auart_driver);
779	if (r)
780	goto out_err;
781
782	return 0;
783	out_err:
784	uart_unregister_driver(&auart_driver);
785	out:
786	return r;
787	}
788
789	static void __exit mxs_auart_exit(void)
790	{
791	platform_driver_unregister(&mxs_auart_driver);
792	uart_unregister_driver(&auart_driver);
793	}
794
795	module_init(mxs_auart_init);
796	module_exit(mxs_auart_exit);
797	MODULE_LICENSE("GPL");
798	MODULE_DESCRIPTION("Freescale MXS application uart driver");