projects / linux-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
tty: remove use of __devexit
[linux-block.git] / drivers / tty / serial / mxs-auart.c
CommitLineData
47d37d6f
SH		 1/*
2 * Freescale STMP37XX/STMP378X Application UART driver
3 *
4 * Author: dmitry pervushin <dimka@embeddedalley.com>
5 *
6 * Copyright 2008-2010 Freescale Semiconductor, Inc.
7 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
8 *
9 * The code contained herein is licensed under the GNU General Public
10 * License. You may obtain a copy of the GNU General Public License
11 * Version 2 or later at the following locations:
12 *
13 * http://www.opensource.org/licenses/gpl-license.html
14 * http://www.gnu.org/copyleft/gpl.html
15 */
16
17#include <linux/kernel.h>
47d37d6f
SH		 18#include <linux/errno.h>
19#include <linux/init.h>
20#include <linux/console.h>
21#include <linux/interrupt.h>
22#include <linux/module.h>
23#include <linux/slab.h>
24#include <linux/wait.h>
25#include <linux/tty.h>
26#include <linux/tty_driver.h>
27#include <linux/tty_flip.h>
28#include <linux/serial.h>
29#include <linux/serial_core.h>
30#include <linux/platform_device.h>
31#include <linux/device.h>
32#include <linux/clk.h>
33#include <linux/delay.h>
34#include <linux/io.h>
2e174c33 35#include <linux/pinctrl/consumer.h>
1ea6607d 36#include <linux/of_device.h>
e8001632
HS		 37#include <linux/dma-mapping.h>
38#include <linux/fsl/mxs-dma.h>
47d37d6f
SH		 39
40#include <asm/cacheflush.h>
41
42#define MXS_AUART_PORTS 5
43
44#define AUART_CTRL0 0x00000000
45#define AUART_CTRL0_SET 0x00000004
46#define AUART_CTRL0_CLR 0x00000008
47#define AUART_CTRL0_TOG 0x0000000c
48#define AUART_CTRL1 0x00000010
49#define AUART_CTRL1_SET 0x00000014
50#define AUART_CTRL1_CLR 0x00000018
51#define AUART_CTRL1_TOG 0x0000001c
52#define AUART_CTRL2 0x00000020
53#define AUART_CTRL2_SET 0x00000024
54#define AUART_CTRL2_CLR 0x00000028
55#define AUART_CTRL2_TOG 0x0000002c
56#define AUART_LINECTRL 0x00000030
57#define AUART_LINECTRL_SET 0x00000034
58#define AUART_LINECTRL_CLR 0x00000038
59#define AUART_LINECTRL_TOG 0x0000003c
60#define AUART_LINECTRL2 0x00000040
61#define AUART_LINECTRL2_SET 0x00000044
62#define AUART_LINECTRL2_CLR 0x00000048
63#define AUART_LINECTRL2_TOG 0x0000004c
64#define AUART_INTR 0x00000050
65#define AUART_INTR_SET 0x00000054
66#define AUART_INTR_CLR 0x00000058
67#define AUART_INTR_TOG 0x0000005c
68#define AUART_DATA 0x00000060
69#define AUART_STAT 0x00000070
70#define AUART_DEBUG 0x00000080
71#define AUART_VERSION 0x00000090
72#define AUART_AUTOBAUD 0x000000a0
73
74#define AUART_CTRL0_SFTRST (1 << 31)
75#define AUART_CTRL0_CLKGATE (1 << 30)
e8001632
HS		 76#define AUART_CTRL0_RXTO_ENABLE (1 << 27)
77#define AUART_CTRL0_RXTIMEOUT(v) (((v) & 0x7ff) << 16)
78#define AUART_CTRL0_XFER_COUNT(v) ((v) & 0xffff)
79
80#define AUART_CTRL1_XFER_COUNT(v) ((v) & 0xffff)
81
82#define AUART_CTRL2_DMAONERR (1 << 26)
83#define AUART_CTRL2_TXDMAE (1 << 25)
84#define AUART_CTRL2_RXDMAE (1 << 24)
47d37d6f
SH		 85
86#define AUART_CTRL2_CTSEN (1 << 15)
00592021 87#define AUART_CTRL2_RTSEN (1 << 14)
47d37d6f
SH		 88#define AUART_CTRL2_RTS (1 << 11)
89#define AUART_CTRL2_RXE (1 << 9)
90#define AUART_CTRL2_TXE (1 << 8)
91#define AUART_CTRL2_UARTEN (1 << 0)
92
93#define AUART_LINECTRL_BAUD_DIVINT_SHIFT 16
94#define AUART_LINECTRL_BAUD_DIVINT_MASK 0xffff0000
95#define AUART_LINECTRL_BAUD_DIVINT(v) (((v) & 0xffff) << 16)
96#define AUART_LINECTRL_BAUD_DIVFRAC_SHIFT 8
97#define AUART_LINECTRL_BAUD_DIVFRAC_MASK 0x00003f00
98#define AUART_LINECTRL_BAUD_DIVFRAC(v) (((v) & 0x3f) << 8)
99#define AUART_LINECTRL_WLEN_MASK 0x00000060
100#define AUART_LINECTRL_WLEN(v) (((v) & 0x3) << 5)
101#define AUART_LINECTRL_FEN (1 << 4)
102#define AUART_LINECTRL_STP2 (1 << 3)
103#define AUART_LINECTRL_EPS (1 << 2)
104#define AUART_LINECTRL_PEN (1 << 1)
105#define AUART_LINECTRL_BRK (1 << 0)
106
107#define AUART_INTR_RTIEN (1 << 22)
108#define AUART_INTR_TXIEN (1 << 21)
109#define AUART_INTR_RXIEN (1 << 20)
110#define AUART_INTR_CTSMIEN (1 << 17)
111#define AUART_INTR_RTIS (1 << 6)
112#define AUART_INTR_TXIS (1 << 5)
113#define AUART_INTR_RXIS (1 << 4)
114#define AUART_INTR_CTSMIS (1 << 1)
115
116#define AUART_STAT_BUSY (1 << 29)
117#define AUART_STAT_CTS (1 << 28)
118#define AUART_STAT_TXFE (1 << 27)
119#define AUART_STAT_TXFF (1 << 25)
120#define AUART_STAT_RXFE (1 << 24)
121#define AUART_STAT_OERR (1 << 19)
122#define AUART_STAT_BERR (1 << 18)
123#define AUART_STAT_PERR (1 << 17)
124#define AUART_STAT_FERR (1 << 16)
e8001632 125#define AUART_STAT_RXCOUNT_MASK 0xffff
47d37d6f
SH		 126
127static struct uart_driver auart_driver;
128
f4b1f03b
HS		 129enum mxs_auart_type {
130 IMX23_AUART,
131 IMX28_AUART,
132};
133
47d37d6f
SH		 134struct mxs_auart_port {
135 struct uart_port port;
136
e8001632
HS		 137#define MXS_AUART_DMA_CONFIG 0x1
138#define MXS_AUART_DMA_ENABLED 0x2
139#define MXS_AUART_DMA_TX_SYNC 2 /* bit 2 */
140#define MXS_AUART_DMA_RX_READY 3 /* bit 3 */
141 unsigned long flags;
47d37d6f 142 unsigned int ctrl;
f4b1f03b 143 enum mxs_auart_type devtype;
47d37d6f
SH		 144
145 unsigned int irq;
146
147 struct clk *clk;
148 struct device *dev;
e8001632
HS		 149
150 /* for DMA */
151 struct mxs_dma_data dma_data;
152 int dma_channel_rx, dma_channel_tx;
153 int dma_irq_rx, dma_irq_tx;
154 int dma_channel;
155
156 struct scatterlist tx_sgl;
157 struct dma_chan *tx_dma_chan;
158 void *tx_dma_buf;
159
160 struct scatterlist rx_sgl;
161 struct dma_chan *rx_dma_chan;
162 void *rx_dma_buf;
47d37d6f
SH		 163};
164
f4b1f03b
HS		 165static struct platform_device_id mxs_auart_devtype[] = {
166 { .name = "mxs-auart-imx23", .driver_data = IMX23_AUART },
167 { .name = "mxs-auart-imx28", .driver_data = IMX28_AUART },
168 { /* sentinel */ }
169};
170MODULE_DEVICE_TABLE(platform, mxs_auart_devtype);
171
172static struct of_device_id mxs_auart_dt_ids[] = {
173 {
174 .compatible = "fsl,imx28-auart",
175 .data = &mxs_auart_devtype[IMX28_AUART]
176 }, {
177 .compatible = "fsl,imx23-auart",
178 .data = &mxs_auart_devtype[IMX23_AUART]
179 }, { /* sentinel */ }
180};
181MODULE_DEVICE_TABLE(of, mxs_auart_dt_ids);
182
183static inline int is_imx28_auart(struct mxs_auart_port *s)
184{
185 return s->devtype == IMX28_AUART;
186}
187
e8001632
HS		 188static inline bool auart_dma_enabled(struct mxs_auart_port *s)
189{
190 return s->flags & MXS_AUART_DMA_ENABLED;
191}
192
47d37d6f
SH		 193static void mxs_auart_stop_tx(struct uart_port *u);
194
195#define to_auart_port(u) container_of(u, struct mxs_auart_port, port)
196
e8001632
HS		 197static void mxs_auart_tx_chars(struct mxs_auart_port *s);
198
199static void dma_tx_callback(void *param)
47d37d6f 200{
e8001632 201 struct mxs_auart_port *s = param;
47d37d6f
SH		 202 struct circ_buf *xmit = &s->port.state->xmit;
203
e8001632
HS		 204 dma_unmap_sg(s->dev, &s->tx_sgl, 1, DMA_TO_DEVICE);
205
206 /* clear the bit used to serialize the DMA tx. */
207 clear_bit(MXS_AUART_DMA_TX_SYNC, &s->flags);
208 smp_mb__after_clear_bit();
209
210 /* wake up the possible processes. */
211 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
212 uart_write_wakeup(&s->port);
213
214 mxs_auart_tx_chars(s);
215}
216
217static int mxs_auart_dma_tx(struct mxs_auart_port *s, int size)
218{
219 struct dma_async_tx_descriptor *desc;
220 struct scatterlist *sgl = &s->tx_sgl;
221 struct dma_chan *channel = s->tx_dma_chan;
222 u32 pio;
223
224 /* [1] : send PIO. Note, the first pio word is CTRL1. */
225 pio = AUART_CTRL1_XFER_COUNT(size);
226 desc = dmaengine_prep_slave_sg(channel, (struct scatterlist *)&pio,
227 1, DMA_TRANS_NONE, 0);
228 if (!desc) {
229 dev_err(s->dev, "step 1 error\n");
230 return -EINVAL;
231 }
232
233 /* [2] : set DMA buffer. */
234 sg_init_one(sgl, s->tx_dma_buf, size);
235 dma_map_sg(s->dev, sgl, 1, DMA_TO_DEVICE);
236 desc = dmaengine_prep_slave_sg(channel, sgl,
237 1, DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
238 if (!desc) {
239 dev_err(s->dev, "step 2 error\n");
240 return -EINVAL;
241 }
242
243 /* [3] : submit the DMA */
244 desc->callback = dma_tx_callback;
245 desc->callback_param = s;
246 dmaengine_submit(desc);
247 dma_async_issue_pending(channel);
248 return 0;
249}
250
251static void mxs_auart_tx_chars(struct mxs_auart_port *s)
252{
253 struct circ_buf *xmit = &s->port.state->xmit;
254
255 if (auart_dma_enabled(s)) {
256 int i = 0;
257 int size;
258 void *buffer = s->tx_dma_buf;
259
260 if (test_and_set_bit(MXS_AUART_DMA_TX_SYNC, &s->flags))
261 return;
262
263 while (!uart_circ_empty(xmit) && !uart_tx_stopped(&s->port)) {
264 size = min_t(u32, UART_XMIT_SIZE - i,
265 CIRC_CNT_TO_END(xmit->head,
266 xmit->tail,
267 UART_XMIT_SIZE));
268 memcpy(buffer + i, xmit->buf + xmit->tail, size);
269 xmit->tail = (xmit->tail + size) & (UART_XMIT_SIZE - 1);
270
271 i += size;
272 if (i >= UART_XMIT_SIZE)
273 break;
274 }
275
276 if (uart_tx_stopped(&s->port))
277 mxs_auart_stop_tx(&s->port);
278
279 if (i) {
280 mxs_auart_dma_tx(s, i);
281 } else {
282 clear_bit(MXS_AUART_DMA_TX_SYNC, &s->flags);
283 smp_mb__after_clear_bit();
284 }
285 return;
286 }
287
288
47d37d6f
SH		 289 while (!(readl(s->port.membase + AUART_STAT) &
290 AUART_STAT_TXFF)) {
291 if (s->port.x_char) {
292 s->port.icount.tx++;
293 writel(s->port.x_char,
294 s->port.membase + AUART_DATA);
295 s->port.x_char = 0;
296 continue;
297 }
298 if (!uart_circ_empty(xmit) && !uart_tx_stopped(&s->port)) {
299 s->port.icount.tx++;
300 writel(xmit->buf[xmit->tail],
301 s->port.membase + AUART_DATA);
302 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
47d37d6f
SH		 303 } else
304 break;
305 }
d0758a28
UKK		 306 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
307 uart_write_wakeup(&s->port);
308
47d37d6f
SH		 309 if (uart_circ_empty(&(s->port.state->xmit)))
310 writel(AUART_INTR_TXIEN,
311 s->port.membase + AUART_INTR_CLR);
312 else
313 writel(AUART_INTR_TXIEN,
314 s->port.membase + AUART_INTR_SET);
315
316 if (uart_tx_stopped(&s->port))
317 mxs_auart_stop_tx(&s->port);
318}
319
320static void mxs_auart_rx_char(struct mxs_auart_port *s)
321{
322 int flag;
323 u32 stat;
324 u8 c;
325
326 c = readl(s->port.membase + AUART_DATA);
327 stat = readl(s->port.membase + AUART_STAT);
328
329 flag = TTY_NORMAL;
330 s->port.icount.rx++;
331
332 if (stat & AUART_STAT_BERR) {
333 s->port.icount.brk++;
334 if (uart_handle_break(&s->port))
335 goto out;
336 } else if (stat & AUART_STAT_PERR) {
337 s->port.icount.parity++;
338 } else if (stat & AUART_STAT_FERR) {
339 s->port.icount.frame++;
340 }
341
342 /*
343 * Mask off conditions which should be ingored.
344 */
345 stat &= s->port.read_status_mask;
346
347 if (stat & AUART_STAT_BERR) {
348 flag = TTY_BREAK;
349 } else if (stat & AUART_STAT_PERR)
350 flag = TTY_PARITY;
351 else if (stat & AUART_STAT_FERR)
352 flag = TTY_FRAME;
353
354 if (stat & AUART_STAT_OERR)
355 s->port.icount.overrun++;
356
357 if (uart_handle_sysrq_char(&s->port, c))
358 goto out;
359
360 uart_insert_char(&s->port, stat, AUART_STAT_OERR, c, flag);
361out:
362 writel(stat, s->port.membase + AUART_STAT);
363}
364
365static void mxs_auart_rx_chars(struct mxs_auart_port *s)
366{
367 struct tty_struct *tty = s->port.state->port.tty;
368 u32 stat = 0;
369
370 for (;;) {
371 stat = readl(s->port.membase + AUART_STAT);
372 if (stat & AUART_STAT_RXFE)
373 break;
374 mxs_auart_rx_char(s);
375 }
376
377 writel(stat, s->port.membase + AUART_STAT);
378 tty_flip_buffer_push(tty);
379}
380
381static int mxs_auart_request_port(struct uart_port *u)
382{
383 return 0;
384}
385
386static int mxs_auart_verify_port(struct uart_port *u,
387 struct serial_struct *ser)
388{
389 if (u->type != PORT_UNKNOWN && u->type != PORT_IMX)
390 return -EINVAL;
391 return 0;
392}
393
394static void mxs_auart_config_port(struct uart_port *u, int flags)
395{
396}
397
398static const char *mxs_auart_type(struct uart_port *u)
399{
400 struct mxs_auart_port *s = to_auart_port(u);
401
402 return dev_name(s->dev);
403}
404
405static void mxs_auart_release_port(struct uart_port *u)
406{
407}
408
409static void mxs_auart_set_mctrl(struct uart_port *u, unsigned mctrl)
410{
411 struct mxs_auart_port *s = to_auart_port(u);
412
413 u32 ctrl = readl(u->membase + AUART_CTRL2);
414
00592021
HS		 415 ctrl &= ~AUART_CTRL2_RTSEN;
416 if (mctrl & TIOCM_RTS) {
f21ec3d2 417 if (tty_port_cts_enabled(&u->state->port))
00592021
HS		 418 ctrl |= AUART_CTRL2_RTSEN;
419 }
420
47d37d6f
SH		 421 s->ctrl = mctrl;
422 writel(ctrl, u->membase + AUART_CTRL2);
423}
424
425static u32 mxs_auart_get_mctrl(struct uart_port *u)
426{
427 struct mxs_auart_port *s = to_auart_port(u);
428 u32 stat = readl(u->membase + AUART_STAT);
429 int ctrl2 = readl(u->membase + AUART_CTRL2);
430 u32 mctrl = s->ctrl;
431
432 mctrl &= ~TIOCM_CTS;
433 if (stat & AUART_STAT_CTS)
434 mctrl |= TIOCM_CTS;
435
436 if (ctrl2 & AUART_CTRL2_RTS)
437 mctrl |= TIOCM_RTS;
438
439 return mctrl;
440}
441
e8001632
HS		 442static bool mxs_auart_dma_filter(struct dma_chan *chan, void *param)
443{
444 struct mxs_auart_port *s = param;
445
446 if (!mxs_dma_is_apbx(chan))
447 return false;
448
449 if (s->dma_channel == chan->chan_id) {
450 chan->private = &s->dma_data;
451 return true;
452 }
453 return false;
454}
455
456static int mxs_auart_dma_prep_rx(struct mxs_auart_port *s);
457static void dma_rx_callback(void *arg)
458{
459 struct mxs_auart_port *s = (struct mxs_auart_port *) arg;
460 struct tty_struct *tty = s->port.state->port.tty;
461 int count;
462 u32 stat;
463
464 stat = readl(s->port.membase + AUART_STAT);
465 stat &= ~(AUART_STAT_OERR | AUART_STAT_BERR |
466 AUART_STAT_PERR | AUART_STAT_FERR);
467
468 count = stat & AUART_STAT_RXCOUNT_MASK;
469 tty_insert_flip_string(tty, s->rx_dma_buf, count);
470
471 writel(stat, s->port.membase + AUART_STAT);
472 tty_flip_buffer_push(tty);
473
474 /* start the next DMA for RX. */
475 mxs_auart_dma_prep_rx(s);
476}
477
478static int mxs_auart_dma_prep_rx(struct mxs_auart_port *s)
479{
480 struct dma_async_tx_descriptor *desc;
481 struct scatterlist *sgl = &s->rx_sgl;
482 struct dma_chan *channel = s->rx_dma_chan;
483 u32 pio[1];
484
485 /* [1] : send PIO */
486 pio[0] = AUART_CTRL0_RXTO_ENABLE
487 | AUART_CTRL0_RXTIMEOUT(0x80)
488 | AUART_CTRL0_XFER_COUNT(UART_XMIT_SIZE);
489 desc = dmaengine_prep_slave_sg(channel, (struct scatterlist *)pio,
490 1, DMA_TRANS_NONE, 0);
491 if (!desc) {
492 dev_err(s->dev, "step 1 error\n");
493 return -EINVAL;
494 }
495
496 /* [2] : send DMA request */
497 sg_init_one(sgl, s->rx_dma_buf, UART_XMIT_SIZE);
498 dma_map_sg(s->dev, sgl, 1, DMA_FROM_DEVICE);
499 desc = dmaengine_prep_slave_sg(channel, sgl, 1, DMA_DEV_TO_MEM,
500 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
501 if (!desc) {
502 dev_err(s->dev, "step 2 error\n");
503 return -1;
504 }
505
506 /* [3] : submit the DMA, but do not issue it. */
507 desc->callback = dma_rx_callback;
508 desc->callback_param = s;
509 dmaengine_submit(desc);
510 dma_async_issue_pending(channel);
511 return 0;
512}
513
514static void mxs_auart_dma_exit_channel(struct mxs_auart_port *s)
515{
516 if (s->tx_dma_chan) {
517 dma_release_channel(s->tx_dma_chan);
518 s->tx_dma_chan = NULL;
519 }
520 if (s->rx_dma_chan) {
521 dma_release_channel(s->rx_dma_chan);
522 s->rx_dma_chan = NULL;
523 }
524
525 kfree(s->tx_dma_buf);
526 kfree(s->rx_dma_buf);
527 s->tx_dma_buf = NULL;
528 s->rx_dma_buf = NULL;
529}
530
531static void mxs_auart_dma_exit(struct mxs_auart_port *s)
532{
533
534 writel(AUART_CTRL2_TXDMAE | AUART_CTRL2_RXDMAE | AUART_CTRL2_DMAONERR,
535 s->port.membase + AUART_CTRL2_CLR);
536
537 mxs_auart_dma_exit_channel(s);
538 s->flags &= ~MXS_AUART_DMA_ENABLED;
539 clear_bit(MXS_AUART_DMA_TX_SYNC, &s->flags);
540 clear_bit(MXS_AUART_DMA_RX_READY, &s->flags);
541}
542
543static int mxs_auart_dma_init(struct mxs_auart_port *s)
544{
545 dma_cap_mask_t mask;
546
547 if (auart_dma_enabled(s))
548 return 0;
549
550 /* We do not get the right DMA channels. */
551 if (s->dma_channel_rx == -1 || s->dma_channel_rx == -1)
552 return -EINVAL;
553
554 /* init for RX */
555 dma_cap_zero(mask);
556 dma_cap_set(DMA_SLAVE, mask);
557 s->dma_channel = s->dma_channel_rx;
558 s->dma_data.chan_irq = s->dma_irq_rx;
559 s->rx_dma_chan = dma_request_channel(mask, mxs_auart_dma_filter, s);
560 if (!s->rx_dma_chan)
561 goto err_out;
562 s->rx_dma_buf = kzalloc(UART_XMIT_SIZE, GFP_KERNEL | GFP_DMA);
563 if (!s->rx_dma_buf)
564 goto err_out;
565
566 /* init for TX */
567 s->dma_channel = s->dma_channel_tx;
568 s->dma_data.chan_irq = s->dma_irq_tx;
569 s->tx_dma_chan = dma_request_channel(mask, mxs_auart_dma_filter, s);
570 if (!s->tx_dma_chan)
571 goto err_out;
572 s->tx_dma_buf = kzalloc(UART_XMIT_SIZE, GFP_KERNEL | GFP_DMA);
573 if (!s->tx_dma_buf)
574 goto err_out;
575
576 /* set the flags */
577 s->flags |= MXS_AUART_DMA_ENABLED;
578 dev_dbg(s->dev, "enabled the DMA support.");
579
580 return 0;
581
582err_out:
583 mxs_auart_dma_exit_channel(s);
584 return -EINVAL;
585
586}
587
47d37d6f
SH		 588static void mxs_auart_settermios(struct uart_port *u,
589 struct ktermios *termios,
590 struct ktermios *old)
591{
e8001632 592 struct mxs_auart_port *s = to_auart_port(u);
47d37d6f
SH		 593 u32 bm, ctrl, ctrl2, div;
594 unsigned int cflag, baud;
595
596 cflag = termios->c_cflag;
597
598 ctrl = AUART_LINECTRL_FEN;
599 ctrl2 = readl(u->membase + AUART_CTRL2);
600
601 /* byte size */
602 switch (cflag & CSIZE) {
603 case CS5:
604 bm = 0;
605 break;
606 case CS6:
607 bm = 1;
608 break;
609 case CS7:
610 bm = 2;
611 break;
612 case CS8:
613 bm = 3;
614 break;
615 default:
616 return;
617 }
618
619 ctrl |= AUART_LINECTRL_WLEN(bm);
620
621 /* parity */
622 if (cflag & PARENB) {
623 ctrl |= AUART_LINECTRL_PEN;
624 if ((cflag & PARODD) == 0)
625 ctrl |= AUART_LINECTRL_EPS;
626 }
627
628 u->read_status_mask = 0;
629
630 if (termios->c_iflag & INPCK)
631 u->read_status_mask |= AUART_STAT_PERR;
632 if (termios->c_iflag & (BRKINT | PARMRK))
633 u->read_status_mask |= AUART_STAT_BERR;
634
635 /*
636 * Characters to ignore
637 */
638 u->ignore_status_mask = 0;
639 if (termios->c_iflag & IGNPAR)
640 u->ignore_status_mask |= AUART_STAT_PERR;
641 if (termios->c_iflag & IGNBRK) {
642 u->ignore_status_mask |= AUART_STAT_BERR;
643 /*
644 * If we're ignoring parity and break indicators,
645 * ignore overruns too (for real raw support).
646 */
647 if (termios->c_iflag & IGNPAR)
648 u->ignore_status_mask |= AUART_STAT_OERR;
649 }
650
651 /*
652 * ignore all characters if CREAD is not set
653 */
654 if (cflag & CREAD)
655 ctrl2 |= AUART_CTRL2_RXE;
656 else
657 ctrl2 &= ~AUART_CTRL2_RXE;
658
659 /* figure out the stop bits requested */
660 if (cflag & CSTOPB)
661 ctrl |= AUART_LINECTRL_STP2;
662
663 /* figure out the hardware flow control settings */
e8001632
HS		 664 if (cflag & CRTSCTS) {
665 /*
666 * The DMA has a bug(see errata:2836) in mx23.
667 * So we can not implement the DMA for auart in mx23,
668 * we can only implement the DMA support for auart
669 * in mx28.
670 */
671 if (is_imx28_auart(s) && (s->flags & MXS_AUART_DMA_CONFIG)) {
672 if (!mxs_auart_dma_init(s))
673 /* enable DMA tranfer */
674 ctrl2 |= AUART_CTRL2_TXDMAE | AUART_CTRL2_RXDMAE
675 | AUART_CTRL2_DMAONERR;
676 }
00592021 677 ctrl2 |= AUART_CTRL2_CTSEN | AUART_CTRL2_RTSEN;
e8001632 678 } else {
00592021 679 ctrl2 &= ~(AUART_CTRL2_CTSEN | AUART_CTRL2_RTSEN);
e8001632 680 }
47d37d6f
SH		 681
682 /* set baud rate */
683 baud = uart_get_baud_rate(u, termios, old, 0, u->uartclk);
684 div = u->uartclk * 32 / baud;
685 ctrl |= AUART_LINECTRL_BAUD_DIVFRAC(div & 0x3F);
686 ctrl |= AUART_LINECTRL_BAUD_DIVINT(div >> 6);
687
688 writel(ctrl, u->membase + AUART_LINECTRL);
689 writel(ctrl2, u->membase + AUART_CTRL2);
8b979f7c
LW		 690
691 uart_update_timeout(u, termios->c_cflag, baud);
e8001632
HS		 692
693 /* prepare for the DMA RX. */
694 if (auart_dma_enabled(s) &&
695 !test_and_set_bit(MXS_AUART_DMA_RX_READY, &s->flags)) {
696 if (!mxs_auart_dma_prep_rx(s)) {
697 /* Disable the normal RX interrupt. */
698 writel(AUART_INTR_RXIEN, u->membase + AUART_INTR_CLR);
699 } else {
700 mxs_auart_dma_exit(s);
701 dev_err(s->dev, "We can not start up the DMA.\n");
702 }
703 }
47d37d6f
SH		 704}
705
706static irqreturn_t mxs_auart_irq_handle(int irq, void *context)
707{
708 u32 istatus, istat;
709 struct mxs_auart_port *s = context;
710 u32 stat = readl(s->port.membase + AUART_STAT);
711
712 istatus = istat = readl(s->port.membase + AUART_INTR);
713
714 if (istat & AUART_INTR_CTSMIS) {
715 uart_handle_cts_change(&s->port, stat & AUART_STAT_CTS);
716 writel(AUART_INTR_CTSMIS,
717 s->port.membase + AUART_INTR_CLR);
718 istat &= ~AUART_INTR_CTSMIS;
719 }
720
721 if (istat & (AUART_INTR_RTIS | AUART_INTR_RXIS)) {
722 mxs_auart_rx_chars(s);
723 istat &= ~(AUART_INTR_RTIS | AUART_INTR_RXIS);
724 }
725
726 if (istat & AUART_INTR_TXIS) {
727 mxs_auart_tx_chars(s);
728 istat &= ~AUART_INTR_TXIS;
729 }
730
731 writel(istatus & (AUART_INTR_RTIS
732 | AUART_INTR_TXIS
733 | AUART_INTR_RXIS
734 | AUART_INTR_CTSMIS),
735 s->port.membase + AUART_INTR_CLR);
736
737 return IRQ_HANDLED;
738}
739
740static void mxs_auart_reset(struct uart_port *u)
741{
742 int i;
743 unsigned int reg;
744
745 writel(AUART_CTRL0_SFTRST, u->membase + AUART_CTRL0_CLR);
746
747 for (i = 0; i < 10000; i++) {
748 reg = readl(u->membase + AUART_CTRL0);
749 if (!(reg & AUART_CTRL0_SFTRST))
750 break;
751 udelay(3);
752 }
753 writel(AUART_CTRL0_CLKGATE, u->membase + AUART_CTRL0_CLR);
754}
755
756static int mxs_auart_startup(struct uart_port *u)
757{
758 struct mxs_auart_port *s = to_auart_port(u);
759
a4813770 760 clk_prepare_enable(s->clk);
47d37d6f
SH		 761
762 writel(AUART_CTRL0_CLKGATE, u->membase + AUART_CTRL0_CLR);
763
764 writel(AUART_CTRL2_UARTEN, u->membase + AUART_CTRL2_SET);
765
766 writel(AUART_INTR_RXIEN | AUART_INTR_RTIEN | AUART_INTR_CTSMIEN,
767 u->membase + AUART_INTR);
768
769 /*
770 * Enable fifo so all four bytes of a DMA word are written to
771 * output (otherwise, only the LSB is written, ie. 1 in 4 bytes)
772 */
773 writel(AUART_LINECTRL_FEN, u->membase + AUART_LINECTRL_SET);
774
775 return 0;
776}
777
778static void mxs_auart_shutdown(struct uart_port *u)
779{
780 struct mxs_auart_port *s = to_auart_port(u);
781
e8001632
HS		 782 if (auart_dma_enabled(s))
783 mxs_auart_dma_exit(s);
784
47d37d6f
SH		 785 writel(AUART_CTRL2_UARTEN, u->membase + AUART_CTRL2_CLR);
786
47d37d6f
SH		 787 writel(AUART_INTR_RXIEN | AUART_INTR_RTIEN | AUART_INTR_CTSMIEN,
788 u->membase + AUART_INTR_CLR);
789
851b714b
HS		 790 writel(AUART_CTRL0_CLKGATE, u->membase + AUART_CTRL0_SET);
791
a4813770 792 clk_disable_unprepare(s->clk);
47d37d6f
SH		 793}
794
795static unsigned int mxs_auart_tx_empty(struct uart_port *u)
796{
797 if (readl(u->membase + AUART_STAT) & AUART_STAT_TXFE)
798 return TIOCSER_TEMT;
799 else
800 return 0;
801}
802
803static void mxs_auart_start_tx(struct uart_port *u)
804{
805 struct mxs_auart_port *s = to_auart_port(u);
806
807 /* enable transmitter */
808 writel(AUART_CTRL2_TXE, u->membase + AUART_CTRL2_SET);
809
810 mxs_auart_tx_chars(s);
811}
812
813static void mxs_auart_stop_tx(struct uart_port *u)
814{
815 writel(AUART_CTRL2_TXE, u->membase + AUART_CTRL2_CLR);
816}
817
818static void mxs_auart_stop_rx(struct uart_port *u)
819{
820 writel(AUART_CTRL2_RXE, u->membase + AUART_CTRL2_CLR);
821}
822
823static void mxs_auart_break_ctl(struct uart_port *u, int ctl)
824{
825 if (ctl)
826 writel(AUART_LINECTRL_BRK,
827 u->membase + AUART_LINECTRL_SET);
828 else
829 writel(AUART_LINECTRL_BRK,
830 u->membase + AUART_LINECTRL_CLR);
831}
832
833static void mxs_auart_enable_ms(struct uart_port *port)
834{
835 /* just empty */
836}
837
838static struct uart_ops mxs_auart_ops = {
839 .tx_empty = mxs_auart_tx_empty,
840 .start_tx = mxs_auart_start_tx,
841 .stop_tx = mxs_auart_stop_tx,
842 .stop_rx = mxs_auart_stop_rx,
843 .enable_ms = mxs_auart_enable_ms,
844 .break_ctl = mxs_auart_break_ctl,
845 .set_mctrl = mxs_auart_set_mctrl,
846 .get_mctrl = mxs_auart_get_mctrl,
847 .startup = mxs_auart_startup,
848 .shutdown = mxs_auart_shutdown,
849 .set_termios = mxs_auart_settermios,
850 .type = mxs_auart_type,
851 .release_port = mxs_auart_release_port,
852 .request_port = mxs_auart_request_port,
853 .config_port = mxs_auart_config_port,
854 .verify_port = mxs_auart_verify_port,
855};
856
857static struct mxs_auart_port *auart_port[MXS_AUART_PORTS];
858
859#ifdef CONFIG_SERIAL_MXS_AUART_CONSOLE
860static void mxs_auart_console_putchar(struct uart_port *port, int ch)
861{
862 unsigned int to = 1000;
863
864 while (readl(port->membase + AUART_STAT) & AUART_STAT_TXFF) {
865 if (!to--)
866 break;
867 udelay(1);
868 }
869
870 writel(ch, port->membase + AUART_DATA);
871}
872
873static void
874auart_console_write(struct console *co, const char *str, unsigned int count)
875{
876 struct mxs_auart_port *s;
877 struct uart_port *port;
878 unsigned int old_ctrl0, old_ctrl2;
879 unsigned int to = 1000;
880
881 if (co->index > MXS_AUART_PORTS || co->index < 0)
882 return;
883
884 s = auart_port[co->index];
885 port = &s->port;
886
887 clk_enable(s->clk);
888
889 /* First save the CR then disable the interrupts */
890 old_ctrl2 = readl(port->membase + AUART_CTRL2);
891 old_ctrl0 = readl(port->membase + AUART_CTRL0);
892
893 writel(AUART_CTRL0_CLKGATE,
894 port->membase + AUART_CTRL0_CLR);
895 writel(AUART_CTRL2_UARTEN | AUART_CTRL2_TXE,
896 port->membase + AUART_CTRL2_SET);
897
898 uart_console_write(port, str, count, mxs_auart_console_putchar);
899
900 /*
901 * Finally, wait for transmitter to become empty
902 * and restore the TCR
903 */
904 while (readl(port->membase + AUART_STAT) & AUART_STAT_BUSY) {
905 if (!to--)
906 break;
907 udelay(1);
908 }
909
910 writel(old_ctrl0, port->membase + AUART_CTRL0);
911 writel(old_ctrl2, port->membase + AUART_CTRL2);
912
913 clk_disable(s->clk);
914}
915
916static void __init
917auart_console_get_options(struct uart_port *port, int *baud,
918 int *parity, int *bits)
919{
920 unsigned int lcr_h, quot;
921
922 if (!(readl(port->membase + AUART_CTRL2) & AUART_CTRL2_UARTEN))
923 return;
924
925 lcr_h = readl(port->membase + AUART_LINECTRL);
926
927 *parity = 'n';
928 if (lcr_h & AUART_LINECTRL_PEN) {
929 if (lcr_h & AUART_LINECTRL_EPS)
930 *parity = 'e';
931 else
932 *parity = 'o';
933 }
934
935 if ((lcr_h & AUART_LINECTRL_WLEN_MASK) == AUART_LINECTRL_WLEN(2))
936 *bits = 7;
937 else
938 *bits = 8;
939
940 quot = ((readl(port->membase + AUART_LINECTRL)
941 & AUART_LINECTRL_BAUD_DIVINT_MASK))
942 >> (AUART_LINECTRL_BAUD_DIVINT_SHIFT - 6);
943 quot |= ((readl(port->membase + AUART_LINECTRL)
944 & AUART_LINECTRL_BAUD_DIVFRAC_MASK))
945 >> AUART_LINECTRL_BAUD_DIVFRAC_SHIFT;
946 if (quot == 0)
947 quot = 1;
948
949 *baud = (port->uartclk << 2) / quot;
950}
951
952static int __init
953auart_console_setup(struct console *co, char *options)
954{
955 struct mxs_auart_port *s;
956 int baud = 9600;
957 int bits = 8;
958 int parity = 'n';
959 int flow = 'n';
960 int ret;
961
962 /*
963 * Check whether an invalid uart number has been specified, and
964 * if so, search for the first available port that does have
965 * console support.
966 */
967 if (co->index == -1 || co->index >= ARRAY_SIZE(auart_port))
968 co->index = 0;
969 s = auart_port[co->index];
970 if (!s)
971 return -ENODEV;
972
a4813770 973 clk_prepare_enable(s->clk);
47d37d6f
SH		 974
975 if (options)
976 uart_parse_options(options, &baud, &parity, &bits, &flow);
977 else
978 auart_console_get_options(&s->port, &baud, &parity, &bits);
979
980 ret = uart_set_options(&s->port, co, baud, parity, bits, flow);
981
a4813770 982 clk_disable_unprepare(s->clk);
47d37d6f
SH		 983
984 return ret;
985}
986
987static struct console auart_console = {
988 .name = "ttyAPP",
989 .write = auart_console_write,
990 .device = uart_console_device,
991 .setup = auart_console_setup,
992 .flags = CON_PRINTBUFFER,
993 .index = -1,
994 .data = &auart_driver,
995};
996#endif
997
998static struct uart_driver auart_driver = {
999 .owner = THIS_MODULE,
1000 .driver_name = "ttyAPP",
1001 .dev_name = "ttyAPP",
1002 .major = 0,
1003 .minor = 0,
1004 .nr = MXS_AUART_PORTS,
1005#ifdef CONFIG_SERIAL_MXS_AUART_CONSOLE
1006 .cons = &auart_console,
1007#endif
1008};
1009
1ea6607d
FE		 1010/*
1011 * This function returns 1 if pdev isn't a device instatiated by dt, 0 if it
1012 * could successfully get all information from dt or a negative errno.
1013 */
1014static int serial_mxs_probe_dt(struct mxs_auart_port *s,
1015 struct platform_device *pdev)
1016{
1017 struct device_node *np = pdev->dev.of_node;
e8001632 1018 u32 dma_channel[2];
1ea6607d
FE		 1019 int ret;
1020
1021 if (!np)
1022 /* no device tree device */
1023 return 1;
1024
1025 ret = of_alias_get_id(np, "serial");
1026 if (ret < 0) {
1027 dev_err(&pdev->dev, "failed to get alias id: %d\n", ret);
1028 return ret;
1029 }
1030 s->port.line = ret;
1031
e8001632
HS		 1032 s->dma_irq_rx = platform_get_irq(pdev, 1);
1033 s->dma_irq_tx = platform_get_irq(pdev, 2);
1034
1035 ret = of_property_read_u32_array(np, "fsl,auart-dma-channel",
1036 dma_channel, 2);
1037 if (ret == 0) {
1038 s->dma_channel_rx = dma_channel[0];
1039 s->dma_channel_tx = dma_channel[1];
1040
1041 s->flags |= MXS_AUART_DMA_CONFIG;
1042 } else {
1043 s->dma_channel_rx = -1;
1044 s->dma_channel_tx = -1;
1045 }
1ea6607d
FE		 1046 return 0;
1047}
1048
9671f099 1049static int mxs_auart_probe(struct platform_device *pdev)
47d37d6f 1050{
f4b1f03b
HS		 1051 const struct of_device_id *of_id =
1052 of_match_device(mxs_auart_dt_ids, &pdev->dev);
47d37d6f
SH		 1053 struct mxs_auart_port *s;
1054 u32 version;
1055 int ret = 0;
1056 struct resource *r;
2e174c33 1057 struct pinctrl *pinctrl;
47d37d6f
SH		 1058
1059 s = kzalloc(sizeof(struct mxs_auart_port), GFP_KERNEL);
1060 if (!s) {
1061 ret = -ENOMEM;
1062 goto out;
1063 }
1064
1ea6607d
FE		 1065 ret = serial_mxs_probe_dt(s, pdev);
1066 if (ret > 0)
1067 s->port.line = pdev->id < 0 ? 0 : pdev->id;
1068 else if (ret < 0)
1069 goto out_free;
1070
2e174c33
SG		 1071 pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
1072 if (IS_ERR(pinctrl)) {
1073 ret = PTR_ERR(pinctrl);
1074 goto out_free;
1075 }
1076
f4b1f03b
HS		 1077 if (of_id) {
1078 pdev->id_entry = of_id->data;
1079 s->devtype = pdev->id_entry->driver_data;
1080 }
1081
47d37d6f
SH		 1082 s->clk = clk_get(&pdev->dev, NULL);
1083 if (IS_ERR(s->clk)) {
1084 ret = PTR_ERR(s->clk);
1085 goto out_free;
1086 }
1087
1088 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1089 if (!r) {
1090 ret = -ENXIO;
1091 goto out_free_clk;
1092 }
1093
1094 s->port.mapbase = r->start;
1095 s->port.membase = ioremap(r->start, resource_size(r));
1096 s->port.ops = &mxs_auart_ops;
1097 s->port.iotype = UPIO_MEM;
47d37d6f
SH		 1098 s->port.fifosize = 16;
1099 s->port.uartclk = clk_get_rate(s->clk);
1100 s->port.type = PORT_IMX;
1101 s->port.dev = s->dev = get_device(&pdev->dev);
1102
47d37d6f
SH		 1103 s->ctrl = 0;
1104
1105 s->irq = platform_get_irq(pdev, 0);
1106 s->port.irq = s->irq;
1107 ret = request_irq(s->irq, mxs_auart_irq_handle, 0, dev_name(&pdev->dev), s);
1108 if (ret)
1109 goto out_free_clk;
1110
1111 platform_set_drvdata(pdev, s);
1112
1ea6607d 1113 auart_port[s->port.line] = s;
47d37d6f
SH		 1114
1115 mxs_auart_reset(&s->port);
1116
1117 ret = uart_add_one_port(&auart_driver, &s->port);
1118 if (ret)
1119 goto out_free_irq;
1120
1121 version = readl(s->port.membase + AUART_VERSION);
1122 dev_info(&pdev->dev, "Found APPUART %d.%d.%d\n",
1123 (version >> 24) & 0xff,
1124 (version >> 16) & 0xff, version & 0xffff);
1125
1126 return 0;
1127
1128out_free_irq:
1129 auart_port[pdev->id] = NULL;
1130 free_irq(s->irq, s);
1131out_free_clk:
23666a74 1132 put_device(s->dev);
47d37d6f
SH		 1133 clk_put(s->clk);
1134out_free:
1135 kfree(s);
1136out:
1137 return ret;
1138}
1139
ae8d8a14 1140static int mxs_auart_remove(struct platform_device *pdev)
47d37d6f
SH		 1141{
1142 struct mxs_auart_port *s = platform_get_drvdata(pdev);
1143
1144 uart_remove_one_port(&auart_driver, &s->port);
1145
1146 auart_port[pdev->id] = NULL;
1147
b69200fb 1148 put_device(s->dev);
47d37d6f
SH		 1149 clk_put(s->clk);
1150 free_irq(s->irq, s);
1151 kfree(s);
1152
1153 return 0;
1154}
1155
1156static struct platform_driver mxs_auart_driver = {
1157 .probe = mxs_auart_probe,
2d47b716 1158 .remove = mxs_auart_remove,
47d37d6f
SH		 1159 .driver = {
1160 .name = "mxs-auart",
1161 .owner = THIS_MODULE,
1ea6607d 1162 .of_match_table = mxs_auart_dt_ids,
47d37d6f
SH		 1163 },
1164};
1165
1166static int __init mxs_auart_init(void)
1167{
1168 int r;
1169
1170 r = uart_register_driver(&auart_driver);
1171 if (r)
1172 goto out;
1173
1174 r = platform_driver_register(&mxs_auart_driver);
1175 if (r)
1176 goto out_err;
1177
1178 return 0;
1179out_err:
1180 uart_unregister_driver(&auart_driver);
1181out:
1182 return r;
1183}
1184
1185static void __exit mxs_auart_exit(void)
1186{
1187 platform_driver_unregister(&mxs_auart_driver);
1188 uart_unregister_driver(&auart_driver);
1189}
1190
1191module_init(mxs_auart_init);
1192module_exit(mxs_auart_exit);
1193MODULE_LICENSE("GPL");
1194MODULE_DESCRIPTION("Freescale MXS application uart driver");
1ea6607d 1195MODULE_ALIAS("platform:mxs-auart");
Linux 6.x block layer and io_uring tree(s)