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47d37d6f SH |
1 | /* |
2 | * Freescale STMP37XX/STMP378X Application UART driver | |
3 | * | |
4 | * Author: dmitry pervushin <dimka@embeddedalley.com> | |
5 | * | |
6 | * Copyright 2008-2010 Freescale Semiconductor, Inc. | |
7 | * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. | |
8 | * | |
9 | * The code contained herein is licensed under the GNU General Public | |
10 | * License. You may obtain a copy of the GNU General Public License | |
11 | * Version 2 or later at the following locations: | |
12 | * | |
13 | * http://www.opensource.org/licenses/gpl-license.html | |
14 | * http://www.gnu.org/copyleft/gpl.html | |
15 | */ | |
16 | ||
17 | #include <linux/kernel.h> | |
47d37d6f SH |
18 | #include <linux/errno.h> |
19 | #include <linux/init.h> | |
20 | #include <linux/console.h> | |
21 | #include <linux/interrupt.h> | |
22 | #include <linux/module.h> | |
23 | #include <linux/slab.h> | |
24 | #include <linux/wait.h> | |
25 | #include <linux/tty.h> | |
26 | #include <linux/tty_driver.h> | |
27 | #include <linux/tty_flip.h> | |
28 | #include <linux/serial.h> | |
29 | #include <linux/serial_core.h> | |
30 | #include <linux/platform_device.h> | |
31 | #include <linux/device.h> | |
32 | #include <linux/clk.h> | |
33 | #include <linux/delay.h> | |
34 | #include <linux/io.h> | |
2e174c33 | 35 | #include <linux/pinctrl/consumer.h> |
1ea6607d | 36 | #include <linux/of_device.h> |
47d37d6f SH |
37 | |
38 | #include <asm/cacheflush.h> | |
39 | ||
40 | #define MXS_AUART_PORTS 5 | |
41 | ||
42 | #define AUART_CTRL0 0x00000000 | |
43 | #define AUART_CTRL0_SET 0x00000004 | |
44 | #define AUART_CTRL0_CLR 0x00000008 | |
45 | #define AUART_CTRL0_TOG 0x0000000c | |
46 | #define AUART_CTRL1 0x00000010 | |
47 | #define AUART_CTRL1_SET 0x00000014 | |
48 | #define AUART_CTRL1_CLR 0x00000018 | |
49 | #define AUART_CTRL1_TOG 0x0000001c | |
50 | #define AUART_CTRL2 0x00000020 | |
51 | #define AUART_CTRL2_SET 0x00000024 | |
52 | #define AUART_CTRL2_CLR 0x00000028 | |
53 | #define AUART_CTRL2_TOG 0x0000002c | |
54 | #define AUART_LINECTRL 0x00000030 | |
55 | #define AUART_LINECTRL_SET 0x00000034 | |
56 | #define AUART_LINECTRL_CLR 0x00000038 | |
57 | #define AUART_LINECTRL_TOG 0x0000003c | |
58 | #define AUART_LINECTRL2 0x00000040 | |
59 | #define AUART_LINECTRL2_SET 0x00000044 | |
60 | #define AUART_LINECTRL2_CLR 0x00000048 | |
61 | #define AUART_LINECTRL2_TOG 0x0000004c | |
62 | #define AUART_INTR 0x00000050 | |
63 | #define AUART_INTR_SET 0x00000054 | |
64 | #define AUART_INTR_CLR 0x00000058 | |
65 | #define AUART_INTR_TOG 0x0000005c | |
66 | #define AUART_DATA 0x00000060 | |
67 | #define AUART_STAT 0x00000070 | |
68 | #define AUART_DEBUG 0x00000080 | |
69 | #define AUART_VERSION 0x00000090 | |
70 | #define AUART_AUTOBAUD 0x000000a0 | |
71 | ||
72 | #define AUART_CTRL0_SFTRST (1 << 31) | |
73 | #define AUART_CTRL0_CLKGATE (1 << 30) | |
74 | ||
75 | #define AUART_CTRL2_CTSEN (1 << 15) | |
00592021 | 76 | #define AUART_CTRL2_RTSEN (1 << 14) |
47d37d6f SH |
77 | #define AUART_CTRL2_RTS (1 << 11) |
78 | #define AUART_CTRL2_RXE (1 << 9) | |
79 | #define AUART_CTRL2_TXE (1 << 8) | |
80 | #define AUART_CTRL2_UARTEN (1 << 0) | |
81 | ||
82 | #define AUART_LINECTRL_BAUD_DIVINT_SHIFT 16 | |
83 | #define AUART_LINECTRL_BAUD_DIVINT_MASK 0xffff0000 | |
84 | #define AUART_LINECTRL_BAUD_DIVINT(v) (((v) & 0xffff) << 16) | |
85 | #define AUART_LINECTRL_BAUD_DIVFRAC_SHIFT 8 | |
86 | #define AUART_LINECTRL_BAUD_DIVFRAC_MASK 0x00003f00 | |
87 | #define AUART_LINECTRL_BAUD_DIVFRAC(v) (((v) & 0x3f) << 8) | |
88 | #define AUART_LINECTRL_WLEN_MASK 0x00000060 | |
89 | #define AUART_LINECTRL_WLEN(v) (((v) & 0x3) << 5) | |
90 | #define AUART_LINECTRL_FEN (1 << 4) | |
91 | #define AUART_LINECTRL_STP2 (1 << 3) | |
92 | #define AUART_LINECTRL_EPS (1 << 2) | |
93 | #define AUART_LINECTRL_PEN (1 << 1) | |
94 | #define AUART_LINECTRL_BRK (1 << 0) | |
95 | ||
96 | #define AUART_INTR_RTIEN (1 << 22) | |
97 | #define AUART_INTR_TXIEN (1 << 21) | |
98 | #define AUART_INTR_RXIEN (1 << 20) | |
99 | #define AUART_INTR_CTSMIEN (1 << 17) | |
100 | #define AUART_INTR_RTIS (1 << 6) | |
101 | #define AUART_INTR_TXIS (1 << 5) | |
102 | #define AUART_INTR_RXIS (1 << 4) | |
103 | #define AUART_INTR_CTSMIS (1 << 1) | |
104 | ||
105 | #define AUART_STAT_BUSY (1 << 29) | |
106 | #define AUART_STAT_CTS (1 << 28) | |
107 | #define AUART_STAT_TXFE (1 << 27) | |
108 | #define AUART_STAT_TXFF (1 << 25) | |
109 | #define AUART_STAT_RXFE (1 << 24) | |
110 | #define AUART_STAT_OERR (1 << 19) | |
111 | #define AUART_STAT_BERR (1 << 18) | |
112 | #define AUART_STAT_PERR (1 << 17) | |
113 | #define AUART_STAT_FERR (1 << 16) | |
114 | ||
115 | static struct uart_driver auart_driver; | |
116 | ||
117 | struct mxs_auart_port { | |
118 | struct uart_port port; | |
119 | ||
120 | unsigned int flags; | |
121 | unsigned int ctrl; | |
122 | ||
123 | unsigned int irq; | |
124 | ||
125 | struct clk *clk; | |
126 | struct device *dev; | |
127 | }; | |
128 | ||
129 | static void mxs_auart_stop_tx(struct uart_port *u); | |
130 | ||
131 | #define to_auart_port(u) container_of(u, struct mxs_auart_port, port) | |
132 | ||
133 | static inline void mxs_auart_tx_chars(struct mxs_auart_port *s) | |
134 | { | |
135 | struct circ_buf *xmit = &s->port.state->xmit; | |
136 | ||
137 | while (!(readl(s->port.membase + AUART_STAT) & | |
138 | AUART_STAT_TXFF)) { | |
139 | if (s->port.x_char) { | |
140 | s->port.icount.tx++; | |
141 | writel(s->port.x_char, | |
142 | s->port.membase + AUART_DATA); | |
143 | s->port.x_char = 0; | |
144 | continue; | |
145 | } | |
146 | if (!uart_circ_empty(xmit) && !uart_tx_stopped(&s->port)) { | |
147 | s->port.icount.tx++; | |
148 | writel(xmit->buf[xmit->tail], | |
149 | s->port.membase + AUART_DATA); | |
150 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); | |
47d37d6f SH |
151 | } else |
152 | break; | |
153 | } | |
d0758a28 UKK |
154 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) |
155 | uart_write_wakeup(&s->port); | |
156 | ||
47d37d6f SH |
157 | if (uart_circ_empty(&(s->port.state->xmit))) |
158 | writel(AUART_INTR_TXIEN, | |
159 | s->port.membase + AUART_INTR_CLR); | |
160 | else | |
161 | writel(AUART_INTR_TXIEN, | |
162 | s->port.membase + AUART_INTR_SET); | |
163 | ||
164 | if (uart_tx_stopped(&s->port)) | |
165 | mxs_auart_stop_tx(&s->port); | |
166 | } | |
167 | ||
168 | static void mxs_auart_rx_char(struct mxs_auart_port *s) | |
169 | { | |
170 | int flag; | |
171 | u32 stat; | |
172 | u8 c; | |
173 | ||
174 | c = readl(s->port.membase + AUART_DATA); | |
175 | stat = readl(s->port.membase + AUART_STAT); | |
176 | ||
177 | flag = TTY_NORMAL; | |
178 | s->port.icount.rx++; | |
179 | ||
180 | if (stat & AUART_STAT_BERR) { | |
181 | s->port.icount.brk++; | |
182 | if (uart_handle_break(&s->port)) | |
183 | goto out; | |
184 | } else if (stat & AUART_STAT_PERR) { | |
185 | s->port.icount.parity++; | |
186 | } else if (stat & AUART_STAT_FERR) { | |
187 | s->port.icount.frame++; | |
188 | } | |
189 | ||
190 | /* | |
191 | * Mask off conditions which should be ingored. | |
192 | */ | |
193 | stat &= s->port.read_status_mask; | |
194 | ||
195 | if (stat & AUART_STAT_BERR) { | |
196 | flag = TTY_BREAK; | |
197 | } else if (stat & AUART_STAT_PERR) | |
198 | flag = TTY_PARITY; | |
199 | else if (stat & AUART_STAT_FERR) | |
200 | flag = TTY_FRAME; | |
201 | ||
202 | if (stat & AUART_STAT_OERR) | |
203 | s->port.icount.overrun++; | |
204 | ||
205 | if (uart_handle_sysrq_char(&s->port, c)) | |
206 | goto out; | |
207 | ||
208 | uart_insert_char(&s->port, stat, AUART_STAT_OERR, c, flag); | |
209 | out: | |
210 | writel(stat, s->port.membase + AUART_STAT); | |
211 | } | |
212 | ||
213 | static void mxs_auart_rx_chars(struct mxs_auart_port *s) | |
214 | { | |
215 | struct tty_struct *tty = s->port.state->port.tty; | |
216 | u32 stat = 0; | |
217 | ||
218 | for (;;) { | |
219 | stat = readl(s->port.membase + AUART_STAT); | |
220 | if (stat & AUART_STAT_RXFE) | |
221 | break; | |
222 | mxs_auart_rx_char(s); | |
223 | } | |
224 | ||
225 | writel(stat, s->port.membase + AUART_STAT); | |
226 | tty_flip_buffer_push(tty); | |
227 | } | |
228 | ||
229 | static int mxs_auart_request_port(struct uart_port *u) | |
230 | { | |
231 | return 0; | |
232 | } | |
233 | ||
234 | static int mxs_auart_verify_port(struct uart_port *u, | |
235 | struct serial_struct *ser) | |
236 | { | |
237 | if (u->type != PORT_UNKNOWN && u->type != PORT_IMX) | |
238 | return -EINVAL; | |
239 | return 0; | |
240 | } | |
241 | ||
242 | static void mxs_auart_config_port(struct uart_port *u, int flags) | |
243 | { | |
244 | } | |
245 | ||
246 | static const char *mxs_auart_type(struct uart_port *u) | |
247 | { | |
248 | struct mxs_auart_port *s = to_auart_port(u); | |
249 | ||
250 | return dev_name(s->dev); | |
251 | } | |
252 | ||
253 | static void mxs_auart_release_port(struct uart_port *u) | |
254 | { | |
255 | } | |
256 | ||
257 | static void mxs_auart_set_mctrl(struct uart_port *u, unsigned mctrl) | |
258 | { | |
259 | struct mxs_auart_port *s = to_auart_port(u); | |
260 | ||
261 | u32 ctrl = readl(u->membase + AUART_CTRL2); | |
262 | ||
00592021 HS |
263 | ctrl &= ~AUART_CTRL2_RTSEN; |
264 | if (mctrl & TIOCM_RTS) { | |
f21ec3d2 | 265 | if (tty_port_cts_enabled(&u->state->port)) |
00592021 HS |
266 | ctrl |= AUART_CTRL2_RTSEN; |
267 | } | |
268 | ||
47d37d6f SH |
269 | s->ctrl = mctrl; |
270 | writel(ctrl, u->membase + AUART_CTRL2); | |
271 | } | |
272 | ||
273 | static u32 mxs_auart_get_mctrl(struct uart_port *u) | |
274 | { | |
275 | struct mxs_auart_port *s = to_auart_port(u); | |
276 | u32 stat = readl(u->membase + AUART_STAT); | |
277 | int ctrl2 = readl(u->membase + AUART_CTRL2); | |
278 | u32 mctrl = s->ctrl; | |
279 | ||
280 | mctrl &= ~TIOCM_CTS; | |
281 | if (stat & AUART_STAT_CTS) | |
282 | mctrl |= TIOCM_CTS; | |
283 | ||
284 | if (ctrl2 & AUART_CTRL2_RTS) | |
285 | mctrl |= TIOCM_RTS; | |
286 | ||
287 | return mctrl; | |
288 | } | |
289 | ||
290 | static void mxs_auart_settermios(struct uart_port *u, | |
291 | struct ktermios *termios, | |
292 | struct ktermios *old) | |
293 | { | |
294 | u32 bm, ctrl, ctrl2, div; | |
295 | unsigned int cflag, baud; | |
296 | ||
297 | cflag = termios->c_cflag; | |
298 | ||
299 | ctrl = AUART_LINECTRL_FEN; | |
300 | ctrl2 = readl(u->membase + AUART_CTRL2); | |
301 | ||
302 | /* byte size */ | |
303 | switch (cflag & CSIZE) { | |
304 | case CS5: | |
305 | bm = 0; | |
306 | break; | |
307 | case CS6: | |
308 | bm = 1; | |
309 | break; | |
310 | case CS7: | |
311 | bm = 2; | |
312 | break; | |
313 | case CS8: | |
314 | bm = 3; | |
315 | break; | |
316 | default: | |
317 | return; | |
318 | } | |
319 | ||
320 | ctrl |= AUART_LINECTRL_WLEN(bm); | |
321 | ||
322 | /* parity */ | |
323 | if (cflag & PARENB) { | |
324 | ctrl |= AUART_LINECTRL_PEN; | |
325 | if ((cflag & PARODD) == 0) | |
326 | ctrl |= AUART_LINECTRL_EPS; | |
327 | } | |
328 | ||
329 | u->read_status_mask = 0; | |
330 | ||
331 | if (termios->c_iflag & INPCK) | |
332 | u->read_status_mask |= AUART_STAT_PERR; | |
333 | if (termios->c_iflag & (BRKINT | PARMRK)) | |
334 | u->read_status_mask |= AUART_STAT_BERR; | |
335 | ||
336 | /* | |
337 | * Characters to ignore | |
338 | */ | |
339 | u->ignore_status_mask = 0; | |
340 | if (termios->c_iflag & IGNPAR) | |
341 | u->ignore_status_mask |= AUART_STAT_PERR; | |
342 | if (termios->c_iflag & IGNBRK) { | |
343 | u->ignore_status_mask |= AUART_STAT_BERR; | |
344 | /* | |
345 | * If we're ignoring parity and break indicators, | |
346 | * ignore overruns too (for real raw support). | |
347 | */ | |
348 | if (termios->c_iflag & IGNPAR) | |
349 | u->ignore_status_mask |= AUART_STAT_OERR; | |
350 | } | |
351 | ||
352 | /* | |
353 | * ignore all characters if CREAD is not set | |
354 | */ | |
355 | if (cflag & CREAD) | |
356 | ctrl2 |= AUART_CTRL2_RXE; | |
357 | else | |
358 | ctrl2 &= ~AUART_CTRL2_RXE; | |
359 | ||
360 | /* figure out the stop bits requested */ | |
361 | if (cflag & CSTOPB) | |
362 | ctrl |= AUART_LINECTRL_STP2; | |
363 | ||
364 | /* figure out the hardware flow control settings */ | |
365 | if (cflag & CRTSCTS) | |
00592021 | 366 | ctrl2 |= AUART_CTRL2_CTSEN | AUART_CTRL2_RTSEN; |
47d37d6f | 367 | else |
00592021 | 368 | ctrl2 &= ~(AUART_CTRL2_CTSEN | AUART_CTRL2_RTSEN); |
47d37d6f SH |
369 | |
370 | /* set baud rate */ | |
371 | baud = uart_get_baud_rate(u, termios, old, 0, u->uartclk); | |
372 | div = u->uartclk * 32 / baud; | |
373 | ctrl |= AUART_LINECTRL_BAUD_DIVFRAC(div & 0x3F); | |
374 | ctrl |= AUART_LINECTRL_BAUD_DIVINT(div >> 6); | |
375 | ||
376 | writel(ctrl, u->membase + AUART_LINECTRL); | |
377 | writel(ctrl2, u->membase + AUART_CTRL2); | |
8b979f7c LW |
378 | |
379 | uart_update_timeout(u, termios->c_cflag, baud); | |
47d37d6f SH |
380 | } |
381 | ||
382 | static irqreturn_t mxs_auart_irq_handle(int irq, void *context) | |
383 | { | |
384 | u32 istatus, istat; | |
385 | struct mxs_auart_port *s = context; | |
386 | u32 stat = readl(s->port.membase + AUART_STAT); | |
387 | ||
388 | istatus = istat = readl(s->port.membase + AUART_INTR); | |
389 | ||
390 | if (istat & AUART_INTR_CTSMIS) { | |
391 | uart_handle_cts_change(&s->port, stat & AUART_STAT_CTS); | |
392 | writel(AUART_INTR_CTSMIS, | |
393 | s->port.membase + AUART_INTR_CLR); | |
394 | istat &= ~AUART_INTR_CTSMIS; | |
395 | } | |
396 | ||
397 | if (istat & (AUART_INTR_RTIS | AUART_INTR_RXIS)) { | |
398 | mxs_auart_rx_chars(s); | |
399 | istat &= ~(AUART_INTR_RTIS | AUART_INTR_RXIS); | |
400 | } | |
401 | ||
402 | if (istat & AUART_INTR_TXIS) { | |
403 | mxs_auart_tx_chars(s); | |
404 | istat &= ~AUART_INTR_TXIS; | |
405 | } | |
406 | ||
407 | writel(istatus & (AUART_INTR_RTIS | |
408 | | AUART_INTR_TXIS | |
409 | | AUART_INTR_RXIS | |
410 | | AUART_INTR_CTSMIS), | |
411 | s->port.membase + AUART_INTR_CLR); | |
412 | ||
413 | return IRQ_HANDLED; | |
414 | } | |
415 | ||
416 | static void mxs_auart_reset(struct uart_port *u) | |
417 | { | |
418 | int i; | |
419 | unsigned int reg; | |
420 | ||
421 | writel(AUART_CTRL0_SFTRST, u->membase + AUART_CTRL0_CLR); | |
422 | ||
423 | for (i = 0; i < 10000; i++) { | |
424 | reg = readl(u->membase + AUART_CTRL0); | |
425 | if (!(reg & AUART_CTRL0_SFTRST)) | |
426 | break; | |
427 | udelay(3); | |
428 | } | |
429 | writel(AUART_CTRL0_CLKGATE, u->membase + AUART_CTRL0_CLR); | |
430 | } | |
431 | ||
432 | static int mxs_auart_startup(struct uart_port *u) | |
433 | { | |
434 | struct mxs_auart_port *s = to_auart_port(u); | |
435 | ||
a4813770 | 436 | clk_prepare_enable(s->clk); |
47d37d6f SH |
437 | |
438 | writel(AUART_CTRL0_CLKGATE, u->membase + AUART_CTRL0_CLR); | |
439 | ||
440 | writel(AUART_CTRL2_UARTEN, u->membase + AUART_CTRL2_SET); | |
441 | ||
442 | writel(AUART_INTR_RXIEN | AUART_INTR_RTIEN | AUART_INTR_CTSMIEN, | |
443 | u->membase + AUART_INTR); | |
444 | ||
445 | /* | |
446 | * Enable fifo so all four bytes of a DMA word are written to | |
447 | * output (otherwise, only the LSB is written, ie. 1 in 4 bytes) | |
448 | */ | |
449 | writel(AUART_LINECTRL_FEN, u->membase + AUART_LINECTRL_SET); | |
450 | ||
451 | return 0; | |
452 | } | |
453 | ||
454 | static void mxs_auart_shutdown(struct uart_port *u) | |
455 | { | |
456 | struct mxs_auart_port *s = to_auart_port(u); | |
457 | ||
458 | writel(AUART_CTRL2_UARTEN, u->membase + AUART_CTRL2_CLR); | |
459 | ||
47d37d6f SH |
460 | writel(AUART_INTR_RXIEN | AUART_INTR_RTIEN | AUART_INTR_CTSMIEN, |
461 | u->membase + AUART_INTR_CLR); | |
462 | ||
851b714b HS |
463 | writel(AUART_CTRL0_CLKGATE, u->membase + AUART_CTRL0_SET); |
464 | ||
a4813770 | 465 | clk_disable_unprepare(s->clk); |
47d37d6f SH |
466 | } |
467 | ||
468 | static unsigned int mxs_auart_tx_empty(struct uart_port *u) | |
469 | { | |
470 | if (readl(u->membase + AUART_STAT) & AUART_STAT_TXFE) | |
471 | return TIOCSER_TEMT; | |
472 | else | |
473 | return 0; | |
474 | } | |
475 | ||
476 | static void mxs_auart_start_tx(struct uart_port *u) | |
477 | { | |
478 | struct mxs_auart_port *s = to_auart_port(u); | |
479 | ||
480 | /* enable transmitter */ | |
481 | writel(AUART_CTRL2_TXE, u->membase + AUART_CTRL2_SET); | |
482 | ||
483 | mxs_auart_tx_chars(s); | |
484 | } | |
485 | ||
486 | static void mxs_auart_stop_tx(struct uart_port *u) | |
487 | { | |
488 | writel(AUART_CTRL2_TXE, u->membase + AUART_CTRL2_CLR); | |
489 | } | |
490 | ||
491 | static void mxs_auart_stop_rx(struct uart_port *u) | |
492 | { | |
493 | writel(AUART_CTRL2_RXE, u->membase + AUART_CTRL2_CLR); | |
494 | } | |
495 | ||
496 | static void mxs_auart_break_ctl(struct uart_port *u, int ctl) | |
497 | { | |
498 | if (ctl) | |
499 | writel(AUART_LINECTRL_BRK, | |
500 | u->membase + AUART_LINECTRL_SET); | |
501 | else | |
502 | writel(AUART_LINECTRL_BRK, | |
503 | u->membase + AUART_LINECTRL_CLR); | |
504 | } | |
505 | ||
506 | static void mxs_auart_enable_ms(struct uart_port *port) | |
507 | { | |
508 | /* just empty */ | |
509 | } | |
510 | ||
511 | static struct uart_ops mxs_auart_ops = { | |
512 | .tx_empty = mxs_auart_tx_empty, | |
513 | .start_tx = mxs_auart_start_tx, | |
514 | .stop_tx = mxs_auart_stop_tx, | |
515 | .stop_rx = mxs_auart_stop_rx, | |
516 | .enable_ms = mxs_auart_enable_ms, | |
517 | .break_ctl = mxs_auart_break_ctl, | |
518 | .set_mctrl = mxs_auart_set_mctrl, | |
519 | .get_mctrl = mxs_auart_get_mctrl, | |
520 | .startup = mxs_auart_startup, | |
521 | .shutdown = mxs_auart_shutdown, | |
522 | .set_termios = mxs_auart_settermios, | |
523 | .type = mxs_auart_type, | |
524 | .release_port = mxs_auart_release_port, | |
525 | .request_port = mxs_auart_request_port, | |
526 | .config_port = mxs_auart_config_port, | |
527 | .verify_port = mxs_auart_verify_port, | |
528 | }; | |
529 | ||
530 | static struct mxs_auart_port *auart_port[MXS_AUART_PORTS]; | |
531 | ||
532 | #ifdef CONFIG_SERIAL_MXS_AUART_CONSOLE | |
533 | static void mxs_auart_console_putchar(struct uart_port *port, int ch) | |
534 | { | |
535 | unsigned int to = 1000; | |
536 | ||
537 | while (readl(port->membase + AUART_STAT) & AUART_STAT_TXFF) { | |
538 | if (!to--) | |
539 | break; | |
540 | udelay(1); | |
541 | } | |
542 | ||
543 | writel(ch, port->membase + AUART_DATA); | |
544 | } | |
545 | ||
546 | static void | |
547 | auart_console_write(struct console *co, const char *str, unsigned int count) | |
548 | { | |
549 | struct mxs_auart_port *s; | |
550 | struct uart_port *port; | |
551 | unsigned int old_ctrl0, old_ctrl2; | |
552 | unsigned int to = 1000; | |
553 | ||
554 | if (co->index > MXS_AUART_PORTS || co->index < 0) | |
555 | return; | |
556 | ||
557 | s = auart_port[co->index]; | |
558 | port = &s->port; | |
559 | ||
560 | clk_enable(s->clk); | |
561 | ||
562 | /* First save the CR then disable the interrupts */ | |
563 | old_ctrl2 = readl(port->membase + AUART_CTRL2); | |
564 | old_ctrl0 = readl(port->membase + AUART_CTRL0); | |
565 | ||
566 | writel(AUART_CTRL0_CLKGATE, | |
567 | port->membase + AUART_CTRL0_CLR); | |
568 | writel(AUART_CTRL2_UARTEN | AUART_CTRL2_TXE, | |
569 | port->membase + AUART_CTRL2_SET); | |
570 | ||
571 | uart_console_write(port, str, count, mxs_auart_console_putchar); | |
572 | ||
573 | /* | |
574 | * Finally, wait for transmitter to become empty | |
575 | * and restore the TCR | |
576 | */ | |
577 | while (readl(port->membase + AUART_STAT) & AUART_STAT_BUSY) { | |
578 | if (!to--) | |
579 | break; | |
580 | udelay(1); | |
581 | } | |
582 | ||
583 | writel(old_ctrl0, port->membase + AUART_CTRL0); | |
584 | writel(old_ctrl2, port->membase + AUART_CTRL2); | |
585 | ||
586 | clk_disable(s->clk); | |
587 | } | |
588 | ||
589 | static void __init | |
590 | auart_console_get_options(struct uart_port *port, int *baud, | |
591 | int *parity, int *bits) | |
592 | { | |
593 | unsigned int lcr_h, quot; | |
594 | ||
595 | if (!(readl(port->membase + AUART_CTRL2) & AUART_CTRL2_UARTEN)) | |
596 | return; | |
597 | ||
598 | lcr_h = readl(port->membase + AUART_LINECTRL); | |
599 | ||
600 | *parity = 'n'; | |
601 | if (lcr_h & AUART_LINECTRL_PEN) { | |
602 | if (lcr_h & AUART_LINECTRL_EPS) | |
603 | *parity = 'e'; | |
604 | else | |
605 | *parity = 'o'; | |
606 | } | |
607 | ||
608 | if ((lcr_h & AUART_LINECTRL_WLEN_MASK) == AUART_LINECTRL_WLEN(2)) | |
609 | *bits = 7; | |
610 | else | |
611 | *bits = 8; | |
612 | ||
613 | quot = ((readl(port->membase + AUART_LINECTRL) | |
614 | & AUART_LINECTRL_BAUD_DIVINT_MASK)) | |
615 | >> (AUART_LINECTRL_BAUD_DIVINT_SHIFT - 6); | |
616 | quot |= ((readl(port->membase + AUART_LINECTRL) | |
617 | & AUART_LINECTRL_BAUD_DIVFRAC_MASK)) | |
618 | >> AUART_LINECTRL_BAUD_DIVFRAC_SHIFT; | |
619 | if (quot == 0) | |
620 | quot = 1; | |
621 | ||
622 | *baud = (port->uartclk << 2) / quot; | |
623 | } | |
624 | ||
625 | static int __init | |
626 | auart_console_setup(struct console *co, char *options) | |
627 | { | |
628 | struct mxs_auart_port *s; | |
629 | int baud = 9600; | |
630 | int bits = 8; | |
631 | int parity = 'n'; | |
632 | int flow = 'n'; | |
633 | int ret; | |
634 | ||
635 | /* | |
636 | * Check whether an invalid uart number has been specified, and | |
637 | * if so, search for the first available port that does have | |
638 | * console support. | |
639 | */ | |
640 | if (co->index == -1 || co->index >= ARRAY_SIZE(auart_port)) | |
641 | co->index = 0; | |
642 | s = auart_port[co->index]; | |
643 | if (!s) | |
644 | return -ENODEV; | |
645 | ||
a4813770 | 646 | clk_prepare_enable(s->clk); |
47d37d6f SH |
647 | |
648 | if (options) | |
649 | uart_parse_options(options, &baud, &parity, &bits, &flow); | |
650 | else | |
651 | auart_console_get_options(&s->port, &baud, &parity, &bits); | |
652 | ||
653 | ret = uart_set_options(&s->port, co, baud, parity, bits, flow); | |
654 | ||
a4813770 | 655 | clk_disable_unprepare(s->clk); |
47d37d6f SH |
656 | |
657 | return ret; | |
658 | } | |
659 | ||
660 | static struct console auart_console = { | |
661 | .name = "ttyAPP", | |
662 | .write = auart_console_write, | |
663 | .device = uart_console_device, | |
664 | .setup = auart_console_setup, | |
665 | .flags = CON_PRINTBUFFER, | |
666 | .index = -1, | |
667 | .data = &auart_driver, | |
668 | }; | |
669 | #endif | |
670 | ||
671 | static struct uart_driver auart_driver = { | |
672 | .owner = THIS_MODULE, | |
673 | .driver_name = "ttyAPP", | |
674 | .dev_name = "ttyAPP", | |
675 | .major = 0, | |
676 | .minor = 0, | |
677 | .nr = MXS_AUART_PORTS, | |
678 | #ifdef CONFIG_SERIAL_MXS_AUART_CONSOLE | |
679 | .cons = &auart_console, | |
680 | #endif | |
681 | }; | |
682 | ||
1ea6607d FE |
683 | /* |
684 | * This function returns 1 if pdev isn't a device instatiated by dt, 0 if it | |
685 | * could successfully get all information from dt or a negative errno. | |
686 | */ | |
687 | static int serial_mxs_probe_dt(struct mxs_auart_port *s, | |
688 | struct platform_device *pdev) | |
689 | { | |
690 | struct device_node *np = pdev->dev.of_node; | |
691 | int ret; | |
692 | ||
693 | if (!np) | |
694 | /* no device tree device */ | |
695 | return 1; | |
696 | ||
697 | ret = of_alias_get_id(np, "serial"); | |
698 | if (ret < 0) { | |
699 | dev_err(&pdev->dev, "failed to get alias id: %d\n", ret); | |
700 | return ret; | |
701 | } | |
702 | s->port.line = ret; | |
703 | ||
704 | return 0; | |
705 | } | |
706 | ||
47d37d6f SH |
707 | static int __devinit mxs_auart_probe(struct platform_device *pdev) |
708 | { | |
709 | struct mxs_auart_port *s; | |
710 | u32 version; | |
711 | int ret = 0; | |
712 | struct resource *r; | |
2e174c33 | 713 | struct pinctrl *pinctrl; |
47d37d6f SH |
714 | |
715 | s = kzalloc(sizeof(struct mxs_auart_port), GFP_KERNEL); | |
716 | if (!s) { | |
717 | ret = -ENOMEM; | |
718 | goto out; | |
719 | } | |
720 | ||
1ea6607d FE |
721 | ret = serial_mxs_probe_dt(s, pdev); |
722 | if (ret > 0) | |
723 | s->port.line = pdev->id < 0 ? 0 : pdev->id; | |
724 | else if (ret < 0) | |
725 | goto out_free; | |
726 | ||
2e174c33 SG |
727 | pinctrl = devm_pinctrl_get_select_default(&pdev->dev); |
728 | if (IS_ERR(pinctrl)) { | |
729 | ret = PTR_ERR(pinctrl); | |
730 | goto out_free; | |
731 | } | |
732 | ||
47d37d6f SH |
733 | s->clk = clk_get(&pdev->dev, NULL); |
734 | if (IS_ERR(s->clk)) { | |
735 | ret = PTR_ERR(s->clk); | |
736 | goto out_free; | |
737 | } | |
738 | ||
739 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
740 | if (!r) { | |
741 | ret = -ENXIO; | |
742 | goto out_free_clk; | |
743 | } | |
744 | ||
745 | s->port.mapbase = r->start; | |
746 | s->port.membase = ioremap(r->start, resource_size(r)); | |
747 | s->port.ops = &mxs_auart_ops; | |
748 | s->port.iotype = UPIO_MEM; | |
47d37d6f SH |
749 | s->port.fifosize = 16; |
750 | s->port.uartclk = clk_get_rate(s->clk); | |
751 | s->port.type = PORT_IMX; | |
752 | s->port.dev = s->dev = get_device(&pdev->dev); | |
753 | ||
754 | s->flags = 0; | |
755 | s->ctrl = 0; | |
756 | ||
757 | s->irq = platform_get_irq(pdev, 0); | |
758 | s->port.irq = s->irq; | |
759 | ret = request_irq(s->irq, mxs_auart_irq_handle, 0, dev_name(&pdev->dev), s); | |
760 | if (ret) | |
761 | goto out_free_clk; | |
762 | ||
763 | platform_set_drvdata(pdev, s); | |
764 | ||
1ea6607d | 765 | auart_port[s->port.line] = s; |
47d37d6f SH |
766 | |
767 | mxs_auart_reset(&s->port); | |
768 | ||
769 | ret = uart_add_one_port(&auart_driver, &s->port); | |
770 | if (ret) | |
771 | goto out_free_irq; | |
772 | ||
773 | version = readl(s->port.membase + AUART_VERSION); | |
774 | dev_info(&pdev->dev, "Found APPUART %d.%d.%d\n", | |
775 | (version >> 24) & 0xff, | |
776 | (version >> 16) & 0xff, version & 0xffff); | |
777 | ||
778 | return 0; | |
779 | ||
780 | out_free_irq: | |
781 | auart_port[pdev->id] = NULL; | |
782 | free_irq(s->irq, s); | |
783 | out_free_clk: | |
784 | clk_put(s->clk); | |
785 | out_free: | |
786 | kfree(s); | |
787 | out: | |
788 | return ret; | |
789 | } | |
790 | ||
791 | static int __devexit mxs_auart_remove(struct platform_device *pdev) | |
792 | { | |
793 | struct mxs_auart_port *s = platform_get_drvdata(pdev); | |
794 | ||
795 | uart_remove_one_port(&auart_driver, &s->port); | |
796 | ||
797 | auart_port[pdev->id] = NULL; | |
798 | ||
799 | clk_put(s->clk); | |
800 | free_irq(s->irq, s); | |
801 | kfree(s); | |
802 | ||
803 | return 0; | |
804 | } | |
805 | ||
1ea6607d FE |
806 | static struct of_device_id mxs_auart_dt_ids[] = { |
807 | { .compatible = "fsl,imx23-auart", }, | |
808 | { /* sentinel */ } | |
809 | }; | |
810 | MODULE_DEVICE_TABLE(of, mxs_auart_dt_ids); | |
811 | ||
47d37d6f SH |
812 | static struct platform_driver mxs_auart_driver = { |
813 | .probe = mxs_auart_probe, | |
814 | .remove = __devexit_p(mxs_auart_remove), | |
815 | .driver = { | |
816 | .name = "mxs-auart", | |
817 | .owner = THIS_MODULE, | |
1ea6607d | 818 | .of_match_table = mxs_auart_dt_ids, |
47d37d6f SH |
819 | }, |
820 | }; | |
821 | ||
822 | static int __init mxs_auart_init(void) | |
823 | { | |
824 | int r; | |
825 | ||
826 | r = uart_register_driver(&auart_driver); | |
827 | if (r) | |
828 | goto out; | |
829 | ||
830 | r = platform_driver_register(&mxs_auart_driver); | |
831 | if (r) | |
832 | goto out_err; | |
833 | ||
834 | return 0; | |
835 | out_err: | |
836 | uart_unregister_driver(&auart_driver); | |
837 | out: | |
838 | return r; | |
839 | } | |
840 | ||
841 | static void __exit mxs_auart_exit(void) | |
842 | { | |
843 | platform_driver_unregister(&mxs_auart_driver); | |
844 | uart_unregister_driver(&auart_driver); | |
845 | } | |
846 | ||
847 | module_init(mxs_auart_init); | |
848 | module_exit(mxs_auart_exit); | |
849 | MODULE_LICENSE("GPL"); | |
850 | MODULE_DESCRIPTION("Freescale MXS application uart driver"); | |
1ea6607d | 851 | MODULE_ALIAS("platform:mxs-auart"); |