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serial: mxs: enable the DMA only when the RTS/CTS is valid
[linux-2.6-block.git] / drivers / tty / serial / mxs-auart.c
CommitLineData
47d37d6f
SH		 1/*
2 * Freescale STMP37XX/STMP378X Application UART driver
3 *
4 * Author: dmitry pervushin <dimka@embeddedalley.com>
5 *
6 * Copyright 2008-2010 Freescale Semiconductor, Inc.
7 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
8 *
9 * The code contained herein is licensed under the GNU General Public
10 * License. You may obtain a copy of the GNU General Public License
11 * Version 2 or later at the following locations:
12 *
13 * http://www.opensource.org/licenses/gpl-license.html
14 * http://www.gnu.org/copyleft/gpl.html
15 */
16
17#include <linux/kernel.h>
47d37d6f
SH		 18#include <linux/errno.h>
19#include <linux/init.h>
20#include <linux/console.h>
21#include <linux/interrupt.h>
22#include <linux/module.h>
23#include <linux/slab.h>
24#include <linux/wait.h>
25#include <linux/tty.h>
26#include <linux/tty_driver.h>
27#include <linux/tty_flip.h>
28#include <linux/serial.h>
29#include <linux/serial_core.h>
30#include <linux/platform_device.h>
31#include <linux/device.h>
32#include <linux/clk.h>
33#include <linux/delay.h>
34#include <linux/io.h>
1ea6607d 35#include <linux/of_device.h>
e8001632 36#include <linux/dma-mapping.h>
bcc20f9e 37#include <linux/dmaengine.h>
47d37d6f
SH		 38
39#include <asm/cacheflush.h>
40
41#define MXS_AUART_PORTS 5
42
43#define AUART_CTRL0 0x00000000
44#define AUART_CTRL0_SET 0x00000004
45#define AUART_CTRL0_CLR 0x00000008
46#define AUART_CTRL0_TOG 0x0000000c
47#define AUART_CTRL1 0x00000010
48#define AUART_CTRL1_SET 0x00000014
49#define AUART_CTRL1_CLR 0x00000018
50#define AUART_CTRL1_TOG 0x0000001c
51#define AUART_CTRL2 0x00000020
52#define AUART_CTRL2_SET 0x00000024
53#define AUART_CTRL2_CLR 0x00000028
54#define AUART_CTRL2_TOG 0x0000002c
55#define AUART_LINECTRL 0x00000030
56#define AUART_LINECTRL_SET 0x00000034
57#define AUART_LINECTRL_CLR 0x00000038
58#define AUART_LINECTRL_TOG 0x0000003c
59#define AUART_LINECTRL2 0x00000040
60#define AUART_LINECTRL2_SET 0x00000044
61#define AUART_LINECTRL2_CLR 0x00000048
62#define AUART_LINECTRL2_TOG 0x0000004c
63#define AUART_INTR 0x00000050
64#define AUART_INTR_SET 0x00000054
65#define AUART_INTR_CLR 0x00000058
66#define AUART_INTR_TOG 0x0000005c
67#define AUART_DATA 0x00000060
68#define AUART_STAT 0x00000070
69#define AUART_DEBUG 0x00000080
70#define AUART_VERSION 0x00000090
71#define AUART_AUTOBAUD 0x000000a0
72
73#define AUART_CTRL0_SFTRST (1 << 31)
74#define AUART_CTRL0_CLKGATE (1 << 30)
e8001632
HS		 75#define AUART_CTRL0_RXTO_ENABLE (1 << 27)
76#define AUART_CTRL0_RXTIMEOUT(v) (((v) & 0x7ff) << 16)
77#define AUART_CTRL0_XFER_COUNT(v) ((v) & 0xffff)
78
79#define AUART_CTRL1_XFER_COUNT(v) ((v) & 0xffff)
80
81#define AUART_CTRL2_DMAONERR (1 << 26)
82#define AUART_CTRL2_TXDMAE (1 << 25)
83#define AUART_CTRL2_RXDMAE (1 << 24)
47d37d6f
SH		 84
85#define AUART_CTRL2_CTSEN (1 << 15)
00592021 86#define AUART_CTRL2_RTSEN (1 << 14)
47d37d6f
SH		 87#define AUART_CTRL2_RTS (1 << 11)
88#define AUART_CTRL2_RXE (1 << 9)
89#define AUART_CTRL2_TXE (1 << 8)
90#define AUART_CTRL2_UARTEN (1 << 0)
91
92#define AUART_LINECTRL_BAUD_DIVINT_SHIFT 16
93#define AUART_LINECTRL_BAUD_DIVINT_MASK 0xffff0000
94#define AUART_LINECTRL_BAUD_DIVINT(v) (((v) & 0xffff) << 16)
95#define AUART_LINECTRL_BAUD_DIVFRAC_SHIFT 8
96#define AUART_LINECTRL_BAUD_DIVFRAC_MASK 0x00003f00
97#define AUART_LINECTRL_BAUD_DIVFRAC(v) (((v) & 0x3f) << 8)
98#define AUART_LINECTRL_WLEN_MASK 0x00000060
99#define AUART_LINECTRL_WLEN(v) (((v) & 0x3) << 5)
100#define AUART_LINECTRL_FEN (1 << 4)
101#define AUART_LINECTRL_STP2 (1 << 3)
102#define AUART_LINECTRL_EPS (1 << 2)
103#define AUART_LINECTRL_PEN (1 << 1)
104#define AUART_LINECTRL_BRK (1 << 0)
105
106#define AUART_INTR_RTIEN (1 << 22)
107#define AUART_INTR_TXIEN (1 << 21)
108#define AUART_INTR_RXIEN (1 << 20)
109#define AUART_INTR_CTSMIEN (1 << 17)
110#define AUART_INTR_RTIS (1 << 6)
111#define AUART_INTR_TXIS (1 << 5)
112#define AUART_INTR_RXIS (1 << 4)
113#define AUART_INTR_CTSMIS (1 << 1)
114
115#define AUART_STAT_BUSY (1 << 29)
116#define AUART_STAT_CTS (1 << 28)
117#define AUART_STAT_TXFE (1 << 27)
118#define AUART_STAT_TXFF (1 << 25)
119#define AUART_STAT_RXFE (1 << 24)
120#define AUART_STAT_OERR (1 << 19)
121#define AUART_STAT_BERR (1 << 18)
122#define AUART_STAT_PERR (1 << 17)
123#define AUART_STAT_FERR (1 << 16)
e8001632 124#define AUART_STAT_RXCOUNT_MASK 0xffff
47d37d6f
SH		 125
126static struct uart_driver auart_driver;
127
f4b1f03b
HS		 128enum mxs_auart_type {
129 IMX23_AUART,
130 IMX28_AUART,
131};
132
47d37d6f
SH		 133struct mxs_auart_port {
134 struct uart_port port;
135
e8001632
HS		 136#define MXS_AUART_DMA_CONFIG 0x1
137#define MXS_AUART_DMA_ENABLED 0x2
138#define MXS_AUART_DMA_TX_SYNC 2 /* bit 2 */
139#define MXS_AUART_DMA_RX_READY 3 /* bit 3 */
8418e67d 140#define MXS_AUART_RTSCTS 4 /* bit 4 */
e8001632 141 unsigned long flags;
47d37d6f 142 unsigned int ctrl;
f4b1f03b 143 enum mxs_auart_type devtype;
47d37d6f
SH		 144
145 unsigned int irq;
146
147 struct clk *clk;
148 struct device *dev;
e8001632
HS		 149
150 /* for DMA */
e8001632
HS		 151 struct scatterlist tx_sgl;
152 struct dma_chan *tx_dma_chan;
153 void *tx_dma_buf;
154
155 struct scatterlist rx_sgl;
156 struct dma_chan *rx_dma_chan;
157 void *rx_dma_buf;
47d37d6f
SH		 158};
159
f4b1f03b
HS		 160static struct platform_device_id mxs_auart_devtype[] = {
161 { .name = "mxs-auart-imx23", .driver_data = IMX23_AUART },
162 { .name = "mxs-auart-imx28", .driver_data = IMX28_AUART },
163 { /* sentinel */ }
164};
165MODULE_DEVICE_TABLE(platform, mxs_auart_devtype);
166
167static struct of_device_id mxs_auart_dt_ids[] = {
168 {
169 .compatible = "fsl,imx28-auart",
170 .data = &mxs_auart_devtype[IMX28_AUART]
171 }, {
172 .compatible = "fsl,imx23-auart",
173 .data = &mxs_auart_devtype[IMX23_AUART]
174 }, { /* sentinel */ }
175};
176MODULE_DEVICE_TABLE(of, mxs_auart_dt_ids);
177
178static inline int is_imx28_auart(struct mxs_auart_port *s)
179{
180 return s->devtype == IMX28_AUART;
181}
182
e8001632
HS		 183static inline bool auart_dma_enabled(struct mxs_auart_port *s)
184{
185 return s->flags & MXS_AUART_DMA_ENABLED;
186}
187
47d37d6f
SH		 188static void mxs_auart_stop_tx(struct uart_port *u);
189
190#define to_auart_port(u) container_of(u, struct mxs_auart_port, port)
191
e8001632
HS		 192static void mxs_auart_tx_chars(struct mxs_auart_port *s);
193
194static void dma_tx_callback(void *param)
47d37d6f 195{
e8001632 196 struct mxs_auart_port *s = param;
47d37d6f
SH		 197 struct circ_buf *xmit = &s->port.state->xmit;
198
e8001632
HS		 199 dma_unmap_sg(s->dev, &s->tx_sgl, 1, DMA_TO_DEVICE);
200
201 /* clear the bit used to serialize the DMA tx. */
202 clear_bit(MXS_AUART_DMA_TX_SYNC, &s->flags);
203 smp_mb__after_clear_bit();
204
205 /* wake up the possible processes. */
206 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
207 uart_write_wakeup(&s->port);
208
209 mxs_auart_tx_chars(s);
210}
211
212static int mxs_auart_dma_tx(struct mxs_auart_port *s, int size)
213{
214 struct dma_async_tx_descriptor *desc;
215 struct scatterlist *sgl = &s->tx_sgl;
216 struct dma_chan *channel = s->tx_dma_chan;
217 u32 pio;
218
219 /* [1] : send PIO. Note, the first pio word is CTRL1. */
220 pio = AUART_CTRL1_XFER_COUNT(size);
221 desc = dmaengine_prep_slave_sg(channel, (struct scatterlist *)&pio,
222 1, DMA_TRANS_NONE, 0);
223 if (!desc) {
224 dev_err(s->dev, "step 1 error\n");
225 return -EINVAL;
226 }
227
228 /* [2] : set DMA buffer. */
229 sg_init_one(sgl, s->tx_dma_buf, size);
230 dma_map_sg(s->dev, sgl, 1, DMA_TO_DEVICE);
231 desc = dmaengine_prep_slave_sg(channel, sgl,
232 1, DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
233 if (!desc) {
234 dev_err(s->dev, "step 2 error\n");
235 return -EINVAL;
236 }
237
238 /* [3] : submit the DMA */
239 desc->callback = dma_tx_callback;
240 desc->callback_param = s;
241 dmaengine_submit(desc);
242 dma_async_issue_pending(channel);
243 return 0;
244}
245
246static void mxs_auart_tx_chars(struct mxs_auart_port *s)
247{
248 struct circ_buf *xmit = &s->port.state->xmit;
249
250 if (auart_dma_enabled(s)) {
87b8bed2 251 u32 i = 0;
e8001632
HS		 252 int size;
253 void *buffer = s->tx_dma_buf;
254
255 if (test_and_set_bit(MXS_AUART_DMA_TX_SYNC, &s->flags))
256 return;
257
258 while (!uart_circ_empty(xmit) && !uart_tx_stopped(&s->port)) {
259 size = min_t(u32, UART_XMIT_SIZE - i,
260 CIRC_CNT_TO_END(xmit->head,
261 xmit->tail,
262 UART_XMIT_SIZE));
263 memcpy(buffer + i, xmit->buf + xmit->tail, size);
264 xmit->tail = (xmit->tail + size) & (UART_XMIT_SIZE - 1);
265
266 i += size;
267 if (i >= UART_XMIT_SIZE)
268 break;
269 }
270
271 if (uart_tx_stopped(&s->port))
272 mxs_auart_stop_tx(&s->port);
273
274 if (i) {
275 mxs_auart_dma_tx(s, i);
276 } else {
277 clear_bit(MXS_AUART_DMA_TX_SYNC, &s->flags);
278 smp_mb__after_clear_bit();
279 }
280 return;
281 }
282
283
47d37d6f
SH		 284 while (!(readl(s->port.membase + AUART_STAT) &
285 AUART_STAT_TXFF)) {
286 if (s->port.x_char) {
287 s->port.icount.tx++;
288 writel(s->port.x_char,
289 s->port.membase + AUART_DATA);
290 s->port.x_char = 0;
291 continue;
292 }
293 if (!uart_circ_empty(xmit) && !uart_tx_stopped(&s->port)) {
294 s->port.icount.tx++;
295 writel(xmit->buf[xmit->tail],
296 s->port.membase + AUART_DATA);
297 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
47d37d6f
SH		 298 } else
299 break;
300 }
d0758a28
UKK		 301 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
302 uart_write_wakeup(&s->port);
303
47d37d6f
SH		 304 if (uart_circ_empty(&(s->port.state->xmit)))
305 writel(AUART_INTR_TXIEN,
306 s->port.membase + AUART_INTR_CLR);
307 else
308 writel(AUART_INTR_TXIEN,
309 s->port.membase + AUART_INTR_SET);
310
311 if (uart_tx_stopped(&s->port))
312 mxs_auart_stop_tx(&s->port);
313}
314
315static void mxs_auart_rx_char(struct mxs_auart_port *s)
316{
317 int flag;
318 u32 stat;
319 u8 c;
320
321 c = readl(s->port.membase + AUART_DATA);
322 stat = readl(s->port.membase + AUART_STAT);
323
324 flag = TTY_NORMAL;
325 s->port.icount.rx++;
326
327 if (stat & AUART_STAT_BERR) {
328 s->port.icount.brk++;
329 if (uart_handle_break(&s->port))
330 goto out;
331 } else if (stat & AUART_STAT_PERR) {
332 s->port.icount.parity++;
333 } else if (stat & AUART_STAT_FERR) {
334 s->port.icount.frame++;
335 }
336
337 /*
338 * Mask off conditions which should be ingored.
339 */
340 stat &= s->port.read_status_mask;
341
342 if (stat & AUART_STAT_BERR) {
343 flag = TTY_BREAK;
344 } else if (stat & AUART_STAT_PERR)
345 flag = TTY_PARITY;
346 else if (stat & AUART_STAT_FERR)
347 flag = TTY_FRAME;
348
349 if (stat & AUART_STAT_OERR)
350 s->port.icount.overrun++;
351
352 if (uart_handle_sysrq_char(&s->port, c))
353 goto out;
354
355 uart_insert_char(&s->port, stat, AUART_STAT_OERR, c, flag);
356out:
357 writel(stat, s->port.membase + AUART_STAT);
358}
359
360static void mxs_auart_rx_chars(struct mxs_auart_port *s)
361{
47d37d6f
SH		 362 u32 stat = 0;
363
364 for (;;) {
365 stat = readl(s->port.membase + AUART_STAT);
366 if (stat & AUART_STAT_RXFE)
367 break;
368 mxs_auart_rx_char(s);
369 }
370
371 writel(stat, s->port.membase + AUART_STAT);
2e124b4a 372 tty_flip_buffer_push(&s->port.state->port);
47d37d6f
SH		 373}
374
375static int mxs_auart_request_port(struct uart_port *u)
376{
377 return 0;
378}
379
380static int mxs_auart_verify_port(struct uart_port *u,
381 struct serial_struct *ser)
382{
383 if (u->type != PORT_UNKNOWN && u->type != PORT_IMX)
384 return -EINVAL;
385 return 0;
386}
387
388static void mxs_auart_config_port(struct uart_port *u, int flags)
389{
390}
391
392static const char *mxs_auart_type(struct uart_port *u)
393{
394 struct mxs_auart_port *s = to_auart_port(u);
395
396 return dev_name(s->dev);
397}
398
399static void mxs_auart_release_port(struct uart_port *u)
400{
401}
402
403static void mxs_auart_set_mctrl(struct uart_port *u, unsigned mctrl)
404{
405 struct mxs_auart_port *s = to_auart_port(u);
406
407 u32 ctrl = readl(u->membase + AUART_CTRL2);
408
a6833214 409 ctrl &= ~(AUART_CTRL2_RTSEN | AUART_CTRL2_RTS);
00592021 410 if (mctrl & TIOCM_RTS) {
f21ec3d2 411 if (tty_port_cts_enabled(&u->state->port))
00592021 412 ctrl |= AUART_CTRL2_RTSEN;
a6833214
ST		 413 else
414 ctrl |= AUART_CTRL2_RTS;
00592021
HS		 415 }
416
47d37d6f
SH		 417 s->ctrl = mctrl;
418 writel(ctrl, u->membase + AUART_CTRL2);
419}
420
421static u32 mxs_auart_get_mctrl(struct uart_port *u)
422{
423 struct mxs_auart_port *s = to_auart_port(u);
424 u32 stat = readl(u->membase + AUART_STAT);
425 int ctrl2 = readl(u->membase + AUART_CTRL2);
426 u32 mctrl = s->ctrl;
427
428 mctrl &= ~TIOCM_CTS;
429 if (stat & AUART_STAT_CTS)
430 mctrl |= TIOCM_CTS;
431
432 if (ctrl2 & AUART_CTRL2_RTS)
433 mctrl |= TIOCM_RTS;
434
435 return mctrl;
436}
437
e8001632
HS		 438static int mxs_auart_dma_prep_rx(struct mxs_auart_port *s);
439static void dma_rx_callback(void *arg)
440{
441 struct mxs_auart_port *s = (struct mxs_auart_port *) arg;
05c7cd39 442 struct tty_port *port = &s->port.state->port;
e8001632
HS		 443 int count;
444 u32 stat;
445
d7ffb932
HS		 446 dma_unmap_sg(s->dev, &s->rx_sgl, 1, DMA_FROM_DEVICE);
447
e8001632
HS		 448 stat = readl(s->port.membase + AUART_STAT);
449 stat &= ~(AUART_STAT_OERR | AUART_STAT_BERR |
450 AUART_STAT_PERR | AUART_STAT_FERR);
451
452 count = stat & AUART_STAT_RXCOUNT_MASK;
05c7cd39 453 tty_insert_flip_string(port, s->rx_dma_buf, count);
e8001632
HS		 454
455 writel(stat, s->port.membase + AUART_STAT);
2e124b4a 456 tty_flip_buffer_push(port);
e8001632
HS		 457
458 /* start the next DMA for RX. */
459 mxs_auart_dma_prep_rx(s);
460}
461
462static int mxs_auart_dma_prep_rx(struct mxs_auart_port *s)
463{
464 struct dma_async_tx_descriptor *desc;
465 struct scatterlist *sgl = &s->rx_sgl;
466 struct dma_chan *channel = s->rx_dma_chan;
467 u32 pio[1];
468
469 /* [1] : send PIO */
470 pio[0] = AUART_CTRL0_RXTO_ENABLE
471 | AUART_CTRL0_RXTIMEOUT(0x80)
472 | AUART_CTRL0_XFER_COUNT(UART_XMIT_SIZE);
473 desc = dmaengine_prep_slave_sg(channel, (struct scatterlist *)pio,
474 1, DMA_TRANS_NONE, 0);
475 if (!desc) {
476 dev_err(s->dev, "step 1 error\n");
477 return -EINVAL;
478 }
479
480 /* [2] : send DMA request */
481 sg_init_one(sgl, s->rx_dma_buf, UART_XMIT_SIZE);
482 dma_map_sg(s->dev, sgl, 1, DMA_FROM_DEVICE);
483 desc = dmaengine_prep_slave_sg(channel, sgl, 1, DMA_DEV_TO_MEM,
484 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
485 if (!desc) {
486 dev_err(s->dev, "step 2 error\n");
487 return -1;
488 }
489
490 /* [3] : submit the DMA, but do not issue it. */
491 desc->callback = dma_rx_callback;
492 desc->callback_param = s;
493 dmaengine_submit(desc);
494 dma_async_issue_pending(channel);
495 return 0;
496}
497
498static void mxs_auart_dma_exit_channel(struct mxs_auart_port *s)
499{
500 if (s->tx_dma_chan) {
501 dma_release_channel(s->tx_dma_chan);
502 s->tx_dma_chan = NULL;
503 }
504 if (s->rx_dma_chan) {
505 dma_release_channel(s->rx_dma_chan);
506 s->rx_dma_chan = NULL;
507 }
508
509 kfree(s->tx_dma_buf);
510 kfree(s->rx_dma_buf);
511 s->tx_dma_buf = NULL;
512 s->rx_dma_buf = NULL;
513}
514
515static void mxs_auart_dma_exit(struct mxs_auart_port *s)
516{
517
518 writel(AUART_CTRL2_TXDMAE | AUART_CTRL2_RXDMAE | AUART_CTRL2_DMAONERR,
519 s->port.membase + AUART_CTRL2_CLR);
520
521 mxs_auart_dma_exit_channel(s);
522 s->flags &= ~MXS_AUART_DMA_ENABLED;
523 clear_bit(MXS_AUART_DMA_TX_SYNC, &s->flags);
524 clear_bit(MXS_AUART_DMA_RX_READY, &s->flags);
525}
526
527static int mxs_auart_dma_init(struct mxs_auart_port *s)
528{
e8001632
HS		 529 if (auart_dma_enabled(s))
530 return 0;
531
e8001632 532 /* init for RX */
bcc20f9e 533 s->rx_dma_chan = dma_request_slave_channel(s->dev, "rx");
e8001632
HS		 534 if (!s->rx_dma_chan)
535 goto err_out;
536 s->rx_dma_buf = kzalloc(UART_XMIT_SIZE, GFP_KERNEL | GFP_DMA);
537 if (!s->rx_dma_buf)
538 goto err_out;
539
540 /* init for TX */
bcc20f9e 541 s->tx_dma_chan = dma_request_slave_channel(s->dev, "tx");
e8001632
HS		 542 if (!s->tx_dma_chan)
543 goto err_out;
544 s->tx_dma_buf = kzalloc(UART_XMIT_SIZE, GFP_KERNEL | GFP_DMA);
545 if (!s->tx_dma_buf)
546 goto err_out;
547
548 /* set the flags */
549 s->flags |= MXS_AUART_DMA_ENABLED;
550 dev_dbg(s->dev, "enabled the DMA support.");
551
552 return 0;
553
554err_out:
555 mxs_auart_dma_exit_channel(s);
556 return -EINVAL;
557
558}
559
47d37d6f
SH		 560static void mxs_auart_settermios(struct uart_port *u,
561 struct ktermios *termios,
562 struct ktermios *old)
563{
e8001632 564 struct mxs_auart_port *s = to_auart_port(u);
47d37d6f
SH		 565 u32 bm, ctrl, ctrl2, div;
566 unsigned int cflag, baud;
567
568 cflag = termios->c_cflag;
569
570 ctrl = AUART_LINECTRL_FEN;
571 ctrl2 = readl(u->membase + AUART_CTRL2);
572
573 /* byte size */
574 switch (cflag & CSIZE) {
575 case CS5:
576 bm = 0;
577 break;
578 case CS6:
579 bm = 1;
580 break;
581 case CS7:
582 bm = 2;
583 break;
584 case CS8:
585 bm = 3;
586 break;
587 default:
588 return;
589 }
590
591 ctrl |= AUART_LINECTRL_WLEN(bm);
592
593 /* parity */
594 if (cflag & PARENB) {
595 ctrl |= AUART_LINECTRL_PEN;
596 if ((cflag & PARODD) == 0)
597 ctrl |= AUART_LINECTRL_EPS;
598 }
599
600 u->read_status_mask = 0;
601
602 if (termios->c_iflag & INPCK)
603 u->read_status_mask |= AUART_STAT_PERR;
604 if (termios->c_iflag & (BRKINT | PARMRK))
605 u->read_status_mask |= AUART_STAT_BERR;
606
607 /*
608 * Characters to ignore
609 */
610 u->ignore_status_mask = 0;
611 if (termios->c_iflag & IGNPAR)
612 u->ignore_status_mask |= AUART_STAT_PERR;
613 if (termios->c_iflag & IGNBRK) {
614 u->ignore_status_mask |= AUART_STAT_BERR;
615 /*
616 * If we're ignoring parity and break indicators,
617 * ignore overruns too (for real raw support).
618 */
619 if (termios->c_iflag & IGNPAR)
620 u->ignore_status_mask |= AUART_STAT_OERR;
621 }
622
623 /*
624 * ignore all characters if CREAD is not set
625 */
626 if (cflag & CREAD)
627 ctrl2 |= AUART_CTRL2_RXE;
628 else
629 ctrl2 &= ~AUART_CTRL2_RXE;
630
631 /* figure out the stop bits requested */
632 if (cflag & CSTOPB)
633 ctrl |= AUART_LINECTRL_STP2;
634
635 /* figure out the hardware flow control settings */
e8001632
HS		 636 if (cflag & CRTSCTS) {
637 /*
638 * The DMA has a bug(see errata:2836) in mx23.
639 * So we can not implement the DMA for auart in mx23,
640 * we can only implement the DMA support for auart
641 * in mx28.
642 */
8418e67d
HS		 643 if (is_imx28_auart(s) && (s->flags & MXS_AUART_DMA_CONFIG)
644 && test_bit(MXS_AUART_RTSCTS, &s->flags)) {
e8001632
HS		 645 if (!mxs_auart_dma_init(s))
646 /* enable DMA tranfer */
647 ctrl2 |= AUART_CTRL2_TXDMAE | AUART_CTRL2_RXDMAE
648 | AUART_CTRL2_DMAONERR;
649 }
00592021 650 ctrl2 |= AUART_CTRL2_CTSEN | AUART_CTRL2_RTSEN;
e8001632 651 } else {
00592021 652 ctrl2 &= ~(AUART_CTRL2_CTSEN | AUART_CTRL2_RTSEN);
e8001632 653 }
47d37d6f
SH		 654
655 /* set baud rate */
656 baud = uart_get_baud_rate(u, termios, old, 0, u->uartclk);
657 div = u->uartclk * 32 / baud;
658 ctrl |= AUART_LINECTRL_BAUD_DIVFRAC(div & 0x3F);
659 ctrl |= AUART_LINECTRL_BAUD_DIVINT(div >> 6);
660
661 writel(ctrl, u->membase + AUART_LINECTRL);
662 writel(ctrl2, u->membase + AUART_CTRL2);
8b979f7c
LW		 663
664 uart_update_timeout(u, termios->c_cflag, baud);
e8001632
HS		 665
666 /* prepare for the DMA RX. */
667 if (auart_dma_enabled(s) &&
668 !test_and_set_bit(MXS_AUART_DMA_RX_READY, &s->flags)) {
669 if (!mxs_auart_dma_prep_rx(s)) {
670 /* Disable the normal RX interrupt. */
a5919442
HS		 671 writel(AUART_INTR_RXIEN | AUART_INTR_RTIEN,
672 u->membase + AUART_INTR_CLR);
e8001632
HS		 673 } else {
674 mxs_auart_dma_exit(s);
675 dev_err(s->dev, "We can not start up the DMA.\n");
676 }
677 }
47d37d6f
SH		 678}
679
680static irqreturn_t mxs_auart_irq_handle(int irq, void *context)
681{
d970d7fe 682 u32 istat;
47d37d6f
SH		 683 struct mxs_auart_port *s = context;
684 u32 stat = readl(s->port.membase + AUART_STAT);
685
d970d7fe
UKK		 686 istat = readl(s->port.membase + AUART_INTR);
687
688 /* ack irq */
689 writel(istat & (AUART_INTR_RTIS
690 | AUART_INTR_TXIS
691 | AUART_INTR_RXIS
692 | AUART_INTR_CTSMIS),
693 s->port.membase + AUART_INTR_CLR);
47d37d6f
SH		 694
695 if (istat & AUART_INTR_CTSMIS) {
696 uart_handle_cts_change(&s->port, stat & AUART_STAT_CTS);
697 writel(AUART_INTR_CTSMIS,
698 s->port.membase + AUART_INTR_CLR);
699 istat &= ~AUART_INTR_CTSMIS;
700 }
701
702 if (istat & (AUART_INTR_RTIS | AUART_INTR_RXIS)) {
a5919442
HS		 703 if (!auart_dma_enabled(s))
704 mxs_auart_rx_chars(s);
47d37d6f
SH		 705 istat &= ~(AUART_INTR_RTIS | AUART_INTR_RXIS);
706 }
707
708 if (istat & AUART_INTR_TXIS) {
709 mxs_auart_tx_chars(s);
710 istat &= ~AUART_INTR_TXIS;
711 }
712
47d37d6f
SH		 713 return IRQ_HANDLED;
714}
715
716static void mxs_auart_reset(struct uart_port *u)
717{
718 int i;
719 unsigned int reg;
720
721 writel(AUART_CTRL0_SFTRST, u->membase + AUART_CTRL0_CLR);
722
723 for (i = 0; i < 10000; i++) {
724 reg = readl(u->membase + AUART_CTRL0);
725 if (!(reg & AUART_CTRL0_SFTRST))
726 break;
727 udelay(3);
728 }
729 writel(AUART_CTRL0_CLKGATE, u->membase + AUART_CTRL0_CLR);
730}
731
732static int mxs_auart_startup(struct uart_port *u)
733{
734 struct mxs_auart_port *s = to_auart_port(u);
735
a4813770 736 clk_prepare_enable(s->clk);
47d37d6f
SH		 737
738 writel(AUART_CTRL0_CLKGATE, u->membase + AUART_CTRL0_CLR);
739
740 writel(AUART_CTRL2_UARTEN, u->membase + AUART_CTRL2_SET);
741
742 writel(AUART_INTR_RXIEN | AUART_INTR_RTIEN | AUART_INTR_CTSMIEN,
743 u->membase + AUART_INTR);
744
745 /*
746 * Enable fifo so all four bytes of a DMA word are written to
747 * output (otherwise, only the LSB is written, ie. 1 in 4 bytes)
748 */
749 writel(AUART_LINECTRL_FEN, u->membase + AUART_LINECTRL_SET);
750
751 return 0;
752}
753
754static void mxs_auart_shutdown(struct uart_port *u)
755{
756 struct mxs_auart_port *s = to_auart_port(u);
757
e8001632
HS		 758 if (auart_dma_enabled(s))
759 mxs_auart_dma_exit(s);
760
47d37d6f
SH		 761 writel(AUART_CTRL2_UARTEN, u->membase + AUART_CTRL2_CLR);
762
47d37d6f
SH		 763 writel(AUART_INTR_RXIEN | AUART_INTR_RTIEN | AUART_INTR_CTSMIEN,
764 u->membase + AUART_INTR_CLR);
765
851b714b
HS		 766 writel(AUART_CTRL0_CLKGATE, u->membase + AUART_CTRL0_SET);
767
a4813770 768 clk_disable_unprepare(s->clk);
47d37d6f
SH		 769}
770
771static unsigned int mxs_auart_tx_empty(struct uart_port *u)
772{
773 if (readl(u->membase + AUART_STAT) & AUART_STAT_TXFE)
774 return TIOCSER_TEMT;
775 else
776 return 0;
777}
778
779static void mxs_auart_start_tx(struct uart_port *u)
780{
781 struct mxs_auart_port *s = to_auart_port(u);
782
783 /* enable transmitter */
784 writel(AUART_CTRL2_TXE, u->membase + AUART_CTRL2_SET);
785
786 mxs_auart_tx_chars(s);
787}
788
789static void mxs_auart_stop_tx(struct uart_port *u)
790{
791 writel(AUART_CTRL2_TXE, u->membase + AUART_CTRL2_CLR);
792}
793
794static void mxs_auart_stop_rx(struct uart_port *u)
795{
796 writel(AUART_CTRL2_RXE, u->membase + AUART_CTRL2_CLR);
797}
798
799static void mxs_auart_break_ctl(struct uart_port *u, int ctl)
800{
801 if (ctl)
802 writel(AUART_LINECTRL_BRK,
803 u->membase + AUART_LINECTRL_SET);
804 else
805 writel(AUART_LINECTRL_BRK,
806 u->membase + AUART_LINECTRL_CLR);
807}
808
809static void mxs_auart_enable_ms(struct uart_port *port)
810{
811 /* just empty */
812}
813
814static struct uart_ops mxs_auart_ops = {
815 .tx_empty = mxs_auart_tx_empty,
816 .start_tx = mxs_auart_start_tx,
817 .stop_tx = mxs_auart_stop_tx,
818 .stop_rx = mxs_auart_stop_rx,
819 .enable_ms = mxs_auart_enable_ms,
820 .break_ctl = mxs_auart_break_ctl,
821 .set_mctrl = mxs_auart_set_mctrl,
822 .get_mctrl = mxs_auart_get_mctrl,
823 .startup = mxs_auart_startup,
824 .shutdown = mxs_auart_shutdown,
825 .set_termios = mxs_auart_settermios,
826 .type = mxs_auart_type,
827 .release_port = mxs_auart_release_port,
828 .request_port = mxs_auart_request_port,
829 .config_port = mxs_auart_config_port,
830 .verify_port = mxs_auart_verify_port,
831};
832
833static struct mxs_auart_port *auart_port[MXS_AUART_PORTS];
834
835#ifdef CONFIG_SERIAL_MXS_AUART_CONSOLE
836static void mxs_auart_console_putchar(struct uart_port *port, int ch)
837{
838 unsigned int to = 1000;
839
840 while (readl(port->membase + AUART_STAT) & AUART_STAT_TXFF) {
841 if (!to--)
842 break;
843 udelay(1);
844 }
845
846 writel(ch, port->membase + AUART_DATA);
847}
848
849static void
850auart_console_write(struct console *co, const char *str, unsigned int count)
851{
852 struct mxs_auart_port *s;
853 struct uart_port *port;
854 unsigned int old_ctrl0, old_ctrl2;
079a036f 855 unsigned int to = 20000;
47d37d6f 856
4829e765 857 if (co->index >= MXS_AUART_PORTS || co->index < 0)
47d37d6f
SH		 858 return;
859
860 s = auart_port[co->index];
861 port = &s->port;
862
863 clk_enable(s->clk);
864
865 /* First save the CR then disable the interrupts */
866 old_ctrl2 = readl(port->membase + AUART_CTRL2);
867 old_ctrl0 = readl(port->membase + AUART_CTRL0);
868
869 writel(AUART_CTRL0_CLKGATE,
870 port->membase + AUART_CTRL0_CLR);
871 writel(AUART_CTRL2_UARTEN | AUART_CTRL2_TXE,
872 port->membase + AUART_CTRL2_SET);
873
874 uart_console_write(port, str, count, mxs_auart_console_putchar);
875
079a036f 876 /* Finally, wait for transmitter to become empty ... */
47d37d6f 877 while (readl(port->membase + AUART_STAT) & AUART_STAT_BUSY) {
079a036f 878 udelay(1);
47d37d6f
SH		 879 if (!to--)
880 break;
47d37d6f
SH		 881 }
882
079a036f
UKK		 883 /*
884 * ... and restore the TCR if we waited long enough for the transmitter
885 * to be idle. This might keep the transmitter enabled although it is
886 * unused, but that is better than to disable it while it is still
887 * transmitting.
888 */
889 if (!(readl(port->membase + AUART_STAT) & AUART_STAT_BUSY)) {
890 writel(old_ctrl0, port->membase + AUART_CTRL0);
891 writel(old_ctrl2, port->membase + AUART_CTRL2);
892 }
47d37d6f
SH		 893
894 clk_disable(s->clk);
895}
896
897static void __init
898auart_console_get_options(struct uart_port *port, int *baud,
899 int *parity, int *bits)
900{
901 unsigned int lcr_h, quot;
902
903 if (!(readl(port->membase + AUART_CTRL2) & AUART_CTRL2_UARTEN))
904 return;
905
906 lcr_h = readl(port->membase + AUART_LINECTRL);
907
908 *parity = 'n';
909 if (lcr_h & AUART_LINECTRL_PEN) {
910 if (lcr_h & AUART_LINECTRL_EPS)
911 *parity = 'e';
912 else
913 *parity = 'o';
914 }
915
916 if ((lcr_h & AUART_LINECTRL_WLEN_MASK) == AUART_LINECTRL_WLEN(2))
917 *bits = 7;
918 else
919 *bits = 8;
920
921 quot = ((readl(port->membase + AUART_LINECTRL)
922 & AUART_LINECTRL_BAUD_DIVINT_MASK))
923 >> (AUART_LINECTRL_BAUD_DIVINT_SHIFT - 6);
924 quot |= ((readl(port->membase + AUART_LINECTRL)
925 & AUART_LINECTRL_BAUD_DIVFRAC_MASK))
926 >> AUART_LINECTRL_BAUD_DIVFRAC_SHIFT;
927 if (quot == 0)
928 quot = 1;
929
930 *baud = (port->uartclk << 2) / quot;
931}
932
933static int __init
934auart_console_setup(struct console *co, char *options)
935{
936 struct mxs_auart_port *s;
937 int baud = 9600;
938 int bits = 8;
939 int parity = 'n';
940 int flow = 'n';
941 int ret;
942
943 /*
944 * Check whether an invalid uart number has been specified, and
945 * if so, search for the first available port that does have
946 * console support.
947 */
948 if (co->index == -1 || co->index >= ARRAY_SIZE(auart_port))
949 co->index = 0;
950 s = auart_port[co->index];
951 if (!s)
952 return -ENODEV;
953
a4813770 954 clk_prepare_enable(s->clk);
47d37d6f
SH		 955
956 if (options)
957 uart_parse_options(options, &baud, &parity, &bits, &flow);
958 else
959 auart_console_get_options(&s->port, &baud, &parity, &bits);
960
961 ret = uart_set_options(&s->port, co, baud, parity, bits, flow);
962
a4813770 963 clk_disable_unprepare(s->clk);
47d37d6f
SH		 964
965 return ret;
966}
967
968static struct console auart_console = {
969 .name = "ttyAPP",
970 .write = auart_console_write,
971 .device = uart_console_device,
972 .setup = auart_console_setup,
973 .flags = CON_PRINTBUFFER,
974 .index = -1,
975 .data = &auart_driver,
976};
977#endif
978
979static struct uart_driver auart_driver = {
980 .owner = THIS_MODULE,
981 .driver_name = "ttyAPP",
982 .dev_name = "ttyAPP",
983 .major = 0,
984 .minor = 0,
985 .nr = MXS_AUART_PORTS,
986#ifdef CONFIG_SERIAL_MXS_AUART_CONSOLE
987 .cons = &auart_console,
988#endif
989};
990
1ea6607d
FE		 991/*
992 * This function returns 1 if pdev isn't a device instatiated by dt, 0 if it
993 * could successfully get all information from dt or a negative errno.
994 */
995static int serial_mxs_probe_dt(struct mxs_auart_port *s,
996 struct platform_device *pdev)
997{
998 struct device_node *np = pdev->dev.of_node;
999 int ret;
1000
1001 if (!np)
1002 /* no device tree device */
1003 return 1;
1004
1005 ret = of_alias_get_id(np, "serial");
1006 if (ret < 0) {
1007 dev_err(&pdev->dev, "failed to get alias id: %d\n", ret);
1008 return ret;
1009 }
1010 s->port.line = ret;
1011
bcc20f9e 1012 s->flags |= MXS_AUART_DMA_CONFIG;
e8001632 1013
8418e67d
HS		 1014 if (of_get_property(np, "fsl,uart-has-rtscts", NULL))
1015 set_bit(MXS_AUART_RTSCTS, &s->flags);
1016
1ea6607d
FE		 1017 return 0;
1018}
1019
9671f099 1020static int mxs_auart_probe(struct platform_device *pdev)
47d37d6f 1021{
f4b1f03b
HS		 1022 const struct of_device_id *of_id =
1023 of_match_device(mxs_auart_dt_ids, &pdev->dev);
47d37d6f
SH		 1024 struct mxs_auart_port *s;
1025 u32 version;
1026 int ret = 0;
1027 struct resource *r;
1028
1029 s = kzalloc(sizeof(struct mxs_auart_port), GFP_KERNEL);
1030 if (!s) {
1031 ret = -ENOMEM;
1032 goto out;
1033 }
1034
1ea6607d
FE		 1035 ret = serial_mxs_probe_dt(s, pdev);
1036 if (ret > 0)
1037 s->port.line = pdev->id < 0 ? 0 : pdev->id;
1038 else if (ret < 0)
1039 goto out_free;
1040
f4b1f03b
HS		 1041 if (of_id) {
1042 pdev->id_entry = of_id->data;
1043 s->devtype = pdev->id_entry->driver_data;
1044 }
1045
47d37d6f
SH		 1046 s->clk = clk_get(&pdev->dev, NULL);
1047 if (IS_ERR(s->clk)) {
1048 ret = PTR_ERR(s->clk);
1049 goto out_free;
1050 }
1051
1052 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1053 if (!r) {
1054 ret = -ENXIO;
1055 goto out_free_clk;
1056 }
1057
1058 s->port.mapbase = r->start;
1059 s->port.membase = ioremap(r->start, resource_size(r));
1060 s->port.ops = &mxs_auart_ops;
1061 s->port.iotype = UPIO_MEM;
47d37d6f
SH		 1062 s->port.fifosize = 16;
1063 s->port.uartclk = clk_get_rate(s->clk);
1064 s->port.type = PORT_IMX;
4c24f2c9 1065 s->port.dev = s->dev = &pdev->dev;
47d37d6f 1066
47d37d6f
SH		 1067 s->ctrl = 0;
1068
1069 s->irq = platform_get_irq(pdev, 0);
1070 s->port.irq = s->irq;
1071 ret = request_irq(s->irq, mxs_auart_irq_handle, 0, dev_name(&pdev->dev), s);
1072 if (ret)
1073 goto out_free_clk;
1074
1075 platform_set_drvdata(pdev, s);
1076
1ea6607d 1077 auart_port[s->port.line] = s;
47d37d6f
SH		 1078
1079 mxs_auart_reset(&s->port);
1080
1081 ret = uart_add_one_port(&auart_driver, &s->port);
1082 if (ret)
1083 goto out_free_irq;
1084
1085 version = readl(s->port.membase + AUART_VERSION);
1086 dev_info(&pdev->dev, "Found APPUART %d.%d.%d\n",
1087 (version >> 24) & 0xff,
1088 (version >> 16) & 0xff, version & 0xffff);
1089
1090 return 0;
1091
1092out_free_irq:
1093 auart_port[pdev->id] = NULL;
1094 free_irq(s->irq, s);
1095out_free_clk:
1096 clk_put(s->clk);
1097out_free:
1098 kfree(s);
1099out:
1100 return ret;
1101}
1102
ae8d8a14 1103static int mxs_auart_remove(struct platform_device *pdev)
47d37d6f
SH		 1104{
1105 struct mxs_auart_port *s = platform_get_drvdata(pdev);
1106
1107 uart_remove_one_port(&auart_driver, &s->port);
1108
1109 auart_port[pdev->id] = NULL;
1110
1111 clk_put(s->clk);
1112 free_irq(s->irq, s);
1113 kfree(s);
1114
1115 return 0;
1116}
1117
1118static struct platform_driver mxs_auart_driver = {
1119 .probe = mxs_auart_probe,
2d47b716 1120 .remove = mxs_auart_remove,
47d37d6f
SH		 1121 .driver = {
1122 .name = "mxs-auart",
1123 .owner = THIS_MODULE,
1ea6607d 1124 .of_match_table = mxs_auart_dt_ids,
47d37d6f
SH		 1125 },
1126};
1127
1128static int __init mxs_auart_init(void)
1129{
1130 int r;
1131
1132 r = uart_register_driver(&auart_driver);
1133 if (r)
1134 goto out;
1135
1136 r = platform_driver_register(&mxs_auart_driver);
1137 if (r)
1138 goto out_err;
1139
1140 return 0;
1141out_err:
1142 uart_unregister_driver(&auart_driver);
1143out:
1144 return r;
1145}
1146
1147static void __exit mxs_auart_exit(void)
1148{
1149 platform_driver_unregister(&mxs_auart_driver);
1150 uart_unregister_driver(&auart_driver);
1151}
1152
1153module_init(mxs_auart_init);
1154module_exit(mxs_auart_exit);
1155MODULE_LICENSE("GPL");
1156MODULE_DESCRIPTION("Freescale MXS application uart driver");
1ea6607d 1157MODULE_ALIAS("platform:mxs-auart");
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