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e3b3d0f5 | 1 | // SPDX-License-Identifier: GPL-2.0+ |
47d37d6f | 2 | /* |
254da0d7 OR |
3 | * Application UART driver for: |
4 | * Freescale STMP37XX/STMP378X | |
5 | * Alphascale ASM9260 | |
47d37d6f SH |
6 | * |
7 | * Author: dmitry pervushin <dimka@embeddedalley.com> | |
8 | * | |
254da0d7 OR |
9 | * Copyright 2014 Oleksij Rempel <linux@rempel-privat.de> |
10 | * Provide Alphascale ASM9260 support. | |
47d37d6f SH |
11 | * Copyright 2008-2010 Freescale Semiconductor, Inc. |
12 | * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. | |
47d37d6f SH |
13 | */ |
14 | ||
914d3b17 JU |
15 | #if defined(CONFIG_SERIAL_MXS_AUART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) |
16 | #define SUPPORT_SYSRQ | |
17 | #endif | |
18 | ||
47d37d6f | 19 | #include <linux/kernel.h> |
47d37d6f SH |
20 | #include <linux/errno.h> |
21 | #include <linux/init.h> | |
22 | #include <linux/console.h> | |
23 | #include <linux/interrupt.h> | |
24 | #include <linux/module.h> | |
25 | #include <linux/slab.h> | |
26 | #include <linux/wait.h> | |
27 | #include <linux/tty.h> | |
28 | #include <linux/tty_driver.h> | |
29 | #include <linux/tty_flip.h> | |
30 | #include <linux/serial.h> | |
31 | #include <linux/serial_core.h> | |
32 | #include <linux/platform_device.h> | |
33 | #include <linux/device.h> | |
34 | #include <linux/clk.h> | |
35 | #include <linux/delay.h> | |
36 | #include <linux/io.h> | |
1ea6607d | 37 | #include <linux/of_device.h> |
e8001632 | 38 | #include <linux/dma-mapping.h> |
bcc20f9e | 39 | #include <linux/dmaengine.h> |
47d37d6f SH |
40 | |
41 | #include <asm/cacheflush.h> | |
42 | ||
f9e42397 | 43 | #include <linux/gpio/consumer.h> |
7c573d7e | 44 | #include <linux/err.h> |
f9e42397 | 45 | #include <linux/irq.h> |
7c573d7e JU |
46 | #include "serial_mctrl_gpio.h" |
47 | ||
47d37d6f | 48 | #define MXS_AUART_PORTS 5 |
9987f76a | 49 | #define MXS_AUART_FIFO_SIZE 16 |
47d37d6f | 50 | |
254da0d7 OR |
51 | #define SET_REG 0x4 |
52 | #define CLR_REG 0x8 | |
53 | #define TOG_REG 0xc | |
54 | ||
47d37d6f | 55 | #define AUART_CTRL0 0x00000000 |
47d37d6f | 56 | #define AUART_CTRL1 0x00000010 |
47d37d6f | 57 | #define AUART_CTRL2 0x00000020 |
47d37d6f | 58 | #define AUART_LINECTRL 0x00000030 |
47d37d6f | 59 | #define AUART_LINECTRL2 0x00000040 |
47d37d6f | 60 | #define AUART_INTR 0x00000050 |
47d37d6f SH |
61 | #define AUART_DATA 0x00000060 |
62 | #define AUART_STAT 0x00000070 | |
63 | #define AUART_DEBUG 0x00000080 | |
64 | #define AUART_VERSION 0x00000090 | |
65 | #define AUART_AUTOBAUD 0x000000a0 | |
66 | ||
67 | #define AUART_CTRL0_SFTRST (1 << 31) | |
68 | #define AUART_CTRL0_CLKGATE (1 << 30) | |
e8001632 HS |
69 | #define AUART_CTRL0_RXTO_ENABLE (1 << 27) |
70 | #define AUART_CTRL0_RXTIMEOUT(v) (((v) & 0x7ff) << 16) | |
71 | #define AUART_CTRL0_XFER_COUNT(v) ((v) & 0xffff) | |
72 | ||
73 | #define AUART_CTRL1_XFER_COUNT(v) ((v) & 0xffff) | |
74 | ||
75 | #define AUART_CTRL2_DMAONERR (1 << 26) | |
76 | #define AUART_CTRL2_TXDMAE (1 << 25) | |
77 | #define AUART_CTRL2_RXDMAE (1 << 24) | |
47d37d6f SH |
78 | |
79 | #define AUART_CTRL2_CTSEN (1 << 15) | |
00592021 | 80 | #define AUART_CTRL2_RTSEN (1 << 14) |
47d37d6f SH |
81 | #define AUART_CTRL2_RTS (1 << 11) |
82 | #define AUART_CTRL2_RXE (1 << 9) | |
83 | #define AUART_CTRL2_TXE (1 << 8) | |
84 | #define AUART_CTRL2_UARTEN (1 << 0) | |
85 | ||
df57cf6a SW |
86 | #define AUART_LINECTRL_BAUD_DIV_MAX 0x003fffc0 |
87 | #define AUART_LINECTRL_BAUD_DIV_MIN 0x000000ec | |
47d37d6f SH |
88 | #define AUART_LINECTRL_BAUD_DIVINT_SHIFT 16 |
89 | #define AUART_LINECTRL_BAUD_DIVINT_MASK 0xffff0000 | |
90 | #define AUART_LINECTRL_BAUD_DIVINT(v) (((v) & 0xffff) << 16) | |
91 | #define AUART_LINECTRL_BAUD_DIVFRAC_SHIFT 8 | |
92 | #define AUART_LINECTRL_BAUD_DIVFRAC_MASK 0x00003f00 | |
93 | #define AUART_LINECTRL_BAUD_DIVFRAC(v) (((v) & 0x3f) << 8) | |
f87fa71e | 94 | #define AUART_LINECTRL_SPS (1 << 7) |
47d37d6f SH |
95 | #define AUART_LINECTRL_WLEN_MASK 0x00000060 |
96 | #define AUART_LINECTRL_WLEN(v) (((v) & 0x3) << 5) | |
97 | #define AUART_LINECTRL_FEN (1 << 4) | |
98 | #define AUART_LINECTRL_STP2 (1 << 3) | |
99 | #define AUART_LINECTRL_EPS (1 << 2) | |
100 | #define AUART_LINECTRL_PEN (1 << 1) | |
101 | #define AUART_LINECTRL_BRK (1 << 0) | |
102 | ||
103 | #define AUART_INTR_RTIEN (1 << 22) | |
104 | #define AUART_INTR_TXIEN (1 << 21) | |
105 | #define AUART_INTR_RXIEN (1 << 20) | |
106 | #define AUART_INTR_CTSMIEN (1 << 17) | |
107 | #define AUART_INTR_RTIS (1 << 6) | |
108 | #define AUART_INTR_TXIS (1 << 5) | |
109 | #define AUART_INTR_RXIS (1 << 4) | |
110 | #define AUART_INTR_CTSMIS (1 << 1) | |
111 | ||
112 | #define AUART_STAT_BUSY (1 << 29) | |
113 | #define AUART_STAT_CTS (1 << 28) | |
114 | #define AUART_STAT_TXFE (1 << 27) | |
115 | #define AUART_STAT_TXFF (1 << 25) | |
116 | #define AUART_STAT_RXFE (1 << 24) | |
117 | #define AUART_STAT_OERR (1 << 19) | |
118 | #define AUART_STAT_BERR (1 << 18) | |
119 | #define AUART_STAT_PERR (1 << 17) | |
120 | #define AUART_STAT_FERR (1 << 16) | |
e8001632 | 121 | #define AUART_STAT_RXCOUNT_MASK 0xffff |
47d37d6f | 122 | |
254da0d7 OR |
123 | /* |
124 | * Start of Alphascale asm9260 defines | |
125 | * This list contains only differences of existing bits | |
126 | * between imx2x and asm9260 | |
127 | */ | |
128 | #define ASM9260_HW_CTRL0 0x0000 | |
129 | /* | |
130 | * RW. Tell the UART to execute the RX DMA Command. The | |
131 | * UART will clear this bit at the end of receive execution. | |
132 | */ | |
133 | #define ASM9260_BM_CTRL0_RXDMA_RUN BIT(28) | |
134 | /* RW. 0 use FIFO for status register; 1 use DMA */ | |
135 | #define ASM9260_BM_CTRL0_RXTO_SOURCE_STATUS BIT(25) | |
136 | /* | |
137 | * RW. RX TIMEOUT Enable. Valid for FIFO and DMA. | |
138 | * Warning: If this bit is set to 0, the RX timeout will not affect receive DMA | |
139 | * operation. If this bit is set to 1, a receive timeout will cause the receive | |
140 | * DMA logic to terminate by filling the remaining DMA bytes with garbage data. | |
141 | */ | |
142 | #define ASM9260_BM_CTRL0_RXTO_ENABLE BIT(24) | |
143 | /* | |
144 | * RW. Receive Timeout Counter Value: number of 8-bit-time to wait before | |
145 | * asserting timeout on the RX input. If the RXFIFO is not empty and the RX | |
146 | * input is idle, then the watchdog counter will decrement each bit-time. Note | |
147 | * 7-bit-time is added to the programmed value, so a value of zero will set | |
148 | * the counter to 7-bit-time, a value of 0x1 gives 15-bit-time and so on. Also | |
149 | * note that the counter is reloaded at the end of each frame, so if the frame | |
150 | * is 10 bits long and the timeout counter value is zero, then timeout will | |
151 | * occur (when FIFO is not empty) even if the RX input is not idle. The default | |
152 | * value is 0x3 (31 bit-time). | |
153 | */ | |
154 | #define ASM9260_BM_CTRL0_RXTO_MASK (0xff << 16) | |
155 | /* TIMEOUT = (100*7+1)*(1/BAUD) */ | |
156 | #define ASM9260_BM_CTRL0_DEFAULT_RXTIMEOUT (20 << 16) | |
157 | ||
158 | /* TX ctrl register */ | |
159 | #define ASM9260_HW_CTRL1 0x0010 | |
160 | /* | |
161 | * RW. Tell the UART to execute the TX DMA Command. The | |
162 | * UART will clear this bit at the end of transmit execution. | |
163 | */ | |
164 | #define ASM9260_BM_CTRL1_TXDMA_RUN BIT(28) | |
165 | ||
166 | #define ASM9260_HW_CTRL2 0x0020 | |
167 | /* | |
168 | * RW. Receive Interrupt FIFO Level Select. | |
169 | * The trigger points for the receive interrupt are as follows: | |
170 | * ONE_EIGHTHS = 0x0 Trigger on FIFO full to at least 2 of 16 entries. | |
171 | * ONE_QUARTER = 0x1 Trigger on FIFO full to at least 4 of 16 entries. | |
172 | * ONE_HALF = 0x2 Trigger on FIFO full to at least 8 of 16 entries. | |
173 | * THREE_QUARTERS = 0x3 Trigger on FIFO full to at least 12 of 16 entries. | |
174 | * SEVEN_EIGHTHS = 0x4 Trigger on FIFO full to at least 14 of 16 entries. | |
175 | */ | |
176 | #define ASM9260_BM_CTRL2_RXIFLSEL (7 << 20) | |
177 | #define ASM9260_BM_CTRL2_DEFAULT_RXIFLSEL (3 << 20) | |
178 | /* RW. Same as RXIFLSEL */ | |
179 | #define ASM9260_BM_CTRL2_TXIFLSEL (7 << 16) | |
180 | #define ASM9260_BM_CTRL2_DEFAULT_TXIFLSEL (2 << 16) | |
181 | /* RW. Set DTR. When this bit is 1, the output is 0. */ | |
182 | #define ASM9260_BM_CTRL2_DTR BIT(10) | |
183 | /* RW. Loop Back Enable */ | |
184 | #define ASM9260_BM_CTRL2_LBE BIT(7) | |
185 | #define ASM9260_BM_CTRL2_PORT_ENABLE BIT(0) | |
186 | ||
187 | #define ASM9260_HW_LINECTRL 0x0030 | |
188 | /* | |
189 | * RW. Stick Parity Select. When bits 1, 2, and 7 of this register are set, the | |
190 | * parity bit is transmitted and checked as a 0. When bits 1 and 7 are set, | |
191 | * and bit 2 is 0, the parity bit is transmitted and checked as a 1. When this | |
192 | * bit is cleared stick parity is disabled. | |
193 | */ | |
194 | #define ASM9260_BM_LCTRL_SPS BIT(7) | |
195 | /* RW. Word length */ | |
196 | #define ASM9260_BM_LCTRL_WLEN (3 << 5) | |
197 | #define ASM9260_BM_LCTRL_CHRL_5 (0 << 5) | |
198 | #define ASM9260_BM_LCTRL_CHRL_6 (1 << 5) | |
199 | #define ASM9260_BM_LCTRL_CHRL_7 (2 << 5) | |
200 | #define ASM9260_BM_LCTRL_CHRL_8 (3 << 5) | |
201 | ||
202 | /* | |
203 | * Interrupt register. | |
204 | * contains the interrupt enables and the interrupt status bits | |
205 | */ | |
206 | #define ASM9260_HW_INTR 0x0040 | |
207 | /* Tx FIFO EMPTY Raw Interrupt enable */ | |
208 | #define ASM9260_BM_INTR_TFEIEN BIT(27) | |
209 | /* Overrun Error Interrupt Enable. */ | |
210 | #define ASM9260_BM_INTR_OEIEN BIT(26) | |
211 | /* Break Error Interrupt Enable. */ | |
212 | #define ASM9260_BM_INTR_BEIEN BIT(25) | |
213 | /* Parity Error Interrupt Enable. */ | |
214 | #define ASM9260_BM_INTR_PEIEN BIT(24) | |
215 | /* Framing Error Interrupt Enable. */ | |
216 | #define ASM9260_BM_INTR_FEIEN BIT(23) | |
217 | ||
218 | /* nUARTDSR Modem Interrupt Enable. */ | |
219 | #define ASM9260_BM_INTR_DSRMIEN BIT(19) | |
220 | /* nUARTDCD Modem Interrupt Enable. */ | |
221 | #define ASM9260_BM_INTR_DCDMIEN BIT(18) | |
222 | /* nUARTRI Modem Interrupt Enable. */ | |
223 | #define ASM9260_BM_INTR_RIMIEN BIT(16) | |
224 | /* Auto-Boud Timeout */ | |
225 | #define ASM9260_BM_INTR_ABTO BIT(13) | |
226 | #define ASM9260_BM_INTR_ABEO BIT(12) | |
227 | /* Tx FIFO EMPTY Raw Interrupt state */ | |
228 | #define ASM9260_BM_INTR_TFEIS BIT(11) | |
229 | /* Overrun Error */ | |
230 | #define ASM9260_BM_INTR_OEIS BIT(10) | |
231 | /* Break Error */ | |
232 | #define ASM9260_BM_INTR_BEIS BIT(9) | |
233 | /* Parity Error */ | |
234 | #define ASM9260_BM_INTR_PEIS BIT(8) | |
235 | /* Framing Error */ | |
236 | #define ASM9260_BM_INTR_FEIS BIT(7) | |
237 | #define ASM9260_BM_INTR_DSRMIS BIT(3) | |
238 | #define ASM9260_BM_INTR_DCDMIS BIT(2) | |
239 | #define ASM9260_BM_INTR_RIMIS BIT(0) | |
240 | ||
241 | /* | |
242 | * RW. In DMA mode, up to 4 Received/Transmit characters can be accessed at a | |
243 | * time. In PIO mode, only one character can be accessed at a time. The status | |
244 | * register contains the receive data flags and valid bits. | |
245 | */ | |
246 | #define ASM9260_HW_DATA 0x0050 | |
247 | ||
248 | #define ASM9260_HW_STAT 0x0060 | |
249 | /* RO. If 1, UARTAPP is present in this product. */ | |
250 | #define ASM9260_BM_STAT_PRESENT BIT(31) | |
251 | /* RO. If 1, HISPEED is present in this product. */ | |
252 | #define ASM9260_BM_STAT_HISPEED BIT(30) | |
253 | /* RO. Receive FIFO Full. */ | |
254 | #define ASM9260_BM_STAT_RXFULL BIT(26) | |
255 | ||
256 | /* RO. The UART Debug Register contains the state of the DMA signals. */ | |
257 | #define ASM9260_HW_DEBUG 0x0070 | |
258 | /* DMA Command Run Status */ | |
259 | #define ASM9260_BM_DEBUG_TXDMARUN BIT(5) | |
260 | #define ASM9260_BM_DEBUG_RXDMARUN BIT(4) | |
261 | /* DMA Command End Status */ | |
262 | #define ASM9260_BM_DEBUG_TXCMDEND BIT(3) | |
263 | #define ASM9260_BM_DEBUG_RXCMDEND BIT(2) | |
264 | /* DMA Request Status */ | |
265 | #define ASM9260_BM_DEBUG_TXDMARQ BIT(1) | |
266 | #define ASM9260_BM_DEBUG_RXDMARQ BIT(0) | |
267 | ||
268 | #define ASM9260_HW_ILPR 0x0080 | |
269 | ||
270 | #define ASM9260_HW_RS485CTRL 0x0090 | |
271 | /* | |
272 | * RW. This bit reverses the polarity of the direction control signal on the RTS | |
273 | * (or DTR) pin. | |
274 | * If 0, The direction control pin will be driven to logic ‘0’ when the | |
275 | * transmitter has data to be sent. It will be driven to logic ‘1’ after the | |
276 | * last bit of data has been transmitted. | |
277 | */ | |
278 | #define ASM9260_BM_RS485CTRL_ONIV BIT(5) | |
279 | /* RW. Enable Auto Direction Control. */ | |
280 | #define ASM9260_BM_RS485CTRL_DIR_CTRL BIT(4) | |
281 | /* | |
282 | * RW. If 0 and DIR_CTRL = 1, pin RTS is used for direction control. | |
283 | * If 1 and DIR_CTRL = 1, pin DTR is used for direction control. | |
284 | */ | |
285 | #define ASM9260_BM_RS485CTRL_PINSEL BIT(3) | |
286 | /* RW. Enable Auto Address Detect (AAD). */ | |
287 | #define ASM9260_BM_RS485CTRL_AADEN BIT(2) | |
288 | /* RW. Disable receiver. */ | |
289 | #define ASM9260_BM_RS485CTRL_RXDIS BIT(1) | |
290 | /* RW. Enable RS-485/EIA-485 Normal Multidrop Mode (NMM) */ | |
291 | #define ASM9260_BM_RS485CTRL_RS485EN BIT(0) | |
292 | ||
293 | #define ASM9260_HW_RS485ADRMATCH 0x00a0 | |
294 | /* Contains the address match value. */ | |
295 | #define ASM9260_BM_RS485ADRMATCH_MASK (0xff << 0) | |
296 | ||
297 | #define ASM9260_HW_RS485DLY 0x00b0 | |
298 | /* | |
299 | * RW. Contains the direction control (RTS or DTR) delay value. This delay time | |
300 | * is in periods of the baud clock. | |
301 | */ | |
302 | #define ASM9260_BM_RS485DLY_MASK (0xff << 0) | |
303 | ||
304 | #define ASM9260_HW_AUTOBAUD 0x00c0 | |
305 | /* WO. Auto-baud time-out interrupt clear bit. */ | |
306 | #define ASM9260_BM_AUTOBAUD_TO_INT_CLR BIT(9) | |
307 | /* WO. End of auto-baud interrupt clear bit. */ | |
308 | #define ASM9260_BM_AUTOBAUD_EO_INT_CLR BIT(8) | |
309 | /* Restart in case of timeout (counter restarts at next UART Rx falling edge) */ | |
310 | #define ASM9260_BM_AUTOBAUD_AUTORESTART BIT(2) | |
311 | /* Auto-baud mode select bit. 0 - Mode 0, 1 - Mode 1. */ | |
312 | #define ASM9260_BM_AUTOBAUD_MODE BIT(1) | |
313 | /* | |
314 | * Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is | |
315 | * automatically cleared after auto-baud completion. | |
316 | */ | |
317 | #define ASM9260_BM_AUTOBAUD_START BIT(0) | |
318 | ||
319 | #define ASM9260_HW_CTRL3 0x00d0 | |
320 | #define ASM9260_BM_CTRL3_OUTCLK_DIV_MASK (0xffff << 16) | |
321 | /* | |
322 | * RW. Provide clk over OUTCLK pin. In case of asm9260 it can be configured on | |
323 | * pins 137 and 144. | |
324 | */ | |
325 | #define ASM9260_BM_CTRL3_MASTERMODE BIT(6) | |
326 | /* RW. Baud Rate Mode: 1 - Enable sync mode. 0 - async mode. */ | |
327 | #define ASM9260_BM_CTRL3_SYNCMODE BIT(4) | |
328 | /* RW. 1 - MSB bit send frist; 0 - LSB bit frist. */ | |
329 | #define ASM9260_BM_CTRL3_MSBF BIT(2) | |
330 | /* RW. 1 - sample rate = 8 x Baudrate; 0 - sample rate = 16 x Baudrate. */ | |
331 | #define ASM9260_BM_CTRL3_BAUD8 BIT(1) | |
332 | /* RW. 1 - Set word length to 9bit. 0 - use ASM9260_BM_LCTRL_WLEN */ | |
333 | #define ASM9260_BM_CTRL3_9BIT BIT(0) | |
334 | ||
335 | #define ASM9260_HW_ISO7816_CTRL 0x00e0 | |
336 | /* RW. Enable High Speed mode. */ | |
337 | #define ASM9260_BM_ISO7816CTRL_HS BIT(12) | |
338 | /* Disable Successive Receive NACK */ | |
339 | #define ASM9260_BM_ISO7816CTRL_DS_NACK BIT(8) | |
340 | #define ASM9260_BM_ISO7816CTRL_MAX_ITER_MASK (0xff << 4) | |
341 | /* Receive NACK Inhibit */ | |
342 | #define ASM9260_BM_ISO7816CTRL_INACK BIT(3) | |
343 | #define ASM9260_BM_ISO7816CTRL_NEG_DATA BIT(2) | |
344 | /* RW. 1 - ISO7816 mode; 0 - USART mode */ | |
345 | #define ASM9260_BM_ISO7816CTRL_ENABLE BIT(0) | |
346 | ||
347 | #define ASM9260_HW_ISO7816_ERRCNT 0x00f0 | |
348 | /* Parity error counter. Will be cleared after reading */ | |
349 | #define ASM9260_BM_ISO7816_NB_ERRORS_MASK (0xff << 0) | |
350 | ||
351 | #define ASM9260_HW_ISO7816_STATUS 0x0100 | |
352 | /* Max number of Repetitions Reached */ | |
353 | #define ASM9260_BM_ISO7816_STAT_ITERATION BIT(0) | |
354 | ||
355 | /* End of Alphascale asm9260 defines */ | |
356 | ||
47d37d6f SH |
357 | static struct uart_driver auart_driver; |
358 | ||
f4b1f03b HS |
359 | enum mxs_auart_type { |
360 | IMX23_AUART, | |
361 | IMX28_AUART, | |
254da0d7 OR |
362 | ASM9260_AUART, |
363 | }; | |
364 | ||
365 | struct vendor_data { | |
366 | const u16 *reg_offset; | |
367 | }; | |
368 | ||
369 | enum { | |
370 | REG_CTRL0, | |
371 | REG_CTRL1, | |
372 | REG_CTRL2, | |
373 | REG_LINECTRL, | |
374 | REG_LINECTRL2, | |
375 | REG_INTR, | |
376 | REG_DATA, | |
377 | REG_STAT, | |
378 | REG_DEBUG, | |
379 | REG_VERSION, | |
380 | REG_AUTOBAUD, | |
381 | ||
382 | /* The size of the array - must be last */ | |
383 | REG_ARRAY_SIZE, | |
384 | }; | |
385 | ||
386 | static const u16 mxs_asm9260_offsets[REG_ARRAY_SIZE] = { | |
387 | [REG_CTRL0] = ASM9260_HW_CTRL0, | |
388 | [REG_CTRL1] = ASM9260_HW_CTRL1, | |
389 | [REG_CTRL2] = ASM9260_HW_CTRL2, | |
390 | [REG_LINECTRL] = ASM9260_HW_LINECTRL, | |
391 | [REG_INTR] = ASM9260_HW_INTR, | |
392 | [REG_DATA] = ASM9260_HW_DATA, | |
393 | [REG_STAT] = ASM9260_HW_STAT, | |
394 | [REG_DEBUG] = ASM9260_HW_DEBUG, | |
395 | [REG_AUTOBAUD] = ASM9260_HW_AUTOBAUD, | |
396 | }; | |
397 | ||
398 | static const u16 mxs_stmp37xx_offsets[REG_ARRAY_SIZE] = { | |
399 | [REG_CTRL0] = AUART_CTRL0, | |
400 | [REG_CTRL1] = AUART_CTRL1, | |
401 | [REG_CTRL2] = AUART_CTRL2, | |
402 | [REG_LINECTRL] = AUART_LINECTRL, | |
403 | [REG_LINECTRL2] = AUART_LINECTRL2, | |
404 | [REG_INTR] = AUART_INTR, | |
405 | [REG_DATA] = AUART_DATA, | |
406 | [REG_STAT] = AUART_STAT, | |
407 | [REG_DEBUG] = AUART_DEBUG, | |
408 | [REG_VERSION] = AUART_VERSION, | |
409 | [REG_AUTOBAUD] = AUART_AUTOBAUD, | |
410 | }; | |
411 | ||
412 | static const struct vendor_data vendor_alphascale_asm9260 = { | |
413 | .reg_offset = mxs_asm9260_offsets, | |
414 | }; | |
415 | ||
416 | static const struct vendor_data vendor_freescale_stmp37xx = { | |
417 | .reg_offset = mxs_stmp37xx_offsets, | |
f4b1f03b HS |
418 | }; |
419 | ||
47d37d6f SH |
420 | struct mxs_auart_port { |
421 | struct uart_port port; | |
422 | ||
e8001632 HS |
423 | #define MXS_AUART_DMA_ENABLED 0x2 |
424 | #define MXS_AUART_DMA_TX_SYNC 2 /* bit 2 */ | |
425 | #define MXS_AUART_DMA_RX_READY 3 /* bit 3 */ | |
8418e67d | 426 | #define MXS_AUART_RTSCTS 4 /* bit 4 */ |
e8001632 | 427 | unsigned long flags; |
f9e42397 | 428 | unsigned int mctrl_prev; |
f4b1f03b | 429 | enum mxs_auart_type devtype; |
254da0d7 | 430 | const struct vendor_data *vendor; |
47d37d6f | 431 | |
47d37d6f | 432 | struct clk *clk; |
254da0d7 | 433 | struct clk *clk_ahb; |
47d37d6f | 434 | struct device *dev; |
e8001632 HS |
435 | |
436 | /* for DMA */ | |
e8001632 HS |
437 | struct scatterlist tx_sgl; |
438 | struct dma_chan *tx_dma_chan; | |
439 | void *tx_dma_buf; | |
440 | ||
441 | struct scatterlist rx_sgl; | |
442 | struct dma_chan *rx_dma_chan; | |
443 | void *rx_dma_buf; | |
7c573d7e JU |
444 | |
445 | struct mctrl_gpios *gpios; | |
f9e42397 JU |
446 | int gpio_irq[UART_GPIO_MAX]; |
447 | bool ms_irq_enabled; | |
47d37d6f SH |
448 | }; |
449 | ||
0cd4521f | 450 | static const struct platform_device_id mxs_auart_devtype[] = { |
f4b1f03b HS |
451 | { .name = "mxs-auart-imx23", .driver_data = IMX23_AUART }, |
452 | { .name = "mxs-auart-imx28", .driver_data = IMX28_AUART }, | |
254da0d7 | 453 | { .name = "as-auart-asm9260", .driver_data = ASM9260_AUART }, |
f4b1f03b HS |
454 | { /* sentinel */ } |
455 | }; | |
456 | MODULE_DEVICE_TABLE(platform, mxs_auart_devtype); | |
457 | ||
ed0bb232 | 458 | static const struct of_device_id mxs_auart_dt_ids[] = { |
f4b1f03b HS |
459 | { |
460 | .compatible = "fsl,imx28-auart", | |
461 | .data = &mxs_auart_devtype[IMX28_AUART] | |
462 | }, { | |
463 | .compatible = "fsl,imx23-auart", | |
464 | .data = &mxs_auart_devtype[IMX23_AUART] | |
254da0d7 OR |
465 | }, { |
466 | .compatible = "alphascale,asm9260-auart", | |
467 | .data = &mxs_auart_devtype[ASM9260_AUART] | |
f4b1f03b HS |
468 | }, { /* sentinel */ } |
469 | }; | |
470 | MODULE_DEVICE_TABLE(of, mxs_auart_dt_ids); | |
471 | ||
472 | static inline int is_imx28_auart(struct mxs_auart_port *s) | |
473 | { | |
474 | return s->devtype == IMX28_AUART; | |
475 | } | |
476 | ||
254da0d7 OR |
477 | static inline int is_asm9260_auart(struct mxs_auart_port *s) |
478 | { | |
479 | return s->devtype == ASM9260_AUART; | |
480 | } | |
481 | ||
e8001632 HS |
482 | static inline bool auart_dma_enabled(struct mxs_auart_port *s) |
483 | { | |
484 | return s->flags & MXS_AUART_DMA_ENABLED; | |
485 | } | |
486 | ||
254da0d7 OR |
487 | static unsigned int mxs_reg_to_offset(const struct mxs_auart_port *uap, |
488 | unsigned int reg) | |
489 | { | |
490 | return uap->vendor->reg_offset[reg]; | |
491 | } | |
492 | ||
493 | static unsigned int mxs_read(const struct mxs_auart_port *uap, | |
494 | unsigned int reg) | |
495 | { | |
496 | void __iomem *addr = uap->port.membase + mxs_reg_to_offset(uap, reg); | |
497 | ||
498 | return readl_relaxed(addr); | |
499 | } | |
500 | ||
501 | static void mxs_write(unsigned int val, struct mxs_auart_port *uap, | |
502 | unsigned int reg) | |
503 | { | |
504 | void __iomem *addr = uap->port.membase + mxs_reg_to_offset(uap, reg); | |
505 | ||
506 | writel_relaxed(val, addr); | |
507 | } | |
508 | ||
509 | static void mxs_set(unsigned int val, struct mxs_auart_port *uap, | |
510 | unsigned int reg) | |
511 | { | |
512 | void __iomem *addr = uap->port.membase + mxs_reg_to_offset(uap, reg); | |
513 | ||
514 | writel_relaxed(val, addr + SET_REG); | |
515 | } | |
516 | ||
517 | static void mxs_clr(unsigned int val, struct mxs_auart_port *uap, | |
518 | unsigned int reg) | |
519 | { | |
520 | void __iomem *addr = uap->port.membase + mxs_reg_to_offset(uap, reg); | |
521 | ||
522 | writel_relaxed(val, addr + CLR_REG); | |
523 | } | |
524 | ||
47d37d6f SH |
525 | static void mxs_auart_stop_tx(struct uart_port *u); |
526 | ||
527 | #define to_auart_port(u) container_of(u, struct mxs_auart_port, port) | |
528 | ||
e8001632 HS |
529 | static void mxs_auart_tx_chars(struct mxs_auart_port *s); |
530 | ||
531 | static void dma_tx_callback(void *param) | |
47d37d6f | 532 | { |
e8001632 | 533 | struct mxs_auart_port *s = param; |
47d37d6f SH |
534 | struct circ_buf *xmit = &s->port.state->xmit; |
535 | ||
e8001632 HS |
536 | dma_unmap_sg(s->dev, &s->tx_sgl, 1, DMA_TO_DEVICE); |
537 | ||
538 | /* clear the bit used to serialize the DMA tx. */ | |
539 | clear_bit(MXS_AUART_DMA_TX_SYNC, &s->flags); | |
4e857c58 | 540 | smp_mb__after_atomic(); |
e8001632 HS |
541 | |
542 | /* wake up the possible processes. */ | |
543 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
544 | uart_write_wakeup(&s->port); | |
545 | ||
546 | mxs_auart_tx_chars(s); | |
547 | } | |
548 | ||
549 | static int mxs_auart_dma_tx(struct mxs_auart_port *s, int size) | |
550 | { | |
551 | struct dma_async_tx_descriptor *desc; | |
552 | struct scatterlist *sgl = &s->tx_sgl; | |
553 | struct dma_chan *channel = s->tx_dma_chan; | |
554 | u32 pio; | |
555 | ||
556 | /* [1] : send PIO. Note, the first pio word is CTRL1. */ | |
557 | pio = AUART_CTRL1_XFER_COUNT(size); | |
558 | desc = dmaengine_prep_slave_sg(channel, (struct scatterlist *)&pio, | |
559 | 1, DMA_TRANS_NONE, 0); | |
560 | if (!desc) { | |
561 | dev_err(s->dev, "step 1 error\n"); | |
562 | return -EINVAL; | |
563 | } | |
564 | ||
565 | /* [2] : set DMA buffer. */ | |
566 | sg_init_one(sgl, s->tx_dma_buf, size); | |
567 | dma_map_sg(s->dev, sgl, 1, DMA_TO_DEVICE); | |
568 | desc = dmaengine_prep_slave_sg(channel, sgl, | |
569 | 1, DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
570 | if (!desc) { | |
571 | dev_err(s->dev, "step 2 error\n"); | |
572 | return -EINVAL; | |
573 | } | |
574 | ||
575 | /* [3] : submit the DMA */ | |
576 | desc->callback = dma_tx_callback; | |
577 | desc->callback_param = s; | |
578 | dmaengine_submit(desc); | |
579 | dma_async_issue_pending(channel); | |
580 | return 0; | |
581 | } | |
582 | ||
583 | static void mxs_auart_tx_chars(struct mxs_auart_port *s) | |
584 | { | |
585 | struct circ_buf *xmit = &s->port.state->xmit; | |
586 | ||
587 | if (auart_dma_enabled(s)) { | |
87b8bed2 | 588 | u32 i = 0; |
e8001632 HS |
589 | int size; |
590 | void *buffer = s->tx_dma_buf; | |
591 | ||
592 | if (test_and_set_bit(MXS_AUART_DMA_TX_SYNC, &s->flags)) | |
593 | return; | |
594 | ||
595 | while (!uart_circ_empty(xmit) && !uart_tx_stopped(&s->port)) { | |
596 | size = min_t(u32, UART_XMIT_SIZE - i, | |
597 | CIRC_CNT_TO_END(xmit->head, | |
598 | xmit->tail, | |
599 | UART_XMIT_SIZE)); | |
600 | memcpy(buffer + i, xmit->buf + xmit->tail, size); | |
601 | xmit->tail = (xmit->tail + size) & (UART_XMIT_SIZE - 1); | |
602 | ||
603 | i += size; | |
604 | if (i >= UART_XMIT_SIZE) | |
605 | break; | |
606 | } | |
607 | ||
608 | if (uart_tx_stopped(&s->port)) | |
609 | mxs_auart_stop_tx(&s->port); | |
610 | ||
611 | if (i) { | |
612 | mxs_auart_dma_tx(s, i); | |
613 | } else { | |
614 | clear_bit(MXS_AUART_DMA_TX_SYNC, &s->flags); | |
4e857c58 | 615 | smp_mb__after_atomic(); |
e8001632 HS |
616 | } |
617 | return; | |
618 | } | |
619 | ||
620 | ||
254da0d7 | 621 | while (!(mxs_read(s, REG_STAT) & AUART_STAT_TXFF)) { |
47d37d6f SH |
622 | if (s->port.x_char) { |
623 | s->port.icount.tx++; | |
254da0d7 | 624 | mxs_write(s->port.x_char, s, REG_DATA); |
47d37d6f SH |
625 | s->port.x_char = 0; |
626 | continue; | |
627 | } | |
628 | if (!uart_circ_empty(xmit) && !uart_tx_stopped(&s->port)) { | |
629 | s->port.icount.tx++; | |
254da0d7 | 630 | mxs_write(xmit->buf[xmit->tail], s, REG_DATA); |
47d37d6f | 631 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); |
47d37d6f SH |
632 | } else |
633 | break; | |
634 | } | |
d0758a28 UKK |
635 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) |
636 | uart_write_wakeup(&s->port); | |
637 | ||
47d37d6f | 638 | if (uart_circ_empty(&(s->port.state->xmit))) |
254da0d7 | 639 | mxs_clr(AUART_INTR_TXIEN, s, REG_INTR); |
47d37d6f | 640 | else |
254da0d7 | 641 | mxs_set(AUART_INTR_TXIEN, s, REG_INTR); |
47d37d6f SH |
642 | |
643 | if (uart_tx_stopped(&s->port)) | |
644 | mxs_auart_stop_tx(&s->port); | |
645 | } | |
646 | ||
647 | static void mxs_auart_rx_char(struct mxs_auart_port *s) | |
648 | { | |
649 | int flag; | |
650 | u32 stat; | |
651 | u8 c; | |
652 | ||
254da0d7 OR |
653 | c = mxs_read(s, REG_DATA); |
654 | stat = mxs_read(s, REG_STAT); | |
47d37d6f SH |
655 | |
656 | flag = TTY_NORMAL; | |
657 | s->port.icount.rx++; | |
658 | ||
659 | if (stat & AUART_STAT_BERR) { | |
660 | s->port.icount.brk++; | |
661 | if (uart_handle_break(&s->port)) | |
662 | goto out; | |
663 | } else if (stat & AUART_STAT_PERR) { | |
664 | s->port.icount.parity++; | |
665 | } else if (stat & AUART_STAT_FERR) { | |
666 | s->port.icount.frame++; | |
667 | } | |
668 | ||
669 | /* | |
670 | * Mask off conditions which should be ingored. | |
671 | */ | |
672 | stat &= s->port.read_status_mask; | |
673 | ||
674 | if (stat & AUART_STAT_BERR) { | |
675 | flag = TTY_BREAK; | |
676 | } else if (stat & AUART_STAT_PERR) | |
677 | flag = TTY_PARITY; | |
678 | else if (stat & AUART_STAT_FERR) | |
679 | flag = TTY_FRAME; | |
680 | ||
681 | if (stat & AUART_STAT_OERR) | |
682 | s->port.icount.overrun++; | |
683 | ||
684 | if (uart_handle_sysrq_char(&s->port, c)) | |
685 | goto out; | |
686 | ||
687 | uart_insert_char(&s->port, stat, AUART_STAT_OERR, c, flag); | |
688 | out: | |
254da0d7 | 689 | mxs_write(stat, s, REG_STAT); |
47d37d6f SH |
690 | } |
691 | ||
692 | static void mxs_auart_rx_chars(struct mxs_auart_port *s) | |
693 | { | |
47d37d6f SH |
694 | u32 stat = 0; |
695 | ||
696 | for (;;) { | |
254da0d7 | 697 | stat = mxs_read(s, REG_STAT); |
47d37d6f SH |
698 | if (stat & AUART_STAT_RXFE) |
699 | break; | |
700 | mxs_auart_rx_char(s); | |
701 | } | |
702 | ||
254da0d7 | 703 | mxs_write(stat, s, REG_STAT); |
2e124b4a | 704 | tty_flip_buffer_push(&s->port.state->port); |
47d37d6f SH |
705 | } |
706 | ||
707 | static int mxs_auart_request_port(struct uart_port *u) | |
708 | { | |
709 | return 0; | |
710 | } | |
711 | ||
712 | static int mxs_auart_verify_port(struct uart_port *u, | |
713 | struct serial_struct *ser) | |
714 | { | |
715 | if (u->type != PORT_UNKNOWN && u->type != PORT_IMX) | |
716 | return -EINVAL; | |
717 | return 0; | |
718 | } | |
719 | ||
720 | static void mxs_auart_config_port(struct uart_port *u, int flags) | |
721 | { | |
722 | } | |
723 | ||
724 | static const char *mxs_auart_type(struct uart_port *u) | |
725 | { | |
726 | struct mxs_auart_port *s = to_auart_port(u); | |
727 | ||
728 | return dev_name(s->dev); | |
729 | } | |
730 | ||
731 | static void mxs_auart_release_port(struct uart_port *u) | |
732 | { | |
733 | } | |
734 | ||
735 | static void mxs_auart_set_mctrl(struct uart_port *u, unsigned mctrl) | |
736 | { | |
7c573d7e JU |
737 | struct mxs_auart_port *s = to_auart_port(u); |
738 | ||
254da0d7 | 739 | u32 ctrl = mxs_read(s, REG_CTRL2); |
47d37d6f | 740 | |
a6833214 | 741 | ctrl &= ~(AUART_CTRL2_RTSEN | AUART_CTRL2_RTS); |
00592021 | 742 | if (mctrl & TIOCM_RTS) { |
299245a1 | 743 | if (uart_cts_enabled(u)) |
00592021 | 744 | ctrl |= AUART_CTRL2_RTSEN; |
a6833214 ST |
745 | else |
746 | ctrl |= AUART_CTRL2_RTS; | |
00592021 HS |
747 | } |
748 | ||
254da0d7 | 749 | mxs_write(ctrl, s, REG_CTRL2); |
7c573d7e JU |
750 | |
751 | mctrl_gpio_set(s->gpios, mctrl); | |
47d37d6f SH |
752 | } |
753 | ||
f9e42397 JU |
754 | #define MCTRL_ANY_DELTA (TIOCM_RI | TIOCM_DSR | TIOCM_CD | TIOCM_CTS) |
755 | static u32 mxs_auart_modem_status(struct mxs_auart_port *s, u32 mctrl) | |
756 | { | |
757 | u32 mctrl_diff; | |
758 | ||
759 | mctrl_diff = mctrl ^ s->mctrl_prev; | |
760 | s->mctrl_prev = mctrl; | |
761 | if (mctrl_diff & MCTRL_ANY_DELTA && s->ms_irq_enabled && | |
762 | s->port.state != NULL) { | |
763 | if (mctrl_diff & TIOCM_RI) | |
764 | s->port.icount.rng++; | |
765 | if (mctrl_diff & TIOCM_DSR) | |
766 | s->port.icount.dsr++; | |
767 | if (mctrl_diff & TIOCM_CD) | |
768 | uart_handle_dcd_change(&s->port, mctrl & TIOCM_CD); | |
769 | if (mctrl_diff & TIOCM_CTS) | |
770 | uart_handle_cts_change(&s->port, mctrl & TIOCM_CTS); | |
771 | ||
772 | wake_up_interruptible(&s->port.state->port.delta_msr_wait); | |
773 | } | |
774 | return mctrl; | |
775 | } | |
776 | ||
47d37d6f SH |
777 | static u32 mxs_auart_get_mctrl(struct uart_port *u) |
778 | { | |
7c573d7e | 779 | struct mxs_auart_port *s = to_auart_port(u); |
254da0d7 | 780 | u32 stat = mxs_read(s, REG_STAT); |
42b4eba0 | 781 | u32 mctrl = 0; |
47d37d6f | 782 | |
47d37d6f SH |
783 | if (stat & AUART_STAT_CTS) |
784 | mctrl |= TIOCM_CTS; | |
785 | ||
7c573d7e | 786 | return mctrl_gpio_get(s->gpios, &mctrl); |
47d37d6f SH |
787 | } |
788 | ||
f9e42397 JU |
789 | /* |
790 | * Enable modem status interrupts | |
791 | */ | |
792 | static void mxs_auart_enable_ms(struct uart_port *port) | |
793 | { | |
794 | struct mxs_auart_port *s = to_auart_port(port); | |
795 | ||
796 | /* | |
797 | * Interrupt should not be enabled twice | |
798 | */ | |
799 | if (s->ms_irq_enabled) | |
800 | return; | |
801 | ||
802 | s->ms_irq_enabled = true; | |
803 | ||
804 | if (s->gpio_irq[UART_GPIO_CTS] >= 0) | |
805 | enable_irq(s->gpio_irq[UART_GPIO_CTS]); | |
806 | /* TODO: enable AUART_INTR_CTSMIEN otherwise */ | |
807 | ||
808 | if (s->gpio_irq[UART_GPIO_DSR] >= 0) | |
809 | enable_irq(s->gpio_irq[UART_GPIO_DSR]); | |
810 | ||
811 | if (s->gpio_irq[UART_GPIO_RI] >= 0) | |
812 | enable_irq(s->gpio_irq[UART_GPIO_RI]); | |
813 | ||
814 | if (s->gpio_irq[UART_GPIO_DCD] >= 0) | |
815 | enable_irq(s->gpio_irq[UART_GPIO_DCD]); | |
816 | } | |
817 | ||
818 | /* | |
819 | * Disable modem status interrupts | |
820 | */ | |
821 | static void mxs_auart_disable_ms(struct uart_port *port) | |
822 | { | |
823 | struct mxs_auart_port *s = to_auart_port(port); | |
824 | ||
825 | /* | |
826 | * Interrupt should not be disabled twice | |
827 | */ | |
828 | if (!s->ms_irq_enabled) | |
829 | return; | |
830 | ||
831 | s->ms_irq_enabled = false; | |
832 | ||
833 | if (s->gpio_irq[UART_GPIO_CTS] >= 0) | |
834 | disable_irq(s->gpio_irq[UART_GPIO_CTS]); | |
835 | /* TODO: disable AUART_INTR_CTSMIEN otherwise */ | |
836 | ||
837 | if (s->gpio_irq[UART_GPIO_DSR] >= 0) | |
838 | disable_irq(s->gpio_irq[UART_GPIO_DSR]); | |
839 | ||
840 | if (s->gpio_irq[UART_GPIO_RI] >= 0) | |
841 | disable_irq(s->gpio_irq[UART_GPIO_RI]); | |
842 | ||
843 | if (s->gpio_irq[UART_GPIO_DCD] >= 0) | |
844 | disable_irq(s->gpio_irq[UART_GPIO_DCD]); | |
845 | } | |
846 | ||
e8001632 HS |
847 | static int mxs_auart_dma_prep_rx(struct mxs_auart_port *s); |
848 | static void dma_rx_callback(void *arg) | |
849 | { | |
850 | struct mxs_auart_port *s = (struct mxs_auart_port *) arg; | |
05c7cd39 | 851 | struct tty_port *port = &s->port.state->port; |
e8001632 HS |
852 | int count; |
853 | u32 stat; | |
854 | ||
d7ffb932 HS |
855 | dma_unmap_sg(s->dev, &s->rx_sgl, 1, DMA_FROM_DEVICE); |
856 | ||
254da0d7 | 857 | stat = mxs_read(s, REG_STAT); |
e8001632 HS |
858 | stat &= ~(AUART_STAT_OERR | AUART_STAT_BERR | |
859 | AUART_STAT_PERR | AUART_STAT_FERR); | |
860 | ||
861 | count = stat & AUART_STAT_RXCOUNT_MASK; | |
05c7cd39 | 862 | tty_insert_flip_string(port, s->rx_dma_buf, count); |
e8001632 | 863 | |
254da0d7 | 864 | mxs_write(stat, s, REG_STAT); |
2e124b4a | 865 | tty_flip_buffer_push(port); |
e8001632 HS |
866 | |
867 | /* start the next DMA for RX. */ | |
868 | mxs_auart_dma_prep_rx(s); | |
869 | } | |
870 | ||
871 | static int mxs_auart_dma_prep_rx(struct mxs_auart_port *s) | |
872 | { | |
873 | struct dma_async_tx_descriptor *desc; | |
874 | struct scatterlist *sgl = &s->rx_sgl; | |
875 | struct dma_chan *channel = s->rx_dma_chan; | |
876 | u32 pio[1]; | |
877 | ||
878 | /* [1] : send PIO */ | |
879 | pio[0] = AUART_CTRL0_RXTO_ENABLE | |
880 | | AUART_CTRL0_RXTIMEOUT(0x80) | |
881 | | AUART_CTRL0_XFER_COUNT(UART_XMIT_SIZE); | |
882 | desc = dmaengine_prep_slave_sg(channel, (struct scatterlist *)pio, | |
883 | 1, DMA_TRANS_NONE, 0); | |
884 | if (!desc) { | |
885 | dev_err(s->dev, "step 1 error\n"); | |
886 | return -EINVAL; | |
887 | } | |
888 | ||
889 | /* [2] : send DMA request */ | |
890 | sg_init_one(sgl, s->rx_dma_buf, UART_XMIT_SIZE); | |
891 | dma_map_sg(s->dev, sgl, 1, DMA_FROM_DEVICE); | |
892 | desc = dmaengine_prep_slave_sg(channel, sgl, 1, DMA_DEV_TO_MEM, | |
893 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
894 | if (!desc) { | |
895 | dev_err(s->dev, "step 2 error\n"); | |
896 | return -1; | |
897 | } | |
898 | ||
899 | /* [3] : submit the DMA, but do not issue it. */ | |
900 | desc->callback = dma_rx_callback; | |
901 | desc->callback_param = s; | |
902 | dmaengine_submit(desc); | |
903 | dma_async_issue_pending(channel); | |
904 | return 0; | |
905 | } | |
906 | ||
907 | static void mxs_auart_dma_exit_channel(struct mxs_auart_port *s) | |
908 | { | |
909 | if (s->tx_dma_chan) { | |
910 | dma_release_channel(s->tx_dma_chan); | |
911 | s->tx_dma_chan = NULL; | |
912 | } | |
913 | if (s->rx_dma_chan) { | |
914 | dma_release_channel(s->rx_dma_chan); | |
915 | s->rx_dma_chan = NULL; | |
916 | } | |
917 | ||
918 | kfree(s->tx_dma_buf); | |
919 | kfree(s->rx_dma_buf); | |
920 | s->tx_dma_buf = NULL; | |
921 | s->rx_dma_buf = NULL; | |
922 | } | |
923 | ||
924 | static void mxs_auart_dma_exit(struct mxs_auart_port *s) | |
925 | { | |
926 | ||
254da0d7 OR |
927 | mxs_clr(AUART_CTRL2_TXDMAE | AUART_CTRL2_RXDMAE | AUART_CTRL2_DMAONERR, |
928 | s, REG_CTRL2); | |
e8001632 HS |
929 | |
930 | mxs_auart_dma_exit_channel(s); | |
931 | s->flags &= ~MXS_AUART_DMA_ENABLED; | |
932 | clear_bit(MXS_AUART_DMA_TX_SYNC, &s->flags); | |
933 | clear_bit(MXS_AUART_DMA_RX_READY, &s->flags); | |
934 | } | |
935 | ||
936 | static int mxs_auart_dma_init(struct mxs_auart_port *s) | |
937 | { | |
e8001632 HS |
938 | if (auart_dma_enabled(s)) |
939 | return 0; | |
940 | ||
e8001632 | 941 | /* init for RX */ |
bcc20f9e | 942 | s->rx_dma_chan = dma_request_slave_channel(s->dev, "rx"); |
e8001632 HS |
943 | if (!s->rx_dma_chan) |
944 | goto err_out; | |
945 | s->rx_dma_buf = kzalloc(UART_XMIT_SIZE, GFP_KERNEL | GFP_DMA); | |
946 | if (!s->rx_dma_buf) | |
947 | goto err_out; | |
948 | ||
949 | /* init for TX */ | |
bcc20f9e | 950 | s->tx_dma_chan = dma_request_slave_channel(s->dev, "tx"); |
e8001632 HS |
951 | if (!s->tx_dma_chan) |
952 | goto err_out; | |
953 | s->tx_dma_buf = kzalloc(UART_XMIT_SIZE, GFP_KERNEL | GFP_DMA); | |
954 | if (!s->tx_dma_buf) | |
955 | goto err_out; | |
956 | ||
957 | /* set the flags */ | |
958 | s->flags |= MXS_AUART_DMA_ENABLED; | |
959 | dev_dbg(s->dev, "enabled the DMA support."); | |
960 | ||
9987f76a HP |
961 | /* The DMA buffer is now the FIFO the TTY subsystem can use */ |
962 | s->port.fifosize = UART_XMIT_SIZE; | |
963 | ||
e8001632 HS |
964 | return 0; |
965 | ||
966 | err_out: | |
967 | mxs_auart_dma_exit_channel(s); | |
968 | return -EINVAL; | |
969 | ||
970 | } | |
971 | ||
7c573d7e JU |
972 | #define RTS_AT_AUART() IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(s->gpios, \ |
973 | UART_GPIO_RTS)) | |
974 | #define CTS_AT_AUART() IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(s->gpios, \ | |
975 | UART_GPIO_CTS)) | |
47d37d6f SH |
976 | static void mxs_auart_settermios(struct uart_port *u, |
977 | struct ktermios *termios, | |
978 | struct ktermios *old) | |
979 | { | |
e8001632 | 980 | struct mxs_auart_port *s = to_auart_port(u); |
47d37d6f | 981 | u32 bm, ctrl, ctrl2, div; |
df57cf6a | 982 | unsigned int cflag, baud, baud_min, baud_max; |
47d37d6f SH |
983 | |
984 | cflag = termios->c_cflag; | |
985 | ||
986 | ctrl = AUART_LINECTRL_FEN; | |
254da0d7 | 987 | ctrl2 = mxs_read(s, REG_CTRL2); |
47d37d6f SH |
988 | |
989 | /* byte size */ | |
990 | switch (cflag & CSIZE) { | |
991 | case CS5: | |
992 | bm = 0; | |
993 | break; | |
994 | case CS6: | |
995 | bm = 1; | |
996 | break; | |
997 | case CS7: | |
998 | bm = 2; | |
999 | break; | |
1000 | case CS8: | |
1001 | bm = 3; | |
1002 | break; | |
1003 | default: | |
1004 | return; | |
1005 | } | |
1006 | ||
1007 | ctrl |= AUART_LINECTRL_WLEN(bm); | |
1008 | ||
1009 | /* parity */ | |
1010 | if (cflag & PARENB) { | |
1011 | ctrl |= AUART_LINECTRL_PEN; | |
1012 | if ((cflag & PARODD) == 0) | |
1013 | ctrl |= AUART_LINECTRL_EPS; | |
f87fa71e WO |
1014 | if (cflag & CMSPAR) |
1015 | ctrl |= AUART_LINECTRL_SPS; | |
47d37d6f SH |
1016 | } |
1017 | ||
b8106454 | 1018 | u->read_status_mask = AUART_STAT_OERR; |
47d37d6f SH |
1019 | |
1020 | if (termios->c_iflag & INPCK) | |
1021 | u->read_status_mask |= AUART_STAT_PERR; | |
ef8b9ddc | 1022 | if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) |
47d37d6f SH |
1023 | u->read_status_mask |= AUART_STAT_BERR; |
1024 | ||
1025 | /* | |
1026 | * Characters to ignore | |
1027 | */ | |
1028 | u->ignore_status_mask = 0; | |
1029 | if (termios->c_iflag & IGNPAR) | |
1030 | u->ignore_status_mask |= AUART_STAT_PERR; | |
1031 | if (termios->c_iflag & IGNBRK) { | |
1032 | u->ignore_status_mask |= AUART_STAT_BERR; | |
1033 | /* | |
1034 | * If we're ignoring parity and break indicators, | |
1035 | * ignore overruns too (for real raw support). | |
1036 | */ | |
1037 | if (termios->c_iflag & IGNPAR) | |
1038 | u->ignore_status_mask |= AUART_STAT_OERR; | |
1039 | } | |
1040 | ||
1041 | /* | |
1042 | * ignore all characters if CREAD is not set | |
1043 | */ | |
1044 | if (cflag & CREAD) | |
1045 | ctrl2 |= AUART_CTRL2_RXE; | |
1046 | else | |
1047 | ctrl2 &= ~AUART_CTRL2_RXE; | |
1048 | ||
1049 | /* figure out the stop bits requested */ | |
1050 | if (cflag & CSTOPB) | |
1051 | ctrl |= AUART_LINECTRL_STP2; | |
1052 | ||
1053 | /* figure out the hardware flow control settings */ | |
7c573d7e | 1054 | ctrl2 &= ~(AUART_CTRL2_CTSEN | AUART_CTRL2_RTSEN); |
e8001632 HS |
1055 | if (cflag & CRTSCTS) { |
1056 | /* | |
1057 | * The DMA has a bug(see errata:2836) in mx23. | |
1058 | * So we can not implement the DMA for auart in mx23, | |
1059 | * we can only implement the DMA support for auart | |
1060 | * in mx28. | |
1061 | */ | |
afab2203 | 1062 | if (is_imx28_auart(s) |
8418e67d | 1063 | && test_bit(MXS_AUART_RTSCTS, &s->flags)) { |
e8001632 HS |
1064 | if (!mxs_auart_dma_init(s)) |
1065 | /* enable DMA tranfer */ | |
1066 | ctrl2 |= AUART_CTRL2_TXDMAE | AUART_CTRL2_RXDMAE | |
1067 | | AUART_CTRL2_DMAONERR; | |
1068 | } | |
7c573d7e JU |
1069 | /* Even if RTS is GPIO line RTSEN can be enabled because |
1070 | * the pinctrl configuration decides about RTS pin function */ | |
1071 | ctrl2 |= AUART_CTRL2_RTSEN; | |
1072 | if (CTS_AT_AUART()) | |
1073 | ctrl2 |= AUART_CTRL2_CTSEN; | |
e8001632 | 1074 | } |
47d37d6f SH |
1075 | |
1076 | /* set baud rate */ | |
254da0d7 OR |
1077 | if (is_asm9260_auart(s)) { |
1078 | baud = uart_get_baud_rate(u, termios, old, | |
1079 | u->uartclk * 4 / 0x3FFFFF, | |
1080 | u->uartclk / 16); | |
1081 | div = u->uartclk * 4 / baud; | |
1082 | } else { | |
1083 | baud_min = DIV_ROUND_UP(u->uartclk * 32, | |
1084 | AUART_LINECTRL_BAUD_DIV_MAX); | |
1085 | baud_max = u->uartclk * 32 / AUART_LINECTRL_BAUD_DIV_MIN; | |
1086 | baud = uart_get_baud_rate(u, termios, old, baud_min, baud_max); | |
a6040bc6 | 1087 | div = DIV_ROUND_CLOSEST(u->uartclk * 32, baud); |
254da0d7 OR |
1088 | } |
1089 | ||
47d37d6f SH |
1090 | ctrl |= AUART_LINECTRL_BAUD_DIVFRAC(div & 0x3F); |
1091 | ctrl |= AUART_LINECTRL_BAUD_DIVINT(div >> 6); | |
254da0d7 | 1092 | mxs_write(ctrl, s, REG_LINECTRL); |
47d37d6f | 1093 | |
254da0d7 | 1094 | mxs_write(ctrl2, s, REG_CTRL2); |
8b979f7c LW |
1095 | |
1096 | uart_update_timeout(u, termios->c_cflag, baud); | |
e8001632 HS |
1097 | |
1098 | /* prepare for the DMA RX. */ | |
1099 | if (auart_dma_enabled(s) && | |
1100 | !test_and_set_bit(MXS_AUART_DMA_RX_READY, &s->flags)) { | |
1101 | if (!mxs_auart_dma_prep_rx(s)) { | |
1102 | /* Disable the normal RX interrupt. */ | |
254da0d7 OR |
1103 | mxs_clr(AUART_INTR_RXIEN | AUART_INTR_RTIEN, |
1104 | s, REG_INTR); | |
e8001632 HS |
1105 | } else { |
1106 | mxs_auart_dma_exit(s); | |
1107 | dev_err(s->dev, "We can not start up the DMA.\n"); | |
1108 | } | |
1109 | } | |
f9e42397 JU |
1110 | |
1111 | /* CTS flow-control and modem-status interrupts */ | |
1112 | if (UART_ENABLE_MS(u, termios->c_cflag)) | |
1113 | mxs_auart_enable_ms(u); | |
1114 | else | |
1115 | mxs_auart_disable_ms(u); | |
47d37d6f SH |
1116 | } |
1117 | ||
f3006e44 FE |
1118 | static void mxs_auart_set_ldisc(struct uart_port *port, |
1119 | struct ktermios *termios) | |
36a26278 | 1120 | { |
f3006e44 | 1121 | if (termios->c_line == N_PPS) { |
36a26278 JU |
1122 | port->flags |= UPF_HARDPPS_CD; |
1123 | mxs_auart_enable_ms(port); | |
1124 | } else { | |
1125 | port->flags &= ~UPF_HARDPPS_CD; | |
1126 | } | |
1127 | } | |
1128 | ||
47d37d6f SH |
1129 | static irqreturn_t mxs_auart_irq_handle(int irq, void *context) |
1130 | { | |
d970d7fe | 1131 | u32 istat; |
47d37d6f | 1132 | struct mxs_auart_port *s = context; |
08f937f4 | 1133 | u32 mctrl_temp = s->mctrl_prev; |
254da0d7 | 1134 | u32 stat = mxs_read(s, REG_STAT); |
47d37d6f | 1135 | |
254da0d7 | 1136 | istat = mxs_read(s, REG_INTR); |
d970d7fe UKK |
1137 | |
1138 | /* ack irq */ | |
254da0d7 OR |
1139 | mxs_clr(istat & (AUART_INTR_RTIS | AUART_INTR_TXIS | AUART_INTR_RXIS |
1140 | | AUART_INTR_CTSMIS), s, REG_INTR); | |
47d37d6f | 1141 | |
f9e42397 JU |
1142 | /* |
1143 | * Dealing with GPIO interrupt | |
1144 | */ | |
1145 | if (irq == s->gpio_irq[UART_GPIO_CTS] || | |
1146 | irq == s->gpio_irq[UART_GPIO_DCD] || | |
1147 | irq == s->gpio_irq[UART_GPIO_DSR] || | |
1148 | irq == s->gpio_irq[UART_GPIO_RI]) | |
1149 | mxs_auart_modem_status(s, | |
08f937f4 | 1150 | mctrl_gpio_get(s->gpios, &mctrl_temp)); |
f9e42397 | 1151 | |
47d37d6f | 1152 | if (istat & AUART_INTR_CTSMIS) { |
f9e42397 | 1153 | if (CTS_AT_AUART() && s->ms_irq_enabled) |
7c573d7e JU |
1154 | uart_handle_cts_change(&s->port, |
1155 | stat & AUART_STAT_CTS); | |
254da0d7 | 1156 | mxs_clr(AUART_INTR_CTSMIS, s, REG_INTR); |
47d37d6f SH |
1157 | istat &= ~AUART_INTR_CTSMIS; |
1158 | } | |
1159 | ||
1160 | if (istat & (AUART_INTR_RTIS | AUART_INTR_RXIS)) { | |
a5919442 HS |
1161 | if (!auart_dma_enabled(s)) |
1162 | mxs_auart_rx_chars(s); | |
47d37d6f SH |
1163 | istat &= ~(AUART_INTR_RTIS | AUART_INTR_RXIS); |
1164 | } | |
1165 | ||
1166 | if (istat & AUART_INTR_TXIS) { | |
1167 | mxs_auart_tx_chars(s); | |
1168 | istat &= ~AUART_INTR_TXIS; | |
1169 | } | |
1170 | ||
47d37d6f SH |
1171 | return IRQ_HANDLED; |
1172 | } | |
1173 | ||
254da0d7 | 1174 | static void mxs_auart_reset_deassert(struct mxs_auart_port *s) |
47d37d6f SH |
1175 | { |
1176 | int i; | |
1177 | unsigned int reg; | |
1178 | ||
254da0d7 | 1179 | mxs_clr(AUART_CTRL0_SFTRST, s, REG_CTRL0); |
47d37d6f SH |
1180 | |
1181 | for (i = 0; i < 10000; i++) { | |
254da0d7 | 1182 | reg = mxs_read(s, REG_CTRL0); |
47d37d6f SH |
1183 | if (!(reg & AUART_CTRL0_SFTRST)) |
1184 | break; | |
1185 | udelay(3); | |
1186 | } | |
254da0d7 | 1187 | mxs_clr(AUART_CTRL0_CLKGATE, s, REG_CTRL0); |
47d37d6f SH |
1188 | } |
1189 | ||
254da0d7 | 1190 | static void mxs_auart_reset_assert(struct mxs_auart_port *s) |
17dc72cf JB |
1191 | { |
1192 | int i; | |
1193 | u32 reg; | |
1194 | ||
254da0d7 | 1195 | reg = mxs_read(s, REG_CTRL0); |
17dc72cf JB |
1196 | /* if already in reset state, keep it untouched */ |
1197 | if (reg & AUART_CTRL0_SFTRST) | |
1198 | return; | |
1199 | ||
254da0d7 OR |
1200 | mxs_clr(AUART_CTRL0_CLKGATE, s, REG_CTRL0); |
1201 | mxs_set(AUART_CTRL0_SFTRST, s, REG_CTRL0); | |
17dc72cf JB |
1202 | |
1203 | for (i = 0; i < 1000; i++) { | |
254da0d7 | 1204 | reg = mxs_read(s, REG_CTRL0); |
17dc72cf JB |
1205 | /* reset is finished when the clock is gated */ |
1206 | if (reg & AUART_CTRL0_CLKGATE) | |
1207 | return; | |
1208 | udelay(10); | |
1209 | } | |
1210 | ||
254da0d7 | 1211 | dev_err(s->dev, "Failed to reset the unit."); |
17dc72cf JB |
1212 | } |
1213 | ||
47d37d6f SH |
1214 | static int mxs_auart_startup(struct uart_port *u) |
1215 | { | |
9bbc3dca | 1216 | int ret; |
47d37d6f SH |
1217 | struct mxs_auart_port *s = to_auart_port(u); |
1218 | ||
9bbc3dca FE |
1219 | ret = clk_prepare_enable(s->clk); |
1220 | if (ret) | |
1221 | return ret; | |
47d37d6f | 1222 | |
17dc72cf | 1223 | if (uart_console(u)) { |
254da0d7 | 1224 | mxs_clr(AUART_CTRL0_CLKGATE, s, REG_CTRL0); |
17dc72cf JB |
1225 | } else { |
1226 | /* reset the unit to a well known state */ | |
254da0d7 OR |
1227 | mxs_auart_reset_assert(s); |
1228 | mxs_auart_reset_deassert(s); | |
17dc72cf | 1229 | } |
47d37d6f | 1230 | |
254da0d7 | 1231 | mxs_set(AUART_CTRL2_UARTEN, s, REG_CTRL2); |
47d37d6f | 1232 | |
254da0d7 OR |
1233 | mxs_write(AUART_INTR_RXIEN | AUART_INTR_RTIEN | AUART_INTR_CTSMIEN, |
1234 | s, REG_INTR); | |
47d37d6f | 1235 | |
9987f76a HP |
1236 | /* Reset FIFO size (it could have changed if DMA was enabled) */ |
1237 | u->fifosize = MXS_AUART_FIFO_SIZE; | |
1238 | ||
47d37d6f SH |
1239 | /* |
1240 | * Enable fifo so all four bytes of a DMA word are written to | |
1241 | * output (otherwise, only the LSB is written, ie. 1 in 4 bytes) | |
1242 | */ | |
254da0d7 | 1243 | mxs_set(AUART_LINECTRL_FEN, s, REG_LINECTRL); |
47d37d6f | 1244 | |
f9e42397 JU |
1245 | /* get initial status of modem lines */ |
1246 | mctrl_gpio_get(s->gpios, &s->mctrl_prev); | |
1247 | ||
1248 | s->ms_irq_enabled = false; | |
47d37d6f SH |
1249 | return 0; |
1250 | } | |
1251 | ||
1252 | static void mxs_auart_shutdown(struct uart_port *u) | |
1253 | { | |
1254 | struct mxs_auart_port *s = to_auart_port(u); | |
1255 | ||
f9e42397 JU |
1256 | mxs_auart_disable_ms(u); |
1257 | ||
e8001632 HS |
1258 | if (auart_dma_enabled(s)) |
1259 | mxs_auart_dma_exit(s); | |
1260 | ||
17dc72cf | 1261 | if (uart_console(u)) { |
254da0d7 OR |
1262 | mxs_clr(AUART_CTRL2_UARTEN, s, REG_CTRL2); |
1263 | ||
1264 | mxs_clr(AUART_INTR_RXIEN | AUART_INTR_RTIEN | | |
1265 | AUART_INTR_CTSMIEN, s, REG_INTR); | |
1266 | mxs_set(AUART_CTRL0_CLKGATE, s, REG_CTRL0); | |
17dc72cf | 1267 | } else { |
254da0d7 | 1268 | mxs_auart_reset_assert(s); |
17dc72cf | 1269 | } |
851b714b | 1270 | |
a4813770 | 1271 | clk_disable_unprepare(s->clk); |
47d37d6f SH |
1272 | } |
1273 | ||
1274 | static unsigned int mxs_auart_tx_empty(struct uart_port *u) | |
1275 | { | |
254da0d7 OR |
1276 | struct mxs_auart_port *s = to_auart_port(u); |
1277 | ||
1278 | if ((mxs_read(s, REG_STAT) & | |
2b310ec7 | 1279 | (AUART_STAT_TXFE | AUART_STAT_BUSY)) == AUART_STAT_TXFE) |
47d37d6f | 1280 | return TIOCSER_TEMT; |
2b310ec7 JU |
1281 | |
1282 | return 0; | |
47d37d6f SH |
1283 | } |
1284 | ||
1285 | static void mxs_auart_start_tx(struct uart_port *u) | |
1286 | { | |
1287 | struct mxs_auart_port *s = to_auart_port(u); | |
1288 | ||
1289 | /* enable transmitter */ | |
254da0d7 | 1290 | mxs_set(AUART_CTRL2_TXE, s, REG_CTRL2); |
47d37d6f SH |
1291 | |
1292 | mxs_auart_tx_chars(s); | |
1293 | } | |
1294 | ||
1295 | static void mxs_auart_stop_tx(struct uart_port *u) | |
1296 | { | |
254da0d7 OR |
1297 | struct mxs_auart_port *s = to_auart_port(u); |
1298 | ||
1299 | mxs_clr(AUART_CTRL2_TXE, s, REG_CTRL2); | |
47d37d6f SH |
1300 | } |
1301 | ||
1302 | static void mxs_auart_stop_rx(struct uart_port *u) | |
1303 | { | |
254da0d7 OR |
1304 | struct mxs_auart_port *s = to_auart_port(u); |
1305 | ||
1306 | mxs_clr(AUART_CTRL2_RXE, s, REG_CTRL2); | |
47d37d6f SH |
1307 | } |
1308 | ||
1309 | static void mxs_auart_break_ctl(struct uart_port *u, int ctl) | |
1310 | { | |
254da0d7 OR |
1311 | struct mxs_auart_port *s = to_auart_port(u); |
1312 | ||
47d37d6f | 1313 | if (ctl) |
254da0d7 | 1314 | mxs_set(AUART_LINECTRL_BRK, s, REG_LINECTRL); |
47d37d6f | 1315 | else |
254da0d7 | 1316 | mxs_clr(AUART_LINECTRL_BRK, s, REG_LINECTRL); |
47d37d6f SH |
1317 | } |
1318 | ||
069a47e5 | 1319 | static const struct uart_ops mxs_auart_ops = { |
47d37d6f SH |
1320 | .tx_empty = mxs_auart_tx_empty, |
1321 | .start_tx = mxs_auart_start_tx, | |
1322 | .stop_tx = mxs_auart_stop_tx, | |
1323 | .stop_rx = mxs_auart_stop_rx, | |
f9e42397 | 1324 | .enable_ms = mxs_auart_enable_ms, |
47d37d6f SH |
1325 | .break_ctl = mxs_auart_break_ctl, |
1326 | .set_mctrl = mxs_auart_set_mctrl, | |
1327 | .get_mctrl = mxs_auart_get_mctrl, | |
1328 | .startup = mxs_auart_startup, | |
1329 | .shutdown = mxs_auart_shutdown, | |
1330 | .set_termios = mxs_auart_settermios, | |
36a26278 | 1331 | .set_ldisc = mxs_auart_set_ldisc, |
47d37d6f SH |
1332 | .type = mxs_auart_type, |
1333 | .release_port = mxs_auart_release_port, | |
1334 | .request_port = mxs_auart_request_port, | |
1335 | .config_port = mxs_auart_config_port, | |
1336 | .verify_port = mxs_auart_verify_port, | |
1337 | }; | |
1338 | ||
1339 | static struct mxs_auart_port *auart_port[MXS_AUART_PORTS]; | |
1340 | ||
1341 | #ifdef CONFIG_SERIAL_MXS_AUART_CONSOLE | |
1342 | static void mxs_auart_console_putchar(struct uart_port *port, int ch) | |
1343 | { | |
254da0d7 | 1344 | struct mxs_auart_port *s = to_auart_port(port); |
47d37d6f SH |
1345 | unsigned int to = 1000; |
1346 | ||
254da0d7 | 1347 | while (mxs_read(s, REG_STAT) & AUART_STAT_TXFF) { |
47d37d6f SH |
1348 | if (!to--) |
1349 | break; | |
1350 | udelay(1); | |
1351 | } | |
1352 | ||
254da0d7 | 1353 | mxs_write(ch, s, REG_DATA); |
47d37d6f SH |
1354 | } |
1355 | ||
1356 | static void | |
1357 | auart_console_write(struct console *co, const char *str, unsigned int count) | |
1358 | { | |
1359 | struct mxs_auart_port *s; | |
1360 | struct uart_port *port; | |
1361 | unsigned int old_ctrl0, old_ctrl2; | |
079a036f | 1362 | unsigned int to = 20000; |
47d37d6f | 1363 | |
4829e765 | 1364 | if (co->index >= MXS_AUART_PORTS || co->index < 0) |
47d37d6f SH |
1365 | return; |
1366 | ||
1367 | s = auart_port[co->index]; | |
1368 | port = &s->port; | |
1369 | ||
1370 | clk_enable(s->clk); | |
1371 | ||
1372 | /* First save the CR then disable the interrupts */ | |
254da0d7 OR |
1373 | old_ctrl2 = mxs_read(s, REG_CTRL2); |
1374 | old_ctrl0 = mxs_read(s, REG_CTRL0); | |
47d37d6f | 1375 | |
254da0d7 OR |
1376 | mxs_clr(AUART_CTRL0_CLKGATE, s, REG_CTRL0); |
1377 | mxs_set(AUART_CTRL2_UARTEN | AUART_CTRL2_TXE, s, REG_CTRL2); | |
47d37d6f SH |
1378 | |
1379 | uart_console_write(port, str, count, mxs_auart_console_putchar); | |
1380 | ||
079a036f | 1381 | /* Finally, wait for transmitter to become empty ... */ |
254da0d7 | 1382 | while (mxs_read(s, REG_STAT) & AUART_STAT_BUSY) { |
079a036f | 1383 | udelay(1); |
47d37d6f SH |
1384 | if (!to--) |
1385 | break; | |
47d37d6f SH |
1386 | } |
1387 | ||
079a036f UKK |
1388 | /* |
1389 | * ... and restore the TCR if we waited long enough for the transmitter | |
1390 | * to be idle. This might keep the transmitter enabled although it is | |
1391 | * unused, but that is better than to disable it while it is still | |
1392 | * transmitting. | |
1393 | */ | |
254da0d7 OR |
1394 | if (!(mxs_read(s, REG_STAT) & AUART_STAT_BUSY)) { |
1395 | mxs_write(old_ctrl0, s, REG_CTRL0); | |
1396 | mxs_write(old_ctrl2, s, REG_CTRL2); | |
079a036f | 1397 | } |
47d37d6f SH |
1398 | |
1399 | clk_disable(s->clk); | |
1400 | } | |
1401 | ||
1402 | static void __init | |
254da0d7 | 1403 | auart_console_get_options(struct mxs_auart_port *s, int *baud, |
47d37d6f SH |
1404 | int *parity, int *bits) |
1405 | { | |
254da0d7 | 1406 | struct uart_port *port = &s->port; |
47d37d6f SH |
1407 | unsigned int lcr_h, quot; |
1408 | ||
254da0d7 | 1409 | if (!(mxs_read(s, REG_CTRL2) & AUART_CTRL2_UARTEN)) |
47d37d6f SH |
1410 | return; |
1411 | ||
254da0d7 | 1412 | lcr_h = mxs_read(s, REG_LINECTRL); |
47d37d6f SH |
1413 | |
1414 | *parity = 'n'; | |
1415 | if (lcr_h & AUART_LINECTRL_PEN) { | |
1416 | if (lcr_h & AUART_LINECTRL_EPS) | |
1417 | *parity = 'e'; | |
1418 | else | |
1419 | *parity = 'o'; | |
1420 | } | |
1421 | ||
1422 | if ((lcr_h & AUART_LINECTRL_WLEN_MASK) == AUART_LINECTRL_WLEN(2)) | |
1423 | *bits = 7; | |
1424 | else | |
1425 | *bits = 8; | |
1426 | ||
254da0d7 OR |
1427 | quot = ((mxs_read(s, REG_LINECTRL) & AUART_LINECTRL_BAUD_DIVINT_MASK)) |
1428 | >> (AUART_LINECTRL_BAUD_DIVINT_SHIFT - 6); | |
1429 | quot |= ((mxs_read(s, REG_LINECTRL) & AUART_LINECTRL_BAUD_DIVFRAC_MASK)) | |
1430 | >> AUART_LINECTRL_BAUD_DIVFRAC_SHIFT; | |
47d37d6f SH |
1431 | if (quot == 0) |
1432 | quot = 1; | |
1433 | ||
1434 | *baud = (port->uartclk << 2) / quot; | |
1435 | } | |
1436 | ||
1437 | static int __init | |
1438 | auart_console_setup(struct console *co, char *options) | |
1439 | { | |
1440 | struct mxs_auart_port *s; | |
1441 | int baud = 9600; | |
1442 | int bits = 8; | |
1443 | int parity = 'n'; | |
1444 | int flow = 'n'; | |
1445 | int ret; | |
1446 | ||
1447 | /* | |
1448 | * Check whether an invalid uart number has been specified, and | |
1449 | * if so, search for the first available port that does have | |
1450 | * console support. | |
1451 | */ | |
1452 | if (co->index == -1 || co->index >= ARRAY_SIZE(auart_port)) | |
1453 | co->index = 0; | |
1454 | s = auart_port[co->index]; | |
1455 | if (!s) | |
1456 | return -ENODEV; | |
1457 | ||
9bbc3dca FE |
1458 | ret = clk_prepare_enable(s->clk); |
1459 | if (ret) | |
1460 | return ret; | |
47d37d6f SH |
1461 | |
1462 | if (options) | |
1463 | uart_parse_options(options, &baud, &parity, &bits, &flow); | |
1464 | else | |
254da0d7 | 1465 | auart_console_get_options(s, &baud, &parity, &bits); |
47d37d6f SH |
1466 | |
1467 | ret = uart_set_options(&s->port, co, baud, parity, bits, flow); | |
1468 | ||
a4813770 | 1469 | clk_disable_unprepare(s->clk); |
47d37d6f SH |
1470 | |
1471 | return ret; | |
1472 | } | |
1473 | ||
1474 | static struct console auart_console = { | |
1475 | .name = "ttyAPP", | |
1476 | .write = auart_console_write, | |
1477 | .device = uart_console_device, | |
1478 | .setup = auart_console_setup, | |
1479 | .flags = CON_PRINTBUFFER, | |
1480 | .index = -1, | |
1481 | .data = &auart_driver, | |
1482 | }; | |
1483 | #endif | |
1484 | ||
1485 | static struct uart_driver auart_driver = { | |
1486 | .owner = THIS_MODULE, | |
1487 | .driver_name = "ttyAPP", | |
1488 | .dev_name = "ttyAPP", | |
1489 | .major = 0, | |
1490 | .minor = 0, | |
1491 | .nr = MXS_AUART_PORTS, | |
1492 | #ifdef CONFIG_SERIAL_MXS_AUART_CONSOLE | |
1493 | .cons = &auart_console, | |
1494 | #endif | |
1495 | }; | |
1496 | ||
254da0d7 OR |
1497 | static void mxs_init_regs(struct mxs_auart_port *s) |
1498 | { | |
1499 | if (is_asm9260_auart(s)) | |
1500 | s->vendor = &vendor_alphascale_asm9260; | |
1501 | else | |
1502 | s->vendor = &vendor_freescale_stmp37xx; | |
1503 | } | |
1504 | ||
1505 | static int mxs_get_clks(struct mxs_auart_port *s, | |
1506 | struct platform_device *pdev) | |
1507 | { | |
1508 | int err; | |
1509 | ||
1510 | if (!is_asm9260_auart(s)) { | |
1511 | s->clk = devm_clk_get(&pdev->dev, NULL); | |
0d2665b6 | 1512 | return PTR_ERR_OR_ZERO(s->clk); |
254da0d7 OR |
1513 | } |
1514 | ||
1515 | s->clk = devm_clk_get(s->dev, "mod"); | |
1516 | if (IS_ERR(s->clk)) { | |
1517 | dev_err(s->dev, "Failed to get \"mod\" clk\n"); | |
1518 | return PTR_ERR(s->clk); | |
1519 | } | |
1520 | ||
1521 | s->clk_ahb = devm_clk_get(s->dev, "ahb"); | |
1522 | if (IS_ERR(s->clk_ahb)) { | |
1523 | dev_err(s->dev, "Failed to get \"ahb\" clk\n"); | |
1524 | return PTR_ERR(s->clk_ahb); | |
1525 | } | |
1526 | ||
1527 | err = clk_prepare_enable(s->clk_ahb); | |
1528 | if (err) { | |
1529 | dev_err(s->dev, "Failed to enable ahb_clk!\n"); | |
1530 | return err; | |
1531 | } | |
1532 | ||
1533 | err = clk_set_rate(s->clk, clk_get_rate(s->clk_ahb)); | |
1534 | if (err) { | |
1535 | dev_err(s->dev, "Failed to set rate!\n"); | |
1664bc40 | 1536 | goto disable_clk_ahb; |
254da0d7 OR |
1537 | } |
1538 | ||
1539 | err = clk_prepare_enable(s->clk); | |
1540 | if (err) { | |
1541 | dev_err(s->dev, "Failed to enable clk!\n"); | |
5d7519df | 1542 | goto disable_clk_ahb; |
254da0d7 OR |
1543 | } |
1544 | ||
1545 | return 0; | |
5d7519df FE |
1546 | |
1547 | disable_clk_ahb: | |
1548 | clk_disable_unprepare(s->clk_ahb); | |
1549 | return err; | |
254da0d7 OR |
1550 | } |
1551 | ||
1ea6607d FE |
1552 | /* |
1553 | * This function returns 1 if pdev isn't a device instatiated by dt, 0 if it | |
1554 | * could successfully get all information from dt or a negative errno. | |
1555 | */ | |
1556 | static int serial_mxs_probe_dt(struct mxs_auart_port *s, | |
1557 | struct platform_device *pdev) | |
1558 | { | |
1559 | struct device_node *np = pdev->dev.of_node; | |
1560 | int ret; | |
1561 | ||
1562 | if (!np) | |
1563 | /* no device tree device */ | |
1564 | return 1; | |
1565 | ||
1566 | ret = of_alias_get_id(np, "serial"); | |
1567 | if (ret < 0) { | |
1568 | dev_err(&pdev->dev, "failed to get alias id: %d\n", ret); | |
1569 | return ret; | |
1570 | } | |
1571 | s->port.line = ret; | |
1572 | ||
182cdcb8 GU |
1573 | if (of_get_property(np, "uart-has-rtscts", NULL) || |
1574 | of_get_property(np, "fsl,uart-has-rtscts", NULL) /* deprecated */) | |
8418e67d HS |
1575 | set_bit(MXS_AUART_RTSCTS, &s->flags); |
1576 | ||
1ea6607d FE |
1577 | return 0; |
1578 | } | |
1579 | ||
343fda95 | 1580 | static int mxs_auart_init_gpios(struct mxs_auart_port *s, struct device *dev) |
7c573d7e | 1581 | { |
f9e42397 JU |
1582 | enum mctrl_gpio_idx i; |
1583 | struct gpio_desc *gpiod; | |
1584 | ||
7d8c70d8 | 1585 | s->gpios = mctrl_gpio_init_noauto(dev, 0); |
343fda95 UKK |
1586 | if (IS_ERR(s->gpios)) |
1587 | return PTR_ERR(s->gpios); | |
7c573d7e JU |
1588 | |
1589 | /* Block (enabled before) DMA option if RTS or CTS is GPIO line */ | |
1590 | if (!RTS_AT_AUART() || !CTS_AT_AUART()) { | |
1591 | if (test_bit(MXS_AUART_RTSCTS, &s->flags)) | |
1592 | dev_warn(dev, | |
1593 | "DMA and flow control via gpio may cause some problems. DMA disabled!\n"); | |
1594 | clear_bit(MXS_AUART_RTSCTS, &s->flags); | |
1595 | } | |
1596 | ||
f9e42397 JU |
1597 | for (i = 0; i < UART_GPIO_MAX; i++) { |
1598 | gpiod = mctrl_gpio_to_gpiod(s->gpios, i); | |
f8bdfe9d | 1599 | if (gpiod && (gpiod_get_direction(gpiod) == 1)) |
f9e42397 JU |
1600 | s->gpio_irq[i] = gpiod_to_irq(gpiod); |
1601 | else | |
1602 | s->gpio_irq[i] = -EINVAL; | |
1603 | } | |
1604 | ||
343fda95 | 1605 | return 0; |
7c573d7e JU |
1606 | } |
1607 | ||
f9e42397 JU |
1608 | static void mxs_auart_free_gpio_irq(struct mxs_auart_port *s) |
1609 | { | |
1610 | enum mctrl_gpio_idx i; | |
1611 | ||
1612 | for (i = 0; i < UART_GPIO_MAX; i++) | |
1613 | if (s->gpio_irq[i] >= 0) | |
1614 | free_irq(s->gpio_irq[i], s); | |
1615 | } | |
1616 | ||
1617 | static int mxs_auart_request_gpio_irq(struct mxs_auart_port *s) | |
1618 | { | |
1619 | int *irq = s->gpio_irq; | |
1620 | enum mctrl_gpio_idx i; | |
1621 | int err = 0; | |
1622 | ||
1623 | for (i = 0; (i < UART_GPIO_MAX) && !err; i++) { | |
1624 | if (irq[i] < 0) | |
1625 | continue; | |
1626 | ||
1627 | irq_set_status_flags(irq[i], IRQ_NOAUTOEN); | |
1628 | err = request_irq(irq[i], mxs_auart_irq_handle, | |
1629 | IRQ_TYPE_EDGE_BOTH, dev_name(s->dev), s); | |
1630 | if (err) | |
1631 | dev_err(s->dev, "%s - Can't get %d irq\n", | |
1632 | __func__, irq[i]); | |
1633 | } | |
1634 | ||
1635 | /* | |
1636 | * If something went wrong, rollback. | |
1637 | */ | |
1638 | while (err && (--i >= 0)) | |
1639 | if (irq[i] >= 0) | |
1640 | free_irq(irq[i], s); | |
1641 | ||
1642 | return err; | |
1643 | } | |
1644 | ||
9671f099 | 1645 | static int mxs_auart_probe(struct platform_device *pdev) |
47d37d6f | 1646 | { |
f4b1f03b HS |
1647 | const struct of_device_id *of_id = |
1648 | of_match_device(mxs_auart_dt_ids, &pdev->dev); | |
47d37d6f SH |
1649 | struct mxs_auart_port *s; |
1650 | u32 version; | |
5f9ba5b6 | 1651 | int ret, irq; |
47d37d6f SH |
1652 | struct resource *r; |
1653 | ||
46778bca | 1654 | s = devm_kzalloc(&pdev->dev, sizeof(*s), GFP_KERNEL); |
11387b0a FE |
1655 | if (!s) |
1656 | return -ENOMEM; | |
47d37d6f | 1657 | |
254da0d7 OR |
1658 | s->port.dev = &pdev->dev; |
1659 | s->dev = &pdev->dev; | |
1660 | ||
1ea6607d FE |
1661 | ret = serial_mxs_probe_dt(s, pdev); |
1662 | if (ret > 0) | |
1663 | s->port.line = pdev->id < 0 ? 0 : pdev->id; | |
1664 | else if (ret < 0) | |
46778bca | 1665 | return ret; |
1ea6607d | 1666 | |
f4b1f03b HS |
1667 | if (of_id) { |
1668 | pdev->id_entry = of_id->data; | |
1669 | s->devtype = pdev->id_entry->driver_data; | |
1670 | } | |
1671 | ||
254da0d7 OR |
1672 | ret = mxs_get_clks(s, pdev); |
1673 | if (ret) | |
1674 | return ret; | |
47d37d6f SH |
1675 | |
1676 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
75beb268 FE |
1677 | if (!r) |
1678 | return -ENXIO; | |
1679 | ||
47d37d6f SH |
1680 | s->port.mapbase = r->start; |
1681 | s->port.membase = ioremap(r->start, resource_size(r)); | |
1682 | s->port.ops = &mxs_auart_ops; | |
1683 | s->port.iotype = UPIO_MEM; | |
9987f76a | 1684 | s->port.fifosize = MXS_AUART_FIFO_SIZE; |
47d37d6f SH |
1685 | s->port.uartclk = clk_get_rate(s->clk); |
1686 | s->port.type = PORT_IMX; | |
254da0d7 OR |
1687 | |
1688 | mxs_init_regs(s); | |
47d37d6f | 1689 | |
f9e42397 JU |
1690 | s->mctrl_prev = 0; |
1691 | ||
6960cd46 | 1692 | irq = platform_get_irq(pdev, 0); |
99c932c2 FE |
1693 | if (irq < 0) |
1694 | return irq; | |
1695 | ||
6960cd46 FE |
1696 | s->port.irq = irq; |
1697 | ret = devm_request_irq(&pdev->dev, irq, mxs_auart_irq_handle, 0, | |
9e5df9f8 | 1698 | dev_name(&pdev->dev), s); |
47d37d6f | 1699 | if (ret) |
75beb268 | 1700 | return ret; |
47d37d6f SH |
1701 | |
1702 | platform_set_drvdata(pdev, s); | |
1703 | ||
343fda95 UKK |
1704 | ret = mxs_auart_init_gpios(s, &pdev->dev); |
1705 | if (ret) { | |
1706 | dev_err(&pdev->dev, "Failed to initialize GPIOs.\n"); | |
ac25e8c7 | 1707 | return ret; |
343fda95 | 1708 | } |
7c573d7e | 1709 | |
f9e42397 JU |
1710 | /* |
1711 | * Get the GPIO lines IRQ | |
1712 | */ | |
1713 | ret = mxs_auart_request_gpio_irq(s); | |
1714 | if (ret) | |
9e5df9f8 | 1715 | return ret; |
f9e42397 | 1716 | |
1ea6607d | 1717 | auart_port[s->port.line] = s; |
47d37d6f | 1718 | |
254da0d7 | 1719 | mxs_auart_reset_deassert(s); |
47d37d6f SH |
1720 | |
1721 | ret = uart_add_one_port(&auart_driver, &s->port); | |
1722 | if (ret) | |
5c305539 | 1723 | goto out_disable_clks_free_qpio_irq; |
47d37d6f | 1724 | |
254da0d7 OR |
1725 | /* ASM9260 don't have version reg */ |
1726 | if (is_asm9260_auart(s)) { | |
1727 | dev_info(&pdev->dev, "Found APPUART ASM9260\n"); | |
1728 | } else { | |
1729 | version = mxs_read(s, REG_VERSION); | |
1730 | dev_info(&pdev->dev, "Found APPUART %d.%d.%d\n", | |
1731 | (version >> 24) & 0xff, | |
1732 | (version >> 16) & 0xff, version & 0xffff); | |
1733 | } | |
47d37d6f SH |
1734 | |
1735 | return 0; | |
1736 | ||
5c305539 BR |
1737 | out_disable_clks_free_qpio_irq: |
1738 | if (s->clk) | |
1739 | clk_disable_unprepare(s->clk_ahb); | |
1740 | if (s->clk_ahb) | |
1741 | clk_disable_unprepare(s->clk_ahb); | |
f9e42397 | 1742 | mxs_auart_free_gpio_irq(s); |
47d37d6f | 1743 | auart_port[pdev->id] = NULL; |
47d37d6f SH |
1744 | return ret; |
1745 | } | |
1746 | ||
ae8d8a14 | 1747 | static int mxs_auart_remove(struct platform_device *pdev) |
47d37d6f SH |
1748 | { |
1749 | struct mxs_auart_port *s = platform_get_drvdata(pdev); | |
1750 | ||
1751 | uart_remove_one_port(&auart_driver, &s->port); | |
47d37d6f | 1752 | auart_port[pdev->id] = NULL; |
f9e42397 | 1753 | mxs_auart_free_gpio_irq(s); |
47d37d6f SH |
1754 | |
1755 | return 0; | |
1756 | } | |
1757 | ||
1758 | static struct platform_driver mxs_auart_driver = { | |
1759 | .probe = mxs_auart_probe, | |
2d47b716 | 1760 | .remove = mxs_auart_remove, |
47d37d6f SH |
1761 | .driver = { |
1762 | .name = "mxs-auart", | |
1ea6607d | 1763 | .of_match_table = mxs_auart_dt_ids, |
47d37d6f SH |
1764 | }, |
1765 | }; | |
1766 | ||
1767 | static int __init mxs_auart_init(void) | |
1768 | { | |
1769 | int r; | |
1770 | ||
1771 | r = uart_register_driver(&auart_driver); | |
1772 | if (r) | |
1773 | goto out; | |
1774 | ||
1775 | r = platform_driver_register(&mxs_auart_driver); | |
1776 | if (r) | |
1777 | goto out_err; | |
1778 | ||
1779 | return 0; | |
1780 | out_err: | |
1781 | uart_unregister_driver(&auart_driver); | |
1782 | out: | |
1783 | return r; | |
1784 | } | |
1785 | ||
1786 | static void __exit mxs_auart_exit(void) | |
1787 | { | |
1788 | platform_driver_unregister(&mxs_auart_driver); | |
1789 | uart_unregister_driver(&auart_driver); | |
1790 | } | |
1791 | ||
1792 | module_init(mxs_auart_init); | |
1793 | module_exit(mxs_auart_exit); | |
1794 | MODULE_LICENSE("GPL"); | |
1795 | MODULE_DESCRIPTION("Freescale MXS application uart driver"); | |
1ea6607d | 1796 | MODULE_ALIAS("platform:mxs-auart"); |