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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/mason/linux...
[linux-2.6-block.git] / drivers / tty / serial / msm_serial.c
CommitLineData
04896a77 1/*
99edb3d1 2 * Driver for msm7k serial device and console
04896a77
RL		 3 *
4 * Copyright (C) 2007 Google, Inc.
5 * Author: Robert Love <rlove@google.com>
ec8f29e7 6 * Copyright (c) 2011, Code Aurora Forum. All rights reserved.
04896a77
RL		 7 *
8 * This software is licensed under the terms of the GNU General Public
9 * License version 2, as published by the Free Software Foundation, and
10 * may be copied, distributed, and modified under those terms.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
17
18#if defined(CONFIG_SERIAL_MSM_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
19# define SUPPORT_SYSRQ
20#endif
21
cfdad2ab 22#include <linux/atomic.h>
04896a77
RL		 23#include <linux/hrtimer.h>
24#include <linux/module.h>
25#include <linux/io.h>
26#include <linux/ioport.h>
27#include <linux/irq.h>
28#include <linux/init.h>
29#include <linux/console.h>
30#include <linux/tty.h>
31#include <linux/tty_flip.h>
32#include <linux/serial_core.h>
33#include <linux/serial.h>
34#include <linux/clk.h>
35#include <linux/platform_device.h>
ec8f29e7 36#include <linux/delay.h>
cfdad2ab
DB		 37#include <linux/of.h>
38#include <linux/of_device.h>
04896a77
RL		 39
40#include "msm_serial.h"
41
f7e54d7a
SB		 42enum {
43 UARTDM_1P1 = 1,
44 UARTDM_1P2,
45 UARTDM_1P3,
46 UARTDM_1P4,
47};
48
04896a77
RL		 49struct msm_port {
50 struct uart_port uart;
51 char name[16];
52 struct clk *clk;
ec8f29e7 53 struct clk *pclk;
04896a77 54 unsigned int imr;
ec8f29e7
SM		 55 int is_uartdm;
56 unsigned int old_snap_state;
04896a77
RL		 57};
58
4a5662d6 59static inline void wait_for_xmitr(struct uart_port *port)
ec8f29e7 60{
4a5662d6
SB		 61 while (!(msm_read(port, UART_SR) & UART_SR_TX_EMPTY)) {
62 if (msm_read(port, UART_ISR) & UART_ISR_TX_READY)
63 break;
64 udelay(1);
65 }
66 msm_write(port, UART_CR_CMD_RESET_TX_READY, UART_CR);
ec8f29e7
SM		 67}
68
04896a77
RL		 69static void msm_stop_tx(struct uart_port *port)
70{
71 struct msm_port *msm_port = UART_TO_MSM(port);
72
73 msm_port->imr &= ~UART_IMR_TXLEV;
74 msm_write(port, msm_port->imr, UART_IMR);
75}
76
77static void msm_start_tx(struct uart_port *port)
78{
79 struct msm_port *msm_port = UART_TO_MSM(port);
80
81 msm_port->imr |= UART_IMR_TXLEV;
82 msm_write(port, msm_port->imr, UART_IMR);
83}
84
85static void msm_stop_rx(struct uart_port *port)
86{
87 struct msm_port *msm_port = UART_TO_MSM(port);
88
89 msm_port->imr &= ~(UART_IMR_RXLEV | UART_IMR_RXSTALE);
90 msm_write(port, msm_port->imr, UART_IMR);
91}
92
93static void msm_enable_ms(struct uart_port *port)
94{
95 struct msm_port *msm_port = UART_TO_MSM(port);
96
97 msm_port->imr |= UART_IMR_DELTA_CTS;
98 msm_write(port, msm_port->imr, UART_IMR);
99}
100
ec8f29e7
SM		 101static void handle_rx_dm(struct uart_port *port, unsigned int misr)
102{
92a19f9c 103 struct tty_port *tport = &port->state->port;
ec8f29e7
SM		 104 unsigned int sr;
105 int count = 0;
106 struct msm_port *msm_port = UART_TO_MSM(port);
107
108 if ((msm_read(port, UART_SR) & UART_SR_OVERRUN)) {
109 port->icount.overrun++;
92a19f9c 110 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
ec8f29e7
SM		 111 msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR);
112 }
113
114 if (misr & UART_IMR_RXSTALE) {
115 count = msm_read(port, UARTDM_RX_TOTAL_SNAP) -
116 msm_port->old_snap_state;
117 msm_port->old_snap_state = 0;
118 } else {
119 count = 4 * (msm_read(port, UART_RFWR));
120 msm_port->old_snap_state += count;
121 }
122
123 /* TODO: Precise error reporting */
124
125 port->icount.rx += count;
126
127 while (count > 0) {
68252424 128 unsigned char buf[4];
ec8f29e7
SM		 129
130 sr = msm_read(port, UART_SR);
131 if ((sr & UART_SR_RX_READY) == 0) {
132 msm_port->old_snap_state -= count;
133 break;
134 }
68252424 135 ioread32_rep(port->membase + UARTDM_RF, buf, 1);
ec8f29e7
SM		 136 if (sr & UART_SR_RX_BREAK) {
137 port->icount.brk++;
138 if (uart_handle_break(port))
139 continue;
140 } else if (sr & UART_SR_PAR_FRAME_ERR)
141 port->icount.frame++;
142
143 /* TODO: handle sysrq */
68252424 144 tty_insert_flip_string(tport, buf, min(count, 4));
ec8f29e7
SM		 145 count -= 4;
146 }
147
f77232da 148 spin_unlock(&port->lock);
2e124b4a 149 tty_flip_buffer_push(tport);
f77232da
VK		 150 spin_lock(&port->lock);
151
ec8f29e7
SM		 152 if (misr & (UART_IMR_RXSTALE))
153 msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR);
154 msm_write(port, 0xFFFFFF, UARTDM_DMRX);
155 msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR);
156}
157
04896a77
RL		 158static void handle_rx(struct uart_port *port)
159{
92a19f9c 160 struct tty_port *tport = &port->state->port;
04896a77
RL		 161 unsigned int sr;
162
163 /*
164 * Handle overrun. My understanding of the hardware is that overrun
165 * is not tied to the RX buffer, so we handle the case out of band.
166 */
167 if ((msm_read(port, UART_SR) & UART_SR_OVERRUN)) {
168 port->icount.overrun++;
92a19f9c 169 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
04896a77
RL		 170 msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR);
171 }
172
173 /* and now the main RX loop */
174 while ((sr = msm_read(port, UART_SR)) & UART_SR_RX_READY) {
175 unsigned int c;
176 char flag = TTY_NORMAL;
177
178 c = msm_read(port, UART_RF);
179
180 if (sr & UART_SR_RX_BREAK) {
181 port->icount.brk++;
182 if (uart_handle_break(port))
183 continue;
184 } else if (sr & UART_SR_PAR_FRAME_ERR) {
185 port->icount.frame++;
186 } else {
187 port->icount.rx++;
188 }
189
190 /* Mask conditions we're ignorning. */
191 sr &= port->read_status_mask;
192
ddea392e 193 if (sr & UART_SR_RX_BREAK)
04896a77 194 flag = TTY_BREAK;
ddea392e 195 else if (sr & UART_SR_PAR_FRAME_ERR)
04896a77 196 flag = TTY_FRAME;
04896a77
RL		 197
198 if (!uart_handle_sysrq_char(port, c))
92a19f9c 199 tty_insert_flip_char(tport, c, flag);
04896a77
RL		 200 }
201
f77232da 202 spin_unlock(&port->lock);
2e124b4a 203 tty_flip_buffer_push(tport);
f77232da 204 spin_lock(&port->lock);
04896a77
RL		 205}
206
17fae28e 207static void reset_dm_count(struct uart_port *port, int count)
ec8f29e7 208{
4a5662d6 209 wait_for_xmitr(port);
17fae28e 210 msm_write(port, count, UARTDM_NCF_TX);
4a5662d6 211 msm_read(port, UARTDM_NCF_TX);
ec8f29e7
SM		 212}
213
04896a77
RL		 214static void handle_tx(struct uart_port *port)
215{
ebd2c8f6 216 struct circ_buf *xmit = &port->state->xmit;
04896a77 217 struct msm_port *msm_port = UART_TO_MSM(port);
17fae28e
SB		 218 unsigned int tx_count, num_chars;
219 unsigned int tf_pointer = 0;
68252424
SB		 220 void __iomem *tf;
221
222 if (msm_port->is_uartdm)
223 tf = port->membase + UARTDM_TF;
224 else
225 tf = port->membase + UART_TF;
17fae28e
SB		 226
227 tx_count = uart_circ_chars_pending(xmit);
228 tx_count = min3(tx_count, (unsigned int)UART_XMIT_SIZE - xmit->tail,
229 port->fifosize);
04896a77
RL		 230
231 if (port->x_char) {
ec8f29e7 232 if (msm_port->is_uartdm)
17fae28e 233 reset_dm_count(port, tx_count + 1);
ec8f29e7 234
68252424 235 iowrite8_rep(tf, &port->x_char, 1);
04896a77
RL		 236 port->icount.tx++;
237 port->x_char = 0;
17fae28e
SB		 238 } else if (tx_count && msm_port->is_uartdm) {
239 reset_dm_count(port, tx_count);
04896a77
RL		 240 }
241
17fae28e
SB		 242 while (tf_pointer < tx_count) {
243 int i;
244 char buf[4] = { 0 };
ec8f29e7 245
17fae28e 246 if (!(msm_read(port, UART_SR) & UART_SR_TX_READY))
04896a77 247 break;
04896a77 248
ec8f29e7 249 if (msm_port->is_uartdm)
4f749f24
JH		 250 num_chars = min(tx_count - tf_pointer,
251 (unsigned int)sizeof(buf));
17fae28e
SB		 252 else
253 num_chars = 1;
04896a77 254
17fae28e
SB		 255 for (i = 0; i < num_chars; i++) {
256 buf[i] = xmit->buf[xmit->tail + i];
257 port->icount.tx++;
258 }
259
68252424 260 iowrite32_rep(tf, buf, 1);
17fae28e
SB		 261 xmit->tail = (xmit->tail + num_chars) & (UART_XMIT_SIZE - 1);
262 tf_pointer += num_chars;
04896a77
RL		 263 }
264
17fae28e
SB		 265 /* disable tx interrupts if nothing more to send */
266 if (uart_circ_empty(xmit))
267 msm_stop_tx(port);
268
04896a77
RL		 269 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
270 uart_write_wakeup(port);
271}
272
273static void handle_delta_cts(struct uart_port *port)
274{
275 msm_write(port, UART_CR_CMD_RESET_CTS, UART_CR);
276 port->icount.cts++;
bdc04e31 277 wake_up_interruptible(&port->state->port.delta_msr_wait);
04896a77
RL		 278}
279
280static irqreturn_t msm_irq(int irq, void *dev_id)
281{
282 struct uart_port *port = dev_id;
283 struct msm_port *msm_port = UART_TO_MSM(port);
284 unsigned int misr;
285
286 spin_lock(&port->lock);
287 misr = msm_read(port, UART_MISR);
288 msm_write(port, 0, UART_IMR); /* disable interrupt */
289
ec8f29e7
SM		 290 if (misr & (UART_IMR_RXLEV | UART_IMR_RXSTALE)) {
291 if (msm_port->is_uartdm)
292 handle_rx_dm(port, misr);
293 else
294 handle_rx(port);
295 }
04896a77
RL		 296 if (misr & UART_IMR_TXLEV)
297 handle_tx(port);
298 if (misr & UART_IMR_DELTA_CTS)
299 handle_delta_cts(port);
300
301 msm_write(port, msm_port->imr, UART_IMR); /* restore interrupt */
302 spin_unlock(&port->lock);
303
304 return IRQ_HANDLED;
305}
306
307static unsigned int msm_tx_empty(struct uart_port *port)
308{
309 return (msm_read(port, UART_SR) & UART_SR_TX_EMPTY) ? TIOCSER_TEMT : 0;
310}
311
312static unsigned int msm_get_mctrl(struct uart_port *port)
313{
314 return TIOCM_CAR | TIOCM_CTS | TIOCM_DSR | TIOCM_RTS;
315}
316
ec8f29e7 317static void msm_reset(struct uart_port *port)
04896a77 318{
f7e54d7a
SB		 319 struct msm_port *msm_port = UART_TO_MSM(port);
320
ec8f29e7
SM		 321 /* reset everything */
322 msm_write(port, UART_CR_CMD_RESET_RX, UART_CR);
323 msm_write(port, UART_CR_CMD_RESET_TX, UART_CR);
324 msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR);
325 msm_write(port, UART_CR_CMD_RESET_BREAK_INT, UART_CR);
326 msm_write(port, UART_CR_CMD_RESET_CTS, UART_CR);
327 msm_write(port, UART_CR_CMD_SET_RFR, UART_CR);
f7e54d7a
SB		 328
329 /* Disable DM modes */
330 if (msm_port->is_uartdm)
331 msm_write(port, 0, UARTDM_DMEN);
ec8f29e7 332}
04896a77 333
f8fb952f 334static void msm_set_mctrl(struct uart_port *port, unsigned int mctrl)
ec8f29e7
SM		 335{
336 unsigned int mr;
e919cefb 337
04896a77
RL		 338 mr = msm_read(port, UART_MR1);
339
340 if (!(mctrl & TIOCM_RTS)) {
341 mr &= ~UART_MR1_RX_RDY_CTL;
342 msm_write(port, mr, UART_MR1);
343 msm_write(port, UART_CR_CMD_RESET_RFR, UART_CR);
344 } else {
345 mr |= UART_MR1_RX_RDY_CTL;
346 msm_write(port, mr, UART_MR1);
347 }
348}
349
350static void msm_break_ctl(struct uart_port *port, int break_ctl)
351{
352 if (break_ctl)
353 msm_write(port, UART_CR_CMD_START_BREAK, UART_CR);
354 else
355 msm_write(port, UART_CR_CMD_STOP_BREAK, UART_CR);
356}
357
6909dadd
SB		 358struct msm_baud_map {
359 u16 divisor;
360 u8 code;
361 u8 rxstale;
362};
363
364static const struct msm_baud_map *
365msm_find_best_baud(struct uart_port *port, unsigned int baud)
366{
367 unsigned int i, divisor;
368 const struct msm_baud_map *entry;
369 static const struct msm_baud_map table[] = {
370 { 1536, 0x00, 1 },
371 { 768, 0x11, 1 },
372 { 384, 0x22, 1 },
373 { 192, 0x33, 1 },
374 { 96, 0x44, 1 },
375 { 48, 0x55, 1 },
376 { 32, 0x66, 1 },
377 { 24, 0x77, 1 },
378 { 16, 0x88, 1 },
379 { 12, 0x99, 6 },
380 { 8, 0xaa, 6 },
381 { 6, 0xbb, 6 },
382 { 4, 0xcc, 6 },
383 { 3, 0xdd, 8 },
384 { 2, 0xee, 16 },
385 { 1, 0xff, 31 },
386 };
387
388 divisor = uart_get_divisor(port, baud);
389
390 for (i = 0, entry = table; i < ARRAY_SIZE(table); i++, entry++)
391 if (entry->divisor <= divisor)
392 break;
393
394 return entry; /* Default to smallest divider */
395}
396
44da59e4 397static int msm_set_baud_rate(struct uart_port *port, unsigned int baud)
04896a77 398{
6909dadd 399 unsigned int rxstale, watermark;
ec8f29e7 400 struct msm_port *msm_port = UART_TO_MSM(port);
6909dadd 401 const struct msm_baud_map *entry;
04896a77 402
6909dadd 403 entry = msm_find_best_baud(port, baud);
04896a77 404
ec8f29e7
SM		 405 if (msm_port->is_uartdm)
406 msm_write(port, UART_CR_CMD_RESET_RX, UART_CR);
407
6909dadd 408 msm_write(port, entry->code, UART_CSR);
04896a77
RL		 409
410 /* RX stale watermark */
6909dadd 411 rxstale = entry->rxstale;
04896a77
RL		 412 watermark = UART_IPR_STALE_LSB & rxstale;
413 watermark |= UART_IPR_RXSTALE_LAST;
414 watermark |= UART_IPR_STALE_TIMEOUT_MSB & (rxstale << 2);
415 msm_write(port, watermark, UART_IPR);
416
417 /* set RX watermark */
418 watermark = (port->fifosize * 3) / 4;
419 msm_write(port, watermark, UART_RFWR);
420
421 /* set TX watermark */
422 msm_write(port, 10, UART_TFWR);
44da59e4 423
ec8f29e7
SM		 424 if (msm_port->is_uartdm) {
425 msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR);
426 msm_write(port, 0xFFFFFF, UARTDM_DMRX);
427 msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR);
428 }
429
44da59e4 430 return baud;
04896a77
RL		 431}
432
04896a77
RL		 433static void msm_init_clock(struct uart_port *port)
434{
435 struct msm_port *msm_port = UART_TO_MSM(port);
436
f98cf83d 437 clk_prepare_enable(msm_port->clk);
bfaddb7d 438 clk_prepare_enable(msm_port->pclk);
18c79d76 439 msm_serial_set_mnd_regs(port);
04896a77
RL		 440}
441
442static int msm_startup(struct uart_port *port)
443{
444 struct msm_port *msm_port = UART_TO_MSM(port);
445 unsigned int data, rfr_level;
446 int ret;
447
448 snprintf(msm_port->name, sizeof(msm_port->name),
449 "msm_serial%d", port->line);
450
451 ret = request_irq(port->irq, msm_irq, IRQF_TRIGGER_HIGH,
452 msm_port->name, port);
453 if (unlikely(ret))
454 return ret;
455
456 msm_init_clock(port);
457
458 if (likely(port->fifosize > 12))
459 rfr_level = port->fifosize - 12;
460 else
461 rfr_level = port->fifosize;
462
463 /* set automatic RFR level */
464 data = msm_read(port, UART_MR1);
465 data &= ~UART_MR1_AUTO_RFR_LEVEL1;
466 data &= ~UART_MR1_AUTO_RFR_LEVEL0;
467 data |= UART_MR1_AUTO_RFR_LEVEL1 & (rfr_level << 2);
468 data |= UART_MR1_AUTO_RFR_LEVEL0 & rfr_level;
469 msm_write(port, data, UART_MR1);
470
471 /* make sure that RXSTALE count is non-zero */
472 data = msm_read(port, UART_IPR);
473 if (unlikely(!data)) {
474 data |= UART_IPR_RXSTALE_LAST;
475 data |= UART_IPR_STALE_LSB;
476 msm_write(port, data, UART_IPR);
477 }
478
ec8f29e7
SM		 479 data = 0;
480 if (!port->cons || (port->cons && !(port->cons->flags & CON_ENABLED))) {
481 msm_write(port, UART_CR_CMD_PROTECTION_EN, UART_CR);
482 msm_reset(port);
483 data = UART_CR_TX_ENABLE;
484 }
485
486 data |= UART_CR_RX_ENABLE;
487 msm_write(port, data, UART_CR); /* enable TX & RX */
04896a77 488
ec8f29e7
SM		 489 /* Make sure IPR is not 0 to start with*/
490 if (msm_port->is_uartdm)
491 msm_write(port, UART_IPR_STALE_LSB, UART_IPR);
04896a77
RL		 492
493 /* turn on RX and CTS interrupts */
494 msm_port->imr = UART_IMR_RXLEV | UART_IMR_RXSTALE |
495 UART_IMR_CURRENT_CTS;
04896a77 496
ec8f29e7
SM		 497 if (msm_port->is_uartdm) {
498 msm_write(port, 0xFFFFFF, UARTDM_DMRX);
499 msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR);
500 msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR);
501 }
502
503 msm_write(port, msm_port->imr, UART_IMR);
04896a77
RL		 504 return 0;
505}
506
507static void msm_shutdown(struct uart_port *port)
508{
509 struct msm_port *msm_port = UART_TO_MSM(port);
510
511 msm_port->imr = 0;
512 msm_write(port, 0, UART_IMR); /* disable interrupts */
513
f98cf83d 514 clk_disable_unprepare(msm_port->clk);
04896a77
RL		 515
516 free_irq(port->irq, port);
517}
518
519static void msm_set_termios(struct uart_port *port, struct ktermios *termios,
520 struct ktermios *old)
521{
522 unsigned long flags;
523 unsigned int baud, mr;
524
525 spin_lock_irqsave(&port->lock, flags);
526
527 /* calculate and set baud rate */
528 baud = uart_get_baud_rate(port, termios, old, 300, 115200);
44da59e4
AC		 529 baud = msm_set_baud_rate(port, baud);
530 if (tty_termios_baud_rate(termios))
531 tty_termios_encode_baud_rate(termios, baud, baud);
ec8f29e7 532
04896a77
RL		 533 /* calculate parity */
534 mr = msm_read(port, UART_MR2);
535 mr &= ~UART_MR2_PARITY_MODE;
536 if (termios->c_cflag & PARENB) {
537 if (termios->c_cflag & PARODD)
538 mr |= UART_MR2_PARITY_MODE_ODD;
539 else if (termios->c_cflag & CMSPAR)
540 mr |= UART_MR2_PARITY_MODE_SPACE;
541 else
542 mr |= UART_MR2_PARITY_MODE_EVEN;
543 }
544
545 /* calculate bits per char */
546 mr &= ~UART_MR2_BITS_PER_CHAR;
547 switch (termios->c_cflag & CSIZE) {
548 case CS5:
549 mr |= UART_MR2_BITS_PER_CHAR_5;
550 break;
551 case CS6:
552 mr |= UART_MR2_BITS_PER_CHAR_6;
553 break;
554 case CS7:
555 mr |= UART_MR2_BITS_PER_CHAR_7;
556 break;
557 case CS8:
558 default:
559 mr |= UART_MR2_BITS_PER_CHAR_8;
560 break;
561 }
562
563 /* calculate stop bits */
564 mr &= ~(UART_MR2_STOP_BIT_LEN_ONE | UART_MR2_STOP_BIT_LEN_TWO);
565 if (termios->c_cflag & CSTOPB)
566 mr |= UART_MR2_STOP_BIT_LEN_TWO;
567 else
568 mr |= UART_MR2_STOP_BIT_LEN_ONE;
569
570 /* set parity, bits per char, and stop bit */
571 msm_write(port, mr, UART_MR2);
572
573 /* calculate and set hardware flow control */
574 mr = msm_read(port, UART_MR1);
575 mr &= ~(UART_MR1_CTS_CTL | UART_MR1_RX_RDY_CTL);
576 if (termios->c_cflag & CRTSCTS) {
577 mr |= UART_MR1_CTS_CTL;
578 mr |= UART_MR1_RX_RDY_CTL;
579 }
580 msm_write(port, mr, UART_MR1);
581
582 /* Configure status bits to ignore based on termio flags. */
583 port->read_status_mask = 0;
584 if (termios->c_iflag & INPCK)
585 port->read_status_mask |= UART_SR_PAR_FRAME_ERR;
ef8b9ddc 586 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
04896a77
RL		 587 port->read_status_mask |= UART_SR_RX_BREAK;
588
589 uart_update_timeout(port, termios->c_cflag, baud);
590
591 spin_unlock_irqrestore(&port->lock, flags);
592}
593
594static const char *msm_type(struct uart_port *port)
595{
596 return "MSM";
597}
598
599static void msm_release_port(struct uart_port *port)
600{
601 struct platform_device *pdev = to_platform_device(port->dev);
ec8f29e7 602 struct resource *uart_resource;
04896a77
RL		 603 resource_size_t size;
604
ec8f29e7
SM		 605 uart_resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
606 if (unlikely(!uart_resource))
04896a77 607 return;
ec8f29e7 608 size = resource_size(uart_resource);
04896a77
RL		 609
610 release_mem_region(port->mapbase, size);
611 iounmap(port->membase);
612 port->membase = NULL;
613}
614
615static int msm_request_port(struct uart_port *port)
616{
617 struct platform_device *pdev = to_platform_device(port->dev);
ec8f29e7 618 struct resource *uart_resource;
04896a77 619 resource_size_t size;
ec8f29e7 620 int ret;
04896a77 621
886a451b 622 uart_resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
ec8f29e7 623 if (unlikely(!uart_resource))
04896a77 624 return -ENXIO;
04896a77 625
ec8f29e7
SM		 626 size = resource_size(uart_resource);
627
628 if (!request_mem_region(port->mapbase, size, "msm_serial"))
04896a77
RL		 629 return -EBUSY;
630
631 port->membase = ioremap(port->mapbase, size);
632 if (!port->membase) {
ec8f29e7
SM		 633 ret = -EBUSY;
634 goto fail_release_port;
635 }
636
04896a77 637 return 0;
ec8f29e7 638
ec8f29e7
SM		 639fail_release_port:
640 release_mem_region(port->mapbase, size);
641 return ret;
04896a77
RL		 642}
643
644static void msm_config_port(struct uart_port *port, int flags)
645{
ec8f29e7 646 int ret;
e919cefb 647
04896a77
RL		 648 if (flags & UART_CONFIG_TYPE) {
649 port->type = PORT_MSM;
ec8f29e7
SM		 650 ret = msm_request_port(port);
651 if (ret)
652 return;
04896a77
RL		 653 }
654}
655
656static int msm_verify_port(struct uart_port *port, struct serial_struct *ser)
657{
658 if (unlikely(ser->type != PORT_UNKNOWN && ser->type != PORT_MSM))
659 return -EINVAL;
660 if (unlikely(port->irq != ser->irq))
661 return -EINVAL;
662 return 0;
663}
664
665static void msm_power(struct uart_port *port, unsigned int state,
666 unsigned int oldstate)
667{
668 struct msm_port *msm_port = UART_TO_MSM(port);
669
670 switch (state) {
671 case 0:
f98cf83d 672 clk_prepare_enable(msm_port->clk);
bfaddb7d 673 clk_prepare_enable(msm_port->pclk);
04896a77
RL		 674 break;
675 case 3:
f98cf83d 676 clk_disable_unprepare(msm_port->clk);
bfaddb7d 677 clk_disable_unprepare(msm_port->pclk);
04896a77
RL		 678 break;
679 default:
6a7cfe46 680 pr_err("msm_serial: Unknown PM state %d\n", state);
04896a77
RL		 681 }
682}
683
f7e54d7a 684#ifdef CONFIG_CONSOLE_POLL
f7e54d7a
SB		 685static int msm_poll_get_char_single(struct uart_port *port)
686{
687 struct msm_port *msm_port = UART_TO_MSM(port);
688 unsigned int rf_reg = msm_port->is_uartdm ? UARTDM_RF : UART_RF;
689
690 if (!(msm_read(port, UART_SR) & UART_SR_RX_READY))
691 return NO_POLL_CHAR;
6f47abcb
KP		 692
693 return msm_read(port, rf_reg) & 0xff;
f7e54d7a
SB		 694}
695
8b374399 696static int msm_poll_get_char_dm(struct uart_port *port)
f7e54d7a
SB		 697{
698 int c;
699 static u32 slop;
700 static int count;
701 unsigned char *sp = (unsigned char *)&slop;
702
703 /* Check if a previous read had more than one char */
704 if (count) {
705 c = sp[sizeof(slop) - count];
706 count--;
707 /* Or if FIFO is empty */
708 } else if (!(msm_read(port, UART_SR) & UART_SR_RX_READY)) {
709 /*
710 * If RX packing buffer has less than a word, force stale to
711 * push contents into RX FIFO
712 */
713 count = msm_read(port, UARTDM_RXFS);
714 count = (count >> UARTDM_RXFS_BUF_SHIFT) & UARTDM_RXFS_BUF_MASK;
715 if (count) {
716 msm_write(port, UART_CR_CMD_FORCE_STALE, UART_CR);
717 slop = msm_read(port, UARTDM_RF);
718 c = sp[0];
719 count--;
8b374399
SB		 720 msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR);
721 msm_write(port, 0xFFFFFF, UARTDM_DMRX);
722 msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE,
723 UART_CR);
f7e54d7a
SB		 724 } else {
725 c = NO_POLL_CHAR;
726 }
727 /* FIFO has a word */
728 } else {
729 slop = msm_read(port, UARTDM_RF);
730 c = sp[0];
731 count = sizeof(slop) - 1;
732 }
733
734 return c;
735}
736
737static int msm_poll_get_char(struct uart_port *port)
738{
739 u32 imr;
740 int c;
741 struct msm_port *msm_port = UART_TO_MSM(port);
742
743 /* Disable all interrupts */
744 imr = msm_read(port, UART_IMR);
745 msm_write(port, 0, UART_IMR);
746
8b374399
SB		 747 if (msm_port->is_uartdm)
748 c = msm_poll_get_char_dm(port);
f7e54d7a
SB		 749 else
750 c = msm_poll_get_char_single(port);
751
752 /* Enable interrupts */
753 msm_write(port, imr, UART_IMR);
754
755 return c;
756}
757
758static void msm_poll_put_char(struct uart_port *port, unsigned char c)
759{
760 u32 imr;
761 struct msm_port *msm_port = UART_TO_MSM(port);
762
763 /* Disable all interrupts */
764 imr = msm_read(port, UART_IMR);
765 msm_write(port, 0, UART_IMR);
766
767 if (msm_port->is_uartdm)
768 reset_dm_count(port, 1);
769
770 /* Wait until FIFO is empty */
771 while (!(msm_read(port, UART_SR) & UART_SR_TX_READY))
772 cpu_relax();
773
774 /* Write a character */
775 msm_write(port, c, msm_port->is_uartdm ? UARTDM_TF : UART_TF);
776
777 /* Wait until FIFO is empty */
778 while (!(msm_read(port, UART_SR) & UART_SR_TX_READY))
779 cpu_relax();
780
781 /* Enable interrupts */
782 msm_write(port, imr, UART_IMR);
f7e54d7a
SB		 783}
784#endif
785
04896a77
RL		 786static struct uart_ops msm_uart_pops = {
787 .tx_empty = msm_tx_empty,
788 .set_mctrl = msm_set_mctrl,
789 .get_mctrl = msm_get_mctrl,
790 .stop_tx = msm_stop_tx,
791 .start_tx = msm_start_tx,
792 .stop_rx = msm_stop_rx,
793 .enable_ms = msm_enable_ms,
794 .break_ctl = msm_break_ctl,
795 .startup = msm_startup,
796 .shutdown = msm_shutdown,
797 .set_termios = msm_set_termios,
798 .type = msm_type,
799 .release_port = msm_release_port,
800 .request_port = msm_request_port,
801 .config_port = msm_config_port,
802 .verify_port = msm_verify_port,
803 .pm = msm_power,
f7e54d7a 804#ifdef CONFIG_CONSOLE_POLL
f7e54d7a
SB		 805 .poll_get_char = msm_poll_get_char,
806 .poll_put_char = msm_poll_put_char,
807#endif
04896a77
RL		 808};
809
810static struct msm_port msm_uart_ports[] = {
811 {
812 .uart = {
813 .iotype = UPIO_MEM,
814 .ops = &msm_uart_pops,
815 .flags = UPF_BOOT_AUTOCONF,
ec8f29e7 816 .fifosize = 64,
04896a77
RL		 817 .line = 0,
818 },
819 },
820 {
821 .uart = {
822 .iotype = UPIO_MEM,
823 .ops = &msm_uart_pops,
824 .flags = UPF_BOOT_AUTOCONF,
ec8f29e7 825 .fifosize = 64,
04896a77
RL		 826 .line = 1,
827 },
828 },
829 {
830 .uart = {
831 .iotype = UPIO_MEM,
832 .ops = &msm_uart_pops,
833 .flags = UPF_BOOT_AUTOCONF,
834 .fifosize = 64,
835 .line = 2,
836 },
837 },
838};
839
840#define UART_NR ARRAY_SIZE(msm_uart_ports)
841
842static inline struct uart_port *get_port_from_line(unsigned int line)
843{
844 return &msm_uart_ports[line].uart;
845}
846
847#ifdef CONFIG_SERIAL_MSM_CONSOLE
0efe7296
SB		 848static void __msm_console_write(struct uart_port *port, const char *s,
849 unsigned int count, bool is_uartdm)
04896a77 850{
a3957e80 851 int i;
a3957e80
SB		 852 int num_newlines = 0;
853 bool replaced = false;
68252424 854 void __iomem *tf;
04896a77 855
0efe7296 856 if (is_uartdm)
68252424
SB		 857 tf = port->membase + UARTDM_TF;
858 else
859 tf = port->membase + UART_TF;
860
a3957e80
SB		 861 /* Account for newlines that will get a carriage return added */
862 for (i = 0; i < count; i++)
863 if (s[i] == '\n')
864 num_newlines++;
865 count += num_newlines;
866
04896a77 867 spin_lock(&port->lock);
0efe7296 868 if (is_uartdm)
a3957e80
SB		 869 reset_dm_count(port, count);
870
871 i = 0;
872 while (i < count) {
873 int j;
874 unsigned int num_chars;
875 char buf[4] = { 0 };
a3957e80 876
0efe7296 877 if (is_uartdm)
a3957e80
SB		 878 num_chars = min(count - i, (unsigned int)sizeof(buf));
879 else
880 num_chars = 1;
881
882 for (j = 0; j < num_chars; j++) {
883 char c = *s;
884
885 if (c == '\n' && !replaced) {
886 buf[j] = '\r';
887 j++;
888 replaced = true;
889 }
890 if (j < num_chars) {
891 buf[j] = c;
892 s++;
893 replaced = false;
894 }
895 }
896
897 while (!(msm_read(port, UART_SR) & UART_SR_TX_READY))
898 cpu_relax();
899
68252424 900 iowrite32_rep(tf, buf, 1);
a3957e80
SB		 901 i += num_chars;
902 }
04896a77
RL		 903 spin_unlock(&port->lock);
904}
905
0efe7296
SB		 906static void msm_console_write(struct console *co, const char *s,
907 unsigned int count)
908{
909 struct uart_port *port;
910 struct msm_port *msm_port;
911
912 BUG_ON(co->index < 0 || co->index >= UART_NR);
913
914 port = get_port_from_line(co->index);
915 msm_port = UART_TO_MSM(port);
916
917 __msm_console_write(port, s, count, msm_port->is_uartdm);
918}
919
04896a77
RL		 920static int __init msm_console_setup(struct console *co, char *options)
921{
922 struct uart_port *port;
ec8f29e7 923 struct msm_port *msm_port;
2b844ad2 924 int baud = 0, flow, bits, parity;
04896a77
RL		 925
926 if (unlikely(co->index >= UART_NR || co->index < 0))
927 return -ENXIO;
928
929 port = get_port_from_line(co->index);
ec8f29e7 930 msm_port = UART_TO_MSM(port);
04896a77
RL		 931
932 if (unlikely(!port->membase))
933 return -ENXIO;
934
04896a77
RL		 935 msm_init_clock(port);
936
937 if (options)
938 uart_parse_options(options, &baud, &parity, &bits, &flow);
939
940 bits = 8;
941 parity = 'n';
942 flow = 'n';
943 msm_write(port, UART_MR2_BITS_PER_CHAR_8 | UART_MR2_STOP_BIT_LEN_ONE,
944 UART_MR2); /* 8N1 */
945
946 if (baud < 300 || baud > 115200)
947 baud = 115200;
948 msm_set_baud_rate(port, baud);
949
950 msm_reset(port);
951
ec8f29e7
SM		 952 if (msm_port->is_uartdm) {
953 msm_write(port, UART_CR_CMD_PROTECTION_EN, UART_CR);
954 msm_write(port, UART_CR_TX_ENABLE, UART_CR);
955 }
956
6a7cfe46 957 pr_info("msm_serial: console setup on port #%d\n", port->line);
04896a77
RL		 958
959 return uart_set_options(port, co, baud, parity, bits, flow);
960}
961
0efe7296
SB		 962static void
963msm_serial_early_write(struct console *con, const char *s, unsigned n)
964{
965 struct earlycon_device *dev = con->data;
966
967 __msm_console_write(&dev->port, s, n, false);
968}
969
970static int __init
971msm_serial_early_console_setup(struct earlycon_device *device, const char *opt)
972{
973 if (!device->port.membase)
974 return -ENODEV;
975
976 device->con->write = msm_serial_early_write;
977 return 0;
978}
979EARLYCON_DECLARE(msm_serial, msm_serial_early_console_setup);
980OF_EARLYCON_DECLARE(msm_serial, "qcom,msm-uart",
981 msm_serial_early_console_setup);
982
983static void
984msm_serial_early_write_dm(struct console *con, const char *s, unsigned n)
985{
986 struct earlycon_device *dev = con->data;
987
988 __msm_console_write(&dev->port, s, n, true);
989}
990
991static int __init
992msm_serial_early_console_setup_dm(struct earlycon_device *device,
993 const char *opt)
994{
995 if (!device->port.membase)
996 return -ENODEV;
997
998 device->con->write = msm_serial_early_write_dm;
999 return 0;
1000}
1001EARLYCON_DECLARE(msm_serial_dm, msm_serial_early_console_setup_dm);
1002OF_EARLYCON_DECLARE(msm_serial_dm, "qcom,msm-uartdm",
1003 msm_serial_early_console_setup_dm);
1004
04896a77
RL		 1005static struct uart_driver msm_uart_driver;
1006
1007static struct console msm_console = {
1008 .name = "ttyMSM",
1009 .write = msm_console_write,
1010 .device = uart_console_device,
1011 .setup = msm_console_setup,
1012 .flags = CON_PRINTBUFFER,
1013 .index = -1,
1014 .data = &msm_uart_driver,
1015};
1016
1017#define MSM_CONSOLE (&msm_console)
1018
1019#else
1020#define MSM_CONSOLE NULL
1021#endif
1022
1023static struct uart_driver msm_uart_driver = {
1024 .owner = THIS_MODULE,
1025 .driver_name = "msm_serial",
1026 .dev_name = "ttyMSM",
1027 .nr = UART_NR,
1028 .cons = MSM_CONSOLE,
1029};
1030
cfdad2ab
DB		 1031static atomic_t msm_uart_next_id = ATOMIC_INIT(0);
1032
c3b5d3be 1033static const struct of_device_id msm_uartdm_table[] = {
f7e54d7a
SB		 1034 { .compatible = "qcom,msm-uartdm-v1.1", .data = (void *)UARTDM_1P1 },
1035 { .compatible = "qcom,msm-uartdm-v1.2", .data = (void *)UARTDM_1P2 },
1036 { .compatible = "qcom,msm-uartdm-v1.3", .data = (void *)UARTDM_1P3 },
1037 { .compatible = "qcom,msm-uartdm-v1.4", .data = (void *)UARTDM_1P4 },
c3b5d3be
SB		 1038 { }
1039};
1040
4cc29462 1041static int msm_serial_probe(struct platform_device *pdev)
04896a77
RL		 1042{
1043 struct msm_port *msm_port;
1044 struct resource *resource;
1045 struct uart_port *port;
f7e54d7a 1046 const struct of_device_id *id;
1e091751 1047 int irq;
04896a77 1048
cfdad2ab
DB		 1049 if (pdev->id == -1)
1050 pdev->id = atomic_inc_return(&msm_uart_next_id) - 1;
1051
04896a77
RL		 1052 if (unlikely(pdev->id < 0 || pdev->id >= UART_NR))
1053 return -ENXIO;
1054
6a7cfe46 1055 dev_info(&pdev->dev, "msm_serial: detected port #%d\n", pdev->id);
04896a77
RL		 1056
1057 port = get_port_from_line(pdev->id);
1058 port->dev = &pdev->dev;
1059 msm_port = UART_TO_MSM(port);
1060
f7e54d7a
SB		 1061 id = of_match_device(msm_uartdm_table, &pdev->dev);
1062 if (id)
1063 msm_port->is_uartdm = (unsigned long)id->data;
ec8f29e7
SM		 1064 else
1065 msm_port->is_uartdm = 0;
1066
bfaddb7d 1067 msm_port->clk = devm_clk_get(&pdev->dev, "core");
519b371d
SB		 1068 if (IS_ERR(msm_port->clk))
1069 return PTR_ERR(msm_port->clk);
1070
1071 if (msm_port->is_uartdm) {
bfaddb7d 1072 msm_port->pclk = devm_clk_get(&pdev->dev, "iface");
519b371d
SB		 1073 if (IS_ERR(msm_port->pclk))
1074 return PTR_ERR(msm_port->pclk);
ec8f29e7 1075
7b6031a7 1076 clk_set_rate(msm_port->clk, 1843200);
519b371d 1077 }
ec8f29e7 1078
04896a77 1079 port->uartclk = clk_get_rate(msm_port->clk);
6a7cfe46 1080 dev_info(&pdev->dev, "uartclk = %d\n", port->uartclk);
04896a77 1081
886a451b 1082 resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
04896a77
RL		 1083 if (unlikely(!resource))
1084 return -ENXIO;
1085 port->mapbase = resource->start;
1086
1e091751
RK		 1087 irq = platform_get_irq(pdev, 0);
1088 if (unlikely(irq < 0))
04896a77 1089 return -ENXIO;
1e091751 1090 port->irq = irq;
04896a77
RL		 1091
1092 platform_set_drvdata(pdev, port);
1093
1094 return uart_add_one_port(&msm_uart_driver, port);
1095}
1096
ae8d8a14 1097static int msm_serial_remove(struct platform_device *pdev)
04896a77 1098{
519b371d 1099 struct uart_port *port = platform_get_drvdata(pdev);
04896a77 1100
519b371d 1101 uart_remove_one_port(&msm_uart_driver, port);
04896a77
RL		 1102
1103 return 0;
1104}
1105
af300539 1106static const struct of_device_id msm_match_table[] = {
cfdad2ab 1107 { .compatible = "qcom,msm-uart" },
c3b5d3be 1108 { .compatible = "qcom,msm-uartdm" },
cfdad2ab
DB		 1109 {}
1110};
1111
04896a77 1112static struct platform_driver msm_platform_driver = {
04896a77 1113 .remove = msm_serial_remove,
31964ffe 1114 .probe = msm_serial_probe,
04896a77
RL		 1115 .driver = {
1116 .name = "msm_serial",
1117 .owner = THIS_MODULE,
cfdad2ab 1118 .of_match_table = msm_match_table,
04896a77
RL		 1119 },
1120};
1121
1122static int __init msm_serial_init(void)
1123{
1124 int ret;
1125
1126 ret = uart_register_driver(&msm_uart_driver);
1127 if (unlikely(ret))
1128 return ret;
1129
31964ffe 1130 ret = platform_driver_register(&msm_platform_driver);
04896a77
RL		 1131 if (unlikely(ret))
1132 uart_unregister_driver(&msm_uart_driver);
1133
6a7cfe46 1134 pr_info("msm_serial: driver initialized\n");
04896a77
RL		 1135
1136 return ret;
1137}
1138
1139static void __exit msm_serial_exit(void)
1140{
1141#ifdef CONFIG_SERIAL_MSM_CONSOLE
1142 unregister_console(&msm_console);
1143#endif
1144 platform_driver_unregister(&msm_platform_driver);
1145 uart_unregister_driver(&msm_uart_driver);
1146}
1147
1148module_init(msm_serial_init);
1149module_exit(msm_serial_exit);
1150
1151MODULE_AUTHOR("Robert Love <rlove@google.com>");
1152MODULE_DESCRIPTION("Driver for msm7x serial device");
1153MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)