Commit | Line | Data |
---|---|---|
04896a77 | 1 | /* |
99edb3d1 | 2 | * Driver for msm7k serial device and console |
04896a77 RL |
3 | * |
4 | * Copyright (C) 2007 Google, Inc. | |
5 | * Author: Robert Love <rlove@google.com> | |
ec8f29e7 | 6 | * Copyright (c) 2011, Code Aurora Forum. All rights reserved. |
04896a77 RL |
7 | * |
8 | * This software is licensed under the terms of the GNU General Public | |
9 | * License version 2, as published by the Free Software Foundation, and | |
10 | * may be copied, distributed, and modified under those terms. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | */ | |
17 | ||
18 | #if defined(CONFIG_SERIAL_MSM_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) | |
19 | # define SUPPORT_SYSRQ | |
20 | #endif | |
21 | ||
e4276ff8 | 22 | #include <linux/kernel.h> |
cfdad2ab | 23 | #include <linux/atomic.h> |
3a878c43 II |
24 | #include <linux/dma-mapping.h> |
25 | #include <linux/dmaengine.h> | |
04896a77 RL |
26 | #include <linux/module.h> |
27 | #include <linux/io.h> | |
28 | #include <linux/ioport.h> | |
e4276ff8 | 29 | #include <linux/interrupt.h> |
04896a77 RL |
30 | #include <linux/init.h> |
31 | #include <linux/console.h> | |
32 | #include <linux/tty.h> | |
33 | #include <linux/tty_flip.h> | |
34 | #include <linux/serial_core.h> | |
99693945 | 35 | #include <linux/slab.h> |
04896a77 RL |
36 | #include <linux/clk.h> |
37 | #include <linux/platform_device.h> | |
ec8f29e7 | 38 | #include <linux/delay.h> |
cfdad2ab DB |
39 | #include <linux/of.h> |
40 | #include <linux/of_device.h> | |
e4276ff8 | 41 | #include <linux/wait.h> |
04896a77 | 42 | |
32173741 | 43 | #define UART_MR1 0x0000 |
04896a77 | 44 | |
32173741 SB |
45 | #define UART_MR1_AUTO_RFR_LEVEL0 0x3F |
46 | #define UART_MR1_AUTO_RFR_LEVEL1 0x3FF00 | |
47 | #define UART_DM_MR1_AUTO_RFR_LEVEL1 0xFFFFFF00 | |
48 | #define UART_MR1_RX_RDY_CTL BIT(7) | |
49 | #define UART_MR1_CTS_CTL BIT(6) | |
50 | ||
51 | #define UART_MR2 0x0004 | |
52 | #define UART_MR2_ERROR_MODE BIT(6) | |
53 | #define UART_MR2_BITS_PER_CHAR 0x30 | |
54 | #define UART_MR2_BITS_PER_CHAR_5 (0x0 << 4) | |
55 | #define UART_MR2_BITS_PER_CHAR_6 (0x1 << 4) | |
56 | #define UART_MR2_BITS_PER_CHAR_7 (0x2 << 4) | |
57 | #define UART_MR2_BITS_PER_CHAR_8 (0x3 << 4) | |
58 | #define UART_MR2_STOP_BIT_LEN_ONE (0x1 << 2) | |
59 | #define UART_MR2_STOP_BIT_LEN_TWO (0x3 << 2) | |
60 | #define UART_MR2_PARITY_MODE_NONE 0x0 | |
61 | #define UART_MR2_PARITY_MODE_ODD 0x1 | |
62 | #define UART_MR2_PARITY_MODE_EVEN 0x2 | |
63 | #define UART_MR2_PARITY_MODE_SPACE 0x3 | |
64 | #define UART_MR2_PARITY_MODE 0x3 | |
65 | ||
66 | #define UART_CSR 0x0008 | |
67 | ||
68 | #define UART_TF 0x000C | |
69 | #define UARTDM_TF 0x0070 | |
70 | ||
71 | #define UART_CR 0x0010 | |
72 | #define UART_CR_CMD_NULL (0 << 4) | |
73 | #define UART_CR_CMD_RESET_RX (1 << 4) | |
74 | #define UART_CR_CMD_RESET_TX (2 << 4) | |
75 | #define UART_CR_CMD_RESET_ERR (3 << 4) | |
76 | #define UART_CR_CMD_RESET_BREAK_INT (4 << 4) | |
77 | #define UART_CR_CMD_START_BREAK (5 << 4) | |
78 | #define UART_CR_CMD_STOP_BREAK (6 << 4) | |
79 | #define UART_CR_CMD_RESET_CTS (7 << 4) | |
80 | #define UART_CR_CMD_RESET_STALE_INT (8 << 4) | |
81 | #define UART_CR_CMD_PACKET_MODE (9 << 4) | |
82 | #define UART_CR_CMD_MODE_RESET (12 << 4) | |
83 | #define UART_CR_CMD_SET_RFR (13 << 4) | |
84 | #define UART_CR_CMD_RESET_RFR (14 << 4) | |
85 | #define UART_CR_CMD_PROTECTION_EN (16 << 4) | |
86 | #define UART_CR_CMD_STALE_EVENT_DISABLE (6 << 8) | |
87 | #define UART_CR_CMD_STALE_EVENT_ENABLE (80 << 4) | |
88 | #define UART_CR_CMD_FORCE_STALE (4 << 8) | |
89 | #define UART_CR_CMD_RESET_TX_READY (3 << 8) | |
90 | #define UART_CR_TX_DISABLE BIT(3) | |
91 | #define UART_CR_TX_ENABLE BIT(2) | |
92 | #define UART_CR_RX_DISABLE BIT(1) | |
93 | #define UART_CR_RX_ENABLE BIT(0) | |
94 | #define UART_CR_CMD_RESET_RXBREAK_START ((1 << 11) | (2 << 4)) | |
95 | ||
96 | #define UART_IMR 0x0014 | |
97 | #define UART_IMR_TXLEV BIT(0) | |
98 | #define UART_IMR_RXSTALE BIT(3) | |
99 | #define UART_IMR_RXLEV BIT(4) | |
100 | #define UART_IMR_DELTA_CTS BIT(5) | |
101 | #define UART_IMR_CURRENT_CTS BIT(6) | |
102 | #define UART_IMR_RXBREAK_START BIT(10) | |
103 | ||
104 | #define UART_IPR_RXSTALE_LAST 0x20 | |
105 | #define UART_IPR_STALE_LSB 0x1F | |
106 | #define UART_IPR_STALE_TIMEOUT_MSB 0x3FF80 | |
107 | #define UART_DM_IPR_STALE_TIMEOUT_MSB 0xFFFFFF80 | |
108 | ||
109 | #define UART_IPR 0x0018 | |
110 | #define UART_TFWR 0x001C | |
111 | #define UART_RFWR 0x0020 | |
112 | #define UART_HCR 0x0024 | |
113 | ||
114 | #define UART_MREG 0x0028 | |
115 | #define UART_NREG 0x002C | |
116 | #define UART_DREG 0x0030 | |
117 | #define UART_MNDREG 0x0034 | |
118 | #define UART_IRDA 0x0038 | |
119 | #define UART_MISR_MODE 0x0040 | |
120 | #define UART_MISR_RESET 0x0044 | |
121 | #define UART_MISR_EXPORT 0x0048 | |
122 | #define UART_MISR_VAL 0x004C | |
123 | #define UART_TEST_CTRL 0x0050 | |
124 | ||
125 | #define UART_SR 0x0008 | |
126 | #define UART_SR_HUNT_CHAR BIT(7) | |
127 | #define UART_SR_RX_BREAK BIT(6) | |
128 | #define UART_SR_PAR_FRAME_ERR BIT(5) | |
129 | #define UART_SR_OVERRUN BIT(4) | |
130 | #define UART_SR_TX_EMPTY BIT(3) | |
131 | #define UART_SR_TX_READY BIT(2) | |
132 | #define UART_SR_RX_FULL BIT(1) | |
133 | #define UART_SR_RX_READY BIT(0) | |
134 | ||
135 | #define UART_RF 0x000C | |
136 | #define UARTDM_RF 0x0070 | |
137 | #define UART_MISR 0x0010 | |
138 | #define UART_ISR 0x0014 | |
139 | #define UART_ISR_TX_READY BIT(7) | |
140 | ||
141 | #define UARTDM_RXFS 0x50 | |
142 | #define UARTDM_RXFS_BUF_SHIFT 0x7 | |
143 | #define UARTDM_RXFS_BUF_MASK 0x7 | |
144 | ||
145 | #define UARTDM_DMEN 0x3C | |
146 | #define UARTDM_DMEN_RX_SC_ENABLE BIT(5) | |
147 | #define UARTDM_DMEN_TX_SC_ENABLE BIT(4) | |
148 | ||
149 | #define UARTDM_DMEN_TX_BAM_ENABLE BIT(2) /* UARTDM_1P4 */ | |
150 | #define UARTDM_DMEN_TX_DM_ENABLE BIT(0) /* < UARTDM_1P4 */ | |
151 | ||
152 | #define UARTDM_DMEN_RX_BAM_ENABLE BIT(3) /* UARTDM_1P4 */ | |
153 | #define UARTDM_DMEN_RX_DM_ENABLE BIT(1) /* < UARTDM_1P4 */ | |
154 | ||
155 | #define UARTDM_DMRX 0x34 | |
156 | #define UARTDM_NCF_TX 0x40 | |
157 | #define UARTDM_RX_TOTAL_SNAP 0x38 | |
158 | ||
159 | #define UARTDM_BURST_SIZE 16 /* in bytes */ | |
160 | #define UARTDM_TX_AIGN(x) ((x) & ~0x3) /* valid for > 1p3 */ | |
161 | #define UARTDM_TX_MAX 256 /* in bytes, valid for <= 1p3 */ | |
162 | #define UARTDM_RX_SIZE (UART_XMIT_SIZE / 4) | |
3a878c43 | 163 | |
f7e54d7a SB |
164 | enum { |
165 | UARTDM_1P1 = 1, | |
166 | UARTDM_1P2, | |
167 | UARTDM_1P3, | |
168 | UARTDM_1P4, | |
169 | }; | |
170 | ||
3a878c43 II |
171 | struct msm_dma { |
172 | struct dma_chan *chan; | |
173 | enum dma_data_direction dir; | |
174 | dma_addr_t phys; | |
175 | unsigned char *virt; | |
176 | dma_cookie_t cookie; | |
177 | u32 enable_bit; | |
178 | unsigned int count; | |
179 | struct dma_async_tx_descriptor *desc; | |
180 | }; | |
181 | ||
04896a77 RL |
182 | struct msm_port { |
183 | struct uart_port uart; | |
184 | char name[16]; | |
185 | struct clk *clk; | |
ec8f29e7 | 186 | struct clk *pclk; |
04896a77 | 187 | unsigned int imr; |
ec8f29e7 SM |
188 | int is_uartdm; |
189 | unsigned int old_snap_state; | |
0896d4d4 | 190 | bool break_detected; |
3a878c43 | 191 | struct msm_dma tx_dma; |
99693945 | 192 | struct msm_dma rx_dma; |
04896a77 RL |
193 | }; |
194 | ||
32173741 SB |
195 | #define UART_TO_MSM(uart_port) container_of(uart_port, struct msm_port, uart) |
196 | ||
197 | static | |
198 | void msm_write(struct uart_port *port, unsigned int val, unsigned int off) | |
199 | { | |
200 | writel_relaxed(val, port->membase + off); | |
201 | } | |
202 | ||
203 | static | |
204 | unsigned int msm_read(struct uart_port *port, unsigned int off) | |
205 | { | |
206 | return readl_relaxed(port->membase + off); | |
207 | } | |
208 | ||
209 | /* | |
210 | * Setup the MND registers to use the TCXO clock. | |
211 | */ | |
212 | static void msm_serial_set_mnd_regs_tcxo(struct uart_port *port) | |
213 | { | |
214 | msm_write(port, 0x06, UART_MREG); | |
215 | msm_write(port, 0xF1, UART_NREG); | |
216 | msm_write(port, 0x0F, UART_DREG); | |
217 | msm_write(port, 0x1A, UART_MNDREG); | |
218 | port->uartclk = 1843200; | |
219 | } | |
220 | ||
221 | /* | |
222 | * Setup the MND registers to use the TCXO clock divided by 4. | |
223 | */ | |
224 | static void msm_serial_set_mnd_regs_tcxoby4(struct uart_port *port) | |
225 | { | |
226 | msm_write(port, 0x18, UART_MREG); | |
227 | msm_write(port, 0xF6, UART_NREG); | |
228 | msm_write(port, 0x0F, UART_DREG); | |
229 | msm_write(port, 0x0A, UART_MNDREG); | |
230 | port->uartclk = 1843200; | |
231 | } | |
232 | ||
233 | static void msm_serial_set_mnd_regs(struct uart_port *port) | |
234 | { | |
2a31f094 SB |
235 | struct msm_port *msm_port = UART_TO_MSM(port); |
236 | ||
237 | /* | |
238 | * These registers don't exist so we change the clk input rate | |
239 | * on uartdm hardware instead | |
240 | */ | |
241 | if (msm_port->is_uartdm) | |
242 | return; | |
243 | ||
32173741 SB |
244 | if (port->uartclk == 19200000) |
245 | msm_serial_set_mnd_regs_tcxo(port); | |
246 | else if (port->uartclk == 4800000) | |
247 | msm_serial_set_mnd_regs_tcxoby4(port); | |
248 | } | |
249 | ||
3a878c43 | 250 | static void msm_handle_tx(struct uart_port *port); |
99693945 | 251 | static void msm_start_rx_dma(struct msm_port *msm_port); |
3a878c43 | 252 | |
9a3f5bf2 | 253 | static void msm_stop_dma(struct uart_port *port, struct msm_dma *dma) |
3a878c43 II |
254 | { |
255 | struct device *dev = port->dev; | |
256 | unsigned int mapped; | |
257 | u32 val; | |
258 | ||
259 | mapped = dma->count; | |
260 | dma->count = 0; | |
261 | ||
262 | dmaengine_terminate_all(dma->chan); | |
263 | ||
264 | /* | |
265 | * DMA Stall happens if enqueue and flush command happens concurrently. | |
266 | * For example before changing the baud rate/protocol configuration and | |
267 | * sending flush command to ADM, disable the channel of UARTDM. | |
268 | * Note: should not reset the receiver here immediately as it is not | |
269 | * suggested to do disable/reset or reset/disable at the same time. | |
270 | */ | |
271 | val = msm_read(port, UARTDM_DMEN); | |
272 | val &= ~dma->enable_bit; | |
273 | msm_write(port, val, UARTDM_DMEN); | |
274 | ||
275 | if (mapped) | |
276 | dma_unmap_single(dev, dma->phys, mapped, dma->dir); | |
277 | } | |
278 | ||
279 | static void msm_release_dma(struct msm_port *msm_port) | |
280 | { | |
281 | struct msm_dma *dma; | |
282 | ||
283 | dma = &msm_port->tx_dma; | |
284 | if (dma->chan) { | |
285 | msm_stop_dma(&msm_port->uart, dma); | |
286 | dma_release_channel(dma->chan); | |
287 | } | |
288 | ||
289 | memset(dma, 0, sizeof(*dma)); | |
99693945 II |
290 | |
291 | dma = &msm_port->rx_dma; | |
292 | if (dma->chan) { | |
293 | msm_stop_dma(&msm_port->uart, dma); | |
294 | dma_release_channel(dma->chan); | |
295 | kfree(dma->virt); | |
296 | } | |
297 | ||
298 | memset(dma, 0, sizeof(*dma)); | |
3a878c43 II |
299 | } |
300 | ||
301 | static void msm_request_tx_dma(struct msm_port *msm_port, resource_size_t base) | |
302 | { | |
303 | struct device *dev = msm_port->uart.dev; | |
304 | struct dma_slave_config conf; | |
305 | struct msm_dma *dma; | |
306 | u32 crci = 0; | |
307 | int ret; | |
308 | ||
309 | dma = &msm_port->tx_dma; | |
310 | ||
311 | /* allocate DMA resources, if available */ | |
312 | dma->chan = dma_request_slave_channel_reason(dev, "tx"); | |
313 | if (IS_ERR(dma->chan)) | |
314 | goto no_tx; | |
315 | ||
316 | of_property_read_u32(dev->of_node, "qcom,tx-crci", &crci); | |
317 | ||
318 | memset(&conf, 0, sizeof(conf)); | |
319 | conf.direction = DMA_MEM_TO_DEV; | |
320 | conf.device_fc = true; | |
321 | conf.dst_addr = base + UARTDM_TF; | |
322 | conf.dst_maxburst = UARTDM_BURST_SIZE; | |
323 | conf.slave_id = crci; | |
324 | ||
325 | ret = dmaengine_slave_config(dma->chan, &conf); | |
326 | if (ret) | |
327 | goto rel_tx; | |
328 | ||
329 | dma->dir = DMA_TO_DEVICE; | |
330 | ||
331 | if (msm_port->is_uartdm < UARTDM_1P4) | |
332 | dma->enable_bit = UARTDM_DMEN_TX_DM_ENABLE; | |
333 | else | |
334 | dma->enable_bit = UARTDM_DMEN_TX_BAM_ENABLE; | |
335 | ||
336 | return; | |
337 | ||
338 | rel_tx: | |
339 | dma_release_channel(dma->chan); | |
340 | no_tx: | |
341 | memset(dma, 0, sizeof(*dma)); | |
342 | } | |
343 | ||
99693945 II |
344 | static void msm_request_rx_dma(struct msm_port *msm_port, resource_size_t base) |
345 | { | |
346 | struct device *dev = msm_port->uart.dev; | |
347 | struct dma_slave_config conf; | |
348 | struct msm_dma *dma; | |
349 | u32 crci = 0; | |
350 | int ret; | |
351 | ||
352 | dma = &msm_port->rx_dma; | |
353 | ||
354 | /* allocate DMA resources, if available */ | |
355 | dma->chan = dma_request_slave_channel_reason(dev, "rx"); | |
356 | if (IS_ERR(dma->chan)) | |
357 | goto no_rx; | |
358 | ||
359 | of_property_read_u32(dev->of_node, "qcom,rx-crci", &crci); | |
360 | ||
361 | dma->virt = kzalloc(UARTDM_RX_SIZE, GFP_KERNEL); | |
362 | if (!dma->virt) | |
363 | goto rel_rx; | |
364 | ||
365 | memset(&conf, 0, sizeof(conf)); | |
366 | conf.direction = DMA_DEV_TO_MEM; | |
367 | conf.device_fc = true; | |
368 | conf.src_addr = base + UARTDM_RF; | |
369 | conf.src_maxburst = UARTDM_BURST_SIZE; | |
370 | conf.slave_id = crci; | |
371 | ||
372 | ret = dmaengine_slave_config(dma->chan, &conf); | |
373 | if (ret) | |
374 | goto err; | |
375 | ||
376 | dma->dir = DMA_FROM_DEVICE; | |
377 | ||
378 | if (msm_port->is_uartdm < UARTDM_1P4) | |
379 | dma->enable_bit = UARTDM_DMEN_RX_DM_ENABLE; | |
380 | else | |
381 | dma->enable_bit = UARTDM_DMEN_RX_BAM_ENABLE; | |
382 | ||
383 | return; | |
384 | err: | |
385 | kfree(dma->virt); | |
386 | rel_rx: | |
387 | dma_release_channel(dma->chan); | |
388 | no_rx: | |
389 | memset(dma, 0, sizeof(*dma)); | |
390 | } | |
391 | ||
558abdb0 | 392 | static inline void msm_wait_for_xmitr(struct uart_port *port) |
ec8f29e7 | 393 | { |
4a5662d6 SB |
394 | while (!(msm_read(port, UART_SR) & UART_SR_TX_EMPTY)) { |
395 | if (msm_read(port, UART_ISR) & UART_ISR_TX_READY) | |
396 | break; | |
397 | udelay(1); | |
398 | } | |
399 | msm_write(port, UART_CR_CMD_RESET_TX_READY, UART_CR); | |
ec8f29e7 SM |
400 | } |
401 | ||
04896a77 RL |
402 | static void msm_stop_tx(struct uart_port *port) |
403 | { | |
404 | struct msm_port *msm_port = UART_TO_MSM(port); | |
405 | ||
406 | msm_port->imr &= ~UART_IMR_TXLEV; | |
407 | msm_write(port, msm_port->imr, UART_IMR); | |
408 | } | |
409 | ||
410 | static void msm_start_tx(struct uart_port *port) | |
411 | { | |
412 | struct msm_port *msm_port = UART_TO_MSM(port); | |
3a878c43 II |
413 | struct msm_dma *dma = &msm_port->tx_dma; |
414 | ||
415 | /* Already started in DMA mode */ | |
416 | if (dma->count) | |
417 | return; | |
04896a77 RL |
418 | |
419 | msm_port->imr |= UART_IMR_TXLEV; | |
420 | msm_write(port, msm_port->imr, UART_IMR); | |
421 | } | |
422 | ||
3a878c43 II |
423 | static void msm_reset_dm_count(struct uart_port *port, int count) |
424 | { | |
425 | msm_wait_for_xmitr(port); | |
426 | msm_write(port, count, UARTDM_NCF_TX); | |
427 | msm_read(port, UARTDM_NCF_TX); | |
428 | } | |
429 | ||
430 | static void msm_complete_tx_dma(void *args) | |
431 | { | |
432 | struct msm_port *msm_port = args; | |
433 | struct uart_port *port = &msm_port->uart; | |
434 | struct circ_buf *xmit = &port->state->xmit; | |
435 | struct msm_dma *dma = &msm_port->tx_dma; | |
436 | struct dma_tx_state state; | |
437 | enum dma_status status; | |
438 | unsigned long flags; | |
439 | unsigned int count; | |
440 | u32 val; | |
441 | ||
442 | spin_lock_irqsave(&port->lock, flags); | |
443 | ||
444 | /* Already stopped */ | |
445 | if (!dma->count) | |
446 | goto done; | |
447 | ||
448 | status = dmaengine_tx_status(dma->chan, dma->cookie, &state); | |
449 | ||
450 | dma_unmap_single(port->dev, dma->phys, dma->count, dma->dir); | |
451 | ||
452 | val = msm_read(port, UARTDM_DMEN); | |
453 | val &= ~dma->enable_bit; | |
454 | msm_write(port, val, UARTDM_DMEN); | |
455 | ||
456 | if (msm_port->is_uartdm > UARTDM_1P3) { | |
457 | msm_write(port, UART_CR_CMD_RESET_TX, UART_CR); | |
458 | msm_write(port, UART_CR_TX_ENABLE, UART_CR); | |
459 | } | |
460 | ||
461 | count = dma->count - state.residue; | |
462 | port->icount.tx += count; | |
463 | dma->count = 0; | |
464 | ||
465 | xmit->tail += count; | |
466 | xmit->tail &= UART_XMIT_SIZE - 1; | |
467 | ||
468 | /* Restore "Tx FIFO below watermark" interrupt */ | |
469 | msm_port->imr |= UART_IMR_TXLEV; | |
470 | msm_write(port, msm_port->imr, UART_IMR); | |
471 | ||
472 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
473 | uart_write_wakeup(port); | |
474 | ||
475 | msm_handle_tx(port); | |
476 | done: | |
477 | spin_unlock_irqrestore(&port->lock, flags); | |
478 | } | |
479 | ||
480 | static int msm_handle_tx_dma(struct msm_port *msm_port, unsigned int count) | |
481 | { | |
482 | struct circ_buf *xmit = &msm_port->uart.state->xmit; | |
483 | struct uart_port *port = &msm_port->uart; | |
484 | struct msm_dma *dma = &msm_port->tx_dma; | |
485 | void *cpu_addr; | |
486 | int ret; | |
487 | u32 val; | |
488 | ||
489 | cpu_addr = &xmit->buf[xmit->tail]; | |
490 | ||
491 | dma->phys = dma_map_single(port->dev, cpu_addr, count, dma->dir); | |
492 | ret = dma_mapping_error(port->dev, dma->phys); | |
493 | if (ret) | |
494 | return ret; | |
495 | ||
496 | dma->desc = dmaengine_prep_slave_single(dma->chan, dma->phys, | |
497 | count, DMA_MEM_TO_DEV, | |
498 | DMA_PREP_INTERRUPT | | |
499 | DMA_PREP_FENCE); | |
500 | if (!dma->desc) { | |
501 | ret = -EIO; | |
502 | goto unmap; | |
503 | } | |
504 | ||
505 | dma->desc->callback = msm_complete_tx_dma; | |
506 | dma->desc->callback_param = msm_port; | |
507 | ||
508 | dma->cookie = dmaengine_submit(dma->desc); | |
509 | ret = dma_submit_error(dma->cookie); | |
510 | if (ret) | |
511 | goto unmap; | |
512 | ||
513 | /* | |
514 | * Using DMA complete for Tx FIFO reload, no need for | |
515 | * "Tx FIFO below watermark" one, disable it | |
516 | */ | |
517 | msm_port->imr &= ~UART_IMR_TXLEV; | |
518 | msm_write(port, msm_port->imr, UART_IMR); | |
519 | ||
520 | dma->count = count; | |
521 | ||
522 | val = msm_read(port, UARTDM_DMEN); | |
523 | val |= dma->enable_bit; | |
524 | ||
525 | if (msm_port->is_uartdm < UARTDM_1P4) | |
526 | msm_write(port, val, UARTDM_DMEN); | |
527 | ||
528 | msm_reset_dm_count(port, count); | |
529 | ||
530 | if (msm_port->is_uartdm > UARTDM_1P3) | |
531 | msm_write(port, val, UARTDM_DMEN); | |
532 | ||
533 | dma_async_issue_pending(dma->chan); | |
534 | return 0; | |
535 | unmap: | |
536 | dma_unmap_single(port->dev, dma->phys, count, dma->dir); | |
537 | return ret; | |
538 | } | |
99693945 II |
539 | |
540 | static void msm_complete_rx_dma(void *args) | |
541 | { | |
542 | struct msm_port *msm_port = args; | |
543 | struct uart_port *port = &msm_port->uart; | |
544 | struct tty_port *tport = &port->state->port; | |
545 | struct msm_dma *dma = &msm_port->rx_dma; | |
546 | int count = 0, i, sysrq; | |
547 | unsigned long flags; | |
548 | u32 val; | |
549 | ||
550 | spin_lock_irqsave(&port->lock, flags); | |
551 | ||
552 | /* Already stopped */ | |
553 | if (!dma->count) | |
554 | goto done; | |
555 | ||
556 | val = msm_read(port, UARTDM_DMEN); | |
557 | val &= ~dma->enable_bit; | |
558 | msm_write(port, val, UARTDM_DMEN); | |
559 | ||
99693945 II |
560 | if (msm_read(port, UART_SR) & UART_SR_OVERRUN) { |
561 | port->icount.overrun++; | |
562 | tty_insert_flip_char(tport, 0, TTY_OVERRUN); | |
563 | msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR); | |
564 | } | |
565 | ||
566 | count = msm_read(port, UARTDM_RX_TOTAL_SNAP); | |
567 | ||
568 | port->icount.rx += count; | |
569 | ||
570 | dma->count = 0; | |
571 | ||
572 | dma_unmap_single(port->dev, dma->phys, UARTDM_RX_SIZE, dma->dir); | |
573 | ||
574 | for (i = 0; i < count; i++) { | |
575 | char flag = TTY_NORMAL; | |
576 | ||
577 | if (msm_port->break_detected && dma->virt[i] == 0) { | |
578 | port->icount.brk++; | |
579 | flag = TTY_BREAK; | |
580 | msm_port->break_detected = false; | |
581 | if (uart_handle_break(port)) | |
582 | continue; | |
583 | } | |
584 | ||
585 | if (!(port->read_status_mask & UART_SR_RX_BREAK)) | |
586 | flag = TTY_NORMAL; | |
587 | ||
588 | spin_unlock_irqrestore(&port->lock, flags); | |
589 | sysrq = uart_handle_sysrq_char(port, dma->virt[i]); | |
590 | spin_lock_irqsave(&port->lock, flags); | |
591 | if (!sysrq) | |
592 | tty_insert_flip_char(tport, dma->virt[i], flag); | |
593 | } | |
594 | ||
595 | msm_start_rx_dma(msm_port); | |
596 | done: | |
597 | spin_unlock_irqrestore(&port->lock, flags); | |
598 | ||
599 | if (count) | |
600 | tty_flip_buffer_push(tport); | |
601 | } | |
602 | ||
603 | static void msm_start_rx_dma(struct msm_port *msm_port) | |
604 | { | |
605 | struct msm_dma *dma = &msm_port->rx_dma; | |
606 | struct uart_port *uart = &msm_port->uart; | |
607 | u32 val; | |
608 | int ret; | |
609 | ||
610 | if (!dma->chan) | |
611 | return; | |
612 | ||
613 | dma->phys = dma_map_single(uart->dev, dma->virt, | |
614 | UARTDM_RX_SIZE, dma->dir); | |
615 | ret = dma_mapping_error(uart->dev, dma->phys); | |
616 | if (ret) | |
617 | return; | |
618 | ||
619 | dma->desc = dmaengine_prep_slave_single(dma->chan, dma->phys, | |
620 | UARTDM_RX_SIZE, DMA_DEV_TO_MEM, | |
621 | DMA_PREP_INTERRUPT); | |
622 | if (!dma->desc) | |
623 | goto unmap; | |
624 | ||
625 | dma->desc->callback = msm_complete_rx_dma; | |
626 | dma->desc->callback_param = msm_port; | |
627 | ||
628 | dma->cookie = dmaengine_submit(dma->desc); | |
629 | ret = dma_submit_error(dma->cookie); | |
630 | if (ret) | |
631 | goto unmap; | |
632 | /* | |
633 | * Using DMA for FIFO off-load, no need for "Rx FIFO over | |
634 | * watermark" or "stale" interrupts, disable them | |
635 | */ | |
636 | msm_port->imr &= ~(UART_IMR_RXLEV | UART_IMR_RXSTALE); | |
637 | ||
638 | /* | |
639 | * Well, when DMA is ADM3 engine(implied by <= UARTDM v1.3), | |
640 | * we need RXSTALE to flush input DMA fifo to memory | |
641 | */ | |
642 | if (msm_port->is_uartdm < UARTDM_1P4) | |
643 | msm_port->imr |= UART_IMR_RXSTALE; | |
644 | ||
645 | msm_write(uart, msm_port->imr, UART_IMR); | |
646 | ||
647 | dma->count = UARTDM_RX_SIZE; | |
648 | ||
649 | dma_async_issue_pending(dma->chan); | |
650 | ||
651 | msm_write(uart, UART_CR_CMD_RESET_STALE_INT, UART_CR); | |
652 | msm_write(uart, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR); | |
653 | ||
654 | val = msm_read(uart, UARTDM_DMEN); | |
655 | val |= dma->enable_bit; | |
656 | ||
657 | if (msm_port->is_uartdm < UARTDM_1P4) | |
658 | msm_write(uart, val, UARTDM_DMEN); | |
659 | ||
660 | msm_write(uart, UARTDM_RX_SIZE, UARTDM_DMRX); | |
661 | ||
662 | if (msm_port->is_uartdm > UARTDM_1P3) | |
663 | msm_write(uart, val, UARTDM_DMEN); | |
664 | ||
665 | return; | |
666 | unmap: | |
667 | dma_unmap_single(uart->dev, dma->phys, UARTDM_RX_SIZE, dma->dir); | |
668 | } | |
669 | ||
04896a77 RL |
670 | static void msm_stop_rx(struct uart_port *port) |
671 | { | |
672 | struct msm_port *msm_port = UART_TO_MSM(port); | |
99693945 | 673 | struct msm_dma *dma = &msm_port->rx_dma; |
04896a77 RL |
674 | |
675 | msm_port->imr &= ~(UART_IMR_RXLEV | UART_IMR_RXSTALE); | |
676 | msm_write(port, msm_port->imr, UART_IMR); | |
99693945 II |
677 | |
678 | if (dma->chan) | |
679 | msm_stop_dma(port, dma); | |
04896a77 RL |
680 | } |
681 | ||
682 | static void msm_enable_ms(struct uart_port *port) | |
683 | { | |
684 | struct msm_port *msm_port = UART_TO_MSM(port); | |
685 | ||
686 | msm_port->imr |= UART_IMR_DELTA_CTS; | |
687 | msm_write(port, msm_port->imr, UART_IMR); | |
688 | } | |
689 | ||
558abdb0 | 690 | static void msm_handle_rx_dm(struct uart_port *port, unsigned int misr) |
ec8f29e7 | 691 | { |
92a19f9c | 692 | struct tty_port *tport = &port->state->port; |
ec8f29e7 SM |
693 | unsigned int sr; |
694 | int count = 0; | |
695 | struct msm_port *msm_port = UART_TO_MSM(port); | |
696 | ||
697 | if ((msm_read(port, UART_SR) & UART_SR_OVERRUN)) { | |
698 | port->icount.overrun++; | |
92a19f9c | 699 | tty_insert_flip_char(tport, 0, TTY_OVERRUN); |
ec8f29e7 SM |
700 | msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR); |
701 | } | |
702 | ||
703 | if (misr & UART_IMR_RXSTALE) { | |
704 | count = msm_read(port, UARTDM_RX_TOTAL_SNAP) - | |
705 | msm_port->old_snap_state; | |
706 | msm_port->old_snap_state = 0; | |
707 | } else { | |
708 | count = 4 * (msm_read(port, UART_RFWR)); | |
709 | msm_port->old_snap_state += count; | |
710 | } | |
711 | ||
712 | /* TODO: Precise error reporting */ | |
713 | ||
714 | port->icount.rx += count; | |
715 | ||
716 | while (count > 0) { | |
68252424 | 717 | unsigned char buf[4]; |
0896d4d4 | 718 | int sysrq, r_count, i; |
ec8f29e7 SM |
719 | |
720 | sr = msm_read(port, UART_SR); | |
721 | if ((sr & UART_SR_RX_READY) == 0) { | |
722 | msm_port->old_snap_state -= count; | |
723 | break; | |
724 | } | |
ec8f29e7 | 725 | |
0896d4d4 SB |
726 | ioread32_rep(port->membase + UARTDM_RF, buf, 1); |
727 | r_count = min_t(int, count, sizeof(buf)); | |
728 | ||
729 | for (i = 0; i < r_count; i++) { | |
730 | char flag = TTY_NORMAL; | |
731 | ||
732 | if (msm_port->break_detected && buf[i] == 0) { | |
733 | port->icount.brk++; | |
734 | flag = TTY_BREAK; | |
735 | msm_port->break_detected = false; | |
736 | if (uart_handle_break(port)) | |
737 | continue; | |
738 | } | |
739 | ||
740 | if (!(port->read_status_mask & UART_SR_RX_BREAK)) | |
741 | flag = TTY_NORMAL; | |
742 | ||
743 | spin_unlock(&port->lock); | |
744 | sysrq = uart_handle_sysrq_char(port, buf[i]); | |
745 | spin_lock(&port->lock); | |
746 | if (!sysrq) | |
747 | tty_insert_flip_char(tport, buf[i], flag); | |
748 | } | |
749 | count -= r_count; | |
ec8f29e7 SM |
750 | } |
751 | ||
f77232da | 752 | spin_unlock(&port->lock); |
2e124b4a | 753 | tty_flip_buffer_push(tport); |
f77232da VK |
754 | spin_lock(&port->lock); |
755 | ||
ec8f29e7 SM |
756 | if (misr & (UART_IMR_RXSTALE)) |
757 | msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR); | |
758 | msm_write(port, 0xFFFFFF, UARTDM_DMRX); | |
759 | msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR); | |
99693945 II |
760 | |
761 | /* Try to use DMA */ | |
762 | msm_start_rx_dma(msm_port); | |
ec8f29e7 SM |
763 | } |
764 | ||
558abdb0 | 765 | static void msm_handle_rx(struct uart_port *port) |
04896a77 | 766 | { |
92a19f9c | 767 | struct tty_port *tport = &port->state->port; |
04896a77 RL |
768 | unsigned int sr; |
769 | ||
770 | /* | |
771 | * Handle overrun. My understanding of the hardware is that overrun | |
772 | * is not tied to the RX buffer, so we handle the case out of band. | |
773 | */ | |
774 | if ((msm_read(port, UART_SR) & UART_SR_OVERRUN)) { | |
775 | port->icount.overrun++; | |
92a19f9c | 776 | tty_insert_flip_char(tport, 0, TTY_OVERRUN); |
04896a77 RL |
777 | msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR); |
778 | } | |
779 | ||
780 | /* and now the main RX loop */ | |
781 | while ((sr = msm_read(port, UART_SR)) & UART_SR_RX_READY) { | |
782 | unsigned int c; | |
783 | char flag = TTY_NORMAL; | |
660beb0e | 784 | int sysrq; |
04896a77 RL |
785 | |
786 | c = msm_read(port, UART_RF); | |
787 | ||
788 | if (sr & UART_SR_RX_BREAK) { | |
789 | port->icount.brk++; | |
790 | if (uart_handle_break(port)) | |
791 | continue; | |
792 | } else if (sr & UART_SR_PAR_FRAME_ERR) { | |
793 | port->icount.frame++; | |
794 | } else { | |
795 | port->icount.rx++; | |
796 | } | |
797 | ||
798 | /* Mask conditions we're ignorning. */ | |
799 | sr &= port->read_status_mask; | |
800 | ||
ddea392e | 801 | if (sr & UART_SR_RX_BREAK) |
04896a77 | 802 | flag = TTY_BREAK; |
ddea392e | 803 | else if (sr & UART_SR_PAR_FRAME_ERR) |
04896a77 | 804 | flag = TTY_FRAME; |
04896a77 | 805 | |
660beb0e SB |
806 | spin_unlock(&port->lock); |
807 | sysrq = uart_handle_sysrq_char(port, c); | |
808 | spin_lock(&port->lock); | |
809 | if (!sysrq) | |
92a19f9c | 810 | tty_insert_flip_char(tport, c, flag); |
04896a77 RL |
811 | } |
812 | ||
f77232da | 813 | spin_unlock(&port->lock); |
2e124b4a | 814 | tty_flip_buffer_push(tport); |
f77232da | 815 | spin_lock(&port->lock); |
04896a77 RL |
816 | } |
817 | ||
3a878c43 | 818 | static void msm_handle_tx_pio(struct uart_port *port, unsigned int tx_count) |
04896a77 | 819 | { |
ebd2c8f6 | 820 | struct circ_buf *xmit = &port->state->xmit; |
04896a77 | 821 | struct msm_port *msm_port = UART_TO_MSM(port); |
3a878c43 | 822 | unsigned int num_chars; |
17fae28e | 823 | unsigned int tf_pointer = 0; |
68252424 SB |
824 | void __iomem *tf; |
825 | ||
826 | if (msm_port->is_uartdm) | |
827 | tf = port->membase + UARTDM_TF; | |
828 | else | |
829 | tf = port->membase + UART_TF; | |
17fae28e | 830 | |
3a878c43 | 831 | if (tx_count && msm_port->is_uartdm) |
558abdb0 | 832 | msm_reset_dm_count(port, tx_count); |
04896a77 | 833 | |
17fae28e SB |
834 | while (tf_pointer < tx_count) { |
835 | int i; | |
836 | char buf[4] = { 0 }; | |
ec8f29e7 | 837 | |
17fae28e | 838 | if (!(msm_read(port, UART_SR) & UART_SR_TX_READY)) |
04896a77 | 839 | break; |
04896a77 | 840 | |
ec8f29e7 | 841 | if (msm_port->is_uartdm) |
4f749f24 JH |
842 | num_chars = min(tx_count - tf_pointer, |
843 | (unsigned int)sizeof(buf)); | |
17fae28e SB |
844 | else |
845 | num_chars = 1; | |
04896a77 | 846 | |
17fae28e SB |
847 | for (i = 0; i < num_chars; i++) { |
848 | buf[i] = xmit->buf[xmit->tail + i]; | |
849 | port->icount.tx++; | |
850 | } | |
851 | ||
68252424 | 852 | iowrite32_rep(tf, buf, 1); |
17fae28e SB |
853 | xmit->tail = (xmit->tail + num_chars) & (UART_XMIT_SIZE - 1); |
854 | tf_pointer += num_chars; | |
04896a77 RL |
855 | } |
856 | ||
17fae28e SB |
857 | /* disable tx interrupts if nothing more to send */ |
858 | if (uart_circ_empty(xmit)) | |
859 | msm_stop_tx(port); | |
860 | ||
04896a77 RL |
861 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) |
862 | uart_write_wakeup(port); | |
863 | } | |
864 | ||
3a878c43 II |
865 | static void msm_handle_tx(struct uart_port *port) |
866 | { | |
867 | struct msm_port *msm_port = UART_TO_MSM(port); | |
868 | struct circ_buf *xmit = &msm_port->uart.state->xmit; | |
869 | struct msm_dma *dma = &msm_port->tx_dma; | |
870 | unsigned int pio_count, dma_count, dma_min; | |
871 | void __iomem *tf; | |
872 | int err = 0; | |
873 | ||
874 | if (port->x_char) { | |
875 | if (msm_port->is_uartdm) | |
876 | tf = port->membase + UARTDM_TF; | |
877 | else | |
878 | tf = port->membase + UART_TF; | |
879 | ||
880 | if (msm_port->is_uartdm) | |
881 | msm_reset_dm_count(port, 1); | |
882 | ||
883 | iowrite8_rep(tf, &port->x_char, 1); | |
884 | port->icount.tx++; | |
885 | port->x_char = 0; | |
886 | return; | |
887 | } | |
888 | ||
889 | if (uart_circ_empty(xmit) || uart_tx_stopped(port)) { | |
890 | msm_stop_tx(port); | |
891 | return; | |
892 | } | |
893 | ||
30acf549 | 894 | pio_count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE); |
3a878c43 II |
895 | dma_count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE); |
896 | ||
897 | dma_min = 1; /* Always DMA */ | |
898 | if (msm_port->is_uartdm > UARTDM_1P3) { | |
899 | dma_count = UARTDM_TX_AIGN(dma_count); | |
900 | dma_min = UARTDM_BURST_SIZE; | |
901 | } else { | |
902 | if (dma_count > UARTDM_TX_MAX) | |
903 | dma_count = UARTDM_TX_MAX; | |
904 | } | |
905 | ||
906 | if (pio_count > port->fifosize) | |
907 | pio_count = port->fifosize; | |
908 | ||
909 | if (!dma->chan || dma_count < dma_min) | |
910 | msm_handle_tx_pio(port, pio_count); | |
911 | else | |
912 | err = msm_handle_tx_dma(msm_port, dma_count); | |
913 | ||
914 | if (err) /* fall back to PIO mode */ | |
915 | msm_handle_tx_pio(port, pio_count); | |
916 | } | |
917 | ||
558abdb0 | 918 | static void msm_handle_delta_cts(struct uart_port *port) |
04896a77 RL |
919 | { |
920 | msm_write(port, UART_CR_CMD_RESET_CTS, UART_CR); | |
921 | port->icount.cts++; | |
bdc04e31 | 922 | wake_up_interruptible(&port->state->port.delta_msr_wait); |
04896a77 RL |
923 | } |
924 | ||
558abdb0 | 925 | static irqreturn_t msm_uart_irq(int irq, void *dev_id) |
04896a77 RL |
926 | { |
927 | struct uart_port *port = dev_id; | |
928 | struct msm_port *msm_port = UART_TO_MSM(port); | |
99693945 | 929 | struct msm_dma *dma = &msm_port->rx_dma; |
3a878c43 | 930 | unsigned long flags; |
04896a77 | 931 | unsigned int misr; |
99693945 | 932 | u32 val; |
04896a77 | 933 | |
3a878c43 | 934 | spin_lock_irqsave(&port->lock, flags); |
04896a77 RL |
935 | misr = msm_read(port, UART_MISR); |
936 | msm_write(port, 0, UART_IMR); /* disable interrupt */ | |
937 | ||
0896d4d4 SB |
938 | if (misr & UART_IMR_RXBREAK_START) { |
939 | msm_port->break_detected = true; | |
940 | msm_write(port, UART_CR_CMD_RESET_RXBREAK_START, UART_CR); | |
941 | } | |
942 | ||
ec8f29e7 | 943 | if (misr & (UART_IMR_RXLEV | UART_IMR_RXSTALE)) { |
99693945 II |
944 | if (dma->count) { |
945 | val = UART_CR_CMD_STALE_EVENT_DISABLE; | |
946 | msm_write(port, val, UART_CR); | |
947 | val = UART_CR_CMD_RESET_STALE_INT; | |
948 | msm_write(port, val, UART_CR); | |
949 | /* | |
950 | * Flush DMA input fifo to memory, this will also | |
951 | * trigger DMA RX completion | |
952 | */ | |
953 | dmaengine_terminate_all(dma->chan); | |
954 | } else if (msm_port->is_uartdm) { | |
558abdb0 | 955 | msm_handle_rx_dm(port, misr); |
99693945 | 956 | } else { |
558abdb0 | 957 | msm_handle_rx(port); |
99693945 | 958 | } |
ec8f29e7 | 959 | } |
04896a77 | 960 | if (misr & UART_IMR_TXLEV) |
558abdb0 | 961 | msm_handle_tx(port); |
04896a77 | 962 | if (misr & UART_IMR_DELTA_CTS) |
558abdb0 | 963 | msm_handle_delta_cts(port); |
04896a77 RL |
964 | |
965 | msm_write(port, msm_port->imr, UART_IMR); /* restore interrupt */ | |
3a878c43 | 966 | spin_unlock_irqrestore(&port->lock, flags); |
04896a77 RL |
967 | |
968 | return IRQ_HANDLED; | |
969 | } | |
970 | ||
971 | static unsigned int msm_tx_empty(struct uart_port *port) | |
972 | { | |
973 | return (msm_read(port, UART_SR) & UART_SR_TX_EMPTY) ? TIOCSER_TEMT : 0; | |
974 | } | |
975 | ||
976 | static unsigned int msm_get_mctrl(struct uart_port *port) | |
977 | { | |
978 | return TIOCM_CAR | TIOCM_CTS | TIOCM_DSR | TIOCM_RTS; | |
979 | } | |
980 | ||
ec8f29e7 | 981 | static void msm_reset(struct uart_port *port) |
04896a77 | 982 | { |
f7e54d7a SB |
983 | struct msm_port *msm_port = UART_TO_MSM(port); |
984 | ||
ec8f29e7 SM |
985 | /* reset everything */ |
986 | msm_write(port, UART_CR_CMD_RESET_RX, UART_CR); | |
987 | msm_write(port, UART_CR_CMD_RESET_TX, UART_CR); | |
988 | msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR); | |
989 | msm_write(port, UART_CR_CMD_RESET_BREAK_INT, UART_CR); | |
990 | msm_write(port, UART_CR_CMD_RESET_CTS, UART_CR); | |
991 | msm_write(port, UART_CR_CMD_SET_RFR, UART_CR); | |
f7e54d7a SB |
992 | |
993 | /* Disable DM modes */ | |
994 | if (msm_port->is_uartdm) | |
995 | msm_write(port, 0, UARTDM_DMEN); | |
ec8f29e7 | 996 | } |
04896a77 | 997 | |
f8fb952f | 998 | static void msm_set_mctrl(struct uart_port *port, unsigned int mctrl) |
ec8f29e7 SM |
999 | { |
1000 | unsigned int mr; | |
e919cefb | 1001 | |
04896a77 RL |
1002 | mr = msm_read(port, UART_MR1); |
1003 | ||
1004 | if (!(mctrl & TIOCM_RTS)) { | |
1005 | mr &= ~UART_MR1_RX_RDY_CTL; | |
1006 | msm_write(port, mr, UART_MR1); | |
1007 | msm_write(port, UART_CR_CMD_RESET_RFR, UART_CR); | |
1008 | } else { | |
1009 | mr |= UART_MR1_RX_RDY_CTL; | |
1010 | msm_write(port, mr, UART_MR1); | |
1011 | } | |
1012 | } | |
1013 | ||
1014 | static void msm_break_ctl(struct uart_port *port, int break_ctl) | |
1015 | { | |
1016 | if (break_ctl) | |
1017 | msm_write(port, UART_CR_CMD_START_BREAK, UART_CR); | |
1018 | else | |
1019 | msm_write(port, UART_CR_CMD_STOP_BREAK, UART_CR); | |
1020 | } | |
1021 | ||
6909dadd SB |
1022 | struct msm_baud_map { |
1023 | u16 divisor; | |
1024 | u8 code; | |
1025 | u8 rxstale; | |
1026 | }; | |
1027 | ||
1028 | static const struct msm_baud_map * | |
98952bf5 SB |
1029 | msm_find_best_baud(struct uart_port *port, unsigned int baud, |
1030 | unsigned long *rate) | |
6909dadd | 1031 | { |
98952bf5 SB |
1032 | struct msm_port *msm_port = UART_TO_MSM(port); |
1033 | unsigned int divisor, result; | |
1034 | unsigned long target, old, best_rate = 0, diff, best_diff = ULONG_MAX; | |
1035 | const struct msm_baud_map *entry, *end, *best; | |
6909dadd | 1036 | static const struct msm_baud_map table[] = { |
6909dadd | 1037 | { 1, 0xff, 31 }, |
98952bf5 SB |
1038 | { 2, 0xee, 16 }, |
1039 | { 3, 0xdd, 8 }, | |
1040 | { 4, 0xcc, 6 }, | |
1041 | { 6, 0xbb, 6 }, | |
1042 | { 8, 0xaa, 6 }, | |
1043 | { 12, 0x99, 6 }, | |
1044 | { 16, 0x88, 1 }, | |
1045 | { 24, 0x77, 1 }, | |
1046 | { 32, 0x66, 1 }, | |
1047 | { 48, 0x55, 1 }, | |
1048 | { 96, 0x44, 1 }, | |
1049 | { 192, 0x33, 1 }, | |
1050 | { 384, 0x22, 1 }, | |
1051 | { 768, 0x11, 1 }, | |
1052 | { 1536, 0x00, 1 }, | |
6909dadd SB |
1053 | }; |
1054 | ||
98952bf5 SB |
1055 | best = table; /* Default to smallest divider */ |
1056 | target = clk_round_rate(msm_port->clk, 16 * baud); | |
1057 | divisor = DIV_ROUND_CLOSEST(target, 16 * baud); | |
1058 | ||
1059 | end = table + ARRAY_SIZE(table); | |
1060 | entry = table; | |
1061 | while (entry < end) { | |
1062 | if (entry->divisor <= divisor) { | |
1063 | result = target / entry->divisor / 16; | |
1064 | diff = abs(result - baud); | |
1065 | ||
1066 | /* Keep track of best entry */ | |
1067 | if (diff < best_diff) { | |
1068 | best_diff = diff; | |
1069 | best = entry; | |
1070 | best_rate = target; | |
1071 | } | |
6909dadd | 1072 | |
98952bf5 SB |
1073 | if (result == baud) |
1074 | break; | |
1075 | } else if (entry->divisor > divisor) { | |
1076 | old = target; | |
1077 | target = clk_round_rate(msm_port->clk, old + 1); | |
1078 | /* | |
1079 | * The rate didn't get any faster so we can't do | |
1080 | * better at dividing it down | |
1081 | */ | |
1082 | if (target == old) | |
1083 | break; | |
1084 | ||
1085 | /* Start the divisor search over at this new rate */ | |
1086 | entry = table; | |
1087 | divisor = DIV_ROUND_CLOSEST(target, 16 * baud); | |
1088 | continue; | |
1089 | } | |
1090 | entry++; | |
1091 | } | |
6909dadd | 1092 | |
98952bf5 SB |
1093 | *rate = best_rate; |
1094 | return best; | |
6909dadd SB |
1095 | } |
1096 | ||
850b37a7 II |
1097 | static int msm_set_baud_rate(struct uart_port *port, unsigned int baud, |
1098 | unsigned long *saved_flags) | |
04896a77 | 1099 | { |
12b9b9f1 | 1100 | unsigned int rxstale, watermark, mask; |
ec8f29e7 | 1101 | struct msm_port *msm_port = UART_TO_MSM(port); |
6909dadd | 1102 | const struct msm_baud_map *entry; |
98952bf5 | 1103 | unsigned long flags, rate; |
850b37a7 II |
1104 | |
1105 | flags = *saved_flags; | |
1106 | spin_unlock_irqrestore(&port->lock, flags); | |
1107 | ||
98952bf5 SB |
1108 | entry = msm_find_best_baud(port, baud, &rate); |
1109 | clk_set_rate(msm_port->clk, rate); | |
1110 | baud = rate / 16 / entry->divisor; | |
850b37a7 II |
1111 | |
1112 | spin_lock_irqsave(&port->lock, flags); | |
1113 | *saved_flags = flags; | |
98952bf5 SB |
1114 | port->uartclk = rate; |
1115 | ||
1116 | msm_write(port, entry->code, UART_CSR); | |
850b37a7 | 1117 | |
04896a77 | 1118 | /* RX stale watermark */ |
6909dadd | 1119 | rxstale = entry->rxstale; |
04896a77 | 1120 | watermark = UART_IPR_STALE_LSB & rxstale; |
12b9b9f1 PG |
1121 | if (msm_port->is_uartdm) { |
1122 | mask = UART_DM_IPR_STALE_TIMEOUT_MSB; | |
1123 | } else { | |
1124 | watermark |= UART_IPR_RXSTALE_LAST; | |
1125 | mask = UART_IPR_STALE_TIMEOUT_MSB; | |
1126 | } | |
1127 | ||
1128 | watermark |= mask & (rxstale << 2); | |
1129 | ||
04896a77 RL |
1130 | msm_write(port, watermark, UART_IPR); |
1131 | ||
1132 | /* set RX watermark */ | |
1133 | watermark = (port->fifosize * 3) / 4; | |
1134 | msm_write(port, watermark, UART_RFWR); | |
1135 | ||
1136 | /* set TX watermark */ | |
1137 | msm_write(port, 10, UART_TFWR); | |
44da59e4 | 1138 | |
a12f1b40 SB |
1139 | msm_write(port, UART_CR_CMD_PROTECTION_EN, UART_CR); |
1140 | msm_reset(port); | |
1141 | ||
1142 | /* Enable RX and TX */ | |
1143 | msm_write(port, UART_CR_TX_ENABLE | UART_CR_RX_ENABLE, UART_CR); | |
1144 | ||
1145 | /* turn on RX and CTS interrupts */ | |
1146 | msm_port->imr = UART_IMR_RXLEV | UART_IMR_RXSTALE | | |
1147 | UART_IMR_CURRENT_CTS | UART_IMR_RXBREAK_START; | |
1148 | ||
1149 | msm_write(port, msm_port->imr, UART_IMR); | |
1150 | ||
ec8f29e7 SM |
1151 | if (msm_port->is_uartdm) { |
1152 | msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR); | |
1153 | msm_write(port, 0xFFFFFF, UARTDM_DMRX); | |
1154 | msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR); | |
1155 | } | |
1156 | ||
44da59e4 | 1157 | return baud; |
04896a77 RL |
1158 | } |
1159 | ||
04896a77 RL |
1160 | static void msm_init_clock(struct uart_port *port) |
1161 | { | |
1162 | struct msm_port *msm_port = UART_TO_MSM(port); | |
1163 | ||
f98cf83d | 1164 | clk_prepare_enable(msm_port->clk); |
bfaddb7d | 1165 | clk_prepare_enable(msm_port->pclk); |
18c79d76 | 1166 | msm_serial_set_mnd_regs(port); |
04896a77 RL |
1167 | } |
1168 | ||
1169 | static int msm_startup(struct uart_port *port) | |
1170 | { | |
1171 | struct msm_port *msm_port = UART_TO_MSM(port); | |
12b9b9f1 | 1172 | unsigned int data, rfr_level, mask; |
04896a77 RL |
1173 | int ret; |
1174 | ||
1175 | snprintf(msm_port->name, sizeof(msm_port->name), | |
1176 | "msm_serial%d", port->line); | |
1177 | ||
558abdb0 | 1178 | ret = request_irq(port->irq, msm_uart_irq, IRQF_TRIGGER_HIGH, |
04896a77 RL |
1179 | msm_port->name, port); |
1180 | if (unlikely(ret)) | |
1181 | return ret; | |
1182 | ||
1183 | msm_init_clock(port); | |
1184 | ||
1185 | if (likely(port->fifosize > 12)) | |
1186 | rfr_level = port->fifosize - 12; | |
1187 | else | |
1188 | rfr_level = port->fifosize; | |
1189 | ||
1190 | /* set automatic RFR level */ | |
1191 | data = msm_read(port, UART_MR1); | |
12b9b9f1 PG |
1192 | |
1193 | if (msm_port->is_uartdm) | |
1194 | mask = UART_DM_MR1_AUTO_RFR_LEVEL1; | |
1195 | else | |
1196 | mask = UART_MR1_AUTO_RFR_LEVEL1; | |
1197 | ||
1198 | data &= ~mask; | |
04896a77 | 1199 | data &= ~UART_MR1_AUTO_RFR_LEVEL0; |
12b9b9f1 | 1200 | data |= mask & (rfr_level << 2); |
04896a77 RL |
1201 | data |= UART_MR1_AUTO_RFR_LEVEL0 & rfr_level; |
1202 | msm_write(port, data, UART_MR1); | |
12b9b9f1 | 1203 | |
99693945 | 1204 | if (msm_port->is_uartdm) { |
3a878c43 | 1205 | msm_request_tx_dma(msm_port, msm_port->uart.mapbase); |
99693945 II |
1206 | msm_request_rx_dma(msm_port, msm_port->uart.mapbase); |
1207 | } | |
3a878c43 | 1208 | |
04896a77 RL |
1209 | return 0; |
1210 | } | |
1211 | ||
1212 | static void msm_shutdown(struct uart_port *port) | |
1213 | { | |
1214 | struct msm_port *msm_port = UART_TO_MSM(port); | |
1215 | ||
1216 | msm_port->imr = 0; | |
1217 | msm_write(port, 0, UART_IMR); /* disable interrupts */ | |
1218 | ||
3a878c43 II |
1219 | if (msm_port->is_uartdm) |
1220 | msm_release_dma(msm_port); | |
1221 | ||
f98cf83d | 1222 | clk_disable_unprepare(msm_port->clk); |
04896a77 RL |
1223 | |
1224 | free_irq(port->irq, port); | |
1225 | } | |
1226 | ||
1227 | static void msm_set_termios(struct uart_port *port, struct ktermios *termios, | |
1228 | struct ktermios *old) | |
1229 | { | |
99693945 II |
1230 | struct msm_port *msm_port = UART_TO_MSM(port); |
1231 | struct msm_dma *dma = &msm_port->rx_dma; | |
04896a77 RL |
1232 | unsigned long flags; |
1233 | unsigned int baud, mr; | |
1234 | ||
1235 | spin_lock_irqsave(&port->lock, flags); | |
1236 | ||
99693945 II |
1237 | if (dma->chan) /* Terminate if any */ |
1238 | msm_stop_dma(port, dma); | |
1239 | ||
04896a77 | 1240 | /* calculate and set baud rate */ |
850b37a7 II |
1241 | baud = uart_get_baud_rate(port, termios, old, 300, 4000000); |
1242 | baud = msm_set_baud_rate(port, baud, &flags); | |
44da59e4 AC |
1243 | if (tty_termios_baud_rate(termios)) |
1244 | tty_termios_encode_baud_rate(termios, baud, baud); | |
ec8f29e7 | 1245 | |
04896a77 RL |
1246 | /* calculate parity */ |
1247 | mr = msm_read(port, UART_MR2); | |
1248 | mr &= ~UART_MR2_PARITY_MODE; | |
1249 | if (termios->c_cflag & PARENB) { | |
1250 | if (termios->c_cflag & PARODD) | |
1251 | mr |= UART_MR2_PARITY_MODE_ODD; | |
1252 | else if (termios->c_cflag & CMSPAR) | |
1253 | mr |= UART_MR2_PARITY_MODE_SPACE; | |
1254 | else | |
1255 | mr |= UART_MR2_PARITY_MODE_EVEN; | |
1256 | } | |
1257 | ||
1258 | /* calculate bits per char */ | |
1259 | mr &= ~UART_MR2_BITS_PER_CHAR; | |
1260 | switch (termios->c_cflag & CSIZE) { | |
1261 | case CS5: | |
1262 | mr |= UART_MR2_BITS_PER_CHAR_5; | |
1263 | break; | |
1264 | case CS6: | |
1265 | mr |= UART_MR2_BITS_PER_CHAR_6; | |
1266 | break; | |
1267 | case CS7: | |
1268 | mr |= UART_MR2_BITS_PER_CHAR_7; | |
1269 | break; | |
1270 | case CS8: | |
1271 | default: | |
1272 | mr |= UART_MR2_BITS_PER_CHAR_8; | |
1273 | break; | |
1274 | } | |
1275 | ||
1276 | /* calculate stop bits */ | |
1277 | mr &= ~(UART_MR2_STOP_BIT_LEN_ONE | UART_MR2_STOP_BIT_LEN_TWO); | |
1278 | if (termios->c_cflag & CSTOPB) | |
1279 | mr |= UART_MR2_STOP_BIT_LEN_TWO; | |
1280 | else | |
1281 | mr |= UART_MR2_STOP_BIT_LEN_ONE; | |
1282 | ||
1283 | /* set parity, bits per char, and stop bit */ | |
1284 | msm_write(port, mr, UART_MR2); | |
1285 | ||
1286 | /* calculate and set hardware flow control */ | |
1287 | mr = msm_read(port, UART_MR1); | |
1288 | mr &= ~(UART_MR1_CTS_CTL | UART_MR1_RX_RDY_CTL); | |
1289 | if (termios->c_cflag & CRTSCTS) { | |
1290 | mr |= UART_MR1_CTS_CTL; | |
1291 | mr |= UART_MR1_RX_RDY_CTL; | |
1292 | } | |
1293 | msm_write(port, mr, UART_MR1); | |
1294 | ||
1295 | /* Configure status bits to ignore based on termio flags. */ | |
1296 | port->read_status_mask = 0; | |
1297 | if (termios->c_iflag & INPCK) | |
1298 | port->read_status_mask |= UART_SR_PAR_FRAME_ERR; | |
ef8b9ddc | 1299 | if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) |
04896a77 RL |
1300 | port->read_status_mask |= UART_SR_RX_BREAK; |
1301 | ||
1302 | uart_update_timeout(port, termios->c_cflag, baud); | |
1303 | ||
99693945 II |
1304 | /* Try to use DMA */ |
1305 | msm_start_rx_dma(msm_port); | |
1306 | ||
04896a77 RL |
1307 | spin_unlock_irqrestore(&port->lock, flags); |
1308 | } | |
1309 | ||
1310 | static const char *msm_type(struct uart_port *port) | |
1311 | { | |
1312 | return "MSM"; | |
1313 | } | |
1314 | ||
1315 | static void msm_release_port(struct uart_port *port) | |
1316 | { | |
1317 | struct platform_device *pdev = to_platform_device(port->dev); | |
ec8f29e7 | 1318 | struct resource *uart_resource; |
04896a77 RL |
1319 | resource_size_t size; |
1320 | ||
ec8f29e7 SM |
1321 | uart_resource = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
1322 | if (unlikely(!uart_resource)) | |
04896a77 | 1323 | return; |
ec8f29e7 | 1324 | size = resource_size(uart_resource); |
04896a77 RL |
1325 | |
1326 | release_mem_region(port->mapbase, size); | |
1327 | iounmap(port->membase); | |
1328 | port->membase = NULL; | |
1329 | } | |
1330 | ||
1331 | static int msm_request_port(struct uart_port *port) | |
1332 | { | |
1333 | struct platform_device *pdev = to_platform_device(port->dev); | |
ec8f29e7 | 1334 | struct resource *uart_resource; |
04896a77 | 1335 | resource_size_t size; |
ec8f29e7 | 1336 | int ret; |
04896a77 | 1337 | |
886a451b | 1338 | uart_resource = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
ec8f29e7 | 1339 | if (unlikely(!uart_resource)) |
04896a77 | 1340 | return -ENXIO; |
04896a77 | 1341 | |
ec8f29e7 SM |
1342 | size = resource_size(uart_resource); |
1343 | ||
1344 | if (!request_mem_region(port->mapbase, size, "msm_serial")) | |
04896a77 RL |
1345 | return -EBUSY; |
1346 | ||
1347 | port->membase = ioremap(port->mapbase, size); | |
1348 | if (!port->membase) { | |
ec8f29e7 SM |
1349 | ret = -EBUSY; |
1350 | goto fail_release_port; | |
1351 | } | |
1352 | ||
04896a77 | 1353 | return 0; |
ec8f29e7 | 1354 | |
ec8f29e7 SM |
1355 | fail_release_port: |
1356 | release_mem_region(port->mapbase, size); | |
1357 | return ret; | |
04896a77 RL |
1358 | } |
1359 | ||
1360 | static void msm_config_port(struct uart_port *port, int flags) | |
1361 | { | |
ec8f29e7 | 1362 | int ret; |
e919cefb | 1363 | |
04896a77 RL |
1364 | if (flags & UART_CONFIG_TYPE) { |
1365 | port->type = PORT_MSM; | |
ec8f29e7 SM |
1366 | ret = msm_request_port(port); |
1367 | if (ret) | |
1368 | return; | |
04896a77 RL |
1369 | } |
1370 | } | |
1371 | ||
1372 | static int msm_verify_port(struct uart_port *port, struct serial_struct *ser) | |
1373 | { | |
1374 | if (unlikely(ser->type != PORT_UNKNOWN && ser->type != PORT_MSM)) | |
1375 | return -EINVAL; | |
1376 | if (unlikely(port->irq != ser->irq)) | |
1377 | return -EINVAL; | |
1378 | return 0; | |
1379 | } | |
1380 | ||
1381 | static void msm_power(struct uart_port *port, unsigned int state, | |
1382 | unsigned int oldstate) | |
1383 | { | |
1384 | struct msm_port *msm_port = UART_TO_MSM(port); | |
1385 | ||
1386 | switch (state) { | |
1387 | case 0: | |
f98cf83d | 1388 | clk_prepare_enable(msm_port->clk); |
bfaddb7d | 1389 | clk_prepare_enable(msm_port->pclk); |
04896a77 RL |
1390 | break; |
1391 | case 3: | |
f98cf83d | 1392 | clk_disable_unprepare(msm_port->clk); |
bfaddb7d | 1393 | clk_disable_unprepare(msm_port->pclk); |
04896a77 RL |
1394 | break; |
1395 | default: | |
6a7cfe46 | 1396 | pr_err("msm_serial: Unknown PM state %d\n", state); |
04896a77 RL |
1397 | } |
1398 | } | |
1399 | ||
f7e54d7a | 1400 | #ifdef CONFIG_CONSOLE_POLL |
f7e54d7a SB |
1401 | static int msm_poll_get_char_single(struct uart_port *port) |
1402 | { | |
1403 | struct msm_port *msm_port = UART_TO_MSM(port); | |
1404 | unsigned int rf_reg = msm_port->is_uartdm ? UARTDM_RF : UART_RF; | |
1405 | ||
1406 | if (!(msm_read(port, UART_SR) & UART_SR_RX_READY)) | |
1407 | return NO_POLL_CHAR; | |
6f47abcb KP |
1408 | |
1409 | return msm_read(port, rf_reg) & 0xff; | |
f7e54d7a SB |
1410 | } |
1411 | ||
8b374399 | 1412 | static int msm_poll_get_char_dm(struct uart_port *port) |
f7e54d7a SB |
1413 | { |
1414 | int c; | |
1415 | static u32 slop; | |
1416 | static int count; | |
1417 | unsigned char *sp = (unsigned char *)&slop; | |
1418 | ||
1419 | /* Check if a previous read had more than one char */ | |
1420 | if (count) { | |
1421 | c = sp[sizeof(slop) - count]; | |
1422 | count--; | |
1423 | /* Or if FIFO is empty */ | |
1424 | } else if (!(msm_read(port, UART_SR) & UART_SR_RX_READY)) { | |
1425 | /* | |
1426 | * If RX packing buffer has less than a word, force stale to | |
1427 | * push contents into RX FIFO | |
1428 | */ | |
1429 | count = msm_read(port, UARTDM_RXFS); | |
1430 | count = (count >> UARTDM_RXFS_BUF_SHIFT) & UARTDM_RXFS_BUF_MASK; | |
1431 | if (count) { | |
1432 | msm_write(port, UART_CR_CMD_FORCE_STALE, UART_CR); | |
1433 | slop = msm_read(port, UARTDM_RF); | |
1434 | c = sp[0]; | |
1435 | count--; | |
8b374399 SB |
1436 | msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR); |
1437 | msm_write(port, 0xFFFFFF, UARTDM_DMRX); | |
1438 | msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE, | |
1439 | UART_CR); | |
f7e54d7a SB |
1440 | } else { |
1441 | c = NO_POLL_CHAR; | |
1442 | } | |
1443 | /* FIFO has a word */ | |
1444 | } else { | |
1445 | slop = msm_read(port, UARTDM_RF); | |
1446 | c = sp[0]; | |
1447 | count = sizeof(slop) - 1; | |
1448 | } | |
1449 | ||
1450 | return c; | |
1451 | } | |
1452 | ||
1453 | static int msm_poll_get_char(struct uart_port *port) | |
1454 | { | |
1455 | u32 imr; | |
1456 | int c; | |
1457 | struct msm_port *msm_port = UART_TO_MSM(port); | |
1458 | ||
1459 | /* Disable all interrupts */ | |
1460 | imr = msm_read(port, UART_IMR); | |
1461 | msm_write(port, 0, UART_IMR); | |
1462 | ||
8b374399 SB |
1463 | if (msm_port->is_uartdm) |
1464 | c = msm_poll_get_char_dm(port); | |
f7e54d7a SB |
1465 | else |
1466 | c = msm_poll_get_char_single(port); | |
1467 | ||
1468 | /* Enable interrupts */ | |
1469 | msm_write(port, imr, UART_IMR); | |
1470 | ||
1471 | return c; | |
1472 | } | |
1473 | ||
1474 | static void msm_poll_put_char(struct uart_port *port, unsigned char c) | |
1475 | { | |
1476 | u32 imr; | |
1477 | struct msm_port *msm_port = UART_TO_MSM(port); | |
1478 | ||
1479 | /* Disable all interrupts */ | |
1480 | imr = msm_read(port, UART_IMR); | |
1481 | msm_write(port, 0, UART_IMR); | |
1482 | ||
1483 | if (msm_port->is_uartdm) | |
558abdb0 | 1484 | msm_reset_dm_count(port, 1); |
f7e54d7a SB |
1485 | |
1486 | /* Wait until FIFO is empty */ | |
1487 | while (!(msm_read(port, UART_SR) & UART_SR_TX_READY)) | |
1488 | cpu_relax(); | |
1489 | ||
1490 | /* Write a character */ | |
1491 | msm_write(port, c, msm_port->is_uartdm ? UARTDM_TF : UART_TF); | |
1492 | ||
1493 | /* Wait until FIFO is empty */ | |
1494 | while (!(msm_read(port, UART_SR) & UART_SR_TX_READY)) | |
1495 | cpu_relax(); | |
1496 | ||
1497 | /* Enable interrupts */ | |
1498 | msm_write(port, imr, UART_IMR); | |
f7e54d7a SB |
1499 | } |
1500 | #endif | |
1501 | ||
04896a77 RL |
1502 | static struct uart_ops msm_uart_pops = { |
1503 | .tx_empty = msm_tx_empty, | |
1504 | .set_mctrl = msm_set_mctrl, | |
1505 | .get_mctrl = msm_get_mctrl, | |
1506 | .stop_tx = msm_stop_tx, | |
1507 | .start_tx = msm_start_tx, | |
1508 | .stop_rx = msm_stop_rx, | |
1509 | .enable_ms = msm_enable_ms, | |
1510 | .break_ctl = msm_break_ctl, | |
1511 | .startup = msm_startup, | |
1512 | .shutdown = msm_shutdown, | |
1513 | .set_termios = msm_set_termios, | |
1514 | .type = msm_type, | |
1515 | .release_port = msm_release_port, | |
1516 | .request_port = msm_request_port, | |
1517 | .config_port = msm_config_port, | |
1518 | .verify_port = msm_verify_port, | |
1519 | .pm = msm_power, | |
f7e54d7a | 1520 | #ifdef CONFIG_CONSOLE_POLL |
f7e54d7a SB |
1521 | .poll_get_char = msm_poll_get_char, |
1522 | .poll_put_char = msm_poll_put_char, | |
1523 | #endif | |
04896a77 RL |
1524 | }; |
1525 | ||
1526 | static struct msm_port msm_uart_ports[] = { | |
1527 | { | |
1528 | .uart = { | |
1529 | .iotype = UPIO_MEM, | |
1530 | .ops = &msm_uart_pops, | |
1531 | .flags = UPF_BOOT_AUTOCONF, | |
ec8f29e7 | 1532 | .fifosize = 64, |
04896a77 RL |
1533 | .line = 0, |
1534 | }, | |
1535 | }, | |
1536 | { | |
1537 | .uart = { | |
1538 | .iotype = UPIO_MEM, | |
1539 | .ops = &msm_uart_pops, | |
1540 | .flags = UPF_BOOT_AUTOCONF, | |
ec8f29e7 | 1541 | .fifosize = 64, |
04896a77 RL |
1542 | .line = 1, |
1543 | }, | |
1544 | }, | |
1545 | { | |
1546 | .uart = { | |
1547 | .iotype = UPIO_MEM, | |
1548 | .ops = &msm_uart_pops, | |
1549 | .flags = UPF_BOOT_AUTOCONF, | |
1550 | .fifosize = 64, | |
1551 | .line = 2, | |
1552 | }, | |
1553 | }, | |
1554 | }; | |
1555 | ||
1556 | #define UART_NR ARRAY_SIZE(msm_uart_ports) | |
1557 | ||
558abdb0 | 1558 | static inline struct uart_port *msm_get_port_from_line(unsigned int line) |
04896a77 RL |
1559 | { |
1560 | return &msm_uart_ports[line].uart; | |
1561 | } | |
1562 | ||
1563 | #ifdef CONFIG_SERIAL_MSM_CONSOLE | |
0efe7296 SB |
1564 | static void __msm_console_write(struct uart_port *port, const char *s, |
1565 | unsigned int count, bool is_uartdm) | |
04896a77 | 1566 | { |
a3957e80 | 1567 | int i; |
a3957e80 SB |
1568 | int num_newlines = 0; |
1569 | bool replaced = false; | |
68252424 | 1570 | void __iomem *tf; |
04896a77 | 1571 | |
0efe7296 | 1572 | if (is_uartdm) |
68252424 SB |
1573 | tf = port->membase + UARTDM_TF; |
1574 | else | |
1575 | tf = port->membase + UART_TF; | |
1576 | ||
a3957e80 SB |
1577 | /* Account for newlines that will get a carriage return added */ |
1578 | for (i = 0; i < count; i++) | |
1579 | if (s[i] == '\n') | |
1580 | num_newlines++; | |
1581 | count += num_newlines; | |
1582 | ||
04896a77 | 1583 | spin_lock(&port->lock); |
0efe7296 | 1584 | if (is_uartdm) |
558abdb0 | 1585 | msm_reset_dm_count(port, count); |
a3957e80 SB |
1586 | |
1587 | i = 0; | |
1588 | while (i < count) { | |
1589 | int j; | |
1590 | unsigned int num_chars; | |
1591 | char buf[4] = { 0 }; | |
a3957e80 | 1592 | |
0efe7296 | 1593 | if (is_uartdm) |
a3957e80 SB |
1594 | num_chars = min(count - i, (unsigned int)sizeof(buf)); |
1595 | else | |
1596 | num_chars = 1; | |
1597 | ||
1598 | for (j = 0; j < num_chars; j++) { | |
1599 | char c = *s; | |
1600 | ||
1601 | if (c == '\n' && !replaced) { | |
1602 | buf[j] = '\r'; | |
1603 | j++; | |
1604 | replaced = true; | |
1605 | } | |
1606 | if (j < num_chars) { | |
1607 | buf[j] = c; | |
1608 | s++; | |
1609 | replaced = false; | |
1610 | } | |
1611 | } | |
1612 | ||
1613 | while (!(msm_read(port, UART_SR) & UART_SR_TX_READY)) | |
1614 | cpu_relax(); | |
1615 | ||
68252424 | 1616 | iowrite32_rep(tf, buf, 1); |
a3957e80 SB |
1617 | i += num_chars; |
1618 | } | |
04896a77 RL |
1619 | spin_unlock(&port->lock); |
1620 | } | |
1621 | ||
0efe7296 SB |
1622 | static void msm_console_write(struct console *co, const char *s, |
1623 | unsigned int count) | |
1624 | { | |
1625 | struct uart_port *port; | |
1626 | struct msm_port *msm_port; | |
1627 | ||
1628 | BUG_ON(co->index < 0 || co->index >= UART_NR); | |
1629 | ||
558abdb0 | 1630 | port = msm_get_port_from_line(co->index); |
0efe7296 SB |
1631 | msm_port = UART_TO_MSM(port); |
1632 | ||
1633 | __msm_console_write(port, s, count, msm_port->is_uartdm); | |
1634 | } | |
1635 | ||
04896a77 RL |
1636 | static int __init msm_console_setup(struct console *co, char *options) |
1637 | { | |
1638 | struct uart_port *port; | |
4daba334 PG |
1639 | int baud = 115200; |
1640 | int bits = 8; | |
1641 | int parity = 'n'; | |
1642 | int flow = 'n'; | |
04896a77 RL |
1643 | |
1644 | if (unlikely(co->index >= UART_NR || co->index < 0)) | |
1645 | return -ENXIO; | |
1646 | ||
558abdb0 | 1647 | port = msm_get_port_from_line(co->index); |
04896a77 RL |
1648 | |
1649 | if (unlikely(!port->membase)) | |
1650 | return -ENXIO; | |
1651 | ||
04896a77 RL |
1652 | msm_init_clock(port); |
1653 | ||
1654 | if (options) | |
1655 | uart_parse_options(options, &baud, &parity, &bits, &flow); | |
1656 | ||
6a7cfe46 | 1657 | pr_info("msm_serial: console setup on port #%d\n", port->line); |
04896a77 RL |
1658 | |
1659 | return uart_set_options(port, co, baud, parity, bits, flow); | |
1660 | } | |
1661 | ||
0efe7296 SB |
1662 | static void |
1663 | msm_serial_early_write(struct console *con, const char *s, unsigned n) | |
1664 | { | |
1665 | struct earlycon_device *dev = con->data; | |
1666 | ||
1667 | __msm_console_write(&dev->port, s, n, false); | |
1668 | } | |
1669 | ||
1670 | static int __init | |
1671 | msm_serial_early_console_setup(struct earlycon_device *device, const char *opt) | |
1672 | { | |
1673 | if (!device->port.membase) | |
1674 | return -ENODEV; | |
1675 | ||
1676 | device->con->write = msm_serial_early_write; | |
1677 | return 0; | |
1678 | } | |
0efe7296 SB |
1679 | OF_EARLYCON_DECLARE(msm_serial, "qcom,msm-uart", |
1680 | msm_serial_early_console_setup); | |
1681 | ||
1682 | static void | |
1683 | msm_serial_early_write_dm(struct console *con, const char *s, unsigned n) | |
1684 | { | |
1685 | struct earlycon_device *dev = con->data; | |
1686 | ||
1687 | __msm_console_write(&dev->port, s, n, true); | |
1688 | } | |
1689 | ||
1690 | static int __init | |
1691 | msm_serial_early_console_setup_dm(struct earlycon_device *device, | |
1692 | const char *opt) | |
1693 | { | |
1694 | if (!device->port.membase) | |
1695 | return -ENODEV; | |
1696 | ||
1697 | device->con->write = msm_serial_early_write_dm; | |
1698 | return 0; | |
1699 | } | |
0efe7296 SB |
1700 | OF_EARLYCON_DECLARE(msm_serial_dm, "qcom,msm-uartdm", |
1701 | msm_serial_early_console_setup_dm); | |
1702 | ||
04896a77 RL |
1703 | static struct uart_driver msm_uart_driver; |
1704 | ||
1705 | static struct console msm_console = { | |
1706 | .name = "ttyMSM", | |
1707 | .write = msm_console_write, | |
1708 | .device = uart_console_device, | |
1709 | .setup = msm_console_setup, | |
1710 | .flags = CON_PRINTBUFFER, | |
1711 | .index = -1, | |
1712 | .data = &msm_uart_driver, | |
1713 | }; | |
1714 | ||
1715 | #define MSM_CONSOLE (&msm_console) | |
1716 | ||
1717 | #else | |
1718 | #define MSM_CONSOLE NULL | |
1719 | #endif | |
1720 | ||
1721 | static struct uart_driver msm_uart_driver = { | |
1722 | .owner = THIS_MODULE, | |
1723 | .driver_name = "msm_serial", | |
1724 | .dev_name = "ttyMSM", | |
1725 | .nr = UART_NR, | |
1726 | .cons = MSM_CONSOLE, | |
1727 | }; | |
1728 | ||
cfdad2ab DB |
1729 | static atomic_t msm_uart_next_id = ATOMIC_INIT(0); |
1730 | ||
c3b5d3be | 1731 | static const struct of_device_id msm_uartdm_table[] = { |
f7e54d7a SB |
1732 | { .compatible = "qcom,msm-uartdm-v1.1", .data = (void *)UARTDM_1P1 }, |
1733 | { .compatible = "qcom,msm-uartdm-v1.2", .data = (void *)UARTDM_1P2 }, | |
1734 | { .compatible = "qcom,msm-uartdm-v1.3", .data = (void *)UARTDM_1P3 }, | |
1735 | { .compatible = "qcom,msm-uartdm-v1.4", .data = (void *)UARTDM_1P4 }, | |
c3b5d3be SB |
1736 | { } |
1737 | }; | |
1738 | ||
4cc29462 | 1739 | static int msm_serial_probe(struct platform_device *pdev) |
04896a77 RL |
1740 | { |
1741 | struct msm_port *msm_port; | |
1742 | struct resource *resource; | |
1743 | struct uart_port *port; | |
f7e54d7a | 1744 | const struct of_device_id *id; |
97f75471 | 1745 | int irq, line; |
04896a77 | 1746 | |
97f75471 SB |
1747 | if (pdev->dev.of_node) |
1748 | line = of_alias_get_id(pdev->dev.of_node, "serial"); | |
1749 | else | |
1750 | line = pdev->id; | |
1751 | ||
7920408b SB |
1752 | if (line < 0) |
1753 | line = atomic_inc_return(&msm_uart_next_id) - 1; | |
1754 | ||
97f75471 | 1755 | if (unlikely(line < 0 || line >= UART_NR)) |
04896a77 RL |
1756 | return -ENXIO; |
1757 | ||
97f75471 | 1758 | dev_info(&pdev->dev, "msm_serial: detected port #%d\n", line); |
04896a77 | 1759 | |
558abdb0 | 1760 | port = msm_get_port_from_line(line); |
04896a77 RL |
1761 | port->dev = &pdev->dev; |
1762 | msm_port = UART_TO_MSM(port); | |
1763 | ||
f7e54d7a SB |
1764 | id = of_match_device(msm_uartdm_table, &pdev->dev); |
1765 | if (id) | |
1766 | msm_port->is_uartdm = (unsigned long)id->data; | |
ec8f29e7 SM |
1767 | else |
1768 | msm_port->is_uartdm = 0; | |
1769 | ||
bfaddb7d | 1770 | msm_port->clk = devm_clk_get(&pdev->dev, "core"); |
519b371d SB |
1771 | if (IS_ERR(msm_port->clk)) |
1772 | return PTR_ERR(msm_port->clk); | |
1773 | ||
1774 | if (msm_port->is_uartdm) { | |
bfaddb7d | 1775 | msm_port->pclk = devm_clk_get(&pdev->dev, "iface"); |
519b371d SB |
1776 | if (IS_ERR(msm_port->pclk)) |
1777 | return PTR_ERR(msm_port->pclk); | |
519b371d | 1778 | } |
ec8f29e7 | 1779 | |
04896a77 | 1780 | port->uartclk = clk_get_rate(msm_port->clk); |
6a7cfe46 | 1781 | dev_info(&pdev->dev, "uartclk = %d\n", port->uartclk); |
04896a77 | 1782 | |
886a451b | 1783 | resource = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
04896a77 RL |
1784 | if (unlikely(!resource)) |
1785 | return -ENXIO; | |
1786 | port->mapbase = resource->start; | |
1787 | ||
1e091751 RK |
1788 | irq = platform_get_irq(pdev, 0); |
1789 | if (unlikely(irq < 0)) | |
04896a77 | 1790 | return -ENXIO; |
1e091751 | 1791 | port->irq = irq; |
04896a77 RL |
1792 | |
1793 | platform_set_drvdata(pdev, port); | |
1794 | ||
1795 | return uart_add_one_port(&msm_uart_driver, port); | |
1796 | } | |
1797 | ||
ae8d8a14 | 1798 | static int msm_serial_remove(struct platform_device *pdev) |
04896a77 | 1799 | { |
519b371d | 1800 | struct uart_port *port = platform_get_drvdata(pdev); |
04896a77 | 1801 | |
519b371d | 1802 | uart_remove_one_port(&msm_uart_driver, port); |
04896a77 RL |
1803 | |
1804 | return 0; | |
1805 | } | |
1806 | ||
af300539 | 1807 | static const struct of_device_id msm_match_table[] = { |
cfdad2ab | 1808 | { .compatible = "qcom,msm-uart" }, |
c3b5d3be | 1809 | { .compatible = "qcom,msm-uartdm" }, |
cfdad2ab DB |
1810 | {} |
1811 | }; | |
1812 | ||
04896a77 | 1813 | static struct platform_driver msm_platform_driver = { |
04896a77 | 1814 | .remove = msm_serial_remove, |
31964ffe | 1815 | .probe = msm_serial_probe, |
04896a77 RL |
1816 | .driver = { |
1817 | .name = "msm_serial", | |
cfdad2ab | 1818 | .of_match_table = msm_match_table, |
04896a77 RL |
1819 | }, |
1820 | }; | |
1821 | ||
1822 | static int __init msm_serial_init(void) | |
1823 | { | |
1824 | int ret; | |
1825 | ||
1826 | ret = uart_register_driver(&msm_uart_driver); | |
1827 | if (unlikely(ret)) | |
1828 | return ret; | |
1829 | ||
31964ffe | 1830 | ret = platform_driver_register(&msm_platform_driver); |
04896a77 RL |
1831 | if (unlikely(ret)) |
1832 | uart_unregister_driver(&msm_uart_driver); | |
1833 | ||
6a7cfe46 | 1834 | pr_info("msm_serial: driver initialized\n"); |
04896a77 RL |
1835 | |
1836 | return ret; | |
1837 | } | |
1838 | ||
1839 | static void __exit msm_serial_exit(void) | |
1840 | { | |
04896a77 RL |
1841 | platform_driver_unregister(&msm_platform_driver); |
1842 | uart_unregister_driver(&msm_uart_driver); | |
1843 | } | |
1844 | ||
1845 | module_init(msm_serial_init); | |
1846 | module_exit(msm_serial_exit); | |
1847 | ||
1848 | MODULE_AUTHOR("Robert Love <rlove@google.com>"); | |
1849 | MODULE_DESCRIPTION("Driver for msm7x serial device"); | |
1850 | MODULE_LICENSE("GPL"); |