projects / linux-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
tty: add SPDX identifiers to all remaining files in drivers/tty/
[linux-block.git] / drivers / tty / serial / mpsc.c
CommitLineData
e3b3d0f5 1// SPDX-License-Identifier: GPL-2.0
1da177e4 2/*
1da177e4
LT		 3 * Generic driver for the MPSC (UART mode) on Marvell parts (e.g., GT64240,
4 * GT64260, MV64340, MV64360, GT96100, ... ).
5 *
6 * Author: Mark A. Greer <mgreer@mvista.com>
7 *
8 * Based on an old MPSC driver that was in the linuxppc tree. It appears to
9 * have been created by Chris Zankel (formerly of MontaVista) but there
10 * is no proper Copyright so I'm not sure. Apparently, parts were also
11 * taken from PPCBoot (now U-Boot). Also based on drivers/serial/8250.c
12 * by Russell King.
13 *
14 * 2004 (c) MontaVista, Software, Inc. This file is licensed under
15 * the terms of the GNU General Public License version 2. This program
16 * is licensed "as is" without any warranty of any kind, whether express
17 * or implied.
18 */
19/*
20 * The MPSC interface is much like a typical network controller's interface.
21 * That is, you set up separate rings of descriptors for transmitting and
22 * receiving data. There is also a pool of buffers with (one buffer per
23 * descriptor) that incoming data are dma'd into or outgoing data are dma'd
24 * out of.
25 *
26 * The MPSC requires two other controllers to be able to work. The Baud Rate
27 * Generator (BRG) provides a clock at programmable frequencies which determines
28 * the baud rate. The Serial DMA Controller (SDMA) takes incoming data from the
29 * MPSC and DMA's it into memory or DMA's outgoing data and passes it to the
30 * MPSC. It is actually the SDMA interrupt that the driver uses to keep the
31 * transmit and receive "engines" going (i.e., indicate data has been
32 * transmitted or received).
33 *
34 * NOTES:
35 *
36 * 1) Some chips have an erratum where several regs cannot be
37 * read. To work around that, we keep a local copy of those regs in
38 * 'mpsc_port_info'.
39 *
40 * 2) Some chips have an erratum where the ctlr will hang when the SDMA ctlr
41 * accesses system mem with coherency enabled. For that reason, the driver
42 * assumes that coherency for that ctlr has been disabled. This means
43 * that when in a cache coherent system, the driver has to manually manage
44 * the data cache on the areas that it touches because the dma_* macro are
45 * basically no-ops.
46 *
47 * 3) There is an erratum (on PPC) where you can't use the instruction to do
48 * a DMA_TO_DEVICE/cache clean so DMA_BIDIRECTIONAL/flushes are used in places
49 * where a DMA_TO_DEVICE/clean would have [otherwise] sufficed.
50 *
51 * 4) AFAICT, hardware flow control isn't supported by the controller --MAG.
52 */
53
e4294b3e
MG		 54
55#if defined(CONFIG_SERIAL_MPSC_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
56#define SUPPORT_SYSRQ
57#endif
58
e4294b3e
MG		 59#include <linux/tty.h>
60#include <linux/tty_flip.h>
61#include <linux/ioport.h>
62#include <linux/init.h>
63#include <linux/console.h>
64#include <linux/sysrq.h>
65#include <linux/serial.h>
66#include <linux/serial_core.h>
67#include <linux/delay.h>
68#include <linux/device.h>
69#include <linux/dma-mapping.h>
70#include <linux/mv643xx.h>
d052d1be 71#include <linux/platform_device.h>
5a0e3ad6 72#include <linux/gfp.h>
d052d1be 73
e4294b3e
MG		 74#include <asm/io.h>
75#include <asm/irq.h>
76
e4294b3e
MG		 77#define MPSC_NUM_CTLRS 2
78
79/*
80 * Descriptors and buffers must be cache line aligned.
81 * Buffers lengths must be multiple of cache line size.
82 * Number of Tx & Rx descriptors must be powers of 2.
83 */
84#define MPSC_RXR_ENTRIES 32
85#define MPSC_RXRE_SIZE dma_get_cache_alignment()
86#define MPSC_RXR_SIZE (MPSC_RXR_ENTRIES * MPSC_RXRE_SIZE)
87#define MPSC_RXBE_SIZE dma_get_cache_alignment()
88#define MPSC_RXB_SIZE (MPSC_RXR_ENTRIES * MPSC_RXBE_SIZE)
89
90#define MPSC_TXR_ENTRIES 32
91#define MPSC_TXRE_SIZE dma_get_cache_alignment()
92#define MPSC_TXR_SIZE (MPSC_TXR_ENTRIES * MPSC_TXRE_SIZE)
93#define MPSC_TXBE_SIZE dma_get_cache_alignment()
94#define MPSC_TXB_SIZE (MPSC_TXR_ENTRIES * MPSC_TXBE_SIZE)
95
2e89db75
MG		 96#define MPSC_DMA_ALLOC_SIZE (MPSC_RXR_SIZE + MPSC_RXB_SIZE + MPSC_TXR_SIZE \
97 + MPSC_TXB_SIZE + dma_get_cache_alignment() /* for alignment */)
e4294b3e
MG		 98
99/* Rx and Tx Ring entry descriptors -- assume entry size is <= cacheline size */
100struct mpsc_rx_desc {
101 u16 bufsize;
102 u16 bytecnt;
103 u32 cmdstat;
104 u32 link;
105 u32 buf_ptr;
106} __attribute((packed));
107
108struct mpsc_tx_desc {
109 u16 bytecnt;
110 u16 shadow;
111 u32 cmdstat;
112 u32 link;
113 u32 buf_ptr;
114} __attribute((packed));
115
116/*
117 * Some regs that have the erratum that you can't read them are are shared
118 * between the two MPSC controllers. This struct contains those shared regs.
119 */
120struct mpsc_shared_regs {
121 phys_addr_t mpsc_routing_base_p;
122 phys_addr_t sdma_intr_base_p;
123
124 void __iomem *mpsc_routing_base;
125 void __iomem *sdma_intr_base;
126
127 u32 MPSC_MRR_m;
128 u32 MPSC_RCRR_m;
129 u32 MPSC_TCRR_m;
130 u32 SDMA_INTR_CAUSE_m;
131 u32 SDMA_INTR_MASK_m;
132};
133
134/* The main driver data structure */
135struct mpsc_port_info {
136 struct uart_port port; /* Overlay uart_port structure */
137
138 /* Internal driver state for this ctlr */
139 u8 ready;
140 u8 rcv_data;
e4294b3e
MG		 141
142 /* Info passed in from platform */
143 u8 mirror_regs; /* Need to mirror regs? */
144 u8 cache_mgmt; /* Need manual cache mgmt? */
145 u8 brg_can_tune; /* BRG has baud tuning? */
146 u32 brg_clk_src;
147 u16 mpsc_max_idle;
148 int default_baud;
149 int default_bits;
150 int default_parity;
151 int default_flow;
152
153 /* Physical addresses of various blocks of registers (from platform) */
154 phys_addr_t mpsc_base_p;
155 phys_addr_t sdma_base_p;
156 phys_addr_t brg_base_p;
157
158 /* Virtual addresses of various blocks of registers (from platform) */
159 void __iomem *mpsc_base;
160 void __iomem *sdma_base;
161 void __iomem *brg_base;
162
163 /* Descriptor ring and buffer allocations */
164 void *dma_region;
165 dma_addr_t dma_region_p;
166
167 dma_addr_t rxr; /* Rx descriptor ring */
168 dma_addr_t rxr_p; /* Phys addr of rxr */
169 u8 *rxb; /* Rx Ring I/O buf */
170 u8 *rxb_p; /* Phys addr of rxb */
171 u32 rxr_posn; /* First desc w/ Rx data */
172
173 dma_addr_t txr; /* Tx descriptor ring */
174 dma_addr_t txr_p; /* Phys addr of txr */
175 u8 *txb; /* Tx Ring I/O buf */
176 u8 *txb_p; /* Phys addr of txb */
177 int txr_head; /* Where new data goes */
178 int txr_tail; /* Where sent data comes off */
1733310b 179 spinlock_t tx_lock; /* transmit lock */
e4294b3e
MG		 180
181 /* Mirrored values of regs we can't read (if 'mirror_regs' set) */
182 u32 MPSC_MPCR_m;
183 u32 MPSC_CHR_1_m;
184 u32 MPSC_CHR_2_m;
185 u32 MPSC_CHR_10_m;
186 u32 BRG_BCR_m;
187 struct mpsc_shared_regs *shared_regs;
188};
189
190/* Hooks to platform-specific code */
191int mpsc_platform_register_driver(void);
192void mpsc_platform_unregister_driver(void);
193
194/* Hooks back in to mpsc common to be called by platform-specific code */
195struct mpsc_port_info *mpsc_device_probe(int index);
196struct mpsc_port_info *mpsc_device_remove(int index);
197
198/* Main MPSC Configuration Register Offsets */
199#define MPSC_MMCRL 0x0000
200#define MPSC_MMCRH 0x0004
201#define MPSC_MPCR 0x0008
202#define MPSC_CHR_1 0x000c
203#define MPSC_CHR_2 0x0010
204#define MPSC_CHR_3 0x0014
205#define MPSC_CHR_4 0x0018
206#define MPSC_CHR_5 0x001c
207#define MPSC_CHR_6 0x0020
208#define MPSC_CHR_7 0x0024
209#define MPSC_CHR_8 0x0028
210#define MPSC_CHR_9 0x002c
211#define MPSC_CHR_10 0x0030
212#define MPSC_CHR_11 0x0034
213
214#define MPSC_MPCR_FRZ (1 << 9)
215#define MPSC_MPCR_CL_5 0
216#define MPSC_MPCR_CL_6 1
217#define MPSC_MPCR_CL_7 2
218#define MPSC_MPCR_CL_8 3
219#define MPSC_MPCR_SBL_1 0
220#define MPSC_MPCR_SBL_2 1
221
222#define MPSC_CHR_2_TEV (1<<1)
223#define MPSC_CHR_2_TA (1<<7)
224#define MPSC_CHR_2_TTCS (1<<9)
225#define MPSC_CHR_2_REV (1<<17)
226#define MPSC_CHR_2_RA (1<<23)
227#define MPSC_CHR_2_CRD (1<<25)
228#define MPSC_CHR_2_EH (1<<31)
229#define MPSC_CHR_2_PAR_ODD 0
230#define MPSC_CHR_2_PAR_SPACE 1
231#define MPSC_CHR_2_PAR_EVEN 2
232#define MPSC_CHR_2_PAR_MARK 3
233
234/* MPSC Signal Routing */
235#define MPSC_MRR 0x0000
236#define MPSC_RCRR 0x0004
237#define MPSC_TCRR 0x0008
238
239/* Serial DMA Controller Interface Registers */
240#define SDMA_SDC 0x0000
241#define SDMA_SDCM 0x0008
242#define SDMA_RX_DESC 0x0800
243#define SDMA_RX_BUF_PTR 0x0808
244#define SDMA_SCRDP 0x0810
245#define SDMA_TX_DESC 0x0c00
246#define SDMA_SCTDP 0x0c10
247#define SDMA_SFTDP 0x0c14
248
249#define SDMA_DESC_CMDSTAT_PE (1<<0)
250#define SDMA_DESC_CMDSTAT_CDL (1<<1)
251#define SDMA_DESC_CMDSTAT_FR (1<<3)
252#define SDMA_DESC_CMDSTAT_OR (1<<6)
253#define SDMA_DESC_CMDSTAT_BR (1<<9)
254#define SDMA_DESC_CMDSTAT_MI (1<<10)
255#define SDMA_DESC_CMDSTAT_A (1<<11)
256#define SDMA_DESC_CMDSTAT_AM (1<<12)
257#define SDMA_DESC_CMDSTAT_CT (1<<13)
258#define SDMA_DESC_CMDSTAT_C (1<<14)
259#define SDMA_DESC_CMDSTAT_ES (1<<15)
260#define SDMA_DESC_CMDSTAT_L (1<<16)
261#define SDMA_DESC_CMDSTAT_F (1<<17)
262#define SDMA_DESC_CMDSTAT_P (1<<18)
263#define SDMA_DESC_CMDSTAT_EI (1<<23)
264#define SDMA_DESC_CMDSTAT_O (1<<31)
265
2e89db75
MG		 266#define SDMA_DESC_DFLT (SDMA_DESC_CMDSTAT_O \
267 | SDMA_DESC_CMDSTAT_EI)
e4294b3e
MG		 268
269#define SDMA_SDC_RFT (1<<0)
270#define SDMA_SDC_SFM (1<<1)
271#define SDMA_SDC_BLMR (1<<6)
272#define SDMA_SDC_BLMT (1<<7)
273#define SDMA_SDC_POVR (1<<8)
274#define SDMA_SDC_RIFB (1<<9)
275
276#define SDMA_SDCM_ERD (1<<7)
277#define SDMA_SDCM_AR (1<<15)
278#define SDMA_SDCM_STD (1<<16)
279#define SDMA_SDCM_TXD (1<<23)
280#define SDMA_SDCM_AT (1<<31)
281
282#define SDMA_0_CAUSE_RXBUF (1<<0)
283#define SDMA_0_CAUSE_RXERR (1<<1)
284#define SDMA_0_CAUSE_TXBUF (1<<2)
285#define SDMA_0_CAUSE_TXEND (1<<3)
286#define SDMA_1_CAUSE_RXBUF (1<<8)
287#define SDMA_1_CAUSE_RXERR (1<<9)
288#define SDMA_1_CAUSE_TXBUF (1<<10)
289#define SDMA_1_CAUSE_TXEND (1<<11)
290
2e89db75
MG		 291#define SDMA_CAUSE_RX_MASK (SDMA_0_CAUSE_RXBUF | SDMA_0_CAUSE_RXERR \
292 | SDMA_1_CAUSE_RXBUF | SDMA_1_CAUSE_RXERR)
293#define SDMA_CAUSE_TX_MASK (SDMA_0_CAUSE_TXBUF | SDMA_0_CAUSE_TXEND \
294 | SDMA_1_CAUSE_TXBUF | SDMA_1_CAUSE_TXEND)
e4294b3e
MG		 295
296/* SDMA Interrupt registers */
297#define SDMA_INTR_CAUSE 0x0000
298#define SDMA_INTR_MASK 0x0080
299
300/* Baud Rate Generator Interface Registers */
301#define BRG_BCR 0x0000
302#define BRG_BTR 0x0004
1da177e4
LT		 303
304/*
305 * Define how this driver is known to the outside (we've been assigned a
306 * range on the "Low-density serial ports" major).
307 */
2e89db75
MG		 308#define MPSC_MAJOR 204
309#define MPSC_MINOR_START 44
310#define MPSC_DRIVER_NAME "MPSC"
311#define MPSC_DEV_NAME "ttyMM"
312#define MPSC_VERSION "1.00"
1da177e4
LT		 313
314static struct mpsc_port_info mpsc_ports[MPSC_NUM_CTLRS];
315static struct mpsc_shared_regs mpsc_shared_regs;
4d0145a7 316static struct uart_driver mpsc_reg;
1da177e4 317
4d0145a7
LN		 318static void mpsc_start_rx(struct mpsc_port_info *pi);
319static void mpsc_free_ring_mem(struct mpsc_port_info *pi);
320static void mpsc_release_port(struct uart_port *port);
1da177e4
LT		 321/*
322 ******************************************************************************
323 *
324 * Baud Rate Generator Routines (BRG)
325 *
326 ******************************************************************************
327 */
2e89db75 328static void mpsc_brg_init(struct mpsc_port_info *pi, u32 clk_src)
1da177e4
LT		 329{
330 u32 v;
331
332 v = (pi->mirror_regs) ? pi->BRG_BCR_m : readl(pi->brg_base + BRG_BCR);
333 v = (v & ~(0xf << 18)) | ((clk_src & 0xf) << 18);
334
335 if (pi->brg_can_tune)
336 v &= ~(1 << 25);
337
338 if (pi->mirror_regs)
339 pi->BRG_BCR_m = v;
340 writel(v, pi->brg_base + BRG_BCR);
341
342 writel(readl(pi->brg_base + BRG_BTR) & 0xffff0000,
343 pi->brg_base + BRG_BTR);
1da177e4
LT		 344}
345
2e89db75 346static void mpsc_brg_enable(struct mpsc_port_info *pi)
1da177e4
LT		 347{
348 u32 v;
349
350 v = (pi->mirror_regs) ? pi->BRG_BCR_m : readl(pi->brg_base + BRG_BCR);
351 v |= (1 << 16);
352
353 if (pi->mirror_regs)
354 pi->BRG_BCR_m = v;
355 writel(v, pi->brg_base + BRG_BCR);
1da177e4
LT		 356}
357
2e89db75 358static void mpsc_brg_disable(struct mpsc_port_info *pi)
1da177e4
LT		 359{
360 u32 v;
361
362 v = (pi->mirror_regs) ? pi->BRG_BCR_m : readl(pi->brg_base + BRG_BCR);
363 v &= ~(1 << 16);
364
365 if (pi->mirror_regs)
366 pi->BRG_BCR_m = v;
367 writel(v, pi->brg_base + BRG_BCR);
1da177e4
LT		 368}
369
2e89db75
MG		 370/*
371 * To set the baud, we adjust the CDV field in the BRG_BCR reg.
372 * From manual: Baud = clk / ((CDV+1)*2) ==> CDV = (clk / (baud*2)) - 1.
373 * However, the input clock is divided by 16 in the MPSC b/c of how
374 * 'MPSC_MMCRH' was set up so we have to divide the 'clk' used in our
375 * calculation by 16 to account for that. So the real calculation
376 * that accounts for the way the mpsc is set up is:
377 * CDV = (clk / (baud*2*16)) - 1 ==> CDV = (clk / (baud << 5)) - 1.
378 */
379static void mpsc_set_baudrate(struct mpsc_port_info *pi, u32 baud)
1da177e4 380{
1da177e4
LT		 381 u32 cdv = (pi->port.uartclk / (baud << 5)) - 1;
382 u32 v;
383
384 mpsc_brg_disable(pi);
385 v = (pi->mirror_regs) ? pi->BRG_BCR_m : readl(pi->brg_base + BRG_BCR);
386 v = (v & 0xffff0000) | (cdv & 0xffff);
387
388 if (pi->mirror_regs)
389 pi->BRG_BCR_m = v;
390 writel(v, pi->brg_base + BRG_BCR);
391 mpsc_brg_enable(pi);
1da177e4
LT		 392}
393
394/*
395 ******************************************************************************
396 *
397 * Serial DMA Routines (SDMA)
398 *
399 ******************************************************************************
400 */
401
2e89db75 402static void mpsc_sdma_burstsize(struct mpsc_port_info *pi, u32 burst_size)
1da177e4
LT		 403{
404 u32 v;
405
406 pr_debug("mpsc_sdma_burstsize[%d]: burst_size: %d\n",
2e89db75 407 pi->port.line, burst_size);
1da177e4
LT		 408
409 burst_size >>= 3; /* Divide by 8 b/c reg values are 8-byte chunks */
410
411 if (burst_size < 2)
412 v = 0x0; /* 1 64-bit word */
413 else if (burst_size < 4)
414 v = 0x1; /* 2 64-bit words */
415 else if (burst_size < 8)
416 v = 0x2; /* 4 64-bit words */
417 else
418 v = 0x3; /* 8 64-bit words */
419
420 writel((readl(pi->sdma_base + SDMA_SDC) & (0x3 << 12)) | (v << 12),
421 pi->sdma_base + SDMA_SDC);
1da177e4
LT		 422}
423
2e89db75 424static void mpsc_sdma_init(struct mpsc_port_info *pi, u32 burst_size)
1da177e4
LT		 425{
426 pr_debug("mpsc_sdma_init[%d]: burst_size: %d\n", pi->port.line,
427 burst_size);
428
429 writel((readl(pi->sdma_base + SDMA_SDC) & 0x3ff) | 0x03f,
430 pi->sdma_base + SDMA_SDC);
431 mpsc_sdma_burstsize(pi, burst_size);
1da177e4
LT		 432}
433
2e89db75 434static u32 mpsc_sdma_intr_mask(struct mpsc_port_info *pi, u32 mask)
1da177e4
LT		 435{
436 u32 old, v;
437
438 pr_debug("mpsc_sdma_intr_mask[%d]: mask: 0x%x\n", pi->port.line, mask);
439
440 old = v = (pi->mirror_regs) ? pi->shared_regs->SDMA_INTR_MASK_m :
441 readl(pi->shared_regs->sdma_intr_base + SDMA_INTR_MASK);
442
443 mask &= 0xf;
444 if (pi->port.line)
445 mask <<= 8;
446 v &= ~mask;
447
448 if (pi->mirror_regs)
449 pi->shared_regs->SDMA_INTR_MASK_m = v;
450 writel(v, pi->shared_regs->sdma_intr_base + SDMA_INTR_MASK);
451
452 if (pi->port.line)
453 old >>= 8;
454 return old & 0xf;
455}
456
2e89db75 457static void mpsc_sdma_intr_unmask(struct mpsc_port_info *pi, u32 mask)
1da177e4
LT		 458{
459 u32 v;
460
461 pr_debug("mpsc_sdma_intr_unmask[%d]: mask: 0x%x\n", pi->port.line,mask);
462
2e89db75
MG		 463 v = (pi->mirror_regs) ? pi->shared_regs->SDMA_INTR_MASK_m
464 : readl(pi->shared_regs->sdma_intr_base + SDMA_INTR_MASK);
1da177e4
LT		 465
466 mask &= 0xf;
467 if (pi->port.line)
468 mask <<= 8;
469 v |= mask;
470
471 if (pi->mirror_regs)
472 pi->shared_regs->SDMA_INTR_MASK_m = v;
473 writel(v, pi->shared_regs->sdma_intr_base + SDMA_INTR_MASK);
1da177e4
LT		 474}
475
2e89db75 476static void mpsc_sdma_intr_ack(struct mpsc_port_info *pi)
1da177e4
LT		 477{
478 pr_debug("mpsc_sdma_intr_ack[%d]: Acknowledging IRQ\n", pi->port.line);
479
480 if (pi->mirror_regs)
481 pi->shared_regs->SDMA_INTR_CAUSE_m = 0;
2e89db75
MG		 482 writeb(0x00, pi->shared_regs->sdma_intr_base + SDMA_INTR_CAUSE
483 + pi->port.line);
1da177e4
LT		 484}
485
2e89db75
MG		 486static void mpsc_sdma_set_rx_ring(struct mpsc_port_info *pi,
487 struct mpsc_rx_desc *rxre_p)
1da177e4
LT		 488{
489 pr_debug("mpsc_sdma_set_rx_ring[%d]: rxre_p: 0x%x\n",
2e89db75 490 pi->port.line, (u32)rxre_p);
1da177e4
LT		 491
492 writel((u32)rxre_p, pi->sdma_base + SDMA_SCRDP);
1da177e4
LT		 493}
494
2e89db75
MG		 495static void mpsc_sdma_set_tx_ring(struct mpsc_port_info *pi,
496 struct mpsc_tx_desc *txre_p)
1da177e4
LT		 497{
498 writel((u32)txre_p, pi->sdma_base + SDMA_SFTDP);
499 writel((u32)txre_p, pi->sdma_base + SDMA_SCTDP);
1da177e4
LT		 500}
501
2e89db75 502static void mpsc_sdma_cmd(struct mpsc_port_info *pi, u32 val)
1da177e4
LT		 503{
504 u32 v;
505
506 v = readl(pi->sdma_base + SDMA_SDCM);
507 if (val)
508 v |= val;
509 else
510 v = 0;
511 wmb();
512 writel(v, pi->sdma_base + SDMA_SDCM);
513 wmb();
1da177e4
LT		 514}
515
2e89db75 516static uint mpsc_sdma_tx_active(struct mpsc_port_info *pi)
1da177e4
LT		 517{
518 return readl(pi->sdma_base + SDMA_SDCM) & SDMA_SDCM_TXD;
519}
520
2e89db75 521static void mpsc_sdma_start_tx(struct mpsc_port_info *pi)
1da177e4
LT		 522{
523 struct mpsc_tx_desc *txre, *txre_p;
524
525 /* If tx isn't running & there's a desc ready to go, start it */
526 if (!mpsc_sdma_tx_active(pi)) {
2e89db75
MG		 527 txre = (struct mpsc_tx_desc *)(pi->txr
528 + (pi->txr_tail * MPSC_TXRE_SIZE));
529 dma_cache_sync(pi->port.dev, (void *)txre, MPSC_TXRE_SIZE,
530 DMA_FROM_DEVICE);
1da177e4
LT		 531#if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
532 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
533 invalidate_dcache_range((ulong)txre,
2e89db75 534 (ulong)txre + MPSC_TXRE_SIZE);
1da177e4
LT		 535#endif
536
537 if (be32_to_cpu(txre->cmdstat) & SDMA_DESC_CMDSTAT_O) {
2e89db75
MG		 538 txre_p = (struct mpsc_tx_desc *)
539 (pi->txr_p + (pi->txr_tail * MPSC_TXRE_SIZE));
1da177e4
LT		 540
541 mpsc_sdma_set_tx_ring(pi, txre_p);
542 mpsc_sdma_cmd(pi, SDMA_SDCM_STD | SDMA_SDCM_TXD);
543 }
544 }
1da177e4
LT		 545}
546
2e89db75 547static void mpsc_sdma_stop(struct mpsc_port_info *pi)
1da177e4
LT		 548{
549 pr_debug("mpsc_sdma_stop[%d]: Stopping SDMA\n", pi->port.line);
550
551 /* Abort any SDMA transfers */
552 mpsc_sdma_cmd(pi, 0);
553 mpsc_sdma_cmd(pi, SDMA_SDCM_AR | SDMA_SDCM_AT);
554
555 /* Clear the SDMA current and first TX and RX pointers */
2c6e7599
AV		 556 mpsc_sdma_set_tx_ring(pi, NULL);
557 mpsc_sdma_set_rx_ring(pi, NULL);
1da177e4
LT		 558
559 /* Disable interrupts */
560 mpsc_sdma_intr_mask(pi, 0xf);
561 mpsc_sdma_intr_ack(pi);
1da177e4
LT		 562}
563
564/*
565 ******************************************************************************
566 *
567 * Multi-Protocol Serial Controller Routines (MPSC)
568 *
569 ******************************************************************************
570 */
571
2e89db75 572static void mpsc_hw_init(struct mpsc_port_info *pi)
1da177e4
LT		 573{
574 u32 v;
575
576 pr_debug("mpsc_hw_init[%d]: Initializing hardware\n", pi->port.line);
577
578 /* Set up clock routing */
579 if (pi->mirror_regs) {
580 v = pi->shared_regs->MPSC_MRR_m;
581 v &= ~0x1c7;
582 pi->shared_regs->MPSC_MRR_m = v;
583 writel(v, pi->shared_regs->mpsc_routing_base + MPSC_MRR);
584
585 v = pi->shared_regs->MPSC_RCRR_m;
586 v = (v & ~0xf0f) | 0x100;
587 pi->shared_regs->MPSC_RCRR_m = v;
588 writel(v, pi->shared_regs->mpsc_routing_base + MPSC_RCRR);
589
590 v = pi->shared_regs->MPSC_TCRR_m;
591 v = (v & ~0xf0f) | 0x100;
592 pi->shared_regs->MPSC_TCRR_m = v;
593 writel(v, pi->shared_regs->mpsc_routing_base + MPSC_TCRR);
2e89db75 594 } else {
1da177e4
LT		 595 v = readl(pi->shared_regs->mpsc_routing_base + MPSC_MRR);
596 v &= ~0x1c7;
597 writel(v, pi->shared_regs->mpsc_routing_base + MPSC_MRR);
598
599 v = readl(pi->shared_regs->mpsc_routing_base + MPSC_RCRR);
600 v = (v & ~0xf0f) | 0x100;
601 writel(v, pi->shared_regs->mpsc_routing_base + MPSC_RCRR);
602
603 v = readl(pi->shared_regs->mpsc_routing_base + MPSC_TCRR);
604 v = (v & ~0xf0f) | 0x100;
605 writel(v, pi->shared_regs->mpsc_routing_base + MPSC_TCRR);
606 }
607
608 /* Put MPSC in UART mode & enabel Tx/Rx egines */
609 writel(0x000004c4, pi->mpsc_base + MPSC_MMCRL);
610
2e89db75 611 /* No preamble, 16x divider, low-latency, */
1da177e4 612 writel(0x04400400, pi->mpsc_base + MPSC_MMCRH);
7bbdc3d5 613 mpsc_set_baudrate(pi, pi->default_baud);
1da177e4
LT		 614
615 if (pi->mirror_regs) {
616 pi->MPSC_CHR_1_m = 0;
617 pi->MPSC_CHR_2_m = 0;
618 }
619 writel(0, pi->mpsc_base + MPSC_CHR_1);
620 writel(0, pi->mpsc_base + MPSC_CHR_2);
621 writel(pi->mpsc_max_idle, pi->mpsc_base + MPSC_CHR_3);
622 writel(0, pi->mpsc_base + MPSC_CHR_4);
623 writel(0, pi->mpsc_base + MPSC_CHR_5);
624 writel(0, pi->mpsc_base + MPSC_CHR_6);
625 writel(0, pi->mpsc_base + MPSC_CHR_7);
626 writel(0, pi->mpsc_base + MPSC_CHR_8);
627 writel(0, pi->mpsc_base + MPSC_CHR_9);
628 writel(0, pi->mpsc_base + MPSC_CHR_10);
1da177e4
LT		 629}
630
2e89db75 631static void mpsc_enter_hunt(struct mpsc_port_info *pi)
1da177e4
LT		 632{
633 pr_debug("mpsc_enter_hunt[%d]: Hunting...\n", pi->port.line);
634
635 if (pi->mirror_regs) {
636 writel(pi->MPSC_CHR_2_m | MPSC_CHR_2_EH,
637 pi->mpsc_base + MPSC_CHR_2);
638 /* Erratum prevents reading CHR_2 so just delay for a while */
639 udelay(100);
2e89db75 640 } else {
1da177e4 641 writel(readl(pi->mpsc_base + MPSC_CHR_2) | MPSC_CHR_2_EH,
2e89db75 642 pi->mpsc_base + MPSC_CHR_2);
1da177e4
LT		 643
644 while (readl(pi->mpsc_base + MPSC_CHR_2) & MPSC_CHR_2_EH)
645 udelay(10);
646 }
1da177e4
LT		 647}
648
2e89db75 649static void mpsc_freeze(struct mpsc_port_info *pi)
1da177e4
LT		 650{
651 u32 v;
652
653 pr_debug("mpsc_freeze[%d]: Freezing\n", pi->port.line);
654
655 v = (pi->mirror_regs) ? pi->MPSC_MPCR_m :
656 readl(pi->mpsc_base + MPSC_MPCR);
657 v |= MPSC_MPCR_FRZ;
658
659 if (pi->mirror_regs)
660 pi->MPSC_MPCR_m = v;
661 writel(v, pi->mpsc_base + MPSC_MPCR);
1da177e4
LT		 662}
663
2e89db75 664static void mpsc_unfreeze(struct mpsc_port_info *pi)
1da177e4
LT		 665{
666 u32 v;
667
668 v = (pi->mirror_regs) ? pi->MPSC_MPCR_m :
669 readl(pi->mpsc_base + MPSC_MPCR);
670 v &= ~MPSC_MPCR_FRZ;
671
672 if (pi->mirror_regs)
673 pi->MPSC_MPCR_m = v;
674 writel(v, pi->mpsc_base + MPSC_MPCR);
675
676 pr_debug("mpsc_unfreeze[%d]: Unfrozen\n", pi->port.line);
1da177e4
LT		 677}
678
2e89db75 679static void mpsc_set_char_length(struct mpsc_port_info *pi, u32 len)
1da177e4
LT		 680{
681 u32 v;
682
683 pr_debug("mpsc_set_char_length[%d]: char len: %d\n", pi->port.line,len);
684
685 v = (pi->mirror_regs) ? pi->MPSC_MPCR_m :
686 readl(pi->mpsc_base + MPSC_MPCR);
687 v = (v & ~(0x3 << 12)) | ((len & 0x3) << 12);
688
689 if (pi->mirror_regs)
690 pi->MPSC_MPCR_m = v;
691 writel(v, pi->mpsc_base + MPSC_MPCR);
1da177e4
LT		 692}
693
2e89db75 694static void mpsc_set_stop_bit_length(struct mpsc_port_info *pi, u32 len)
1da177e4
LT		 695{
696 u32 v;
697
698 pr_debug("mpsc_set_stop_bit_length[%d]: stop bits: %d\n",
699 pi->port.line, len);
700
701 v = (pi->mirror_regs) ? pi->MPSC_MPCR_m :
702 readl(pi->mpsc_base + MPSC_MPCR);
703
704 v = (v & ~(1 << 14)) | ((len & 0x1) << 14);
705
706 if (pi->mirror_regs)
707 pi->MPSC_MPCR_m = v;
708 writel(v, pi->mpsc_base + MPSC_MPCR);
1da177e4
LT		 709}
710
2e89db75 711static void mpsc_set_parity(struct mpsc_port_info *pi, u32 p)
1da177e4
LT		 712{
713 u32 v;
714
715 pr_debug("mpsc_set_parity[%d]: parity bits: 0x%x\n", pi->port.line, p);
716
717 v = (pi->mirror_regs) ? pi->MPSC_CHR_2_m :
718 readl(pi->mpsc_base + MPSC_CHR_2);
719
720 p &= 0x3;
721 v = (v & ~0xc000c) | (p << 18) | (p << 2);
722
723 if (pi->mirror_regs)
724 pi->MPSC_CHR_2_m = v;
725 writel(v, pi->mpsc_base + MPSC_CHR_2);
1da177e4
LT		 726}
727
728/*
729 ******************************************************************************
730 *
731 * Driver Init Routines
732 *
733 ******************************************************************************
734 */
735
2e89db75 736static void mpsc_init_hw(struct mpsc_port_info *pi)
1da177e4
LT		 737{
738 pr_debug("mpsc_init_hw[%d]: Initializing\n", pi->port.line);
739
740 mpsc_brg_init(pi, pi->brg_clk_src);
741 mpsc_brg_enable(pi);
742 mpsc_sdma_init(pi, dma_get_cache_alignment()); /* burst a cacheline */
743 mpsc_sdma_stop(pi);
744 mpsc_hw_init(pi);
1da177e4
LT		 745}
746
2e89db75 747static int mpsc_alloc_ring_mem(struct mpsc_port_info *pi)
1da177e4
LT		 748{
749 int rc = 0;
1da177e4
LT		 750
751 pr_debug("mpsc_alloc_ring_mem[%d]: Allocating ring mem\n",
752 pi->port.line);
753
754 if (!pi->dma_region) {
fc12c116 755 if (!dma_set_mask(pi->port.dev, 0xffffffff)) {
1da177e4
LT		 756 printk(KERN_ERR "MPSC: Inadequate DMA support\n");
757 rc = -ENXIO;
7b45fff0 758 } else if ((pi->dma_region = dma_alloc_attrs(pi->port.dev,
2e89db75 759 MPSC_DMA_ALLOC_SIZE,
7b45fff0
CH		 760 &pi->dma_region_p, GFP_KERNEL,
761 DMA_ATTR_NON_CONSISTENT))
2e89db75 762 == NULL) {
1da177e4
LT		 763 printk(KERN_ERR "MPSC: Can't alloc Desc region\n");
764 rc = -ENOMEM;
765 }
766 }
767
768 return rc;
769}
770
2e89db75 771static void mpsc_free_ring_mem(struct mpsc_port_info *pi)
1da177e4
LT		 772{
773 pr_debug("mpsc_free_ring_mem[%d]: Freeing ring mem\n", pi->port.line);
774
775 if (pi->dma_region) {
7b45fff0
CH		 776 dma_free_attrs(pi->port.dev, MPSC_DMA_ALLOC_SIZE,
777 pi->dma_region, pi->dma_region_p,
778 DMA_ATTR_NON_CONSISTENT);
1da177e4 779 pi->dma_region = NULL;
2e89db75 780 pi->dma_region_p = (dma_addr_t)NULL;
1da177e4 781 }
1da177e4
LT		 782}
783
2e89db75 784static void mpsc_init_rings(struct mpsc_port_info *pi)
1da177e4
LT		 785{
786 struct mpsc_rx_desc *rxre;
787 struct mpsc_tx_desc *txre;
788 dma_addr_t dp, dp_p;
789 u8 *bp, *bp_p;
790 int i;
791
792 pr_debug("mpsc_init_rings[%d]: Initializing rings\n", pi->port.line);
793
794 BUG_ON(pi->dma_region == NULL);
795
796 memset(pi->dma_region, 0, MPSC_DMA_ALLOC_SIZE);
797
798 /*
799 * Descriptors & buffers are multiples of cacheline size and must be
800 * cacheline aligned.
801 */
2e89db75
MG		 802 dp = ALIGN((u32)pi->dma_region, dma_get_cache_alignment());
803 dp_p = ALIGN((u32)pi->dma_region_p, dma_get_cache_alignment());
1da177e4
LT		 804
805 /*
806 * Partition dma region into rx ring descriptor, rx buffers,
807 * tx ring descriptors, and tx buffers.
808 */
809 pi->rxr = dp;
810 pi->rxr_p = dp_p;
811 dp += MPSC_RXR_SIZE;
812 dp_p += MPSC_RXR_SIZE;
813
2e89db75
MG		 814 pi->rxb = (u8 *)dp;
815 pi->rxb_p = (u8 *)dp_p;
1da177e4
LT		 816 dp += MPSC_RXB_SIZE;
817 dp_p += MPSC_RXB_SIZE;
818
819 pi->rxr_posn = 0;
820
821 pi->txr = dp;
822 pi->txr_p = dp_p;
823 dp += MPSC_TXR_SIZE;
824 dp_p += MPSC_TXR_SIZE;
825
2e89db75
MG		 826 pi->txb = (u8 *)dp;
827 pi->txb_p = (u8 *)dp_p;
1da177e4
LT		 828
829 pi->txr_head = 0;
830 pi->txr_tail = 0;
831
832 /* Init rx ring descriptors */
833 dp = pi->rxr;
834 dp_p = pi->rxr_p;
835 bp = pi->rxb;
836 bp_p = pi->rxb_p;
837
838 for (i = 0; i < MPSC_RXR_ENTRIES; i++) {
839 rxre = (struct mpsc_rx_desc *)dp;
840
841 rxre->bufsize = cpu_to_be16(MPSC_RXBE_SIZE);
842 rxre->bytecnt = cpu_to_be16(0);
2e89db75
MG		 843 rxre->cmdstat = cpu_to_be32(SDMA_DESC_CMDSTAT_O
844 | SDMA_DESC_CMDSTAT_EI | SDMA_DESC_CMDSTAT_F
845 | SDMA_DESC_CMDSTAT_L);
1da177e4
LT		 846 rxre->link = cpu_to_be32(dp_p + MPSC_RXRE_SIZE);
847 rxre->buf_ptr = cpu_to_be32(bp_p);
848
849 dp += MPSC_RXRE_SIZE;
850 dp_p += MPSC_RXRE_SIZE;
851 bp += MPSC_RXBE_SIZE;
852 bp_p += MPSC_RXBE_SIZE;
853 }
854 rxre->link = cpu_to_be32(pi->rxr_p); /* Wrap last back to first */
855
856 /* Init tx ring descriptors */
857 dp = pi->txr;
858 dp_p = pi->txr_p;
859 bp = pi->txb;
860 bp_p = pi->txb_p;
861
862 for (i = 0; i < MPSC_TXR_ENTRIES; i++) {
863 txre = (struct mpsc_tx_desc *)dp;
864
865 txre->link = cpu_to_be32(dp_p + MPSC_TXRE_SIZE);
866 txre->buf_ptr = cpu_to_be32(bp_p);
867
868 dp += MPSC_TXRE_SIZE;
869 dp_p += MPSC_TXRE_SIZE;
870 bp += MPSC_TXBE_SIZE;
871 bp_p += MPSC_TXBE_SIZE;
872 }
873 txre->link = cpu_to_be32(pi->txr_p); /* Wrap last back to first */
874
2e89db75
MG		 875 dma_cache_sync(pi->port.dev, (void *)pi->dma_region,
876 MPSC_DMA_ALLOC_SIZE, DMA_BIDIRECTIONAL);
1da177e4
LT		 877#if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
878 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
879 flush_dcache_range((ulong)pi->dma_region,
2e89db75
MG		 880 (ulong)pi->dma_region
881 + MPSC_DMA_ALLOC_SIZE);
1da177e4
LT		 882#endif
883
884 return;
885}
886
2e89db75 887static void mpsc_uninit_rings(struct mpsc_port_info *pi)
1da177e4
LT		 888{
889 pr_debug("mpsc_uninit_rings[%d]: Uninitializing rings\n",pi->port.line);
890
891 BUG_ON(pi->dma_region == NULL);
892
893 pi->rxr = 0;
894 pi->rxr_p = 0;
895 pi->rxb = NULL;
896 pi->rxb_p = NULL;
897 pi->rxr_posn = 0;
898
899 pi->txr = 0;
900 pi->txr_p = 0;
901 pi->txb = NULL;
902 pi->txb_p = NULL;
903 pi->txr_head = 0;
904 pi->txr_tail = 0;
1da177e4
LT		 905}
906
2e89db75 907static int mpsc_make_ready(struct mpsc_port_info *pi)
1da177e4
LT		 908{
909 int rc;
910
911 pr_debug("mpsc_make_ready[%d]: Making cltr ready\n", pi->port.line);
912
913 if (!pi->ready) {
914 mpsc_init_hw(pi);
f2908f70
GKH		 915 rc = mpsc_alloc_ring_mem(pi);
916 if (rc)
1da177e4
LT		 917 return rc;
918 mpsc_init_rings(pi);
919 pi->ready = 1;
920 }
921
922 return 0;
923}
924
3b216c9e
JW		 925#ifdef CONFIG_CONSOLE_POLL
926static int serial_polled;
927#endif
928
1da177e4
LT		 929/*
930 ******************************************************************************
931 *
932 * Interrupt Handling Routines
933 *
934 ******************************************************************************
935 */
936
bf7f5ee3 937static int mpsc_rx_intr(struct mpsc_port_info *pi, unsigned long *flags)
1da177e4
LT		 938{
939 struct mpsc_rx_desc *rxre;
227434f8 940 struct tty_port *port = &pi->port.state->port;
1da177e4
LT		 941 u32 cmdstat, bytes_in, i;
942 int rc = 0;
943 u8 *bp;
944 char flag = TTY_NORMAL;
1da177e4
LT		 945
946 pr_debug("mpsc_rx_intr[%d]: Handling Rx intr\n", pi->port.line);
947
948 rxre = (struct mpsc_rx_desc *)(pi->rxr + (pi->rxr_posn*MPSC_RXRE_SIZE));
949
2e89db75
MG		 950 dma_cache_sync(pi->port.dev, (void *)rxre, MPSC_RXRE_SIZE,
951 DMA_FROM_DEVICE);
1da177e4
LT		 952#if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
953 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
954 invalidate_dcache_range((ulong)rxre,
2e89db75 955 (ulong)rxre + MPSC_RXRE_SIZE);
1da177e4
LT		 956#endif
957
958 /*
959 * Loop through Rx descriptors handling ones that have been completed.
960 */
2e89db75
MG		 961 while (!((cmdstat = be32_to_cpu(rxre->cmdstat))
962 & SDMA_DESC_CMDSTAT_O)) {
1da177e4 963 bytes_in = be16_to_cpu(rxre->bytecnt);
3b216c9e
JW		 964#ifdef CONFIG_CONSOLE_POLL
965 if (unlikely(serial_polled)) {
966 serial_polled = 0;
967 return 0;
968 }
969#endif
1da177e4 970 /* Following use of tty struct directly is deprecated */
227434f8 971 if (tty_buffer_request_room(port, bytes_in) < bytes_in) {
bf7f5ee3
VK		 972 if (port->low_latency) {
973 spin_unlock_irqrestore(&pi->port.lock, *flags);
2e124b4a 974 tty_flip_buffer_push(port);
bf7f5ee3
VK		 975 spin_lock_irqsave(&pi->port.lock, *flags);
976 }
1da177e4 977 /*
33f0f88f
AC		 978 * If this failed then we will throw away the bytes
979 * but must do so to clear interrupts.
1da177e4
LT		 980 */
981 }
982
983 bp = pi->rxb + (pi->rxr_posn * MPSC_RXBE_SIZE);
2e89db75
MG		 984 dma_cache_sync(pi->port.dev, (void *)bp, MPSC_RXBE_SIZE,
985 DMA_FROM_DEVICE);
1da177e4
LT		 986#if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
987 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
988 invalidate_dcache_range((ulong)bp,
2e89db75 989 (ulong)bp + MPSC_RXBE_SIZE);
1da177e4
LT		 990#endif
991
992 /*
993 * Other than for parity error, the manual provides little
994 * info on what data will be in a frame flagged by any of
995 * these errors. For parity error, it is the last byte in
996 * the buffer that had the error. As for the rest, I guess
997 * we'll assume there is no data in the buffer.
998 * If there is...it gets lost.
999 */
2e89db75
MG		 1000 if (unlikely(cmdstat & (SDMA_DESC_CMDSTAT_BR
1001 | SDMA_DESC_CMDSTAT_FR
1002 | SDMA_DESC_CMDSTAT_OR))) {
1da177e4
LT		 1003
1004 pi->port.icount.rx++;
1005
1006 if (cmdstat & SDMA_DESC_CMDSTAT_BR) { /* Break */
1007 pi->port.icount.brk++;
1008
1009 if (uart_handle_break(&pi->port))
1010 goto next_frame;
2e89db75 1011 } else if (cmdstat & SDMA_DESC_CMDSTAT_FR) {
1da177e4 1012 pi->port.icount.frame++;
2e89db75 1013 } else if (cmdstat & SDMA_DESC_CMDSTAT_OR) {
1da177e4 1014 pi->port.icount.overrun++;
2e89db75 1015 }
1da177e4
LT		 1016
1017 cmdstat &= pi->port.read_status_mask;
1018
1019 if (cmdstat & SDMA_DESC_CMDSTAT_BR)
1020 flag = TTY_BREAK;
1021 else if (cmdstat & SDMA_DESC_CMDSTAT_FR)
1022 flag = TTY_FRAME;
1023 else if (cmdstat & SDMA_DESC_CMDSTAT_OR)
1024 flag = TTY_OVERRUN;
1025 else if (cmdstat & SDMA_DESC_CMDSTAT_PE)
1026 flag = TTY_PARITY;
1027 }
1028
7d12e780 1029 if (uart_handle_sysrq_char(&pi->port, *bp)) {
1da177e4
LT		 1030 bp++;
1031 bytes_in--;
3b216c9e
JW		 1032#ifdef CONFIG_CONSOLE_POLL
1033 if (unlikely(serial_polled)) {
1034 serial_polled = 0;
1035 return 0;
1036 }
1037#endif
1da177e4
LT		 1038 goto next_frame;
1039 }
1040
2e89db75
MG		 1041 if ((unlikely(cmdstat & (SDMA_DESC_CMDSTAT_BR
1042 | SDMA_DESC_CMDSTAT_FR
1043 | SDMA_DESC_CMDSTAT_OR)))
1044 && !(cmdstat & pi->port.ignore_status_mask)) {
92a19f9c 1045 tty_insert_flip_char(port, *bp, flag);
2e89db75 1046 } else {
1da177e4 1047 for (i=0; i<bytes_in; i++)
92a19f9c 1048 tty_insert_flip_char(port, *bp++, TTY_NORMAL);
1da177e4
LT		 1049
1050 pi->port.icount.rx += bytes_in;
1051 }
1052
1053next_frame:
1054 rxre->bytecnt = cpu_to_be16(0);
1055 wmb();
2e89db75
MG		 1056 rxre->cmdstat = cpu_to_be32(SDMA_DESC_CMDSTAT_O
1057 | SDMA_DESC_CMDSTAT_EI | SDMA_DESC_CMDSTAT_F
1058 | SDMA_DESC_CMDSTAT_L);
1da177e4 1059 wmb();
2e89db75
MG		 1060 dma_cache_sync(pi->port.dev, (void *)rxre, MPSC_RXRE_SIZE,
1061 DMA_BIDIRECTIONAL);
1da177e4
LT		 1062#if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
1063 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
1064 flush_dcache_range((ulong)rxre,
2e89db75 1065 (ulong)rxre + MPSC_RXRE_SIZE);
1da177e4
LT		 1066#endif
1067
1068 /* Advance to next descriptor */
1069 pi->rxr_posn = (pi->rxr_posn + 1) & (MPSC_RXR_ENTRIES - 1);
2e89db75
MG		 1070 rxre = (struct mpsc_rx_desc *)
1071 (pi->rxr + (pi->rxr_posn * MPSC_RXRE_SIZE));
1072 dma_cache_sync(pi->port.dev, (void *)rxre, MPSC_RXRE_SIZE,
1073 DMA_FROM_DEVICE);
1da177e4
LT		 1074#if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
1075 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
1076 invalidate_dcache_range((ulong)rxre,
2e89db75 1077 (ulong)rxre + MPSC_RXRE_SIZE);
1da177e4 1078#endif
1da177e4
LT		 1079 rc = 1;
1080 }
1081
1082 /* Restart rx engine, if its stopped */
1083 if ((readl(pi->sdma_base + SDMA_SDCM) & SDMA_SDCM_ERD) == 0)
1084 mpsc_start_rx(pi);
1085
bf7f5ee3 1086 spin_unlock_irqrestore(&pi->port.lock, *flags);
2e124b4a 1087 tty_flip_buffer_push(port);
bf7f5ee3 1088 spin_lock_irqsave(&pi->port.lock, *flags);
1da177e4
LT		 1089 return rc;
1090}
1091
2e89db75 1092static void mpsc_setup_tx_desc(struct mpsc_port_info *pi, u32 count, u32 intr)
1da177e4
LT		 1093{
1094 struct mpsc_tx_desc *txre;
1095
2e89db75
MG		 1096 txre = (struct mpsc_tx_desc *)(pi->txr
1097 + (pi->txr_head * MPSC_TXRE_SIZE));
1da177e4
LT		 1098
1099 txre->bytecnt = cpu_to_be16(count);
1100 txre->shadow = txre->bytecnt;
1101 wmb(); /* ensure cmdstat is last field updated */
2e89db75
MG		 1102 txre->cmdstat = cpu_to_be32(SDMA_DESC_CMDSTAT_O | SDMA_DESC_CMDSTAT_F
1103 | SDMA_DESC_CMDSTAT_L
1104 | ((intr) ? SDMA_DESC_CMDSTAT_EI : 0));
1da177e4 1105 wmb();
2e89db75
MG		 1106 dma_cache_sync(pi->port.dev, (void *)txre, MPSC_TXRE_SIZE,
1107 DMA_BIDIRECTIONAL);
1da177e4
LT		 1108#if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
1109 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
1110 flush_dcache_range((ulong)txre,
2e89db75 1111 (ulong)txre + MPSC_TXRE_SIZE);
1da177e4 1112#endif
1da177e4
LT		 1113}
1114
2e89db75 1115static void mpsc_copy_tx_data(struct mpsc_port_info *pi)
1da177e4 1116{
ebd2c8f6 1117 struct circ_buf *xmit = &pi->port.state->xmit;
1da177e4
LT		 1118 u8 *bp;
1119 u32 i;
1120
1121 /* Make sure the desc ring isn't full */
2e89db75
MG		 1122 while (CIRC_CNT(pi->txr_head, pi->txr_tail, MPSC_TXR_ENTRIES)
1123 < (MPSC_TXR_ENTRIES - 1)) {
1da177e4
LT		 1124 if (pi->port.x_char) {
1125 /*
1126 * Ideally, we should use the TCS field in
1127 * CHR_1 to put the x_char out immediately but
1128 * errata prevents us from being able to read
1129 * CHR_2 to know that its safe to write to
1130 * CHR_1. Instead, just put it in-band with
1131 * all the other Tx data.
1132 */
1133 bp = pi->txb + (pi->txr_head * MPSC_TXBE_SIZE);
1134 *bp = pi->port.x_char;
1135 pi->port.x_char = 0;
1136 i = 1;
2e89db75
MG		 1137 } else if (!uart_circ_empty(xmit)
1138 && !uart_tx_stopped(&pi->port)) {
1139 i = min((u32)MPSC_TXBE_SIZE,
1140 (u32)uart_circ_chars_pending(xmit));
1141 i = min(i, (u32)CIRC_CNT_TO_END(xmit->head, xmit->tail,
1da177e4
LT		 1142 UART_XMIT_SIZE));
1143 bp = pi->txb + (pi->txr_head * MPSC_TXBE_SIZE);
1144 memcpy(bp, &xmit->buf[xmit->tail], i);
1145 xmit->tail = (xmit->tail + i) & (UART_XMIT_SIZE - 1);
1146
1147 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1148 uart_write_wakeup(&pi->port);
2e89db75 1149 } else { /* All tx data copied into ring bufs */
1da177e4 1150 return;
2e89db75 1151 }
1da177e4 1152
2e89db75
MG		 1153 dma_cache_sync(pi->port.dev, (void *)bp, MPSC_TXBE_SIZE,
1154 DMA_BIDIRECTIONAL);
1da177e4
LT		 1155#if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
1156 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
1157 flush_dcache_range((ulong)bp,
2e89db75 1158 (ulong)bp + MPSC_TXBE_SIZE);
1da177e4
LT		 1159#endif
1160 mpsc_setup_tx_desc(pi, i, 1);
1161
1162 /* Advance to next descriptor */
1163 pi->txr_head = (pi->txr_head + 1) & (MPSC_TXR_ENTRIES - 1);
1164 }
1da177e4
LT		 1165}
1166
2e89db75 1167static int mpsc_tx_intr(struct mpsc_port_info *pi)
1da177e4
LT		 1168{
1169 struct mpsc_tx_desc *txre;
1170 int rc = 0;
1733310b
DJ		 1171 unsigned long iflags;
1172
1173 spin_lock_irqsave(&pi->tx_lock, iflags);
1da177e4
LT		 1174
1175 if (!mpsc_sdma_tx_active(pi)) {
2e89db75
MG		 1176 txre = (struct mpsc_tx_desc *)(pi->txr
1177 + (pi->txr_tail * MPSC_TXRE_SIZE));
1da177e4 1178
2e89db75
MG		 1179 dma_cache_sync(pi->port.dev, (void *)txre, MPSC_TXRE_SIZE,
1180 DMA_FROM_DEVICE);
1da177e4
LT		 1181#if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
1182 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
1183 invalidate_dcache_range((ulong)txre,
2e89db75 1184 (ulong)txre + MPSC_TXRE_SIZE);
1da177e4
LT		 1185#endif
1186
1187 while (!(be32_to_cpu(txre->cmdstat) & SDMA_DESC_CMDSTAT_O)) {
1188 rc = 1;
1189 pi->port.icount.tx += be16_to_cpu(txre->bytecnt);
1190 pi->txr_tail = (pi->txr_tail+1) & (MPSC_TXR_ENTRIES-1);
1191
1192 /* If no more data to tx, fall out of loop */
1193 if (pi->txr_head == pi->txr_tail)
1194 break;
1195
2e89db75
MG		 1196 txre = (struct mpsc_tx_desc *)(pi->txr
1197 + (pi->txr_tail * MPSC_TXRE_SIZE));
1198 dma_cache_sync(pi->port.dev, (void *)txre,
1199 MPSC_TXRE_SIZE, DMA_FROM_DEVICE);
1da177e4
LT		 1200#if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
1201 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
1202 invalidate_dcache_range((ulong)txre,
2e89db75 1203 (ulong)txre + MPSC_TXRE_SIZE);
1da177e4
LT		 1204#endif
1205 }
1206
1207 mpsc_copy_tx_data(pi);
1208 mpsc_sdma_start_tx(pi); /* start next desc if ready */
1209 }
1210
1733310b 1211 spin_unlock_irqrestore(&pi->tx_lock, iflags);
1da177e4
LT		 1212 return rc;
1213}
1214
1215/*
1216 * This is the driver's interrupt handler. To avoid a race, we first clear
1217 * the interrupt, then handle any completed Rx/Tx descriptors. When done
1218 * handling those descriptors, we restart the Rx/Tx engines if they're stopped.
1219 */
2e89db75 1220static irqreturn_t mpsc_sdma_intr(int irq, void *dev_id)
1da177e4
LT		 1221{
1222 struct mpsc_port_info *pi = dev_id;
1223 ulong iflags;
1224 int rc = IRQ_NONE;
1225
1226 pr_debug("mpsc_sdma_intr[%d]: SDMA Interrupt Received\n",pi->port.line);
1227
1228 spin_lock_irqsave(&pi->port.lock, iflags);
1229 mpsc_sdma_intr_ack(pi);
bf7f5ee3 1230 if (mpsc_rx_intr(pi, &iflags))
1da177e4
LT		 1231 rc = IRQ_HANDLED;
1232 if (mpsc_tx_intr(pi))
1233 rc = IRQ_HANDLED;
1234 spin_unlock_irqrestore(&pi->port.lock, iflags);
1235
1236 pr_debug("mpsc_sdma_intr[%d]: SDMA Interrupt Handled\n", pi->port.line);
1237 return rc;
1238}
1239
1240/*
1241 ******************************************************************************
1242 *
1243 * serial_core.c Interface routines
1244 *
1245 ******************************************************************************
1246 */
2e89db75 1247static uint mpsc_tx_empty(struct uart_port *port)
1da177e4 1248{
22d4d44c
FF		 1249 struct mpsc_port_info *pi =
1250 container_of(port, struct mpsc_port_info, port);
1da177e4
LT		 1251 ulong iflags;
1252 uint rc;
1253
1254 spin_lock_irqsave(&pi->port.lock, iflags);
1255 rc = mpsc_sdma_tx_active(pi) ? 0 : TIOCSER_TEMT;
1256 spin_unlock_irqrestore(&pi->port.lock, iflags);
1257
1258 return rc;
1259}
1260
2e89db75 1261static void mpsc_set_mctrl(struct uart_port *port, uint mctrl)
1da177e4
LT		 1262{
1263 /* Have no way to set modem control lines AFAICT */
1da177e4
LT		 1264}
1265
2e89db75 1266static uint mpsc_get_mctrl(struct uart_port *port)
1da177e4 1267{
22d4d44c
FF		 1268 struct mpsc_port_info *pi =
1269 container_of(port, struct mpsc_port_info, port);
1da177e4 1270 u32 mflags, status;
1da177e4 1271
2e89db75
MG		 1272 status = (pi->mirror_regs) ? pi->MPSC_CHR_10_m
1273 : readl(pi->mpsc_base + MPSC_CHR_10);
1da177e4
LT		 1274
1275 mflags = 0;
1276 if (status & 0x1)
1277 mflags |= TIOCM_CTS;
1278 if (status & 0x2)
1279 mflags |= TIOCM_CAR;
1280
1281 return mflags | TIOCM_DSR; /* No way to tell if DSR asserted */
1282}
1283
2e89db75 1284static void mpsc_stop_tx(struct uart_port *port)
1da177e4 1285{
22d4d44c
FF		 1286 struct mpsc_port_info *pi =
1287 container_of(port, struct mpsc_port_info, port);
1da177e4 1288
b129a8cc 1289 pr_debug("mpsc_stop_tx[%d]\n", port->line);
1da177e4
LT		 1290
1291 mpsc_freeze(pi);
1da177e4
LT		 1292}
1293
2e89db75 1294static void mpsc_start_tx(struct uart_port *port)
1da177e4 1295{
22d4d44c
FF		 1296 struct mpsc_port_info *pi =
1297 container_of(port, struct mpsc_port_info, port);
1733310b
DJ		 1298 unsigned long iflags;
1299
1300 spin_lock_irqsave(&pi->tx_lock, iflags);
1da177e4
LT		 1301
1302 mpsc_unfreeze(pi);
1303 mpsc_copy_tx_data(pi);
1304 mpsc_sdma_start_tx(pi);
1305
1733310b
DJ		 1306 spin_unlock_irqrestore(&pi->tx_lock, iflags);
1307
b129a8cc 1308 pr_debug("mpsc_start_tx[%d]\n", port->line);
1da177e4
LT		 1309}
1310
2e89db75 1311static void mpsc_start_rx(struct mpsc_port_info *pi)
1da177e4
LT		 1312{
1313 pr_debug("mpsc_start_rx[%d]: Starting...\n", pi->port.line);
1314
1315 if (pi->rcv_data) {
1316 mpsc_enter_hunt(pi);
1317 mpsc_sdma_cmd(pi, SDMA_SDCM_ERD);
1318 }
1da177e4
LT		 1319}
1320
2e89db75 1321static void mpsc_stop_rx(struct uart_port *port)
1da177e4 1322{
22d4d44c
FF		 1323 struct mpsc_port_info *pi =
1324 container_of(port, struct mpsc_port_info, port);
1da177e4
LT		 1325
1326 pr_debug("mpsc_stop_rx[%d]: Stopping...\n", port->line);
1327
6c1ead5e
CS		 1328 if (pi->mirror_regs) {
1329 writel(pi->MPSC_CHR_2_m | MPSC_CHR_2_RA,
1330 pi->mpsc_base + MPSC_CHR_2);
1331 /* Erratum prevents reading CHR_2 so just delay for a while */
1332 udelay(100);
2e89db75 1333 } else {
6c1ead5e 1334 writel(readl(pi->mpsc_base + MPSC_CHR_2) | MPSC_CHR_2_RA,
2e89db75 1335 pi->mpsc_base + MPSC_CHR_2);
6c1ead5e
CS		 1336
1337 while (readl(pi->mpsc_base + MPSC_CHR_2) & MPSC_CHR_2_RA)
1338 udelay(10);
1339 }
1340
1da177e4 1341 mpsc_sdma_cmd(pi, SDMA_SDCM_AR);
1da177e4
LT		 1342}
1343
2e89db75 1344static void mpsc_break_ctl(struct uart_port *port, int ctl)
1da177e4 1345{
22d4d44c
FF		 1346 struct mpsc_port_info *pi =
1347 container_of(port, struct mpsc_port_info, port);
1da177e4
LT		 1348 ulong flags;
1349 u32 v;
1350
1351 v = ctl ? 0x00ff0000 : 0;
1352
1353 spin_lock_irqsave(&pi->port.lock, flags);
1354 if (pi->mirror_regs)
1355 pi->MPSC_CHR_1_m = v;
1356 writel(v, pi->mpsc_base + MPSC_CHR_1);
1357 spin_unlock_irqrestore(&pi->port.lock, flags);
1da177e4
LT		 1358}
1359
2e89db75 1360static int mpsc_startup(struct uart_port *port)
1da177e4 1361{
22d4d44c
FF		 1362 struct mpsc_port_info *pi =
1363 container_of(port, struct mpsc_port_info, port);
1da177e4
LT		 1364 u32 flag = 0;
1365 int rc;
1366
1367 pr_debug("mpsc_startup[%d]: Starting up MPSC, irq: %d\n",
1368 port->line, pi->port.irq);
1369
1370 if ((rc = mpsc_make_ready(pi)) == 0) {
1371 /* Setup IRQ handler */
1372 mpsc_sdma_intr_ack(pi);
1373
1374 /* If irq's are shared, need to set flag */
1375 if (mpsc_ports[0].port.irq == mpsc_ports[1].port.irq)
40663cc7 1376 flag = IRQF_SHARED;
1da177e4
LT		 1377
1378 if (request_irq(pi->port.irq, mpsc_sdma_intr, flag,
2e89db75 1379 "mpsc-sdma", pi))
1da177e4 1380 printk(KERN_ERR "MPSC: Can't get SDMA IRQ %d\n",
2e89db75 1381 pi->port.irq);
1da177e4
LT		 1382
1383 mpsc_sdma_intr_unmask(pi, 0xf);
2e89db75
MG		 1384 mpsc_sdma_set_rx_ring(pi, (struct mpsc_rx_desc *)(pi->rxr_p
1385 + (pi->rxr_posn * MPSC_RXRE_SIZE)));
1da177e4
LT		 1386 }
1387
1388 return rc;
1389}
1390
2e89db75 1391static void mpsc_shutdown(struct uart_port *port)
1da177e4 1392{
22d4d44c
FF		 1393 struct mpsc_port_info *pi =
1394 container_of(port, struct mpsc_port_info, port);
1da177e4
LT		 1395
1396 pr_debug("mpsc_shutdown[%d]: Shutting down MPSC\n", port->line);
1397
1398 mpsc_sdma_stop(pi);
1399 free_irq(pi->port.irq, pi);
1da177e4
LT		 1400}
1401
2e89db75 1402static void mpsc_set_termios(struct uart_port *port, struct ktermios *termios,
606d099c 1403 struct ktermios *old)
1da177e4 1404{
22d4d44c
FF		 1405 struct mpsc_port_info *pi =
1406 container_of(port, struct mpsc_port_info, port);
1da177e4
LT		 1407 u32 baud;
1408 ulong flags;
1409 u32 chr_bits, stop_bits, par;
1410
1da177e4
LT		 1411 switch (termios->c_cflag & CSIZE) {
1412 case CS5:
1413 chr_bits = MPSC_MPCR_CL_5;
1414 break;
1415 case CS6:
1416 chr_bits = MPSC_MPCR_CL_6;
1417 break;
1418 case CS7:
1419 chr_bits = MPSC_MPCR_CL_7;
1420 break;
1421 case CS8:
1422 default:
1423 chr_bits = MPSC_MPCR_CL_8;
1424 break;
1425 }
1426
1427 if (termios->c_cflag & CSTOPB)
1428 stop_bits = MPSC_MPCR_SBL_2;
1429 else
1430 stop_bits = MPSC_MPCR_SBL_1;
1431
1432 par = MPSC_CHR_2_PAR_EVEN;
1433 if (termios->c_cflag & PARENB)
1434 if (termios->c_cflag & PARODD)
1435 par = MPSC_CHR_2_PAR_ODD;
1436#ifdef CMSPAR
1437 if (termios->c_cflag & CMSPAR) {
1438 if (termios->c_cflag & PARODD)
1439 par = MPSC_CHR_2_PAR_MARK;
1440 else
1441 par = MPSC_CHR_2_PAR_SPACE;
1442 }
1443#endif
1444
1445 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk);
1446
1447 spin_lock_irqsave(&pi->port.lock, flags);
1448
1449 uart_update_timeout(port, termios->c_cflag, baud);
1450
1451 mpsc_set_char_length(pi, chr_bits);
1452 mpsc_set_stop_bit_length(pi, stop_bits);
1453 mpsc_set_parity(pi, par);
1454 mpsc_set_baudrate(pi, baud);
1455
1456 /* Characters/events to read */
1da177e4
LT		 1457 pi->port.read_status_mask = SDMA_DESC_CMDSTAT_OR;
1458
1459 if (termios->c_iflag & INPCK)
2e89db75
MG		 1460 pi->port.read_status_mask |= SDMA_DESC_CMDSTAT_PE
1461 | SDMA_DESC_CMDSTAT_FR;
1da177e4 1462
ef8b9ddc 1463 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
1da177e4
LT		 1464 pi->port.read_status_mask |= SDMA_DESC_CMDSTAT_BR;
1465
1466 /* Characters/events to ignore */
1467 pi->port.ignore_status_mask = 0;
1468
1469 if (termios->c_iflag & IGNPAR)
2e89db75
MG		 1470 pi->port.ignore_status_mask |= SDMA_DESC_CMDSTAT_PE
1471 | SDMA_DESC_CMDSTAT_FR;
1da177e4
LT		 1472
1473 if (termios->c_iflag & IGNBRK) {
1474 pi->port.ignore_status_mask |= SDMA_DESC_CMDSTAT_BR;
1475
1476 if (termios->c_iflag & IGNPAR)
1477 pi->port.ignore_status_mask |= SDMA_DESC_CMDSTAT_OR;
1478 }
1479
5797ae36
SC		 1480 if ((termios->c_cflag & CREAD)) {
1481 if (!pi->rcv_data) {
1482 pi->rcv_data = 1;
1483 mpsc_start_rx(pi);
1484 }
1485 } else if (pi->rcv_data) {
1486 mpsc_stop_rx(port);
1da177e4 1487 pi->rcv_data = 0;
5797ae36 1488 }
1da177e4
LT		 1489
1490 spin_unlock_irqrestore(&pi->port.lock, flags);
1da177e4
LT		 1491}
1492
2e89db75 1493static const char *mpsc_type(struct uart_port *port)
1da177e4
LT		 1494{
1495 pr_debug("mpsc_type[%d]: port type: %s\n", port->line,MPSC_DRIVER_NAME);
1496 return MPSC_DRIVER_NAME;
1497}
1498
2e89db75 1499static int mpsc_request_port(struct uart_port *port)
1da177e4
LT		 1500{
1501 /* Should make chip/platform specific call */
1502 return 0;
1503}
1504
2e89db75 1505static void mpsc_release_port(struct uart_port *port)
1da177e4 1506{
22d4d44c
FF		 1507 struct mpsc_port_info *pi =
1508 container_of(port, struct mpsc_port_info, port);
1da177e4
LT		 1509
1510 if (pi->ready) {
1511 mpsc_uninit_rings(pi);
1512 mpsc_free_ring_mem(pi);
1513 pi->ready = 0;
1514 }
1da177e4
LT		 1515}
1516
2e89db75 1517static void mpsc_config_port(struct uart_port *port, int flags)
1da177e4 1518{
1da177e4
LT		 1519}
1520
2e89db75 1521static int mpsc_verify_port(struct uart_port *port, struct serial_struct *ser)
1da177e4 1522{
22d4d44c
FF		 1523 struct mpsc_port_info *pi =
1524 container_of(port, struct mpsc_port_info, port);
1da177e4
LT		 1525 int rc = 0;
1526
1527 pr_debug("mpsc_verify_port[%d]: Verifying port data\n", pi->port.line);
1528
1529 if (ser->type != PORT_UNKNOWN && ser->type != PORT_MPSC)
1530 rc = -EINVAL;
1531 else if (pi->port.irq != ser->irq)
1532 rc = -EINVAL;
1533 else if (ser->io_type != SERIAL_IO_MEM)
1534 rc = -EINVAL;
1535 else if (pi->port.uartclk / 16 != ser->baud_base) /* Not sure */
1536 rc = -EINVAL;
1537 else if ((void *)pi->port.mapbase != ser->iomem_base)
1538 rc = -EINVAL;
1539 else if (pi->port.iobase != ser->port)
1540 rc = -EINVAL;
1541 else if (ser->hub6 != 0)
1542 rc = -EINVAL;
1543
1544 return rc;
1545}
3b216c9e
JW		 1546#ifdef CONFIG_CONSOLE_POLL
1547/* Serial polling routines for writing and reading from the uart while
1548 * in an interrupt or debug context.
1549 */
1550
1551static char poll_buf[2048];
1552static int poll_ptr;
1553static int poll_cnt;
1554static void mpsc_put_poll_char(struct uart_port *port,
1555 unsigned char c);
1556
1557static int mpsc_get_poll_char(struct uart_port *port)
1558{
22d4d44c
FF		 1559 struct mpsc_port_info *pi =
1560 container_of(port, struct mpsc_port_info, port);
3b216c9e
JW		 1561 struct mpsc_rx_desc *rxre;
1562 u32 cmdstat, bytes_in, i;
1563 u8 *bp;
1564
1565 if (!serial_polled)
1566 serial_polled = 1;
1567
1568 pr_debug("mpsc_rx_intr[%d]: Handling Rx intr\n", pi->port.line);
1569
1570 if (poll_cnt) {
1571 poll_cnt--;
1572 return poll_buf[poll_ptr++];
1573 }
1574 poll_ptr = 0;
1575 poll_cnt = 0;
1576
1577 while (poll_cnt == 0) {
1578 rxre = (struct mpsc_rx_desc *)(pi->rxr +
1579 (pi->rxr_posn*MPSC_RXRE_SIZE));
1580 dma_cache_sync(pi->port.dev, (void *)rxre,
1581 MPSC_RXRE_SIZE, DMA_FROM_DEVICE);
1582#if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
1583 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
1584 invalidate_dcache_range((ulong)rxre,
1585 (ulong)rxre + MPSC_RXRE_SIZE);
1586#endif
1587 /*
1588 * Loop through Rx descriptors handling ones that have
1589 * been completed.
1590 */
1591 while (poll_cnt == 0 &&
1592 !((cmdstat = be32_to_cpu(rxre->cmdstat)) &
1593 SDMA_DESC_CMDSTAT_O)){
1594 bytes_in = be16_to_cpu(rxre->bytecnt);
1595 bp = pi->rxb + (pi->rxr_posn * MPSC_RXBE_SIZE);
1596 dma_cache_sync(pi->port.dev, (void *) bp,
1597 MPSC_RXBE_SIZE, DMA_FROM_DEVICE);
1598#if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
1599 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
1600 invalidate_dcache_range((ulong)bp,
1601 (ulong)bp + MPSC_RXBE_SIZE);
1602#endif
1603 if ((unlikely(cmdstat & (SDMA_DESC_CMDSTAT_BR |
1604 SDMA_DESC_CMDSTAT_FR | SDMA_DESC_CMDSTAT_OR))) &&
1605 !(cmdstat & pi->port.ignore_status_mask)) {
1606 poll_buf[poll_cnt] = *bp;
1607 poll_cnt++;
1608 } else {
1609 for (i = 0; i < bytes_in; i++) {
1610 poll_buf[poll_cnt] = *bp++;
1611 poll_cnt++;
1612 }
1613 pi->port.icount.rx += bytes_in;
1614 }
1615 rxre->bytecnt = cpu_to_be16(0);
1616 wmb();
1617 rxre->cmdstat = cpu_to_be32(SDMA_DESC_CMDSTAT_O |
1618 SDMA_DESC_CMDSTAT_EI |
1619 SDMA_DESC_CMDSTAT_F |
1620 SDMA_DESC_CMDSTAT_L);
1621 wmb();
1622 dma_cache_sync(pi->port.dev, (void *)rxre,
1623 MPSC_RXRE_SIZE, DMA_BIDIRECTIONAL);
1624#if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
1625 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
1626 flush_dcache_range((ulong)rxre,
1627 (ulong)rxre + MPSC_RXRE_SIZE);
1628#endif
1629
1630 /* Advance to next descriptor */
1631 pi->rxr_posn = (pi->rxr_posn + 1) &
1632 (MPSC_RXR_ENTRIES - 1);
1633 rxre = (struct mpsc_rx_desc *)(pi->rxr +
1634 (pi->rxr_posn * MPSC_RXRE_SIZE));
1635 dma_cache_sync(pi->port.dev, (void *)rxre,
1636 MPSC_RXRE_SIZE, DMA_FROM_DEVICE);
1637#if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
1638 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
1639 invalidate_dcache_range((ulong)rxre,
1640 (ulong)rxre + MPSC_RXRE_SIZE);
1641#endif
1642 }
1643
1644 /* Restart rx engine, if its stopped */
1645 if ((readl(pi->sdma_base + SDMA_SDCM) & SDMA_SDCM_ERD) == 0)
1646 mpsc_start_rx(pi);
1647 }
1648 if (poll_cnt) {
1649 poll_cnt--;
1650 return poll_buf[poll_ptr++];
1651 }
1652
1653 return 0;
1654}
1655
1656
1657static void mpsc_put_poll_char(struct uart_port *port,
1658 unsigned char c)
1659{
22d4d44c
FF		 1660 struct mpsc_port_info *pi =
1661 container_of(port, struct mpsc_port_info, port);
3b216c9e
JW		 1662 u32 data;
1663
1664 data = readl(pi->mpsc_base + MPSC_MPCR);
1665 writeb(c, pi->mpsc_base + MPSC_CHR_1);
1666 mb();
1667 data = readl(pi->mpsc_base + MPSC_CHR_2);
1668 data |= MPSC_CHR_2_TTCS;
1669 writel(data, pi->mpsc_base + MPSC_CHR_2);
1670 mb();
1671
1672 while (readl(pi->mpsc_base + MPSC_CHR_2) & MPSC_CHR_2_TTCS);
1673}
1674#endif
1da177e4 1675
2331e068 1676static const struct uart_ops mpsc_pops = {
2e89db75
MG		 1677 .tx_empty = mpsc_tx_empty,
1678 .set_mctrl = mpsc_set_mctrl,
1679 .get_mctrl = mpsc_get_mctrl,
1680 .stop_tx = mpsc_stop_tx,
1681 .start_tx = mpsc_start_tx,
1682 .stop_rx = mpsc_stop_rx,
2e89db75
MG		 1683 .break_ctl = mpsc_break_ctl,
1684 .startup = mpsc_startup,
1685 .shutdown = mpsc_shutdown,
1686 .set_termios = mpsc_set_termios,
1687 .type = mpsc_type,
1688 .release_port = mpsc_release_port,
1689 .request_port = mpsc_request_port,
1690 .config_port = mpsc_config_port,
1691 .verify_port = mpsc_verify_port,
3b216c9e
JW		 1692#ifdef CONFIG_CONSOLE_POLL
1693 .poll_get_char = mpsc_get_poll_char,
1694 .poll_put_char = mpsc_put_poll_char,
1695#endif
1da177e4
LT		 1696};
1697
1698/*
1699 ******************************************************************************
1700 *
1701 * Console Interface Routines
1702 *
1703 ******************************************************************************
1704 */
1705
1706#ifdef CONFIG_SERIAL_MPSC_CONSOLE
2e89db75 1707static void mpsc_console_write(struct console *co, const char *s, uint count)
1da177e4
LT		 1708{
1709 struct mpsc_port_info *pi = &mpsc_ports[co->index];
1710 u8 *bp, *dp, add_cr = 0;
1711 int i;
1733310b
DJ		 1712 unsigned long iflags;
1713
1714 spin_lock_irqsave(&pi->tx_lock, iflags);
1715
1716 while (pi->txr_head != pi->txr_tail) {
1717 while (mpsc_sdma_tx_active(pi))
1718 udelay(100);
1719 mpsc_sdma_intr_ack(pi);
1720 mpsc_tx_intr(pi);
1721 }
1da177e4
LT		 1722
1723 while (mpsc_sdma_tx_active(pi))
1724 udelay(100);
1725
1726 while (count > 0) {
1727 bp = dp = pi->txb + (pi->txr_head * MPSC_TXBE_SIZE);
1728
1729 for (i = 0; i < MPSC_TXBE_SIZE; i++) {
1730 if (count == 0)
1731 break;
1732
1733 if (add_cr) {
1734 *(dp++) = '\r';
1735 add_cr = 0;
2e89db75 1736 } else {
1da177e4
LT		 1737 *(dp++) = *s;
1738
1739 if (*(s++) == '\n') { /* add '\r' after '\n' */
1740 add_cr = 1;
1741 count++;
1742 }
1743 }
1744
1745 count--;
1746 }
1747
2e89db75
MG		 1748 dma_cache_sync(pi->port.dev, (void *)bp, MPSC_TXBE_SIZE,
1749 DMA_BIDIRECTIONAL);
1da177e4
LT		 1750#if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
1751 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
1752 flush_dcache_range((ulong)bp,
2e89db75 1753 (ulong)bp + MPSC_TXBE_SIZE);
1da177e4
LT		 1754#endif
1755 mpsc_setup_tx_desc(pi, i, 0);
1756 pi->txr_head = (pi->txr_head + 1) & (MPSC_TXR_ENTRIES - 1);
1757 mpsc_sdma_start_tx(pi);
1758
1759 while (mpsc_sdma_tx_active(pi))
1760 udelay(100);
1761
1762 pi->txr_tail = (pi->txr_tail + 1) & (MPSC_TXR_ENTRIES - 1);
1763 }
1764
1733310b 1765 spin_unlock_irqrestore(&pi->tx_lock, iflags);
1da177e4
LT		 1766}
1767
2e89db75 1768static int __init mpsc_console_setup(struct console *co, char *options)
1da177e4
LT		 1769{
1770 struct mpsc_port_info *pi;
1771 int baud, bits, parity, flow;
1772
1773 pr_debug("mpsc_console_setup[%d]: options: %s\n", co->index, options);
1774
1775 if (co->index >= MPSC_NUM_CTLRS)
1776 co->index = 0;
1777
1778 pi = &mpsc_ports[co->index];
1779
1780 baud = pi->default_baud;
1781 bits = pi->default_bits;
1782 parity = pi->default_parity;
1783 flow = pi->default_flow;
1784
1785 if (!pi->port.ops)
1786 return -ENODEV;
1787
1788 spin_lock_init(&pi->port.lock); /* Temporary fix--copied from 8250.c */
1789
1790 if (options)
1791 uart_parse_options(options, &baud, &parity, &bits, &flow);
1792
1793 return uart_set_options(&pi->port, co, baud, parity, bits, flow);
1794}
1795
1da177e4 1796static struct console mpsc_console = {
2e89db75
MG		 1797 .name = MPSC_DEV_NAME,
1798 .write = mpsc_console_write,
1799 .device = uart_console_device,
1800 .setup = mpsc_console_setup,
1801 .flags = CON_PRINTBUFFER,
1802 .index = -1,
1803 .data = &mpsc_reg,
1da177e4
LT		 1804};
1805
2e89db75 1806static int __init mpsc_late_console_init(void)
1da177e4
LT		 1807{
1808 pr_debug("mpsc_late_console_init: Enter\n");
1809
1810 if (!(mpsc_console.flags & CON_ENABLED))
1811 register_console(&mpsc_console);
1812 return 0;
1813}
1814
1815late_initcall(mpsc_late_console_init);
1816
1817#define MPSC_CONSOLE &mpsc_console
1818#else
1819#define MPSC_CONSOLE NULL
1820#endif
1821/*
1822 ******************************************************************************
1823 *
1824 * Dummy Platform Driver to extract & map shared register regions
1825 *
1826 ******************************************************************************
1827 */
2e89db75 1828static void mpsc_resource_err(char *s)
1da177e4
LT		 1829{
1830 printk(KERN_WARNING "MPSC: Platform device resource error in %s\n", s);
1da177e4
LT		 1831}
1832
2e89db75 1833static int mpsc_shared_map_regs(struct platform_device *pd)
1da177e4
LT		 1834{
1835 struct resource *r;
1836
1837 if ((r = platform_get_resource(pd, IORESOURCE_MEM,
2e89db75
MG		 1838 MPSC_ROUTING_BASE_ORDER))
1839 && request_mem_region(r->start,
1840 MPSC_ROUTING_REG_BLOCK_SIZE,
1841 "mpsc_routing_regs")) {
1da177e4 1842 mpsc_shared_regs.mpsc_routing_base = ioremap(r->start,
2e89db75 1843 MPSC_ROUTING_REG_BLOCK_SIZE);
1da177e4 1844 mpsc_shared_regs.mpsc_routing_base_p = r->start;
2e89db75 1845 } else {
1da177e4
LT		 1846 mpsc_resource_err("MPSC routing base");
1847 return -ENOMEM;
1848 }
1849
1850 if ((r = platform_get_resource(pd, IORESOURCE_MEM,
2e89db75
MG		 1851 MPSC_SDMA_INTR_BASE_ORDER))
1852 && request_mem_region(r->start,
1853 MPSC_SDMA_INTR_REG_BLOCK_SIZE,
1854 "sdma_intr_regs")) {
1da177e4
LT		 1855 mpsc_shared_regs.sdma_intr_base = ioremap(r->start,
1856 MPSC_SDMA_INTR_REG_BLOCK_SIZE);
1857 mpsc_shared_regs.sdma_intr_base_p = r->start;
2e89db75 1858 } else {
1da177e4
LT		 1859 iounmap(mpsc_shared_regs.mpsc_routing_base);
1860 release_mem_region(mpsc_shared_regs.mpsc_routing_base_p,
2e89db75 1861 MPSC_ROUTING_REG_BLOCK_SIZE);
1da177e4
LT		 1862 mpsc_resource_err("SDMA intr base");
1863 return -ENOMEM;
1864 }
1865
1866 return 0;
1867}
1868
2e89db75 1869static void mpsc_shared_unmap_regs(void)
1da177e4 1870{
1fba6a59 1871 if (mpsc_shared_regs.mpsc_routing_base) {
1da177e4
LT		 1872 iounmap(mpsc_shared_regs.mpsc_routing_base);
1873 release_mem_region(mpsc_shared_regs.mpsc_routing_base_p,
2e89db75 1874 MPSC_ROUTING_REG_BLOCK_SIZE);
1da177e4 1875 }
1fba6a59 1876 if (mpsc_shared_regs.sdma_intr_base) {
1da177e4
LT		 1877 iounmap(mpsc_shared_regs.sdma_intr_base);
1878 release_mem_region(mpsc_shared_regs.sdma_intr_base_p,
2e89db75 1879 MPSC_SDMA_INTR_REG_BLOCK_SIZE);
1da177e4
LT		 1880 }
1881
2c6e7599
AV		 1882 mpsc_shared_regs.mpsc_routing_base = NULL;
1883 mpsc_shared_regs.sdma_intr_base = NULL;
1da177e4
LT		 1884
1885 mpsc_shared_regs.mpsc_routing_base_p = 0;
1886 mpsc_shared_regs.sdma_intr_base_p = 0;
1da177e4
LT		 1887}
1888
2e89db75 1889static int mpsc_shared_drv_probe(struct platform_device *dev)
1da177e4 1890{
1da177e4 1891 struct mpsc_shared_pdata *pdata;
bca1481e 1892 int rc;
1da177e4 1893
bca1481e
JS		 1894 if (dev->id != 0)
1895 return -ENODEV;
1896
1897 rc = mpsc_shared_map_regs(dev);
1898 if (rc)
1899 return rc;
1900
1901 pdata = dev_get_platdata(&dev->dev);
1902
1903 mpsc_shared_regs.MPSC_MRR_m = pdata->mrr_val;
1904 mpsc_shared_regs.MPSC_RCRR_m= pdata->rcrr_val;
1905 mpsc_shared_regs.MPSC_TCRR_m= pdata->tcrr_val;
1906 mpsc_shared_regs.SDMA_INTR_CAUSE_m = pdata->intr_cause_val;
1907 mpsc_shared_regs.SDMA_INTR_MASK_m = pdata->intr_mask_val;
1908
1909 return 0;
1da177e4
LT		 1910}
1911
2e89db75 1912static int mpsc_shared_drv_remove(struct platform_device *dev)
1da177e4 1913{
bca1481e
JS		 1914 if (dev->id != 0)
1915 return -ENODEV;
1da177e4 1916
bca1481e
JS		 1917 mpsc_shared_unmap_regs();
1918 mpsc_shared_regs.MPSC_MRR_m = 0;
1919 mpsc_shared_regs.MPSC_RCRR_m = 0;
1920 mpsc_shared_regs.MPSC_TCRR_m = 0;
1921 mpsc_shared_regs.SDMA_INTR_CAUSE_m = 0;
1922 mpsc_shared_regs.SDMA_INTR_MASK_m = 0;
1da177e4 1923
bca1481e 1924 return 0;
1da177e4
LT		 1925}
1926
3ae5eaec 1927static struct platform_driver mpsc_shared_driver = {
1da177e4
LT		 1928 .probe = mpsc_shared_drv_probe,
1929 .remove = mpsc_shared_drv_remove,
3ae5eaec 1930 .driver = {
2e89db75 1931 .name = MPSC_SHARED_NAME,
3ae5eaec 1932 },
1da177e4
LT		 1933};
1934
1935/*
1936 ******************************************************************************
1937 *
1938 * Driver Interface Routines
1939 *
1940 ******************************************************************************
1941 */
1942static struct uart_driver mpsc_reg = {
2e89db75
MG		 1943 .owner = THIS_MODULE,
1944 .driver_name = MPSC_DRIVER_NAME,
1945 .dev_name = MPSC_DEV_NAME,
1946 .major = MPSC_MAJOR,
1947 .minor = MPSC_MINOR_START,
1948 .nr = MPSC_NUM_CTLRS,
1949 .cons = MPSC_CONSOLE,
1da177e4
LT		 1950};
1951
2e89db75
MG		 1952static int mpsc_drv_map_regs(struct mpsc_port_info *pi,
1953 struct platform_device *pd)
1da177e4
LT		 1954{
1955 struct resource *r;
1956
2e89db75
MG		 1957 if ((r = platform_get_resource(pd, IORESOURCE_MEM, MPSC_BASE_ORDER))
1958 && request_mem_region(r->start, MPSC_REG_BLOCK_SIZE,
1959 "mpsc_regs")) {
1da177e4
LT		 1960 pi->mpsc_base = ioremap(r->start, MPSC_REG_BLOCK_SIZE);
1961 pi->mpsc_base_p = r->start;
2e89db75 1962 } else {
1da177e4 1963 mpsc_resource_err("MPSC base");
2e89db75 1964 goto err;
1da177e4
LT		 1965 }
1966
1967 if ((r = platform_get_resource(pd, IORESOURCE_MEM,
2e89db75
MG		 1968 MPSC_SDMA_BASE_ORDER))
1969 && request_mem_region(r->start,
1970 MPSC_SDMA_REG_BLOCK_SIZE, "sdma_regs")) {
1da177e4
LT		 1971 pi->sdma_base = ioremap(r->start,MPSC_SDMA_REG_BLOCK_SIZE);
1972 pi->sdma_base_p = r->start;
2e89db75 1973 } else {
1da177e4 1974 mpsc_resource_err("SDMA base");
2e89db75 1975 goto err;
1da177e4
LT		 1976 }
1977
1978 if ((r = platform_get_resource(pd,IORESOURCE_MEM,MPSC_BRG_BASE_ORDER))
2e89db75
MG		 1979 && request_mem_region(r->start,
1980 MPSC_BRG_REG_BLOCK_SIZE, "brg_regs")) {
1da177e4
LT		 1981 pi->brg_base = ioremap(r->start, MPSC_BRG_REG_BLOCK_SIZE);
1982 pi->brg_base_p = r->start;
2e89db75 1983 } else {
1da177e4 1984 mpsc_resource_err("BRG base");
2e89db75 1985 goto err;
1da177e4 1986 }
1da177e4 1987 return 0;
2e89db75
MG		 1988
1989err:
bca1481e
JS		 1990 if (pi->sdma_base) {
1991 iounmap(pi->sdma_base);
1992 pi->sdma_base = NULL;
1993 }
1994 if (pi->mpsc_base) {
1995 iounmap(pi->mpsc_base);
1996 pi->mpsc_base = NULL;
1997 }
2e89db75 1998 return -ENOMEM;
1da177e4
LT		 1999}
2000
2e89db75 2001static void mpsc_drv_unmap_regs(struct mpsc_port_info *pi)
1da177e4 2002{
1fba6a59 2003 if (pi->mpsc_base) {
1da177e4
LT		 2004 iounmap(pi->mpsc_base);
2005 release_mem_region(pi->mpsc_base_p, MPSC_REG_BLOCK_SIZE);
2006 }
1fba6a59 2007 if (pi->sdma_base) {
1da177e4
LT		 2008 iounmap(pi->sdma_base);
2009 release_mem_region(pi->sdma_base_p, MPSC_SDMA_REG_BLOCK_SIZE);
2010 }
1fba6a59 2011 if (pi->brg_base) {
1da177e4
LT		 2012 iounmap(pi->brg_base);
2013 release_mem_region(pi->brg_base_p, MPSC_BRG_REG_BLOCK_SIZE);
2014 }
2015
2c6e7599
AV		 2016 pi->mpsc_base = NULL;
2017 pi->sdma_base = NULL;
2018 pi->brg_base = NULL;
1da177e4
LT		 2019
2020 pi->mpsc_base_p = 0;
2021 pi->sdma_base_p = 0;
2022 pi->brg_base_p = 0;
1da177e4
LT		 2023}
2024
2e89db75
MG		 2025static void mpsc_drv_get_platform_data(struct mpsc_port_info *pi,
2026 struct platform_device *pd, int num)
1da177e4
LT		 2027{
2028 struct mpsc_pdata *pdata;
2029
5c02fab6 2030 pdata = dev_get_platdata(&pd->dev);
1da177e4
LT		 2031
2032 pi->port.uartclk = pdata->brg_clk_freq;
2033 pi->port.iotype = UPIO_MEM;
2034 pi->port.line = num;
2035 pi->port.type = PORT_MPSC;
2036 pi->port.fifosize = MPSC_TXBE_SIZE;
2037 pi->port.membase = pi->mpsc_base;
2038 pi->port.mapbase = (ulong)pi->mpsc_base;
2039 pi->port.ops = &mpsc_pops;
2040
2041 pi->mirror_regs = pdata->mirror_regs;
2042 pi->cache_mgmt = pdata->cache_mgmt;
2043 pi->brg_can_tune = pdata->brg_can_tune;
2044 pi->brg_clk_src = pdata->brg_clk_src;
2045 pi->mpsc_max_idle = pdata->max_idle;
2046 pi->default_baud = pdata->default_baud;
2047 pi->default_bits = pdata->default_bits;
2048 pi->default_parity = pdata->default_parity;
2049 pi->default_flow = pdata->default_flow;
2050
2051 /* Initial values of mirrored regs */
2052 pi->MPSC_CHR_1_m = pdata->chr_1_val;
2053 pi->MPSC_CHR_2_m = pdata->chr_2_val;
2054 pi->MPSC_CHR_10_m = pdata->chr_10_val;
2055 pi->MPSC_MPCR_m = pdata->mpcr_val;
2056 pi->BRG_BCR_m = pdata->bcr_val;
2057
2058 pi->shared_regs = &mpsc_shared_regs;
2059
2060 pi->port.irq = platform_get_irq(pd, 0);
1da177e4
LT		 2061}
2062
2e89db75 2063static int mpsc_drv_probe(struct platform_device *dev)
1da177e4 2064{
bca1481e
JS		 2065 struct mpsc_port_info *pi;
2066 int rc;
2067
2068 dev_dbg(&dev->dev, "mpsc_drv_probe: Adding MPSC %d\n", dev->id);
2069
2070 if (dev->id >= MPSC_NUM_CTLRS)
2071 return -ENODEV;
2072
2073 pi = &mpsc_ports[dev->id];
2074
2075 rc = mpsc_drv_map_regs(pi, dev);
2076 if (rc)
2077 return rc;
1da177e4 2078
bca1481e
JS		 2079 mpsc_drv_get_platform_data(pi, dev, dev->id);
2080 pi->port.dev = &dev->dev;
2081
2082 rc = mpsc_make_ready(pi);
2083 if (rc)
2084 goto err_unmap;
2085
2086 spin_lock_init(&pi->tx_lock);
2087 rc = uart_add_one_port(&mpsc_reg, &pi->port);
2088 if (rc)
2089 goto err_relport;
2090
2091 return 0;
2092err_relport:
2093 mpsc_release_port(&pi->port);
2094err_unmap:
2095 mpsc_drv_unmap_regs(pi);
1da177e4
LT		 2096 return rc;
2097}
2098
3ae5eaec 2099static struct platform_driver mpsc_driver = {
1da177e4 2100 .probe = mpsc_drv_probe,
3ae5eaec 2101 .driver = {
6200cbaf
PG		 2102 .name = MPSC_CTLR_NAME,
2103 .suppress_bind_attrs = true,
3ae5eaec 2104 },
1da177e4
LT		 2105};
2106
2e89db75 2107static int __init mpsc_drv_init(void)
1da177e4
LT		 2108{
2109 int rc;
2110
d87a6d95 2111 printk(KERN_INFO "Serial: MPSC driver\n");
1da177e4
LT		 2112
2113 memset(mpsc_ports, 0, sizeof(mpsc_ports));
2114 memset(&mpsc_shared_regs, 0, sizeof(mpsc_shared_regs));
2115
f2908f70 2116 rc = uart_register_driver(&mpsc_reg);
bca1481e
JS		 2117 if (rc)
2118 return rc;
2119
2120 rc = platform_driver_register(&mpsc_shared_driver);
2121 if (rc)
2122 goto err_unreg_uart;
1da177e4 2123
bca1481e
JS		 2124 rc = platform_driver_register(&mpsc_driver);
2125 if (rc)
2126 goto err_unreg_plat;
2127
2128 return 0;
2129err_unreg_plat:
2130 platform_driver_unregister(&mpsc_shared_driver);
2131err_unreg_uart:
2132 uart_unregister_driver(&mpsc_reg);
1da177e4 2133 return rc;
1da177e4 2134}
128a3d06 2135device_initcall(mpsc_drv_init);
1da177e4 2136
128a3d06 2137/*
1da177e4 2138MODULE_AUTHOR("Mark A. Greer <mgreer@mvista.com>");
d87a6d95 2139MODULE_DESCRIPTION("Generic Marvell MPSC serial/UART driver");
1da177e4 2140MODULE_LICENSE("GPL");
128a3d06 2141*/
Linux 6.x block layer and io_uring tree(s)