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tty: add SPDX identifiers to all remaining files in drivers/tty/
[linux-2.6-block.git] / drivers / tty / serial / meson_uart.c
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e3b3d0f5 1// SPDX-License-Identifier: GPL-2.0
ff7693d0
CC		 2/*
3 * Based on meson_uart.c, by AMLOGIC, INC.
4 *
5 * Copyright (C) 2014 Carlo Caione <carlo@caione.org>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published
9 * by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 */
17
b86ac225
YL		 18#if defined(CONFIG_SERIAL_MESON_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
19#define SUPPORT_SYSRQ
20#endif
21
ff7693d0
CC		 22#include <linux/clk.h>
23#include <linux/console.h>
24#include <linux/delay.h>
25#include <linux/init.h>
26#include <linux/io.h>
27#include <linux/module.h>
28#include <linux/kernel.h>
29#include <linux/of.h>
30#include <linux/platform_device.h>
31#include <linux/serial.h>
32#include <linux/serial_core.h>
33#include <linux/tty.h>
34#include <linux/tty_flip.h>
35
36/* Register offsets */
37#define AML_UART_WFIFO 0x00
38#define AML_UART_RFIFO 0x04
39#define AML_UART_CONTROL 0x08
40#define AML_UART_STATUS 0x0c
41#define AML_UART_MISC 0x10
42#define AML_UART_REG5 0x14
43
44/* AML_UART_CONTROL bits */
45#define AML_UART_TX_EN BIT(12)
46#define AML_UART_RX_EN BIT(13)
47#define AML_UART_TX_RST BIT(22)
48#define AML_UART_RX_RST BIT(23)
49#define AML_UART_CLR_ERR BIT(24)
50#define AML_UART_RX_INT_EN BIT(27)
51#define AML_UART_TX_INT_EN BIT(28)
52#define AML_UART_DATA_LEN_MASK (0x03 << 20)
53#define AML_UART_DATA_LEN_8BIT (0x00 << 20)
54#define AML_UART_DATA_LEN_7BIT (0x01 << 20)
55#define AML_UART_DATA_LEN_6BIT (0x02 << 20)
56#define AML_UART_DATA_LEN_5BIT (0x03 << 20)
57
58/* AML_UART_STATUS bits */
59#define AML_UART_PARITY_ERR BIT(16)
60#define AML_UART_FRAME_ERR BIT(17)
61#define AML_UART_TX_FIFO_WERR BIT(18)
62#define AML_UART_RX_EMPTY BIT(20)
63#define AML_UART_TX_FULL BIT(21)
64#define AML_UART_TX_EMPTY BIT(22)
88679739 65#define AML_UART_XMIT_BUSY BIT(25)
ff7693d0
CC		 66#define AML_UART_ERR (AML_UART_PARITY_ERR | \
67 AML_UART_FRAME_ERR | \
68 AML_UART_TX_FIFO_WERR)
69
70/* AML_UART_CONTROL bits */
71#define AML_UART_TWO_WIRE_EN BIT(15)
72#define AML_UART_PARITY_TYPE BIT(18)
73#define AML_UART_PARITY_EN BIT(19)
74#define AML_UART_CLEAR_ERR BIT(24)
75#define AML_UART_STOP_BIN_LEN_MASK (0x03 << 16)
76#define AML_UART_STOP_BIN_1SB (0x00 << 16)
77#define AML_UART_STOP_BIN_2SB (0x01 << 16)
78
79/* AML_UART_MISC bits */
80#define AML_UART_XMIT_IRQ(c) (((c) & 0xff) << 8)
81#define AML_UART_RECV_IRQ(c) ((c) & 0xff)
82
83/* AML_UART_REG5 bits */
84#define AML_UART_BAUD_MASK 0x7fffff
85#define AML_UART_BAUD_USE BIT(23)
146f3808 86#define AML_UART_BAUD_XTAL BIT(24)
ff7693d0
CC		 87
88#define AML_UART_PORT_NUM 6
89#define AML_UART_DEV_NAME "ttyAML"
90
91
92static struct uart_driver meson_uart_driver;
93
94static struct uart_port *meson_ports[AML_UART_PORT_NUM];
95
96static void meson_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
97{
98}
99
100static unsigned int meson_uart_get_mctrl(struct uart_port *port)
101{
102 return TIOCM_CTS;
103}
104
105static unsigned int meson_uart_tx_empty(struct uart_port *port)
106{
107 u32 val;
108
109 val = readl(port->membase + AML_UART_STATUS);
88679739
BD		 110 val &= (AML_UART_TX_EMPTY | AML_UART_XMIT_BUSY);
111 return (val == AML_UART_TX_EMPTY) ? TIOCSER_TEMT : 0;
ff7693d0
CC		 112}
113
114static void meson_uart_stop_tx(struct uart_port *port)
115{
116 u32 val;
117
118 val = readl(port->membase + AML_UART_CONTROL);
855ddcab 119 val &= ~AML_UART_TX_INT_EN;
ff7693d0
CC		 120 writel(val, port->membase + AML_UART_CONTROL);
121}
122
123static void meson_uart_stop_rx(struct uart_port *port)
124{
125 u32 val;
126
127 val = readl(port->membase + AML_UART_CONTROL);
128 val &= ~AML_UART_RX_EN;
129 writel(val, port->membase + AML_UART_CONTROL);
130}
131
132static void meson_uart_shutdown(struct uart_port *port)
133{
134 unsigned long flags;
135 u32 val;
136
137 free_irq(port->irq, port);
138
139 spin_lock_irqsave(&port->lock, flags);
140
141 val = readl(port->membase + AML_UART_CONTROL);
855ddcab 142 val &= ~AML_UART_RX_EN;
ff7693d0
CC		 143 val &= ~(AML_UART_RX_INT_EN | AML_UART_TX_INT_EN);
144 writel(val, port->membase + AML_UART_CONTROL);
145
146 spin_unlock_irqrestore(&port->lock, flags);
147}
148
149static void meson_uart_start_tx(struct uart_port *port)
150{
151 struct circ_buf *xmit = &port->state->xmit;
152 unsigned int ch;
f1dd05c8 153 u32 val;
ff7693d0
CC		 154
155 if (uart_tx_stopped(port)) {
156 meson_uart_stop_tx(port);
157 return;
158 }
159
160 while (!(readl(port->membase + AML_UART_STATUS) & AML_UART_TX_FULL)) {
161 if (port->x_char) {
162 writel(port->x_char, port->membase + AML_UART_WFIFO);
163 port->icount.tx++;
164 port->x_char = 0;
165 continue;
166 }
167
168 if (uart_circ_empty(xmit))
169 break;
170
171 ch = xmit->buf[xmit->tail];
172 writel(ch, port->membase + AML_UART_WFIFO);
173 xmit->tail = (xmit->tail+1) & (SERIAL_XMIT_SIZE - 1);
174 port->icount.tx++;
175 }
176
f1dd05c8
BD		 177 if (!uart_circ_empty(xmit)) {
178 val = readl(port->membase + AML_UART_CONTROL);
179 val |= AML_UART_TX_INT_EN;
180 writel(val, port->membase + AML_UART_CONTROL);
181 }
182
ff7693d0
CC		 183 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
184 uart_write_wakeup(port);
185}
186
187static void meson_receive_chars(struct uart_port *port)
188{
189 struct tty_port *tport = &port->state->port;
190 char flag;
b86ac225 191 u32 ostatus, status, ch, mode;
ff7693d0
CC		 192
193 do {
194 flag = TTY_NORMAL;
195 port->icount.rx++;
b86ac225 196 ostatus = status = readl(port->membase + AML_UART_STATUS);
ff7693d0
CC		 197
198 if (status & AML_UART_ERR) {
199 if (status & AML_UART_TX_FIFO_WERR)
200 port->icount.overrun++;
201 else if (status & AML_UART_FRAME_ERR)
202 port->icount.frame++;
203 else if (status & AML_UART_PARITY_ERR)
204 port->icount.frame++;
205
206 mode = readl(port->membase + AML_UART_CONTROL);
207 mode |= AML_UART_CLEAR_ERR;
208 writel(mode, port->membase + AML_UART_CONTROL);
209
210 /* It doesn't clear to 0 automatically */
211 mode &= ~AML_UART_CLEAR_ERR;
212 writel(mode, port->membase + AML_UART_CONTROL);
213
214 status &= port->read_status_mask;
215 if (status & AML_UART_FRAME_ERR)
216 flag = TTY_FRAME;
217 else if (status & AML_UART_PARITY_ERR)
218 flag = TTY_PARITY;
219 }
220
221 ch = readl(port->membase + AML_UART_RFIFO);
222 ch &= 0xff;
223
b86ac225
YL		 224 if ((ostatus & AML_UART_FRAME_ERR) && (ch == 0)) {
225 port->icount.brk++;
226 flag = TTY_BREAK;
227 if (uart_handle_break(port))
228 continue;
229 }
230
231 if (uart_handle_sysrq_char(port, ch))
232 continue;
233
ff7693d0
CC		 234 if ((status & port->ignore_status_mask) == 0)
235 tty_insert_flip_char(tport, ch, flag);
236
237 if (status & AML_UART_TX_FIFO_WERR)
238 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
239
240 } while (!(readl(port->membase + AML_UART_STATUS) & AML_UART_RX_EMPTY));
241
242 spin_unlock(&port->lock);
243 tty_flip_buffer_push(tport);
244 spin_lock(&port->lock);
245}
246
247static irqreturn_t meson_uart_interrupt(int irq, void *dev_id)
248{
249 struct uart_port *port = (struct uart_port *)dev_id;
250
251 spin_lock(&port->lock);
252
253 if (!(readl(port->membase + AML_UART_STATUS) & AML_UART_RX_EMPTY))
254 meson_receive_chars(port);
255
39469654
BD		 256 if (!(readl(port->membase + AML_UART_STATUS) & AML_UART_TX_FULL)) {
257 if (readl(port->membase + AML_UART_CONTROL) & AML_UART_TX_INT_EN)
258 meson_uart_start_tx(port);
259 }
ff7693d0
CC		 260
261 spin_unlock(&port->lock);
262
263 return IRQ_HANDLED;
264}
265
266static const char *meson_uart_type(struct uart_port *port)
267{
268 return (port->type == PORT_MESON) ? "meson_uart" : NULL;
269}
270
00661dd8 271static void meson_uart_reset(struct uart_port *port)
ff7693d0
CC		 272{
273 u32 val;
ff7693d0
CC		 274
275 val = readl(port->membase + AML_UART_CONTROL);
276 val |= (AML_UART_RX_RST | AML_UART_TX_RST | AML_UART_CLR_ERR);
277 writel(val, port->membase + AML_UART_CONTROL);
278
279 val &= ~(AML_UART_RX_RST | AML_UART_TX_RST | AML_UART_CLR_ERR);
280 writel(val, port->membase + AML_UART_CONTROL);
00661dd8
BD		 281}
282
283static int meson_uart_startup(struct uart_port *port)
284{
285 u32 val;
286 int ret = 0;
287
288 val = readl(port->membase + AML_UART_CONTROL);
289 val |= AML_UART_CLR_ERR;
290 writel(val, port->membase + AML_UART_CONTROL);
291 val &= ~AML_UART_CLR_ERR;
292 writel(val, port->membase + AML_UART_CONTROL);
ff7693d0
CC		 293
294 val |= (AML_UART_RX_EN | AML_UART_TX_EN);
295 writel(val, port->membase + AML_UART_CONTROL);
296
297 val |= (AML_UART_RX_INT_EN | AML_UART_TX_INT_EN);
298 writel(val, port->membase + AML_UART_CONTROL);
299
300 val = (AML_UART_RECV_IRQ(1) | AML_UART_XMIT_IRQ(port->fifosize / 2));
301 writel(val, port->membase + AML_UART_MISC);
302
303 ret = request_irq(port->irq, meson_uart_interrupt, 0,
8b7a6b2b 304 port->name, port);
ff7693d0
CC		 305
306 return ret;
307}
308
309static void meson_uart_change_speed(struct uart_port *port, unsigned long baud)
310{
311 u32 val;
312
f1f5c140 313 while (!meson_uart_tx_empty(port))
ff7693d0
CC		 314 cpu_relax();
315
146f3808
AF		 316 if (port->uartclk == 24000000) {
317 val = ((port->uartclk / 3) / baud) - 1;
318 val |= AML_UART_BAUD_XTAL;
319 } else {
320 val = ((port->uartclk * 10 / (baud * 4) + 5) / 10) - 1;
321 }
ff7693d0
CC		 322 val |= AML_UART_BAUD_USE;
323 writel(val, port->membase + AML_UART_REG5);
324}
325
326static void meson_uart_set_termios(struct uart_port *port,
327 struct ktermios *termios,
328 struct ktermios *old)
329{
330 unsigned int cflags, iflags, baud;
331 unsigned long flags;
332 u32 val;
333
334 spin_lock_irqsave(&port->lock, flags);
335
336 cflags = termios->c_cflag;
337 iflags = termios->c_iflag;
338
339 val = readl(port->membase + AML_UART_CONTROL);
340
341 val &= ~AML_UART_DATA_LEN_MASK;
342 switch (cflags & CSIZE) {
343 case CS8:
344 val |= AML_UART_DATA_LEN_8BIT;
345 break;
346 case CS7:
347 val |= AML_UART_DATA_LEN_7BIT;
348 break;
349 case CS6:
350 val |= AML_UART_DATA_LEN_6BIT;
351 break;
352 case CS5:
353 val |= AML_UART_DATA_LEN_5BIT;
354 break;
355 }
356
357 if (cflags & PARENB)
358 val |= AML_UART_PARITY_EN;
359 else
360 val &= ~AML_UART_PARITY_EN;
361
362 if (cflags & PARODD)
363 val |= AML_UART_PARITY_TYPE;
364 else
365 val &= ~AML_UART_PARITY_TYPE;
366
367 val &= ~AML_UART_STOP_BIN_LEN_MASK;
368 if (cflags & CSTOPB)
369 val |= AML_UART_STOP_BIN_2SB;
370 else
88f37d70 371 val |= AML_UART_STOP_BIN_1SB;
ff7693d0
CC		 372
373 if (cflags & CRTSCTS)
374 val &= ~AML_UART_TWO_WIRE_EN;
375 else
376 val |= AML_UART_TWO_WIRE_EN;
377
378 writel(val, port->membase + AML_UART_CONTROL);
379
8c9faa55 380 baud = uart_get_baud_rate(port, termios, old, 9600, 4000000);
ff7693d0
CC		 381 meson_uart_change_speed(port, baud);
382
383 port->read_status_mask = AML_UART_TX_FIFO_WERR;
384 if (iflags & INPCK)
385 port->read_status_mask |= AML_UART_PARITY_ERR |
386 AML_UART_FRAME_ERR;
387
388 port->ignore_status_mask = 0;
389 if (iflags & IGNPAR)
390 port->ignore_status_mask |= AML_UART_PARITY_ERR |
391 AML_UART_FRAME_ERR;
392
393 uart_update_timeout(port, termios->c_cflag, baud);
394 spin_unlock_irqrestore(&port->lock, flags);
395}
396
397static int meson_uart_verify_port(struct uart_port *port,
398 struct serial_struct *ser)
399{
400 int ret = 0;
401
402 if (port->type != PORT_MESON)
403 ret = -EINVAL;
404 if (port->irq != ser->irq)
405 ret = -EINVAL;
406 if (ser->baud_base < 9600)
407 ret = -EINVAL;
408 return ret;
409}
410
411static void meson_uart_release_port(struct uart_port *port)
412{
1b1ecaa6
HK		 413 devm_iounmap(port->dev, port->membase);
414 port->membase = NULL;
415 devm_release_mem_region(port->dev, port->mapbase, port->mapsize);
ff7693d0
CC		 416}
417
418static int meson_uart_request_port(struct uart_port *port)
419{
ff3b9cad 420 if (!devm_request_mem_region(port->dev, port->mapbase, port->mapsize,
ff7693d0
CC		 421 dev_name(port->dev))) {
422 dev_err(port->dev, "Memory region busy\n");
423 return -EBUSY;
424 }
425
1b1ecaa6
HK		 426 port->membase = devm_ioremap_nocache(port->dev, port->mapbase,
427 port->mapsize);
428 if (!port->membase)
429 return -ENOMEM;
ff7693d0
CC		 430
431 return 0;
432}
433
434static void meson_uart_config_port(struct uart_port *port, int flags)
435{
436 if (flags & UART_CONFIG_TYPE) {
437 port->type = PORT_MESON;
438 meson_uart_request_port(port);
439 }
440}
441
921469f7 442static const struct uart_ops meson_uart_ops = {
ff7693d0
CC		 443 .set_mctrl = meson_uart_set_mctrl,
444 .get_mctrl = meson_uart_get_mctrl,
445 .tx_empty = meson_uart_tx_empty,
446 .start_tx = meson_uart_start_tx,
447 .stop_tx = meson_uart_stop_tx,
448 .stop_rx = meson_uart_stop_rx,
449 .startup = meson_uart_startup,
450 .shutdown = meson_uart_shutdown,
451 .set_termios = meson_uart_set_termios,
452 .type = meson_uart_type,
453 .config_port = meson_uart_config_port,
454 .request_port = meson_uart_request_port,
455 .release_port = meson_uart_release_port,
456 .verify_port = meson_uart_verify_port,
457};
458
459#ifdef CONFIG_SERIAL_MESON_CONSOLE
5fa4accf
AB		 460static void meson_uart_enable_tx_engine(struct uart_port *port)
461{
462 u32 val;
463
464 val = readl(port->membase + AML_UART_CONTROL);
465 val |= AML_UART_TX_EN;
466 writel(val, port->membase + AML_UART_CONTROL);
467}
ff7693d0
CC		 468
469static void meson_console_putchar(struct uart_port *port, int ch)
470{
471 if (!port->membase)
472 return;
473
474 while (readl(port->membase + AML_UART_STATUS) & AML_UART_TX_FULL)
475 cpu_relax();
476 writel(ch, port->membase + AML_UART_WFIFO);
477}
478
736d5538
AF		 479static void meson_serial_port_write(struct uart_port *port, const char *s,
480 u_int count)
ff7693d0 481{
ff7693d0
CC		 482 unsigned long flags;
483 int locked;
2561f068 484 u32 val, tmp;
ff7693d0 485
ff7693d0
CC		 486 local_irq_save(flags);
487 if (port->sysrq) {
488 locked = 0;
489 } else if (oops_in_progress) {
490 locked = spin_trylock(&port->lock);
491 } else {
492 spin_lock(&port->lock);
493 locked = 1;
494 }
495
41788f05 496 val = readl(port->membase + AML_UART_CONTROL);
2561f068
BD		 497 tmp = val & ~(AML_UART_TX_INT_EN | AML_UART_RX_INT_EN);
498 writel(tmp, port->membase + AML_UART_CONTROL);
41788f05 499
ff7693d0 500 uart_console_write(port, s, count, meson_console_putchar);
2561f068 501 writel(val, port->membase + AML_UART_CONTROL);
ff7693d0
CC		 502
503 if (locked)
504 spin_unlock(&port->lock);
505 local_irq_restore(flags);
506}
507
736d5538
AF		 508static void meson_serial_console_write(struct console *co, const char *s,
509 u_int count)
510{
511 struct uart_port *port;
512
513 port = meson_ports[co->index];
514 if (!port)
515 return;
516
517 meson_serial_port_write(port, s, count);
518}
519
ff7693d0
CC		 520static int meson_serial_console_setup(struct console *co, char *options)
521{
522 struct uart_port *port;
523 int baud = 115200;
524 int bits = 8;
525 int parity = 'n';
526 int flow = 'n';
527
528 if (co->index < 0 || co->index >= AML_UART_PORT_NUM)
529 return -EINVAL;
530
531 port = meson_ports[co->index];
532 if (!port || !port->membase)
533 return -ENODEV;
534
ba50f1df
HK		 535 meson_uart_enable_tx_engine(port);
536
ff7693d0
CC		 537 if (options)
538 uart_parse_options(options, &baud, &parity, &bits, &flow);
539
540 return uart_set_options(port, co, baud, parity, bits, flow);
541}
542
543static struct console meson_serial_console = {
544 .name = AML_UART_DEV_NAME,
545 .write = meson_serial_console_write,
546 .device = uart_console_device,
547 .setup = meson_serial_console_setup,
548 .flags = CON_PRINTBUFFER,
549 .index = -1,
550 .data = &meson_uart_driver,
551};
552
553static int __init meson_serial_console_init(void)
554{
555 register_console(&meson_serial_console);
556 return 0;
557}
558console_initcall(meson_serial_console_init);
559
736d5538
AF		 560static void meson_serial_early_console_write(struct console *co,
561 const char *s,
562 u_int count)
563{
564 struct earlycon_device *dev = co->data;
565
566 meson_serial_port_write(&dev->port, s, count);
567}
568
569static int __init
570meson_serial_early_console_setup(struct earlycon_device *device, const char *opt)
571{
572 if (!device->port.membase)
573 return -ENODEV;
574
ba50f1df 575 meson_uart_enable_tx_engine(&device->port);
736d5538
AF		 576 device->con->write = meson_serial_early_console_write;
577 return 0;
578}
9f60e0e7 579/* Legacy bindings, should be removed when no more used */
736d5538
AF		 580OF_EARLYCON_DECLARE(meson, "amlogic,meson-uart",
581 meson_serial_early_console_setup);
9f60e0e7
HK		 582/* Stable bindings */
583OF_EARLYCON_DECLARE(meson, "amlogic,meson-ao-uart",
584 meson_serial_early_console_setup);
736d5538 585
ff7693d0
CC		 586#define MESON_SERIAL_CONSOLE (&meson_serial_console)
587#else
588#define MESON_SERIAL_CONSOLE NULL
589#endif
590
591static struct uart_driver meson_uart_driver = {
592 .owner = THIS_MODULE,
593 .driver_name = "meson_uart",
594 .dev_name = AML_UART_DEV_NAME,
595 .nr = AML_UART_PORT_NUM,
596 .cons = MESON_SERIAL_CONSOLE,
597};
598
9f60e0e7
HK		 599static inline struct clk *meson_uart_probe_clock(struct device *dev,
600 const char *id)
601{
602 struct clk *clk = NULL;
603 int ret;
604
605 clk = devm_clk_get(dev, id);
606 if (IS_ERR(clk))
607 return clk;
608
609 ret = clk_prepare_enable(clk);
610 if (ret) {
611 dev_err(dev, "couldn't enable clk\n");
612 return ERR_PTR(ret);
613 }
614
615 devm_add_action_or_reset(dev,
616 (void(*)(void *))clk_disable_unprepare,
617 clk);
618
619 return clk;
620}
621
622/*
623 * This function gets clocks in the legacy non-stable DT bindings.
624 * This code will be remove once all the platforms switch to the
625 * new DT bindings.
626 */
627static int meson_uart_probe_clocks_legacy(struct platform_device *pdev,
628 struct uart_port *port)
629{
630 struct clk *clk = NULL;
631
632 clk = meson_uart_probe_clock(&pdev->dev, NULL);
633 if (IS_ERR(clk))
634 return PTR_ERR(clk);
635
636 port->uartclk = clk_get_rate(clk);
637
638 return 0;
639}
640
641static int meson_uart_probe_clocks(struct platform_device *pdev,
642 struct uart_port *port)
643{
644 struct clk *clk_xtal = NULL;
645 struct clk *clk_pclk = NULL;
646 struct clk *clk_baud = NULL;
647
648 clk_pclk = meson_uart_probe_clock(&pdev->dev, "pclk");
649 if (IS_ERR(clk_pclk))
650 return PTR_ERR(clk_pclk);
651
652 clk_xtal = meson_uart_probe_clock(&pdev->dev, "xtal");
653 if (IS_ERR(clk_xtal))
654 return PTR_ERR(clk_xtal);
655
656 clk_baud = meson_uart_probe_clock(&pdev->dev, "baud");
657 if (IS_ERR(clk_baud))
658 return PTR_ERR(clk_baud);
659
660 port->uartclk = clk_get_rate(clk_baud);
661
662 return 0;
663}
664
ff7693d0
CC		 665static int meson_uart_probe(struct platform_device *pdev)
666{
667 struct resource *res_mem, *res_irq;
668 struct uart_port *port;
ff7693d0
CC		 669 int ret = 0;
670
671 if (pdev->dev.of_node)
672 pdev->id = of_alias_get_id(pdev->dev.of_node, "serial");
673
674 if (pdev->id < 0 || pdev->id >= AML_UART_PORT_NUM)
675 return -EINVAL;
676
677 res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
678 if (!res_mem)
679 return -ENODEV;
680
681 res_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
682 if (!res_irq)
683 return -ENODEV;
684
685 if (meson_ports[pdev->id]) {
686 dev_err(&pdev->dev, "port %d already allocated\n", pdev->id);
687 return -EBUSY;
688 }
689
690 port = devm_kzalloc(&pdev->dev, sizeof(struct uart_port), GFP_KERNEL);
691 if (!port)
692 return -ENOMEM;
693
9f60e0e7
HK		 694 /* Use legacy way until all platforms switch to new bindings */
695 if (of_device_is_compatible(pdev->dev.of_node, "amlogic,meson-uart"))
696 ret = meson_uart_probe_clocks_legacy(pdev, port);
697 else
698 ret = meson_uart_probe_clocks(pdev, port);
699
700 if (ret)
701 return ret;
ff7693d0 702
ff7693d0
CC		 703 port->iotype = UPIO_MEM;
704 port->mapbase = res_mem->start;
ff3b9cad 705 port->mapsize = resource_size(res_mem);
ff7693d0 706 port->irq = res_irq->start;
1b1ecaa6 707 port->flags = UPF_BOOT_AUTOCONF | UPF_LOW_LATENCY;
ff7693d0
CC		 708 port->dev = &pdev->dev;
709 port->line = pdev->id;
710 port->type = PORT_MESON;
711 port->x_char = 0;
712 port->ops = &meson_uart_ops;
713 port->fifosize = 64;
714
715 meson_ports[pdev->id] = port;
716 platform_set_drvdata(pdev, port);
717
00661dd8
BD		 718 /* reset port before registering (and possibly registering console) */
719 if (meson_uart_request_port(port) >= 0) {
720 meson_uart_reset(port);
721 meson_uart_release_port(port);
722 }
723
ff7693d0
CC		 724 ret = uart_add_one_port(&meson_uart_driver, port);
725 if (ret)
726 meson_ports[pdev->id] = NULL;
727
728 return ret;
729}
730
731static int meson_uart_remove(struct platform_device *pdev)
732{
733 struct uart_port *port;
734
735 port = platform_get_drvdata(pdev);
736 uart_remove_one_port(&meson_uart_driver, port);
737 meson_ports[pdev->id] = NULL;
738
739 return 0;
740}
741
ff7693d0 742static const struct of_device_id meson_uart_dt_match[] = {
9f60e0e7 743 /* Legacy bindings, should be removed when no more used */
ff7693d0 744 { .compatible = "amlogic,meson-uart" },
9f60e0e7
HK		 745 /* Stable bindings */
746 { .compatible = "amlogic,meson6-uart" },
747 { .compatible = "amlogic,meson8-uart" },
748 { .compatible = "amlogic,meson8b-uart" },
749 { .compatible = "amlogic,meson-gx-uart" },
ff7693d0
CC		 750 { /* sentinel */ },
751};
752MODULE_DEVICE_TABLE(of, meson_uart_dt_match);
753
754static struct platform_driver meson_uart_platform_driver = {
755 .probe = meson_uart_probe,
756 .remove = meson_uart_remove,
757 .driver = {
ff7693d0
CC		 758 .name = "meson_uart",
759 .of_match_table = meson_uart_dt_match,
760 },
761};
762
763static int __init meson_uart_init(void)
764{
765 int ret;
766
767 ret = uart_register_driver(&meson_uart_driver);
768 if (ret)
769 return ret;
770
771 ret = platform_driver_register(&meson_uart_platform_driver);
772 if (ret)
773 uart_unregister_driver(&meson_uart_driver);
774
775 return ret;
776}
777
778static void __exit meson_uart_exit(void)
779{
780 platform_driver_unregister(&meson_uart_platform_driver);
781 uart_unregister_driver(&meson_uart_driver);
782}
783
784module_init(meson_uart_init);
785module_exit(meson_uart_exit);
786
787MODULE_AUTHOR("Carlo Caione <carlo@caione.org>");
788MODULE_DESCRIPTION("Amlogic Meson serial port driver");
789MODULE_LICENSE("GPL v2");
Linux 6.x block layer and io_uring tree(s)