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serial: 8250_fintek: Fix crash with baud rate B0
[linux-2.6-block.git] / drivers / tty / serial / meson_uart.c
CommitLineData
e3b3d0f5 1// SPDX-License-Identifier: GPL-2.0
ff7693d0
CC		 2/*
3 * Based on meson_uart.c, by AMLOGIC, INC.
4 *
5 * Copyright (C) 2014 Carlo Caione <carlo@caione.org>
ff7693d0
CC		 6 */
7
b86ac225
YL		 8#if defined(CONFIG_SERIAL_MESON_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
9#define SUPPORT_SYSRQ
10#endif
11
ff7693d0
CC		 12#include <linux/clk.h>
13#include <linux/console.h>
14#include <linux/delay.h>
15#include <linux/init.h>
16#include <linux/io.h>
17#include <linux/module.h>
18#include <linux/kernel.h>
19#include <linux/of.h>
20#include <linux/platform_device.h>
21#include <linux/serial.h>
22#include <linux/serial_core.h>
23#include <linux/tty.h>
24#include <linux/tty_flip.h>
25
26/* Register offsets */
27#define AML_UART_WFIFO 0x00
28#define AML_UART_RFIFO 0x04
29#define AML_UART_CONTROL 0x08
30#define AML_UART_STATUS 0x0c
31#define AML_UART_MISC 0x10
32#define AML_UART_REG5 0x14
33
34/* AML_UART_CONTROL bits */
35#define AML_UART_TX_EN BIT(12)
36#define AML_UART_RX_EN BIT(13)
37#define AML_UART_TX_RST BIT(22)
38#define AML_UART_RX_RST BIT(23)
39#define AML_UART_CLR_ERR BIT(24)
40#define AML_UART_RX_INT_EN BIT(27)
41#define AML_UART_TX_INT_EN BIT(28)
42#define AML_UART_DATA_LEN_MASK (0x03 << 20)
43#define AML_UART_DATA_LEN_8BIT (0x00 << 20)
44#define AML_UART_DATA_LEN_7BIT (0x01 << 20)
45#define AML_UART_DATA_LEN_6BIT (0x02 << 20)
46#define AML_UART_DATA_LEN_5BIT (0x03 << 20)
47
48/* AML_UART_STATUS bits */
49#define AML_UART_PARITY_ERR BIT(16)
50#define AML_UART_FRAME_ERR BIT(17)
51#define AML_UART_TX_FIFO_WERR BIT(18)
52#define AML_UART_RX_EMPTY BIT(20)
53#define AML_UART_TX_FULL BIT(21)
54#define AML_UART_TX_EMPTY BIT(22)
88679739 55#define AML_UART_XMIT_BUSY BIT(25)
ff7693d0
CC		 56#define AML_UART_ERR (AML_UART_PARITY_ERR | \
57 AML_UART_FRAME_ERR | \
58 AML_UART_TX_FIFO_WERR)
59
60/* AML_UART_CONTROL bits */
61#define AML_UART_TWO_WIRE_EN BIT(15)
62#define AML_UART_PARITY_TYPE BIT(18)
63#define AML_UART_PARITY_EN BIT(19)
64#define AML_UART_CLEAR_ERR BIT(24)
65#define AML_UART_STOP_BIN_LEN_MASK (0x03 << 16)
66#define AML_UART_STOP_BIN_1SB (0x00 << 16)
67#define AML_UART_STOP_BIN_2SB (0x01 << 16)
68
69/* AML_UART_MISC bits */
70#define AML_UART_XMIT_IRQ(c) (((c) & 0xff) << 8)
71#define AML_UART_RECV_IRQ(c) ((c) & 0xff)
72
73/* AML_UART_REG5 bits */
74#define AML_UART_BAUD_MASK 0x7fffff
75#define AML_UART_BAUD_USE BIT(23)
146f3808 76#define AML_UART_BAUD_XTAL BIT(24)
ff7693d0
CC		 77
78#define AML_UART_PORT_NUM 6
79#define AML_UART_DEV_NAME "ttyAML"
80
81
82static struct uart_driver meson_uart_driver;
83
84static struct uart_port *meson_ports[AML_UART_PORT_NUM];
85
86static void meson_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
87{
88}
89
90static unsigned int meson_uart_get_mctrl(struct uart_port *port)
91{
92 return TIOCM_CTS;
93}
94
95static unsigned int meson_uart_tx_empty(struct uart_port *port)
96{
97 u32 val;
98
99 val = readl(port->membase + AML_UART_STATUS);
88679739
BD		 100 val &= (AML_UART_TX_EMPTY | AML_UART_XMIT_BUSY);
101 return (val == AML_UART_TX_EMPTY) ? TIOCSER_TEMT : 0;
ff7693d0
CC		 102}
103
104static void meson_uart_stop_tx(struct uart_port *port)
105{
106 u32 val;
107
108 val = readl(port->membase + AML_UART_CONTROL);
855ddcab 109 val &= ~AML_UART_TX_INT_EN;
ff7693d0
CC		 110 writel(val, port->membase + AML_UART_CONTROL);
111}
112
113static void meson_uart_stop_rx(struct uart_port *port)
114{
115 u32 val;
116
117 val = readl(port->membase + AML_UART_CONTROL);
118 val &= ~AML_UART_RX_EN;
119 writel(val, port->membase + AML_UART_CONTROL);
120}
121
122static void meson_uart_shutdown(struct uart_port *port)
123{
124 unsigned long flags;
125 u32 val;
126
127 free_irq(port->irq, port);
128
129 spin_lock_irqsave(&port->lock, flags);
130
131 val = readl(port->membase + AML_UART_CONTROL);
855ddcab 132 val &= ~AML_UART_RX_EN;
ff7693d0
CC		 133 val &= ~(AML_UART_RX_INT_EN | AML_UART_TX_INT_EN);
134 writel(val, port->membase + AML_UART_CONTROL);
135
136 spin_unlock_irqrestore(&port->lock, flags);
137}
138
139static void meson_uart_start_tx(struct uart_port *port)
140{
141 struct circ_buf *xmit = &port->state->xmit;
142 unsigned int ch;
f1dd05c8 143 u32 val;
ff7693d0
CC		 144
145 if (uart_tx_stopped(port)) {
146 meson_uart_stop_tx(port);
147 return;
148 }
149
150 while (!(readl(port->membase + AML_UART_STATUS) & AML_UART_TX_FULL)) {
151 if (port->x_char) {
152 writel(port->x_char, port->membase + AML_UART_WFIFO);
153 port->icount.tx++;
154 port->x_char = 0;
155 continue;
156 }
157
158 if (uart_circ_empty(xmit))
159 break;
160
161 ch = xmit->buf[xmit->tail];
162 writel(ch, port->membase + AML_UART_WFIFO);
163 xmit->tail = (xmit->tail+1) & (SERIAL_XMIT_SIZE - 1);
164 port->icount.tx++;
165 }
166
f1dd05c8
BD		 167 if (!uart_circ_empty(xmit)) {
168 val = readl(port->membase + AML_UART_CONTROL);
169 val |= AML_UART_TX_INT_EN;
170 writel(val, port->membase + AML_UART_CONTROL);
171 }
172
ff7693d0
CC		 173 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
174 uart_write_wakeup(port);
175}
176
177static void meson_receive_chars(struct uart_port *port)
178{
179 struct tty_port *tport = &port->state->port;
180 char flag;
b86ac225 181 u32 ostatus, status, ch, mode;
ff7693d0
CC		 182
183 do {
184 flag = TTY_NORMAL;
185 port->icount.rx++;
b86ac225 186 ostatus = status = readl(port->membase + AML_UART_STATUS);
ff7693d0
CC		 187
188 if (status & AML_UART_ERR) {
189 if (status & AML_UART_TX_FIFO_WERR)
190 port->icount.overrun++;
191 else if (status & AML_UART_FRAME_ERR)
192 port->icount.frame++;
193 else if (status & AML_UART_PARITY_ERR)
194 port->icount.frame++;
195
196 mode = readl(port->membase + AML_UART_CONTROL);
197 mode |= AML_UART_CLEAR_ERR;
198 writel(mode, port->membase + AML_UART_CONTROL);
199
200 /* It doesn't clear to 0 automatically */
201 mode &= ~AML_UART_CLEAR_ERR;
202 writel(mode, port->membase + AML_UART_CONTROL);
203
204 status &= port->read_status_mask;
205 if (status & AML_UART_FRAME_ERR)
206 flag = TTY_FRAME;
207 else if (status & AML_UART_PARITY_ERR)
208 flag = TTY_PARITY;
209 }
210
211 ch = readl(port->membase + AML_UART_RFIFO);
212 ch &= 0xff;
213
b86ac225
YL		 214 if ((ostatus & AML_UART_FRAME_ERR) && (ch == 0)) {
215 port->icount.brk++;
216 flag = TTY_BREAK;
217 if (uart_handle_break(port))
218 continue;
219 }
220
221 if (uart_handle_sysrq_char(port, ch))
222 continue;
223
ff7693d0
CC		 224 if ((status & port->ignore_status_mask) == 0)
225 tty_insert_flip_char(tport, ch, flag);
226
227 if (status & AML_UART_TX_FIFO_WERR)
228 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
229
230 } while (!(readl(port->membase + AML_UART_STATUS) & AML_UART_RX_EMPTY));
231
232 spin_unlock(&port->lock);
233 tty_flip_buffer_push(tport);
234 spin_lock(&port->lock);
235}
236
237static irqreturn_t meson_uart_interrupt(int irq, void *dev_id)
238{
239 struct uart_port *port = (struct uart_port *)dev_id;
240
241 spin_lock(&port->lock);
242
243 if (!(readl(port->membase + AML_UART_STATUS) & AML_UART_RX_EMPTY))
244 meson_receive_chars(port);
245
39469654
BD		 246 if (!(readl(port->membase + AML_UART_STATUS) & AML_UART_TX_FULL)) {
247 if (readl(port->membase + AML_UART_CONTROL) & AML_UART_TX_INT_EN)
248 meson_uart_start_tx(port);
249 }
ff7693d0
CC		 250
251 spin_unlock(&port->lock);
252
253 return IRQ_HANDLED;
254}
255
256static const char *meson_uart_type(struct uart_port *port)
257{
258 return (port->type == PORT_MESON) ? "meson_uart" : NULL;
259}
260
00661dd8 261static void meson_uart_reset(struct uart_port *port)
ff7693d0
CC		 262{
263 u32 val;
ff7693d0
CC		 264
265 val = readl(port->membase + AML_UART_CONTROL);
266 val |= (AML_UART_RX_RST | AML_UART_TX_RST | AML_UART_CLR_ERR);
267 writel(val, port->membase + AML_UART_CONTROL);
268
269 val &= ~(AML_UART_RX_RST | AML_UART_TX_RST | AML_UART_CLR_ERR);
270 writel(val, port->membase + AML_UART_CONTROL);
00661dd8
BD		 271}
272
273static int meson_uart_startup(struct uart_port *port)
274{
275 u32 val;
276 int ret = 0;
277
278 val = readl(port->membase + AML_UART_CONTROL);
279 val |= AML_UART_CLR_ERR;
280 writel(val, port->membase + AML_UART_CONTROL);
281 val &= ~AML_UART_CLR_ERR;
282 writel(val, port->membase + AML_UART_CONTROL);
ff7693d0
CC		 283
284 val |= (AML_UART_RX_EN | AML_UART_TX_EN);
285 writel(val, port->membase + AML_UART_CONTROL);
286
287 val |= (AML_UART_RX_INT_EN | AML_UART_TX_INT_EN);
288 writel(val, port->membase + AML_UART_CONTROL);
289
290 val = (AML_UART_RECV_IRQ(1) | AML_UART_XMIT_IRQ(port->fifosize / 2));
291 writel(val, port->membase + AML_UART_MISC);
292
293 ret = request_irq(port->irq, meson_uart_interrupt, 0,
8b7a6b2b 294 port->name, port);
ff7693d0
CC		 295
296 return ret;
297}
298
299static void meson_uart_change_speed(struct uart_port *port, unsigned long baud)
300{
301 u32 val;
302
f1f5c140 303 while (!meson_uart_tx_empty(port))
ff7693d0
CC		 304 cpu_relax();
305
146f3808
AF		 306 if (port->uartclk == 24000000) {
307 val = ((port->uartclk / 3) / baud) - 1;
308 val |= AML_UART_BAUD_XTAL;
309 } else {
310 val = ((port->uartclk * 10 / (baud * 4) + 5) / 10) - 1;
311 }
ff7693d0
CC		 312 val |= AML_UART_BAUD_USE;
313 writel(val, port->membase + AML_UART_REG5);
314}
315
316static void meson_uart_set_termios(struct uart_port *port,
317 struct ktermios *termios,
318 struct ktermios *old)
319{
320 unsigned int cflags, iflags, baud;
321 unsigned long flags;
322 u32 val;
323
324 spin_lock_irqsave(&port->lock, flags);
325
326 cflags = termios->c_cflag;
327 iflags = termios->c_iflag;
328
329 val = readl(port->membase + AML_UART_CONTROL);
330
331 val &= ~AML_UART_DATA_LEN_MASK;
332 switch (cflags & CSIZE) {
333 case CS8:
334 val |= AML_UART_DATA_LEN_8BIT;
335 break;
336 case CS7:
337 val |= AML_UART_DATA_LEN_7BIT;
338 break;
339 case CS6:
340 val |= AML_UART_DATA_LEN_6BIT;
341 break;
342 case CS5:
343 val |= AML_UART_DATA_LEN_5BIT;
344 break;
345 }
346
347 if (cflags & PARENB)
348 val |= AML_UART_PARITY_EN;
349 else
350 val &= ~AML_UART_PARITY_EN;
351
352 if (cflags & PARODD)
353 val |= AML_UART_PARITY_TYPE;
354 else
355 val &= ~AML_UART_PARITY_TYPE;
356
357 val &= ~AML_UART_STOP_BIN_LEN_MASK;
358 if (cflags & CSTOPB)
359 val |= AML_UART_STOP_BIN_2SB;
360 else
88f37d70 361 val |= AML_UART_STOP_BIN_1SB;
ff7693d0
CC		 362
363 if (cflags & CRTSCTS)
364 val &= ~AML_UART_TWO_WIRE_EN;
365 else
366 val |= AML_UART_TWO_WIRE_EN;
367
368 writel(val, port->membase + AML_UART_CONTROL);
369
8c9faa55 370 baud = uart_get_baud_rate(port, termios, old, 9600, 4000000);
ff7693d0
CC		 371 meson_uart_change_speed(port, baud);
372
373 port->read_status_mask = AML_UART_TX_FIFO_WERR;
374 if (iflags & INPCK)
375 port->read_status_mask |= AML_UART_PARITY_ERR |
376 AML_UART_FRAME_ERR;
377
378 port->ignore_status_mask = 0;
379 if (iflags & IGNPAR)
380 port->ignore_status_mask |= AML_UART_PARITY_ERR |
381 AML_UART_FRAME_ERR;
382
383 uart_update_timeout(port, termios->c_cflag, baud);
384 spin_unlock_irqrestore(&port->lock, flags);
385}
386
387static int meson_uart_verify_port(struct uart_port *port,
388 struct serial_struct *ser)
389{
390 int ret = 0;
391
392 if (port->type != PORT_MESON)
393 ret = -EINVAL;
394 if (port->irq != ser->irq)
395 ret = -EINVAL;
396 if (ser->baud_base < 9600)
397 ret = -EINVAL;
398 return ret;
399}
400
401static void meson_uart_release_port(struct uart_port *port)
402{
1b1ecaa6
HK		 403 devm_iounmap(port->dev, port->membase);
404 port->membase = NULL;
405 devm_release_mem_region(port->dev, port->mapbase, port->mapsize);
ff7693d0
CC		 406}
407
408static int meson_uart_request_port(struct uart_port *port)
409{
ff3b9cad 410 if (!devm_request_mem_region(port->dev, port->mapbase, port->mapsize,
ff7693d0
CC		 411 dev_name(port->dev))) {
412 dev_err(port->dev, "Memory region busy\n");
413 return -EBUSY;
414 }
415
1b1ecaa6
HK		 416 port->membase = devm_ioremap_nocache(port->dev, port->mapbase,
417 port->mapsize);
418 if (!port->membase)
419 return -ENOMEM;
ff7693d0
CC		 420
421 return 0;
422}
423
424static void meson_uart_config_port(struct uart_port *port, int flags)
425{
426 if (flags & UART_CONFIG_TYPE) {
427 port->type = PORT_MESON;
428 meson_uart_request_port(port);
429 }
430}
431
921469f7 432static const struct uart_ops meson_uart_ops = {
ff7693d0
CC		 433 .set_mctrl = meson_uart_set_mctrl,
434 .get_mctrl = meson_uart_get_mctrl,
435 .tx_empty = meson_uart_tx_empty,
436 .start_tx = meson_uart_start_tx,
437 .stop_tx = meson_uart_stop_tx,
438 .stop_rx = meson_uart_stop_rx,
439 .startup = meson_uart_startup,
440 .shutdown = meson_uart_shutdown,
441 .set_termios = meson_uart_set_termios,
442 .type = meson_uart_type,
443 .config_port = meson_uart_config_port,
444 .request_port = meson_uart_request_port,
445 .release_port = meson_uart_release_port,
446 .verify_port = meson_uart_verify_port,
447};
448
449#ifdef CONFIG_SERIAL_MESON_CONSOLE
5fa4accf
AB		 450static void meson_uart_enable_tx_engine(struct uart_port *port)
451{
452 u32 val;
453
454 val = readl(port->membase + AML_UART_CONTROL);
455 val |= AML_UART_TX_EN;
456 writel(val, port->membase + AML_UART_CONTROL);
457}
ff7693d0
CC		 458
459static void meson_console_putchar(struct uart_port *port, int ch)
460{
461 if (!port->membase)
462 return;
463
464 while (readl(port->membase + AML_UART_STATUS) & AML_UART_TX_FULL)
465 cpu_relax();
466 writel(ch, port->membase + AML_UART_WFIFO);
467}
468
736d5538
AF		 469static void meson_serial_port_write(struct uart_port *port, const char *s,
470 u_int count)
ff7693d0 471{
ff7693d0
CC		 472 unsigned long flags;
473 int locked;
2561f068 474 u32 val, tmp;
ff7693d0 475
ff7693d0
CC		 476 local_irq_save(flags);
477 if (port->sysrq) {
478 locked = 0;
479 } else if (oops_in_progress) {
480 locked = spin_trylock(&port->lock);
481 } else {
482 spin_lock(&port->lock);
483 locked = 1;
484 }
485
41788f05 486 val = readl(port->membase + AML_UART_CONTROL);
2561f068
BD		 487 tmp = val & ~(AML_UART_TX_INT_EN | AML_UART_RX_INT_EN);
488 writel(tmp, port->membase + AML_UART_CONTROL);
41788f05 489
ff7693d0 490 uart_console_write(port, s, count, meson_console_putchar);
2561f068 491 writel(val, port->membase + AML_UART_CONTROL);
ff7693d0
CC		 492
493 if (locked)
494 spin_unlock(&port->lock);
495 local_irq_restore(flags);
496}
497
736d5538
AF		 498static void meson_serial_console_write(struct console *co, const char *s,
499 u_int count)
500{
501 struct uart_port *port;
502
503 port = meson_ports[co->index];
504 if (!port)
505 return;
506
507 meson_serial_port_write(port, s, count);
508}
509
ff7693d0
CC		 510static int meson_serial_console_setup(struct console *co, char *options)
511{
512 struct uart_port *port;
513 int baud = 115200;
514 int bits = 8;
515 int parity = 'n';
516 int flow = 'n';
517
518 if (co->index < 0 || co->index >= AML_UART_PORT_NUM)
519 return -EINVAL;
520
521 port = meson_ports[co->index];
522 if (!port || !port->membase)
523 return -ENODEV;
524
ba50f1df
HK		 525 meson_uart_enable_tx_engine(port);
526
ff7693d0
CC		 527 if (options)
528 uart_parse_options(options, &baud, &parity, &bits, &flow);
529
530 return uart_set_options(port, co, baud, parity, bits, flow);
531}
532
533static struct console meson_serial_console = {
534 .name = AML_UART_DEV_NAME,
535 .write = meson_serial_console_write,
536 .device = uart_console_device,
537 .setup = meson_serial_console_setup,
538 .flags = CON_PRINTBUFFER,
539 .index = -1,
540 .data = &meson_uart_driver,
541};
542
543static int __init meson_serial_console_init(void)
544{
545 register_console(&meson_serial_console);
546 return 0;
547}
548console_initcall(meson_serial_console_init);
549
736d5538
AF		 550static void meson_serial_early_console_write(struct console *co,
551 const char *s,
552 u_int count)
553{
554 struct earlycon_device *dev = co->data;
555
556 meson_serial_port_write(&dev->port, s, count);
557}
558
559static int __init
560meson_serial_early_console_setup(struct earlycon_device *device, const char *opt)
561{
562 if (!device->port.membase)
563 return -ENODEV;
564
ba50f1df 565 meson_uart_enable_tx_engine(&device->port);
736d5538
AF		 566 device->con->write = meson_serial_early_console_write;
567 return 0;
568}
9f60e0e7 569/* Legacy bindings, should be removed when no more used */
736d5538
AF		 570OF_EARLYCON_DECLARE(meson, "amlogic,meson-uart",
571 meson_serial_early_console_setup);
9f60e0e7
HK		 572/* Stable bindings */
573OF_EARLYCON_DECLARE(meson, "amlogic,meson-ao-uart",
574 meson_serial_early_console_setup);
736d5538 575
ff7693d0
CC		 576#define MESON_SERIAL_CONSOLE (&meson_serial_console)
577#else
578#define MESON_SERIAL_CONSOLE NULL
579#endif
580
581static struct uart_driver meson_uart_driver = {
582 .owner = THIS_MODULE,
583 .driver_name = "meson_uart",
584 .dev_name = AML_UART_DEV_NAME,
585 .nr = AML_UART_PORT_NUM,
586 .cons = MESON_SERIAL_CONSOLE,
587};
588
9f60e0e7
HK		 589static inline struct clk *meson_uart_probe_clock(struct device *dev,
590 const char *id)
591{
592 struct clk *clk = NULL;
593 int ret;
594
595 clk = devm_clk_get(dev, id);
596 if (IS_ERR(clk))
597 return clk;
598
599 ret = clk_prepare_enable(clk);
600 if (ret) {
601 dev_err(dev, "couldn't enable clk\n");
602 return ERR_PTR(ret);
603 }
604
605 devm_add_action_or_reset(dev,
606 (void(*)(void *))clk_disable_unprepare,
607 clk);
608
609 return clk;
610}
611
612/*
613 * This function gets clocks in the legacy non-stable DT bindings.
614 * This code will be remove once all the platforms switch to the
615 * new DT bindings.
616 */
617static int meson_uart_probe_clocks_legacy(struct platform_device *pdev,
618 struct uart_port *port)
619{
620 struct clk *clk = NULL;
621
622 clk = meson_uart_probe_clock(&pdev->dev, NULL);
623 if (IS_ERR(clk))
624 return PTR_ERR(clk);
625
626 port->uartclk = clk_get_rate(clk);
627
628 return 0;
629}
630
631static int meson_uart_probe_clocks(struct platform_device *pdev,
632 struct uart_port *port)
633{
634 struct clk *clk_xtal = NULL;
635 struct clk *clk_pclk = NULL;
636 struct clk *clk_baud = NULL;
637
638 clk_pclk = meson_uart_probe_clock(&pdev->dev, "pclk");
639 if (IS_ERR(clk_pclk))
640 return PTR_ERR(clk_pclk);
641
642 clk_xtal = meson_uart_probe_clock(&pdev->dev, "xtal");
643 if (IS_ERR(clk_xtal))
644 return PTR_ERR(clk_xtal);
645
646 clk_baud = meson_uart_probe_clock(&pdev->dev, "baud");
647 if (IS_ERR(clk_baud))
648 return PTR_ERR(clk_baud);
649
650 port->uartclk = clk_get_rate(clk_baud);
651
652 return 0;
653}
654
ff7693d0
CC		 655static int meson_uart_probe(struct platform_device *pdev)
656{
657 struct resource *res_mem, *res_irq;
658 struct uart_port *port;
ff7693d0
CC		 659 int ret = 0;
660
661 if (pdev->dev.of_node)
662 pdev->id = of_alias_get_id(pdev->dev.of_node, "serial");
663
664 if (pdev->id < 0 || pdev->id >= AML_UART_PORT_NUM)
665 return -EINVAL;
666
667 res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
668 if (!res_mem)
669 return -ENODEV;
670
671 res_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
672 if (!res_irq)
673 return -ENODEV;
674
675 if (meson_ports[pdev->id]) {
676 dev_err(&pdev->dev, "port %d already allocated\n", pdev->id);
677 return -EBUSY;
678 }
679
680 port = devm_kzalloc(&pdev->dev, sizeof(struct uart_port), GFP_KERNEL);
681 if (!port)
682 return -ENOMEM;
683
9f60e0e7
HK		 684 /* Use legacy way until all platforms switch to new bindings */
685 if (of_device_is_compatible(pdev->dev.of_node, "amlogic,meson-uart"))
686 ret = meson_uart_probe_clocks_legacy(pdev, port);
687 else
688 ret = meson_uart_probe_clocks(pdev, port);
689
690 if (ret)
691 return ret;
ff7693d0 692
ff7693d0
CC		 693 port->iotype = UPIO_MEM;
694 port->mapbase = res_mem->start;
ff3b9cad 695 port->mapsize = resource_size(res_mem);
ff7693d0 696 port->irq = res_irq->start;
1b1ecaa6 697 port->flags = UPF_BOOT_AUTOCONF | UPF_LOW_LATENCY;
ff7693d0
CC		 698 port->dev = &pdev->dev;
699 port->line = pdev->id;
700 port->type = PORT_MESON;
701 port->x_char = 0;
702 port->ops = &meson_uart_ops;
703 port->fifosize = 64;
704
705 meson_ports[pdev->id] = port;
706 platform_set_drvdata(pdev, port);
707
00661dd8
BD		 708 /* reset port before registering (and possibly registering console) */
709 if (meson_uart_request_port(port) >= 0) {
710 meson_uart_reset(port);
711 meson_uart_release_port(port);
712 }
713
ff7693d0
CC		 714 ret = uart_add_one_port(&meson_uart_driver, port);
715 if (ret)
716 meson_ports[pdev->id] = NULL;
717
718 return ret;
719}
720
721static int meson_uart_remove(struct platform_device *pdev)
722{
723 struct uart_port *port;
724
725 port = platform_get_drvdata(pdev);
726 uart_remove_one_port(&meson_uart_driver, port);
727 meson_ports[pdev->id] = NULL;
728
729 return 0;
730}
731
ff7693d0 732static const struct of_device_id meson_uart_dt_match[] = {
9f60e0e7 733 /* Legacy bindings, should be removed when no more used */
ff7693d0 734 { .compatible = "amlogic,meson-uart" },
9f60e0e7
HK		 735 /* Stable bindings */
736 { .compatible = "amlogic,meson6-uart" },
737 { .compatible = "amlogic,meson8-uart" },
738 { .compatible = "amlogic,meson8b-uart" },
739 { .compatible = "amlogic,meson-gx-uart" },
ff7693d0
CC		 740 { /* sentinel */ },
741};
742MODULE_DEVICE_TABLE(of, meson_uart_dt_match);
743
744static struct platform_driver meson_uart_platform_driver = {
745 .probe = meson_uart_probe,
746 .remove = meson_uart_remove,
747 .driver = {
ff7693d0
CC		 748 .name = "meson_uart",
749 .of_match_table = meson_uart_dt_match,
750 },
751};
752
753static int __init meson_uart_init(void)
754{
755 int ret;
756
757 ret = uart_register_driver(&meson_uart_driver);
758 if (ret)
759 return ret;
760
761 ret = platform_driver_register(&meson_uart_platform_driver);
762 if (ret)
763 uart_unregister_driver(&meson_uart_driver);
764
765 return ret;
766}
767
768static void __exit meson_uart_exit(void)
769{
770 platform_driver_unregister(&meson_uart_platform_driver);
771 uart_unregister_driver(&meson_uart_driver);
772}
773
774module_init(meson_uart_init);
775module_exit(meson_uart_exit);
776
777MODULE_AUTHOR("Carlo Caione <carlo@caione.org>");
778MODULE_DESCRIPTION("Amlogic Meson serial port driver");
779MODULE_LICENSE("GPL v2");
Linux 6.x block layer and io_uring tree(s)