Commit | Line | Data |
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e3b3d0f5 | 1 | // SPDX-License-Identifier: GPL-2.0 |
ff7693d0 CC |
2 | /* |
3 | * Based on meson_uart.c, by AMLOGIC, INC. | |
4 | * | |
5 | * Copyright (C) 2014 Carlo Caione <carlo@caione.org> | |
ff7693d0 CC |
6 | */ |
7 | ||
b86ac225 YL |
8 | #if defined(CONFIG_SERIAL_MESON_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) |
9 | #define SUPPORT_SYSRQ | |
10 | #endif | |
11 | ||
ff7693d0 CC |
12 | #include <linux/clk.h> |
13 | #include <linux/console.h> | |
14 | #include <linux/delay.h> | |
15 | #include <linux/init.h> | |
16 | #include <linux/io.h> | |
17 | #include <linux/module.h> | |
18 | #include <linux/kernel.h> | |
19 | #include <linux/of.h> | |
20 | #include <linux/platform_device.h> | |
21 | #include <linux/serial.h> | |
22 | #include <linux/serial_core.h> | |
23 | #include <linux/tty.h> | |
24 | #include <linux/tty_flip.h> | |
25 | ||
26 | /* Register offsets */ | |
27 | #define AML_UART_WFIFO 0x00 | |
28 | #define AML_UART_RFIFO 0x04 | |
29 | #define AML_UART_CONTROL 0x08 | |
30 | #define AML_UART_STATUS 0x0c | |
31 | #define AML_UART_MISC 0x10 | |
32 | #define AML_UART_REG5 0x14 | |
33 | ||
34 | /* AML_UART_CONTROL bits */ | |
35 | #define AML_UART_TX_EN BIT(12) | |
36 | #define AML_UART_RX_EN BIT(13) | |
44137e40 | 37 | #define AML_UART_TWO_WIRE_EN BIT(15) |
f859722a MB |
38 | #define AML_UART_STOP_BIT_LEN_MASK (0x03 << 16) |
39 | #define AML_UART_STOP_BIT_1SB (0x00 << 16) | |
40 | #define AML_UART_STOP_BIT_2SB (0x01 << 16) | |
44137e40 MB |
41 | #define AML_UART_PARITY_TYPE BIT(18) |
42 | #define AML_UART_PARITY_EN BIT(19) | |
ff7693d0 CC |
43 | #define AML_UART_TX_RST BIT(22) |
44 | #define AML_UART_RX_RST BIT(23) | |
44137e40 | 45 | #define AML_UART_CLEAR_ERR BIT(24) |
ff7693d0 CC |
46 | #define AML_UART_RX_INT_EN BIT(27) |
47 | #define AML_UART_TX_INT_EN BIT(28) | |
48 | #define AML_UART_DATA_LEN_MASK (0x03 << 20) | |
49 | #define AML_UART_DATA_LEN_8BIT (0x00 << 20) | |
50 | #define AML_UART_DATA_LEN_7BIT (0x01 << 20) | |
51 | #define AML_UART_DATA_LEN_6BIT (0x02 << 20) | |
52 | #define AML_UART_DATA_LEN_5BIT (0x03 << 20) | |
53 | ||
54 | /* AML_UART_STATUS bits */ | |
55 | #define AML_UART_PARITY_ERR BIT(16) | |
56 | #define AML_UART_FRAME_ERR BIT(17) | |
57 | #define AML_UART_TX_FIFO_WERR BIT(18) | |
58 | #define AML_UART_RX_EMPTY BIT(20) | |
59 | #define AML_UART_TX_FULL BIT(21) | |
60 | #define AML_UART_TX_EMPTY BIT(22) | |
88679739 | 61 | #define AML_UART_XMIT_BUSY BIT(25) |
ff7693d0 CC |
62 | #define AML_UART_ERR (AML_UART_PARITY_ERR | \ |
63 | AML_UART_FRAME_ERR | \ | |
64 | AML_UART_TX_FIFO_WERR) | |
65 | ||
ff7693d0 CC |
66 | /* AML_UART_MISC bits */ |
67 | #define AML_UART_XMIT_IRQ(c) (((c) & 0xff) << 8) | |
68 | #define AML_UART_RECV_IRQ(c) ((c) & 0xff) | |
69 | ||
70 | /* AML_UART_REG5 bits */ | |
71 | #define AML_UART_BAUD_MASK 0x7fffff | |
72 | #define AML_UART_BAUD_USE BIT(23) | |
146f3808 | 73 | #define AML_UART_BAUD_XTAL BIT(24) |
ff7693d0 CC |
74 | |
75 | #define AML_UART_PORT_NUM 6 | |
76 | #define AML_UART_DEV_NAME "ttyAML" | |
77 | ||
78 | ||
79 | static struct uart_driver meson_uart_driver; | |
80 | ||
81 | static struct uart_port *meson_ports[AML_UART_PORT_NUM]; | |
82 | ||
83 | static void meson_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) | |
84 | { | |
85 | } | |
86 | ||
87 | static unsigned int meson_uart_get_mctrl(struct uart_port *port) | |
88 | { | |
89 | return TIOCM_CTS; | |
90 | } | |
91 | ||
92 | static unsigned int meson_uart_tx_empty(struct uart_port *port) | |
93 | { | |
94 | u32 val; | |
95 | ||
96 | val = readl(port->membase + AML_UART_STATUS); | |
88679739 BD |
97 | val &= (AML_UART_TX_EMPTY | AML_UART_XMIT_BUSY); |
98 | return (val == AML_UART_TX_EMPTY) ? TIOCSER_TEMT : 0; | |
ff7693d0 CC |
99 | } |
100 | ||
101 | static void meson_uart_stop_tx(struct uart_port *port) | |
102 | { | |
103 | u32 val; | |
104 | ||
105 | val = readl(port->membase + AML_UART_CONTROL); | |
855ddcab | 106 | val &= ~AML_UART_TX_INT_EN; |
ff7693d0 CC |
107 | writel(val, port->membase + AML_UART_CONTROL); |
108 | } | |
109 | ||
110 | static void meson_uart_stop_rx(struct uart_port *port) | |
111 | { | |
112 | u32 val; | |
113 | ||
114 | val = readl(port->membase + AML_UART_CONTROL); | |
115 | val &= ~AML_UART_RX_EN; | |
116 | writel(val, port->membase + AML_UART_CONTROL); | |
117 | } | |
118 | ||
119 | static void meson_uart_shutdown(struct uart_port *port) | |
120 | { | |
121 | unsigned long flags; | |
122 | u32 val; | |
123 | ||
124 | free_irq(port->irq, port); | |
125 | ||
126 | spin_lock_irqsave(&port->lock, flags); | |
127 | ||
128 | val = readl(port->membase + AML_UART_CONTROL); | |
855ddcab | 129 | val &= ~AML_UART_RX_EN; |
ff7693d0 CC |
130 | val &= ~(AML_UART_RX_INT_EN | AML_UART_TX_INT_EN); |
131 | writel(val, port->membase + AML_UART_CONTROL); | |
132 | ||
133 | spin_unlock_irqrestore(&port->lock, flags); | |
134 | } | |
135 | ||
136 | static void meson_uart_start_tx(struct uart_port *port) | |
137 | { | |
138 | struct circ_buf *xmit = &port->state->xmit; | |
139 | unsigned int ch; | |
f1dd05c8 | 140 | u32 val; |
ff7693d0 CC |
141 | |
142 | if (uart_tx_stopped(port)) { | |
143 | meson_uart_stop_tx(port); | |
144 | return; | |
145 | } | |
146 | ||
147 | while (!(readl(port->membase + AML_UART_STATUS) & AML_UART_TX_FULL)) { | |
148 | if (port->x_char) { | |
149 | writel(port->x_char, port->membase + AML_UART_WFIFO); | |
150 | port->icount.tx++; | |
151 | port->x_char = 0; | |
152 | continue; | |
153 | } | |
154 | ||
155 | if (uart_circ_empty(xmit)) | |
156 | break; | |
157 | ||
158 | ch = xmit->buf[xmit->tail]; | |
159 | writel(ch, port->membase + AML_UART_WFIFO); | |
160 | xmit->tail = (xmit->tail+1) & (SERIAL_XMIT_SIZE - 1); | |
161 | port->icount.tx++; | |
162 | } | |
163 | ||
f1dd05c8 BD |
164 | if (!uart_circ_empty(xmit)) { |
165 | val = readl(port->membase + AML_UART_CONTROL); | |
166 | val |= AML_UART_TX_INT_EN; | |
167 | writel(val, port->membase + AML_UART_CONTROL); | |
168 | } | |
169 | ||
ff7693d0 CC |
170 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) |
171 | uart_write_wakeup(port); | |
172 | } | |
173 | ||
174 | static void meson_receive_chars(struct uart_port *port) | |
175 | { | |
176 | struct tty_port *tport = &port->state->port; | |
177 | char flag; | |
b86ac225 | 178 | u32 ostatus, status, ch, mode; |
ff7693d0 CC |
179 | |
180 | do { | |
181 | flag = TTY_NORMAL; | |
182 | port->icount.rx++; | |
b86ac225 | 183 | ostatus = status = readl(port->membase + AML_UART_STATUS); |
ff7693d0 CC |
184 | |
185 | if (status & AML_UART_ERR) { | |
186 | if (status & AML_UART_TX_FIFO_WERR) | |
187 | port->icount.overrun++; | |
188 | else if (status & AML_UART_FRAME_ERR) | |
189 | port->icount.frame++; | |
190 | else if (status & AML_UART_PARITY_ERR) | |
191 | port->icount.frame++; | |
192 | ||
193 | mode = readl(port->membase + AML_UART_CONTROL); | |
194 | mode |= AML_UART_CLEAR_ERR; | |
195 | writel(mode, port->membase + AML_UART_CONTROL); | |
196 | ||
197 | /* It doesn't clear to 0 automatically */ | |
198 | mode &= ~AML_UART_CLEAR_ERR; | |
199 | writel(mode, port->membase + AML_UART_CONTROL); | |
200 | ||
201 | status &= port->read_status_mask; | |
202 | if (status & AML_UART_FRAME_ERR) | |
203 | flag = TTY_FRAME; | |
204 | else if (status & AML_UART_PARITY_ERR) | |
205 | flag = TTY_PARITY; | |
206 | } | |
207 | ||
208 | ch = readl(port->membase + AML_UART_RFIFO); | |
209 | ch &= 0xff; | |
210 | ||
b86ac225 YL |
211 | if ((ostatus & AML_UART_FRAME_ERR) && (ch == 0)) { |
212 | port->icount.brk++; | |
213 | flag = TTY_BREAK; | |
214 | if (uart_handle_break(port)) | |
215 | continue; | |
216 | } | |
217 | ||
218 | if (uart_handle_sysrq_char(port, ch)) | |
219 | continue; | |
220 | ||
ff7693d0 CC |
221 | if ((status & port->ignore_status_mask) == 0) |
222 | tty_insert_flip_char(tport, ch, flag); | |
223 | ||
224 | if (status & AML_UART_TX_FIFO_WERR) | |
225 | tty_insert_flip_char(tport, 0, TTY_OVERRUN); | |
226 | ||
227 | } while (!(readl(port->membase + AML_UART_STATUS) & AML_UART_RX_EMPTY)); | |
228 | ||
229 | spin_unlock(&port->lock); | |
230 | tty_flip_buffer_push(tport); | |
231 | spin_lock(&port->lock); | |
232 | } | |
233 | ||
234 | static irqreturn_t meson_uart_interrupt(int irq, void *dev_id) | |
235 | { | |
236 | struct uart_port *port = (struct uart_port *)dev_id; | |
237 | ||
238 | spin_lock(&port->lock); | |
239 | ||
240 | if (!(readl(port->membase + AML_UART_STATUS) & AML_UART_RX_EMPTY)) | |
241 | meson_receive_chars(port); | |
242 | ||
39469654 BD |
243 | if (!(readl(port->membase + AML_UART_STATUS) & AML_UART_TX_FULL)) { |
244 | if (readl(port->membase + AML_UART_CONTROL) & AML_UART_TX_INT_EN) | |
245 | meson_uart_start_tx(port); | |
246 | } | |
ff7693d0 CC |
247 | |
248 | spin_unlock(&port->lock); | |
249 | ||
250 | return IRQ_HANDLED; | |
251 | } | |
252 | ||
253 | static const char *meson_uart_type(struct uart_port *port) | |
254 | { | |
255 | return (port->type == PORT_MESON) ? "meson_uart" : NULL; | |
256 | } | |
257 | ||
00661dd8 | 258 | static void meson_uart_reset(struct uart_port *port) |
ff7693d0 CC |
259 | { |
260 | u32 val; | |
ff7693d0 CC |
261 | |
262 | val = readl(port->membase + AML_UART_CONTROL); | |
c0f0b8c5 | 263 | val |= (AML_UART_RX_RST | AML_UART_TX_RST | AML_UART_CLEAR_ERR); |
ff7693d0 CC |
264 | writel(val, port->membase + AML_UART_CONTROL); |
265 | ||
c0f0b8c5 | 266 | val &= ~(AML_UART_RX_RST | AML_UART_TX_RST | AML_UART_CLEAR_ERR); |
ff7693d0 | 267 | writel(val, port->membase + AML_UART_CONTROL); |
00661dd8 BD |
268 | } |
269 | ||
270 | static int meson_uart_startup(struct uart_port *port) | |
271 | { | |
272 | u32 val; | |
273 | int ret = 0; | |
274 | ||
275 | val = readl(port->membase + AML_UART_CONTROL); | |
c0f0b8c5 | 276 | val |= AML_UART_CLEAR_ERR; |
00661dd8 | 277 | writel(val, port->membase + AML_UART_CONTROL); |
c0f0b8c5 | 278 | val &= ~AML_UART_CLEAR_ERR; |
00661dd8 | 279 | writel(val, port->membase + AML_UART_CONTROL); |
ff7693d0 CC |
280 | |
281 | val |= (AML_UART_RX_EN | AML_UART_TX_EN); | |
282 | writel(val, port->membase + AML_UART_CONTROL); | |
283 | ||
284 | val |= (AML_UART_RX_INT_EN | AML_UART_TX_INT_EN); | |
285 | writel(val, port->membase + AML_UART_CONTROL); | |
286 | ||
287 | val = (AML_UART_RECV_IRQ(1) | AML_UART_XMIT_IRQ(port->fifosize / 2)); | |
288 | writel(val, port->membase + AML_UART_MISC); | |
289 | ||
290 | ret = request_irq(port->irq, meson_uart_interrupt, 0, | |
8b7a6b2b | 291 | port->name, port); |
ff7693d0 CC |
292 | |
293 | return ret; | |
294 | } | |
295 | ||
296 | static void meson_uart_change_speed(struct uart_port *port, unsigned long baud) | |
297 | { | |
298 | u32 val; | |
299 | ||
f1f5c140 | 300 | while (!meson_uart_tx_empty(port)) |
ff7693d0 CC |
301 | cpu_relax(); |
302 | ||
146f3808 AF |
303 | if (port->uartclk == 24000000) { |
304 | val = ((port->uartclk / 3) / baud) - 1; | |
305 | val |= AML_UART_BAUD_XTAL; | |
306 | } else { | |
307 | val = ((port->uartclk * 10 / (baud * 4) + 5) / 10) - 1; | |
308 | } | |
ff7693d0 CC |
309 | val |= AML_UART_BAUD_USE; |
310 | writel(val, port->membase + AML_UART_REG5); | |
311 | } | |
312 | ||
313 | static void meson_uart_set_termios(struct uart_port *port, | |
314 | struct ktermios *termios, | |
315 | struct ktermios *old) | |
316 | { | |
317 | unsigned int cflags, iflags, baud; | |
318 | unsigned long flags; | |
319 | u32 val; | |
320 | ||
321 | spin_lock_irqsave(&port->lock, flags); | |
322 | ||
323 | cflags = termios->c_cflag; | |
324 | iflags = termios->c_iflag; | |
325 | ||
326 | val = readl(port->membase + AML_UART_CONTROL); | |
327 | ||
328 | val &= ~AML_UART_DATA_LEN_MASK; | |
329 | switch (cflags & CSIZE) { | |
330 | case CS8: | |
331 | val |= AML_UART_DATA_LEN_8BIT; | |
332 | break; | |
333 | case CS7: | |
334 | val |= AML_UART_DATA_LEN_7BIT; | |
335 | break; | |
336 | case CS6: | |
337 | val |= AML_UART_DATA_LEN_6BIT; | |
338 | break; | |
339 | case CS5: | |
340 | val |= AML_UART_DATA_LEN_5BIT; | |
341 | break; | |
342 | } | |
343 | ||
344 | if (cflags & PARENB) | |
345 | val |= AML_UART_PARITY_EN; | |
346 | else | |
347 | val &= ~AML_UART_PARITY_EN; | |
348 | ||
349 | if (cflags & PARODD) | |
350 | val |= AML_UART_PARITY_TYPE; | |
351 | else | |
352 | val &= ~AML_UART_PARITY_TYPE; | |
353 | ||
f859722a | 354 | val &= ~AML_UART_STOP_BIT_LEN_MASK; |
ff7693d0 | 355 | if (cflags & CSTOPB) |
f859722a | 356 | val |= AML_UART_STOP_BIT_2SB; |
ff7693d0 | 357 | else |
f859722a | 358 | val |= AML_UART_STOP_BIT_1SB; |
ff7693d0 CC |
359 | |
360 | if (cflags & CRTSCTS) | |
361 | val &= ~AML_UART_TWO_WIRE_EN; | |
362 | else | |
363 | val |= AML_UART_TWO_WIRE_EN; | |
364 | ||
365 | writel(val, port->membase + AML_UART_CONTROL); | |
366 | ||
9b11f19e | 367 | baud = uart_get_baud_rate(port, termios, old, 50, 4000000); |
ff7693d0 CC |
368 | meson_uart_change_speed(port, baud); |
369 | ||
370 | port->read_status_mask = AML_UART_TX_FIFO_WERR; | |
371 | if (iflags & INPCK) | |
372 | port->read_status_mask |= AML_UART_PARITY_ERR | | |
373 | AML_UART_FRAME_ERR; | |
374 | ||
375 | port->ignore_status_mask = 0; | |
376 | if (iflags & IGNPAR) | |
377 | port->ignore_status_mask |= AML_UART_PARITY_ERR | | |
378 | AML_UART_FRAME_ERR; | |
379 | ||
380 | uart_update_timeout(port, termios->c_cflag, baud); | |
381 | spin_unlock_irqrestore(&port->lock, flags); | |
382 | } | |
383 | ||
384 | static int meson_uart_verify_port(struct uart_port *port, | |
385 | struct serial_struct *ser) | |
386 | { | |
387 | int ret = 0; | |
388 | ||
389 | if (port->type != PORT_MESON) | |
390 | ret = -EINVAL; | |
391 | if (port->irq != ser->irq) | |
392 | ret = -EINVAL; | |
393 | if (ser->baud_base < 9600) | |
394 | ret = -EINVAL; | |
395 | return ret; | |
396 | } | |
397 | ||
398 | static void meson_uart_release_port(struct uart_port *port) | |
399 | { | |
1b1ecaa6 HK |
400 | devm_iounmap(port->dev, port->membase); |
401 | port->membase = NULL; | |
402 | devm_release_mem_region(port->dev, port->mapbase, port->mapsize); | |
ff7693d0 CC |
403 | } |
404 | ||
405 | static int meson_uart_request_port(struct uart_port *port) | |
406 | { | |
ff3b9cad | 407 | if (!devm_request_mem_region(port->dev, port->mapbase, port->mapsize, |
ff7693d0 CC |
408 | dev_name(port->dev))) { |
409 | dev_err(port->dev, "Memory region busy\n"); | |
410 | return -EBUSY; | |
411 | } | |
412 | ||
1b1ecaa6 HK |
413 | port->membase = devm_ioremap_nocache(port->dev, port->mapbase, |
414 | port->mapsize); | |
415 | if (!port->membase) | |
416 | return -ENOMEM; | |
ff7693d0 CC |
417 | |
418 | return 0; | |
419 | } | |
420 | ||
421 | static void meson_uart_config_port(struct uart_port *port, int flags) | |
422 | { | |
423 | if (flags & UART_CONFIG_TYPE) { | |
424 | port->type = PORT_MESON; | |
425 | meson_uart_request_port(port); | |
426 | } | |
427 | } | |
428 | ||
921469f7 | 429 | static const struct uart_ops meson_uart_ops = { |
ff7693d0 CC |
430 | .set_mctrl = meson_uart_set_mctrl, |
431 | .get_mctrl = meson_uart_get_mctrl, | |
432 | .tx_empty = meson_uart_tx_empty, | |
433 | .start_tx = meson_uart_start_tx, | |
434 | .stop_tx = meson_uart_stop_tx, | |
435 | .stop_rx = meson_uart_stop_rx, | |
436 | .startup = meson_uart_startup, | |
437 | .shutdown = meson_uart_shutdown, | |
438 | .set_termios = meson_uart_set_termios, | |
439 | .type = meson_uart_type, | |
440 | .config_port = meson_uart_config_port, | |
441 | .request_port = meson_uart_request_port, | |
442 | .release_port = meson_uart_release_port, | |
443 | .verify_port = meson_uart_verify_port, | |
444 | }; | |
445 | ||
446 | #ifdef CONFIG_SERIAL_MESON_CONSOLE | |
5fa4accf AB |
447 | static void meson_uart_enable_tx_engine(struct uart_port *port) |
448 | { | |
449 | u32 val; | |
450 | ||
451 | val = readl(port->membase + AML_UART_CONTROL); | |
452 | val |= AML_UART_TX_EN; | |
453 | writel(val, port->membase + AML_UART_CONTROL); | |
454 | } | |
ff7693d0 CC |
455 | |
456 | static void meson_console_putchar(struct uart_port *port, int ch) | |
457 | { | |
458 | if (!port->membase) | |
459 | return; | |
460 | ||
461 | while (readl(port->membase + AML_UART_STATUS) & AML_UART_TX_FULL) | |
462 | cpu_relax(); | |
463 | writel(ch, port->membase + AML_UART_WFIFO); | |
464 | } | |
465 | ||
736d5538 AF |
466 | static void meson_serial_port_write(struct uart_port *port, const char *s, |
467 | u_int count) | |
ff7693d0 | 468 | { |
ff7693d0 CC |
469 | unsigned long flags; |
470 | int locked; | |
2561f068 | 471 | u32 val, tmp; |
ff7693d0 | 472 | |
ff7693d0 CC |
473 | local_irq_save(flags); |
474 | if (port->sysrq) { | |
475 | locked = 0; | |
476 | } else if (oops_in_progress) { | |
477 | locked = spin_trylock(&port->lock); | |
478 | } else { | |
479 | spin_lock(&port->lock); | |
480 | locked = 1; | |
481 | } | |
482 | ||
41788f05 | 483 | val = readl(port->membase + AML_UART_CONTROL); |
2561f068 BD |
484 | tmp = val & ~(AML_UART_TX_INT_EN | AML_UART_RX_INT_EN); |
485 | writel(tmp, port->membase + AML_UART_CONTROL); | |
41788f05 | 486 | |
ff7693d0 | 487 | uart_console_write(port, s, count, meson_console_putchar); |
2561f068 | 488 | writel(val, port->membase + AML_UART_CONTROL); |
ff7693d0 CC |
489 | |
490 | if (locked) | |
491 | spin_unlock(&port->lock); | |
492 | local_irq_restore(flags); | |
493 | } | |
494 | ||
736d5538 AF |
495 | static void meson_serial_console_write(struct console *co, const char *s, |
496 | u_int count) | |
497 | { | |
498 | struct uart_port *port; | |
499 | ||
500 | port = meson_ports[co->index]; | |
501 | if (!port) | |
502 | return; | |
503 | ||
504 | meson_serial_port_write(port, s, count); | |
505 | } | |
506 | ||
ff7693d0 CC |
507 | static int meson_serial_console_setup(struct console *co, char *options) |
508 | { | |
509 | struct uart_port *port; | |
510 | int baud = 115200; | |
511 | int bits = 8; | |
512 | int parity = 'n'; | |
513 | int flow = 'n'; | |
514 | ||
515 | if (co->index < 0 || co->index >= AML_UART_PORT_NUM) | |
516 | return -EINVAL; | |
517 | ||
518 | port = meson_ports[co->index]; | |
519 | if (!port || !port->membase) | |
520 | return -ENODEV; | |
521 | ||
ba50f1df HK |
522 | meson_uart_enable_tx_engine(port); |
523 | ||
ff7693d0 CC |
524 | if (options) |
525 | uart_parse_options(options, &baud, &parity, &bits, &flow); | |
526 | ||
527 | return uart_set_options(port, co, baud, parity, bits, flow); | |
528 | } | |
529 | ||
530 | static struct console meson_serial_console = { | |
531 | .name = AML_UART_DEV_NAME, | |
532 | .write = meson_serial_console_write, | |
533 | .device = uart_console_device, | |
534 | .setup = meson_serial_console_setup, | |
535 | .flags = CON_PRINTBUFFER, | |
536 | .index = -1, | |
537 | .data = &meson_uart_driver, | |
538 | }; | |
539 | ||
540 | static int __init meson_serial_console_init(void) | |
541 | { | |
542 | register_console(&meson_serial_console); | |
543 | return 0; | |
544 | } | |
545 | console_initcall(meson_serial_console_init); | |
546 | ||
736d5538 AF |
547 | static void meson_serial_early_console_write(struct console *co, |
548 | const char *s, | |
549 | u_int count) | |
550 | { | |
551 | struct earlycon_device *dev = co->data; | |
552 | ||
553 | meson_serial_port_write(&dev->port, s, count); | |
554 | } | |
555 | ||
556 | static int __init | |
557 | meson_serial_early_console_setup(struct earlycon_device *device, const char *opt) | |
558 | { | |
559 | if (!device->port.membase) | |
560 | return -ENODEV; | |
561 | ||
ba50f1df | 562 | meson_uart_enable_tx_engine(&device->port); |
736d5538 AF |
563 | device->con->write = meson_serial_early_console_write; |
564 | return 0; | |
565 | } | |
9f60e0e7 | 566 | /* Legacy bindings, should be removed when no more used */ |
736d5538 AF |
567 | OF_EARLYCON_DECLARE(meson, "amlogic,meson-uart", |
568 | meson_serial_early_console_setup); | |
9f60e0e7 HK |
569 | /* Stable bindings */ |
570 | OF_EARLYCON_DECLARE(meson, "amlogic,meson-ao-uart", | |
571 | meson_serial_early_console_setup); | |
736d5538 | 572 | |
ff7693d0 CC |
573 | #define MESON_SERIAL_CONSOLE (&meson_serial_console) |
574 | #else | |
575 | #define MESON_SERIAL_CONSOLE NULL | |
576 | #endif | |
577 | ||
578 | static struct uart_driver meson_uart_driver = { | |
579 | .owner = THIS_MODULE, | |
580 | .driver_name = "meson_uart", | |
581 | .dev_name = AML_UART_DEV_NAME, | |
582 | .nr = AML_UART_PORT_NUM, | |
583 | .cons = MESON_SERIAL_CONSOLE, | |
584 | }; | |
585 | ||
9f60e0e7 HK |
586 | static inline struct clk *meson_uart_probe_clock(struct device *dev, |
587 | const char *id) | |
588 | { | |
589 | struct clk *clk = NULL; | |
590 | int ret; | |
591 | ||
592 | clk = devm_clk_get(dev, id); | |
593 | if (IS_ERR(clk)) | |
594 | return clk; | |
595 | ||
596 | ret = clk_prepare_enable(clk); | |
597 | if (ret) { | |
598 | dev_err(dev, "couldn't enable clk\n"); | |
599 | return ERR_PTR(ret); | |
600 | } | |
601 | ||
602 | devm_add_action_or_reset(dev, | |
603 | (void(*)(void *))clk_disable_unprepare, | |
604 | clk); | |
605 | ||
606 | return clk; | |
607 | } | |
608 | ||
609 | /* | |
610 | * This function gets clocks in the legacy non-stable DT bindings. | |
611 | * This code will be remove once all the platforms switch to the | |
612 | * new DT bindings. | |
613 | */ | |
614 | static int meson_uart_probe_clocks_legacy(struct platform_device *pdev, | |
615 | struct uart_port *port) | |
616 | { | |
617 | struct clk *clk = NULL; | |
618 | ||
619 | clk = meson_uart_probe_clock(&pdev->dev, NULL); | |
620 | if (IS_ERR(clk)) | |
621 | return PTR_ERR(clk); | |
622 | ||
623 | port->uartclk = clk_get_rate(clk); | |
624 | ||
625 | return 0; | |
626 | } | |
627 | ||
628 | static int meson_uart_probe_clocks(struct platform_device *pdev, | |
629 | struct uart_port *port) | |
630 | { | |
631 | struct clk *clk_xtal = NULL; | |
632 | struct clk *clk_pclk = NULL; | |
633 | struct clk *clk_baud = NULL; | |
634 | ||
635 | clk_pclk = meson_uart_probe_clock(&pdev->dev, "pclk"); | |
636 | if (IS_ERR(clk_pclk)) | |
637 | return PTR_ERR(clk_pclk); | |
638 | ||
639 | clk_xtal = meson_uart_probe_clock(&pdev->dev, "xtal"); | |
640 | if (IS_ERR(clk_xtal)) | |
641 | return PTR_ERR(clk_xtal); | |
642 | ||
643 | clk_baud = meson_uart_probe_clock(&pdev->dev, "baud"); | |
644 | if (IS_ERR(clk_baud)) | |
645 | return PTR_ERR(clk_baud); | |
646 | ||
647 | port->uartclk = clk_get_rate(clk_baud); | |
648 | ||
649 | return 0; | |
650 | } | |
651 | ||
ff7693d0 CC |
652 | static int meson_uart_probe(struct platform_device *pdev) |
653 | { | |
654 | struct resource *res_mem, *res_irq; | |
655 | struct uart_port *port; | |
ff7693d0 CC |
656 | int ret = 0; |
657 | ||
658 | if (pdev->dev.of_node) | |
659 | pdev->id = of_alias_get_id(pdev->dev.of_node, "serial"); | |
660 | ||
661 | if (pdev->id < 0 || pdev->id >= AML_UART_PORT_NUM) | |
662 | return -EINVAL; | |
663 | ||
664 | res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
665 | if (!res_mem) | |
666 | return -ENODEV; | |
667 | ||
668 | res_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); | |
669 | if (!res_irq) | |
670 | return -ENODEV; | |
671 | ||
672 | if (meson_ports[pdev->id]) { | |
673 | dev_err(&pdev->dev, "port %d already allocated\n", pdev->id); | |
674 | return -EBUSY; | |
675 | } | |
676 | ||
677 | port = devm_kzalloc(&pdev->dev, sizeof(struct uart_port), GFP_KERNEL); | |
678 | if (!port) | |
679 | return -ENOMEM; | |
680 | ||
9f60e0e7 HK |
681 | /* Use legacy way until all platforms switch to new bindings */ |
682 | if (of_device_is_compatible(pdev->dev.of_node, "amlogic,meson-uart")) | |
683 | ret = meson_uart_probe_clocks_legacy(pdev, port); | |
684 | else | |
685 | ret = meson_uart_probe_clocks(pdev, port); | |
686 | ||
687 | if (ret) | |
688 | return ret; | |
ff7693d0 | 689 | |
ff7693d0 CC |
690 | port->iotype = UPIO_MEM; |
691 | port->mapbase = res_mem->start; | |
ff3b9cad | 692 | port->mapsize = resource_size(res_mem); |
ff7693d0 | 693 | port->irq = res_irq->start; |
1b1ecaa6 | 694 | port->flags = UPF_BOOT_AUTOCONF | UPF_LOW_LATENCY; |
ff7693d0 CC |
695 | port->dev = &pdev->dev; |
696 | port->line = pdev->id; | |
697 | port->type = PORT_MESON; | |
698 | port->x_char = 0; | |
699 | port->ops = &meson_uart_ops; | |
700 | port->fifosize = 64; | |
701 | ||
702 | meson_ports[pdev->id] = port; | |
703 | platform_set_drvdata(pdev, port); | |
704 | ||
00661dd8 BD |
705 | /* reset port before registering (and possibly registering console) */ |
706 | if (meson_uart_request_port(port) >= 0) { | |
707 | meson_uart_reset(port); | |
708 | meson_uart_release_port(port); | |
709 | } | |
710 | ||
ff7693d0 CC |
711 | ret = uart_add_one_port(&meson_uart_driver, port); |
712 | if (ret) | |
713 | meson_ports[pdev->id] = NULL; | |
714 | ||
715 | return ret; | |
716 | } | |
717 | ||
718 | static int meson_uart_remove(struct platform_device *pdev) | |
719 | { | |
720 | struct uart_port *port; | |
721 | ||
722 | port = platform_get_drvdata(pdev); | |
723 | uart_remove_one_port(&meson_uart_driver, port); | |
724 | meson_ports[pdev->id] = NULL; | |
725 | ||
726 | return 0; | |
727 | } | |
728 | ||
ff7693d0 | 729 | static const struct of_device_id meson_uart_dt_match[] = { |
9f60e0e7 | 730 | /* Legacy bindings, should be removed when no more used */ |
ff7693d0 | 731 | { .compatible = "amlogic,meson-uart" }, |
9f60e0e7 HK |
732 | /* Stable bindings */ |
733 | { .compatible = "amlogic,meson6-uart" }, | |
734 | { .compatible = "amlogic,meson8-uart" }, | |
735 | { .compatible = "amlogic,meson8b-uart" }, | |
736 | { .compatible = "amlogic,meson-gx-uart" }, | |
ff7693d0 CC |
737 | { /* sentinel */ }, |
738 | }; | |
739 | MODULE_DEVICE_TABLE(of, meson_uart_dt_match); | |
740 | ||
741 | static struct platform_driver meson_uart_platform_driver = { | |
742 | .probe = meson_uart_probe, | |
743 | .remove = meson_uart_remove, | |
744 | .driver = { | |
ff7693d0 CC |
745 | .name = "meson_uart", |
746 | .of_match_table = meson_uart_dt_match, | |
747 | }, | |
748 | }; | |
749 | ||
750 | static int __init meson_uart_init(void) | |
751 | { | |
752 | int ret; | |
753 | ||
754 | ret = uart_register_driver(&meson_uart_driver); | |
755 | if (ret) | |
756 | return ret; | |
757 | ||
758 | ret = platform_driver_register(&meson_uart_platform_driver); | |
759 | if (ret) | |
760 | uart_unregister_driver(&meson_uart_driver); | |
761 | ||
762 | return ret; | |
763 | } | |
764 | ||
765 | static void __exit meson_uart_exit(void) | |
766 | { | |
767 | platform_driver_unregister(&meson_uart_platform_driver); | |
768 | uart_unregister_driver(&meson_uart_driver); | |
769 | } | |
770 | ||
771 | module_init(meson_uart_init); | |
772 | module_exit(meson_uart_exit); | |
773 | ||
774 | MODULE_AUTHOR("Carlo Caione <carlo@caione.org>"); | |
775 | MODULE_DESCRIPTION("Amlogic Meson serial port driver"); | |
776 | MODULE_LICENSE("GPL v2"); |