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f6544418 AS |
1 | /* |
2 | * Maxim (Dallas) MAX3107/8 serial driver | |
3 | * | |
10d8b34a | 4 | * Copyright (C) 2012-2013 Alexander Shiyan <shc_work@mail.ru> |
f6544418 AS |
5 | * |
6 | * Based on max3100.c, by Christian Pellegrin <chripell@evolware.org> | |
7 | * Based on max3110.c, by Feng Tang <feng.tang@intel.com> | |
8 | * Based on max3107.c, by Aavamobile | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; either version 2 of the License, or | |
13 | * (at your option) any later version. | |
14 | */ | |
15 | ||
16 | /* TODO: MAX3109 support (Dual) */ | |
17 | /* TODO: MAX14830 support (Quad) */ | |
18 | ||
19 | #include <linux/module.h> | |
10d8b34a | 20 | #include <linux/delay.h> |
f6544418 | 21 | #include <linux/device.h> |
10d8b34a | 22 | #include <linux/bitops.h> |
f6544418 AS |
23 | #include <linux/serial_core.h> |
24 | #include <linux/serial.h> | |
25 | #include <linux/tty.h> | |
26 | #include <linux/tty_flip.h> | |
27 | #include <linux/regmap.h> | |
28 | #include <linux/gpio.h> | |
29 | #include <linux/spi/spi.h> | |
10d8b34a | 30 | |
f6544418 AS |
31 | #include <linux/platform_data/max310x.h> |
32 | ||
10d8b34a | 33 | #define MAX310X_NAME "max310x" |
f6544418 AS |
34 | #define MAX310X_MAJOR 204 |
35 | #define MAX310X_MINOR 209 | |
36 | ||
37 | /* MAX310X register definitions */ | |
38 | #define MAX310X_RHR_REG (0x00) /* RX FIFO */ | |
39 | #define MAX310X_THR_REG (0x00) /* TX FIFO */ | |
40 | #define MAX310X_IRQEN_REG (0x01) /* IRQ enable */ | |
41 | #define MAX310X_IRQSTS_REG (0x02) /* IRQ status */ | |
42 | #define MAX310X_LSR_IRQEN_REG (0x03) /* LSR IRQ enable */ | |
43 | #define MAX310X_LSR_IRQSTS_REG (0x04) /* LSR IRQ status */ | |
10d8b34a AS |
44 | #define MAX310X_REG_05 (0x05) |
45 | #define MAX310X_SPCHR_IRQEN_REG MAX310X_REG_05 /* Special char IRQ en */ | |
f6544418 AS |
46 | #define MAX310X_SPCHR_IRQSTS_REG (0x06) /* Special char IRQ status */ |
47 | #define MAX310X_STS_IRQEN_REG (0x07) /* Status IRQ enable */ | |
48 | #define MAX310X_STS_IRQSTS_REG (0x08) /* Status IRQ status */ | |
49 | #define MAX310X_MODE1_REG (0x09) /* MODE1 */ | |
50 | #define MAX310X_MODE2_REG (0x0a) /* MODE2 */ | |
51 | #define MAX310X_LCR_REG (0x0b) /* LCR */ | |
52 | #define MAX310X_RXTO_REG (0x0c) /* RX timeout */ | |
53 | #define MAX310X_HDPIXDELAY_REG (0x0d) /* Auto transceiver delays */ | |
54 | #define MAX310X_IRDA_REG (0x0e) /* IRDA settings */ | |
55 | #define MAX310X_FLOWLVL_REG (0x0f) /* Flow control levels */ | |
56 | #define MAX310X_FIFOTRIGLVL_REG (0x10) /* FIFO IRQ trigger levels */ | |
57 | #define MAX310X_TXFIFOLVL_REG (0x11) /* TX FIFO level */ | |
58 | #define MAX310X_RXFIFOLVL_REG (0x12) /* RX FIFO level */ | |
59 | #define MAX310X_FLOWCTRL_REG (0x13) /* Flow control */ | |
60 | #define MAX310X_XON1_REG (0x14) /* XON1 character */ | |
61 | #define MAX310X_XON2_REG (0x15) /* XON2 character */ | |
62 | #define MAX310X_XOFF1_REG (0x16) /* XOFF1 character */ | |
63 | #define MAX310X_XOFF2_REG (0x17) /* XOFF2 character */ | |
64 | #define MAX310X_GPIOCFG_REG (0x18) /* GPIO config */ | |
65 | #define MAX310X_GPIODATA_REG (0x19) /* GPIO data */ | |
66 | #define MAX310X_PLLCFG_REG (0x1a) /* PLL config */ | |
67 | #define MAX310X_BRGCFG_REG (0x1b) /* Baud rate generator conf */ | |
68 | #define MAX310X_BRGDIVLSB_REG (0x1c) /* Baud rate divisor LSB */ | |
69 | #define MAX310X_BRGDIVMSB_REG (0x1d) /* Baud rate divisor MSB */ | |
70 | #define MAX310X_CLKSRC_REG (0x1e) /* Clock source */ | |
10d8b34a AS |
71 | #define MAX310X_REG_1F (0x1f) |
72 | ||
73 | #define MAX310X_REVID_REG MAX310X_REG_1F /* Revision ID */ | |
74 | ||
75 | #define MAX310X_GLOBALIRQ_REG MAX310X_REG_1F /* Global IRQ (RO) */ | |
76 | #define MAX310X_GLOBALCMD_REG MAX310X_REG_1F /* Global Command (WO) */ | |
77 | ||
78 | /* Extended registers */ | |
79 | #define MAX310X_REVID_EXTREG MAX310X_REG_05 /* Revision ID */ | |
f6544418 AS |
80 | |
81 | /* IRQ register bits */ | |
82 | #define MAX310X_IRQ_LSR_BIT (1 << 0) /* LSR interrupt */ | |
83 | #define MAX310X_IRQ_SPCHR_BIT (1 << 1) /* Special char interrupt */ | |
84 | #define MAX310X_IRQ_STS_BIT (1 << 2) /* Status interrupt */ | |
85 | #define MAX310X_IRQ_RXFIFO_BIT (1 << 3) /* RX FIFO interrupt */ | |
86 | #define MAX310X_IRQ_TXFIFO_BIT (1 << 4) /* TX FIFO interrupt */ | |
87 | #define MAX310X_IRQ_TXEMPTY_BIT (1 << 5) /* TX FIFO empty interrupt */ | |
88 | #define MAX310X_IRQ_RXEMPTY_BIT (1 << 6) /* RX FIFO empty interrupt */ | |
89 | #define MAX310X_IRQ_CTS_BIT (1 << 7) /* CTS interrupt */ | |
90 | ||
91 | /* LSR register bits */ | |
92 | #define MAX310X_LSR_RXTO_BIT (1 << 0) /* RX timeout */ | |
93 | #define MAX310X_LSR_RXOVR_BIT (1 << 1) /* RX overrun */ | |
94 | #define MAX310X_LSR_RXPAR_BIT (1 << 2) /* RX parity error */ | |
95 | #define MAX310X_LSR_FRERR_BIT (1 << 3) /* Frame error */ | |
96 | #define MAX310X_LSR_RXBRK_BIT (1 << 4) /* RX break */ | |
97 | #define MAX310X_LSR_RXNOISE_BIT (1 << 5) /* RX noise */ | |
98 | #define MAX310X_LSR_CTS_BIT (1 << 7) /* CTS pin state */ | |
99 | ||
100 | /* Special character register bits */ | |
101 | #define MAX310X_SPCHR_XON1_BIT (1 << 0) /* XON1 character */ | |
102 | #define MAX310X_SPCHR_XON2_BIT (1 << 1) /* XON2 character */ | |
103 | #define MAX310X_SPCHR_XOFF1_BIT (1 << 2) /* XOFF1 character */ | |
104 | #define MAX310X_SPCHR_XOFF2_BIT (1 << 3) /* XOFF2 character */ | |
105 | #define MAX310X_SPCHR_BREAK_BIT (1 << 4) /* RX break */ | |
106 | #define MAX310X_SPCHR_MULTIDROP_BIT (1 << 5) /* 9-bit multidrop addr char */ | |
107 | ||
108 | /* Status register bits */ | |
109 | #define MAX310X_STS_GPIO0_BIT (1 << 0) /* GPIO 0 interrupt */ | |
110 | #define MAX310X_STS_GPIO1_BIT (1 << 1) /* GPIO 1 interrupt */ | |
111 | #define MAX310X_STS_GPIO2_BIT (1 << 2) /* GPIO 2 interrupt */ | |
112 | #define MAX310X_STS_GPIO3_BIT (1 << 3) /* GPIO 3 interrupt */ | |
113 | #define MAX310X_STS_CLKREADY_BIT (1 << 5) /* Clock ready */ | |
114 | #define MAX310X_STS_SLEEP_BIT (1 << 6) /* Sleep interrupt */ | |
115 | ||
116 | /* MODE1 register bits */ | |
117 | #define MAX310X_MODE1_RXDIS_BIT (1 << 0) /* RX disable */ | |
118 | #define MAX310X_MODE1_TXDIS_BIT (1 << 1) /* TX disable */ | |
119 | #define MAX310X_MODE1_TXHIZ_BIT (1 << 2) /* TX pin three-state */ | |
120 | #define MAX310X_MODE1_RTSHIZ_BIT (1 << 3) /* RTS pin three-state */ | |
121 | #define MAX310X_MODE1_TRNSCVCTRL_BIT (1 << 4) /* Transceiver ctrl enable */ | |
122 | #define MAX310X_MODE1_FORCESLEEP_BIT (1 << 5) /* Force sleep mode */ | |
123 | #define MAX310X_MODE1_AUTOSLEEP_BIT (1 << 6) /* Auto sleep enable */ | |
124 | #define MAX310X_MODE1_IRQSEL_BIT (1 << 7) /* IRQ pin enable */ | |
125 | ||
126 | /* MODE2 register bits */ | |
127 | #define MAX310X_MODE2_RST_BIT (1 << 0) /* Chip reset */ | |
128 | #define MAX310X_MODE2_FIFORST_BIT (1 << 1) /* FIFO reset */ | |
129 | #define MAX310X_MODE2_RXTRIGINV_BIT (1 << 2) /* RX FIFO INT invert */ | |
130 | #define MAX310X_MODE2_RXEMPTINV_BIT (1 << 3) /* RX FIFO empty INT invert */ | |
131 | #define MAX310X_MODE2_SPCHR_BIT (1 << 4) /* Special chr detect enable */ | |
132 | #define MAX310X_MODE2_LOOPBACK_BIT (1 << 5) /* Internal loopback enable */ | |
133 | #define MAX310X_MODE2_MULTIDROP_BIT (1 << 6) /* 9-bit multidrop enable */ | |
134 | #define MAX310X_MODE2_ECHOSUPR_BIT (1 << 7) /* ECHO suppression enable */ | |
135 | ||
136 | /* LCR register bits */ | |
137 | #define MAX310X_LCR_LENGTH0_BIT (1 << 0) /* Word length bit 0 */ | |
138 | #define MAX310X_LCR_LENGTH1_BIT (1 << 1) /* Word length bit 1 | |
139 | * | |
140 | * Word length bits table: | |
141 | * 00 -> 5 bit words | |
142 | * 01 -> 6 bit words | |
143 | * 10 -> 7 bit words | |
144 | * 11 -> 8 bit words | |
145 | */ | |
146 | #define MAX310X_LCR_STOPLEN_BIT (1 << 2) /* STOP length bit | |
147 | * | |
148 | * STOP length bit table: | |
149 | * 0 -> 1 stop bit | |
150 | * 1 -> 1-1.5 stop bits if | |
151 | * word length is 5, | |
152 | * 2 stop bits otherwise | |
153 | */ | |
154 | #define MAX310X_LCR_PARITY_BIT (1 << 3) /* Parity bit enable */ | |
155 | #define MAX310X_LCR_EVENPARITY_BIT (1 << 4) /* Even parity bit enable */ | |
156 | #define MAX310X_LCR_FORCEPARITY_BIT (1 << 5) /* 9-bit multidrop parity */ | |
157 | #define MAX310X_LCR_TXBREAK_BIT (1 << 6) /* TX break enable */ | |
158 | #define MAX310X_LCR_RTS_BIT (1 << 7) /* RTS pin control */ | |
159 | #define MAX310X_LCR_WORD_LEN_5 (0x00) | |
160 | #define MAX310X_LCR_WORD_LEN_6 (0x01) | |
161 | #define MAX310X_LCR_WORD_LEN_7 (0x02) | |
162 | #define MAX310X_LCR_WORD_LEN_8 (0x03) | |
163 | ||
164 | /* IRDA register bits */ | |
165 | #define MAX310X_IRDA_IRDAEN_BIT (1 << 0) /* IRDA mode enable */ | |
166 | #define MAX310X_IRDA_SIR_BIT (1 << 1) /* SIR mode enable */ | |
167 | #define MAX310X_IRDA_SHORTIR_BIT (1 << 2) /* Short SIR mode enable */ | |
168 | #define MAX310X_IRDA_MIR_BIT (1 << 3) /* MIR mode enable */ | |
169 | #define MAX310X_IRDA_RXINV_BIT (1 << 4) /* RX logic inversion enable */ | |
170 | #define MAX310X_IRDA_TXINV_BIT (1 << 5) /* TX logic inversion enable */ | |
171 | ||
172 | /* Flow control trigger level register masks */ | |
173 | #define MAX310X_FLOWLVL_HALT_MASK (0x000f) /* Flow control halt level */ | |
174 | #define MAX310X_FLOWLVL_RES_MASK (0x00f0) /* Flow control resume level */ | |
175 | #define MAX310X_FLOWLVL_HALT(words) ((words / 8) & 0x0f) | |
176 | #define MAX310X_FLOWLVL_RES(words) (((words / 8) & 0x0f) << 4) | |
177 | ||
178 | /* FIFO interrupt trigger level register masks */ | |
179 | #define MAX310X_FIFOTRIGLVL_TX_MASK (0x0f) /* TX FIFO trigger level */ | |
180 | #define MAX310X_FIFOTRIGLVL_RX_MASK (0xf0) /* RX FIFO trigger level */ | |
181 | #define MAX310X_FIFOTRIGLVL_TX(words) ((words / 8) & 0x0f) | |
182 | #define MAX310X_FIFOTRIGLVL_RX(words) (((words / 8) & 0x0f) << 4) | |
183 | ||
184 | /* Flow control register bits */ | |
185 | #define MAX310X_FLOWCTRL_AUTORTS_BIT (1 << 0) /* Auto RTS flow ctrl enable */ | |
186 | #define MAX310X_FLOWCTRL_AUTOCTS_BIT (1 << 1) /* Auto CTS flow ctrl enable */ | |
187 | #define MAX310X_FLOWCTRL_GPIADDR_BIT (1 << 2) /* Enables that GPIO inputs | |
188 | * are used in conjunction with | |
189 | * XOFF2 for definition of | |
190 | * special character */ | |
191 | #define MAX310X_FLOWCTRL_SWFLOWEN_BIT (1 << 3) /* Auto SW flow ctrl enable */ | |
192 | #define MAX310X_FLOWCTRL_SWFLOW0_BIT (1 << 4) /* SWFLOW bit 0 */ | |
193 | #define MAX310X_FLOWCTRL_SWFLOW1_BIT (1 << 5) /* SWFLOW bit 1 | |
194 | * | |
195 | * SWFLOW bits 1 & 0 table: | |
196 | * 00 -> no transmitter flow | |
197 | * control | |
198 | * 01 -> receiver compares | |
199 | * XON2 and XOFF2 | |
200 | * and controls | |
201 | * transmitter | |
202 | * 10 -> receiver compares | |
203 | * XON1 and XOFF1 | |
204 | * and controls | |
205 | * transmitter | |
206 | * 11 -> receiver compares | |
207 | * XON1, XON2, XOFF1 and | |
208 | * XOFF2 and controls | |
209 | * transmitter | |
210 | */ | |
211 | #define MAX310X_FLOWCTRL_SWFLOW2_BIT (1 << 6) /* SWFLOW bit 2 */ | |
212 | #define MAX310X_FLOWCTRL_SWFLOW3_BIT (1 << 7) /* SWFLOW bit 3 | |
213 | * | |
214 | * SWFLOW bits 3 & 2 table: | |
215 | * 00 -> no received flow | |
216 | * control | |
217 | * 01 -> transmitter generates | |
218 | * XON2 and XOFF2 | |
219 | * 10 -> transmitter generates | |
220 | * XON1 and XOFF1 | |
221 | * 11 -> transmitter generates | |
222 | * XON1, XON2, XOFF1 and | |
223 | * XOFF2 | |
224 | */ | |
225 | ||
226 | /* GPIO configuration register bits */ | |
227 | #define MAX310X_GPIOCFG_GP0OUT_BIT (1 << 0) /* GPIO 0 output enable */ | |
228 | #define MAX310X_GPIOCFG_GP1OUT_BIT (1 << 1) /* GPIO 1 output enable */ | |
229 | #define MAX310X_GPIOCFG_GP2OUT_BIT (1 << 2) /* GPIO 2 output enable */ | |
230 | #define MAX310X_GPIOCFG_GP3OUT_BIT (1 << 3) /* GPIO 3 output enable */ | |
231 | #define MAX310X_GPIOCFG_GP0OD_BIT (1 << 4) /* GPIO 0 open-drain enable */ | |
232 | #define MAX310X_GPIOCFG_GP1OD_BIT (1 << 5) /* GPIO 1 open-drain enable */ | |
233 | #define MAX310X_GPIOCFG_GP2OD_BIT (1 << 6) /* GPIO 2 open-drain enable */ | |
234 | #define MAX310X_GPIOCFG_GP3OD_BIT (1 << 7) /* GPIO 3 open-drain enable */ | |
235 | ||
236 | /* GPIO DATA register bits */ | |
237 | #define MAX310X_GPIODATA_GP0OUT_BIT (1 << 0) /* GPIO 0 output value */ | |
238 | #define MAX310X_GPIODATA_GP1OUT_BIT (1 << 1) /* GPIO 1 output value */ | |
239 | #define MAX310X_GPIODATA_GP2OUT_BIT (1 << 2) /* GPIO 2 output value */ | |
240 | #define MAX310X_GPIODATA_GP3OUT_BIT (1 << 3) /* GPIO 3 output value */ | |
241 | #define MAX310X_GPIODATA_GP0IN_BIT (1 << 4) /* GPIO 0 input value */ | |
242 | #define MAX310X_GPIODATA_GP1IN_BIT (1 << 5) /* GPIO 1 input value */ | |
243 | #define MAX310X_GPIODATA_GP2IN_BIT (1 << 6) /* GPIO 2 input value */ | |
244 | #define MAX310X_GPIODATA_GP3IN_BIT (1 << 7) /* GPIO 3 input value */ | |
245 | ||
246 | /* PLL configuration register masks */ | |
247 | #define MAX310X_PLLCFG_PREDIV_MASK (0x3f) /* PLL predivision value */ | |
248 | #define MAX310X_PLLCFG_PLLFACTOR_MASK (0xc0) /* PLL multiplication factor */ | |
249 | ||
250 | /* Baud rate generator configuration register bits */ | |
251 | #define MAX310X_BRGCFG_2XMODE_BIT (1 << 4) /* Double baud rate */ | |
252 | #define MAX310X_BRGCFG_4XMODE_BIT (1 << 5) /* Quadruple baud rate */ | |
253 | ||
254 | /* Clock source register bits */ | |
255 | #define MAX310X_CLKSRC_CRYST_BIT (1 << 1) /* Crystal osc enable */ | |
256 | #define MAX310X_CLKSRC_PLL_BIT (1 << 2) /* PLL enable */ | |
257 | #define MAX310X_CLKSRC_PLLBYP_BIT (1 << 3) /* PLL bypass */ | |
258 | #define MAX310X_CLKSRC_EXTCLK_BIT (1 << 4) /* External clock enable */ | |
259 | #define MAX310X_CLKSRC_CLK2RTS_BIT (1 << 7) /* Baud clk to RTS pin */ | |
260 | ||
10d8b34a AS |
261 | /* Global commands */ |
262 | #define MAX310X_EXTREG_ENBL (0xce) | |
263 | #define MAX310X_EXTREG_DSBL (0xcd) | |
264 | ||
f6544418 AS |
265 | /* Misc definitions */ |
266 | #define MAX310X_FIFO_SIZE (128) | |
10d8b34a | 267 | #define MAX310x_REV_MASK (0xfc) |
f6544418 AS |
268 | |
269 | /* MAX3107 specific */ | |
270 | #define MAX3107_REV_ID (0xa0) | |
10d8b34a AS |
271 | |
272 | struct max310x_devtype { | |
273 | char name[9]; | |
274 | int nr; | |
275 | int (*detect)(struct device *); | |
276 | void (*power)(struct uart_port *, int); | |
f6544418 AS |
277 | }; |
278 | ||
10d8b34a | 279 | struct max310x_one { |
f6544418 | 280 | struct uart_port port; |
10d8b34a AS |
281 | struct work_struct tx_work; |
282 | }; | |
f6544418 | 283 | |
10d8b34a AS |
284 | struct max310x_port { |
285 | struct uart_driver uart; | |
286 | struct max310x_devtype *devtype; | |
287 | struct regmap *regmap; | |
288 | struct regmap_config regcfg; | |
289 | struct mutex mutex; | |
290 | struct max310x_pdata *pdata; | |
291 | int gpio_used; | |
f6544418 AS |
292 | #ifdef CONFIG_GPIOLIB |
293 | struct gpio_chip gpio; | |
294 | #endif | |
10d8b34a AS |
295 | struct max310x_one p[0]; |
296 | }; | |
f6544418 | 297 | |
10d8b34a AS |
298 | static u8 max310x_port_read(struct uart_port *port, u8 reg) |
299 | { | |
300 | struct max310x_port *s = dev_get_drvdata(port->dev); | |
301 | unsigned int val = 0; | |
f6544418 | 302 | |
10d8b34a | 303 | regmap_read(s->regmap, port->iobase + reg, &val); |
f6544418 | 304 | |
10d8b34a AS |
305 | return val; |
306 | } | |
f6544418 | 307 | |
10d8b34a AS |
308 | static void max310x_port_write(struct uart_port *port, u8 reg, u8 val) |
309 | { | |
310 | struct max310x_port *s = dev_get_drvdata(port->dev); | |
311 | ||
312 | regmap_write(s->regmap, port->iobase + reg, val); | |
313 | } | |
314 | ||
315 | static void max310x_port_update(struct uart_port *port, u8 reg, u8 mask, u8 val) | |
316 | { | |
317 | struct max310x_port *s = dev_get_drvdata(port->dev); | |
318 | ||
319 | regmap_update_bits(s->regmap, port->iobase + reg, mask, val); | |
320 | } | |
321 | ||
322 | static int max3107_detect(struct device *dev) | |
323 | { | |
324 | struct max310x_port *s = dev_get_drvdata(dev); | |
325 | unsigned int val = 0; | |
326 | int ret; | |
327 | ||
328 | ret = regmap_read(s->regmap, MAX310X_REVID_REG, &val); | |
329 | if (ret) | |
330 | return ret; | |
331 | ||
332 | if (((val & MAX310x_REV_MASK) != MAX3107_REV_ID)) { | |
333 | dev_err(dev, | |
334 | "%s ID 0x%02x does not match\n", s->devtype->name, val); | |
335 | return -ENODEV; | |
336 | } | |
337 | ||
338 | return 0; | |
339 | } | |
340 | ||
341 | static int max3108_detect(struct device *dev) | |
342 | { | |
343 | struct max310x_port *s = dev_get_drvdata(dev); | |
344 | unsigned int val = 0; | |
345 | int ret; | |
346 | ||
347 | /* MAX3108 have not REV ID register, we just check default value | |
348 | * from clocksource register to make sure everything works. | |
349 | */ | |
350 | ret = regmap_read(s->regmap, MAX310X_CLKSRC_REG, &val); | |
351 | if (ret) | |
352 | return ret; | |
353 | ||
354 | if (val != (MAX310X_CLKSRC_EXTCLK_BIT | MAX310X_CLKSRC_PLLBYP_BIT)) { | |
355 | dev_err(dev, "%s not present\n", s->devtype->name); | |
356 | return -ENODEV; | |
357 | } | |
358 | ||
359 | return 0; | |
360 | } | |
361 | ||
362 | static void max310x_power(struct uart_port *port, int on) | |
363 | { | |
364 | max310x_port_update(port, MAX310X_MODE1_REG, | |
365 | MAX310X_MODE1_FORCESLEEP_BIT, | |
366 | on ? 0 : MAX310X_MODE1_FORCESLEEP_BIT); | |
367 | if (on) | |
368 | msleep(50); | |
369 | } | |
370 | ||
371 | static const struct max310x_devtype max3107_devtype = { | |
372 | .name = "MAX3107", | |
373 | .nr = 1, | |
374 | .detect = max3107_detect, | |
375 | .power = max310x_power, | |
f6544418 AS |
376 | }; |
377 | ||
10d8b34a AS |
378 | static const struct max310x_devtype max3108_devtype = { |
379 | .name = "MAX3108", | |
380 | .nr = 1, | |
381 | .detect = max3108_detect, | |
382 | .power = max310x_power, | |
383 | }; | |
384 | ||
385 | static bool max310x_reg_writeable(struct device *dev, unsigned int reg) | |
f6544418 | 386 | { |
10d8b34a | 387 | switch (reg & 0x1f) { |
f6544418 AS |
388 | case MAX310X_IRQSTS_REG: |
389 | case MAX310X_LSR_IRQSTS_REG: | |
390 | case MAX310X_SPCHR_IRQSTS_REG: | |
391 | case MAX310X_STS_IRQSTS_REG: | |
392 | case MAX310X_TXFIFOLVL_REG: | |
393 | case MAX310X_RXFIFOLVL_REG: | |
f6544418 AS |
394 | return false; |
395 | default: | |
396 | break; | |
397 | } | |
398 | ||
399 | return true; | |
400 | } | |
401 | ||
402 | static bool max310x_reg_volatile(struct device *dev, unsigned int reg) | |
403 | { | |
10d8b34a | 404 | switch (reg & 0x1f) { |
f6544418 AS |
405 | case MAX310X_RHR_REG: |
406 | case MAX310X_IRQSTS_REG: | |
407 | case MAX310X_LSR_IRQSTS_REG: | |
408 | case MAX310X_SPCHR_IRQSTS_REG: | |
409 | case MAX310X_STS_IRQSTS_REG: | |
410 | case MAX310X_TXFIFOLVL_REG: | |
411 | case MAX310X_RXFIFOLVL_REG: | |
412 | case MAX310X_GPIODATA_REG: | |
10d8b34a AS |
413 | case MAX310X_BRGDIVLSB_REG: |
414 | case MAX310X_REG_05: | |
415 | case MAX310X_REG_1F: | |
f6544418 AS |
416 | return true; |
417 | default: | |
418 | break; | |
419 | } | |
420 | ||
421 | return false; | |
422 | } | |
423 | ||
424 | static bool max310x_reg_precious(struct device *dev, unsigned int reg) | |
425 | { | |
10d8b34a | 426 | switch (reg & 0x1f) { |
f6544418 AS |
427 | case MAX310X_RHR_REG: |
428 | case MAX310X_IRQSTS_REG: | |
429 | case MAX310X_SPCHR_IRQSTS_REG: | |
430 | case MAX310X_STS_IRQSTS_REG: | |
431 | return true; | |
432 | default: | |
433 | break; | |
434 | } | |
435 | ||
436 | return false; | |
437 | } | |
438 | ||
10d8b34a | 439 | static void max310x_set_baud(struct uart_port *port, int baud) |
f6544418 | 440 | { |
10d8b34a | 441 | unsigned int mode = 0, div = port->uartclk / baud; |
f6544418 AS |
442 | |
443 | if (!(div / 16)) { | |
444 | /* Mode x2 */ | |
445 | mode = MAX310X_BRGCFG_2XMODE_BIT; | |
10d8b34a | 446 | div = (port->uartclk * 2) / baud; |
f6544418 AS |
447 | } |
448 | ||
449 | if (!(div / 16)) { | |
450 | /* Mode x4 */ | |
451 | mode = MAX310X_BRGCFG_4XMODE_BIT; | |
10d8b34a | 452 | div = (port->uartclk * 4) / baud; |
f6544418 AS |
453 | } |
454 | ||
10d8b34a AS |
455 | max310x_port_write(port, MAX310X_BRGDIVMSB_REG, (div / 16) >> 8); |
456 | max310x_port_write(port, MAX310X_BRGDIVLSB_REG, div / 16); | |
457 | max310x_port_write(port, MAX310X_BRGCFG_REG, (div % 16) | mode); | |
f6544418 AS |
458 | } |
459 | ||
9671f099 | 460 | static int max310x_update_best_err(unsigned long f, long *besterr) |
f6544418 AS |
461 | { |
462 | /* Use baudrate 115200 for calculate error */ | |
463 | long err = f % (115200 * 16); | |
464 | ||
465 | if ((*besterr < 0) || (*besterr > err)) { | |
466 | *besterr = err; | |
467 | return 0; | |
468 | } | |
469 | ||
470 | return 1; | |
471 | } | |
472 | ||
9671f099 | 473 | static int max310x_set_ref_clk(struct max310x_port *s) |
f6544418 AS |
474 | { |
475 | unsigned int div, clksrc, pllcfg = 0; | |
476 | long besterr = -1; | |
477 | unsigned long fdiv, fmul, bestfreq = s->pdata->frequency; | |
478 | ||
479 | /* First, update error without PLL */ | |
480 | max310x_update_best_err(s->pdata->frequency, &besterr); | |
481 | ||
482 | /* Try all possible PLL dividers */ | |
483 | for (div = 1; (div <= 63) && besterr; div++) { | |
484 | fdiv = DIV_ROUND_CLOSEST(s->pdata->frequency, div); | |
485 | ||
486 | /* Try multiplier 6 */ | |
487 | fmul = fdiv * 6; | |
488 | if ((fdiv >= 500000) && (fdiv <= 800000)) | |
489 | if (!max310x_update_best_err(fmul, &besterr)) { | |
490 | pllcfg = (0 << 6) | div; | |
491 | bestfreq = fmul; | |
492 | } | |
493 | /* Try multiplier 48 */ | |
494 | fmul = fdiv * 48; | |
495 | if ((fdiv >= 850000) && (fdiv <= 1200000)) | |
496 | if (!max310x_update_best_err(fmul, &besterr)) { | |
497 | pllcfg = (1 << 6) | div; | |
498 | bestfreq = fmul; | |
499 | } | |
500 | /* Try multiplier 96 */ | |
501 | fmul = fdiv * 96; | |
502 | if ((fdiv >= 425000) && (fdiv <= 1000000)) | |
503 | if (!max310x_update_best_err(fmul, &besterr)) { | |
504 | pllcfg = (2 << 6) | div; | |
505 | bestfreq = fmul; | |
506 | } | |
507 | /* Try multiplier 144 */ | |
508 | fmul = fdiv * 144; | |
509 | if ((fdiv >= 390000) && (fdiv <= 667000)) | |
510 | if (!max310x_update_best_err(fmul, &besterr)) { | |
511 | pllcfg = (3 << 6) | div; | |
512 | bestfreq = fmul; | |
513 | } | |
514 | } | |
515 | ||
516 | /* Configure clock source */ | |
517 | if (s->pdata->driver_flags & MAX310X_EXT_CLK) | |
518 | clksrc = MAX310X_CLKSRC_EXTCLK_BIT; | |
519 | else | |
520 | clksrc = MAX310X_CLKSRC_CRYST_BIT; | |
521 | ||
522 | /* Configure PLL */ | |
523 | if (pllcfg) { | |
524 | clksrc |= MAX310X_CLKSRC_PLL_BIT; | |
525 | regmap_write(s->regmap, MAX310X_PLLCFG_REG, pllcfg); | |
526 | } else | |
527 | clksrc |= MAX310X_CLKSRC_PLLBYP_BIT; | |
528 | ||
529 | regmap_write(s->regmap, MAX310X_CLKSRC_REG, clksrc); | |
530 | ||
10d8b34a AS |
531 | /* Wait for crystal */ |
532 | if (pllcfg && !(s->pdata->driver_flags & MAX310X_EXT_CLK)) | |
533 | msleep(10); | |
f6544418 AS |
534 | |
535 | return (int)bestfreq; | |
536 | } | |
537 | ||
10d8b34a | 538 | static void max310x_handle_rx(struct uart_port *port, unsigned int rxlen) |
f6544418 | 539 | { |
10d8b34a | 540 | unsigned int sts, ch, flag; |
f6544418 | 541 | |
10d8b34a AS |
542 | if (unlikely(rxlen >= port->fifosize)) { |
543 | dev_warn_ratelimited(port->dev, | |
544 | "Port %i: Possible RX FIFO overrun\n", | |
545 | port->line); | |
546 | port->icount.buf_overrun++; | |
f6544418 | 547 | /* Ensure sanity of RX level */ |
10d8b34a | 548 | rxlen = port->fifosize; |
f6544418 AS |
549 | } |
550 | ||
f6544418 | 551 | while (rxlen--) { |
10d8b34a AS |
552 | ch = max310x_port_read(port, MAX310X_RHR_REG); |
553 | sts = max310x_port_read(port, MAX310X_LSR_IRQSTS_REG); | |
f6544418 AS |
554 | |
555 | sts &= MAX310X_LSR_RXPAR_BIT | MAX310X_LSR_FRERR_BIT | | |
556 | MAX310X_LSR_RXOVR_BIT | MAX310X_LSR_RXBRK_BIT; | |
557 | ||
10d8b34a | 558 | port->icount.rx++; |
f6544418 AS |
559 | flag = TTY_NORMAL; |
560 | ||
561 | if (unlikely(sts)) { | |
562 | if (sts & MAX310X_LSR_RXBRK_BIT) { | |
10d8b34a AS |
563 | port->icount.brk++; |
564 | if (uart_handle_break(port)) | |
f6544418 AS |
565 | continue; |
566 | } else if (sts & MAX310X_LSR_RXPAR_BIT) | |
10d8b34a | 567 | port->icount.parity++; |
f6544418 | 568 | else if (sts & MAX310X_LSR_FRERR_BIT) |
10d8b34a | 569 | port->icount.frame++; |
f6544418 | 570 | else if (sts & MAX310X_LSR_RXOVR_BIT) |
10d8b34a | 571 | port->icount.overrun++; |
f6544418 | 572 | |
10d8b34a | 573 | sts &= port->read_status_mask; |
f6544418 AS |
574 | if (sts & MAX310X_LSR_RXBRK_BIT) |
575 | flag = TTY_BREAK; | |
576 | else if (sts & MAX310X_LSR_RXPAR_BIT) | |
577 | flag = TTY_PARITY; | |
578 | else if (sts & MAX310X_LSR_FRERR_BIT) | |
579 | flag = TTY_FRAME; | |
580 | else if (sts & MAX310X_LSR_RXOVR_BIT) | |
581 | flag = TTY_OVERRUN; | |
582 | } | |
583 | ||
10d8b34a | 584 | if (uart_handle_sysrq_char(port, ch)) |
f6544418 AS |
585 | continue; |
586 | ||
10d8b34a | 587 | if (sts & port->ignore_status_mask) |
f6544418 AS |
588 | continue; |
589 | ||
10d8b34a | 590 | uart_insert_char(port, sts, MAX310X_LSR_RXOVR_BIT, ch, flag); |
f6544418 AS |
591 | } |
592 | ||
10d8b34a | 593 | tty_flip_buffer_push(&port->state->port); |
f6544418 AS |
594 | } |
595 | ||
10d8b34a | 596 | static void max310x_handle_tx(struct uart_port *port) |
f6544418 | 597 | { |
10d8b34a AS |
598 | struct circ_buf *xmit = &port->state->xmit; |
599 | unsigned int txlen, to_send; | |
f6544418 | 600 | |
10d8b34a AS |
601 | if (unlikely(port->x_char)) { |
602 | max310x_port_write(port, MAX310X_THR_REG, port->x_char); | |
603 | port->icount.tx++; | |
604 | port->x_char = 0; | |
f6544418 AS |
605 | return; |
606 | } | |
607 | ||
10d8b34a | 608 | if (uart_circ_empty(xmit) || uart_tx_stopped(port)) |
f6544418 AS |
609 | return; |
610 | ||
611 | /* Get length of data pending in circular buffer */ | |
612 | to_send = uart_circ_chars_pending(xmit); | |
613 | if (likely(to_send)) { | |
614 | /* Limit to size of TX FIFO */ | |
10d8b34a AS |
615 | txlen = max310x_port_read(port, MAX310X_TXFIFOLVL_REG); |
616 | txlen = port->fifosize - txlen; | |
f6544418 AS |
617 | to_send = (to_send > txlen) ? txlen : to_send; |
618 | ||
f6544418 | 619 | /* Add data to send */ |
10d8b34a | 620 | port->icount.tx += to_send; |
f6544418 | 621 | while (to_send--) { |
10d8b34a AS |
622 | max310x_port_write(port, MAX310X_THR_REG, |
623 | xmit->buf[xmit->tail]); | |
f6544418 AS |
624 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); |
625 | }; | |
626 | } | |
627 | ||
628 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
10d8b34a | 629 | uart_write_wakeup(port); |
f6544418 AS |
630 | } |
631 | ||
10d8b34a | 632 | static void max310x_port_irq(struct max310x_port *s, int portno) |
f6544418 | 633 | { |
10d8b34a | 634 | struct uart_port *port = &s->p[portno].port; |
f6544418 | 635 | |
10d8b34a AS |
636 | do { |
637 | unsigned int ists, lsr, rxlen; | |
f6544418 | 638 | |
f6544418 | 639 | /* Read IRQ status & RX FIFO level */ |
10d8b34a AS |
640 | ists = max310x_port_read(port, MAX310X_IRQSTS_REG); |
641 | rxlen = max310x_port_read(port, MAX310X_RXFIFOLVL_REG); | |
642 | if (!ists && !rxlen) | |
f6544418 AS |
643 | break; |
644 | ||
10d8b34a AS |
645 | if (ists & MAX310X_IRQ_CTS_BIT) { |
646 | lsr = max310x_port_read(port, MAX310X_LSR_IRQSTS_REG); | |
647 | uart_handle_cts_change(port, | |
f6544418 | 648 | !!(lsr & MAX310X_LSR_CTS_BIT)); |
10d8b34a AS |
649 | } |
650 | if (rxlen) | |
651 | max310x_handle_rx(port, rxlen); | |
652 | if (ists & MAX310X_IRQ_TXEMPTY_BIT) { | |
653 | mutex_lock(&s->mutex); | |
654 | max310x_handle_tx(port); | |
655 | mutex_unlock(&s->mutex); | |
656 | } | |
657 | } while (1); | |
658 | } | |
f6544418 | 659 | |
10d8b34a AS |
660 | static irqreturn_t max310x_ist(int irq, void *dev_id) |
661 | { | |
662 | struct max310x_port *s = (struct max310x_port *)dev_id; | |
663 | ||
664 | if (s->uart.nr > 1) { | |
665 | do { | |
666 | unsigned int val = ~0; | |
667 | ||
668 | WARN_ON_ONCE(regmap_read(s->regmap, | |
669 | MAX310X_GLOBALIRQ_REG, &val)); | |
670 | val = ((1 << s->uart.nr) - 1) & ~val; | |
671 | if (!val) | |
672 | break; | |
673 | max310x_port_irq(s, fls(val) - 1); | |
674 | } while (1); | |
675 | } else | |
676 | max310x_port_irq(s, 0); | |
f6544418 AS |
677 | |
678 | return IRQ_HANDLED; | |
679 | } | |
680 | ||
681 | static void max310x_wq_proc(struct work_struct *ws) | |
682 | { | |
10d8b34a AS |
683 | struct max310x_one *one = container_of(ws, struct max310x_one, tx_work); |
684 | struct max310x_port *s = dev_get_drvdata(one->port.dev); | |
f6544418 | 685 | |
10d8b34a AS |
686 | mutex_lock(&s->mutex); |
687 | max310x_handle_tx(&one->port); | |
688 | mutex_unlock(&s->mutex); | |
f6544418 AS |
689 | } |
690 | ||
691 | static void max310x_start_tx(struct uart_port *port) | |
692 | { | |
10d8b34a | 693 | struct max310x_one *one = container_of(port, struct max310x_one, port); |
f6544418 | 694 | |
10d8b34a AS |
695 | if (!work_pending(&one->tx_work)) |
696 | schedule_work(&one->tx_work); | |
f6544418 AS |
697 | } |
698 | ||
699 | static unsigned int max310x_tx_empty(struct uart_port *port) | |
700 | { | |
10d8b34a | 701 | unsigned int lvl, sts; |
f6544418 | 702 | |
10d8b34a AS |
703 | lvl = max310x_port_read(port, MAX310X_TXFIFOLVL_REG); |
704 | sts = max310x_port_read(port, MAX310X_IRQSTS_REG); | |
f6544418 | 705 | |
10d8b34a | 706 | return ((sts & MAX310X_IRQ_TXEMPTY_BIT) && !lvl) ? TIOCSER_TEMT : 0; |
f6544418 AS |
707 | } |
708 | ||
709 | static unsigned int max310x_get_mctrl(struct uart_port *port) | |
710 | { | |
711 | /* DCD and DSR are not wired and CTS/RTS is handled automatically | |
712 | * so just indicate DSR and CAR asserted | |
713 | */ | |
714 | return TIOCM_DSR | TIOCM_CAR; | |
715 | } | |
716 | ||
717 | static void max310x_set_mctrl(struct uart_port *port, unsigned int mctrl) | |
718 | { | |
719 | /* DCD and DSR are not wired and CTS/RTS is hadnled automatically | |
720 | * so do nothing | |
721 | */ | |
722 | } | |
723 | ||
724 | static void max310x_break_ctl(struct uart_port *port, int break_state) | |
725 | { | |
10d8b34a AS |
726 | max310x_port_update(port, MAX310X_LCR_REG, |
727 | MAX310X_LCR_TXBREAK_BIT, | |
728 | break_state ? MAX310X_LCR_TXBREAK_BIT : 0); | |
f6544418 AS |
729 | } |
730 | ||
731 | static void max310x_set_termios(struct uart_port *port, | |
732 | struct ktermios *termios, | |
733 | struct ktermios *old) | |
734 | { | |
f6544418 AS |
735 | unsigned int lcr, flow = 0; |
736 | int baud; | |
737 | ||
f6544418 AS |
738 | /* Mask termios capabilities we don't support */ |
739 | termios->c_cflag &= ~CMSPAR; | |
f6544418 AS |
740 | |
741 | /* Word size */ | |
742 | switch (termios->c_cflag & CSIZE) { | |
743 | case CS5: | |
744 | lcr = MAX310X_LCR_WORD_LEN_5; | |
745 | break; | |
746 | case CS6: | |
747 | lcr = MAX310X_LCR_WORD_LEN_6; | |
748 | break; | |
749 | case CS7: | |
750 | lcr = MAX310X_LCR_WORD_LEN_7; | |
751 | break; | |
752 | case CS8: | |
753 | default: | |
754 | lcr = MAX310X_LCR_WORD_LEN_8; | |
755 | break; | |
756 | } | |
757 | ||
758 | /* Parity */ | |
759 | if (termios->c_cflag & PARENB) { | |
760 | lcr |= MAX310X_LCR_PARITY_BIT; | |
761 | if (!(termios->c_cflag & PARODD)) | |
762 | lcr |= MAX310X_LCR_EVENPARITY_BIT; | |
763 | } | |
764 | ||
765 | /* Stop bits */ | |
766 | if (termios->c_cflag & CSTOPB) | |
767 | lcr |= MAX310X_LCR_STOPLEN_BIT; /* 2 stops */ | |
768 | ||
769 | /* Update LCR register */ | |
10d8b34a | 770 | max310x_port_write(port, MAX310X_LCR_REG, lcr); |
f6544418 AS |
771 | |
772 | /* Set read status mask */ | |
773 | port->read_status_mask = MAX310X_LSR_RXOVR_BIT; | |
774 | if (termios->c_iflag & INPCK) | |
775 | port->read_status_mask |= MAX310X_LSR_RXPAR_BIT | | |
776 | MAX310X_LSR_FRERR_BIT; | |
777 | if (termios->c_iflag & (BRKINT | PARMRK)) | |
778 | port->read_status_mask |= MAX310X_LSR_RXBRK_BIT; | |
779 | ||
780 | /* Set status ignore mask */ | |
781 | port->ignore_status_mask = 0; | |
782 | if (termios->c_iflag & IGNBRK) | |
783 | port->ignore_status_mask |= MAX310X_LSR_RXBRK_BIT; | |
784 | if (!(termios->c_cflag & CREAD)) | |
785 | port->ignore_status_mask |= MAX310X_LSR_RXPAR_BIT | | |
786 | MAX310X_LSR_RXOVR_BIT | | |
787 | MAX310X_LSR_FRERR_BIT | | |
788 | MAX310X_LSR_RXBRK_BIT; | |
789 | ||
790 | /* Configure flow control */ | |
10d8b34a AS |
791 | max310x_port_write(port, MAX310X_XON1_REG, termios->c_cc[VSTART]); |
792 | max310x_port_write(port, MAX310X_XOFF1_REG, termios->c_cc[VSTOP]); | |
f6544418 AS |
793 | if (termios->c_cflag & CRTSCTS) |
794 | flow |= MAX310X_FLOWCTRL_AUTOCTS_BIT | | |
795 | MAX310X_FLOWCTRL_AUTORTS_BIT; | |
796 | if (termios->c_iflag & IXON) | |
797 | flow |= MAX310X_FLOWCTRL_SWFLOW3_BIT | | |
798 | MAX310X_FLOWCTRL_SWFLOWEN_BIT; | |
799 | if (termios->c_iflag & IXOFF) | |
800 | flow |= MAX310X_FLOWCTRL_SWFLOW1_BIT | | |
801 | MAX310X_FLOWCTRL_SWFLOWEN_BIT; | |
10d8b34a | 802 | max310x_port_write(port, MAX310X_FLOWCTRL_REG, flow); |
f6544418 AS |
803 | |
804 | /* Get baud rate generator configuration */ | |
805 | baud = uart_get_baud_rate(port, termios, old, | |
806 | port->uartclk / 16 / 0xffff, | |
807 | port->uartclk / 4); | |
808 | ||
809 | /* Setup baudrate generator */ | |
10d8b34a | 810 | max310x_set_baud(port, baud); |
f6544418 AS |
811 | |
812 | /* Update timeout according to new baud rate */ | |
813 | uart_update_timeout(port, termios->c_cflag, baud); | |
f6544418 AS |
814 | } |
815 | ||
816 | static int max310x_startup(struct uart_port *port) | |
817 | { | |
818 | unsigned int val, line = port->line; | |
10d8b34a | 819 | struct max310x_port *s = dev_get_drvdata(port->dev); |
f6544418 | 820 | |
10d8b34a | 821 | s->devtype->power(port, 1); |
f6544418 AS |
822 | |
823 | /* Configure baud rate, 9600 as default */ | |
10d8b34a | 824 | max310x_set_baud(port, 9600); |
f6544418 AS |
825 | |
826 | /* Configure LCR register, 8N1 mode by default */ | |
10d8b34a | 827 | max310x_port_write(port, MAX310X_LCR_REG, MAX310X_LCR_WORD_LEN_8); |
f6544418 AS |
828 | |
829 | /* Configure MODE1 register */ | |
10d8b34a AS |
830 | max310x_port_update(port, MAX310X_MODE1_REG, |
831 | MAX310X_MODE1_TRNSCVCTRL_BIT, | |
832 | (s->pdata->uart_flags[line] & MAX310X_AUTO_DIR_CTRL) | |
833 | ? MAX310X_MODE1_TRNSCVCTRL_BIT : 0); | |
f6544418 AS |
834 | |
835 | /* Configure MODE2 register */ | |
836 | val = MAX310X_MODE2_RXEMPTINV_BIT; | |
837 | if (s->pdata->uart_flags[line] & MAX310X_LOOPBACK) | |
838 | val |= MAX310X_MODE2_LOOPBACK_BIT; | |
839 | if (s->pdata->uart_flags[line] & MAX310X_ECHO_SUPRESS) | |
840 | val |= MAX310X_MODE2_ECHOSUPR_BIT; | |
841 | ||
842 | /* Reset FIFOs */ | |
843 | val |= MAX310X_MODE2_FIFORST_BIT; | |
10d8b34a AS |
844 | max310x_port_write(port, MAX310X_MODE2_REG, val); |
845 | max310x_port_update(port, MAX310X_MODE2_REG, | |
846 | MAX310X_MODE2_FIFORST_BIT, 0); | |
f6544418 AS |
847 | |
848 | /* Configure flow control levels */ | |
849 | /* Flow control halt level 96, resume level 48 */ | |
10d8b34a AS |
850 | max310x_port_write(port, MAX310X_FLOWLVL_REG, |
851 | MAX310X_FLOWLVL_RES(48) | MAX310X_FLOWLVL_HALT(96)); | |
f6544418 | 852 | |
10d8b34a AS |
853 | /* Clear IRQ status register */ |
854 | max310x_port_read(port, MAX310X_IRQSTS_REG); | |
f6544418 | 855 | |
10d8b34a AS |
856 | /* Enable RX, TX, CTS change interrupts */ |
857 | val = MAX310X_IRQ_RXEMPTY_BIT | MAX310X_IRQ_TXEMPTY_BIT; | |
858 | max310x_port_write(port, MAX310X_IRQEN_REG, val | MAX310X_IRQ_CTS_BIT); | |
f6544418 AS |
859 | |
860 | return 0; | |
861 | } | |
862 | ||
863 | static void max310x_shutdown(struct uart_port *port) | |
864 | { | |
10d8b34a | 865 | struct max310x_port *s = dev_get_drvdata(port->dev); |
f6544418 AS |
866 | |
867 | /* Disable all interrupts */ | |
10d8b34a | 868 | max310x_port_write(port, MAX310X_IRQEN_REG, 0); |
f6544418 | 869 | |
10d8b34a | 870 | s->devtype->power(port, 0); |
f6544418 AS |
871 | } |
872 | ||
873 | static const char *max310x_type(struct uart_port *port) | |
874 | { | |
10d8b34a | 875 | struct max310x_port *s = dev_get_drvdata(port->dev); |
f6544418 | 876 | |
10d8b34a | 877 | return (port->type == PORT_MAX310X) ? s->devtype->name : NULL; |
f6544418 AS |
878 | } |
879 | ||
880 | static int max310x_request_port(struct uart_port *port) | |
881 | { | |
882 | /* Do nothing */ | |
883 | return 0; | |
884 | } | |
885 | ||
f6544418 AS |
886 | static void max310x_config_port(struct uart_port *port, int flags) |
887 | { | |
888 | if (flags & UART_CONFIG_TYPE) | |
889 | port->type = PORT_MAX310X; | |
890 | } | |
891 | ||
10d8b34a | 892 | static int max310x_verify_port(struct uart_port *port, struct serial_struct *s) |
f6544418 | 893 | { |
10d8b34a AS |
894 | if ((s->type != PORT_UNKNOWN) && (s->type != PORT_MAX310X)) |
895 | return -EINVAL; | |
896 | if (s->irq != port->irq) | |
897 | return -EINVAL; | |
f6544418 | 898 | |
10d8b34a | 899 | return 0; |
f6544418 AS |
900 | } |
901 | ||
10d8b34a AS |
902 | static void max310x_null_void(struct uart_port *port) |
903 | { | |
904 | /* Do nothing */ | |
905 | } | |
906 | ||
907 | static const struct uart_ops max310x_ops = { | |
f6544418 AS |
908 | .tx_empty = max310x_tx_empty, |
909 | .set_mctrl = max310x_set_mctrl, | |
910 | .get_mctrl = max310x_get_mctrl, | |
10d8b34a | 911 | .stop_tx = max310x_null_void, |
f6544418 | 912 | .start_tx = max310x_start_tx, |
10d8b34a AS |
913 | .stop_rx = max310x_null_void, |
914 | .enable_ms = max310x_null_void, | |
f6544418 AS |
915 | .break_ctl = max310x_break_ctl, |
916 | .startup = max310x_startup, | |
917 | .shutdown = max310x_shutdown, | |
918 | .set_termios = max310x_set_termios, | |
919 | .type = max310x_type, | |
920 | .request_port = max310x_request_port, | |
10d8b34a | 921 | .release_port = max310x_null_void, |
f6544418 AS |
922 | .config_port = max310x_config_port, |
923 | .verify_port = max310x_verify_port, | |
924 | }; | |
925 | ||
10d8b34a AS |
926 | static int __maybe_unused max310x_suspend(struct spi_device *spi, |
927 | pm_message_t state) | |
f6544418 | 928 | { |
10d8b34a AS |
929 | struct max310x_port *s = dev_get_drvdata(&spi->dev); |
930 | int i; | |
f6544418 | 931 | |
10d8b34a AS |
932 | for (i = 0; i < s->uart.nr; i++) { |
933 | uart_suspend_port(&s->uart, &s->p[i].port); | |
934 | s->devtype->power(&s->p[i].port, 0); | |
935 | } | |
f6544418 | 936 | |
10d8b34a | 937 | return 0; |
f6544418 AS |
938 | } |
939 | ||
10d8b34a | 940 | static int __maybe_unused max310x_resume(struct spi_device *spi) |
f6544418 | 941 | { |
10d8b34a AS |
942 | struct max310x_port *s = dev_get_drvdata(&spi->dev); |
943 | int i; | |
f6544418 | 944 | |
10d8b34a AS |
945 | for (i = 0; i < s->uart.nr; i++) { |
946 | s->devtype->power(&s->p[i].port, 1); | |
947 | uart_resume_port(&s->uart, &s->p[i].port); | |
948 | } | |
f6544418 | 949 | |
10d8b34a | 950 | return 0; |
f6544418 AS |
951 | } |
952 | ||
953 | #ifdef CONFIG_GPIOLIB | |
954 | static int max310x_gpio_get(struct gpio_chip *chip, unsigned offset) | |
955 | { | |
10d8b34a | 956 | unsigned int val; |
f6544418 | 957 | struct max310x_port *s = container_of(chip, struct max310x_port, gpio); |
10d8b34a | 958 | struct uart_port *port = &s->p[offset / 4].port; |
f6544418 | 959 | |
10d8b34a | 960 | val = max310x_port_read(port, MAX310X_GPIODATA_REG); |
f6544418 | 961 | |
10d8b34a | 962 | return !!((val >> 4) & (1 << (offset % 4))); |
f6544418 AS |
963 | } |
964 | ||
965 | static void max310x_gpio_set(struct gpio_chip *chip, unsigned offset, int value) | |
966 | { | |
967 | struct max310x_port *s = container_of(chip, struct max310x_port, gpio); | |
10d8b34a | 968 | struct uart_port *port = &s->p[offset / 4].port; |
f6544418 | 969 | |
10d8b34a AS |
970 | max310x_port_update(port, MAX310X_GPIODATA_REG, 1 << (offset % 4), |
971 | value ? 1 << (offset % 4) : 0); | |
f6544418 AS |
972 | } |
973 | ||
974 | static int max310x_gpio_direction_input(struct gpio_chip *chip, unsigned offset) | |
975 | { | |
976 | struct max310x_port *s = container_of(chip, struct max310x_port, gpio); | |
10d8b34a | 977 | struct uart_port *port = &s->p[offset / 4].port; |
f6544418 | 978 | |
10d8b34a | 979 | max310x_port_update(port, MAX310X_GPIOCFG_REG, 1 << (offset % 4), 0); |
f6544418 AS |
980 | |
981 | return 0; | |
982 | } | |
983 | ||
984 | static int max310x_gpio_direction_output(struct gpio_chip *chip, | |
985 | unsigned offset, int value) | |
986 | { | |
987 | struct max310x_port *s = container_of(chip, struct max310x_port, gpio); | |
10d8b34a | 988 | struct uart_port *port = &s->p[offset / 4].port; |
f6544418 | 989 | |
10d8b34a AS |
990 | max310x_port_update(port, MAX310X_GPIODATA_REG, 1 << (offset % 4), |
991 | value ? 1 << (offset % 4) : 0); | |
992 | max310x_port_update(port, MAX310X_GPIOCFG_REG, 1 << (offset % 4), | |
993 | 1 << (offset % 4)); | |
f6544418 AS |
994 | |
995 | return 0; | |
996 | } | |
997 | #endif | |
998 | ||
10d8b34a AS |
999 | static int max310x_probe(struct device *dev, int is_spi, |
1000 | struct max310x_devtype *devtype, int irq) | |
f6544418 AS |
1001 | { |
1002 | struct max310x_port *s; | |
10d8b34a AS |
1003 | struct max310x_pdata *pdata = dev_get_platdata(dev); |
1004 | int i, ret, uartclk; | |
f6544418 AS |
1005 | |
1006 | /* Check for IRQ */ | |
10d8b34a | 1007 | if (irq <= 0) { |
f6544418 AS |
1008 | dev_err(dev, "No IRQ specified\n"); |
1009 | return -ENOTSUPP; | |
1010 | } | |
1011 | ||
10d8b34a AS |
1012 | if (!pdata) { |
1013 | dev_err(dev, "No platform data supplied\n"); | |
1014 | return -EINVAL; | |
1015 | } | |
1016 | ||
f6544418 | 1017 | /* Alloc port structure */ |
10d8b34a AS |
1018 | s = devm_kzalloc(dev, sizeof(*s) + |
1019 | sizeof(struct max310x_one) * devtype->nr, GFP_KERNEL); | |
f6544418 AS |
1020 | if (!s) { |
1021 | dev_err(dev, "Error allocating port structure\n"); | |
1022 | return -ENOMEM; | |
1023 | } | |
f6544418 AS |
1024 | |
1025 | /* Check input frequency */ | |
1026 | if ((pdata->driver_flags & MAX310X_EXT_CLK) && | |
1027 | ((pdata->frequency < 500000) || (pdata->frequency > 35000000))) | |
1028 | goto err_freq; | |
1029 | /* Check frequency for quartz */ | |
1030 | if (!(pdata->driver_flags & MAX310X_EXT_CLK) && | |
1031 | ((pdata->frequency < 1000000) || (pdata->frequency > 4000000))) | |
1032 | goto err_freq; | |
1033 | ||
10d8b34a AS |
1034 | s->pdata = pdata; |
1035 | s->devtype = devtype; | |
1036 | dev_set_drvdata(dev, s); | |
f6544418 | 1037 | |
10d8b34a | 1038 | mutex_init(&s->mutex); |
f6544418 AS |
1039 | |
1040 | /* Setup regmap */ | |
1041 | s->regcfg.reg_bits = 8; | |
1042 | s->regcfg.val_bits = 8; | |
1043 | s->regcfg.read_flag_mask = 0x00; | |
1044 | s->regcfg.write_flag_mask = 0x80; | |
1045 | s->regcfg.cache_type = REGCACHE_RBTREE; | |
10d8b34a | 1046 | s->regcfg.writeable_reg = max310x_reg_writeable; |
f6544418 AS |
1047 | s->regcfg.volatile_reg = max310x_reg_volatile; |
1048 | s->regcfg.precious_reg = max310x_reg_precious; | |
10d8b34a AS |
1049 | s->regcfg.max_register = devtype->nr * 0x20 - 1; |
1050 | ||
1051 | if (IS_ENABLED(CONFIG_SPI_MASTER) && is_spi) { | |
1052 | struct spi_device *spi = to_spi_device(dev); | |
1053 | ||
1054 | s->regmap = devm_regmap_init_spi(spi, &s->regcfg); | |
1055 | } else | |
1056 | return -ENOTSUPP; | |
1057 | ||
f6544418 | 1058 | if (IS_ERR(s->regmap)) { |
f6544418 | 1059 | dev_err(dev, "Failed to initialize register map\n"); |
10d8b34a | 1060 | return PTR_ERR(s->regmap); |
f6544418 AS |
1061 | } |
1062 | ||
1063 | /* Board specific configure */ | |
10d8b34a AS |
1064 | if (s->pdata->init) |
1065 | s->pdata->init(); | |
1066 | ||
1067 | /* Check device to ensure we are talking to what we expect */ | |
1068 | ret = devtype->detect(dev); | |
1069 | if (ret) | |
1070 | return ret; | |
1071 | ||
1072 | for (i = 0; i < devtype->nr; i++) { | |
1073 | unsigned int offs = i << 5; | |
1074 | ||
1075 | /* Reset port */ | |
1076 | regmap_write(s->regmap, MAX310X_MODE2_REG + offs, | |
1077 | MAX310X_MODE2_RST_BIT); | |
1078 | /* Clear port reset */ | |
1079 | regmap_write(s->regmap, MAX310X_MODE2_REG + offs, 0); | |
1080 | ||
1081 | /* Wait for port startup */ | |
1082 | do { | |
1083 | regmap_read(s->regmap, | |
1084 | MAX310X_BRGDIVLSB_REG + offs, &ret); | |
1085 | } while (ret != 0x01); | |
1086 | ||
1087 | regmap_update_bits(s->regmap, MAX310X_MODE1_REG + offs, | |
1088 | MAX310X_MODE1_AUTOSLEEP_BIT, | |
1089 | MAX310X_MODE1_AUTOSLEEP_BIT); | |
f6544418 AS |
1090 | } |
1091 | ||
10d8b34a AS |
1092 | uartclk = max310x_set_ref_clk(s); |
1093 | dev_dbg(dev, "Reference clock set to %i Hz\n", uartclk); | |
1094 | ||
f6544418 AS |
1095 | /* Register UART driver */ |
1096 | s->uart.owner = THIS_MODULE; | |
f6544418 AS |
1097 | s->uart.dev_name = "ttyMAX"; |
1098 | s->uart.major = MAX310X_MAJOR; | |
1099 | s->uart.minor = MAX310X_MINOR; | |
10d8b34a | 1100 | s->uart.nr = devtype->nr; |
f6544418 AS |
1101 | ret = uart_register_driver(&s->uart); |
1102 | if (ret) { | |
1103 | dev_err(dev, "Registering UART driver failed\n"); | |
10d8b34a | 1104 | return ret; |
f6544418 AS |
1105 | } |
1106 | ||
10d8b34a AS |
1107 | for (i = 0; i < devtype->nr; i++) { |
1108 | /* Initialize port data */ | |
1109 | s->p[i].port.line = i; | |
1110 | s->p[i].port.dev = dev; | |
1111 | s->p[i].port.irq = irq; | |
1112 | s->p[i].port.type = PORT_MAX310X; | |
1113 | s->p[i].port.fifosize = MAX310X_FIFO_SIZE; | |
1114 | s->p[i].port.flags = UPF_SKIP_TEST | UPF_FIXED_TYPE | | |
1115 | UPF_LOW_LATENCY; | |
1116 | s->p[i].port.iotype = UPIO_PORT; | |
1117 | s->p[i].port.iobase = i * 0x20; | |
1118 | s->p[i].port.membase = (void __iomem *)~0; | |
1119 | s->p[i].port.uartclk = uartclk; | |
1120 | s->p[i].port.ops = &max310x_ops; | |
1121 | /* Disable all interrupts */ | |
1122 | max310x_port_write(&s->p[i].port, MAX310X_IRQEN_REG, 0); | |
1123 | /* Clear IRQ status register */ | |
1124 | max310x_port_read(&s->p[i].port, MAX310X_IRQSTS_REG); | |
1125 | /* Enable IRQ pin */ | |
1126 | max310x_port_update(&s->p[i].port, MAX310X_MODE1_REG, | |
1127 | MAX310X_MODE1_IRQSEL_BIT, | |
1128 | MAX310X_MODE1_IRQSEL_BIT); | |
1129 | /* Initialize queue for start TX */ | |
1130 | INIT_WORK(&s->p[i].tx_work, max310x_wq_proc); | |
1131 | /* Register port */ | |
1132 | uart_add_one_port(&s->uart, &s->p[i].port); | |
1133 | /* Go to suspend mode */ | |
1134 | devtype->power(&s->p[i].port, 0); | |
1135 | } | |
f6544418 AS |
1136 | |
1137 | #ifdef CONFIG_GPIOLIB | |
1138 | /* Setup GPIO cotroller */ | |
10d8b34a | 1139 | if (s->pdata->gpio_base) { |
f6544418 AS |
1140 | s->gpio.owner = THIS_MODULE; |
1141 | s->gpio.dev = dev; | |
1142 | s->gpio.label = dev_name(dev); | |
1143 | s->gpio.direction_input = max310x_gpio_direction_input; | |
1144 | s->gpio.get = max310x_gpio_get; | |
1145 | s->gpio.direction_output= max310x_gpio_direction_output; | |
1146 | s->gpio.set = max310x_gpio_set; | |
10d8b34a AS |
1147 | s->gpio.base = s->pdata->gpio_base; |
1148 | s->gpio.ngpio = devtype->nr * 4; | |
273a4b8a | 1149 | s->gpio.can_sleep = 1; |
10d8b34a AS |
1150 | if (!gpiochip_add(&s->gpio)) |
1151 | s->gpio_used = 1; | |
f6544418 AS |
1152 | } else |
1153 | dev_info(dev, "GPIO support not enabled\n"); | |
1154 | #endif | |
1155 | ||
10d8b34a AS |
1156 | /* Setup interrupt */ |
1157 | ret = devm_request_threaded_irq(dev, irq, NULL, max310x_ist, | |
1158 | IRQF_TRIGGER_FALLING | IRQF_ONESHOT, | |
1159 | dev_name(dev), s); | |
1160 | if (ret) { | |
1161 | dev_err(dev, "Unable to reguest IRQ %i\n", irq); | |
1162 | #ifdef CONFIG_GPIOLIB | |
1163 | if (s->gpio_used) | |
1164 | WARN_ON(gpiochip_remove(&s->gpio)); | |
1165 | #endif | |
1166 | } | |
f6544418 | 1167 | |
10d8b34a | 1168 | return ret; |
f6544418 AS |
1169 | |
1170 | err_freq: | |
1171 | dev_err(dev, "Frequency parameter incorrect\n"); | |
10d8b34a | 1172 | return -EINVAL; |
f6544418 AS |
1173 | } |
1174 | ||
10d8b34a | 1175 | static int max310x_remove(struct device *dev) |
f6544418 | 1176 | { |
f6544418 | 1177 | struct max310x_port *s = dev_get_drvdata(dev); |
10d8b34a | 1178 | int i, ret = 0; |
f6544418 | 1179 | |
10d8b34a AS |
1180 | for (i = 0; i < s->uart.nr; i++) { |
1181 | cancel_work_sync(&s->p[i].tx_work); | |
1182 | uart_remove_one_port(&s->uart, &s->p[i].port); | |
1183 | s->devtype->power(&s->p[i].port, 0); | |
1184 | } | |
f6544418 AS |
1185 | |
1186 | uart_unregister_driver(&s->uart); | |
1187 | ||
1188 | #ifdef CONFIG_GPIOLIB | |
10d8b34a | 1189 | if (s->gpio_used) |
23e7c6a7 | 1190 | ret = gpiochip_remove(&s->gpio); |
f6544418 AS |
1191 | #endif |
1192 | ||
f6544418 AS |
1193 | if (s->pdata->exit) |
1194 | s->pdata->exit(); | |
1195 | ||
23e7c6a7 | 1196 | return ret; |
f6544418 AS |
1197 | } |
1198 | ||
10d8b34a AS |
1199 | #ifdef CONFIG_SPI_MASTER |
1200 | static int max310x_spi_probe(struct spi_device *spi) | |
1201 | { | |
1202 | struct max310x_devtype *devtype = | |
1203 | (struct max310x_devtype *)spi_get_device_id(spi)->driver_data; | |
1204 | int ret; | |
1205 | ||
1206 | /* Setup SPI bus */ | |
1207 | spi->bits_per_word = 8; | |
1208 | spi->mode = spi->mode ? : SPI_MODE_0; | |
1209 | spi->max_speed_hz = spi->max_speed_hz ? : 26000000; | |
1210 | ret = spi_setup(spi); | |
1211 | if (ret) { | |
1212 | dev_err(&spi->dev, "SPI setup failed\n"); | |
1213 | return ret; | |
1214 | } | |
1215 | ||
1216 | return max310x_probe(&spi->dev, 1, devtype, spi->irq); | |
1217 | } | |
1218 | ||
1219 | static int max310x_spi_remove(struct spi_device *spi) | |
1220 | { | |
1221 | return max310x_remove(&spi->dev); | |
1222 | } | |
1223 | ||
1224 | static SIMPLE_DEV_PM_OPS(max310x_pm_ops, max310x_suspend, max310x_resume); | |
1225 | ||
f6544418 | 1226 | static const struct spi_device_id max310x_id_table[] = { |
10d8b34a AS |
1227 | { "max3107", (kernel_ulong_t)&max3107_devtype, }, |
1228 | { "max3108", (kernel_ulong_t)&max3108_devtype, }, | |
1838b8c4 | 1229 | { } |
f6544418 AS |
1230 | }; |
1231 | MODULE_DEVICE_TABLE(spi, max310x_id_table); | |
1232 | ||
10d8b34a | 1233 | static struct spi_driver max310x_uart_driver = { |
f6544418 | 1234 | .driver = { |
10d8b34a | 1235 | .name = MAX310X_NAME, |
f6544418 | 1236 | .owner = THIS_MODULE, |
10d8b34a | 1237 | .pm = &max310x_pm_ops, |
f6544418 | 1238 | }, |
10d8b34a AS |
1239 | .probe = max310x_spi_probe, |
1240 | .remove = max310x_spi_remove, | |
f6544418 AS |
1241 | .id_table = max310x_id_table, |
1242 | }; | |
10d8b34a AS |
1243 | module_spi_driver(max310x_uart_driver); |
1244 | #endif | |
f6544418 | 1245 | |
10d8b34a | 1246 | MODULE_LICENSE("GPL"); |
f6544418 AS |
1247 | MODULE_AUTHOR("Alexander Shiyan <shc_work@mail.ru>"); |
1248 | MODULE_DESCRIPTION("MAX310X serial driver"); |