Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * m32r_sio.c | |
3 | * | |
4 | * Driver for M32R serial ports | |
5 | * | |
6 | * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. | |
7 | * Based on drivers/serial/8250.c. | |
8 | * | |
9 | * Copyright (C) 2001 Russell King. | |
10 | * Copyright (C) 2004 Hirokazu Takata <takata at linux-m32r.org> | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or modify | |
13 | * it under the terms of the GNU General Public License as published by | |
14 | * the Free Software Foundation; either version 2 of the License, or | |
15 | * (at your option) any later version. | |
16 | */ | |
17 | ||
18 | /* | |
19 | * A note about mapbase / membase | |
20 | * | |
21 | * mapbase is the physical address of the IO port. Currently, we don't | |
22 | * support this very well, and it may well be dropped from this driver | |
23 | * in future. As such, mapbase should be NULL. | |
24 | * | |
25 | * membase is an 'ioremapped' cookie. This is compatible with the old | |
26 | * serial.c driver, and is currently the preferred form. | |
27 | */ | |
1da177e4 LT |
28 | |
29 | #if defined(CONFIG_SERIAL_M32R_SIO_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) | |
30 | #define SUPPORT_SYSRQ | |
31 | #endif | |
32 | ||
1da177e4 | 33 | #include <linux/tty.h> |
ee160a38 | 34 | #include <linux/tty_flip.h> |
1da177e4 LT |
35 | #include <linux/ioport.h> |
36 | #include <linux/init.h> | |
37 | #include <linux/console.h> | |
38 | #include <linux/sysrq.h> | |
39 | #include <linux/serial.h> | |
1da177e4 LT |
40 | #include <linux/delay.h> |
41 | ||
42 | #include <asm/m32r.h> | |
43 | #include <asm/io.h> | |
44 | #include <asm/irq.h> | |
45 | ||
1da177e4 LT |
46 | #define BAUD_RATE 115200 |
47 | ||
48 | #include <linux/serial_core.h> | |
1da177e4 LT |
49 | #include "m32r_sio_reg.h" |
50 | ||
1da177e4 LT |
51 | #define PASS_LIMIT 256 |
52 | ||
d4dbe374 | 53 | static const struct { |
d4dbe374 JS |
54 | unsigned int port; |
55 | unsigned int irq; | |
d4dbe374 | 56 | } old_serial_port[] = { |
c8e7d143 JS |
57 | #if defined(CONFIG_PLAT_USRV) |
58 | /* PORT IRQ FLAGS */ | |
59 | { 0x3F8, PLD_IRQ_UART0 }, /* ttyS0 */ | |
60 | { 0x2F8, PLD_IRQ_UART1 }, /* ttyS1 */ | |
61 | #elif defined(CONFIG_SERIAL_M32R_PLDSIO) | |
62 | { ((unsigned long)PLD_ESIO0CR), PLD_IRQ_SIO0_RCV }, /* ttyS0 */ | |
63 | #else | |
64 | { M32R_SIO_OFFSET, M32R_IRQ_SIO0_R }, /* ttyS0 */ | |
65 | #endif | |
1da177e4 LT |
66 | }; |
67 | ||
68 | #define UART_NR ARRAY_SIZE(old_serial_port) | |
69 | ||
70 | struct uart_sio_port { | |
71 | struct uart_port port; | |
72 | struct timer_list timer; /* "no irq" timer */ | |
73 | struct list_head list; /* ports on this IRQ */ | |
1da177e4 | 74 | unsigned char ier; |
1da177e4 LT |
75 | }; |
76 | ||
77 | struct irq_info { | |
78 | spinlock_t lock; | |
79 | struct list_head *head; | |
80 | }; | |
81 | ||
82 | static struct irq_info irq_lists[NR_IRQS]; | |
83 | ||
1da177e4 LT |
84 | #ifdef CONFIG_SERIAL_M32R_PLDSIO |
85 | ||
86 | #define __sio_in(x) inw((unsigned long)(x)) | |
87 | #define __sio_out(v,x) outw((v),(unsigned long)(x)) | |
88 | ||
89 | static inline void sio_set_baud_rate(unsigned long baud) | |
90 | { | |
91 | unsigned short sbaud; | |
92 | sbaud = (boot_cpu_data.bus_clock / (baud * 4))-1; | |
93 | __sio_out(sbaud, PLD_ESIO0BAUR); | |
94 | } | |
95 | ||
96 | static void sio_reset(void) | |
97 | { | |
98 | unsigned short tmp; | |
99 | ||
100 | tmp = __sio_in(PLD_ESIO0RXB); | |
101 | tmp = __sio_in(PLD_ESIO0RXB); | |
102 | tmp = __sio_in(PLD_ESIO0CR); | |
103 | sio_set_baud_rate(BAUD_RATE); | |
104 | __sio_out(0x0300, PLD_ESIO0CR); | |
105 | __sio_out(0x0003, PLD_ESIO0CR); | |
106 | } | |
107 | ||
108 | static void sio_init(void) | |
109 | { | |
110 | unsigned short tmp; | |
111 | ||
112 | tmp = __sio_in(PLD_ESIO0RXB); | |
113 | tmp = __sio_in(PLD_ESIO0RXB); | |
114 | tmp = __sio_in(PLD_ESIO0CR); | |
115 | __sio_out(0x0300, PLD_ESIO0CR); | |
116 | __sio_out(0x0003, PLD_ESIO0CR); | |
117 | } | |
118 | ||
119 | static void sio_error(int *status) | |
120 | { | |
121 | printk("SIO0 error[%04x]\n", *status); | |
122 | do { | |
123 | sio_init(); | |
124 | } while ((*status = __sio_in(PLD_ESIO0CR)) != 3); | |
125 | } | |
126 | ||
127 | #else /* not CONFIG_SERIAL_M32R_PLDSIO */ | |
128 | ||
129 | #define __sio_in(x) inl(x) | |
130 | #define __sio_out(v,x) outl((v),(x)) | |
131 | ||
132 | static inline void sio_set_baud_rate(unsigned long baud) | |
133 | { | |
134 | unsigned long i, j; | |
135 | ||
136 | i = boot_cpu_data.bus_clock / (baud * 16); | |
137 | j = (boot_cpu_data.bus_clock - (i * baud * 16)) / baud; | |
138 | i -= 1; | |
139 | j = (j + 1) >> 1; | |
140 | ||
141 | __sio_out(i, M32R_SIO0_BAUR_PORTL); | |
142 | __sio_out(j, M32R_SIO0_RBAUR_PORTL); | |
143 | } | |
144 | ||
145 | static void sio_reset(void) | |
146 | { | |
147 | __sio_out(0x00000300, M32R_SIO0_CR_PORTL); /* init status */ | |
148 | __sio_out(0x00000800, M32R_SIO0_MOD1_PORTL); /* 8bit */ | |
149 | __sio_out(0x00000080, M32R_SIO0_MOD0_PORTL); /* 1stop non */ | |
150 | sio_set_baud_rate(BAUD_RATE); | |
151 | __sio_out(0x00000000, M32R_SIO0_TRCR_PORTL); | |
152 | __sio_out(0x00000003, M32R_SIO0_CR_PORTL); /* RXCEN */ | |
153 | } | |
154 | ||
155 | static void sio_init(void) | |
156 | { | |
157 | unsigned int tmp; | |
158 | ||
159 | tmp = __sio_in(M32R_SIO0_RXB_PORTL); | |
160 | tmp = __sio_in(M32R_SIO0_RXB_PORTL); | |
161 | tmp = __sio_in(M32R_SIO0_STS_PORTL); | |
162 | __sio_out(0x00000003, M32R_SIO0_CR_PORTL); | |
163 | } | |
164 | ||
165 | static void sio_error(int *status) | |
166 | { | |
167 | printk("SIO0 error[%04x]\n", *status); | |
168 | do { | |
169 | sio_init(); | |
170 | } while ((*status = __sio_in(M32R_SIO0_CR_PORTL)) != 3); | |
171 | } | |
172 | ||
173 | #endif /* CONFIG_SERIAL_M32R_PLDSIO */ | |
174 | ||
41c28ff1 | 175 | static unsigned int sio_in(struct uart_sio_port *up, int offset) |
1da177e4 LT |
176 | { |
177 | return __sio_in(up->port.iobase + offset); | |
178 | } | |
179 | ||
41c28ff1 | 180 | static void sio_out(struct uart_sio_port *up, int offset, int value) |
1da177e4 LT |
181 | { |
182 | __sio_out(value, up->port.iobase + offset); | |
183 | } | |
184 | ||
41c28ff1 | 185 | static unsigned int serial_in(struct uart_sio_port *up, int offset) |
1da177e4 LT |
186 | { |
187 | if (!offset) | |
188 | return 0; | |
189 | ||
190 | return __sio_in(offset); | |
191 | } | |
192 | ||
41c28ff1 | 193 | static void serial_out(struct uart_sio_port *up, int offset, int value) |
1da177e4 LT |
194 | { |
195 | if (!offset) | |
196 | return; | |
197 | ||
198 | __sio_out(value, offset); | |
199 | } | |
200 | ||
b129a8cc | 201 | static void m32r_sio_stop_tx(struct uart_port *port) |
1da177e4 | 202 | { |
b6b30d67 FF |
203 | struct uart_sio_port *up = |
204 | container_of(port, struct uart_sio_port, port); | |
1da177e4 LT |
205 | |
206 | if (up->ier & UART_IER_THRI) { | |
207 | up->ier &= ~UART_IER_THRI; | |
208 | serial_out(up, UART_IER, up->ier); | |
209 | } | |
210 | } | |
211 | ||
b129a8cc | 212 | static void m32r_sio_start_tx(struct uart_port *port) |
1da177e4 LT |
213 | { |
214 | #ifdef CONFIG_SERIAL_M32R_PLDSIO | |
b6b30d67 FF |
215 | struct uart_sio_port *up = |
216 | container_of(port, struct uart_sio_port, port); | |
ebd2c8f6 | 217 | struct circ_buf *xmit = &up->port.state->xmit; |
1da177e4 LT |
218 | |
219 | if (!(up->ier & UART_IER_THRI)) { | |
220 | up->ier |= UART_IER_THRI; | |
221 | serial_out(up, UART_IER, up->ier); | |
c557d392 PH |
222 | if (!uart_circ_empty(xmit)) { |
223 | serial_out(up, UART_TX, xmit->buf[xmit->tail]); | |
224 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); | |
225 | up->port.icount.tx++; | |
226 | } | |
1da177e4 LT |
227 | } |
228 | while((serial_in(up, UART_LSR) & UART_EMPTY) != UART_EMPTY); | |
229 | #else | |
b6b30d67 FF |
230 | struct uart_sio_port *up = |
231 | container_of(port, struct uart_sio_port, port); | |
1da177e4 LT |
232 | |
233 | if (!(up->ier & UART_IER_THRI)) { | |
234 | up->ier |= UART_IER_THRI; | |
235 | serial_out(up, UART_IER, up->ier); | |
236 | } | |
237 | #endif | |
238 | } | |
239 | ||
240 | static void m32r_sio_stop_rx(struct uart_port *port) | |
241 | { | |
b6b30d67 FF |
242 | struct uart_sio_port *up = |
243 | container_of(port, struct uart_sio_port, port); | |
1da177e4 LT |
244 | |
245 | up->ier &= ~UART_IER_RLSI; | |
246 | up->port.read_status_mask &= ~UART_LSR_DR; | |
247 | serial_out(up, UART_IER, up->ier); | |
248 | } | |
249 | ||
250 | static void m32r_sio_enable_ms(struct uart_port *port) | |
251 | { | |
b6b30d67 FF |
252 | struct uart_sio_port *up = |
253 | container_of(port, struct uart_sio_port, port); | |
1da177e4 LT |
254 | |
255 | up->ier |= UART_IER_MSI; | |
256 | serial_out(up, UART_IER, up->ier); | |
257 | } | |
258 | ||
7d12e780 | 259 | static void receive_chars(struct uart_sio_port *up, int *status) |
1da177e4 | 260 | { |
92a19f9c | 261 | struct tty_port *port = &up->port.state->port; |
1da177e4 | 262 | unsigned char ch; |
33f0f88f | 263 | unsigned char flag; |
1da177e4 LT |
264 | int max_count = 256; |
265 | ||
266 | do { | |
1da177e4 | 267 | ch = sio_in(up, SIORXB); |
33f0f88f | 268 | flag = TTY_NORMAL; |
1da177e4 LT |
269 | up->port.icount.rx++; |
270 | ||
271 | if (unlikely(*status & (UART_LSR_BI | UART_LSR_PE | | |
272 | UART_LSR_FE | UART_LSR_OE))) { | |
273 | /* | |
274 | * For statistics only | |
275 | */ | |
276 | if (*status & UART_LSR_BI) { | |
277 | *status &= ~(UART_LSR_FE | UART_LSR_PE); | |
278 | up->port.icount.brk++; | |
279 | /* | |
280 | * We do the SysRQ and SAK checking | |
281 | * here because otherwise the break | |
282 | * may get masked by ignore_status_mask | |
283 | * or read_status_mask. | |
284 | */ | |
285 | if (uart_handle_break(&up->port)) | |
286 | goto ignore_char; | |
287 | } else if (*status & UART_LSR_PE) | |
288 | up->port.icount.parity++; | |
289 | else if (*status & UART_LSR_FE) | |
290 | up->port.icount.frame++; | |
291 | if (*status & UART_LSR_OE) | |
292 | up->port.icount.overrun++; | |
293 | ||
294 | /* | |
295 | * Mask off conditions which should be ingored. | |
296 | */ | |
297 | *status &= up->port.read_status_mask; | |
298 | ||
1da177e4 | 299 | if (*status & UART_LSR_BI) { |
ad245aa2 | 300 | pr_debug("handling break....\n"); |
33f0f88f | 301 | flag = TTY_BREAK; |
1da177e4 | 302 | } else if (*status & UART_LSR_PE) |
33f0f88f | 303 | flag = TTY_PARITY; |
1da177e4 | 304 | else if (*status & UART_LSR_FE) |
33f0f88f | 305 | flag = TTY_FRAME; |
1da177e4 | 306 | } |
7d12e780 | 307 | if (uart_handle_sysrq_char(&up->port, ch)) |
1da177e4 | 308 | goto ignore_char; |
33f0f88f | 309 | if ((*status & up->port.ignore_status_mask) == 0) |
92a19f9c | 310 | tty_insert_flip_char(port, ch, flag); |
33f0f88f AC |
311 | |
312 | if (*status & UART_LSR_OE) { | |
1da177e4 LT |
313 | /* |
314 | * Overrun is special, since it's reported | |
315 | * immediately, and doesn't affect the current | |
316 | * character. | |
317 | */ | |
92a19f9c | 318 | tty_insert_flip_char(port, 0, TTY_OVERRUN); |
1da177e4 LT |
319 | } |
320 | ignore_char: | |
321 | *status = serial_in(up, UART_LSR); | |
322 | } while ((*status & UART_LSR_DR) && (max_count-- > 0)); | |
af89f837 VK |
323 | |
324 | spin_unlock(&up->port.lock); | |
2e124b4a | 325 | tty_flip_buffer_push(port); |
af89f837 | 326 | spin_lock(&up->port.lock); |
1da177e4 LT |
327 | } |
328 | ||
41c28ff1 | 329 | static void transmit_chars(struct uart_sio_port *up) |
1da177e4 | 330 | { |
ebd2c8f6 | 331 | struct circ_buf *xmit = &up->port.state->xmit; |
1da177e4 LT |
332 | int count; |
333 | ||
334 | if (up->port.x_char) { | |
335 | #ifndef CONFIG_SERIAL_M32R_PLDSIO /* XXX */ | |
336 | serial_out(up, UART_TX, up->port.x_char); | |
337 | #endif | |
338 | up->port.icount.tx++; | |
339 | up->port.x_char = 0; | |
340 | return; | |
341 | } | |
342 | if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) { | |
b129a8cc | 343 | m32r_sio_stop_tx(&up->port); |
1da177e4 LT |
344 | return; |
345 | } | |
346 | ||
347 | count = up->port.fifosize; | |
348 | do { | |
349 | serial_out(up, UART_TX, xmit->buf[xmit->tail]); | |
350 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); | |
351 | up->port.icount.tx++; | |
352 | if (uart_circ_empty(xmit)) | |
353 | break; | |
022d917d | 354 | while (!(serial_in(up, UART_LSR) & UART_LSR_THRE)); |
1da177e4 LT |
355 | |
356 | } while (--count > 0); | |
357 | ||
358 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
359 | uart_write_wakeup(&up->port); | |
360 | ||
ad245aa2 | 361 | pr_debug("THRE...\n"); |
1da177e4 LT |
362 | |
363 | if (uart_circ_empty(xmit)) | |
b129a8cc | 364 | m32r_sio_stop_tx(&up->port); |
1da177e4 LT |
365 | } |
366 | ||
367 | /* | |
368 | * This handles the interrupt from one port. | |
369 | */ | |
370 | static inline void m32r_sio_handle_port(struct uart_sio_port *up, | |
7d12e780 | 371 | unsigned int status) |
1da177e4 | 372 | { |
ad245aa2 | 373 | pr_debug("status = %x...\n", status); |
1da177e4 LT |
374 | |
375 | if (status & 0x04) | |
7d12e780 | 376 | receive_chars(up, &status); |
1da177e4 LT |
377 | if (status & 0x01) |
378 | transmit_chars(up); | |
379 | } | |
380 | ||
381 | /* | |
382 | * This is the serial driver's interrupt routine. | |
383 | * | |
384 | * Arjan thinks the old way was overly complex, so it got simplified. | |
385 | * Alan disagrees, saying that need the complexity to handle the weird | |
386 | * nature of ISA shared interrupts. (This is a special exception.) | |
387 | * | |
388 | * In order to handle ISA shared interrupts properly, we need to check | |
389 | * that all ports have been serviced, and therefore the ISA interrupt | |
390 | * line has been de-asserted. | |
391 | * | |
392 | * This means we need to loop through all ports. checking that they | |
393 | * don't have an interrupt pending. | |
394 | */ | |
7d12e780 | 395 | static irqreturn_t m32r_sio_interrupt(int irq, void *dev_id) |
1da177e4 LT |
396 | { |
397 | struct irq_info *i = dev_id; | |
398 | struct list_head *l, *end = NULL; | |
399 | int pass_counter = 0; | |
400 | ||
ad245aa2 | 401 | pr_debug("m32r_sio_interrupt(%d)...\n", irq); |
1da177e4 LT |
402 | |
403 | #ifdef CONFIG_SERIAL_M32R_PLDSIO | |
404 | // if (irq == PLD_IRQ_SIO0_SND) | |
405 | // irq = PLD_IRQ_SIO0_RCV; | |
406 | #else | |
407 | if (irq == M32R_IRQ_SIO0_S) | |
408 | irq = M32R_IRQ_SIO0_R; | |
409 | #endif | |
410 | ||
411 | spin_lock(&i->lock); | |
412 | ||
413 | l = i->head; | |
414 | do { | |
415 | struct uart_sio_port *up; | |
416 | unsigned int sts; | |
417 | ||
418 | up = list_entry(l, struct uart_sio_port, list); | |
419 | ||
420 | sts = sio_in(up, SIOSTS); | |
421 | if (sts & 0x5) { | |
422 | spin_lock(&up->port.lock); | |
7d12e780 | 423 | m32r_sio_handle_port(up, sts); |
1da177e4 LT |
424 | spin_unlock(&up->port.lock); |
425 | ||
426 | end = NULL; | |
427 | } else if (end == NULL) | |
428 | end = l; | |
429 | ||
430 | l = l->next; | |
431 | ||
432 | if (l == i->head && pass_counter++ > PASS_LIMIT) { | |
433 | if (sts & 0xe0) | |
434 | sio_error(&sts); | |
435 | break; | |
436 | } | |
437 | } while (l != end); | |
438 | ||
439 | spin_unlock(&i->lock); | |
440 | ||
ad245aa2 | 441 | pr_debug("end.\n"); |
1da177e4 LT |
442 | |
443 | return IRQ_HANDLED; | |
444 | } | |
445 | ||
446 | /* | |
447 | * To support ISA shared interrupts, we need to have one interrupt | |
448 | * handler that ensures that the IRQ line has been deasserted | |
449 | * before returning. Failing to do this will result in the IRQ | |
450 | * line being stuck active, and, since ISA irqs are edge triggered, | |
451 | * no more IRQs will be seen. | |
452 | */ | |
453 | static void serial_do_unlink(struct irq_info *i, struct uart_sio_port *up) | |
454 | { | |
455 | spin_lock_irq(&i->lock); | |
456 | ||
457 | if (!list_empty(i->head)) { | |
458 | if (i->head == &up->list) | |
459 | i->head = i->head->next; | |
460 | list_del(&up->list); | |
461 | } else { | |
462 | BUG_ON(i->head != &up->list); | |
463 | i->head = NULL; | |
464 | } | |
465 | ||
466 | spin_unlock_irq(&i->lock); | |
467 | } | |
468 | ||
469 | static int serial_link_irq_chain(struct uart_sio_port *up) | |
470 | { | |
471 | struct irq_info *i = irq_lists + up->port.irq; | |
dab8f496 | 472 | int ret, irq_flags = 0; |
1da177e4 LT |
473 | |
474 | spin_lock_irq(&i->lock); | |
475 | ||
476 | if (i->head) { | |
477 | list_add(&up->list, i->head); | |
478 | spin_unlock_irq(&i->lock); | |
479 | ||
480 | ret = 0; | |
481 | } else { | |
482 | INIT_LIST_HEAD(&up->list); | |
483 | i->head = &up->list; | |
484 | spin_unlock_irq(&i->lock); | |
485 | ||
486 | ret = request_irq(up->port.irq, m32r_sio_interrupt, | |
487 | irq_flags, "SIO0-RX", i); | |
488 | ret |= request_irq(up->port.irq + 1, m32r_sio_interrupt, | |
489 | irq_flags, "SIO0-TX", i); | |
490 | if (ret < 0) | |
491 | serial_do_unlink(i, up); | |
492 | } | |
493 | ||
494 | return ret; | |
495 | } | |
496 | ||
497 | static void serial_unlink_irq_chain(struct uart_sio_port *up) | |
498 | { | |
499 | struct irq_info *i = irq_lists + up->port.irq; | |
500 | ||
501 | BUG_ON(i->head == NULL); | |
502 | ||
503 | if (list_empty(i->head)) { | |
504 | free_irq(up->port.irq, i); | |
505 | free_irq(up->port.irq + 1, i); | |
506 | } | |
507 | ||
508 | serial_do_unlink(i, up); | |
509 | } | |
510 | ||
511 | /* | |
512 | * This function is used to handle ports that do not have an interrupt. | |
513 | */ | |
514 | static void m32r_sio_timeout(unsigned long data) | |
515 | { | |
516 | struct uart_sio_port *up = (struct uart_sio_port *)data; | |
517 | unsigned int timeout; | |
518 | unsigned int sts; | |
519 | ||
520 | sts = sio_in(up, SIOSTS); | |
521 | if (sts & 0x5) { | |
522 | spin_lock(&up->port.lock); | |
9c8e7f5c | 523 | m32r_sio_handle_port(up, sts); |
1da177e4 LT |
524 | spin_unlock(&up->port.lock); |
525 | } | |
526 | ||
527 | timeout = up->port.timeout; | |
528 | timeout = timeout > 6 ? (timeout / 2 - 2) : 1; | |
529 | mod_timer(&up->timer, jiffies + timeout); | |
530 | } | |
531 | ||
532 | static unsigned int m32r_sio_tx_empty(struct uart_port *port) | |
533 | { | |
b6b30d67 FF |
534 | struct uart_sio_port *up = |
535 | container_of(port, struct uart_sio_port, port); | |
1da177e4 LT |
536 | unsigned long flags; |
537 | unsigned int ret; | |
538 | ||
539 | spin_lock_irqsave(&up->port.lock, flags); | |
540 | ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0; | |
541 | spin_unlock_irqrestore(&up->port.lock, flags); | |
542 | ||
543 | return ret; | |
544 | } | |
545 | ||
546 | static unsigned int m32r_sio_get_mctrl(struct uart_port *port) | |
547 | { | |
548 | return 0; | |
549 | } | |
550 | ||
551 | static void m32r_sio_set_mctrl(struct uart_port *port, unsigned int mctrl) | |
552 | { | |
553 | ||
554 | } | |
555 | ||
556 | static void m32r_sio_break_ctl(struct uart_port *port, int break_state) | |
557 | { | |
558 | ||
559 | } | |
560 | ||
561 | static int m32r_sio_startup(struct uart_port *port) | |
562 | { | |
b6b30d67 FF |
563 | struct uart_sio_port *up = |
564 | container_of(port, struct uart_sio_port, port); | |
1da177e4 LT |
565 | int retval; |
566 | ||
567 | sio_init(); | |
568 | ||
569 | /* | |
570 | * If the "interrupt" for this port doesn't correspond with any | |
571 | * hardware interrupt, we use a timer-based system. The original | |
572 | * driver used to do this with IRQ0. | |
573 | */ | |
d4e33fac | 574 | if (!up->port.irq) { |
1da177e4 LT |
575 | unsigned int timeout = up->port.timeout; |
576 | ||
577 | timeout = timeout > 6 ? (timeout / 2 - 2) : 1; | |
578 | ||
579 | up->timer.data = (unsigned long)up; | |
580 | mod_timer(&up->timer, jiffies + timeout); | |
581 | } else { | |
582 | retval = serial_link_irq_chain(up); | |
583 | if (retval) | |
584 | return retval; | |
585 | } | |
586 | ||
587 | /* | |
588 | * Finally, enable interrupts. Note: Modem status interrupts | |
589 | * are set via set_termios(), which will be occurring imminently | |
590 | * anyway, so we don't enable them here. | |
591 | * - M32R_SIO: 0x0c | |
592 | * - M32R_PLDSIO: 0x04 | |
593 | */ | |
594 | up->ier = UART_IER_MSI | UART_IER_RLSI | UART_IER_RDI; | |
595 | sio_out(up, SIOTRCR, up->ier); | |
596 | ||
597 | /* | |
598 | * And clear the interrupt registers again for luck. | |
599 | */ | |
600 | sio_reset(); | |
601 | ||
602 | return 0; | |
603 | } | |
604 | ||
605 | static void m32r_sio_shutdown(struct uart_port *port) | |
606 | { | |
b6b30d67 FF |
607 | struct uart_sio_port *up = |
608 | container_of(port, struct uart_sio_port, port); | |
1da177e4 LT |
609 | |
610 | /* | |
611 | * Disable interrupts from this port | |
612 | */ | |
613 | up->ier = 0; | |
614 | sio_out(up, SIOTRCR, 0); | |
615 | ||
616 | /* | |
617 | * Disable break condition and FIFOs | |
618 | */ | |
619 | ||
620 | sio_init(); | |
621 | ||
d4e33fac | 622 | if (!up->port.irq) |
1da177e4 LT |
623 | del_timer_sync(&up->timer); |
624 | else | |
625 | serial_unlink_irq_chain(up); | |
626 | } | |
627 | ||
628 | static unsigned int m32r_sio_get_divisor(struct uart_port *port, | |
629 | unsigned int baud) | |
630 | { | |
631 | return uart_get_divisor(port, baud); | |
632 | } | |
633 | ||
634 | static void m32r_sio_set_termios(struct uart_port *port, | |
606d099c | 635 | struct ktermios *termios, struct ktermios *old) |
1da177e4 | 636 | { |
b6b30d67 FF |
637 | struct uart_sio_port *up = |
638 | container_of(port, struct uart_sio_port, port); | |
1da177e4 LT |
639 | unsigned char cval = 0; |
640 | unsigned long flags; | |
641 | unsigned int baud, quot; | |
642 | ||
643 | switch (termios->c_cflag & CSIZE) { | |
644 | case CS5: | |
0a8b80c5 | 645 | cval = UART_LCR_WLEN5; |
1da177e4 LT |
646 | break; |
647 | case CS6: | |
0a8b80c5 | 648 | cval = UART_LCR_WLEN6; |
1da177e4 LT |
649 | break; |
650 | case CS7: | |
0a8b80c5 | 651 | cval = UART_LCR_WLEN7; |
1da177e4 LT |
652 | break; |
653 | default: | |
654 | case CS8: | |
0a8b80c5 | 655 | cval = UART_LCR_WLEN8; |
1da177e4 LT |
656 | break; |
657 | } | |
658 | ||
659 | if (termios->c_cflag & CSTOPB) | |
0a8b80c5 | 660 | cval |= UART_LCR_STOP; |
1da177e4 LT |
661 | if (termios->c_cflag & PARENB) |
662 | cval |= UART_LCR_PARITY; | |
663 | if (!(termios->c_cflag & PARODD)) | |
664 | cval |= UART_LCR_EPAR; | |
665 | #ifdef CMSPAR | |
666 | if (termios->c_cflag & CMSPAR) | |
667 | cval |= UART_LCR_SPAR; | |
668 | #endif | |
669 | ||
670 | /* | |
671 | * Ask the core to calculate the divisor for us. | |
672 | */ | |
673 | #ifdef CONFIG_SERIAL_M32R_PLDSIO | |
674 | baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/4); | |
675 | #else | |
676 | baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16); | |
677 | #endif | |
678 | quot = m32r_sio_get_divisor(port, baud); | |
679 | ||
680 | /* | |
681 | * Ok, we're now changing the port state. Do it with | |
682 | * interrupts disabled. | |
683 | */ | |
684 | spin_lock_irqsave(&up->port.lock, flags); | |
685 | ||
686 | sio_set_baud_rate(baud); | |
687 | ||
688 | /* | |
689 | * Update the per-port timeout. | |
690 | */ | |
691 | uart_update_timeout(port, termios->c_cflag, baud); | |
692 | ||
693 | up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR; | |
694 | if (termios->c_iflag & INPCK) | |
695 | up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE; | |
ef8b9ddc | 696 | if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) |
1da177e4 LT |
697 | up->port.read_status_mask |= UART_LSR_BI; |
698 | ||
699 | /* | |
700 | * Characteres to ignore | |
701 | */ | |
702 | up->port.ignore_status_mask = 0; | |
703 | if (termios->c_iflag & IGNPAR) | |
704 | up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE; | |
705 | if (termios->c_iflag & IGNBRK) { | |
706 | up->port.ignore_status_mask |= UART_LSR_BI; | |
707 | /* | |
708 | * If we're ignoring parity and break indicators, | |
709 | * ignore overruns too (for real raw support). | |
710 | */ | |
711 | if (termios->c_iflag & IGNPAR) | |
712 | up->port.ignore_status_mask |= UART_LSR_OE; | |
713 | } | |
714 | ||
715 | /* | |
716 | * ignore all characters if CREAD is not set | |
717 | */ | |
718 | if ((termios->c_cflag & CREAD) == 0) | |
719 | up->port.ignore_status_mask |= UART_LSR_DR; | |
720 | ||
721 | /* | |
722 | * CTS flow control flag and modem status interrupts | |
723 | */ | |
724 | up->ier &= ~UART_IER_MSI; | |
725 | if (UART_ENABLE_MS(&up->port, termios->c_cflag)) | |
726 | up->ier |= UART_IER_MSI; | |
727 | ||
728 | serial_out(up, UART_IER, up->ier); | |
729 | ||
1da177e4 LT |
730 | spin_unlock_irqrestore(&up->port.lock, flags); |
731 | } | |
732 | ||
1da177e4 LT |
733 | /* |
734 | * Resource handling. This is complicated by the fact that resources | |
735 | * depend on the port type. Maybe we should be claiming the standard | |
736 | * 8250 ports, and then trying to get other resources as necessary? | |
737 | */ | |
738 | static int | |
739 | m32r_sio_request_std_resource(struct uart_sio_port *up, struct resource **res) | |
740 | { | |
741 | unsigned int size = 8 << up->port.regshift; | |
742 | #ifndef CONFIG_SERIAL_M32R_PLDSIO | |
743 | unsigned long start; | |
744 | #endif | |
745 | int ret = 0; | |
746 | ||
747 | switch (up->port.iotype) { | |
748 | case UPIO_MEM: | |
749 | if (up->port.mapbase) { | |
750 | #ifdef CONFIG_SERIAL_M32R_PLDSIO | |
751 | *res = request_mem_region(up->port.mapbase, size, "serial"); | |
752 | #else | |
753 | start = up->port.mapbase; | |
754 | *res = request_mem_region(start, size, "serial"); | |
755 | #endif | |
756 | if (!*res) | |
757 | ret = -EBUSY; | |
758 | } | |
759 | break; | |
760 | ||
761 | case UPIO_PORT: | |
762 | *res = request_region(up->port.iobase, size, "serial"); | |
763 | if (!*res) | |
764 | ret = -EBUSY; | |
765 | break; | |
766 | } | |
767 | return ret; | |
768 | } | |
769 | ||
770 | static void m32r_sio_release_port(struct uart_port *port) | |
771 | { | |
b6b30d67 FF |
772 | struct uart_sio_port *up = |
773 | container_of(port, struct uart_sio_port, port); | |
1da177e4 LT |
774 | unsigned long start, offset = 0, size = 0; |
775 | ||
776 | size <<= up->port.regshift; | |
777 | ||
778 | switch (up->port.iotype) { | |
779 | case UPIO_MEM: | |
780 | if (up->port.mapbase) { | |
781 | /* | |
782 | * Unmap the area. | |
783 | */ | |
784 | iounmap(up->port.membase); | |
785 | up->port.membase = NULL; | |
786 | ||
787 | start = up->port.mapbase; | |
788 | ||
789 | if (size) | |
790 | release_mem_region(start + offset, size); | |
791 | release_mem_region(start, 8 << up->port.regshift); | |
792 | } | |
793 | break; | |
794 | ||
795 | case UPIO_PORT: | |
796 | start = up->port.iobase; | |
797 | ||
798 | if (size) | |
799 | release_region(start + offset, size); | |
800 | release_region(start + offset, 8 << up->port.regshift); | |
801 | break; | |
802 | ||
803 | default: | |
804 | break; | |
805 | } | |
806 | } | |
807 | ||
808 | static int m32r_sio_request_port(struct uart_port *port) | |
809 | { | |
b6b30d67 FF |
810 | struct uart_sio_port *up = |
811 | container_of(port, struct uart_sio_port, port); | |
1da177e4 LT |
812 | struct resource *res = NULL; |
813 | int ret = 0; | |
814 | ||
815 | ret = m32r_sio_request_std_resource(up, &res); | |
816 | ||
817 | /* | |
818 | * If we have a mapbase, then request that as well. | |
819 | */ | |
820 | if (ret == 0 && up->port.flags & UPF_IOREMAP) { | |
28f65c11 | 821 | int size = resource_size(res); |
1da177e4 LT |
822 | |
823 | up->port.membase = ioremap(up->port.mapbase, size); | |
824 | if (!up->port.membase) | |
825 | ret = -ENOMEM; | |
826 | } | |
827 | ||
828 | if (ret < 0) { | |
829 | if (res) | |
830 | release_resource(res); | |
831 | } | |
832 | ||
833 | return ret; | |
834 | } | |
835 | ||
1e806c50 | 836 | static void m32r_sio_config_port(struct uart_port *port, int unused) |
1da177e4 | 837 | { |
b6b30d67 FF |
838 | struct uart_sio_port *up = |
839 | container_of(port, struct uart_sio_port, port); | |
1e806c50 | 840 | unsigned long flags; |
1da177e4 LT |
841 | |
842 | spin_lock_irqsave(&up->port.lock, flags); | |
843 | ||
b8ede90c | 844 | up->port.fifosize = 1; |
1da177e4 LT |
845 | |
846 | spin_unlock_irqrestore(&up->port.lock, flags); | |
847 | } | |
848 | ||
849 | static int | |
850 | m32r_sio_verify_port(struct uart_port *port, struct serial_struct *ser) | |
851 | { | |
b8ede90c | 852 | if (ser->irq >= nr_irqs || ser->irq < 0 || ser->baud_base < 9600) |
1da177e4 LT |
853 | return -EINVAL; |
854 | return 0; | |
855 | } | |
856 | ||
1da177e4 LT |
857 | static struct uart_ops m32r_sio_pops = { |
858 | .tx_empty = m32r_sio_tx_empty, | |
859 | .set_mctrl = m32r_sio_set_mctrl, | |
860 | .get_mctrl = m32r_sio_get_mctrl, | |
861 | .stop_tx = m32r_sio_stop_tx, | |
862 | .start_tx = m32r_sio_start_tx, | |
863 | .stop_rx = m32r_sio_stop_rx, | |
864 | .enable_ms = m32r_sio_enable_ms, | |
865 | .break_ctl = m32r_sio_break_ctl, | |
866 | .startup = m32r_sio_startup, | |
867 | .shutdown = m32r_sio_shutdown, | |
868 | .set_termios = m32r_sio_set_termios, | |
1da177e4 LT |
869 | .release_port = m32r_sio_release_port, |
870 | .request_port = m32r_sio_request_port, | |
871 | .config_port = m32r_sio_config_port, | |
872 | .verify_port = m32r_sio_verify_port, | |
873 | }; | |
874 | ||
875 | static struct uart_sio_port m32r_sio_ports[UART_NR]; | |
876 | ||
877 | static void __init m32r_sio_init_ports(void) | |
878 | { | |
879 | struct uart_sio_port *up; | |
880 | static int first = 1; | |
881 | int i; | |
882 | ||
883 | if (!first) | |
884 | return; | |
885 | first = 0; | |
886 | ||
c8e7d143 | 887 | for (i = 0, up = m32r_sio_ports; i < UART_NR; i++, up++) { |
1da177e4 LT |
888 | up->port.iobase = old_serial_port[i].port; |
889 | up->port.irq = irq_canonicalize(old_serial_port[i].irq); | |
c8e7d143 | 890 | up->port.uartclk = BAUD_RATE * 16; |
6137b7a6 | 891 | up->port.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST; |
c8e7d143 JS |
892 | up->port.membase = 0; |
893 | up->port.iotype = 0; | |
894 | up->port.regshift = 0; | |
1da177e4 LT |
895 | up->port.ops = &m32r_sio_pops; |
896 | } | |
897 | } | |
898 | ||
899 | static void __init m32r_sio_register_ports(struct uart_driver *drv) | |
900 | { | |
901 | int i; | |
902 | ||
903 | m32r_sio_init_ports(); | |
904 | ||
905 | for (i = 0; i < UART_NR; i++) { | |
906 | struct uart_sio_port *up = &m32r_sio_ports[i]; | |
907 | ||
908 | up->port.line = i; | |
909 | up->port.ops = &m32r_sio_pops; | |
910 | init_timer(&up->timer); | |
911 | up->timer.function = m32r_sio_timeout; | |
912 | ||
1da177e4 LT |
913 | uart_add_one_port(drv, &up->port); |
914 | } | |
915 | } | |
916 | ||
917 | #ifdef CONFIG_SERIAL_M32R_SIO_CONSOLE | |
918 | ||
919 | /* | |
920 | * Wait for transmitter & holding register to empty | |
921 | */ | |
9cdb9332 | 922 | static void wait_for_xmitr(struct uart_sio_port *up) |
1da177e4 LT |
923 | { |
924 | unsigned int status, tmout = 10000; | |
925 | ||
926 | /* Wait up to 10ms for the character(s) to be sent. */ | |
927 | do { | |
928 | status = sio_in(up, SIOSTS); | |
929 | ||
930 | if (--tmout == 0) | |
931 | break; | |
932 | udelay(1); | |
933 | } while ((status & UART_EMPTY) != UART_EMPTY); | |
934 | ||
935 | /* Wait up to 1s for flow control if necessary */ | |
936 | if (up->port.flags & UPF_CONS_FLOW) { | |
937 | tmout = 1000000; | |
938 | while (--tmout) | |
939 | udelay(1); | |
940 | } | |
941 | } | |
942 | ||
d358788f RK |
943 | static void m32r_sio_console_putchar(struct uart_port *port, int ch) |
944 | { | |
b6b30d67 FF |
945 | struct uart_sio_port *up = |
946 | container_of(port, struct uart_sio_port, port); | |
d358788f RK |
947 | |
948 | wait_for_xmitr(up); | |
949 | sio_out(up, SIOTXB, ch); | |
950 | } | |
951 | ||
1da177e4 LT |
952 | /* |
953 | * Print a string to the serial port trying not to disturb | |
954 | * any possible real use of the port... | |
955 | * | |
956 | * The console_lock must be held when we get here. | |
957 | */ | |
958 | static void m32r_sio_console_write(struct console *co, const char *s, | |
959 | unsigned int count) | |
960 | { | |
961 | struct uart_sio_port *up = &m32r_sio_ports[co->index]; | |
962 | unsigned int ier; | |
1da177e4 LT |
963 | |
964 | /* | |
965 | * First save the UER then disable the interrupts | |
966 | */ | |
967 | ier = sio_in(up, SIOTRCR); | |
968 | sio_out(up, SIOTRCR, 0); | |
969 | ||
d358788f | 970 | uart_console_write(&up->port, s, count, m32r_sio_console_putchar); |
1da177e4 LT |
971 | |
972 | /* | |
973 | * Finally, wait for transmitter to become empty | |
974 | * and restore the IER | |
975 | */ | |
976 | wait_for_xmitr(up); | |
977 | sio_out(up, SIOTRCR, ier); | |
978 | } | |
979 | ||
980 | static int __init m32r_sio_console_setup(struct console *co, char *options) | |
981 | { | |
982 | struct uart_port *port; | |
983 | int baud = 9600; | |
984 | int bits = 8; | |
985 | int parity = 'n'; | |
986 | int flow = 'n'; | |
987 | ||
988 | /* | |
989 | * Check whether an invalid uart number has been specified, and | |
990 | * if so, search for the first available port that does have | |
991 | * console support. | |
992 | */ | |
993 | if (co->index >= UART_NR) | |
994 | co->index = 0; | |
995 | port = &m32r_sio_ports[co->index].port; | |
996 | ||
997 | /* | |
998 | * Temporary fix. | |
999 | */ | |
1000 | spin_lock_init(&port->lock); | |
1001 | ||
1002 | if (options) | |
1003 | uart_parse_options(options, &baud, &parity, &bits, &flow); | |
1004 | ||
1005 | return uart_set_options(port, co, baud, parity, bits, flow); | |
1006 | } | |
1007 | ||
a828b8e4 | 1008 | static struct uart_driver m32r_sio_reg; |
1da177e4 LT |
1009 | static struct console m32r_sio_console = { |
1010 | .name = "ttyS", | |
1011 | .write = m32r_sio_console_write, | |
1012 | .device = uart_console_device, | |
1013 | .setup = m32r_sio_console_setup, | |
1014 | .flags = CON_PRINTBUFFER, | |
1015 | .index = -1, | |
1016 | .data = &m32r_sio_reg, | |
1017 | }; | |
1018 | ||
1019 | static int __init m32r_sio_console_init(void) | |
1020 | { | |
1021 | sio_reset(); | |
1022 | sio_init(); | |
1023 | m32r_sio_init_ports(); | |
1024 | register_console(&m32r_sio_console); | |
1025 | return 0; | |
1026 | } | |
1027 | console_initcall(m32r_sio_console_init); | |
1028 | ||
1029 | #define M32R_SIO_CONSOLE &m32r_sio_console | |
1030 | #else | |
1031 | #define M32R_SIO_CONSOLE NULL | |
1032 | #endif | |
1033 | ||
1034 | static struct uart_driver m32r_sio_reg = { | |
1035 | .owner = THIS_MODULE, | |
1036 | .driver_name = "sio", | |
1da177e4 LT |
1037 | .dev_name = "ttyS", |
1038 | .major = TTY_MAJOR, | |
1039 | .minor = 64, | |
1040 | .nr = UART_NR, | |
1041 | .cons = M32R_SIO_CONSOLE, | |
1042 | }; | |
1043 | ||
1da177e4 LT |
1044 | static int __init m32r_sio_init(void) |
1045 | { | |
1046 | int ret, i; | |
1047 | ||
d87a6d95 | 1048 | printk(KERN_INFO "Serial: M32R SIO driver\n"); |
1da177e4 | 1049 | |
a62c4133 | 1050 | for (i = 0; i < nr_irqs; i++) |
1da177e4 LT |
1051 | spin_lock_init(&irq_lists[i].lock); |
1052 | ||
1053 | ret = uart_register_driver(&m32r_sio_reg); | |
1054 | if (ret >= 0) | |
1055 | m32r_sio_register_ports(&m32r_sio_reg); | |
1056 | ||
1057 | return ret; | |
1058 | } | |
a10aebe2 | 1059 | device_initcall(m32r_sio_init); |