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tty: add SPDX identifiers to all remaining files in drivers/tty/
[linux-2.6-block.git] / drivers / tty / serial / lpc32xx_hs.c
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e3b3d0f5 1// SPDX-License-Identifier: GPL-2.0+
596f93f5
RS		 2/*
3 * High Speed Serial Ports on NXP LPC32xx SoC
4 *
5 * Authors: Kevin Wells <kevin.wells@nxp.com>
6 * Roland Stigge <stigge@antcom.de>
7 *
8 * Copyright (C) 2010 NXP Semiconductors
9 * Copyright (C) 2012 Roland Stigge
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 */
21
22#include <linux/module.h>
23#include <linux/ioport.h>
24#include <linux/init.h>
25#include <linux/console.h>
26#include <linux/sysrq.h>
27#include <linux/tty.h>
28#include <linux/tty_flip.h>
29#include <linux/serial_core.h>
30#include <linux/serial.h>
31#include <linux/platform_device.h>
32#include <linux/delay.h>
33#include <linux/nmi.h>
34#include <linux/io.h>
35#include <linux/irq.h>
36#include <linux/gpio.h>
37#include <linux/of.h>
38#include <mach/platform.h>
39#include <mach/hardware.h>
40
41/*
42 * High Speed UART register offsets
43 */
44#define LPC32XX_HSUART_FIFO(x) ((x) + 0x00)
45#define LPC32XX_HSUART_LEVEL(x) ((x) + 0x04)
46#define LPC32XX_HSUART_IIR(x) ((x) + 0x08)
47#define LPC32XX_HSUART_CTRL(x) ((x) + 0x0C)
48#define LPC32XX_HSUART_RATE(x) ((x) + 0x10)
49
50#define LPC32XX_HSU_BREAK_DATA (1 << 10)
51#define LPC32XX_HSU_ERROR_DATA (1 << 9)
52#define LPC32XX_HSU_RX_EMPTY (1 << 8)
53
54#define LPC32XX_HSU_TX_LEV(n) (((n) >> 8) & 0xFF)
55#define LPC32XX_HSU_RX_LEV(n) ((n) & 0xFF)
56
57#define LPC32XX_HSU_TX_INT_SET (1 << 6)
58#define LPC32XX_HSU_RX_OE_INT (1 << 5)
59#define LPC32XX_HSU_BRK_INT (1 << 4)
60#define LPC32XX_HSU_FE_INT (1 << 3)
61#define LPC32XX_HSU_RX_TIMEOUT_INT (1 << 2)
62#define LPC32XX_HSU_RX_TRIG_INT (1 << 1)
63#define LPC32XX_HSU_TX_INT (1 << 0)
64
65#define LPC32XX_HSU_HRTS_INV (1 << 21)
66#define LPC32XX_HSU_HRTS_TRIG_8B (0x0 << 19)
67#define LPC32XX_HSU_HRTS_TRIG_16B (0x1 << 19)
68#define LPC32XX_HSU_HRTS_TRIG_32B (0x2 << 19)
69#define LPC32XX_HSU_HRTS_TRIG_48B (0x3 << 19)
70#define LPC32XX_HSU_HRTS_EN (1 << 18)
71#define LPC32XX_HSU_TMO_DISABLED (0x0 << 16)
72#define LPC32XX_HSU_TMO_INACT_4B (0x1 << 16)
73#define LPC32XX_HSU_TMO_INACT_8B (0x2 << 16)
74#define LPC32XX_HSU_TMO_INACT_16B (0x3 << 16)
75#define LPC32XX_HSU_HCTS_INV (1 << 15)
76#define LPC32XX_HSU_HCTS_EN (1 << 14)
77#define LPC32XX_HSU_OFFSET(n) ((n) << 9)
78#define LPC32XX_HSU_BREAK (1 << 8)
79#define LPC32XX_HSU_ERR_INT_EN (1 << 7)
80#define LPC32XX_HSU_RX_INT_EN (1 << 6)
81#define LPC32XX_HSU_TX_INT_EN (1 << 5)
82#define LPC32XX_HSU_RX_TL1B (0x0 << 2)
83#define LPC32XX_HSU_RX_TL4B (0x1 << 2)
84#define LPC32XX_HSU_RX_TL8B (0x2 << 2)
85#define LPC32XX_HSU_RX_TL16B (0x3 << 2)
86#define LPC32XX_HSU_RX_TL32B (0x4 << 2)
87#define LPC32XX_HSU_RX_TL48B (0x5 << 2)
88#define LPC32XX_HSU_TX_TLEMPTY (0x0 << 0)
89#define LPC32XX_HSU_TX_TL0B (0x0 << 0)
90#define LPC32XX_HSU_TX_TL4B (0x1 << 0)
91#define LPC32XX_HSU_TX_TL8B (0x2 << 0)
92#define LPC32XX_HSU_TX_TL16B (0x3 << 0)
93
94#define MODNAME "lpc32xx_hsuart"
95
96struct lpc32xx_hsuart_port {
97 struct uart_port port;
98};
99
100#define FIFO_READ_LIMIT 128
101#define MAX_PORTS 3
102#define LPC32XX_TTY_NAME "ttyTX"
103static struct lpc32xx_hsuart_port lpc32xx_hs_ports[MAX_PORTS];
104
105#ifdef CONFIG_SERIAL_HS_LPC32XX_CONSOLE
106static void wait_for_xmit_empty(struct uart_port *port)
107{
108 unsigned int timeout = 10000;
109
110 do {
111 if (LPC32XX_HSU_TX_LEV(readl(LPC32XX_HSUART_LEVEL(
112 port->membase))) == 0)
113 break;
114 if (--timeout == 0)
115 break;
116 udelay(1);
117 } while (1);
118}
119
120static void wait_for_xmit_ready(struct uart_port *port)
121{
122 unsigned int timeout = 10000;
123
124 while (1) {
125 if (LPC32XX_HSU_TX_LEV(readl(LPC32XX_HSUART_LEVEL(
126 port->membase))) < 32)
127 break;
128 if (--timeout == 0)
129 break;
130 udelay(1);
131 }
132}
133
134static void lpc32xx_hsuart_console_putchar(struct uart_port *port, int ch)
135{
136 wait_for_xmit_ready(port);
137 writel((u32)ch, LPC32XX_HSUART_FIFO(port->membase));
138}
139
140static void lpc32xx_hsuart_console_write(struct console *co, const char *s,
141 unsigned int count)
142{
143 struct lpc32xx_hsuart_port *up = &lpc32xx_hs_ports[co->index];
144 unsigned long flags;
145 int locked = 1;
146
147 touch_nmi_watchdog();
148 local_irq_save(flags);
149 if (up->port.sysrq)
150 locked = 0;
151 else if (oops_in_progress)
152 locked = spin_trylock(&up->port.lock);
153 else
154 spin_lock(&up->port.lock);
155
156 uart_console_write(&up->port, s, count, lpc32xx_hsuart_console_putchar);
157 wait_for_xmit_empty(&up->port);
158
159 if (locked)
160 spin_unlock(&up->port.lock);
161 local_irq_restore(flags);
162}
163
164static int __init lpc32xx_hsuart_console_setup(struct console *co,
165 char *options)
166{
167 struct uart_port *port;
168 int baud = 115200;
169 int bits = 8;
170 int parity = 'n';
171 int flow = 'n';
172
173 if (co->index >= MAX_PORTS)
174 co->index = 0;
175
176 port = &lpc32xx_hs_ports[co->index].port;
177 if (!port->membase)
178 return -ENODEV;
179
180 if (options)
181 uart_parse_options(options, &baud, &parity, &bits, &flow);
182
183 return uart_set_options(port, co, baud, parity, bits, flow);
184}
185
186static struct uart_driver lpc32xx_hsuart_reg;
187static struct console lpc32xx_hsuart_console = {
188 .name = LPC32XX_TTY_NAME,
189 .write = lpc32xx_hsuart_console_write,
190 .device = uart_console_device,
191 .setup = lpc32xx_hsuart_console_setup,
192 .flags = CON_PRINTBUFFER,
193 .index = -1,
194 .data = &lpc32xx_hsuart_reg,
195};
196
197static int __init lpc32xx_hsuart_console_init(void)
198{
199 register_console(&lpc32xx_hsuart_console);
200 return 0;
201}
202console_initcall(lpc32xx_hsuart_console_init);
203
204#define LPC32XX_HSUART_CONSOLE (&lpc32xx_hsuart_console)
205#else
206#define LPC32XX_HSUART_CONSOLE NULL
207#endif
208
209static struct uart_driver lpc32xx_hs_reg = {
210 .owner = THIS_MODULE,
211 .driver_name = MODNAME,
212 .dev_name = LPC32XX_TTY_NAME,
213 .nr = MAX_PORTS,
214 .cons = LPC32XX_HSUART_CONSOLE,
215};
216static int uarts_registered;
217
218static unsigned int __serial_get_clock_div(unsigned long uartclk,
219 unsigned long rate)
220{
221 u32 div, goodrate, hsu_rate, l_hsu_rate, comprate;
222 u32 rate_diff;
223
224 /* Find the closest divider to get the desired clock rate */
225 div = uartclk / rate;
226 goodrate = hsu_rate = (div / 14) - 1;
227 if (hsu_rate != 0)
228 hsu_rate--;
229
230 /* Tweak divider */
231 l_hsu_rate = hsu_rate + 3;
232 rate_diff = 0xFFFFFFFF;
233
234 while (hsu_rate < l_hsu_rate) {
235 comprate = uartclk / ((hsu_rate + 1) * 14);
236 if (abs(comprate - rate) < rate_diff) {
237 goodrate = hsu_rate;
238 rate_diff = abs(comprate - rate);
239 }
240
241 hsu_rate++;
242 }
243 if (hsu_rate > 0xFF)
244 hsu_rate = 0xFF;
245
246 return goodrate;
247}
248
249static void __serial_uart_flush(struct uart_port *port)
250{
251 u32 tmp;
252 int cnt = 0;
253
254 while ((readl(LPC32XX_HSUART_LEVEL(port->membase)) > 0) &&
255 (cnt++ < FIFO_READ_LIMIT))
256 tmp = readl(LPC32XX_HSUART_FIFO(port->membase));
257}
258
259static void __serial_lpc32xx_rx(struct uart_port *port)
260{
92a19f9c 261 struct tty_port *tport = &port->state->port;
596f93f5 262 unsigned int tmp, flag;
596f93f5
RS		 263
264 /* Read data from FIFO and push into terminal */
265 tmp = readl(LPC32XX_HSUART_FIFO(port->membase));
266 while (!(tmp & LPC32XX_HSU_RX_EMPTY)) {
267 flag = TTY_NORMAL;
268 port->icount.rx++;
269
270 if (tmp & LPC32XX_HSU_ERROR_DATA) {
271 /* Framing error */
272 writel(LPC32XX_HSU_FE_INT,
273 LPC32XX_HSUART_IIR(port->membase));
274 port->icount.frame++;
275 flag = TTY_FRAME;
92a19f9c 276 tty_insert_flip_char(tport, 0, TTY_FRAME);
596f93f5
RS		 277 }
278
92a19f9c 279 tty_insert_flip_char(tport, (tmp & 0xFF), flag);
596f93f5
RS		 280
281 tmp = readl(LPC32XX_HSUART_FIFO(port->membase));
282 }
ec128510
VK		 283
284 spin_unlock(&port->lock);
2e124b4a 285 tty_flip_buffer_push(tport);
ec128510 286 spin_lock(&port->lock);
596f93f5
RS		 287}
288
289static void __serial_lpc32xx_tx(struct uart_port *port)
290{
291 struct circ_buf *xmit = &port->state->xmit;
292 unsigned int tmp;
293
294 if (port->x_char) {
295 writel((u32)port->x_char, LPC32XX_HSUART_FIFO(port->membase));
296 port->icount.tx++;
297 port->x_char = 0;
298 return;
299 }
300
301 if (uart_circ_empty(xmit) || uart_tx_stopped(port))
302 goto exit_tx;
303
304 /* Transfer data */
305 while (LPC32XX_HSU_TX_LEV(readl(
306 LPC32XX_HSUART_LEVEL(port->membase))) < 64) {
307 writel((u32) xmit->buf[xmit->tail],
308 LPC32XX_HSUART_FIFO(port->membase));
309 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
310 port->icount.tx++;
311 if (uart_circ_empty(xmit))
312 break;
313 }
314
315 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
316 uart_write_wakeup(port);
317
318exit_tx:
319 if (uart_circ_empty(xmit)) {
320 tmp = readl(LPC32XX_HSUART_CTRL(port->membase));
321 tmp &= ~LPC32XX_HSU_TX_INT_EN;
322 writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
323 }
324}
325
326static irqreturn_t serial_lpc32xx_interrupt(int irq, void *dev_id)
327{
328 struct uart_port *port = dev_id;
33aeb9da 329 struct tty_port *tport = &port->state->port;
596f93f5
RS		 330 u32 status;
331
332 spin_lock(&port->lock);
333
334 /* Read UART status and clear latched interrupts */
335 status = readl(LPC32XX_HSUART_IIR(port->membase));
336
337 if (status & LPC32XX_HSU_BRK_INT) {
338 /* Break received */
339 writel(LPC32XX_HSU_BRK_INT, LPC32XX_HSUART_IIR(port->membase));
340 port->icount.brk++;
341 uart_handle_break(port);
342 }
343
344 /* Framing error */
345 if (status & LPC32XX_HSU_FE_INT)
346 writel(LPC32XX_HSU_FE_INT, LPC32XX_HSUART_IIR(port->membase));
347
348 if (status & LPC32XX_HSU_RX_OE_INT) {
349 /* Receive FIFO overrun */
350 writel(LPC32XX_HSU_RX_OE_INT,
351 LPC32XX_HSUART_IIR(port->membase));
352 port->icount.overrun++;
92a19f9c 353 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
6732c8bb 354 tty_schedule_flip(tport);
596f93f5
RS		 355 }
356
357 /* Data received? */
97f2c428 358 if (status & (LPC32XX_HSU_RX_TIMEOUT_INT | LPC32XX_HSU_RX_TRIG_INT))
596f93f5 359 __serial_lpc32xx_rx(port);
596f93f5
RS		 360
361 /* Transmit data request? */
362 if ((status & LPC32XX_HSU_TX_INT) && (!uart_tx_stopped(port))) {
363 writel(LPC32XX_HSU_TX_INT, LPC32XX_HSUART_IIR(port->membase));
364 __serial_lpc32xx_tx(port);
365 }
366
367 spin_unlock(&port->lock);
596f93f5
RS		 368
369 return IRQ_HANDLED;
370}
371
372/* port->lock is not held. */
373static unsigned int serial_lpc32xx_tx_empty(struct uart_port *port)
374{
375 unsigned int ret = 0;
376
377 if (LPC32XX_HSU_TX_LEV(readl(LPC32XX_HSUART_LEVEL(port->membase))) == 0)
378 ret = TIOCSER_TEMT;
379
380 return ret;
381}
382
383/* port->lock held by caller. */
384static void serial_lpc32xx_set_mctrl(struct uart_port *port,
385 unsigned int mctrl)
386{
387 /* No signals are supported on HS UARTs */
388}
389
390/* port->lock is held by caller and interrupts are disabled. */
391static unsigned int serial_lpc32xx_get_mctrl(struct uart_port *port)
392{
393 /* No signals are supported on HS UARTs */
394 return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
395}
396
397/* port->lock held by caller. */
398static void serial_lpc32xx_stop_tx(struct uart_port *port)
399{
400 u32 tmp;
401
402 tmp = readl(LPC32XX_HSUART_CTRL(port->membase));
403 tmp &= ~LPC32XX_HSU_TX_INT_EN;
404 writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
405}
406
407/* port->lock held by caller. */
408static void serial_lpc32xx_start_tx(struct uart_port *port)
409{
410 u32 tmp;
411
412 __serial_lpc32xx_tx(port);
413 tmp = readl(LPC32XX_HSUART_CTRL(port->membase));
414 tmp |= LPC32XX_HSU_TX_INT_EN;
415 writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
416}
417
418/* port->lock held by caller. */
419static void serial_lpc32xx_stop_rx(struct uart_port *port)
420{
421 u32 tmp;
422
423 tmp = readl(LPC32XX_HSUART_CTRL(port->membase));
424 tmp &= ~(LPC32XX_HSU_RX_INT_EN | LPC32XX_HSU_ERR_INT_EN);
425 writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
426
427 writel((LPC32XX_HSU_BRK_INT | LPC32XX_HSU_RX_OE_INT |
428 LPC32XX_HSU_FE_INT), LPC32XX_HSUART_IIR(port->membase));
429}
430
596f93f5
RS		 431/* port->lock is not held. */
432static void serial_lpc32xx_break_ctl(struct uart_port *port,
433 int break_state)
434{
435 unsigned long flags;
436 u32 tmp;
437
438 spin_lock_irqsave(&port->lock, flags);
439 tmp = readl(LPC32XX_HSUART_CTRL(port->membase));
440 if (break_state != 0)
441 tmp |= LPC32XX_HSU_BREAK;
442 else
443 tmp &= ~LPC32XX_HSU_BREAK;
444 writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
445 spin_unlock_irqrestore(&port->lock, flags);
446}
447
448/* LPC3250 Errata HSUART.1: Hang workaround via loopback mode on inactivity */
449static void lpc32xx_loopback_set(resource_size_t mapbase, int state)
450{
451 int bit;
452 u32 tmp;
453
454 switch (mapbase) {
455 case LPC32XX_HS_UART1_BASE:
456 bit = 0;
457 break;
458 case LPC32XX_HS_UART2_BASE:
459 bit = 1;
460 break;
461 case LPC32XX_HS_UART7_BASE:
462 bit = 6;
463 break;
464 default:
465 WARN(1, "lpc32xx_hs: Warning: Unknown port at %08x\n", mapbase);
466 return;
467 }
468
469 tmp = readl(LPC32XX_UARTCTL_CLOOP);
470 if (state)
471 tmp |= (1 << bit);
472 else
473 tmp &= ~(1 << bit);
474 writel(tmp, LPC32XX_UARTCTL_CLOOP);
475}
476
477/* port->lock is not held. */
478static int serial_lpc32xx_startup(struct uart_port *port)
479{
480 int retval;
481 unsigned long flags;
482 u32 tmp;
483
484 spin_lock_irqsave(&port->lock, flags);
485
486 __serial_uart_flush(port);
487
488 writel((LPC32XX_HSU_TX_INT | LPC32XX_HSU_FE_INT |
489 LPC32XX_HSU_BRK_INT | LPC32XX_HSU_RX_OE_INT),
490 LPC32XX_HSUART_IIR(port->membase));
491
492 writel(0xFF, LPC32XX_HSUART_RATE(port->membase));
493
494 /*
495 * Set receiver timeout, HSU offset of 20, no break, no interrupts,
496 * and default FIFO trigger levels
497 */
498 tmp = LPC32XX_HSU_TX_TL8B | LPC32XX_HSU_RX_TL32B |
499 LPC32XX_HSU_OFFSET(20) | LPC32XX_HSU_TMO_INACT_4B;
500 writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
501
502 lpc32xx_loopback_set(port->mapbase, 0); /* get out of loopback mode */
503
504 spin_unlock_irqrestore(&port->lock, flags);
505
506 retval = request_irq(port->irq, serial_lpc32xx_interrupt,
507 0, MODNAME, port);
508 if (!retval)
509 writel((tmp | LPC32XX_HSU_RX_INT_EN | LPC32XX_HSU_ERR_INT_EN),
510 LPC32XX_HSUART_CTRL(port->membase));
511
512 return retval;
513}
514
515/* port->lock is not held. */
516static void serial_lpc32xx_shutdown(struct uart_port *port)
517{
518 u32 tmp;
519 unsigned long flags;
520
521 spin_lock_irqsave(&port->lock, flags);
522
523 tmp = LPC32XX_HSU_TX_TL8B | LPC32XX_HSU_RX_TL32B |
524 LPC32XX_HSU_OFFSET(20) | LPC32XX_HSU_TMO_INACT_4B;
525 writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
526
527 lpc32xx_loopback_set(port->mapbase, 1); /* go to loopback mode */
528
529 spin_unlock_irqrestore(&port->lock, flags);
530
531 free_irq(port->irq, port);
532}
533
534/* port->lock is not held. */
535static void serial_lpc32xx_set_termios(struct uart_port *port,
536 struct ktermios *termios,
537 struct ktermios *old)
538{
539 unsigned long flags;
540 unsigned int baud, quot;
541 u32 tmp;
542
543 /* Always 8-bit, no parity, 1 stop bit */
544 termios->c_cflag &= ~(CSIZE | CSTOPB | PARENB | PARODD);
545 termios->c_cflag |= CS8;
546
547 termios->c_cflag &= ~(HUPCL | CMSPAR | CLOCAL | CRTSCTS);
548
549 baud = uart_get_baud_rate(port, termios, old, 0,
550 port->uartclk / 14);
551
552 quot = __serial_get_clock_div(port->uartclk, baud);
553
554 spin_lock_irqsave(&port->lock, flags);
555
556 /* Ignore characters? */
557 tmp = readl(LPC32XX_HSUART_CTRL(port->membase));
558 if ((termios->c_cflag & CREAD) == 0)
559 tmp &= ~(LPC32XX_HSU_RX_INT_EN | LPC32XX_HSU_ERR_INT_EN);
560 else
561 tmp |= LPC32XX_HSU_RX_INT_EN | LPC32XX_HSU_ERR_INT_EN;
562 writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
563
564 writel(quot, LPC32XX_HSUART_RATE(port->membase));
565
566 uart_update_timeout(port, termios->c_cflag, baud);
567
568 spin_unlock_irqrestore(&port->lock, flags);
569
570 /* Don't rewrite B0 */
571 if (tty_termios_baud_rate(termios))
572 tty_termios_encode_baud_rate(termios, baud, baud);
573}
574
575static const char *serial_lpc32xx_type(struct uart_port *port)
576{
577 return MODNAME;
578}
579
580static void serial_lpc32xx_release_port(struct uart_port *port)
581{
582 if ((port->iotype == UPIO_MEM32) && (port->mapbase)) {
583 if (port->flags & UPF_IOREMAP) {
584 iounmap(port->membase);
585 port->membase = NULL;
586 }
587
588 release_mem_region(port->mapbase, SZ_4K);
589 }
590}
591
592static int serial_lpc32xx_request_port(struct uart_port *port)
593{
594 int ret = -ENODEV;
595
596 if ((port->iotype == UPIO_MEM32) && (port->mapbase)) {
597 ret = 0;
598
599 if (!request_mem_region(port->mapbase, SZ_4K, MODNAME))
600 ret = -EBUSY;
601 else if (port->flags & UPF_IOREMAP) {
602 port->membase = ioremap(port->mapbase, SZ_4K);
603 if (!port->membase) {
604 release_mem_region(port->mapbase, SZ_4K);
605 ret = -ENOMEM;
606 }
607 }
608 }
609
610 return ret;
611}
612
613static void serial_lpc32xx_config_port(struct uart_port *port, int uflags)
614{
615 int ret;
616
617 ret = serial_lpc32xx_request_port(port);
618 if (ret < 0)
619 return;
620 port->type = PORT_UART00;
621 port->fifosize = 64;
622
623 __serial_uart_flush(port);
624
625 writel((LPC32XX_HSU_TX_INT | LPC32XX_HSU_FE_INT |
626 LPC32XX_HSU_BRK_INT | LPC32XX_HSU_RX_OE_INT),
627 LPC32XX_HSUART_IIR(port->membase));
628
629 writel(0xFF, LPC32XX_HSUART_RATE(port->membase));
630
631 /* Set receiver timeout, HSU offset of 20, no break, no interrupts,
632 and default FIFO trigger levels */
633 writel(LPC32XX_HSU_TX_TL8B | LPC32XX_HSU_RX_TL32B |
634 LPC32XX_HSU_OFFSET(20) | LPC32XX_HSU_TMO_INACT_4B,
635 LPC32XX_HSUART_CTRL(port->membase));
636}
637
638static int serial_lpc32xx_verify_port(struct uart_port *port,
639 struct serial_struct *ser)
640{
641 int ret = 0;
642
643 if (ser->type != PORT_UART00)
644 ret = -EINVAL;
645
646 return ret;
647}
648
2331e068 649static const struct uart_ops serial_lpc32xx_pops = {
596f93f5
RS		 650 .tx_empty = serial_lpc32xx_tx_empty,
651 .set_mctrl = serial_lpc32xx_set_mctrl,
652 .get_mctrl = serial_lpc32xx_get_mctrl,
653 .stop_tx = serial_lpc32xx_stop_tx,
654 .start_tx = serial_lpc32xx_start_tx,
655 .stop_rx = serial_lpc32xx_stop_rx,
596f93f5
RS		 656 .break_ctl = serial_lpc32xx_break_ctl,
657 .startup = serial_lpc32xx_startup,
658 .shutdown = serial_lpc32xx_shutdown,
659 .set_termios = serial_lpc32xx_set_termios,
660 .type = serial_lpc32xx_type,
661 .release_port = serial_lpc32xx_release_port,
662 .request_port = serial_lpc32xx_request_port,
663 .config_port = serial_lpc32xx_config_port,
664 .verify_port = serial_lpc32xx_verify_port,
665};
666
667/*
668 * Register a set of serial devices attached to a platform device
669 */
9671f099 670static int serial_hs_lpc32xx_probe(struct platform_device *pdev)
596f93f5
RS		 671{
672 struct lpc32xx_hsuart_port *p = &lpc32xx_hs_ports[uarts_registered];
673 int ret = 0;
674 struct resource *res;
675
676 if (uarts_registered >= MAX_PORTS) {
677 dev_err(&pdev->dev,
678 "Error: Number of possible ports exceeded (%d)!\n",
679 uarts_registered + 1);
680 return -ENXIO;
681 }
682
683 memset(p, 0, sizeof(*p));
684
685 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
686 if (!res) {
687 dev_err(&pdev->dev,
688 "Error getting mem resource for HS UART port %d\n",
689 uarts_registered);
690 return -ENXIO;
691 }
692 p->port.mapbase = res->start;
693 p->port.membase = NULL;
694
14996122
AH		 695 ret = platform_get_irq(pdev, 0);
696 if (ret < 0) {
596f93f5
RS		 697 dev_err(&pdev->dev, "Error getting irq for HS UART port %d\n",
698 uarts_registered);
14996122 699 return ret;
596f93f5 700 }
14996122 701 p->port.irq = ret;
596f93f5
RS		 702
703 p->port.iotype = UPIO_MEM32;
704 p->port.uartclk = LPC32XX_MAIN_OSC_FREQ;
705 p->port.regshift = 2;
706 p->port.flags = UPF_BOOT_AUTOCONF | UPF_FIXED_PORT | UPF_IOREMAP;
707 p->port.dev = &pdev->dev;
708 p->port.ops = &serial_lpc32xx_pops;
709 p->port.line = uarts_registered++;
710 spin_lock_init(&p->port.lock);
711
712 /* send port to loopback mode by default */
713 lpc32xx_loopback_set(p->port.mapbase, 1);
714
715 ret = uart_add_one_port(&lpc32xx_hs_reg, &p->port);
716
717 platform_set_drvdata(pdev, p);
718
719 return ret;
720}
721
722/*
723 * Remove serial ports registered against a platform device.
724 */
ae8d8a14 725static int serial_hs_lpc32xx_remove(struct platform_device *pdev)
596f93f5
RS		 726{
727 struct lpc32xx_hsuart_port *p = platform_get_drvdata(pdev);
728
729 uart_remove_one_port(&lpc32xx_hs_reg, &p->port);
730
731 return 0;
732}
733
734
735#ifdef CONFIG_PM
736static int serial_hs_lpc32xx_suspend(struct platform_device *pdev,
737 pm_message_t state)
738{
739 struct lpc32xx_hsuart_port *p = platform_get_drvdata(pdev);
740
741 uart_suspend_port(&lpc32xx_hs_reg, &p->port);
742
743 return 0;
744}
745
746static int serial_hs_lpc32xx_resume(struct platform_device *pdev)
747{
748 struct lpc32xx_hsuart_port *p = platform_get_drvdata(pdev);
749
750 uart_resume_port(&lpc32xx_hs_reg, &p->port);
751
752 return 0;
753}
754#else
755#define serial_hs_lpc32xx_suspend NULL
756#define serial_hs_lpc32xx_resume NULL
757#endif
758
759static const struct of_device_id serial_hs_lpc32xx_dt_ids[] = {
760 { .compatible = "nxp,lpc3220-hsuart" },
761 { /* sentinel */ }
762};
763
764MODULE_DEVICE_TABLE(of, serial_hs_lpc32xx_dt_ids);
765
766static struct platform_driver serial_hs_lpc32xx_driver = {
767 .probe = serial_hs_lpc32xx_probe,
2d47b716 768 .remove = serial_hs_lpc32xx_remove,
596f93f5
RS		 769 .suspend = serial_hs_lpc32xx_suspend,
770 .resume = serial_hs_lpc32xx_resume,
771 .driver = {
772 .name = MODNAME,
596f93f5
RS		 773 .of_match_table = serial_hs_lpc32xx_dt_ids,
774 },
775};
776
777static int __init lpc32xx_hsuart_init(void)
778{
779 int ret;
780
781 ret = uart_register_driver(&lpc32xx_hs_reg);
782 if (ret)
783 return ret;
784
785 ret = platform_driver_register(&serial_hs_lpc32xx_driver);
786 if (ret)
787 uart_unregister_driver(&lpc32xx_hs_reg);
788
789 return ret;
790}
791
792static void __exit lpc32xx_hsuart_exit(void)
793{
794 platform_driver_unregister(&serial_hs_lpc32xx_driver);
795 uart_unregister_driver(&lpc32xx_hs_reg);
796}
797
798module_init(lpc32xx_hsuart_init);
799module_exit(lpc32xx_hsuart_exit);
800
801MODULE_AUTHOR("Kevin Wells <kevin.wells@nxp.com>");
802MODULE_AUTHOR("Roland Stigge <stigge@antcom.de>");
803MODULE_DESCRIPTION("NXP LPC32XX High Speed UART driver");
804MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)