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Merge tag 'drm-msm-next-2018-06-04' of git://people.freedesktop.org/~robclark/linux...
[linux-2.6-block.git] / drivers / tty / serial / lantiq.c
CommitLineData
e3b3d0f5 1// SPDX-License-Identifier: GPL-2.0
2f0fc415
JC		 2/*
3 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
4 *
2f0fc415
JC		 5 * Copyright (C) 2004 Infineon IFAP DC COM CPE
6 * Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org>
552df698 7 * Copyright (C) 2007 John Crispin <john@phrozen.org>
2f0fc415
JC		 8 * Copyright (C) 2010 Thomas Langer, <thomas.langer@lantiq.com>
9 */
10
11#include <linux/slab.h>
2f0fc415
JC		 12#include <linux/ioport.h>
13#include <linux/init.h>
14#include <linux/console.h>
15#include <linux/sysrq.h>
16#include <linux/device.h>
17#include <linux/tty.h>
18#include <linux/tty_flip.h>
19#include <linux/serial_core.h>
20#include <linux/serial.h>
ceff2676
JC		 21#include <linux/of_platform.h>
22#include <linux/of_address.h>
23#include <linux/of_irq.h>
2f0fc415
JC		 24#include <linux/io.h>
25#include <linux/clk.h>
ceff2676 26#include <linux/gpio.h>
2f0fc415
JC		 27
28#include <lantiq_soc.h>
29
30#define PORT_LTQ_ASC 111
31#define MAXPORTS 2
32#define UART_DUMMY_UER_RX 1
ceff2676 33#define DRVNAME "lantiq,asc"
2f0fc415
JC		 34#ifdef __BIG_ENDIAN
35#define LTQ_ASC_TBUF (0x0020 + 3)
36#define LTQ_ASC_RBUF (0x0024 + 3)
37#else
38#define LTQ_ASC_TBUF 0x0020
39#define LTQ_ASC_RBUF 0x0024
40#endif
41#define LTQ_ASC_FSTAT 0x0048
42#define LTQ_ASC_WHBSTATE 0x0018
43#define LTQ_ASC_STATE 0x0014
44#define LTQ_ASC_IRNCR 0x00F8
45#define LTQ_ASC_CLC 0x0000
46#define LTQ_ASC_ID 0x0008
47#define LTQ_ASC_PISEL 0x0004
48#define LTQ_ASC_TXFCON 0x0044
49#define LTQ_ASC_RXFCON 0x0040
50#define LTQ_ASC_CON 0x0010
51#define LTQ_ASC_BG 0x0050
52#define LTQ_ASC_IRNREN 0x00F4
53
54#define ASC_IRNREN_TX 0x1
55#define ASC_IRNREN_RX 0x2
56#define ASC_IRNREN_ERR 0x4
57#define ASC_IRNREN_TX_BUF 0x8
58#define ASC_IRNCR_TIR 0x1
59#define ASC_IRNCR_RIR 0x2
60#define ASC_IRNCR_EIR 0x4
61
62#define ASCOPT_CSIZE 0x3
63#define TXFIFO_FL 1
64#define RXFIFO_FL 1
65#define ASCCLC_DISS 0x2
66#define ASCCLC_RMCMASK 0x0000FF00
67#define ASCCLC_RMCOFFSET 8
68#define ASCCON_M_8ASYNC 0x0
69#define ASCCON_M_7ASYNC 0x2
70#define ASCCON_ODD 0x00000020
71#define ASCCON_STP 0x00000080
72#define ASCCON_BRS 0x00000100
73#define ASCCON_FDE 0x00000200
74#define ASCCON_R 0x00008000
75#define ASCCON_FEN 0x00020000
76#define ASCCON_ROEN 0x00080000
77#define ASCCON_TOEN 0x00100000
78#define ASCSTATE_PE 0x00010000
79#define ASCSTATE_FE 0x00020000
80#define ASCSTATE_ROE 0x00080000
81#define ASCSTATE_ANY (ASCSTATE_ROE|ASCSTATE_PE|ASCSTATE_FE)
82#define ASCWHBSTATE_CLRREN 0x00000001
83#define ASCWHBSTATE_SETREN 0x00000002
84#define ASCWHBSTATE_CLRPE 0x00000004
85#define ASCWHBSTATE_CLRFE 0x00000008
86#define ASCWHBSTATE_CLRROE 0x00000020
87#define ASCTXFCON_TXFEN 0x0001
88#define ASCTXFCON_TXFFLU 0x0002
89#define ASCTXFCON_TXFITLMASK 0x3F00
90#define ASCTXFCON_TXFITLOFF 8
91#define ASCRXFCON_RXFEN 0x0001
92#define ASCRXFCON_RXFFLU 0x0002
93#define ASCRXFCON_RXFITLMASK 0x3F00
94#define ASCRXFCON_RXFITLOFF 8
95#define ASCFSTAT_RXFFLMASK 0x003F
96#define ASCFSTAT_TXFFLMASK 0x3F00
97#define ASCFSTAT_TXFREEMASK 0x3F000000
98#define ASCFSTAT_TXFREEOFF 24
99
100static void lqasc_tx_chars(struct uart_port *port);
101static struct ltq_uart_port *lqasc_port[MAXPORTS];
102static struct uart_driver lqasc_reg;
103static DEFINE_SPINLOCK(ltq_asc_lock);
104
105struct ltq_uart_port {
106 struct uart_port port;
ceff2676
JC		 107 /* clock used to derive divider */
108 struct clk *fpiclk;
109 /* clock gating of the ASC core */
2f0fc415
JC		 110 struct clk *clk;
111 unsigned int tx_irq;
112 unsigned int rx_irq;
113 unsigned int err_irq;
114};
115
116static inline struct
117ltq_uart_port *to_ltq_uart_port(struct uart_port *port)
118{
119 return container_of(port, struct ltq_uart_port, port);
120}
121
122static void
123lqasc_stop_tx(struct uart_port *port)
124{
125 return;
126}
127
128static void
129lqasc_start_tx(struct uart_port *port)
130{
131 unsigned long flags;
132 spin_lock_irqsave(&ltq_asc_lock, flags);
133 lqasc_tx_chars(port);
134 spin_unlock_irqrestore(&ltq_asc_lock, flags);
135 return;
136}
137
138static void
139lqasc_stop_rx(struct uart_port *port)
140{
141 ltq_w32(ASCWHBSTATE_CLRREN, port->membase + LTQ_ASC_WHBSTATE);
142}
143
2f0fc415
JC		 144static int
145lqasc_rx_chars(struct uart_port *port)
146{
92a19f9c 147 struct tty_port *tport = &port->state->port;
2f0fc415
JC		 148 unsigned int ch = 0, rsr = 0, fifocnt;
149
2e124b4a 150 fifocnt = ltq_r32(port->membase + LTQ_ASC_FSTAT) & ASCFSTAT_RXFFLMASK;
2f0fc415
JC		 151 while (fifocnt--) {
152 u8 flag = TTY_NORMAL;
153 ch = ltq_r8(port->membase + LTQ_ASC_RBUF);
154 rsr = (ltq_r32(port->membase + LTQ_ASC_STATE)
155 & ASCSTATE_ANY) | UART_DUMMY_UER_RX;
2e124b4a 156 tty_flip_buffer_push(tport);
2f0fc415
JC		 157 port->icount.rx++;
158
159 /*
160 * Note that the error handling code is
161 * out of the main execution path
162 */
163 if (rsr & ASCSTATE_ANY) {
164 if (rsr & ASCSTATE_PE) {
165 port->icount.parity++;
166 ltq_w32_mask(0, ASCWHBSTATE_CLRPE,
167 port->membase + LTQ_ASC_WHBSTATE);
168 } else if (rsr & ASCSTATE_FE) {
169 port->icount.frame++;
170 ltq_w32_mask(0, ASCWHBSTATE_CLRFE,
171 port->membase + LTQ_ASC_WHBSTATE);
172 }
173 if (rsr & ASCSTATE_ROE) {
174 port->icount.overrun++;
175 ltq_w32_mask(0, ASCWHBSTATE_CLRROE,
176 port->membase + LTQ_ASC_WHBSTATE);
177 }
178
179 rsr &= port->read_status_mask;
180
181 if (rsr & ASCSTATE_PE)
182 flag = TTY_PARITY;
183 else if (rsr & ASCSTATE_FE)
184 flag = TTY_FRAME;
185 }
186
187 if ((rsr & port->ignore_status_mask) == 0)
92a19f9c 188 tty_insert_flip_char(tport, ch, flag);
2f0fc415
JC		 189
190 if (rsr & ASCSTATE_ROE)
191 /*
192 * Overrun is special, since it's reported
193 * immediately, and doesn't affect the current
194 * character
195 */
92a19f9c 196 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
2f0fc415 197 }
2e124b4a 198
2f0fc415 199 if (ch != 0)
2e124b4a
JS		 200 tty_flip_buffer_push(tport);
201
2f0fc415
JC		 202 return 0;
203}
204
205static void
206lqasc_tx_chars(struct uart_port *port)
207{
208 struct circ_buf *xmit = &port->state->xmit;
209 if (uart_tx_stopped(port)) {
210 lqasc_stop_tx(port);
211 return;
212 }
213
214 while (((ltq_r32(port->membase + LTQ_ASC_FSTAT) &
215 ASCFSTAT_TXFREEMASK) >> ASCFSTAT_TXFREEOFF) != 0) {
216 if (port->x_char) {
217 ltq_w8(port->x_char, port->membase + LTQ_ASC_TBUF);
218 port->icount.tx++;
219 port->x_char = 0;
220 continue;
221 }
222
223 if (uart_circ_empty(xmit))
224 break;
225
226 ltq_w8(port->state->xmit.buf[port->state->xmit.tail],
227 port->membase + LTQ_ASC_TBUF);
228 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
229 port->icount.tx++;
230 }
231
232 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
233 uart_write_wakeup(port);
234}
235
236static irqreturn_t
237lqasc_tx_int(int irq, void *_port)
238{
239 unsigned long flags;
240 struct uart_port *port = (struct uart_port *)_port;
241 spin_lock_irqsave(&ltq_asc_lock, flags);
242 ltq_w32(ASC_IRNCR_TIR, port->membase + LTQ_ASC_IRNCR);
243 spin_unlock_irqrestore(&ltq_asc_lock, flags);
244 lqasc_start_tx(port);
245 return IRQ_HANDLED;
246}
247
248static irqreturn_t
249lqasc_err_int(int irq, void *_port)
250{
251 unsigned long flags;
252 struct uart_port *port = (struct uart_port *)_port;
253 spin_lock_irqsave(&ltq_asc_lock, flags);
254 /* clear any pending interrupts */
255 ltq_w32_mask(0, ASCWHBSTATE_CLRPE | ASCWHBSTATE_CLRFE |
256 ASCWHBSTATE_CLRROE, port->membase + LTQ_ASC_WHBSTATE);
257 spin_unlock_irqrestore(&ltq_asc_lock, flags);
258 return IRQ_HANDLED;
259}
260
261static irqreturn_t
262lqasc_rx_int(int irq, void *_port)
263{
264 unsigned long flags;
265 struct uart_port *port = (struct uart_port *)_port;
266 spin_lock_irqsave(&ltq_asc_lock, flags);
267 ltq_w32(ASC_IRNCR_RIR, port->membase + LTQ_ASC_IRNCR);
268 lqasc_rx_chars(port);
269 spin_unlock_irqrestore(&ltq_asc_lock, flags);
270 return IRQ_HANDLED;
271}
272
273static unsigned int
274lqasc_tx_empty(struct uart_port *port)
275{
276 int status;
277 status = ltq_r32(port->membase + LTQ_ASC_FSTAT) & ASCFSTAT_TXFFLMASK;
278 return status ? 0 : TIOCSER_TEMT;
279}
280
281static unsigned int
282lqasc_get_mctrl(struct uart_port *port)
283{
284 return TIOCM_CTS | TIOCM_CAR | TIOCM_DSR;
285}
286
287static void
288lqasc_set_mctrl(struct uart_port *port, u_int mctrl)
289{
290}
291
292static void
293lqasc_break_ctl(struct uart_port *port, int break_state)
294{
295}
296
297static int
298lqasc_startup(struct uart_port *port)
299{
300 struct ltq_uart_port *ltq_port = to_ltq_uart_port(port);
301 int retval;
302
8ad2ee95 303 if (!IS_ERR(ltq_port->clk))
ceff2676
JC		 304 clk_enable(ltq_port->clk);
305 port->uartclk = clk_get_rate(ltq_port->fpiclk);
2f0fc415
JC		 306
307 ltq_w32_mask(ASCCLC_DISS | ASCCLC_RMCMASK, (1 << ASCCLC_RMCOFFSET),
308 port->membase + LTQ_ASC_CLC);
309
310 ltq_w32(0, port->membase + LTQ_ASC_PISEL);
311 ltq_w32(
312 ((TXFIFO_FL << ASCTXFCON_TXFITLOFF) & ASCTXFCON_TXFITLMASK) |
313 ASCTXFCON_TXFEN | ASCTXFCON_TXFFLU,
314 port->membase + LTQ_ASC_TXFCON);
315 ltq_w32(
316 ((RXFIFO_FL << ASCRXFCON_RXFITLOFF) & ASCRXFCON_RXFITLMASK)
317 | ASCRXFCON_RXFEN | ASCRXFCON_RXFFLU,
318 port->membase + LTQ_ASC_RXFCON);
319 /* make sure other settings are written to hardware before
320 * setting enable bits
321 */
322 wmb();
323 ltq_w32_mask(0, ASCCON_M_8ASYNC | ASCCON_FEN | ASCCON_TOEN |
324 ASCCON_ROEN, port->membase + LTQ_ASC_CON);
325
326 retval = request_irq(ltq_port->tx_irq, lqasc_tx_int,
9cfb5c05 327 0, "asc_tx", port);
2f0fc415
JC		 328 if (retval) {
329 pr_err("failed to request lqasc_tx_int\n");
330 return retval;
331 }
332
333 retval = request_irq(ltq_port->rx_irq, lqasc_rx_int,
9cfb5c05 334 0, "asc_rx", port);
2f0fc415
JC		 335 if (retval) {
336 pr_err("failed to request lqasc_rx_int\n");
337 goto err1;
338 }
339
340 retval = request_irq(ltq_port->err_irq, lqasc_err_int,
9cfb5c05 341 0, "asc_err", port);
2f0fc415
JC		 342 if (retval) {
343 pr_err("failed to request lqasc_err_int\n");
344 goto err2;
345 }
346
347 ltq_w32(ASC_IRNREN_RX | ASC_IRNREN_ERR | ASC_IRNREN_TX,
348 port->membase + LTQ_ASC_IRNREN);
349 return 0;
350
351err2:
352 free_irq(ltq_port->rx_irq, port);
353err1:
354 free_irq(ltq_port->tx_irq, port);
355 return retval;
356}
357
358static void
359lqasc_shutdown(struct uart_port *port)
360{
361 struct ltq_uart_port *ltq_port = to_ltq_uart_port(port);
362 free_irq(ltq_port->tx_irq, port);
363 free_irq(ltq_port->rx_irq, port);
364 free_irq(ltq_port->err_irq, port);
365
366 ltq_w32(0, port->membase + LTQ_ASC_CON);
367 ltq_w32_mask(ASCRXFCON_RXFEN, ASCRXFCON_RXFFLU,
368 port->membase + LTQ_ASC_RXFCON);
369 ltq_w32_mask(ASCTXFCON_TXFEN, ASCTXFCON_TXFFLU,
370 port->membase + LTQ_ASC_TXFCON);
8ad2ee95 371 if (!IS_ERR(ltq_port->clk))
ceff2676 372 clk_disable(ltq_port->clk);
2f0fc415
JC		 373}
374
375static void
376lqasc_set_termios(struct uart_port *port,
377 struct ktermios *new, struct ktermios *old)
378{
379 unsigned int cflag;
380 unsigned int iflag;
381 unsigned int divisor;
382 unsigned int baud;
383 unsigned int con = 0;
384 unsigned long flags;
385
386 cflag = new->c_cflag;
387 iflag = new->c_iflag;
388
389 switch (cflag & CSIZE) {
390 case CS7:
391 con = ASCCON_M_7ASYNC;
392 break;
393
394 case CS5:
395 case CS6:
396 default:
397 new->c_cflag &= ~ CSIZE;
398 new->c_cflag |= CS8;
399 con = ASCCON_M_8ASYNC;
400 break;
401 }
402
403 cflag &= ~CMSPAR; /* Mark/Space parity is not supported */
404
405 if (cflag & CSTOPB)
406 con |= ASCCON_STP;
407
408 if (cflag & PARENB) {
409 if (!(cflag & PARODD))
410 con &= ~ASCCON_ODD;
411 else
412 con |= ASCCON_ODD;
413 }
414
415 port->read_status_mask = ASCSTATE_ROE;
416 if (iflag & INPCK)
417 port->read_status_mask |= ASCSTATE_FE | ASCSTATE_PE;
418
419 port->ignore_status_mask = 0;
420 if (iflag & IGNPAR)
421 port->ignore_status_mask |= ASCSTATE_FE | ASCSTATE_PE;
422
423 if (iflag & IGNBRK) {
424 /*
425 * If we're ignoring parity and break indicators,
426 * ignore overruns too (for real raw support).
427 */
428 if (iflag & IGNPAR)
429 port->ignore_status_mask |= ASCSTATE_ROE;
430 }
431
432 if ((cflag & CREAD) == 0)
433 port->ignore_status_mask |= UART_DUMMY_UER_RX;
434
435 /* set error signals - framing, parity and overrun, enable receiver */
436 con |= ASCCON_FEN | ASCCON_TOEN | ASCCON_ROEN;
437
438 spin_lock_irqsave(&ltq_asc_lock, flags);
439
440 /* set up CON */
441 ltq_w32_mask(0, con, port->membase + LTQ_ASC_CON);
442
443 /* Set baud rate - take a divider of 2 into account */
444 baud = uart_get_baud_rate(port, new, old, 0, port->uartclk / 16);
445 divisor = uart_get_divisor(port, baud);
446 divisor = divisor / 2 - 1;
447
448 /* disable the baudrate generator */
449 ltq_w32_mask(ASCCON_R, 0, port->membase + LTQ_ASC_CON);
450
451 /* make sure the fractional divider is off */
452 ltq_w32_mask(ASCCON_FDE, 0, port->membase + LTQ_ASC_CON);
453
454 /* set up to use divisor of 2 */
455 ltq_w32_mask(ASCCON_BRS, 0, port->membase + LTQ_ASC_CON);
456
457 /* now we can write the new baudrate into the register */
458 ltq_w32(divisor, port->membase + LTQ_ASC_BG);
459
460 /* turn the baudrate generator back on */
461 ltq_w32_mask(0, ASCCON_R, port->membase + LTQ_ASC_CON);
462
463 /* enable rx */
464 ltq_w32(ASCWHBSTATE_SETREN, port->membase + LTQ_ASC_WHBSTATE);
465
466 spin_unlock_irqrestore(&ltq_asc_lock, flags);
467
468 /* Don't rewrite B0 */
b7867f1b 469 if (tty_termios_baud_rate(new))
2f0fc415 470 tty_termios_encode_baud_rate(new, baud, baud);
b7867f1b
JC		 471
472 uart_update_timeout(port, cflag, baud);
2f0fc415
JC		 473}
474
475static const char*
476lqasc_type(struct uart_port *port)
477{
478 if (port->type == PORT_LTQ_ASC)
479 return DRVNAME;
480 else
481 return NULL;
482}
483
484static void
485lqasc_release_port(struct uart_port *port)
486{
1511316f
SM		 487 struct platform_device *pdev = to_platform_device(port->dev);
488
2f0fc415 489 if (port->flags & UPF_IOREMAP) {
1511316f 490 devm_iounmap(&pdev->dev, port->membase);
2f0fc415
JC		 491 port->membase = NULL;
492 }
493}
494
495static int
496lqasc_request_port(struct uart_port *port)
497{
498 struct platform_device *pdev = to_platform_device(port->dev);
499 struct resource *res;
500 int size;
501
502 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
503 if (!res) {
504 dev_err(&pdev->dev, "cannot obtain I/O memory region");
505 return -ENODEV;
506 }
507 size = resource_size(res);
508
509 res = devm_request_mem_region(&pdev->dev, res->start,
510 size, dev_name(&pdev->dev));
511 if (!res) {
512 dev_err(&pdev->dev, "cannot request I/O memory region");
513 return -EBUSY;
514 }
515
516 if (port->flags & UPF_IOREMAP) {
517 port->membase = devm_ioremap_nocache(&pdev->dev,
518 port->mapbase, size);
519 if (port->membase == NULL)
520 return -ENOMEM;
521 }
522 return 0;
523}
524
525static void
526lqasc_config_port(struct uart_port *port, int flags)
527{
528 if (flags & UART_CONFIG_TYPE) {
529 port->type = PORT_LTQ_ASC;
530 lqasc_request_port(port);
531 }
532}
533
534static int
535lqasc_verify_port(struct uart_port *port,
536 struct serial_struct *ser)
537{
538 int ret = 0;
539 if (ser->type != PORT_UNKNOWN && ser->type != PORT_LTQ_ASC)
540 ret = -EINVAL;
541 if (ser->irq < 0 || ser->irq >= NR_IRQS)
542 ret = -EINVAL;
543 if (ser->baud_base < 9600)
544 ret = -EINVAL;
545 return ret;
546}
547
2331e068 548static const struct uart_ops lqasc_pops = {
2f0fc415
JC		 549 .tx_empty = lqasc_tx_empty,
550 .set_mctrl = lqasc_set_mctrl,
551 .get_mctrl = lqasc_get_mctrl,
552 .stop_tx = lqasc_stop_tx,
553 .start_tx = lqasc_start_tx,
554 .stop_rx = lqasc_stop_rx,
2f0fc415
JC		 555 .break_ctl = lqasc_break_ctl,
556 .startup = lqasc_startup,
557 .shutdown = lqasc_shutdown,
558 .set_termios = lqasc_set_termios,
559 .type = lqasc_type,
560 .release_port = lqasc_release_port,
561 .request_port = lqasc_request_port,
562 .config_port = lqasc_config_port,
563 .verify_port = lqasc_verify_port,
564};
565
566static void
567lqasc_console_putchar(struct uart_port *port, int ch)
568{
569 int fifofree;
570
571 if (!port->membase)
572 return;
573
574 do {
575 fifofree = (ltq_r32(port->membase + LTQ_ASC_FSTAT)
576 & ASCFSTAT_TXFREEMASK) >> ASCFSTAT_TXFREEOFF;
577 } while (fifofree == 0);
578 ltq_w8(ch, port->membase + LTQ_ASC_TBUF);
579}
580
ec84aa0a
MB		 581static void lqasc_serial_port_write(struct uart_port *port, const char *s,
582 u_int count)
583{
584 unsigned long flags;
585
586 spin_lock_irqsave(&ltq_asc_lock, flags);
587 uart_console_write(port, s, count, lqasc_console_putchar);
588 spin_unlock_irqrestore(&ltq_asc_lock, flags);
589}
2f0fc415
JC		 590
591static void
592lqasc_console_write(struct console *co, const char *s, u_int count)
593{
594 struct ltq_uart_port *ltq_port;
2f0fc415
JC		 595
596 if (co->index >= MAXPORTS)
597 return;
598
599 ltq_port = lqasc_port[co->index];
600 if (!ltq_port)
601 return;
602
ec84aa0a 603 lqasc_serial_port_write(&ltq_port->port, s, count);
2f0fc415
JC		 604}
605
606static int __init
607lqasc_console_setup(struct console *co, char *options)
608{
609 struct ltq_uart_port *ltq_port;
610 struct uart_port *port;
611 int baud = 115200;
612 int bits = 8;
613 int parity = 'n';
614 int flow = 'n';
615
616 if (co->index >= MAXPORTS)
617 return -ENODEV;
618
619 ltq_port = lqasc_port[co->index];
620 if (!ltq_port)
621 return -ENODEV;
622
623 port = &ltq_port->port;
624
7c658e6b
TL		 625 if (!IS_ERR(ltq_port->clk))
626 clk_enable(ltq_port->clk);
627
ceff2676 628 port->uartclk = clk_get_rate(ltq_port->fpiclk);
2f0fc415
JC		 629
630 if (options)
631 uart_parse_options(options, &baud, &parity, &bits, &flow);
632 return uart_set_options(port, co, baud, parity, bits, flow);
633}
634
635static struct console lqasc_console = {
636 .name = "ttyLTQ",
637 .write = lqasc_console_write,
638 .device = uart_console_device,
639 .setup = lqasc_console_setup,
640 .flags = CON_PRINTBUFFER,
641 .index = -1,
642 .data = &lqasc_reg,
643};
644
645static int __init
646lqasc_console_init(void)
647{
648 register_console(&lqasc_console);
649 return 0;
650}
651console_initcall(lqasc_console_init);
652
ec84aa0a
MB		 653static void lqasc_serial_early_console_write(struct console *co,
654 const char *s,
655 u_int count)
656{
657 struct earlycon_device *dev = co->data;
658
659 lqasc_serial_port_write(&dev->port, s, count);
660}
661
662static int __init
663lqasc_serial_early_console_setup(struct earlycon_device *device,
664 const char *opt)
665{
666 if (!device->port.membase)
667 return -ENODEV;
668
669 device->con->write = lqasc_serial_early_console_write;
670 return 0;
671}
672OF_EARLYCON_DECLARE(lantiq, DRVNAME, lqasc_serial_early_console_setup);
673
2f0fc415
JC		 674static struct uart_driver lqasc_reg = {
675 .owner = THIS_MODULE,
676 .driver_name = DRVNAME,
677 .dev_name = "ttyLTQ",
678 .major = 0,
679 .minor = 0,
680 .nr = MAXPORTS,
681 .cons = &lqasc_console,
682};
683
684static int __init
685lqasc_probe(struct platform_device *pdev)
686{
ceff2676 687 struct device_node *node = pdev->dev.of_node;
2f0fc415
JC		 688 struct ltq_uart_port *ltq_port;
689 struct uart_port *port;
ceff2676
JC		 690 struct resource *mmres, irqres[3];
691 int line = 0;
2f0fc415
JC		 692 int ret;
693
694 mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
ceff2676
JC		 695 ret = of_irq_to_resource_table(node, irqres, 3);
696 if (!mmres || (ret != 3)) {
697 dev_err(&pdev->dev,
698 "failed to get memory/irq for serial port\n");
2f0fc415 699 return -ENODEV;
ceff2676 700 }
2f0fc415 701
ceff2676
JC		 702 /* check if this is the console port */
703 if (mmres->start != CPHYSADDR(LTQ_EARLY_ASC))
704 line = 1;
2f0fc415 705
ceff2676
JC		 706 if (lqasc_port[line]) {
707 dev_err(&pdev->dev, "port %d already allocated\n", line);
2f0fc415 708 return -EBUSY;
2f0fc415
JC		 709 }
710
ceff2676
JC		 711 ltq_port = devm_kzalloc(&pdev->dev, sizeof(struct ltq_uart_port),
712 GFP_KERNEL);
2f0fc415
JC		 713 if (!ltq_port)
714 return -ENOMEM;
715
716 port = &ltq_port->port;
717
718 port->iotype = SERIAL_IO_MEM;
5fda7a0e 719 port->flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP;
2f0fc415
JC		 720 port->ops = &lqasc_pops;
721 port->fifosize = 16;
722 port->type = PORT_LTQ_ASC,
ceff2676 723 port->line = line;
2f0fc415 724 port->dev = &pdev->dev;
ceff2676
JC		 725 /* unused, just to be backward-compatible */
726 port->irq = irqres[0].start;
2f0fc415
JC		 727 port->mapbase = mmres->start;
728
ceff2676
JC		 729 ltq_port->fpiclk = clk_get_fpi();
730 if (IS_ERR(ltq_port->fpiclk)) {
731 pr_err("failed to get fpi clk\n");
732 return -ENOENT;
733 }
2f0fc415 734
ceff2676
JC		 735 /* not all asc ports have clock gates, lets ignore the return code */
736 ltq_port->clk = clk_get(&pdev->dev, NULL);
2f0fc415 737
ceff2676
JC		 738 ltq_port->tx_irq = irqres[0].start;
739 ltq_port->rx_irq = irqres[1].start;
740 ltq_port->err_irq = irqres[2].start;
741
742 lqasc_port[line] = ltq_port;
2f0fc415
JC		 743 platform_set_drvdata(pdev, ltq_port);
744
745 ret = uart_add_one_port(&lqasc_reg, port);
746
747 return ret;
748}
749
ceff2676
JC		 750static const struct of_device_id ltq_asc_match[] = {
751 { .compatible = DRVNAME },
752 {},
753};
ceff2676 754
2f0fc415
JC		 755static struct platform_driver lqasc_driver = {
756 .driver = {
757 .name = DRVNAME,
ceff2676 758 .of_match_table = ltq_asc_match,
2f0fc415
JC		 759 },
760};
761
762int __init
763init_lqasc(void)
764{
765 int ret;
766
767 ret = uart_register_driver(&lqasc_reg);
768 if (ret != 0)
769 return ret;
770
771 ret = platform_driver_probe(&lqasc_driver, lqasc_probe);
772 if (ret != 0)
773 uart_unregister_driver(&lqasc_reg);
774
775 return ret;
776}
1106d2db 777device_initcall(init_lqasc);
Linux 6.x block layer and io_uring tree(s)