projects / linux-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
tty: add SPDX identifiers to all remaining files in drivers/tty/
[linux-block.git] / drivers / tty / serial / ip22zilog.c
CommitLineData
e3b3d0f5 1// SPDX-License-Identifier: GPL-2.0
1da177e4
LT		 2/*
3 * Driver for Zilog serial chips found on SGI workstations and
4 * servers. This driver could actually be made more generic.
5 *
6 * This is based on the drivers/serial/sunzilog.c code as of 2.6.0-test7 and the
7 * old drivers/sgi/char/sgiserial.c code which itself is based of the original
8 * drivers/sbus/char/zs.c code. A lot of code has been simply moved over
9 * directly from there but much has been rewritten. Credits therefore go out
10 * to David S. Miller, Eddie C. Dost, Pete Zaitcev, Ted Ts'o and Alex Buell
11 * for their work there.
12 *
13 * Copyright (C) 2002 Ralf Baechle (ralf@linux-mips.org)
14 * Copyright (C) 2002 David S. Miller (davem@redhat.com)
15 */
1da177e4
LT		 16#include <linux/module.h>
17#include <linux/kernel.h>
1da177e4
LT		 18#include <linux/errno.h>
19#include <linux/delay.h>
20#include <linux/tty.h>
21#include <linux/tty_flip.h>
22#include <linux/major.h>
23#include <linux/string.h>
24#include <linux/ptrace.h>
25#include <linux/ioport.h>
26#include <linux/slab.h>
27#include <linux/circ_buf.h>
28#include <linux/serial.h>
29#include <linux/sysrq.h>
30#include <linux/console.h>
31#include <linux/spinlock.h>
32#include <linux/init.h>
33
34#include <asm/io.h>
35#include <asm/irq.h>
36#include <asm/sgialib.h>
37#include <asm/sgi/ioc.h>
38#include <asm/sgi/hpc3.h>
39#include <asm/sgi/ip22.h>
40
41#if defined(CONFIG_SERIAL_IP22_ZILOG_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
42#define SUPPORT_SYSRQ
43#endif
44
45#include <linux/serial_core.h>
46
47#include "ip22zilog.h"
48
1da177e4
LT		 49/*
50 * On IP22 we need to delay after register accesses but we do not need to
51 * flush writes.
52 */
53#define ZSDELAY() udelay(5)
54#define ZSDELAY_LONG() udelay(20)
55#define ZS_WSYNC(channel) do { } while (0)
56
57#define NUM_IP22ZILOG 1
58#define NUM_CHANNELS (NUM_IP22ZILOG * 2)
59
60#define ZS_CLOCK 3672000 /* Zilog input clock rate. */
61#define ZS_CLOCK_DIVISOR 16 /* Divisor this driver uses. */
62
63/*
64 * We wrap our port structure around the generic uart_port.
65 */
66struct uart_ip22zilog_port {
67 struct uart_port port;
68
69 /* IRQ servicing chain. */
70 struct uart_ip22zilog_port *next;
71
72 /* Current values of Zilog write registers. */
73 unsigned char curregs[NUM_ZSREGS];
74
75 unsigned int flags;
76#define IP22ZILOG_FLAG_IS_CONS 0x00000004
77#define IP22ZILOG_FLAG_IS_KGDB 0x00000008
78#define IP22ZILOG_FLAG_MODEM_STATUS 0x00000010
79#define IP22ZILOG_FLAG_IS_CHANNEL_A 0x00000020
80#define IP22ZILOG_FLAG_REGS_HELD 0x00000040
81#define IP22ZILOG_FLAG_TX_STOPPED 0x00000080
82#define IP22ZILOG_FLAG_TX_ACTIVE 0x00000100
68576cf1 83#define IP22ZILOG_FLAG_RESET_DONE 0x00000200
1da177e4 84
68576cf1 85 unsigned int tty_break;
1da177e4
LT		 86
87 unsigned char parity_mask;
88 unsigned char prev_status;
89};
90
91#define ZILOG_CHANNEL_FROM_PORT(PORT) ((struct zilog_channel *)((PORT)->membase))
92#define UART_ZILOG(PORT) ((struct uart_ip22zilog_port *)(PORT))
93#define IP22ZILOG_GET_CURR_REG(PORT, REGNUM) \
94 (UART_ZILOG(PORT)->curregs[REGNUM])
95#define IP22ZILOG_SET_CURR_REG(PORT, REGNUM, REGVAL) \
96 ((UART_ZILOG(PORT)->curregs[REGNUM]) = (REGVAL))
97#define ZS_IS_CONS(UP) ((UP)->flags & IP22ZILOG_FLAG_IS_CONS)
98#define ZS_IS_KGDB(UP) ((UP)->flags & IP22ZILOG_FLAG_IS_KGDB)
99#define ZS_WANTS_MODEM_STATUS(UP) ((UP)->flags & IP22ZILOG_FLAG_MODEM_STATUS)
100#define ZS_IS_CHANNEL_A(UP) ((UP)->flags & IP22ZILOG_FLAG_IS_CHANNEL_A)
101#define ZS_REGS_HELD(UP) ((UP)->flags & IP22ZILOG_FLAG_REGS_HELD)
102#define ZS_TX_STOPPED(UP) ((UP)->flags & IP22ZILOG_FLAG_TX_STOPPED)
103#define ZS_TX_ACTIVE(UP) ((UP)->flags & IP22ZILOG_FLAG_TX_ACTIVE)
104
105/* Reading and writing Zilog8530 registers. The delays are to make this
106 * driver work on the IP22 which needs a settling delay after each chip
107 * register access, other machines handle this in hardware via auxiliary
108 * flip-flops which implement the settle time we do in software.
109 *
110 * The port lock must be held and local IRQs must be disabled
111 * when {read,write}_zsreg is invoked.
112 */
113static unsigned char read_zsreg(struct zilog_channel *channel,
114 unsigned char reg)
115{
116 unsigned char retval;
117
118 writeb(reg, &channel->control);
119 ZSDELAY();
120 retval = readb(&channel->control);
121 ZSDELAY();
122
123 return retval;
124}
125
126static void write_zsreg(struct zilog_channel *channel,
127 unsigned char reg, unsigned char value)
128{
129 writeb(reg, &channel->control);
130 ZSDELAY();
131 writeb(value, &channel->control);
132 ZSDELAY();
133}
134
135static void ip22zilog_clear_fifo(struct zilog_channel *channel)
136{
137 int i;
138
139 for (i = 0; i < 32; i++) {
140 unsigned char regval;
141
142 regval = readb(&channel->control);
143 ZSDELAY();
144 if (regval & Rx_CH_AV)
145 break;
146
147 regval = read_zsreg(channel, R1);
148 readb(&channel->data);
149 ZSDELAY();
150
151 if (regval & (PAR_ERR | Rx_OVR | CRC_ERR)) {
152 writeb(ERR_RES, &channel->control);
153 ZSDELAY();
154 ZS_WSYNC(channel);
155 }
156 }
157}
158
159/* This function must only be called when the TX is not busy. The UART
160 * port lock must be held and local interrupts disabled.
161 */
162static void __load_zsregs(struct zilog_channel *channel, unsigned char *regs)
163{
164 int i;
165
166 /* Let pending transmits finish. */
167 for (i = 0; i < 1000; i++) {
168 unsigned char stat = read_zsreg(channel, R1);
169 if (stat & ALL_SNT)
170 break;
171 udelay(100);
172 }
173
174 writeb(ERR_RES, &channel->control);
175 ZSDELAY();
176 ZS_WSYNC(channel);
177
178 ip22zilog_clear_fifo(channel);
179
180 /* Disable all interrupts. */
181 write_zsreg(channel, R1,
182 regs[R1] & ~(RxINT_MASK | TxINT_ENAB | EXT_INT_ENAB));
183
184 /* Set parity, sync config, stop bits, and clock divisor. */
185 write_zsreg(channel, R4, regs[R4]);
186
187 /* Set misc. TX/RX control bits. */
188 write_zsreg(channel, R10, regs[R10]);
189
190 /* Set TX/RX controls sans the enable bits. */
191 write_zsreg(channel, R3, regs[R3] & ~RxENAB);
192 write_zsreg(channel, R5, regs[R5] & ~TxENAB);
193
194 /* Synchronous mode config. */
195 write_zsreg(channel, R6, regs[R6]);
196 write_zsreg(channel, R7, regs[R7]);
197
198 /* Don't mess with the interrupt vector (R2, unused by us) and
199 * master interrupt control (R9). We make sure this is setup
200 * properly at probe time then never touch it again.
201 */
202
203 /* Disable baud generator. */
204 write_zsreg(channel, R14, regs[R14] & ~BRENAB);
205
206 /* Clock mode control. */
207 write_zsreg(channel, R11, regs[R11]);
208
209 /* Lower and upper byte of baud rate generator divisor. */
210 write_zsreg(channel, R12, regs[R12]);
211 write_zsreg(channel, R13, regs[R13]);
7369a8b3 212
1da177e4
LT		 213 /* Now rewrite R14, with BRENAB (if set). */
214 write_zsreg(channel, R14, regs[R14]);
215
216 /* External status interrupt control. */
217 write_zsreg(channel, R15, regs[R15]);
218
219 /* Reset external status interrupts. */
220 write_zsreg(channel, R0, RES_EXT_INT);
221 write_zsreg(channel, R0, RES_EXT_INT);
222
223 /* Rewrite R3/R5, this time without enables masked. */
224 write_zsreg(channel, R3, regs[R3]);
225 write_zsreg(channel, R5, regs[R5]);
226
227 /* Rewrite R1, this time without IRQ enabled masked. */
228 write_zsreg(channel, R1, regs[R1]);
229}
230
231/* Reprogram the Zilog channel HW registers with the copies found in the
232 * software state struct. If the transmitter is busy, we defer this update
233 * until the next TX complete interrupt. Else, we do it right now.
234 *
235 * The UART port lock must be held and local interrupts disabled.
236 */
237static void ip22zilog_maybe_update_regs(struct uart_ip22zilog_port *up,
238 struct zilog_channel *channel)
239{
240 if (!ZS_REGS_HELD(up)) {
241 if (ZS_TX_ACTIVE(up)) {
242 up->flags |= IP22ZILOG_FLAG_REGS_HELD;
243 } else {
244 __load_zsregs(channel, up->curregs);
245 }
246 }
247}
248
68576cf1
TB		 249#define Rx_BRK 0x0100 /* BREAK event software flag. */
250#define Rx_SYS 0x0200 /* SysRq event software flag. */
251
2894500d 252static bool ip22zilog_receive_chars(struct uart_ip22zilog_port *up,
68576cf1 253 struct zilog_channel *channel)
1da177e4 254{
68576cf1
TB		 255 unsigned char ch, flag;
256 unsigned int r1;
2894500d 257 bool push = up->port.state != NULL;
68576cf1
TB		 258
259 for (;;) {
260 ch = readb(&channel->control);
261 ZSDELAY();
262 if (!(ch & Rx_CH_AV))
263 break;
1da177e4
LT		 264
265 r1 = read_zsreg(channel, R1);
266 if (r1 & (PAR_ERR | Rx_OVR | CRC_ERR)) {
267 writeb(ERR_RES, &channel->control);
268 ZSDELAY();
269 ZS_WSYNC(channel);
270 }
271
1da177e4
LT		 272 ch = readb(&channel->data);
273 ZSDELAY();
274
275 ch &= up->parity_mask;
276
68576cf1
TB		 277 /* Handle the null char got when BREAK is removed. */
278 if (!ch)
279 r1 |= up->tty_break;
1da177e4
LT		 280
281 /* A real serial line, record the character and status. */
33f0f88f 282 flag = TTY_NORMAL;
1da177e4 283 up->port.icount.rx++;
68576cf1
TB		 284 if (r1 & (PAR_ERR | Rx_OVR | CRC_ERR | Rx_SYS | Rx_BRK)) {
285 up->tty_break = 0;
286
287 if (r1 & (Rx_SYS | Rx_BRK)) {
1da177e4 288 up->port.icount.brk++;
68576cf1
TB		 289 if (r1 & Rx_SYS)
290 continue;
291 r1 &= ~(PAR_ERR | CRC_ERR);
1da177e4
LT		 292 }
293 else if (r1 & PAR_ERR)
294 up->port.icount.parity++;
295 else if (r1 & CRC_ERR)
296 up->port.icount.frame++;
297 if (r1 & Rx_OVR)
298 up->port.icount.overrun++;
299 r1 &= up->port.read_status_mask;
68576cf1 300 if (r1 & Rx_BRK)
33f0f88f 301 flag = TTY_BREAK;
1da177e4 302 else if (r1 & PAR_ERR)
33f0f88f 303 flag = TTY_PARITY;
1da177e4 304 else if (r1 & CRC_ERR)
33f0f88f 305 flag = TTY_FRAME;
1da177e4 306 }
1da177e4 307
68576cf1
TB		 308 if (uart_handle_sysrq_char(&up->port, ch))
309 continue;
33f0f88f 310
2894500d 311 if (push)
68576cf1 312 uart_insert_char(&up->port, r1, Rx_OVR, ch, flag);
1da177e4 313 }
2894500d 314 return push;
1da177e4
LT		 315}
316
317static void ip22zilog_status_handle(struct uart_ip22zilog_port *up,
7d12e780 318 struct zilog_channel *channel)
1da177e4
LT		 319{
320 unsigned char status;
321
322 status = readb(&channel->control);
323 ZSDELAY();
324
325 writeb(RES_EXT_INT, &channel->control);
326 ZSDELAY();
327 ZS_WSYNC(channel);
328
68576cf1
TB		 329 if (up->curregs[R15] & BRKIE) {
330 if ((status & BRK_ABRT) && !(up->prev_status & BRK_ABRT)) {
331 if (uart_handle_break(&up->port))
332 up->tty_break = Rx_SYS;
333 else
334 up->tty_break = Rx_BRK;
335 }
336 }
337
1da177e4
LT		 338 if (ZS_WANTS_MODEM_STATUS(up)) {
339 if (status & SYNC)
340 up->port.icount.dsr++;
341
342 /* The Zilog just gives us an interrupt when DCD/CTS/etc. change.
343 * But it does not tell us which bit has changed, we have to keep
344 * track of this ourselves.
345 */
68576cf1 346 if ((status ^ up->prev_status) ^ DCD)
1da177e4
LT		 347 uart_handle_dcd_change(&up->port,
348 (status & DCD));
68576cf1 349 if ((status ^ up->prev_status) ^ CTS)
1da177e4
LT		 350 uart_handle_cts_change(&up->port,
351 (status & CTS));
352
bdc04e31 353 wake_up_interruptible(&up->port.state->port.delta_msr_wait);
1da177e4
LT		 354 }
355
356 up->prev_status = status;
357}
358
359static void ip22zilog_transmit_chars(struct uart_ip22zilog_port *up,
360 struct zilog_channel *channel)
361{
362 struct circ_buf *xmit;
363
364 if (ZS_IS_CONS(up)) {
365 unsigned char status = readb(&channel->control);
366 ZSDELAY();
367
368 /* TX still busy? Just wait for the next TX done interrupt.
369 *
370 * It can occur because of how we do serial console writes. It would
371 * be nice to transmit console writes just like we normally would for
372 * a TTY line. (ie. buffered and TX interrupt driven). That is not
373 * easy because console writes cannot sleep. One solution might be
25985edc 374 * to poll on enough port->xmit space becoming free. -DaveM
1da177e4
LT		 375 */
376 if (!(status & Tx_BUF_EMP))
377 return;
378 }
379
380 up->flags &= ~IP22ZILOG_FLAG_TX_ACTIVE;
381
382 if (ZS_REGS_HELD(up)) {
383 __load_zsregs(channel, up->curregs);
384 up->flags &= ~IP22ZILOG_FLAG_REGS_HELD;
385 }
386
387 if (ZS_TX_STOPPED(up)) {
388 up->flags &= ~IP22ZILOG_FLAG_TX_STOPPED;
389 goto ack_tx_int;
390 }
391
392 if (up->port.x_char) {
393 up->flags |= IP22ZILOG_FLAG_TX_ACTIVE;
394 writeb(up->port.x_char, &channel->data);
395 ZSDELAY();
396 ZS_WSYNC(channel);
397
398 up->port.icount.tx++;
399 up->port.x_char = 0;
400 return;
401 }
402
ebd2c8f6 403 if (up->port.state == NULL)
1da177e4 404 goto ack_tx_int;
ebd2c8f6 405 xmit = &up->port.state->xmit;
c4432c41 406 if (uart_circ_empty(xmit))
1da177e4 407 goto ack_tx_int;
1da177e4
LT		 408 if (uart_tx_stopped(&up->port))
409 goto ack_tx_int;
410
411 up->flags |= IP22ZILOG_FLAG_TX_ACTIVE;
412 writeb(xmit->buf[xmit->tail], &channel->data);
413 ZSDELAY();
414 ZS_WSYNC(channel);
415
416 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
417 up->port.icount.tx++;
418
419 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
420 uart_write_wakeup(&up->port);
421
422 return;
423
424ack_tx_int:
425 writeb(RES_Tx_P, &channel->control);
426 ZSDELAY();
427 ZS_WSYNC(channel);
428}
429
7d12e780 430static irqreturn_t ip22zilog_interrupt(int irq, void *dev_id)
1da177e4
LT		 431{
432 struct uart_ip22zilog_port *up = dev_id;
433
434 while (up) {
435 struct zilog_channel *channel
436 = ZILOG_CHANNEL_FROM_PORT(&up->port);
437 unsigned char r3;
2894500d 438 bool push = false;
1da177e4
LT		 439
440 spin_lock(&up->port.lock);
441 r3 = read_zsreg(channel, R3);
442
443 /* Channel A */
444 if (r3 & (CHAEXT | CHATxIP | CHARxIP)) {
445 writeb(RES_H_IUS, &channel->control);
446 ZSDELAY();
447 ZS_WSYNC(channel);
448
449 if (r3 & CHARxIP)
2894500d 450 push = ip22zilog_receive_chars(up, channel);
1da177e4 451 if (r3 & CHAEXT)
7d12e780 452 ip22zilog_status_handle(up, channel);
1da177e4
LT		 453 if (r3 & CHATxIP)
454 ip22zilog_transmit_chars(up, channel);
455 }
456 spin_unlock(&up->port.lock);
457
2894500d
JS		 458 if (push)
459 tty_flip_buffer_push(&up->port.state->port);
68576cf1 460
1da177e4
LT		 461 /* Channel B */
462 up = up->next;
463 channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
2894500d 464 push = false;
1da177e4
LT		 465
466 spin_lock(&up->port.lock);
467 if (r3 & (CHBEXT | CHBTxIP | CHBRxIP)) {
468 writeb(RES_H_IUS, &channel->control);
469 ZSDELAY();
470 ZS_WSYNC(channel);
471
472 if (r3 & CHBRxIP)
2894500d 473 push = ip22zilog_receive_chars(up, channel);
1da177e4 474 if (r3 & CHBEXT)
7d12e780 475 ip22zilog_status_handle(up, channel);
1da177e4
LT		 476 if (r3 & CHBTxIP)
477 ip22zilog_transmit_chars(up, channel);
478 }
479 spin_unlock(&up->port.lock);
480
2894500d
JS		 481 if (push)
482 tty_flip_buffer_push(&up->port.state->port);
68576cf1 483
1da177e4
LT		 484 up = up->next;
485 }
486
487 return IRQ_HANDLED;
488}
489
490/* A convenient way to quickly get R0 status. The caller must _not_ hold the
491 * port lock, it is acquired here.
492 */
493static __inline__ unsigned char ip22zilog_read_channel_status(struct uart_port *port)
494{
495 struct zilog_channel *channel;
1da177e4
LT		 496 unsigned char status;
497
1da177e4
LT		 498 channel = ZILOG_CHANNEL_FROM_PORT(port);
499 status = readb(&channel->control);
500 ZSDELAY();
501
1da177e4
LT		 502 return status;
503}
504
505/* The port lock is not held. */
506static unsigned int ip22zilog_tx_empty(struct uart_port *port)
507{
c5f4644e 508 unsigned long flags;
1da177e4
LT		 509 unsigned char status;
510 unsigned int ret;
511
c5f4644e
RK		 512 spin_lock_irqsave(&port->lock, flags);
513
1da177e4 514 status = ip22zilog_read_channel_status(port);
c5f4644e
RK		 515
516 spin_unlock_irqrestore(&port->lock, flags);
517
1da177e4
LT		 518 if (status & Tx_BUF_EMP)
519 ret = TIOCSER_TEMT;
520 else
521 ret = 0;
522
523 return ret;
524}
525
c5f4644e 526/* The port lock is held and interrupts are disabled. */
1da177e4
LT		 527static unsigned int ip22zilog_get_mctrl(struct uart_port *port)
528{
529 unsigned char status;
530 unsigned int ret;
531
532 status = ip22zilog_read_channel_status(port);
533
534 ret = 0;
535 if (status & DCD)
536 ret |= TIOCM_CAR;
537 if (status & SYNC)
538 ret |= TIOCM_DSR;
539 if (status & CTS)
540 ret |= TIOCM_CTS;
541
542 return ret;
543}
544
545/* The port lock is held and interrupts are disabled. */
546static void ip22zilog_set_mctrl(struct uart_port *port, unsigned int mctrl)
547{
2413b320
FF		 548 struct uart_ip22zilog_port *up =
549 container_of(port, struct uart_ip22zilog_port, port);
1da177e4
LT		 550 struct zilog_channel *channel = ZILOG_CHANNEL_FROM_PORT(port);
551 unsigned char set_bits, clear_bits;
552
553 set_bits = clear_bits = 0;
554
555 if (mctrl & TIOCM_RTS)
556 set_bits |= RTS;
557 else
558 clear_bits |= RTS;
559 if (mctrl & TIOCM_DTR)
560 set_bits |= DTR;
561 else
562 clear_bits |= DTR;
563
7369a8b3 564 /* NOTE: Not subject to 'transmitter active' rule. */
1da177e4
LT		 565 up->curregs[R5] |= set_bits;
566 up->curregs[R5] &= ~clear_bits;
567 write_zsreg(channel, R5, up->curregs[R5]);
568}
569
570/* The port lock is held and interrupts are disabled. */
b129a8cc 571static void ip22zilog_stop_tx(struct uart_port *port)
1da177e4 572{
2413b320
FF		 573 struct uart_ip22zilog_port *up =
574 container_of(port, struct uart_ip22zilog_port, port);
1da177e4
LT		 575
576 up->flags |= IP22ZILOG_FLAG_TX_STOPPED;
577}
578
579/* The port lock is held and interrupts are disabled. */
b129a8cc 580static void ip22zilog_start_tx(struct uart_port *port)
1da177e4 581{
2413b320
FF		 582 struct uart_ip22zilog_port *up =
583 container_of(port, struct uart_ip22zilog_port, port);
1da177e4
LT		 584 struct zilog_channel *channel = ZILOG_CHANNEL_FROM_PORT(port);
585 unsigned char status;
586
587 up->flags |= IP22ZILOG_FLAG_TX_ACTIVE;
588 up->flags &= ~IP22ZILOG_FLAG_TX_STOPPED;
589
590 status = readb(&channel->control);
591 ZSDELAY();
592
593 /* TX busy? Just wait for the TX done interrupt. */
594 if (!(status & Tx_BUF_EMP))
595 return;
596
597 /* Send the first character to jump-start the TX done
598 * IRQ sending engine.
599 */
600 if (port->x_char) {
601 writeb(port->x_char, &channel->data);
602 ZSDELAY();
603 ZS_WSYNC(channel);
604
605 port->icount.tx++;
606 port->x_char = 0;
607 } else {
ebd2c8f6 608 struct circ_buf *xmit = &port->state->xmit;
1da177e4 609
c557d392
PH		 610 if (uart_circ_empty(xmit))
611 return;
1da177e4
LT		 612 writeb(xmit->buf[xmit->tail], &channel->data);
613 ZSDELAY();
614 ZS_WSYNC(channel);
615
616 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
617 port->icount.tx++;
618
619 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
620 uart_write_wakeup(&up->port);
621 }
622}
623
624/* The port lock is held and interrupts are disabled. */
625static void ip22zilog_stop_rx(struct uart_port *port)
626{
627 struct uart_ip22zilog_port *up = UART_ZILOG(port);
628 struct zilog_channel *channel;
629
630 if (ZS_IS_CONS(up))
631 return;
632
633 channel = ZILOG_CHANNEL_FROM_PORT(port);
634
635 /* Disable all RX interrupts. */
636 up->curregs[R1] &= ~RxINT_MASK;
637 ip22zilog_maybe_update_regs(up, channel);
638}
639
640/* The port lock is held. */
641static void ip22zilog_enable_ms(struct uart_port *port)
642{
2413b320
FF		 643 struct uart_ip22zilog_port *up =
644 container_of(port, struct uart_ip22zilog_port, port);
1da177e4
LT		 645 struct zilog_channel *channel = ZILOG_CHANNEL_FROM_PORT(port);
646 unsigned char new_reg;
647
648 new_reg = up->curregs[R15] | (DCDIE | SYNCIE | CTSIE);
649 if (new_reg != up->curregs[R15]) {
650 up->curregs[R15] = new_reg;
651
7369a8b3 652 /* NOTE: Not subject to 'transmitter active' rule. */
1da177e4
LT		 653 write_zsreg(channel, R15, up->curregs[R15]);
654 }
655}
656
657/* The port lock is not held. */
658static void ip22zilog_break_ctl(struct uart_port *port, int break_state)
659{
2413b320
FF		 660 struct uart_ip22zilog_port *up =
661 container_of(port, struct uart_ip22zilog_port, port);
1da177e4
LT		 662 struct zilog_channel *channel = ZILOG_CHANNEL_FROM_PORT(port);
663 unsigned char set_bits, clear_bits, new_reg;
664 unsigned long flags;
665
666 set_bits = clear_bits = 0;
667
668 if (break_state)
669 set_bits |= SND_BRK;
670 else
671 clear_bits |= SND_BRK;
672
673 spin_lock_irqsave(&port->lock, flags);
674
675 new_reg = (up->curregs[R5] | set_bits) & ~clear_bits;
676 if (new_reg != up->curregs[R5]) {
677 up->curregs[R5] = new_reg;
678
7369a8b3 679 /* NOTE: Not subject to 'transmitter active' rule. */
1da177e4
LT		 680 write_zsreg(channel, R5, up->curregs[R5]);
681 }
682
683 spin_unlock_irqrestore(&port->lock, flags);
684}
685
68576cf1
TB		 686static void __ip22zilog_reset(struct uart_ip22zilog_port *up)
687{
688 struct zilog_channel *channel;
689 int i;
690
691 if (up->flags & IP22ZILOG_FLAG_RESET_DONE)
692 return;
693
694 /* Let pending transmits finish. */
695 channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
696 for (i = 0; i < 1000; i++) {
697 unsigned char stat = read_zsreg(channel, R1);
698 if (stat & ALL_SNT)
699 break;
700 udelay(100);
701 }
702
703 if (!ZS_IS_CHANNEL_A(up)) {
704 up++;
705 channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
706 }
707 write_zsreg(channel, R9, FHWRES);
708 ZSDELAY_LONG();
709 (void) read_zsreg(channel, R0);
710
711 up->flags |= IP22ZILOG_FLAG_RESET_DONE;
712 up->next->flags |= IP22ZILOG_FLAG_RESET_DONE;
713}
714
1da177e4
LT		 715static void __ip22zilog_startup(struct uart_ip22zilog_port *up)
716{
717 struct zilog_channel *channel;
718
719 channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
68576cf1
TB		 720
721 __ip22zilog_reset(up);
722
723 __load_zsregs(channel, up->curregs);
724 /* set master interrupt enable */
725 write_zsreg(channel, R9, up->curregs[R9]);
1da177e4
LT		 726 up->prev_status = readb(&channel->control);
727
728 /* Enable receiver and transmitter. */
729 up->curregs[R3] |= RxENAB;
730 up->curregs[R5] |= TxENAB;
731
732 up->curregs[R1] |= EXT_INT_ENAB | INT_ALL_Rx | TxINT_ENAB;
733 ip22zilog_maybe_update_regs(up, channel);
734}
735
736static int ip22zilog_startup(struct uart_port *port)
737{
738 struct uart_ip22zilog_port *up = UART_ZILOG(port);
739 unsigned long flags;
740
741 if (ZS_IS_CONS(up))
742 return 0;
743
744 spin_lock_irqsave(&port->lock, flags);
745 __ip22zilog_startup(up);
746 spin_unlock_irqrestore(&port->lock, flags);
747 return 0;
748}
749
750/*
751 * The test for ZS_IS_CONS is explained by the following e-mail:
752 *****
753 * From: Russell King <rmk@arm.linux.org.uk>
754 * Date: Sun, 8 Dec 2002 10:18:38 +0000
755 *
756 * On Sun, Dec 08, 2002 at 02:43:36AM -0500, Pete Zaitcev wrote:
757 * > I boot my 2.5 boxes using "console=ttyS0,9600" argument,
758 * > and I noticed that something is not right with reference
759 * > counting in this case. It seems that when the console
760 * > is open by kernel initially, this is not accounted
761 * > as an open, and uart_startup is not called.
762 *
763 * That is correct. We are unable to call uart_startup when the serial
764 * console is initialised because it may need to allocate memory (as
765 * request_irq does) and the memory allocators may not have been
766 * initialised.
767 *
768 * 1. initialise the port into a state where it can send characters in the
769 * console write method.
770 *
771 * 2. don't do the actual hardware shutdown in your shutdown() method (but
772 * do the normal software shutdown - ie, free irqs etc)
773 *****
774 */
775static void ip22zilog_shutdown(struct uart_port *port)
776{
777 struct uart_ip22zilog_port *up = UART_ZILOG(port);
778 struct zilog_channel *channel;
779 unsigned long flags;
780
781 if (ZS_IS_CONS(up))
782 return;
783
784 spin_lock_irqsave(&port->lock, flags);
785
786 channel = ZILOG_CHANNEL_FROM_PORT(port);
787
788 /* Disable receiver and transmitter. */
789 up->curregs[R3] &= ~RxENAB;
790 up->curregs[R5] &= ~TxENAB;
791
792 /* Disable all interrupts and BRK assertion. */
793 up->curregs[R1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK);
794 up->curregs[R5] &= ~SND_BRK;
795 ip22zilog_maybe_update_regs(up, channel);
796
797 spin_unlock_irqrestore(&port->lock, flags);
798}
799
800/* Shared by TTY driver and serial console setup. The port lock is held
801 * and local interrupts are disabled.
802 */
803static void
804ip22zilog_convert_to_zs(struct uart_ip22zilog_port *up, unsigned int cflag,
805 unsigned int iflag, int brg)
806{
807
808 up->curregs[R10] = NRZ;
809 up->curregs[R11] = TCBR | RCBR;
810
811 /* Program BAUD and clock source. */
812 up->curregs[R4] &= ~XCLK_MASK;
813 up->curregs[R4] |= X16CLK;
814 up->curregs[R12] = brg & 0xff;
815 up->curregs[R13] = (brg >> 8) & 0xff;
816 up->curregs[R14] = BRENAB;
817
818 /* Character size, stop bits, and parity. */
819 up->curregs[3] &= ~RxN_MASK;
820 up->curregs[5] &= ~TxN_MASK;
821 switch (cflag & CSIZE) {
822 case CS5:
823 up->curregs[3] |= Rx5;
824 up->curregs[5] |= Tx5;
825 up->parity_mask = 0x1f;
826 break;
827 case CS6:
828 up->curregs[3] |= Rx6;
829 up->curregs[5] |= Tx6;
830 up->parity_mask = 0x3f;
831 break;
832 case CS7:
833 up->curregs[3] |= Rx7;
834 up->curregs[5] |= Tx7;
835 up->parity_mask = 0x7f;
836 break;
837 case CS8:
838 default:
839 up->curregs[3] |= Rx8;
840 up->curregs[5] |= Tx8;
841 up->parity_mask = 0xff;
842 break;
fc811472 843 }
1da177e4
LT		 844 up->curregs[4] &= ~0x0c;
845 if (cflag & CSTOPB)
846 up->curregs[4] |= SB2;
847 else
848 up->curregs[4] |= SB1;
849 if (cflag & PARENB)
850 up->curregs[4] |= PAR_ENAB;
851 else
852 up->curregs[4] &= ~PAR_ENAB;
853 if (!(cflag & PARODD))
854 up->curregs[4] |= PAR_EVEN;
855 else
856 up->curregs[4] &= ~PAR_EVEN;
857
858 up->port.read_status_mask = Rx_OVR;
859 if (iflag & INPCK)
860 up->port.read_status_mask |= CRC_ERR | PAR_ERR;
ef8b9ddc 861 if (iflag & (IGNBRK | BRKINT | PARMRK))
1da177e4
LT		 862 up->port.read_status_mask |= BRK_ABRT;
863
864 up->port.ignore_status_mask = 0;
865 if (iflag & IGNPAR)
866 up->port.ignore_status_mask |= CRC_ERR | PAR_ERR;
867 if (iflag & IGNBRK) {
868 up->port.ignore_status_mask |= BRK_ABRT;
869 if (iflag & IGNPAR)
870 up->port.ignore_status_mask |= Rx_OVR;
871 }
872
873 if ((cflag & CREAD) == 0)
874 up->port.ignore_status_mask = 0xff;
875}
876
877/* The port lock is not held. */
878static void
606d099c
AC		 879ip22zilog_set_termios(struct uart_port *port, struct ktermios *termios,
880 struct ktermios *old)
1da177e4 881{
2413b320
FF		 882 struct uart_ip22zilog_port *up =
883 container_of(port, struct uart_ip22zilog_port, port);
1da177e4
LT		 884 unsigned long flags;
885 int baud, brg;
886
887 baud = uart_get_baud_rate(port, termios, old, 1200, 76800);
888
889 spin_lock_irqsave(&up->port.lock, flags);
890
891 brg = BPS_TO_BRG(baud, ZS_CLOCK / ZS_CLOCK_DIVISOR);
892
893 ip22zilog_convert_to_zs(up, termios->c_cflag, termios->c_iflag, brg);
894
895 if (UART_ENABLE_MS(&up->port, termios->c_cflag))
896 up->flags |= IP22ZILOG_FLAG_MODEM_STATUS;
897 else
898 up->flags &= ~IP22ZILOG_FLAG_MODEM_STATUS;
899
1da177e4 900 ip22zilog_maybe_update_regs(up, ZILOG_CHANNEL_FROM_PORT(port));
c1fbac44 901 uart_update_timeout(port, termios->c_cflag, baud);
1da177e4
LT		 902
903 spin_unlock_irqrestore(&up->port.lock, flags);
904}
905
906static const char *ip22zilog_type(struct uart_port *port)
907{
908 return "IP22-Zilog";
909}
910
911/* We do not request/release mappings of the registers here, this
912 * happens at early serial probe time.
913 */
914static void ip22zilog_release_port(struct uart_port *port)
915{
916}
917
918static int ip22zilog_request_port(struct uart_port *port)
919{
920 return 0;
921}
922
923/* These do not need to do anything interesting either. */
924static void ip22zilog_config_port(struct uart_port *port, int flags)
925{
926}
927
928/* We do not support letting the user mess with the divisor, IRQ, etc. */
929static int ip22zilog_verify_port(struct uart_port *port, struct serial_struct *ser)
930{
931 return -EINVAL;
932}
933
2331e068 934static const struct uart_ops ip22zilog_pops = {
1da177e4
LT		 935 .tx_empty = ip22zilog_tx_empty,
936 .set_mctrl = ip22zilog_set_mctrl,
937 .get_mctrl = ip22zilog_get_mctrl,
938 .stop_tx = ip22zilog_stop_tx,
939 .start_tx = ip22zilog_start_tx,
940 .stop_rx = ip22zilog_stop_rx,
941 .enable_ms = ip22zilog_enable_ms,
942 .break_ctl = ip22zilog_break_ctl,
943 .startup = ip22zilog_startup,
944 .shutdown = ip22zilog_shutdown,
945 .set_termios = ip22zilog_set_termios,
946 .type = ip22zilog_type,
947 .release_port = ip22zilog_release_port,
948 .request_port = ip22zilog_request_port,
949 .config_port = ip22zilog_config_port,
950 .verify_port = ip22zilog_verify_port,
951};
952
953static struct uart_ip22zilog_port *ip22zilog_port_table;
954static struct zilog_layout **ip22zilog_chip_regs;
955
956static struct uart_ip22zilog_port *ip22zilog_irq_chain;
957static int zilog_irq = -1;
958
959static void * __init alloc_one_table(unsigned long size)
960{
8f31bb39 961 return kzalloc(size, GFP_KERNEL);
1da177e4
LT		 962}
963
964static void __init ip22zilog_alloc_tables(void)
965{
966 ip22zilog_port_table = (struct uart_ip22zilog_port *)
967 alloc_one_table(NUM_CHANNELS * sizeof(struct uart_ip22zilog_port));
968 ip22zilog_chip_regs = (struct zilog_layout **)
969 alloc_one_table(NUM_IP22ZILOG * sizeof(struct zilog_layout *));
970
971 if (ip22zilog_port_table == NULL || ip22zilog_chip_regs == NULL) {
972 panic("IP22-Zilog: Cannot allocate IP22-Zilog tables.");
973 }
974}
975
976/* Get the address of the registers for IP22-Zilog instance CHIP. */
977static struct zilog_layout * __init get_zs(int chip)
978{
979 unsigned long base;
980
981 if (chip < 0 || chip >= NUM_IP22ZILOG) {
982 panic("IP22-Zilog: Illegal chip number %d in get_zs.", chip);
983 }
984
985 /* Not probe-able, hard code it. */
986 base = (unsigned long) &sgioc->uart;
987
988 zilog_irq = SGI_SERIAL_IRQ;
989 request_mem_region(base, 8, "IP22-Zilog");
990
991 return (struct zilog_layout *) base;
992}
993
994#define ZS_PUT_CHAR_MAX_DELAY 2000 /* 10 ms */
995
996#ifdef CONFIG_SERIAL_IP22_ZILOG_CONSOLE
d358788f 997static void ip22zilog_put_char(struct uart_port *port, int ch)
1da177e4 998{
d358788f 999 struct zilog_channel *channel = ZILOG_CHANNEL_FROM_PORT(port);
1da177e4
LT		 1000 int loops = ZS_PUT_CHAR_MAX_DELAY;
1001
1002 /* This is a timed polling loop so do not switch the explicit
1003 * udelay with ZSDELAY as that is a NOP on some platforms. -DaveM
1004 */
1005 do {
1006 unsigned char val = readb(&channel->control);
1007 if (val & Tx_BUF_EMP) {
1008 ZSDELAY();
1009 break;
1010 }
1011 udelay(5);
1012 } while (--loops);
1013
1014 writeb(ch, &channel->data);
1015 ZSDELAY();
1016 ZS_WSYNC(channel);
1017}
1018
1019static void
1020ip22zilog_console_write(struct console *con, const char *s, unsigned int count)
1021{
1022 struct uart_ip22zilog_port *up = &ip22zilog_port_table[con->index];
1da177e4 1023 unsigned long flags;
1da177e4
LT		 1024
1025 spin_lock_irqsave(&up->port.lock, flags);
d358788f 1026 uart_console_write(&up->port, s, count, ip22zilog_put_char);
1da177e4
LT		 1027 udelay(2);
1028 spin_unlock_irqrestore(&up->port.lock, flags);
1029}
1030
1da177e4
LT		 1031static int __init ip22zilog_console_setup(struct console *con, char *options)
1032{
1033 struct uart_ip22zilog_port *up = &ip22zilog_port_table[con->index];
1034 unsigned long flags;
68576cf1
TB		 1035 int baud = 9600, bits = 8;
1036 int parity = 'n';
1037 int flow = 'n';
1da177e4 1038
68576cf1 1039 up->flags |= IP22ZILOG_FLAG_IS_CONS;
1da177e4 1040
68576cf1 1041 printk(KERN_INFO "Console: ttyS%d (IP22-Zilog)\n", con->index);
1da177e4
LT		 1042
1043 spin_lock_irqsave(&up->port.lock, flags);
1044
68576cf1 1045 up->curregs[R15] |= BRKIE;
1da177e4
LT		 1046
1047 __ip22zilog_startup(up);
1048
1049 spin_unlock_irqrestore(&up->port.lock, flags);
1050
68576cf1
TB		 1051 if (options)
1052 uart_parse_options(options, &baud, &parity, &bits, &flow);
1053 return uart_set_options(&up->port, con, baud, parity, bits, flow);
1da177e4
LT		 1054}
1055
1056static struct uart_driver ip22zilog_reg;
1057
1058static struct console ip22zilog_console = {
1059 .name = "ttyS",
1060 .write = ip22zilog_console_write,
1061 .device = uart_console_device,
1062 .setup = ip22zilog_console_setup,
1063 .flags = CON_PRINTBUFFER,
1064 .index = -1,
1065 .data = &ip22zilog_reg,
1066};
1067#endif /* CONFIG_SERIAL_IP22_ZILOG_CONSOLE */
1068
1069static struct uart_driver ip22zilog_reg = {
1070 .owner = THIS_MODULE,
1071 .driver_name = "serial",
1da177e4
LT		 1072 .dev_name = "ttyS",
1073 .major = TTY_MAJOR,
1074 .minor = 64,
1075 .nr = NUM_CHANNELS,
1076#ifdef CONFIG_SERIAL_IP22_ZILOG_CONSOLE
1077 .cons = &ip22zilog_console,
1078#endif
1079};
1080
1081static void __init ip22zilog_prepare(void)
1082{
1083 struct uart_ip22zilog_port *up;
1084 struct zilog_layout *rp;
1085 int channel, chip;
1086
1087 /*
1088 * Temporary fix.
1089 */
1090 for (channel = 0; channel < NUM_CHANNELS; channel++)
1091 spin_lock_init(&ip22zilog_port_table[channel].port.lock);
1092
1093 ip22zilog_irq_chain = &ip22zilog_port_table[NUM_CHANNELS - 1];
1094 up = &ip22zilog_port_table[0];
1095 for (channel = NUM_CHANNELS - 1 ; channel > 0; channel--)
1096 up[channel].next = &up[channel - 1];
1097 up[channel].next = NULL;
1098
1099 for (chip = 0; chip < NUM_IP22ZILOG; chip++) {
1100 if (!ip22zilog_chip_regs[chip]) {
1101 ip22zilog_chip_regs[chip] = rp = get_zs(chip);
1102
1103 up[(chip * 2) + 0].port.membase = (char *) &rp->channelB;
1104 up[(chip * 2) + 1].port.membase = (char *) &rp->channelA;
1105
1106 /* In theory mapbase is the physical address ... */
1107 up[(chip * 2) + 0].port.mapbase =
1108 (unsigned long) ioremap((unsigned long) &rp->channelB, 8);
1109 up[(chip * 2) + 1].port.mapbase =
1110 (unsigned long) ioremap((unsigned long) &rp->channelA, 8);
1111 }
1112
1113 /* Channel A */
1114 up[(chip * 2) + 0].port.iotype = UPIO_MEM;
1115 up[(chip * 2) + 0].port.irq = zilog_irq;
1116 up[(chip * 2) + 0].port.uartclk = ZS_CLOCK;
1117 up[(chip * 2) + 0].port.fifosize = 1;
1118 up[(chip * 2) + 0].port.ops = &ip22zilog_pops;
1119 up[(chip * 2) + 0].port.type = PORT_IP22ZILOG;
1120 up[(chip * 2) + 0].port.flags = 0;
1121 up[(chip * 2) + 0].port.line = (chip * 2) + 0;
1122 up[(chip * 2) + 0].flags = 0;
1123
1124 /* Channel B */
1125 up[(chip * 2) + 1].port.iotype = UPIO_MEM;
1126 up[(chip * 2) + 1].port.irq = zilog_irq;
1127 up[(chip * 2) + 1].port.uartclk = ZS_CLOCK;
1128 up[(chip * 2) + 1].port.fifosize = 1;
1129 up[(chip * 2) + 1].port.ops = &ip22zilog_pops;
1130 up[(chip * 2) + 1].port.type = PORT_IP22ZILOG;
1da177e4 1131 up[(chip * 2) + 1].port.line = (chip * 2) + 1;
c65b15cf 1132 up[(chip * 2) + 1].flags |= IP22ZILOG_FLAG_IS_CHANNEL_A;
1da177e4 1133 }
1da177e4 1134
68576cf1
TB		 1135 for (channel = 0; channel < NUM_CHANNELS; channel++) {
1136 struct uart_ip22zilog_port *up = &ip22zilog_port_table[channel];
1137 int brg;
1da177e4
LT		 1138
1139 /* Normal serial TTY. */
1140 up->parity_mask = 0xff;
1141 up->curregs[R1] = EXT_INT_ENAB | INT_ALL_Rx | TxINT_ENAB;
1142 up->curregs[R4] = PAR_EVEN | X16CLK | SB1;
1143 up->curregs[R3] = RxENAB | Rx8;
1144 up->curregs[R5] = TxENAB | Tx8;
1145 up->curregs[R9] = NV | MIE;
1146 up->curregs[R10] = NRZ;
1147 up->curregs[R11] = TCBR | RCBR;
68576cf1 1148 brg = BPS_TO_BRG(9600, ZS_CLOCK / ZS_CLOCK_DIVISOR);
1da177e4
LT		 1149 up->curregs[R12] = (brg & 0xff);
1150 up->curregs[R13] = (brg >> 8) & 0xff;
1151 up->curregs[R14] = BRENAB;
1da177e4
LT		 1152 }
1153}
1154
1155static int __init ip22zilog_ports_init(void)
1156{
1157 int ret;
1158
1159 printk(KERN_INFO "Serial: IP22 Zilog driver (%d chips).\n", NUM_IP22ZILOG);
1160
1161 ip22zilog_prepare();
1162
1163 if (request_irq(zilog_irq, ip22zilog_interrupt, 0,
1164 "IP22-Zilog", ip22zilog_irq_chain)) {
1165 panic("IP22-Zilog: Unable to register zs interrupt handler.\n");
1166 }
1167
1da177e4
LT		 1168 ret = uart_register_driver(&ip22zilog_reg);
1169 if (ret == 0) {
1170 int i;
1171
1172 for (i = 0; i < NUM_CHANNELS; i++) {
1173 struct uart_ip22zilog_port *up = &ip22zilog_port_table[i];
1174
1175 uart_add_one_port(&ip22zilog_reg, &up->port);
1176 }
1177 }
1178
1179 return ret;
1180}
1181
1182static int __init ip22zilog_init(void)
1183{
1184 /* IP22 Zilog setup is hard coded, no probing to do. */
1185 ip22zilog_alloc_tables();
1186 ip22zilog_ports_init();
1187
1188 return 0;
1189}
1190
1191static void __exit ip22zilog_exit(void)
1192{
1193 int i;
6257b3bd 1194 struct uart_ip22zilog_port *up;
1da177e4
LT		 1195
1196 for (i = 0; i < NUM_CHANNELS; i++) {
6257b3bd 1197 up = &ip22zilog_port_table[i];
1da177e4
LT		 1198
1199 uart_remove_one_port(&ip22zilog_reg, &up->port);
1200 }
1201
6257b3bd
AL		 1202 /* Free IO mem */
1203 up = &ip22zilog_port_table[0];
1204 for (i = 0; i < NUM_IP22ZILOG; i++) {
1205 if (up[(i * 2) + 0].port.mapbase) {
1206 iounmap((void*)up[(i * 2) + 0].port.mapbase);
1207 up[(i * 2) + 0].port.mapbase = 0;
1208 }
1209 if (up[(i * 2) + 1].port.mapbase) {
1210 iounmap((void*)up[(i * 2) + 1].port.mapbase);
1211 up[(i * 2) + 1].port.mapbase = 0;
1212 }
1213 }
1214
1da177e4
LT		 1215 uart_unregister_driver(&ip22zilog_reg);
1216}
1217
1218module_init(ip22zilog_init);
1219module_exit(ip22zilog_exit);
1220
1221/* David wrote it but I'm to blame for the bugs ... */
1222MODULE_AUTHOR("Ralf Baechle <ralf@linux-mips.org>");
1223MODULE_DESCRIPTION("SGI Zilog serial port driver");
1224MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)