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tty: serial: imx: correct dma cookie status
[linux-2.6-block.git] / drivers / tty / serial / imx.c
CommitLineData
e3b3d0f5 1// SPDX-License-Identifier: GPL-2.0+
1da177e4 2/*
f890cef2 3 * Driver for Motorola/Freescale IMX serial ports
1da177e4 4 *
f890cef2 5 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
1da177e4 6 *
f890cef2
UKK		 7 * Author: Sascha Hauer <sascha@saschahauer.de>
8 * Copyright (C) 2004 Pengutronix
1da177e4 9 */
1da177e4
LT		 10
11#if defined(CONFIG_SERIAL_IMX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
12#define SUPPORT_SYSRQ
13#endif
14
15#include <linux/module.h>
16#include <linux/ioport.h>
17#include <linux/init.h>
18#include <linux/console.h>
19#include <linux/sysrq.h>
d052d1be 20#include <linux/platform_device.h>
1da177e4
LT		 21#include <linux/tty.h>
22#include <linux/tty_flip.h>
23#include <linux/serial_core.h>
24#include <linux/serial.h>
38a41fdf 25#include <linux/clk.h>
b6e49138 26#include <linux/delay.h>
534fca06 27#include <linux/rational.h>
5a0e3ad6 28#include <linux/slab.h>
22698aa2
SG		 29#include <linux/of.h>
30#include <linux/of_device.h>
e32a9f8f 31#include <linux/io.h>
b4cdc8f6 32#include <linux/dma-mapping.h>
1da177e4 33
1da177e4 34#include <asm/irq.h>
82906b13 35#include <linux/platform_data/serial-imx.h>
b4cdc8f6 36#include <linux/platform_data/dma-imx.h>
1da177e4 37
58362d5b
UKK		 38#include "serial_mctrl_gpio.h"
39
ff4bfb21
SH		 40/* Register definitions */
41#define URXD0 0x0 /* Receiver Register */
42#define URTX0 0x40 /* Transmitter Register */
43#define UCR1 0x80 /* Control Register 1 */
44#define UCR2 0x84 /* Control Register 2 */
45#define UCR3 0x88 /* Control Register 3 */
46#define UCR4 0x8c /* Control Register 4 */
47#define UFCR 0x90 /* FIFO Control Register */
48#define USR1 0x94 /* Status Register 1 */
49#define USR2 0x98 /* Status Register 2 */
50#define UESC 0x9c /* Escape Character Register */
51#define UTIM 0xa0 /* Escape Timer Register */
52#define UBIR 0xa4 /* BRM Incremental Register */
53#define UBMR 0xa8 /* BRM Modulator Register */
54#define UBRC 0xac /* Baud Rate Count Register */
fe6b540a
SG		 55#define IMX21_ONEMS 0xb0 /* One Millisecond register */
56#define IMX1_UTS 0xd0 /* UART Test Register on i.mx1 */
57#define IMX21_UTS 0xb4 /* UART Test Register on all other i.mx*/
ff4bfb21
SH		 58
59/* UART Control Register Bit Fields.*/
55d8693a 60#define URXD_DUMMY_READ (1<<16)
82313e66
SK		 61#define URXD_CHARRDY (1<<15)
62#define URXD_ERR (1<<14)
63#define URXD_OVRRUN (1<<13)
64#define URXD_FRMERR (1<<12)
65#define URXD_BRK (1<<11)
66#define URXD_PRERR (1<<10)
26c47412 67#define URXD_RX_DATA (0xFF<<0)
82313e66
SK		 68#define UCR1_ADEN (1<<15) /* Auto detect interrupt */
69#define UCR1_ADBR (1<<14) /* Auto detect baud rate */
70#define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */
71#define UCR1_IDEN (1<<12) /* Idle condition interrupt */
b4cdc8f6 72#define UCR1_ICD_REG(x) (((x) & 3) << 10) /* idle condition detect */
82313e66 73#define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */
302e8dcc 74#define UCR1_RXDMAEN (1<<8) /* Recv ready DMA enable */
82313e66
SK		 75#define UCR1_IREN (1<<7) /* Infrared interface enable */
76#define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */
77#define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
78#define UCR1_SNDBRK (1<<4) /* Send break */
302e8dcc 79#define UCR1_TXDMAEN (1<<3) /* Transmitter ready DMA enable */
82313e66 80#define IMX1_UCR1_UARTCLKEN (1<<2) /* UART clock enabled, i.mx1 only */
b4cdc8f6 81#define UCR1_ATDMAEN (1<<2) /* Aging DMA Timer Enable */
82313e66
SK		 82#define UCR1_DOZE (1<<1) /* Doze */
83#define UCR1_UARTEN (1<<0) /* UART enabled */
84#define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */
85#define UCR2_IRTS (1<<14) /* Ignore RTS pin */
86#define UCR2_CTSC (1<<13) /* CTS pin control */
87#define UCR2_CTS (1<<12) /* Clear to send */
88#define UCR2_ESCEN (1<<11) /* Escape enable */
89#define UCR2_PREN (1<<8) /* Parity enable */
90#define UCR2_PROE (1<<7) /* Parity odd/even */
91#define UCR2_STPB (1<<6) /* Stop */
92#define UCR2_WS (1<<5) /* Word size */
93#define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */
94#define UCR2_ATEN (1<<3) /* Aging Timer Enable */
95#define UCR2_TXEN (1<<2) /* Transmitter enabled */
96#define UCR2_RXEN (1<<1) /* Receiver enabled */
97#define UCR2_SRST (1<<0) /* SW reset */
98#define UCR3_DTREN (1<<13) /* DTR interrupt enable */
99#define UCR3_PARERREN (1<<12) /* Parity enable */
100#define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */
101#define UCR3_DSR (1<<10) /* Data set ready */
102#define UCR3_DCD (1<<9) /* Data carrier detect */
103#define UCR3_RI (1<<8) /* Ring indicator */
b38cb7d2 104#define UCR3_ADNIMP (1<<7) /* Autobaud Detection Not Improved */
82313e66
SK		 105#define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */
106#define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */
107#define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */
27e16501 108#define UCR3_DTRDEN (1<<3) /* Data Terminal Ready Delta Enable. */
82313e66
SK		 109#define IMX21_UCR3_RXDMUXSEL (1<<2) /* RXD Muxed Input Select */
110#define UCR3_INVT (1<<1) /* Inverted Infrared transmission */
111#define UCR3_BPEN (1<<0) /* Preset registers enable */
112#define UCR4_CTSTL_SHF 10 /* CTS trigger level shift */
113#define UCR4_CTSTL_MASK 0x3F /* CTS trigger is 6 bits wide */
114#define UCR4_INVR (1<<9) /* Inverted infrared reception */
115#define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */
116#define UCR4_WKEN (1<<7) /* Wake interrupt enable */
117#define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */
b4cdc8f6 118#define UCR4_IDDMAEN (1<<6) /* DMA IDLE Condition Detected */
82313e66
SK		 119#define UCR4_IRSC (1<<5) /* IR special case */
120#define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */
121#define UCR4_BKEN (1<<2) /* Break condition interrupt enable */
122#define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */
123#define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */
124#define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */
125#define UFCR_DCEDTE (1<<6) /* DCE/DTE mode select */
126#define UFCR_RFDIV (7<<7) /* Reference freq divider mask */
127#define UFCR_RFDIV_REG(x) (((x) < 7 ? 6 - (x) : 6) << 7)
128#define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */
129#define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */
130#define USR1_RTSS (1<<14) /* RTS pin status */
131#define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */
132#define USR1_RTSD (1<<12) /* RTS delta */
133#define USR1_ESCF (1<<11) /* Escape seq interrupt flag */
134#define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */
135#define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */
86a04ba6 136#define USR1_AGTIM (1<<8) /* Ageing timer interrupt flag */
27e16501 137#define USR1_DTRD (1<<7) /* DTR Delta */
82313e66
SK		 138#define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */
139#define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */
140#define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */
141#define USR2_ADET (1<<15) /* Auto baud rate detect complete */
142#define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */
143#define USR2_DTRF (1<<13) /* DTR edge interrupt flag */
144#define USR2_IDLE (1<<12) /* Idle condition */
90ebc483
UKK		 145#define USR2_RIDELT (1<<10) /* Ring Interrupt Delta */
146#define USR2_RIIN (1<<9) /* Ring Indicator Input */
82313e66
SK		 147#define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */
148#define USR2_WAKE (1<<7) /* Wake */
90ebc483 149#define USR2_DCDIN (1<<5) /* Data Carrier Detect Input */
82313e66
SK		 150#define USR2_RTSF (1<<4) /* RTS edge interrupt flag */
151#define USR2_TXDC (1<<3) /* Transmitter complete */
152#define USR2_BRCD (1<<2) /* Break condition */
153#define USR2_ORE (1<<1) /* Overrun error */
154#define USR2_RDR (1<<0) /* Recv data ready */
155#define UTS_FRCPERR (1<<13) /* Force parity error */
156#define UTS_LOOP (1<<12) /* Loop tx and rx */
157#define UTS_TXEMPTY (1<<6) /* TxFIFO empty */
158#define UTS_RXEMPTY (1<<5) /* RxFIFO empty */
159#define UTS_TXFULL (1<<4) /* TxFIFO full */
160#define UTS_RXFULL (1<<3) /* RxFIFO full */
161#define UTS_SOFTRST (1<<0) /* Software reset */
ff4bfb21 162
1da177e4 163/* We've been assigned a range on the "Low-density serial ports" major */
82313e66
SK		 164#define SERIAL_IMX_MAJOR 207
165#define MINOR_START 16
e3d13ff4 166#define DEV_NAME "ttymxc"
1da177e4 167
1da177e4
LT		 168/*
169 * This determines how often we check the modem status signals
170 * for any change. They generally aren't connected to an IRQ
171 * so we have to poll them. We also check immediately before
172 * filling the TX fifo incase CTS has been dropped.
173 */
174#define MCTRL_TIMEOUT (250*HZ/1000)
175
176#define DRIVER_NAME "IMX-uart"
177
dbff4e9e
SH		 178#define UART_NR 8
179
f95661b2 180/* i.MX21 type uart runs on all i.mx except i.MX1 and i.MX6q */
fe6b540a
SG		 181enum imx_uart_type {
182 IMX1_UART,
183 IMX21_UART,
1c06bde6 184 IMX53_UART,
a496e628 185 IMX6Q_UART,
fe6b540a
SG		 186};
187
188/* device type dependent stuff */
189struct imx_uart_data {
190 unsigned uts_reg;
191 enum imx_uart_type devtype;
192};
193
1da177e4
LT		 194struct imx_port {
195 struct uart_port port;
196 struct timer_list timer;
197 unsigned int old_status;
26bbb3ff 198 unsigned int have_rtscts:1;
7b7e8e8e 199 unsigned int have_rtsgpio:1;
20ff2fe6 200 unsigned int dte_mode:1;
3a9465fa
SH		 201 struct clk *clk_ipg;
202 struct clk *clk_per;
7d0b066f 203 const struct imx_uart_data *devdata;
b4cdc8f6 204
58362d5b
UKK		 205 struct mctrl_gpios *gpios;
206
3a0ab62f
UKK		 207 /* shadow registers */
208 unsigned int ucr1;
209 unsigned int ucr2;
210 unsigned int ucr3;
211 unsigned int ucr4;
212 unsigned int ufcr;
213
b4cdc8f6 214 /* DMA fields */
b4cdc8f6
HS		 215 unsigned int dma_is_enabled:1;
216 unsigned int dma_is_rxing:1;
217 unsigned int dma_is_txing:1;
218 struct dma_chan *dma_chan_rx, *dma_chan_tx;
219 struct scatterlist rx_sgl, tx_sgl[2];
220 void *rx_buf;
9d297239
NH		 221 struct circ_buf rx_ring;
222 unsigned int rx_periods;
223 dma_cookie_t rx_cookie;
7cb92fd2 224 unsigned int tx_bytes;
b4cdc8f6 225 unsigned int dma_tx_nents;
90bb6bd3 226 unsigned int saved_reg[10];
c868cbb7 227 bool context_saved;
1da177e4
LT		 228};
229
0ad5a814
DB		 230struct imx_port_ucrs {
231 unsigned int ucr1;
232 unsigned int ucr2;
233 unsigned int ucr3;
234};
235
fe6b540a
SG		 236static struct imx_uart_data imx_uart_devdata[] = {
237 [IMX1_UART] = {
238 .uts_reg = IMX1_UTS,
239 .devtype = IMX1_UART,
240 },
241 [IMX21_UART] = {
242 .uts_reg = IMX21_UTS,
243 .devtype = IMX21_UART,
244 },
1c06bde6
MW		 245 [IMX53_UART] = {
246 .uts_reg = IMX21_UTS,
247 .devtype = IMX53_UART,
248 },
a496e628
HS		 249 [IMX6Q_UART] = {
250 .uts_reg = IMX21_UTS,
251 .devtype = IMX6Q_UART,
252 },
fe6b540a
SG		 253};
254
31ada047 255static const struct platform_device_id imx_uart_devtype[] = {
fe6b540a
SG		 256 {
257 .name = "imx1-uart",
258 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX1_UART],
259 }, {
260 .name = "imx21-uart",
261 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX21_UART],
1c06bde6
MW		 262 }, {
263 .name = "imx53-uart",
264 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX53_UART],
a496e628
HS		 265 }, {
266 .name = "imx6q-uart",
267 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX6Q_UART],
fe6b540a
SG		 268 }, {
269 /* sentinel */
270 }
271};
272MODULE_DEVICE_TABLE(platform, imx_uart_devtype);
273
ad3d4fdc 274static const struct of_device_id imx_uart_dt_ids[] = {
a496e628 275 { .compatible = "fsl,imx6q-uart", .data = &imx_uart_devdata[IMX6Q_UART], },
1c06bde6 276 { .compatible = "fsl,imx53-uart", .data = &imx_uart_devdata[IMX53_UART], },
22698aa2
SG		 277 { .compatible = "fsl,imx1-uart", .data = &imx_uart_devdata[IMX1_UART], },
278 { .compatible = "fsl,imx21-uart", .data = &imx_uart_devdata[IMX21_UART], },
279 { /* sentinel */ }
280};
281MODULE_DEVICE_TABLE(of, imx_uart_dt_ids);
282
27c84426
UKK		 283static void imx_uart_writel(struct imx_port *sport, u32 val, u32 offset)
284{
3a0ab62f
UKK		 285 switch (offset) {
286 case UCR1:
287 sport->ucr1 = val;
288 break;
289 case UCR2:
290 sport->ucr2 = val;
291 break;
292 case UCR3:
293 sport->ucr3 = val;
294 break;
295 case UCR4:
296 sport->ucr4 = val;
297 break;
298 case UFCR:
299 sport->ufcr = val;
300 break;
301 default:
302 break;
303 }
27c84426
UKK		 304 writel(val, sport->port.membase + offset);
305}
306
307static u32 imx_uart_readl(struct imx_port *sport, u32 offset)
308{
3a0ab62f
UKK		 309 switch (offset) {
310 case UCR1:
311 return sport->ucr1;
312 break;
313 case UCR2:
314 /*
315 * UCR2_SRST is the only bit in the cached registers that might
316 * differ from the value that was last written. As it only
728e74a4
UKK		 317 * automatically becomes one after being cleared, reread
318 * conditionally.
3a0ab62f 319 */
0aa821d8 320 if (!(sport->ucr2 & UCR2_SRST))
3a0ab62f
UKK		 321 sport->ucr2 = readl(sport->port.membase + offset);
322 return sport->ucr2;
323 break;
324 case UCR3:
325 return sport->ucr3;
326 break;
327 case UCR4:
328 return sport->ucr4;
329 break;
330 case UFCR:
331 return sport->ufcr;
332 break;
333 default:
334 return readl(sport->port.membase + offset);
335 }
27c84426
UKK		 336}
337
9d1a50a2 338static inline unsigned imx_uart_uts_reg(struct imx_port *sport)
fe6b540a
SG		 339{
340 return sport->devdata->uts_reg;
341}
342
9d1a50a2 343static inline int imx_uart_is_imx1(struct imx_port *sport)
fe6b540a
SG		 344{
345 return sport->devdata->devtype == IMX1_UART;
346}
347
9d1a50a2 348static inline int imx_uart_is_imx21(struct imx_port *sport)
fe6b540a
SG		 349{
350 return sport->devdata->devtype == IMX21_UART;
351}
352
9d1a50a2 353static inline int imx_uart_is_imx53(struct imx_port *sport)
1c06bde6
MW		 354{
355 return sport->devdata->devtype == IMX53_UART;
356}
357
9d1a50a2 358static inline int imx_uart_is_imx6q(struct imx_port *sport)
a496e628
HS		 359{
360 return sport->devdata->devtype == IMX6Q_UART;
361}
44a75411 362/*
363 * Save and restore functions for UCR1, UCR2 and UCR3 registers
364 */
93d94b37 365#if defined(CONFIG_SERIAL_IMX_CONSOLE)
9d1a50a2 366static void imx_uart_ucrs_save(struct imx_port *sport,
44a75411 367 struct imx_port_ucrs *ucr)
368{
369 /* save control registers */
27c84426
UKK		 370 ucr->ucr1 = imx_uart_readl(sport, UCR1);
371 ucr->ucr2 = imx_uart_readl(sport, UCR2);
372 ucr->ucr3 = imx_uart_readl(sport, UCR3);
44a75411 373}
374
9d1a50a2 375static void imx_uart_ucrs_restore(struct imx_port *sport,
44a75411 376 struct imx_port_ucrs *ucr)
377{
378 /* restore control registers */
27c84426
UKK		 379 imx_uart_writel(sport, ucr->ucr1, UCR1);
380 imx_uart_writel(sport, ucr->ucr2, UCR2);
381 imx_uart_writel(sport, ucr->ucr3, UCR3);
44a75411 382}
e8bfa760 383#endif
44a75411 384
9d1a50a2 385static void imx_uart_rts_active(struct imx_port *sport, u32 *ucr2)
58362d5b 386{
bc2be239 387 *ucr2 &= ~(UCR2_CTSC | UCR2_CTS);
58362d5b 388
a0983c74
IJ		 389 sport->port.mctrl |= TIOCM_RTS;
390 mctrl_gpio_set(sport->gpios, sport->port.mctrl);
58362d5b
UKK		 391}
392
9d1a50a2 393static void imx_uart_rts_inactive(struct imx_port *sport, u32 *ucr2)
58362d5b 394{
bc2be239
FE		 395 *ucr2 &= ~UCR2_CTSC;
396 *ucr2 |= UCR2_CTS;
58362d5b 397
a0983c74
IJ		 398 sport->port.mctrl &= ~TIOCM_RTS;
399 mctrl_gpio_set(sport->gpios, sport->port.mctrl);
58362d5b
UKK		 400}
401
9d1a50a2 402static void imx_uart_rts_auto(struct imx_port *sport, u32 *ucr2)
58362d5b
UKK		 403{
404 *ucr2 |= UCR2_CTSC;
405}
406
76821e22 407/* called with port.lock taken and irqs off */
9d1a50a2 408static void imx_uart_start_rx(struct uart_port *port)
76821e22
UKK		 409{
410 struct imx_port *sport = (struct imx_port *)port;
411 unsigned int ucr1, ucr2;
412
413 ucr1 = imx_uart_readl(sport, UCR1);
414 ucr2 = imx_uart_readl(sport, UCR2);
415
416 ucr2 |= UCR2_RXEN;
417
418 if (sport->dma_is_enabled) {
419 ucr1 |= UCR1_RXDMAEN | UCR1_ATDMAEN;
420 } else {
421 ucr1 |= UCR1_RRDYEN;
81ca8e82 422 ucr2 |= UCR2_ATEN;
76821e22
UKK		 423 }
424
425 /* Write UCR2 first as it includes RXEN */
426 imx_uart_writel(sport, ucr2, UCR2);
427 imx_uart_writel(sport, ucr1, UCR1);
428}
429
6aed2a88 430/* called with port.lock taken and irqs off */
9d1a50a2 431static void imx_uart_stop_tx(struct uart_port *port)
1da177e4
LT		 432{
433 struct imx_port *sport = (struct imx_port *)port;
4444dcf1 434 u32 ucr1;
ff4bfb21 435
9ce4f8f3
GKH		 436 /*
437 * We are maybe in the SMP context, so if the DMA TX thread is running
438 * on other cpu, we have to wait for it to finish.
439 */
686351f3 440 if (sport->dma_is_txing)
9ce4f8f3 441 return;
b4cdc8f6 442
4444dcf1
UKK		 443 ucr1 = imx_uart_readl(sport, UCR1);
444 imx_uart_writel(sport, ucr1 & ~UCR1_TXMPTYEN, UCR1);
17b8f2a3
UKK		 445
446 /* in rs485 mode disable transmitter if shifter is empty */
447 if (port->rs485.flags & SER_RS485_ENABLED &&
27c84426 448 imx_uart_readl(sport, USR2) & USR2_TXDC) {
4444dcf1 449 u32 ucr2 = imx_uart_readl(sport, UCR2), ucr4;
17b8f2a3 450 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND)
9d1a50a2 451 imx_uart_rts_active(sport, &ucr2);
1a613626 452 else
9d1a50a2 453 imx_uart_rts_inactive(sport, &ucr2);
4444dcf1 454 imx_uart_writel(sport, ucr2, UCR2);
17b8f2a3 455
9d1a50a2 456 imx_uart_start_rx(port);
76821e22 457
4444dcf1
UKK		 458 ucr4 = imx_uart_readl(sport, UCR4);
459 ucr4 &= ~UCR4_TCEN;
460 imx_uart_writel(sport, ucr4, UCR4);
17b8f2a3 461 }
1da177e4
LT		 462}
463
6aed2a88 464/* called with port.lock taken and irqs off */
9d1a50a2 465static void imx_uart_stop_rx(struct uart_port *port)
1da177e4
LT		 466{
467 struct imx_port *sport = (struct imx_port *)port;
4444dcf1 468 u32 ucr1, ucr2;
ff4bfb21 469
76821e22 470 ucr1 = imx_uart_readl(sport, UCR1);
4444dcf1 471 ucr2 = imx_uart_readl(sport, UCR2);
85878399 472
76821e22
UKK		 473 if (sport->dma_is_enabled) {
474 ucr1 &= ~(UCR1_RXDMAEN | UCR1_ATDMAEN);
475 } else {
476 ucr1 &= ~UCR1_RRDYEN;
81ca8e82 477 ucr2 &= ~UCR2_ATEN;
76821e22
UKK		 478 }
479 imx_uart_writel(sport, ucr1, UCR1);
480
481 ucr2 &= ~UCR2_RXEN;
482 imx_uart_writel(sport, ucr2, UCR2);
1da177e4
LT		 483}
484
6aed2a88 485/* called with port.lock taken and irqs off */
9d1a50a2 486static void imx_uart_enable_ms(struct uart_port *port)
1da177e4
LT		 487{
488 struct imx_port *sport = (struct imx_port *)port;
489
490 mod_timer(&sport->timer, jiffies);
58362d5b
UKK		 491
492 mctrl_gpio_enable_ms(sport->gpios);
1da177e4
LT		 493}
494
9d1a50a2 495static void imx_uart_dma_tx(struct imx_port *sport);
6aed2a88
UKK		 496
497/* called with port.lock taken and irqs off */
9d1a50a2 498static inline void imx_uart_transmit_buffer(struct imx_port *sport)
1da177e4 499{
ebd2c8f6 500 struct circ_buf *xmit = &sport->port.state->xmit;
1da177e4 501
5e42e9a3
PH		 502 if (sport->port.x_char) {
503 /* Send next char */
27c84426 504 imx_uart_writel(sport, sport->port.x_char, URTX0);
7e2fb5aa
JW		 505 sport->port.icount.tx++;
506 sport->port.x_char = 0;
5e42e9a3
PH		 507 return;
508 }
509
510 if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) {
9d1a50a2 511 imx_uart_stop_tx(&sport->port);
5e42e9a3
PH		 512 return;
513 }
514
91a1a909 515 if (sport->dma_is_enabled) {
4444dcf1 516 u32 ucr1;
91a1a909
JW		 517 /*
518 * We've just sent a X-char Ensure the TX DMA is enabled
519 * and the TX IRQ is disabled.
520 **/
4444dcf1
UKK		 521 ucr1 = imx_uart_readl(sport, UCR1);
522 ucr1 &= ~UCR1_TXMPTYEN;
91a1a909 523 if (sport->dma_is_txing) {
4444dcf1
UKK		 524 ucr1 |= UCR1_TXDMAEN;
525 imx_uart_writel(sport, ucr1, UCR1);
91a1a909 526 } else {
4444dcf1 527 imx_uart_writel(sport, ucr1, UCR1);
9d1a50a2 528 imx_uart_dma_tx(sport);
91a1a909 529 }
91a1a909 530
5aabd3b0 531 return;
0c549223 532 }
5aabd3b0
IJ		 533
534 while (!uart_circ_empty(xmit) &&
9d1a50a2 535 !(imx_uart_readl(sport, imx_uart_uts_reg(sport)) & UTS_TXFULL)) {
1da177e4
LT		 536 /* send xmit->buf[xmit->tail]
537 * out the port here */
27c84426 538 imx_uart_writel(sport, xmit->buf[xmit->tail], URTX0);
d3810cd4 539 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1da177e4 540 sport->port.icount.tx++;
8c0b254b 541 }
1da177e4 542
97775731
FG		 543 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
544 uart_write_wakeup(&sport->port);
545
1da177e4 546 if (uart_circ_empty(xmit))
9d1a50a2 547 imx_uart_stop_tx(&sport->port);
1da177e4
LT		 548}
549
9d1a50a2 550static void imx_uart_dma_tx_callback(void *data)
b4cdc8f6
HS		 551{
552 struct imx_port *sport = data;
553 struct scatterlist *sgl = &sport->tx_sgl[0];
554 struct circ_buf *xmit = &sport->port.state->xmit;
555 unsigned long flags;
4444dcf1 556 u32 ucr1;
b4cdc8f6 557
42f752b3 558 spin_lock_irqsave(&sport->port.lock, flags);
b4cdc8f6 559
42f752b3 560 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
b4cdc8f6 561
4444dcf1
UKK		 562 ucr1 = imx_uart_readl(sport, UCR1);
563 ucr1 &= ~UCR1_TXDMAEN;
564 imx_uart_writel(sport, ucr1, UCR1);
a2c718ce 565
b4cdc8f6 566 /* update the stat */
b4cdc8f6
HS		 567 xmit->tail = (xmit->tail + sport->tx_bytes) & (UART_XMIT_SIZE - 1);
568 sport->port.icount.tx += sport->tx_bytes;
b4cdc8f6
HS		 569
570 dev_dbg(sport->port.dev, "we finish the TX DMA.\n");
571
42f752b3
DB		 572 sport->dma_is_txing = 0;
573
d64b8607
JW		 574 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
575 uart_write_wakeup(&sport->port);
9ce4f8f3 576
0bbc9b81 577 if (!uart_circ_empty(xmit) && !uart_tx_stopped(&sport->port))
9d1a50a2 578 imx_uart_dma_tx(sport);
18665414
UKK		 579 else if (sport->port.rs485.flags & SER_RS485_ENABLED) {
580 u32 ucr4 = imx_uart_readl(sport, UCR4);
581 ucr4 |= UCR4_TCEN;
582 imx_uart_writel(sport, ucr4, UCR4);
583 }
64432a85 584
0bbc9b81 585 spin_unlock_irqrestore(&sport->port.lock, flags);
b4cdc8f6
HS		 586}
587
6aed2a88 588/* called with port.lock taken and irqs off */
9d1a50a2 589static void imx_uart_dma_tx(struct imx_port *sport)
b4cdc8f6 590{
b4cdc8f6
HS		 591 struct circ_buf *xmit = &sport->port.state->xmit;
592 struct scatterlist *sgl = sport->tx_sgl;
593 struct dma_async_tx_descriptor *desc;
594 struct dma_chan *chan = sport->dma_chan_tx;
595 struct device *dev = sport->port.dev;
18665414 596 u32 ucr1, ucr4;
b4cdc8f6
HS		 597 int ret;
598
42f752b3 599 if (sport->dma_is_txing)
b4cdc8f6
HS		 600 return;
601
18665414
UKK		 602 ucr4 = imx_uart_readl(sport, UCR4);
603 ucr4 &= ~UCR4_TCEN;
604 imx_uart_writel(sport, ucr4, UCR4);
605
b4cdc8f6 606 sport->tx_bytes = uart_circ_chars_pending(xmit);
b4cdc8f6 607
7942f857
DB		 608 if (xmit->tail < xmit->head) {
609 sport->dma_tx_nents = 1;
610 sg_init_one(sgl, xmit->buf + xmit->tail, sport->tx_bytes);
611 } else {
b4cdc8f6
HS		 612 sport->dma_tx_nents = 2;
613 sg_init_table(sgl, 2);
614 sg_set_buf(sgl, xmit->buf + xmit->tail,
615 UART_XMIT_SIZE - xmit->tail);
616 sg_set_buf(sgl + 1, xmit->buf, xmit->head);
b4cdc8f6 617 }
b4cdc8f6
HS		 618
619 ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
620 if (ret == 0) {
621 dev_err(dev, "DMA mapping error for TX.\n");
622 return;
623 }
624 desc = dmaengine_prep_slave_sg(chan, sgl, sport->dma_tx_nents,
625 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
626 if (!desc) {
24649821
DB		 627 dma_unmap_sg(dev, sgl, sport->dma_tx_nents,
628 DMA_TO_DEVICE);
b4cdc8f6
HS		 629 dev_err(dev, "We cannot prepare for the TX slave dma!\n");
630 return;
631 }
9d1a50a2 632 desc->callback = imx_uart_dma_tx_callback;
b4cdc8f6
HS		 633 desc->callback_param = sport;
634
635 dev_dbg(dev, "TX: prepare to send %lu bytes by DMA.\n",
636 uart_circ_chars_pending(xmit));
a2c718ce 637
4444dcf1
UKK		 638 ucr1 = imx_uart_readl(sport, UCR1);
639 ucr1 |= UCR1_TXDMAEN;
640 imx_uart_writel(sport, ucr1, UCR1);
a2c718ce 641
b4cdc8f6
HS		 642 /* fire it */
643 sport->dma_is_txing = 1;
644 dmaengine_submit(desc);
645 dma_async_issue_pending(chan);
646 return;
647}
648
6aed2a88 649/* called with port.lock taken and irqs off */
9d1a50a2 650static void imx_uart_start_tx(struct uart_port *port)
1da177e4
LT		 651{
652 struct imx_port *sport = (struct imx_port *)port;
4444dcf1 653 u32 ucr1;
1da177e4 654
48669b69
UKK		 655 if (!sport->port.x_char && uart_circ_empty(&port->state->xmit))
656 return;
657
17b8f2a3 658 if (port->rs485.flags & SER_RS485_ENABLED) {
18665414 659 u32 ucr2;
4444dcf1
UKK		 660
661 ucr2 = imx_uart_readl(sport, UCR2);
17b8f2a3 662 if (port->rs485.flags & SER_RS485_RTS_ON_SEND)
9d1a50a2 663 imx_uart_rts_active(sport, &ucr2);
1a613626 664 else
9d1a50a2 665 imx_uart_rts_inactive(sport, &ucr2);
4444dcf1 666 imx_uart_writel(sport, ucr2, UCR2);
17b8f2a3 667
76821e22 668 if (!(port->rs485.flags & SER_RS485_RX_DURING_TX))
9d1a50a2 669 imx_uart_stop_rx(port);
76821e22 670
18665414
UKK		 671 /*
672 * Enable transmitter and shifter empty irq only if DMA is off.
673 * In the DMA case this is done in the tx-callback.
674 */
675 if (!sport->dma_is_enabled) {
676 u32 ucr4 = imx_uart_readl(sport, UCR4);
677 ucr4 |= UCR4_TCEN;
678 imx_uart_writel(sport, ucr4, UCR4);
679 }
17b8f2a3
UKK		 680 }
681
b4cdc8f6 682 if (!sport->dma_is_enabled) {
4444dcf1
UKK		 683 ucr1 = imx_uart_readl(sport, UCR1);
684 imx_uart_writel(sport, ucr1 | UCR1_TXMPTYEN, UCR1);
b4cdc8f6 685 }
1da177e4 686
b4cdc8f6 687 if (sport->dma_is_enabled) {
91a1a909
JW		 688 if (sport->port.x_char) {
689 /* We have X-char to send, so enable TX IRQ and
690 * disable TX DMA to let TX interrupt to send X-char */
4444dcf1
UKK		 691 ucr1 = imx_uart_readl(sport, UCR1);
692 ucr1 &= ~UCR1_TXDMAEN;
693 ucr1 |= UCR1_TXMPTYEN;
694 imx_uart_writel(sport, ucr1, UCR1);
91a1a909
JW		 695 return;
696 }
697
5e42e9a3
PH		 698 if (!uart_circ_empty(&port->state->xmit) &&
699 !uart_tx_stopped(port))
9d1a50a2 700 imx_uart_dma_tx(sport);
b4cdc8f6
HS		 701 return;
702 }
1da177e4
LT		 703}
704
9d1a50a2 705static irqreturn_t imx_uart_rtsint(int irq, void *dev_id)
ceca629e 706{
15aafa2f 707 struct imx_port *sport = dev_id;
4444dcf1 708 u32 usr1;
ceca629e
SH		 709 unsigned long flags;
710
711 spin_lock_irqsave(&sport->port.lock, flags);
712
27c84426 713 imx_uart_writel(sport, USR1_RTSD, USR1);
4444dcf1
UKK		 714 usr1 = imx_uart_readl(sport, USR1) & USR1_RTSS;
715 uart_handle_cts_change(&sport->port, !!usr1);
bdc04e31 716 wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
ceca629e
SH		 717
718 spin_unlock_irqrestore(&sport->port.lock, flags);
719 return IRQ_HANDLED;
720}
721
9d1a50a2 722static irqreturn_t imx_uart_txint(int irq, void *dev_id)
1da177e4 723{
15aafa2f 724 struct imx_port *sport = dev_id;
1da177e4
LT		 725 unsigned long flags;
726
82313e66 727 spin_lock_irqsave(&sport->port.lock, flags);
9d1a50a2 728 imx_uart_transmit_buffer(sport);
82313e66 729 spin_unlock_irqrestore(&sport->port.lock, flags);
1da177e4
LT		 730 return IRQ_HANDLED;
731}
732
9d1a50a2 733static irqreturn_t imx_uart_rxint(int irq, void *dev_id)
1da177e4
LT		 734{
735 struct imx_port *sport = dev_id;
82313e66 736 unsigned int rx, flg, ignored = 0;
92a19f9c 737 struct tty_port *port = &sport->port.state->port;
4444dcf1 738 unsigned long flags;
1da177e4 739
82313e66 740 spin_lock_irqsave(&sport->port.lock, flags);
1da177e4 741
27c84426 742 while (imx_uart_readl(sport, USR2) & USR2_RDR) {
4444dcf1
UKK		 743 u32 usr2;
744
1da177e4
LT		 745 flg = TTY_NORMAL;
746 sport->port.icount.rx++;
747
27c84426 748 rx = imx_uart_readl(sport, URXD0);
0d3c3938 749
4444dcf1
UKK		 750 usr2 = imx_uart_readl(sport, USR2);
751 if (usr2 & USR2_BRCD) {
27c84426 752 imx_uart_writel(sport, USR2_BRCD, USR2);
864eeed0
SH		 753 if (uart_handle_break(&sport->port))
754 continue;
1da177e4
LT		 755 }
756
d3810cd4 757 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx))
864eeed0
SH		 758 continue;
759
019dc9ea
HW		 760 if (unlikely(rx & URXD_ERR)) {
761 if (rx & URXD_BRK)
762 sport->port.icount.brk++;
763 else if (rx & URXD_PRERR)
864eeed0
SH		 764 sport->port.icount.parity++;
765 else if (rx & URXD_FRMERR)
766 sport->port.icount.frame++;
767 if (rx & URXD_OVRRUN)
768 sport->port.icount.overrun++;
769
770 if (rx & sport->port.ignore_status_mask) {
771 if (++ignored > 100)
772 goto out;
773 continue;
774 }
775
8d267fd9 776 rx &= (sport->port.read_status_mask | 0xFF);
864eeed0 777
019dc9ea
HW		 778 if (rx & URXD_BRK)
779 flg = TTY_BREAK;
780 else if (rx & URXD_PRERR)
864eeed0
SH		 781 flg = TTY_PARITY;
782 else if (rx & URXD_FRMERR)
783 flg = TTY_FRAME;
784 if (rx & URXD_OVRRUN)
785 flg = TTY_OVERRUN;
1da177e4 786
864eeed0
SH		 787#ifdef SUPPORT_SYSRQ
788 sport->port.sysrq = 0;
789#endif
790 }
1da177e4 791
55d8693a
JW		 792 if (sport->port.ignore_status_mask & URXD_DUMMY_READ)
793 goto out;
794
9b289932
MS		 795 if (tty_insert_flip_char(port, rx, flg) == 0)
796 sport->port.icount.buf_overrun++;
864eeed0 797 }
1da177e4
LT		 798
799out:
82313e66 800 spin_unlock_irqrestore(&sport->port.lock, flags);
2e124b4a 801 tty_flip_buffer_push(port);
1da177e4 802 return IRQ_HANDLED;
1da177e4
LT		 803}
804
9d1a50a2 805static void imx_uart_clear_rx_errors(struct imx_port *sport);
b4cdc8f6 806
66f95884
UKK		 807/*
808 * We have a modem side uart, so the meanings of RTS and CTS are inverted.
809 */
9d1a50a2 810static unsigned int imx_uart_get_hwmctrl(struct imx_port *sport)
66f95884
UKK		 811{
812 unsigned int tmp = TIOCM_DSR;
27c84426
UKK		 813 unsigned usr1 = imx_uart_readl(sport, USR1);
814 unsigned usr2 = imx_uart_readl(sport, USR2);
66f95884
UKK		 815
816 if (usr1 & USR1_RTSS)
817 tmp |= TIOCM_CTS;
818
819 /* in DCE mode DCDIN is always 0 */
4b75f800 820 if (!(usr2 & USR2_DCDIN))
66f95884
UKK		 821 tmp |= TIOCM_CAR;
822
823 if (sport->dte_mode)
27c84426 824 if (!(imx_uart_readl(sport, USR2) & USR2_RIIN))
66f95884
UKK		 825 tmp |= TIOCM_RI;
826
827 return tmp;
828}
829
830/*
831 * Handle any change of modem status signal since we were last called.
832 */
9d1a50a2 833static void imx_uart_mctrl_check(struct imx_port *sport)
66f95884
UKK		 834{
835 unsigned int status, changed;
836
9d1a50a2 837 status = imx_uart_get_hwmctrl(sport);
66f95884
UKK		 838 changed = status ^ sport->old_status;
839
840 if (changed == 0)
841 return;
842
843 sport->old_status = status;
844
845 if (changed & TIOCM_RI && status & TIOCM_RI)
846 sport->port.icount.rng++;
847 if (changed & TIOCM_DSR)
848 sport->port.icount.dsr++;
849 if (changed & TIOCM_CAR)
850 uart_handle_dcd_change(&sport->port, status & TIOCM_CAR);
851 if (changed & TIOCM_CTS)
852 uart_handle_cts_change(&sport->port, status & TIOCM_CTS);
853
854 wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
855}
856
9d1a50a2 857static irqreturn_t imx_uart_int(int irq, void *dev_id)
e3d13ff4
SH		 858{
859 struct imx_port *sport = dev_id;
43776896 860 unsigned int usr1, usr2, ucr1, ucr2, ucr3, ucr4;
4d845a62 861 irqreturn_t ret = IRQ_NONE;
e3d13ff4 862
27c84426
UKK		 863 usr1 = imx_uart_readl(sport, USR1);
864 usr2 = imx_uart_readl(sport, USR2);
865 ucr1 = imx_uart_readl(sport, UCR1);
866 ucr2 = imx_uart_readl(sport, UCR2);
867 ucr3 = imx_uart_readl(sport, UCR3);
868 ucr4 = imx_uart_readl(sport, UCR4);
e3d13ff4 869
43776896
UKK		 870 /*
871 * Even if a condition is true that can trigger an irq only handle it if
872 * the respective irq source is enabled. This prevents some undesired
873 * actions, for example if a character that sits in the RX FIFO and that
874 * should be fetched via DMA is tried to be fetched using PIO. Or the
875 * receiver is currently off and so reading from URXD0 results in an
876 * exception. So just mask the (raw) status bits for disabled irqs.
877 */
878 if ((ucr1 & UCR1_RRDYEN) == 0)
879 usr1 &= ~USR1_RRDY;
880 if ((ucr2 & UCR2_ATEN) == 0)
881 usr1 &= ~USR1_AGTIM;
882 if ((ucr1 & UCR1_TXMPTYEN) == 0)
883 usr1 &= ~USR1_TRDY;
884 if ((ucr4 & UCR4_TCEN) == 0)
885 usr2 &= ~USR2_TXDC;
886 if ((ucr3 & UCR3_DTRDEN) == 0)
887 usr1 &= ~USR1_DTRD;
888 if ((ucr1 & UCR1_RTSDEN) == 0)
889 usr1 &= ~USR1_RTSD;
890 if ((ucr3 & UCR3_AWAKEN) == 0)
891 usr1 &= ~USR1_AWAKE;
892 if ((ucr4 & UCR4_OREN) == 0)
893 usr2 &= ~USR2_ORE;
894
895 if (usr1 & (USR1_RRDY | USR1_AGTIM)) {
9d1a50a2 896 imx_uart_rxint(irq, dev_id);
4d845a62 897 ret = IRQ_HANDLED;
b4cdc8f6 898 }
e3d13ff4 899
43776896 900 if ((usr1 & USR1_TRDY) || (usr2 & USR2_TXDC)) {
9d1a50a2 901 imx_uart_txint(irq, dev_id);
4d845a62
UKK		 902 ret = IRQ_HANDLED;
903 }
e3d13ff4 904
0399fd61 905 if (usr1 & USR1_DTRD) {
27e16501
UKK		 906 unsigned long flags;
907
27c84426 908 imx_uart_writel(sport, USR1_DTRD, USR1);
27e16501
UKK		 909
910 spin_lock_irqsave(&sport->port.lock, flags);
9d1a50a2 911 imx_uart_mctrl_check(sport);
27e16501
UKK		 912 spin_unlock_irqrestore(&sport->port.lock, flags);
913
914 ret = IRQ_HANDLED;
915 }
916
0399fd61 917 if (usr1 & USR1_RTSD) {
9d1a50a2 918 imx_uart_rtsint(irq, dev_id);
4d845a62
UKK		 919 ret = IRQ_HANDLED;
920 }
e3d13ff4 921
0399fd61 922 if (usr1 & USR1_AWAKE) {
27c84426 923 imx_uart_writel(sport, USR1_AWAKE, USR1);
4d845a62
UKK		 924 ret = IRQ_HANDLED;
925 }
db1a9b55 926
0399fd61 927 if (usr2 & USR2_ORE) {
f1f836e4 928 sport->port.icount.overrun++;
27c84426 929 imx_uart_writel(sport, USR2_ORE, USR2);
4d845a62 930 ret = IRQ_HANDLED;
f1f836e4
AS		 931 }
932
4d845a62 933 return ret;
e3d13ff4
SH		 934}
935
1da177e4
LT		 936/*
937 * Return TIOCSER_TEMT when transmitter is not busy.
938 */
9d1a50a2 939static unsigned int imx_uart_tx_empty(struct uart_port *port)
1da177e4
LT		 940{
941 struct imx_port *sport = (struct imx_port *)port;
1ce43e58 942 unsigned int ret;
1da177e4 943
27c84426 944 ret = (imx_uart_readl(sport, USR2) & USR2_TXDC) ? TIOCSER_TEMT : 0;
1da177e4 945
1ce43e58 946 /* If the TX DMA is working, return 0. */
686351f3 947 if (sport->dma_is_txing)
1ce43e58
HS		 948 ret = 0;
949
950 return ret;
1da177e4
LT		 951}
952
6aed2a88 953/* called with port.lock taken and irqs off */
9d1a50a2 954static unsigned int imx_uart_get_mctrl(struct uart_port *port)
58362d5b
UKK		 955{
956 struct imx_port *sport = (struct imx_port *)port;
9d1a50a2 957 unsigned int ret = imx_uart_get_hwmctrl(sport);
58362d5b
UKK		 958
959 mctrl_gpio_get(sport->gpios, &ret);
960
961 return ret;
962}
963
6aed2a88 964/* called with port.lock taken and irqs off */
9d1a50a2 965static void imx_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
1da177e4 966{
d3810cd4 967 struct imx_port *sport = (struct imx_port *)port;
4444dcf1 968 u32 ucr3, uts;
ff4bfb21 969
17b8f2a3 970 if (!(port->rs485.flags & SER_RS485_ENABLED)) {
4444dcf1
UKK		 971 u32 ucr2;
972
973 ucr2 = imx_uart_readl(sport, UCR2);
974 ucr2 &= ~(UCR2_CTS | UCR2_CTSC);
17b8f2a3 975 if (mctrl & TIOCM_RTS)
4444dcf1
UKK		 976 ucr2 |= UCR2_CTS | UCR2_CTSC;
977 imx_uart_writel(sport, ucr2, UCR2);
17b8f2a3 978 }
6b471a98 979
4444dcf1 980 ucr3 = imx_uart_readl(sport, UCR3) & ~UCR3_DSR;
90ebc483 981 if (!(mctrl & TIOCM_DTR))
4444dcf1
UKK		 982 ucr3 |= UCR3_DSR;
983 imx_uart_writel(sport, ucr3, UCR3);
90ebc483 984
9d1a50a2 985 uts = imx_uart_readl(sport, imx_uart_uts_reg(sport)) & ~UTS_LOOP;
6b471a98 986 if (mctrl & TIOCM_LOOP)
4444dcf1 987 uts |= UTS_LOOP;
9d1a50a2 988 imx_uart_writel(sport, uts, imx_uart_uts_reg(sport));
58362d5b
UKK		 989
990 mctrl_gpio_set(sport->gpios, mctrl);
1da177e4
LT		 991}
992
993/*
994 * Interrupts always disabled.
995 */
9d1a50a2 996static void imx_uart_break_ctl(struct uart_port *port, int break_state)
1da177e4
LT		 997{
998 struct imx_port *sport = (struct imx_port *)port;
4444dcf1
UKK		 999 unsigned long flags;
1000 u32 ucr1;
1da177e4
LT		 1001
1002 spin_lock_irqsave(&sport->port.lock, flags);
1003
4444dcf1 1004 ucr1 = imx_uart_readl(sport, UCR1) & ~UCR1_SNDBRK;
ff4bfb21 1005
82313e66 1006 if (break_state != 0)
4444dcf1 1007 ucr1 |= UCR1_SNDBRK;
ff4bfb21 1008
4444dcf1 1009 imx_uart_writel(sport, ucr1, UCR1);
1da177e4
LT		 1010
1011 spin_unlock_irqrestore(&sport->port.lock, flags);
1012}
1013
cc568849
UKK		 1014/*
1015 * This is our per-port timeout handler, for checking the
1016 * modem status signals.
1017 */
9d1a50a2 1018static void imx_uart_timeout(struct timer_list *t)
cc568849 1019{
e99e88a9 1020 struct imx_port *sport = from_timer(sport, t, timer);
cc568849
UKK		 1021 unsigned long flags;
1022
1023 if (sport->port.state) {
1024 spin_lock_irqsave(&sport->port.lock, flags);
9d1a50a2 1025 imx_uart_mctrl_check(sport);
cc568849
UKK		 1026 spin_unlock_irqrestore(&sport->port.lock, flags);
1027
1028 mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT);
1029 }
1030}
1031
351ea50d
GKH		 1032#define RX_BUF_SIZE (PAGE_SIZE)
1033
b4cdc8f6 1034/*
905c0dec 1035 * There are two kinds of RX DMA interrupts(such as in the MX6Q):
b4cdc8f6 1036 * [1] the RX DMA buffer is full.
905c0dec 1037 * [2] the aging timer expires
b4cdc8f6 1038 *
905c0dec
LS		 1039 * Condition [2] is triggered when a character has been sitting in the FIFO
1040 * for at least 8 byte durations.
b4cdc8f6 1041 */
9d1a50a2 1042static void imx_uart_dma_rx_callback(void *data)
b4cdc8f6
HS		 1043{
1044 struct imx_port *sport = data;
1045 struct dma_chan *chan = sport->dma_chan_rx;
1046 struct scatterlist *sgl = &sport->rx_sgl;
7cb92fd2 1047 struct tty_port *port = &sport->port.state->port;
b4cdc8f6 1048 struct dma_tx_state state;
9d297239 1049 struct circ_buf *rx_ring = &sport->rx_ring;
b4cdc8f6 1050 enum dma_status status;
9d297239
NH		 1051 unsigned int w_bytes = 0;
1052 unsigned int r_bytes;
1053 unsigned int bd_size;
b4cdc8f6 1054
fb7f1bf8 1055 status = dmaengine_tx_status(chan, sport->rx_cookie, &state);
392bceed 1056
9d297239 1057 if (status == DMA_ERROR) {
9d1a50a2 1058 imx_uart_clear_rx_errors(sport);
9d297239
NH		 1059 return;
1060 }
1061
1062 if (!(sport->port.ignore_status_mask & URXD_DUMMY_READ)) {
b4cdc8f6 1063
9d297239
NH		 1064 /*
1065 * The state-residue variable represents the empty space
1066 * relative to the entire buffer. Taking this in consideration
1067 * the head is always calculated base on the buffer total
1068 * length - DMA transaction residue. The UART script from the
1069 * SDMA firmware will jump to the next buffer descriptor,
1070 * once a DMA transaction if finalized (IMX53 RM - A.4.1.2.4).
1071 * Taking this in consideration the tail is always at the
1072 * beginning of the buffer descriptor that contains the head.
1073 */
9b289932 1074
9d297239
NH		 1075 /* Calculate the head */
1076 rx_ring->head = sg_dma_len(sgl) - state.residue;
1077
1078 /* Calculate the tail. */
1079 bd_size = sg_dma_len(sgl) / sport->rx_periods;
1080 rx_ring->tail = ((rx_ring->head-1) / bd_size) * bd_size;
1081
1082 if (rx_ring->head <= sg_dma_len(sgl) &&
1083 rx_ring->head > rx_ring->tail) {
1084
1085 /* Move data from tail to head */
1086 r_bytes = rx_ring->head - rx_ring->tail;
1087
1088 /* CPU claims ownership of RX DMA buffer */
1089 dma_sync_sg_for_cpu(sport->port.dev, sgl, 1,
1090 DMA_FROM_DEVICE);
1091
1092 w_bytes = tty_insert_flip_string(port,
1093 sport->rx_buf + rx_ring->tail, r_bytes);
1094
1095 /* UART retrieves ownership of RX DMA buffer */
1096 dma_sync_sg_for_device(sport->port.dev, sgl, 1,
1097 DMA_FROM_DEVICE);
1098
1099 if (w_bytes != r_bytes)
9b289932 1100 sport->port.icount.buf_overrun++;
9d297239
NH		 1101
1102 sport->port.icount.rx += w_bytes;
1103 } else {
1104 WARN_ON(rx_ring->head > sg_dma_len(sgl));
1105 WARN_ON(rx_ring->head <= rx_ring->tail);
9b289932 1106 }
976b39cd 1107 }
7cb92fd2 1108
9d297239
NH		 1109 if (w_bytes) {
1110 tty_flip_buffer_push(port);
1111 dev_dbg(sport->port.dev, "We get %d bytes.\n", w_bytes);
1112 }
b4cdc8f6
HS		 1113}
1114
351ea50d
GKH		 1115/* RX DMA buffer periods */
1116#define RX_DMA_PERIODS 4
1117
9d1a50a2 1118static int imx_uart_start_rx_dma(struct imx_port *sport)
b4cdc8f6
HS		 1119{
1120 struct scatterlist *sgl = &sport->rx_sgl;
1121 struct dma_chan *chan = sport->dma_chan_rx;
1122 struct device *dev = sport->port.dev;
1123 struct dma_async_tx_descriptor *desc;
1124 int ret;
1125
9d297239
NH		 1126 sport->rx_ring.head = 0;
1127 sport->rx_ring.tail = 0;
351ea50d 1128 sport->rx_periods = RX_DMA_PERIODS;
9d297239 1129
351ea50d 1130 sg_init_one(sgl, sport->rx_buf, RX_BUF_SIZE);
b4cdc8f6
HS		 1131 ret = dma_map_sg(dev, sgl, 1, DMA_FROM_DEVICE);
1132 if (ret == 0) {
1133 dev_err(dev, "DMA mapping error for RX.\n");
1134 return -EINVAL;
1135 }
9d297239
NH		 1136
1137 desc = dmaengine_prep_dma_cyclic(chan, sg_dma_address(sgl),
1138 sg_dma_len(sgl), sg_dma_len(sgl) / sport->rx_periods,
1139 DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT);
1140
b4cdc8f6 1141 if (!desc) {
24649821 1142 dma_unmap_sg(dev, sgl, 1, DMA_FROM_DEVICE);
b4cdc8f6
HS		 1143 dev_err(dev, "We cannot prepare for the RX slave dma!\n");
1144 return -EINVAL;
1145 }
9d1a50a2 1146 desc->callback = imx_uart_dma_rx_callback;
b4cdc8f6
HS		 1147 desc->callback_param = sport;
1148
1149 dev_dbg(dev, "RX: prepare for the DMA.\n");
4139fd76 1150 sport->dma_is_rxing = 1;
9d297239 1151 sport->rx_cookie = dmaengine_submit(desc);
b4cdc8f6
HS		 1152 dma_async_issue_pending(chan);
1153 return 0;
1154}
41d98b5d 1155
9d1a50a2 1156static void imx_uart_clear_rx_errors(struct imx_port *sport)
41d98b5d 1157{
45ca673e 1158 struct tty_port *port = &sport->port.state->port;
4444dcf1 1159 u32 usr1, usr2;
41d98b5d 1160
4444dcf1
UKK		 1161 usr1 = imx_uart_readl(sport, USR1);
1162 usr2 = imx_uart_readl(sport, USR2);
41d98b5d 1163
4444dcf1 1164 if (usr2 & USR2_BRCD) {
41d98b5d 1165 sport->port.icount.brk++;
27c84426 1166 imx_uart_writel(sport, USR2_BRCD, USR2);
45ca673e
TK		 1167 uart_handle_break(&sport->port);
1168 if (tty_insert_flip_char(port, 0, TTY_BREAK) == 0)
1169 sport->port.icount.buf_overrun++;
1170 tty_flip_buffer_push(port);
1171 } else {
1172 dev_err(sport->port.dev, "DMA transaction error.\n");
4444dcf1 1173 if (usr1 & USR1_FRAMERR) {
45ca673e 1174 sport->port.icount.frame++;
27c84426 1175 imx_uart_writel(sport, USR1_FRAMERR, USR1);
4444dcf1 1176 } else if (usr1 & USR1_PARITYERR) {
45ca673e 1177 sport->port.icount.parity++;
27c84426 1178 imx_uart_writel(sport, USR1_PARITYERR, USR1);
45ca673e 1179 }
41d98b5d
NH		 1180 }
1181
4444dcf1 1182 if (usr2 & USR2_ORE) {
41d98b5d 1183 sport->port.icount.overrun++;
27c84426 1184 imx_uart_writel(sport, USR2_ORE, USR2);
41d98b5d
NH		 1185 }
1186
1187}
b4cdc8f6 1188
cc32382d
LS		 1189#define TXTL_DEFAULT 2 /* reset default */
1190#define RXTL_DEFAULT 1 /* reset default */
184bd70b
LS		 1191#define TXTL_DMA 8 /* DMA burst setting */
1192#define RXTL_DMA 9 /* DMA burst setting */
cc32382d 1193
9d1a50a2
UKK		 1194static void imx_uart_setup_ufcr(struct imx_port *sport,
1195 unsigned char txwl, unsigned char rxwl)
cc32382d
LS		 1196{
1197 unsigned int val;
1198
1199 /* set receiver / transmitter trigger level */
27c84426 1200 val = imx_uart_readl(sport, UFCR) & (UFCR_RFDIV | UFCR_DCEDTE);
cc32382d 1201 val |= txwl << UFCR_TXTL_SHF | rxwl;
27c84426 1202 imx_uart_writel(sport, val, UFCR);
cc32382d
LS		 1203}
1204
b4cdc8f6
HS		 1205static void imx_uart_dma_exit(struct imx_port *sport)
1206{
1207 if (sport->dma_chan_rx) {
e5e89602 1208 dmaengine_terminate_sync(sport->dma_chan_rx);
b4cdc8f6
HS		 1209 dma_release_channel(sport->dma_chan_rx);
1210 sport->dma_chan_rx = NULL;
9d297239 1211 sport->rx_cookie = -EINVAL;
b4cdc8f6
HS		 1212 kfree(sport->rx_buf);
1213 sport->rx_buf = NULL;
1214 }
1215
1216 if (sport->dma_chan_tx) {
e5e89602 1217 dmaengine_terminate_sync(sport->dma_chan_tx);
b4cdc8f6
HS		 1218 dma_release_channel(sport->dma_chan_tx);
1219 sport->dma_chan_tx = NULL;
1220 }
b4cdc8f6
HS		 1221}
1222
1223static int imx_uart_dma_init(struct imx_port *sport)
1224{
b09c74ae 1225 struct dma_slave_config slave_config = {};
b4cdc8f6
HS		 1226 struct device *dev = sport->port.dev;
1227 int ret;
1228
1229 /* Prepare for RX : */
1230 sport->dma_chan_rx = dma_request_slave_channel(dev, "rx");
1231 if (!sport->dma_chan_rx) {
1232 dev_dbg(dev, "cannot get the DMA channel.\n");
1233 ret = -EINVAL;
1234 goto err;
1235 }
1236
1237 slave_config.direction = DMA_DEV_TO_MEM;
1238 slave_config.src_addr = sport->port.mapbase + URXD0;
1239 slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
184bd70b
LS		 1240 /* one byte less than the watermark level to enable the aging timer */
1241 slave_config.src_maxburst = RXTL_DMA - 1;
b4cdc8f6
HS		 1242 ret = dmaengine_slave_config(sport->dma_chan_rx, &slave_config);
1243 if (ret) {
1244 dev_err(dev, "error in RX dma configuration.\n");
1245 goto err;
1246 }
1247
f654b23c 1248 sport->rx_buf = kzalloc(RX_BUF_SIZE, GFP_KERNEL);
b4cdc8f6 1249 if (!sport->rx_buf) {
b4cdc8f6
HS		 1250 ret = -ENOMEM;
1251 goto err;
1252 }
9d297239 1253 sport->rx_ring.buf = sport->rx_buf;
b4cdc8f6
HS		 1254
1255 /* Prepare for TX : */
1256 sport->dma_chan_tx = dma_request_slave_channel(dev, "tx");
1257 if (!sport->dma_chan_tx) {
1258 dev_err(dev, "cannot get the TX DMA channel!\n");
1259 ret = -EINVAL;
1260 goto err;
1261 }
1262
1263 slave_config.direction = DMA_MEM_TO_DEV;
1264 slave_config.dst_addr = sport->port.mapbase + URTX0;
1265 slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
184bd70b 1266 slave_config.dst_maxburst = TXTL_DMA;
b4cdc8f6
HS		 1267 ret = dmaengine_slave_config(sport->dma_chan_tx, &slave_config);
1268 if (ret) {
1269 dev_err(dev, "error in TX dma configuration.");
1270 goto err;
1271 }
1272
b4cdc8f6
HS		 1273 return 0;
1274err:
1275 imx_uart_dma_exit(sport);
1276 return ret;
1277}
1278
9d1a50a2 1279static void imx_uart_enable_dma(struct imx_port *sport)
b4cdc8f6 1280{
4444dcf1 1281 u32 ucr1;
b4cdc8f6 1282
9d1a50a2 1283 imx_uart_setup_ufcr(sport, TXTL_DMA, RXTL_DMA);
02b0abd3 1284
b4cdc8f6 1285 /* set UCR1 */
4444dcf1
UKK		 1286 ucr1 = imx_uart_readl(sport, UCR1);
1287 ucr1 |= UCR1_RXDMAEN | UCR1_TXDMAEN | UCR1_ATDMAEN;
1288 imx_uart_writel(sport, ucr1, UCR1);
b4cdc8f6 1289
b4cdc8f6
HS		 1290 sport->dma_is_enabled = 1;
1291}
1292
9d1a50a2 1293static void imx_uart_disable_dma(struct imx_port *sport)
b4cdc8f6 1294{
676a31d8 1295 u32 ucr1;
b4cdc8f6
HS		 1296
1297 /* clear UCR1 */
4444dcf1
UKK		 1298 ucr1 = imx_uart_readl(sport, UCR1);
1299 ucr1 &= ~(UCR1_RXDMAEN | UCR1_TXDMAEN | UCR1_ATDMAEN);
1300 imx_uart_writel(sport, ucr1, UCR1);
b4cdc8f6 1301
9d1a50a2 1302 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
184bd70b 1303
b4cdc8f6 1304 sport->dma_is_enabled = 0;
b4cdc8f6
HS		 1305}
1306
1c5250d6
VL		 1307/* half the RX buffer size */
1308#define CTSTL 16
1309
9d1a50a2 1310static int imx_uart_startup(struct uart_port *port)
1da177e4
LT		 1311{
1312 struct imx_port *sport = (struct imx_port *)port;
458e2c82 1313 int retval, i;
4444dcf1 1314 unsigned long flags;
4238c00b 1315 int dma_is_inited = 0;
4444dcf1 1316 u32 ucr1, ucr2, ucr4;
1da177e4 1317
1cf93e0d
HS		 1318 retval = clk_prepare_enable(sport->clk_per);
1319 if (retval)
cb0f0a5f 1320 return retval;
1cf93e0d
HS		 1321 retval = clk_prepare_enable(sport->clk_ipg);
1322 if (retval) {
1323 clk_disable_unprepare(sport->clk_per);
cb0f0a5f 1324 return retval;
0c375501 1325 }
28eb4274 1326
9d1a50a2 1327 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
1da177e4
LT		 1328
1329 /* disable the DREN bit (Data Ready interrupt enable) before
1330 * requesting IRQs
1331 */
4444dcf1 1332 ucr4 = imx_uart_readl(sport, UCR4);
b6e49138 1333
1c5250d6 1334 /* set the trigger level for CTS */
4444dcf1
UKK		 1335 ucr4 &= ~(UCR4_CTSTL_MASK << UCR4_CTSTL_SHF);
1336 ucr4 |= CTSTL << UCR4_CTSTL_SHF;
1c5250d6 1337
4444dcf1 1338 imx_uart_writel(sport, ucr4 & ~UCR4_DREN, UCR4);
1da177e4 1339
7e11577e 1340 /* Can we enable the DMA support? */
4238c00b
UKK		 1341 if (!uart_console(port) && imx_uart_dma_init(sport) == 0)
1342 dma_is_inited = 1;
7e11577e 1343
53794183 1344 spin_lock_irqsave(&sport->port.lock, flags);
772f8991 1345 /* Reset fifo's and state machines */
458e2c82
FE		 1346 i = 100;
1347
4444dcf1
UKK		 1348 ucr2 = imx_uart_readl(sport, UCR2);
1349 ucr2 &= ~UCR2_SRST;
1350 imx_uart_writel(sport, ucr2, UCR2);
458e2c82 1351
27c84426 1352 while (!(imx_uart_readl(sport, UCR2) & UCR2_SRST) && (--i > 0))
458e2c82 1353 udelay(1);
b6e49138 1354
1da177e4
LT		 1355 /*
1356 * Finally, clear and enable interrupts
1357 */
27c84426
UKK		 1358 imx_uart_writel(sport, USR1_RTSD | USR1_DTRD, USR1);
1359 imx_uart_writel(sport, USR2_ORE, USR2);
ff4bfb21 1360
4444dcf1 1361 ucr1 = imx_uart_readl(sport, UCR1) & ~UCR1_RRDYEN;
4444dcf1 1362 ucr1 |= UCR1_UARTEN;
6376cd39 1363 if (sport->have_rtscts)
4444dcf1 1364 ucr1 |= UCR1_RTSDEN;
b6e49138 1365
4444dcf1 1366 imx_uart_writel(sport, ucr1, UCR1);
1da177e4 1367
4444dcf1 1368 ucr4 = imx_uart_readl(sport, UCR4) & ~UCR4_OREN;
1f043572 1369 if (!sport->dma_is_enabled)
4444dcf1
UKK		 1370 ucr4 |= UCR4_OREN;
1371 imx_uart_writel(sport, ucr4, UCR4);
6f026d6b 1372
4444dcf1
UKK		 1373 ucr2 = imx_uart_readl(sport, UCR2) & ~UCR2_ATEN;
1374 ucr2 |= (UCR2_RXEN | UCR2_TXEN);
bff09b09 1375 if (!sport->have_rtscts)
4444dcf1 1376 ucr2 |= UCR2_IRTS;
16804d68
UKK		 1377 /*
1378 * make sure the edge sensitive RTS-irq is disabled,
1379 * we're using RTSD instead.
1380 */
9d1a50a2 1381 if (!imx_uart_is_imx1(sport))
4444dcf1
UKK		 1382 ucr2 &= ~UCR2_RTSEN;
1383 imx_uart_writel(sport, ucr2, UCR2);
1da177e4 1384
9d1a50a2 1385 if (!imx_uart_is_imx1(sport)) {
4444dcf1
UKK		 1386 u32 ucr3;
1387
1388 ucr3 = imx_uart_readl(sport, UCR3);
16804d68 1389
4444dcf1 1390 ucr3 |= UCR3_DTRDEN | UCR3_RI | UCR3_DCD;
16804d68
UKK		 1391
1392 if (sport->dte_mode)
e61c38d8 1393 /* disable broken interrupts */
4444dcf1 1394 ucr3 &= ~(UCR3_RI | UCR3_DCD);
16804d68 1395
4444dcf1 1396 imx_uart_writel(sport, ucr3, UCR3);
37d6fb62 1397 }
4411805b 1398
1da177e4
LT		 1399 /*
1400 * Enable modem status interrupts
1401 */
9d1a50a2 1402 imx_uart_enable_ms(&sport->port);
18a42088 1403
76821e22 1404 if (dma_is_inited) {
9d1a50a2
UKK		 1405 imx_uart_enable_dma(sport);
1406 imx_uart_start_rx_dma(sport);
76821e22
UKK		 1407 } else {
1408 ucr1 = imx_uart_readl(sport, UCR1);
1409 ucr1 |= UCR1_RRDYEN;
1410 imx_uart_writel(sport, ucr1, UCR1);
81ca8e82
UKK		 1411
1412 ucr2 = imx_uart_readl(sport, UCR2);
1413 ucr2 |= UCR2_ATEN;
1414 imx_uart_writel(sport, ucr2, UCR2);
76821e22 1415 }
18a42088 1416
82313e66 1417 spin_unlock_irqrestore(&sport->port.lock, flags);
1da177e4
LT		 1418
1419 return 0;
1da177e4
LT		 1420}
1421
9d1a50a2 1422static void imx_uart_shutdown(struct uart_port *port)
1da177e4
LT		 1423{
1424 struct imx_port *sport = (struct imx_port *)port;
9ec1882d 1425 unsigned long flags;
339c7a87 1426 u32 ucr1, ucr2, ucr4;
1da177e4 1427
b4cdc8f6 1428 if (sport->dma_is_enabled) {
e5e89602 1429 dmaengine_terminate_sync(sport->dma_chan_tx);
7722c240
SR		 1430 if (sport->dma_is_txing) {
1431 dma_unmap_sg(sport->port.dev, &sport->tx_sgl[0],
1432 sport->dma_tx_nents, DMA_TO_DEVICE);
1433 sport->dma_is_txing = 0;
1434 }
e5e89602 1435 dmaengine_terminate_sync(sport->dma_chan_rx);
7722c240
SR		 1436 if (sport->dma_is_rxing) {
1437 dma_unmap_sg(sport->port.dev, &sport->rx_sgl,
1438 1, DMA_FROM_DEVICE);
1439 sport->dma_is_rxing = 0;
1440 }
a4688bcd 1441
73631813 1442 spin_lock_irqsave(&sport->port.lock, flags);
9d1a50a2
UKK		 1443 imx_uart_stop_tx(port);
1444 imx_uart_stop_rx(port);
1445 imx_uart_disable_dma(sport);
73631813 1446 spin_unlock_irqrestore(&sport->port.lock, flags);
b4cdc8f6
HS		 1447 imx_uart_dma_exit(sport);
1448 }
1449
58362d5b
UKK		 1450 mctrl_gpio_disable_ms(sport->gpios);
1451
9ec1882d 1452 spin_lock_irqsave(&sport->port.lock, flags);
4444dcf1 1453 ucr2 = imx_uart_readl(sport, UCR2);
0fdf1787 1454 ucr2 &= ~(UCR2_TXEN | UCR2_ATEN);
4444dcf1 1455 imx_uart_writel(sport, ucr2, UCR2);
339c7a87
SR		 1456
1457 ucr4 = imx_uart_readl(sport, UCR4);
1458 ucr4 &= ~UCR4_OREN;
1459 imx_uart_writel(sport, ucr4, UCR4);
9ec1882d 1460 spin_unlock_irqrestore(&sport->port.lock, flags);
2e146392 1461
1da177e4
LT		 1462 /*
1463 * Stop our timer.
1464 */
1465 del_timer_sync(&sport->timer);
1466
1da177e4
LT		 1467 /*
1468 * Disable all interrupts, port and break condition.
1469 */
1470
9ec1882d 1471 spin_lock_irqsave(&sport->port.lock, flags);
4444dcf1 1472 ucr1 = imx_uart_readl(sport, UCR1);
76821e22 1473 ucr1 &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN | UCR1_RXDMAEN | UCR1_ATDMAEN);
b6e49138 1474
4444dcf1 1475 imx_uart_writel(sport, ucr1, UCR1);
9ec1882d 1476 spin_unlock_irqrestore(&sport->port.lock, flags);
28eb4274 1477
1cf93e0d
HS		 1478 clk_disable_unprepare(sport->clk_per);
1479 clk_disable_unprepare(sport->clk_ipg);
1da177e4
LT		 1480}
1481
6aed2a88 1482/* called with port.lock taken and irqs off */
9d1a50a2 1483static void imx_uart_flush_buffer(struct uart_port *port)
eb56b7ed
HS		 1484{
1485 struct imx_port *sport = (struct imx_port *)port;
82e86ae9 1486 struct scatterlist *sgl = &sport->tx_sgl[0];
4444dcf1 1487 u32 ucr2;
4f86a95d 1488 int i = 100, ubir, ubmr, uts;
eb56b7ed 1489
82e86ae9
DB		 1490 if (!sport->dma_chan_tx)
1491 return;
1492
1493 sport->tx_bytes = 0;
1494 dmaengine_terminate_all(sport->dma_chan_tx);
1495 if (sport->dma_is_txing) {
4444dcf1
UKK		 1496 u32 ucr1;
1497
82e86ae9
DB		 1498 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents,
1499 DMA_TO_DEVICE);
4444dcf1
UKK		 1500 ucr1 = imx_uart_readl(sport, UCR1);
1501 ucr1 &= ~UCR1_TXDMAEN;
1502 imx_uart_writel(sport, ucr1, UCR1);
0f7bdbd2 1503 sport->dma_is_txing = 0;
eb56b7ed 1504 }
934084a9
FE		 1505
1506 /*
1507 * According to the Reference Manual description of the UART SRST bit:
263763c1 1508 *
934084a9
FE		 1509 * "Reset the transmit and receive state machines,
1510 * all FIFOs and register USR1, USR2, UBIR, UBMR, UBRC, URXD, UTXD
263763c1
MW		 1511 * and UTS[6-3]".
1512 *
1513 * We don't need to restore the old values from USR1, USR2, URXD and
1514 * UTXD. UBRC is read only, so only save/restore the other three
1515 * registers.
934084a9 1516 */
27c84426
UKK		 1517 ubir = imx_uart_readl(sport, UBIR);
1518 ubmr = imx_uart_readl(sport, UBMR);
1519 uts = imx_uart_readl(sport, IMX21_UTS);
934084a9 1520
4444dcf1
UKK		 1521 ucr2 = imx_uart_readl(sport, UCR2);
1522 ucr2 &= ~UCR2_SRST;
1523 imx_uart_writel(sport, ucr2, UCR2);
934084a9 1524
27c84426 1525 while (!(imx_uart_readl(sport, UCR2) & UCR2_SRST) && (--i > 0))
934084a9
FE		 1526 udelay(1);
1527
1528 /* Restore the registers */
27c84426
UKK		 1529 imx_uart_writel(sport, ubir, UBIR);
1530 imx_uart_writel(sport, ubmr, UBMR);
1531 imx_uart_writel(sport, uts, IMX21_UTS);
eb56b7ed
HS		 1532}
1533
1da177e4 1534static void
9d1a50a2
UKK		 1535imx_uart_set_termios(struct uart_port *port, struct ktermios *termios,
1536 struct ktermios *old)
1da177e4
LT		 1537{
1538 struct imx_port *sport = (struct imx_port *)port;
1539 unsigned long flags;
4444dcf1 1540 u32 ucr2, old_ucr1, old_ucr2, ufcr;
58362d5b 1541 unsigned int baud, quot;
1da177e4 1542 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
4444dcf1 1543 unsigned long div;
534fca06 1544 unsigned long num, denom;
d7f8d437 1545 uint64_t tdiv64;
1da177e4 1546
1da177e4
LT		 1547 /*
1548 * We only support CS7 and CS8.
1549 */
1550 while ((termios->c_cflag & CSIZE) != CS7 &&
1551 (termios->c_cflag & CSIZE) != CS8) {
1552 termios->c_cflag &= ~CSIZE;
1553 termios->c_cflag |= old_csize;
1554 old_csize = CS8;
1555 }
1556
1557 if ((termios->c_cflag & CSIZE) == CS8)
1558 ucr2 = UCR2_WS | UCR2_SRST | UCR2_IRTS;
1559 else
1560 ucr2 = UCR2_SRST | UCR2_IRTS;
1561
1562 if (termios->c_cflag & CRTSCTS) {
82313e66 1563 if (sport->have_rtscts) {
5b802344 1564 ucr2 &= ~UCR2_IRTS;
17b8f2a3 1565
12fe59f9 1566 if (port->rs485.flags & SER_RS485_ENABLED) {
17b8f2a3
UKK		 1567 /*
1568 * RTS is mandatory for rs485 operation, so keep
1569 * it under manual control and keep transmitter
1570 * disabled.
1571 */
58362d5b
UKK		 1572 if (port->rs485.flags &
1573 SER_RS485_RTS_AFTER_SEND)
9d1a50a2 1574 imx_uart_rts_active(sport, &ucr2);
1a613626 1575 else
9d1a50a2 1576 imx_uart_rts_inactive(sport, &ucr2);
12fe59f9 1577 } else {
9d1a50a2 1578 imx_uart_rts_auto(sport, &ucr2);
12fe59f9 1579 }
5b802344
SH		 1580 } else {
1581 termios->c_cflag &= ~CRTSCTS;
1582 }
58362d5b 1583 } else if (port->rs485.flags & SER_RS485_ENABLED) {
17b8f2a3 1584 /* disable transmitter */
58362d5b 1585 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND)
9d1a50a2 1586 imx_uart_rts_active(sport, &ucr2);
1a613626 1587 else
9d1a50a2 1588 imx_uart_rts_inactive(sport, &ucr2);
58362d5b
UKK		 1589 }
1590
1da177e4
LT		 1591
1592 if (termios->c_cflag & CSTOPB)
1593 ucr2 |= UCR2_STPB;
1594 if (termios->c_cflag & PARENB) {
1595 ucr2 |= UCR2_PREN;
3261e362 1596 if (termios->c_cflag & PARODD)
1da177e4
LT		 1597 ucr2 |= UCR2_PROE;
1598 }
1599
995234da
EM		 1600 del_timer_sync(&sport->timer);
1601
1da177e4
LT		 1602 /*
1603 * Ask the core to calculate the divisor for us.
1604 */
036bb15e 1605 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
1da177e4
LT		 1606 quot = uart_get_divisor(port, baud);
1607
1608 spin_lock_irqsave(&sport->port.lock, flags);
1609
1610 sport->port.read_status_mask = 0;
1611 if (termios->c_iflag & INPCK)
1612 sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR);
1613 if (termios->c_iflag & (BRKINT | PARMRK))
1614 sport->port.read_status_mask |= URXD_BRK;
1615
1616 /*
1617 * Characters to ignore
1618 */
1619 sport->port.ignore_status_mask = 0;
1620 if (termios->c_iflag & IGNPAR)
865cea85 1621 sport->port.ignore_status_mask |= URXD_PRERR | URXD_FRMERR;
1da177e4
LT		 1622 if (termios->c_iflag & IGNBRK) {
1623 sport->port.ignore_status_mask |= URXD_BRK;
1624 /*
1625 * If we're ignoring parity and break indicators,
1626 * ignore overruns too (for real raw support).
1627 */
1628 if (termios->c_iflag & IGNPAR)
1629 sport->port.ignore_status_mask |= URXD_OVRRUN;
1630 }
1631
55d8693a
JW		 1632 if ((termios->c_cflag & CREAD) == 0)
1633 sport->port.ignore_status_mask |= URXD_DUMMY_READ;
1634
1da177e4
LT		 1635 /*
1636 * Update the per-port timeout.
1637 */
1638 uart_update_timeout(port, termios->c_cflag, baud);
1639
1640 /*
1641 * disable interrupts and drain transmitter
1642 */
27c84426
UKK		 1643 old_ucr1 = imx_uart_readl(sport, UCR1);
1644 imx_uart_writel(sport,
1645 old_ucr1 & ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN),
1646 UCR1);
81ca8e82
UKK		 1647 old_ucr2 = imx_uart_readl(sport, UCR2);
1648 imx_uart_writel(sport, old_ucr2 & ~UCR2_ATEN, UCR2);
1da177e4 1649
27c84426 1650 while (!(imx_uart_readl(sport, USR2) & USR2_TXDC))
1da177e4
LT		 1651 barrier();
1652
1653 /* then, disable everything */
81ca8e82 1654 imx_uart_writel(sport, old_ucr2 & ~(UCR2_TXEN | UCR2_RXEN | UCR2_ATEN), UCR2);
86a04ba6 1655 old_ucr2 &= (UCR2_TXEN | UCR2_RXEN | UCR2_ATEN);
1da177e4 1656
afe9cbb1
UKK		 1657 /* custom-baudrate handling */
1658 div = sport->port.uartclk / (baud * 16);
1659 if (baud == 38400 && quot != div)
1660 baud = sport->port.uartclk / (quot * 16);
1661
1662 div = sport->port.uartclk / (baud * 16);
1663 if (div > 7)
1664 div = 7;
1665 if (!div)
036bb15e
SH		 1666 div = 1;
1667
534fca06
OS		 1668 rational_best_approximation(16 * div * baud, sport->port.uartclk,
1669 1 << 16, 1 << 16, &num, &denom);
036bb15e 1670
eab4f5af
AC		 1671 tdiv64 = sport->port.uartclk;
1672 tdiv64 *= num;
1673 do_div(tdiv64, denom * 16 * div);
1674 tty_termios_encode_baud_rate(termios,
1a2c4b31 1675 (speed_t)tdiv64, (speed_t)tdiv64);
d7f8d437 1676
534fca06
OS		 1677 num -= 1;
1678 denom -= 1;
036bb15e 1679
27c84426 1680 ufcr = imx_uart_readl(sport, UFCR);
b6e49138 1681 ufcr = (ufcr & (~UFCR_RFDIV)) | UFCR_RFDIV_REG(div);
27c84426 1682 imx_uart_writel(sport, ufcr, UFCR);
036bb15e 1683
27c84426
UKK		 1684 imx_uart_writel(sport, num, UBIR);
1685 imx_uart_writel(sport, denom, UBMR);
534fca06 1686
9d1a50a2 1687 if (!imx_uart_is_imx1(sport))
27c84426
UKK		 1688 imx_uart_writel(sport, sport->port.uartclk / div / 1000,
1689 IMX21_ONEMS);
ff4bfb21 1690
27c84426 1691 imx_uart_writel(sport, old_ucr1, UCR1);
1da177e4 1692
ff4bfb21 1693 /* set the parity, stop bits and data size */
27c84426 1694 imx_uart_writel(sport, ucr2 | old_ucr2, UCR2);
1da177e4
LT		 1695
1696 if (UART_ENABLE_MS(&sport->port, termios->c_cflag))
9d1a50a2 1697 imx_uart_enable_ms(&sport->port);
1da177e4
LT		 1698
1699 spin_unlock_irqrestore(&sport->port.lock, flags);
1700}
1701
9d1a50a2 1702static const char *imx_uart_type(struct uart_port *port)
1da177e4
LT		 1703{
1704 struct imx_port *sport = (struct imx_port *)port;
1705
1706 return sport->port.type == PORT_IMX ? "IMX" : NULL;
1707}
1708
1da177e4
LT		 1709/*
1710 * Configure/autoconfigure the port.
1711 */
9d1a50a2 1712static void imx_uart_config_port(struct uart_port *port, int flags)
1da177e4
LT		 1713{
1714 struct imx_port *sport = (struct imx_port *)port;
1715
da82f997 1716 if (flags & UART_CONFIG_TYPE)
1da177e4
LT		 1717 sport->port.type = PORT_IMX;
1718}
1719
1720/*
1721 * Verify the new serial_struct (for TIOCSSERIAL).
1722 * The only change we allow are to the flags and type, and
1723 * even then only between PORT_IMX and PORT_UNKNOWN
1724 */
1725static int
9d1a50a2 1726imx_uart_verify_port(struct uart_port *port, struct serial_struct *ser)
1da177e4
LT		 1727{
1728 struct imx_port *sport = (struct imx_port *)port;
1729 int ret = 0;
1730
1731 if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX)
1732 ret = -EINVAL;
1733 if (sport->port.irq != ser->irq)
1734 ret = -EINVAL;
1735 if (ser->io_type != UPIO_MEM)
1736 ret = -EINVAL;
1737 if (sport->port.uartclk / 16 != ser->baud_base)
1738 ret = -EINVAL;
a50c44ce 1739 if (sport->port.mapbase != (unsigned long)ser->iomem_base)
1da177e4
LT		 1740 ret = -EINVAL;
1741 if (sport->port.iobase != ser->port)
1742 ret = -EINVAL;
1743 if (ser->hub6 != 0)
1744 ret = -EINVAL;
1745 return ret;
1746}
1747
01f56abd 1748#if defined(CONFIG_CONSOLE_POLL)
6b8bdad9 1749
9d1a50a2 1750static int imx_uart_poll_init(struct uart_port *port)
6b8bdad9
DT		 1751{
1752 struct imx_port *sport = (struct imx_port *)port;
1753 unsigned long flags;
4444dcf1 1754 u32 ucr1, ucr2;
6b8bdad9
DT		 1755 int retval;
1756
1757 retval = clk_prepare_enable(sport->clk_ipg);
1758 if (retval)
1759 return retval;
1760 retval = clk_prepare_enable(sport->clk_per);
1761 if (retval)
1762 clk_disable_unprepare(sport->clk_ipg);
1763
9d1a50a2 1764 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
6b8bdad9
DT		 1765
1766 spin_lock_irqsave(&sport->port.lock, flags);
1767
76821e22
UKK		 1768 /*
1769 * Be careful about the order of enabling bits here. First enable the
1770 * receiver (UARTEN + RXEN) and only then the corresponding irqs.
1771 * This prevents that a character that already sits in the RX fifo is
1772 * triggering an irq but the try to fetch it from there results in an
1773 * exception because UARTEN or RXEN is still off.
1774 */
4444dcf1 1775 ucr1 = imx_uart_readl(sport, UCR1);
76821e22
UKK		 1776 ucr2 = imx_uart_readl(sport, UCR2);
1777
9d1a50a2 1778 if (imx_uart_is_imx1(sport))
4444dcf1 1779 ucr1 |= IMX1_UCR1_UARTCLKEN;
6b8bdad9 1780
76821e22
UKK		 1781 ucr1 |= UCR1_UARTEN;
1782 ucr1 &= ~(UCR1_TXMPTYEN | UCR1_RTSDEN | UCR1_RRDYEN);
1783
4444dcf1 1784 ucr2 |= UCR2_RXEN;
81ca8e82 1785 ucr2 &= ~UCR2_ATEN;
76821e22
UKK		 1786
1787 imx_uart_writel(sport, ucr1, UCR1);
4444dcf1 1788 imx_uart_writel(sport, ucr2, UCR2);
6b8bdad9 1789
76821e22
UKK		 1790 /* now enable irqs */
1791 imx_uart_writel(sport, ucr1 | UCR1_RRDYEN, UCR1);
81ca8e82 1792 imx_uart_writel(sport, ucr2 | UCR2_ATEN, UCR2);
76821e22 1793
6b8bdad9
DT		 1794 spin_unlock_irqrestore(&sport->port.lock, flags);
1795
1796 return 0;
1797}
1798
9d1a50a2 1799static int imx_uart_poll_get_char(struct uart_port *port)
01f56abd 1800{
27c84426
UKK		 1801 struct imx_port *sport = (struct imx_port *)port;
1802 if (!(imx_uart_readl(sport, USR2) & USR2_RDR))
26c47412 1803 return NO_POLL_CHAR;
01f56abd 1804
27c84426 1805 return imx_uart_readl(sport, URXD0) & URXD_RX_DATA;
01f56abd
SA		 1806}
1807
9d1a50a2 1808static void imx_uart_poll_put_char(struct uart_port *port, unsigned char c)
01f56abd 1809{
27c84426 1810 struct imx_port *sport = (struct imx_port *)port;
01f56abd
SA		 1811 unsigned int status;
1812
01f56abd
SA		 1813 /* drain */
1814 do {
27c84426 1815 status = imx_uart_readl(sport, USR1);
01f56abd
SA		 1816 } while (~status & USR1_TRDY);
1817
1818 /* write */
27c84426 1819 imx_uart_writel(sport, c, URTX0);
01f56abd
SA		 1820
1821 /* flush */
1822 do {
27c84426 1823 status = imx_uart_readl(sport, USR2);
01f56abd 1824 } while (~status & USR2_TXDC);
01f56abd
SA		 1825}
1826#endif
1827
6aed2a88 1828/* called with port.lock taken and irqs off or from .probe without locking */
9d1a50a2
UKK		 1829static int imx_uart_rs485_config(struct uart_port *port,
1830 struct serial_rs485 *rs485conf)
17b8f2a3
UKK		 1831{
1832 struct imx_port *sport = (struct imx_port *)port;
4444dcf1 1833 u32 ucr2;
17b8f2a3
UKK		 1834
1835 /* unimplemented */
1836 rs485conf->delay_rts_before_send = 0;
1837 rs485conf->delay_rts_after_send = 0;
17b8f2a3
UKK		 1838
1839 /* RTS is required to control the transmitter */
7b7e8e8e 1840 if (!sport->have_rtscts && !sport->have_rtsgpio)
17b8f2a3
UKK		 1841 rs485conf->flags &= ~SER_RS485_ENABLED;
1842
1843 if (rs485conf->flags & SER_RS485_ENABLED) {
6d215f83
SA		 1844 /* Enable receiver if low-active RTS signal is requested */
1845 if (sport->have_rtscts && !sport->have_rtsgpio &&
1846 !(rs485conf->flags & SER_RS485_RTS_ON_SEND))
1847 rs485conf->flags |= SER_RS485_RX_DURING_TX;
1848
17b8f2a3 1849 /* disable transmitter */
4444dcf1 1850 ucr2 = imx_uart_readl(sport, UCR2);
17b8f2a3 1851 if (rs485conf->flags & SER_RS485_RTS_AFTER_SEND)
9d1a50a2 1852 imx_uart_rts_active(sport, &ucr2);
1a613626 1853 else
9d1a50a2 1854 imx_uart_rts_inactive(sport, &ucr2);
4444dcf1 1855 imx_uart_writel(sport, ucr2, UCR2);
17b8f2a3
UKK		 1856 }
1857
7d1cadca
BS		 1858 /* Make sure Rx is enabled in case Tx is active with Rx disabled */
1859 if (!(rs485conf->flags & SER_RS485_ENABLED) ||
76821e22 1860 rs485conf->flags & SER_RS485_RX_DURING_TX)
9d1a50a2 1861 imx_uart_start_rx(port);
7d1cadca 1862
17b8f2a3
UKK		 1863 port->rs485 = *rs485conf;
1864
1865 return 0;
1866}
1867
9d1a50a2
UKK		 1868static const struct uart_ops imx_uart_pops = {
1869 .tx_empty = imx_uart_tx_empty,
1870 .set_mctrl = imx_uart_set_mctrl,
1871 .get_mctrl = imx_uart_get_mctrl,
1872 .stop_tx = imx_uart_stop_tx,
1873 .start_tx = imx_uart_start_tx,
1874 .stop_rx = imx_uart_stop_rx,
1875 .enable_ms = imx_uart_enable_ms,
1876 .break_ctl = imx_uart_break_ctl,
1877 .startup = imx_uart_startup,
1878 .shutdown = imx_uart_shutdown,
1879 .flush_buffer = imx_uart_flush_buffer,
1880 .set_termios = imx_uart_set_termios,
1881 .type = imx_uart_type,
1882 .config_port = imx_uart_config_port,
1883 .verify_port = imx_uart_verify_port,
01f56abd 1884#if defined(CONFIG_CONSOLE_POLL)
9d1a50a2
UKK		 1885 .poll_init = imx_uart_poll_init,
1886 .poll_get_char = imx_uart_poll_get_char,
1887 .poll_put_char = imx_uart_poll_put_char,
01f56abd 1888#endif
1da177e4
LT		 1889};
1890
9d1a50a2 1891static struct imx_port *imx_uart_ports[UART_NR];
1da177e4
LT		 1892
1893#ifdef CONFIG_SERIAL_IMX_CONSOLE
9d1a50a2 1894static void imx_uart_console_putchar(struct uart_port *port, int ch)
d358788f
RK		 1895{
1896 struct imx_port *sport = (struct imx_port *)port;
ff4bfb21 1897
9d1a50a2 1898 while (imx_uart_readl(sport, imx_uart_uts_reg(sport)) & UTS_TXFULL)
d358788f 1899 barrier();
ff4bfb21 1900
27c84426 1901 imx_uart_writel(sport, ch, URTX0);
d358788f 1902}
1da177e4
LT		 1903
1904/*
1905 * Interrupts are disabled on entering
1906 */
1907static void
9d1a50a2 1908imx_uart_console_write(struct console *co, const char *s, unsigned int count)
1da177e4 1909{
9d1a50a2 1910 struct imx_port *sport = imx_uart_ports[co->index];
0ad5a814
DB		 1911 struct imx_port_ucrs old_ucr;
1912 unsigned int ucr1;
f30e8260 1913 unsigned long flags = 0;
677fe555 1914 int locked = 1;
1cf93e0d
HS		 1915 int retval;
1916
0c727a42 1917 retval = clk_enable(sport->clk_per);
1cf93e0d
HS		 1918 if (retval)
1919 return;
0c727a42 1920 retval = clk_enable(sport->clk_ipg);
1cf93e0d 1921 if (retval) {
0c727a42 1922 clk_disable(sport->clk_per);
1cf93e0d
HS		 1923 return;
1924 }
9ec1882d 1925
677fe555
TG		 1926 if (sport->port.sysrq)
1927 locked = 0;
1928 else if (oops_in_progress)
1929 locked = spin_trylock_irqsave(&sport->port.lock, flags);
1930 else
1931 spin_lock_irqsave(&sport->port.lock, flags);
1da177e4
LT		 1932
1933 /*
0ad5a814 1934 * First, save UCR1/2/3 and then disable interrupts
1da177e4 1935 */
9d1a50a2 1936 imx_uart_ucrs_save(sport, &old_ucr);
0ad5a814 1937 ucr1 = old_ucr.ucr1;
1da177e4 1938
9d1a50a2 1939 if (imx_uart_is_imx1(sport))
fe6b540a 1940 ucr1 |= IMX1_UCR1_UARTCLKEN;
37d6fb62
SH		 1941 ucr1 |= UCR1_UARTEN;
1942 ucr1 &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN);
1943
27c84426 1944 imx_uart_writel(sport, ucr1, UCR1);
ff4bfb21 1945
27c84426 1946 imx_uart_writel(sport, old_ucr.ucr2 | UCR2_TXEN, UCR2);
1da177e4 1947
9d1a50a2 1948 uart_console_write(&sport->port, s, count, imx_uart_console_putchar);
1da177e4
LT		 1949
1950 /*
1951 * Finally, wait for transmitter to become empty
0ad5a814 1952 * and restore UCR1/2/3
1da177e4 1953 */
27c84426 1954 while (!(imx_uart_readl(sport, USR2) & USR2_TXDC));
1da177e4 1955
9d1a50a2 1956 imx_uart_ucrs_restore(sport, &old_ucr);
9ec1882d 1957
677fe555
TG		 1958 if (locked)
1959 spin_unlock_irqrestore(&sport->port.lock, flags);
1cf93e0d 1960
0c727a42
FE		 1961 clk_disable(sport->clk_ipg);
1962 clk_disable(sport->clk_per);
1da177e4
LT		 1963}
1964
1965/*
1966 * If the port was already initialised (eg, by a boot loader),
1967 * try to determine the current setup.
1968 */
1969static void __init
9d1a50a2
UKK		 1970imx_uart_console_get_options(struct imx_port *sport, int *baud,
1971 int *parity, int *bits)
1da177e4 1972{
587897f5 1973
27c84426 1974 if (imx_uart_readl(sport, UCR1) & UCR1_UARTEN) {
1da177e4 1975 /* ok, the port was enabled */
82313e66 1976 unsigned int ucr2, ubir, ubmr, uartclk;
587897f5
SH		 1977 unsigned int baud_raw;
1978 unsigned int ucfr_rfdiv;
1da177e4 1979
27c84426 1980 ucr2 = imx_uart_readl(sport, UCR2);
1da177e4
LT		 1981
1982 *parity = 'n';
1983 if (ucr2 & UCR2_PREN) {
1984 if (ucr2 & UCR2_PROE)
1985 *parity = 'o';
1986 else
1987 *parity = 'e';
1988 }
1989
1990 if (ucr2 & UCR2_WS)
1991 *bits = 8;
1992 else
1993 *bits = 7;
1994
27c84426
UKK		 1995 ubir = imx_uart_readl(sport, UBIR) & 0xffff;
1996 ubmr = imx_uart_readl(sport, UBMR) & 0xffff;
587897f5 1997
27c84426 1998 ucfr_rfdiv = (imx_uart_readl(sport, UFCR) & UFCR_RFDIV) >> 7;
587897f5
SH		 1999 if (ucfr_rfdiv == 6)
2000 ucfr_rfdiv = 7;
2001 else
2002 ucfr_rfdiv = 6 - ucfr_rfdiv;
2003
3a9465fa 2004 uartclk = clk_get_rate(sport->clk_per);
587897f5
SH		 2005 uartclk /= ucfr_rfdiv;
2006
2007 { /*
2008 * The next code provides exact computation of
2009 * baud_raw = round(((uartclk/16) * (ubir + 1)) / (ubmr + 1))
2010 * without need of float support or long long division,
2011 * which would be required to prevent 32bit arithmetic overflow
2012 */
2013 unsigned int mul = ubir + 1;
2014 unsigned int div = 16 * (ubmr + 1);
2015 unsigned int rem = uartclk % div;
2016
2017 baud_raw = (uartclk / div) * mul;
2018 baud_raw += (rem * mul + div / 2) / div;
2019 *baud = (baud_raw + 50) / 100 * 100;
2020 }
2021
82313e66 2022 if (*baud != baud_raw)
50bbdba3 2023 pr_info("Console IMX rounded baud rate from %d to %d\n",
587897f5 2024 baud_raw, *baud);
1da177e4
LT		 2025 }
2026}
2027
2028static int __init
9d1a50a2 2029imx_uart_console_setup(struct console *co, char *options)
1da177e4
LT		 2030{
2031 struct imx_port *sport;
2032 int baud = 9600;
2033 int bits = 8;
2034 int parity = 'n';
2035 int flow = 'n';
1cf93e0d 2036 int retval;
1da177e4
LT		 2037
2038 /*
2039 * Check whether an invalid uart number has been specified, and
2040 * if so, search for the first available port that does have
2041 * console support.
2042 */
9d1a50a2 2043 if (co->index == -1 || co->index >= ARRAY_SIZE(imx_uart_ports))
1da177e4 2044 co->index = 0;
9d1a50a2 2045 sport = imx_uart_ports[co->index];
82313e66 2046 if (sport == NULL)
e76afc4e 2047 return -ENODEV;
1da177e4 2048
1cf93e0d
HS		 2049 /* For setting the registers, we only need to enable the ipg clock. */
2050 retval = clk_prepare_enable(sport->clk_ipg);
2051 if (retval)
2052 goto error_console;
2053
1da177e4
LT		 2054 if (options)
2055 uart_parse_options(options, &baud, &parity, &bits, &flow);
2056 else
9d1a50a2 2057 imx_uart_console_get_options(sport, &baud, &parity, &bits);
1da177e4 2058
9d1a50a2 2059 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
587897f5 2060
1cf93e0d
HS		 2061 retval = uart_set_options(&sport->port, co, baud, parity, bits, flow);
2062
0c727a42
FE		 2063 clk_disable(sport->clk_ipg);
2064 if (retval) {
2065 clk_unprepare(sport->clk_ipg);
2066 goto error_console;
2067 }
2068
2069 retval = clk_prepare(sport->clk_per);
2070 if (retval)
2071 clk_disable_unprepare(sport->clk_ipg);
1cf93e0d
HS		 2072
2073error_console:
2074 return retval;
1da177e4
LT		 2075}
2076
9d1a50a2
UKK		 2077static struct uart_driver imx_uart_uart_driver;
2078static struct console imx_uart_console = {
e3d13ff4 2079 .name = DEV_NAME,
9d1a50a2 2080 .write = imx_uart_console_write,
1da177e4 2081 .device = uart_console_device,
9d1a50a2 2082 .setup = imx_uart_console_setup,
1da177e4
LT		 2083 .flags = CON_PRINTBUFFER,
2084 .index = -1,
9d1a50a2 2085 .data = &imx_uart_uart_driver,
1da177e4
LT		 2086};
2087
9d1a50a2 2088#define IMX_CONSOLE &imx_uart_console
913c6c0e
LS		 2089
2090#ifdef CONFIG_OF
9d1a50a2 2091static void imx_uart_console_early_putchar(struct uart_port *port, int ch)
913c6c0e 2092{
27c84426
UKK		 2093 struct imx_port *sport = (struct imx_port *)port;
2094
2095 while (imx_uart_readl(sport, IMX21_UTS) & UTS_TXFULL)
913c6c0e
LS		 2096 cpu_relax();
2097
27c84426 2098 imx_uart_writel(sport, ch, URTX0);
913c6c0e
LS		 2099}
2100
9d1a50a2
UKK		 2101static void imx_uart_console_early_write(struct console *con, const char *s,
2102 unsigned count)
913c6c0e
LS		 2103{
2104 struct earlycon_device *dev = con->data;
2105
9d1a50a2 2106 uart_console_write(&dev->port, s, count, imx_uart_console_early_putchar);
913c6c0e
LS		 2107}
2108
2109static int __init
2110imx_console_early_setup(struct earlycon_device *dev, const char *opt)
2111{
2112 if (!dev->port.membase)
2113 return -ENODEV;
2114
9d1a50a2 2115 dev->con->write = imx_uart_console_early_write;
913c6c0e
LS		 2116
2117 return 0;
2118}
2119OF_EARLYCON_DECLARE(ec_imx6q, "fsl,imx6q-uart", imx_console_early_setup);
2120OF_EARLYCON_DECLARE(ec_imx21, "fsl,imx21-uart", imx_console_early_setup);
2121#endif
2122
1da177e4
LT		 2123#else
2124#define IMX_CONSOLE NULL
2125#endif
2126
9d1a50a2 2127static struct uart_driver imx_uart_uart_driver = {
1da177e4
LT		 2128 .owner = THIS_MODULE,
2129 .driver_name = DRIVER_NAME,
e3d13ff4 2130 .dev_name = DEV_NAME,
1da177e4
LT		 2131 .major = SERIAL_IMX_MAJOR,
2132 .minor = MINOR_START,
9d1a50a2 2133 .nr = ARRAY_SIZE(imx_uart_ports),
1da177e4
LT		 2134 .cons = IMX_CONSOLE,
2135};
2136
22698aa2 2137#ifdef CONFIG_OF
20bb8095
UKK		 2138/*
2139 * This function returns 1 iff pdev isn't a device instatiated by dt, 0 iff it
2140 * could successfully get all information from dt or a negative errno.
2141 */
9d1a50a2
UKK		 2142static int imx_uart_probe_dt(struct imx_port *sport,
2143 struct platform_device *pdev)
22698aa2
SG		 2144{
2145 struct device_node *np = pdev->dev.of_node;
ff05967a 2146 int ret;
22698aa2 2147
5f8b9043
LC		 2148 sport->devdata = of_device_get_match_data(&pdev->dev);
2149 if (!sport->devdata)
20bb8095
UKK		 2150 /* no device tree device */
2151 return 1;
22698aa2 2152
ff05967a
SG		 2153 ret = of_alias_get_id(np, "serial");
2154 if (ret < 0) {
2155 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret);
a197a191 2156 return ret;
ff05967a
SG		 2157 }
2158 sport->port.line = ret;
22698aa2 2159
1006ed7e
GU		 2160 if (of_get_property(np, "uart-has-rtscts", NULL) ||
2161 of_get_property(np, "fsl,uart-has-rtscts", NULL) /* deprecated */)
22698aa2
SG		 2162 sport->have_rtscts = 1;
2163
20ff2fe6
HS		 2164 if (of_get_property(np, "fsl,dte-mode", NULL))
2165 sport->dte_mode = 1;
2166
7b7e8e8e
FE		 2167 if (of_get_property(np, "rts-gpios", NULL))
2168 sport->have_rtsgpio = 1;
2169
22698aa2
SG		 2170 return 0;
2171}
2172#else
9d1a50a2
UKK		 2173static inline int imx_uart_probe_dt(struct imx_port *sport,
2174 struct platform_device *pdev)
22698aa2 2175{
20bb8095 2176 return 1;
22698aa2
SG		 2177}
2178#endif
2179
9d1a50a2
UKK		 2180static void imx_uart_probe_pdata(struct imx_port *sport,
2181 struct platform_device *pdev)
22698aa2 2182{
574de559 2183 struct imxuart_platform_data *pdata = dev_get_platdata(&pdev->dev);
22698aa2
SG		 2184
2185 sport->port.line = pdev->id;
2186 sport->devdata = (struct imx_uart_data *) pdev->id_entry->driver_data;
2187
2188 if (!pdata)
2189 return;
2190
2191 if (pdata->flags & IMXUART_HAVE_RTSCTS)
2192 sport->have_rtscts = 1;
22698aa2
SG		 2193}
2194
9d1a50a2 2195static int imx_uart_probe(struct platform_device *pdev)
1da177e4 2196{
dbff4e9e 2197 struct imx_port *sport;
dbff4e9e 2198 void __iomem *base;
4444dcf1
UKK		 2199 int ret = 0;
2200 u32 ucr1;
dbff4e9e 2201 struct resource *res;
842633bd 2202 int txirq, rxirq, rtsirq;
dbff4e9e 2203
42d34191 2204 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);
dbff4e9e
SH		 2205 if (!sport)
2206 return -ENOMEM;
5b802344 2207
9d1a50a2 2208 ret = imx_uart_probe_dt(sport, pdev);
20bb8095 2209 if (ret > 0)
9d1a50a2 2210 imx_uart_probe_pdata(sport, pdev);
20bb8095 2211 else if (ret < 0)
42d34191 2212 return ret;
22698aa2 2213
9d1a50a2 2214 if (sport->port.line >= ARRAY_SIZE(imx_uart_ports)) {
56734448
GU		 2215 dev_err(&pdev->dev, "serial%d out of range\n",
2216 sport->port.line);
2217 return -EINVAL;
2218 }
2219
dbff4e9e 2220 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
da82f997
AS		 2221 base = devm_ioremap_resource(&pdev->dev, res);
2222 if (IS_ERR(base))
2223 return PTR_ERR(base);
dbff4e9e 2224
842633bd
UKK		 2225 rxirq = platform_get_irq(pdev, 0);
2226 txirq = platform_get_irq(pdev, 1);
2227 rtsirq = platform_get_irq(pdev, 2);
2228
dbff4e9e
SH		 2229 sport->port.dev = &pdev->dev;
2230 sport->port.mapbase = res->start;
2231 sport->port.membase = base;
2232 sport->port.type = PORT_IMX,
2233 sport->port.iotype = UPIO_MEM;
842633bd 2234 sport->port.irq = rxirq;
dbff4e9e 2235 sport->port.fifosize = 32;
9d1a50a2
UKK		 2236 sport->port.ops = &imx_uart_pops;
2237 sport->port.rs485_config = imx_uart_rs485_config;
dbff4e9e 2238 sport->port.flags = UPF_BOOT_AUTOCONF;
9d1a50a2 2239 timer_setup(&sport->timer, imx_uart_timeout, 0);
38a41fdf 2240
58362d5b
UKK		 2241 sport->gpios = mctrl_gpio_init(&sport->port, 0);
2242 if (IS_ERR(sport->gpios))
2243 return PTR_ERR(sport->gpios);
2244
3a9465fa
SH		 2245 sport->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
2246 if (IS_ERR(sport->clk_ipg)) {
2247 ret = PTR_ERR(sport->clk_ipg);
833462e9 2248 dev_err(&pdev->dev, "failed to get ipg clk: %d\n", ret);
42d34191 2249 return ret;
38a41fdf 2250 }
38a41fdf 2251
3a9465fa
SH		 2252 sport->clk_per = devm_clk_get(&pdev->dev, "per");
2253 if (IS_ERR(sport->clk_per)) {
2254 ret = PTR_ERR(sport->clk_per);
833462e9 2255 dev_err(&pdev->dev, "failed to get per clk: %d\n", ret);
42d34191 2256 return ret;
3a9465fa
SH		 2257 }
2258
3a9465fa 2259 sport->port.uartclk = clk_get_rate(sport->clk_per);
dbff4e9e 2260
8a61f0c7
FE		 2261 /* For register access, we only need to enable the ipg clock. */
2262 ret = clk_prepare_enable(sport->clk_ipg);
1e512d45
UKK		 2263 if (ret) {
2264 dev_err(&pdev->dev, "failed to enable per clk: %d\n", ret);
8a61f0c7 2265 return ret;
1e512d45 2266 }
8a61f0c7 2267
3a0ab62f
UKK		 2268 /* initialize shadow register values */
2269 sport->ucr1 = readl(sport->port.membase + UCR1);
2270 sport->ucr2 = readl(sport->port.membase + UCR2);
2271 sport->ucr3 = readl(sport->port.membase + UCR3);
2272 sport->ucr4 = readl(sport->port.membase + UCR4);
2273 sport->ufcr = readl(sport->port.membase + UFCR);
2274
743f93f8
LW		 2275 uart_get_rs485_mode(&pdev->dev, &sport->port.rs485);
2276
b8f3bff0 2277 if (sport->port.rs485.flags & SER_RS485_ENABLED &&
5d7f77ec 2278 (!sport->have_rtscts && !sport->have_rtsgpio))
b8f3bff0
LW		 2279 dev_err(&pdev->dev, "no RTS control, disabling rs485\n");
2280
6d215f83
SA		 2281 /*
2282 * If using the i.MX UART RTS/CTS control then the RTS (CTS_B)
2283 * signal cannot be set low during transmission in case the
2284 * receiver is off (limitation of the i.MX UART IP).
2285 */
2286 if (sport->port.rs485.flags & SER_RS485_ENABLED &&
2287 sport->have_rtscts && !sport->have_rtsgpio &&
2288 (!(sport->port.rs485.flags & SER_RS485_RTS_ON_SEND) &&
2289 !(sport->port.rs485.flags & SER_RS485_RX_DURING_TX)))
2290 dev_err(&pdev->dev,
2291 "low-active RTS not possible when receiver is off, enabling receiver\n");
2292
9d1a50a2 2293 imx_uart_rs485_config(&sport->port, &sport->port.rs485);
b8f3bff0 2294
8a61f0c7 2295 /* Disable interrupts before requesting them */
4444dcf1
UKK		 2296 ucr1 = imx_uart_readl(sport, UCR1);
2297 ucr1 &= ~(UCR1_ADEN | UCR1_TRDYEN | UCR1_IDEN | UCR1_RRDYEN |
8a61f0c7 2298 UCR1_TXMPTYEN | UCR1_RTSDEN);
4444dcf1 2299 imx_uart_writel(sport, ucr1, UCR1);
8a61f0c7 2300
9d1a50a2 2301 if (!imx_uart_is_imx1(sport) && sport->dte_mode) {
e61c38d8
UKK		 2302 /*
2303 * The DCEDTE bit changes the direction of DSR, DCD, DTR and RI
2304 * and influences if UCR3_RI and UCR3_DCD changes the level of RI
2305 * and DCD (when they are outputs) or enables the respective
2306 * irqs. So set this bit early, i.e. before requesting irqs.
2307 */
4444dcf1
UKK		 2308 u32 ufcr = imx_uart_readl(sport, UFCR);
2309 if (!(ufcr & UFCR_DCEDTE))
2310 imx_uart_writel(sport, ufcr | UFCR_DCEDTE, UFCR);
e61c38d8
UKK		 2311
2312 /*
2313 * Disable UCR3_RI and UCR3_DCD irqs. They are also not
2314 * enabled later because they cannot be cleared
2315 * (confirmed on i.MX25) which makes them unusable.
2316 */
27c84426
UKK		 2317 imx_uart_writel(sport,
2318 IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP | UCR3_DSR,
2319 UCR3);
e61c38d8
UKK		 2320
2321 } else {
4444dcf1
UKK		 2322 u32 ucr3 = UCR3_DSR;
2323 u32 ufcr = imx_uart_readl(sport, UFCR);
2324 if (ufcr & UFCR_DCEDTE)
2325 imx_uart_writel(sport, ufcr & ~UFCR_DCEDTE, UFCR);
6df765dc 2326
9d1a50a2 2327 if (!imx_uart_is_imx1(sport))
6df765dc 2328 ucr3 |= IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP;
27c84426 2329 imx_uart_writel(sport, ucr3, UCR3);
e61c38d8
UKK		 2330 }
2331
8a61f0c7
FE		 2332 clk_disable_unprepare(sport->clk_ipg);
2333
c0d1c6b0
FE		 2334 /*
2335 * Allocate the IRQ(s) i.MX1 has three interrupts whereas later
2336 * chips only have one interrupt.
2337 */
842633bd 2338 if (txirq > 0) {
9d1a50a2 2339 ret = devm_request_irq(&pdev->dev, rxirq, imx_uart_rxint, 0,
c0d1c6b0 2340 dev_name(&pdev->dev), sport);
1e512d45
UKK		 2341 if (ret) {
2342 dev_err(&pdev->dev, "failed to request rx irq: %d\n",
2343 ret);
c0d1c6b0 2344 return ret;
1e512d45 2345 }
c0d1c6b0 2346
9d1a50a2 2347 ret = devm_request_irq(&pdev->dev, txirq, imx_uart_txint, 0,
c0d1c6b0 2348 dev_name(&pdev->dev), sport);
1e512d45
UKK		 2349 if (ret) {
2350 dev_err(&pdev->dev, "failed to request tx irq: %d\n",
2351 ret);
c0d1c6b0 2352 return ret;
1e512d45 2353 }
c0d1c6b0 2354 } else {
9d1a50a2 2355 ret = devm_request_irq(&pdev->dev, rxirq, imx_uart_int, 0,
c0d1c6b0 2356 dev_name(&pdev->dev), sport);
1e512d45
UKK		 2357 if (ret) {
2358 dev_err(&pdev->dev, "failed to request irq: %d\n", ret);
c0d1c6b0 2359 return ret;
1e512d45 2360 }
c0d1c6b0
FE		 2361 }
2362
9d1a50a2 2363 imx_uart_ports[sport->port.line] = sport;
5b802344 2364
0a86a86b 2365 platform_set_drvdata(pdev, sport);
5b802344 2366
9d1a50a2 2367 return uart_add_one_port(&imx_uart_uart_driver, &sport->port);
1da177e4
LT		 2368}
2369
9d1a50a2 2370static int imx_uart_remove(struct platform_device *pdev)
1da177e4 2371{
2582d8c1 2372 struct imx_port *sport = platform_get_drvdata(pdev);
1da177e4 2373
9d1a50a2 2374 return uart_remove_one_port(&imx_uart_uart_driver, &sport->port);
1da177e4
LT		 2375}
2376
9d1a50a2 2377static void imx_uart_restore_context(struct imx_port *sport)
c868cbb7
EV		 2378{
2379 if (!sport->context_saved)
2380 return;
2381
27c84426
UKK		 2382 imx_uart_writel(sport, sport->saved_reg[4], UFCR);
2383 imx_uart_writel(sport, sport->saved_reg[5], UESC);
2384 imx_uart_writel(sport, sport->saved_reg[6], UTIM);
2385 imx_uart_writel(sport, sport->saved_reg[7], UBIR);
2386 imx_uart_writel(sport, sport->saved_reg[8], UBMR);
2387 imx_uart_writel(sport, sport->saved_reg[9], IMX21_UTS);
2388 imx_uart_writel(sport, sport->saved_reg[0], UCR1);
2389 imx_uart_writel(sport, sport->saved_reg[1] | UCR2_SRST, UCR2);
2390 imx_uart_writel(sport, sport->saved_reg[2], UCR3);
2391 imx_uart_writel(sport, sport->saved_reg[3], UCR4);
c868cbb7
EV		 2392 sport->context_saved = false;
2393}
2394
9d1a50a2 2395static void imx_uart_save_context(struct imx_port *sport)
c868cbb7
EV		 2396{
2397 /* Save necessary regs */
27c84426
UKK		 2398 sport->saved_reg[0] = imx_uart_readl(sport, UCR1);
2399 sport->saved_reg[1] = imx_uart_readl(sport, UCR2);
2400 sport->saved_reg[2] = imx_uart_readl(sport, UCR3);
2401 sport->saved_reg[3] = imx_uart_readl(sport, UCR4);
2402 sport->saved_reg[4] = imx_uart_readl(sport, UFCR);
2403 sport->saved_reg[5] = imx_uart_readl(sport, UESC);
2404 sport->saved_reg[6] = imx_uart_readl(sport, UTIM);
2405 sport->saved_reg[7] = imx_uart_readl(sport, UBIR);
2406 sport->saved_reg[8] = imx_uart_readl(sport, UBMR);
2407 sport->saved_reg[9] = imx_uart_readl(sport, IMX21_UTS);
c868cbb7
EV		 2408 sport->context_saved = true;
2409}
2410
9d1a50a2 2411static void imx_uart_enable_wakeup(struct imx_port *sport, bool on)
189550b8 2412{
4444dcf1 2413 u32 ucr3;
189550b8 2414
4444dcf1 2415 ucr3 = imx_uart_readl(sport, UCR3);
09df0b34 2416 if (on) {
27c84426 2417 imx_uart_writel(sport, USR1_AWAKE, USR1);
4444dcf1
UKK		 2418 ucr3 |= UCR3_AWAKEN;
2419 } else {
2420 ucr3 &= ~UCR3_AWAKEN;
09df0b34 2421 }
4444dcf1 2422 imx_uart_writel(sport, ucr3, UCR3);
bc85734b 2423
38b1f0fb 2424 if (sport->have_rtscts) {
4444dcf1 2425 u32 ucr1 = imx_uart_readl(sport, UCR1);
38b1f0fb 2426 if (on)
4444dcf1 2427 ucr1 |= UCR1_RTSDEN;
38b1f0fb 2428 else
4444dcf1
UKK		 2429 ucr1 &= ~UCR1_RTSDEN;
2430 imx_uart_writel(sport, ucr1, UCR1);
38b1f0fb 2431 }
189550b8
EV		 2432}
2433
9d1a50a2 2434static int imx_uart_suspend_noirq(struct device *dev)
90bb6bd3 2435{
a406c4b8 2436 struct imx_port *sport = dev_get_drvdata(dev);
90bb6bd3 2437
9d1a50a2 2438 imx_uart_save_context(sport);
90bb6bd3
SW		 2439
2440 clk_disable(sport->clk_ipg);
2441
2442 return 0;
2443}
2444
9d1a50a2 2445static int imx_uart_resume_noirq(struct device *dev)
90bb6bd3 2446{
a406c4b8 2447 struct imx_port *sport = dev_get_drvdata(dev);
90bb6bd3
SW		 2448 int ret;
2449
2450 ret = clk_enable(sport->clk_ipg);
2451 if (ret)
2452 return ret;
2453
9d1a50a2 2454 imx_uart_restore_context(sport);
90bb6bd3 2455
90bb6bd3
SW		 2456 return 0;
2457}
2458
9d1a50a2 2459static int imx_uart_suspend(struct device *dev)
90bb6bd3 2460{
a406c4b8 2461 struct imx_port *sport = dev_get_drvdata(dev);
09df0b34 2462 int ret;
90bb6bd3 2463
9d1a50a2 2464 uart_suspend_port(&imx_uart_uart_driver, &sport->port);
81b289cc 2465 disable_irq(sport->port.irq);
90bb6bd3 2466
09df0b34
MK		 2467 ret = clk_prepare_enable(sport->clk_ipg);
2468 if (ret)
2469 return ret;
2470
2471 /* enable wakeup from i.MX UART */
9d1a50a2 2472 imx_uart_enable_wakeup(sport, true);
09df0b34
MK		 2473
2474 return 0;
90bb6bd3
SW		 2475}
2476
9d1a50a2 2477static int imx_uart_resume(struct device *dev)
90bb6bd3 2478{
a406c4b8 2479 struct imx_port *sport = dev_get_drvdata(dev);
90bb6bd3
SW		 2480
2481 /* disable wakeup from i.MX UART */
9d1a50a2 2482 imx_uart_enable_wakeup(sport, false);
90bb6bd3 2483
9d1a50a2 2484 uart_resume_port(&imx_uart_uart_driver, &sport->port);
81b289cc 2485 enable_irq(sport->port.irq);
90bb6bd3 2486
09df0b34 2487 clk_disable_unprepare(sport->clk_ipg);
29add68d 2488
90bb6bd3
SW		 2489 return 0;
2490}
2491
9d1a50a2 2492static int imx_uart_freeze(struct device *dev)
94be6d74 2493{
a406c4b8 2494 struct imx_port *sport = dev_get_drvdata(dev);
94be6d74 2495
9d1a50a2 2496 uart_suspend_port(&imx_uart_uart_driver, &sport->port);
94be6d74 2497
09df0b34 2498 return clk_prepare_enable(sport->clk_ipg);
94be6d74
PZ		 2499}
2500
9d1a50a2 2501static int imx_uart_thaw(struct device *dev)
94be6d74 2502{
a406c4b8 2503 struct imx_port *sport = dev_get_drvdata(dev);
94be6d74 2504
9d1a50a2 2505 uart_resume_port(&imx_uart_uart_driver, &sport->port);
94be6d74 2506
09df0b34 2507 clk_disable_unprepare(sport->clk_ipg);
94be6d74
PZ		 2508
2509 return 0;
2510}
2511
9d1a50a2
UKK		 2512static const struct dev_pm_ops imx_uart_pm_ops = {
2513 .suspend_noirq = imx_uart_suspend_noirq,
2514 .resume_noirq = imx_uart_resume_noirq,
2515 .freeze_noirq = imx_uart_suspend_noirq,
2516 .restore_noirq = imx_uart_resume_noirq,
2517 .suspend = imx_uart_suspend,
2518 .resume = imx_uart_resume,
2519 .freeze = imx_uart_freeze,
2520 .thaw = imx_uart_thaw,
2521 .restore = imx_uart_thaw,
90bb6bd3
SW		 2522};
2523
9d1a50a2
UKK		 2524static struct platform_driver imx_uart_platform_driver = {
2525 .probe = imx_uart_probe,
2526 .remove = imx_uart_remove,
1da177e4 2527
9d1a50a2
UKK		 2528 .id_table = imx_uart_devtype,
2529 .driver = {
2530 .name = "imx-uart",
22698aa2 2531 .of_match_table = imx_uart_dt_ids,
9d1a50a2 2532 .pm = &imx_uart_pm_ops,
3ae5eaec 2533 },
1da177e4
LT		 2534};
2535
9d1a50a2 2536static int __init imx_uart_init(void)
1da177e4 2537{
9d1a50a2 2538 int ret = uart_register_driver(&imx_uart_uart_driver);
1da177e4 2539
1da177e4
LT		 2540 if (ret)
2541 return ret;
2542
9d1a50a2 2543 ret = platform_driver_register(&imx_uart_platform_driver);
1da177e4 2544 if (ret != 0)
9d1a50a2 2545 uart_unregister_driver(&imx_uart_uart_driver);
1da177e4 2546
f227824e 2547 return ret;
1da177e4
LT		 2548}
2549
9d1a50a2 2550static void __exit imx_uart_exit(void)
1da177e4 2551{
9d1a50a2
UKK		 2552 platform_driver_unregister(&imx_uart_platform_driver);
2553 uart_unregister_driver(&imx_uart_uart_driver);
1da177e4
LT		 2554}
2555
9d1a50a2
UKK		 2556module_init(imx_uart_init);
2557module_exit(imx_uart_exit);
1da177e4
LT		 2558
2559MODULE_AUTHOR("Sascha Hauer");
2560MODULE_DESCRIPTION("IMX generic serial port driver");
2561MODULE_LICENSE("GPL");
e169c139 2562MODULE_ALIAS("platform:imx-uart");
Linux 6.x block layer and io_uring tree(s)