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tty: serial: fsl_lpuart: support suspend/resume
[linux-2.6-block.git] / drivers / tty / serial / fsl_lpuart.c
CommitLineData
c9e2e946
JL		 1/*
2 * Freescale lpuart serial port driver
3 *
380c966c 4 * Copyright 2012-2014 Freescale Semiconductor, Inc.
c9e2e946
JL		 5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 */
11
12#if defined(CONFIG_SERIAL_FSL_LPUART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
13#define SUPPORT_SYSRQ
14#endif
15
f1cd8c87
YY		 16#include <linux/clk.h>
17#include <linux/console.h>
18#include <linux/dma-mapping.h>
19#include <linux/dmaengine.h>
20#include <linux/dmapool.h>
c9e2e946
JL		 21#include <linux/io.h>
22#include <linux/irq.h>
f1cd8c87 23#include <linux/module.h>
c9e2e946
JL		 24#include <linux/of.h>
25#include <linux/of_device.h>
f1cd8c87 26#include <linux/of_dma.h>
c9e2e946 27#include <linux/serial_core.h>
f1cd8c87 28#include <linux/slab.h>
c9e2e946
JL		 29#include <linux/tty_flip.h>
30
31/* All registers are 8-bit width */
32#define UARTBDH 0x00
33#define UARTBDL 0x01
34#define UARTCR1 0x02
35#define UARTCR2 0x03
36#define UARTSR1 0x04
37#define UARTCR3 0x06
38#define UARTDR 0x07
39#define UARTCR4 0x0a
40#define UARTCR5 0x0b
41#define UARTMODEM 0x0d
42#define UARTPFIFO 0x10
43#define UARTCFIFO 0x11
44#define UARTSFIFO 0x12
45#define UARTTWFIFO 0x13
46#define UARTTCFIFO 0x14
47#define UARTRWFIFO 0x15
48
49#define UARTBDH_LBKDIE 0x80
50#define UARTBDH_RXEDGIE 0x40
51#define UARTBDH_SBR_MASK 0x1f
52
53#define UARTCR1_LOOPS 0x80
54#define UARTCR1_RSRC 0x20
55#define UARTCR1_M 0x10
56#define UARTCR1_WAKE 0x08
57#define UARTCR1_ILT 0x04
58#define UARTCR1_PE 0x02
59#define UARTCR1_PT 0x01
60
61#define UARTCR2_TIE 0x80
62#define UARTCR2_TCIE 0x40
63#define UARTCR2_RIE 0x20
64#define UARTCR2_ILIE 0x10
65#define UARTCR2_TE 0x08
66#define UARTCR2_RE 0x04
67#define UARTCR2_RWU 0x02
68#define UARTCR2_SBK 0x01
69
70#define UARTSR1_TDRE 0x80
71#define UARTSR1_TC 0x40
72#define UARTSR1_RDRF 0x20
73#define UARTSR1_IDLE 0x10
74#define UARTSR1_OR 0x08
75#define UARTSR1_NF 0x04
76#define UARTSR1_FE 0x02
77#define UARTSR1_PE 0x01
78
79#define UARTCR3_R8 0x80
80#define UARTCR3_T8 0x40
81#define UARTCR3_TXDIR 0x20
82#define UARTCR3_TXINV 0x10
83#define UARTCR3_ORIE 0x08
84#define UARTCR3_NEIE 0x04
85#define UARTCR3_FEIE 0x02
86#define UARTCR3_PEIE 0x01
87
88#define UARTCR4_MAEN1 0x80
89#define UARTCR4_MAEN2 0x40
90#define UARTCR4_M10 0x20
91#define UARTCR4_BRFA_MASK 0x1f
92#define UARTCR4_BRFA_OFF 0
93
94#define UARTCR5_TDMAS 0x80
95#define UARTCR5_RDMAS 0x20
96
97#define UARTMODEM_RXRTSE 0x08
98#define UARTMODEM_TXRTSPOL 0x04
99#define UARTMODEM_TXRTSE 0x02
100#define UARTMODEM_TXCTSE 0x01
101
102#define UARTPFIFO_TXFE 0x80
103#define UARTPFIFO_FIFOSIZE_MASK 0x7
104#define UARTPFIFO_TXSIZE_OFF 4
105#define UARTPFIFO_RXFE 0x08
106#define UARTPFIFO_RXSIZE_OFF 0
107
108#define UARTCFIFO_TXFLUSH 0x80
109#define UARTCFIFO_RXFLUSH 0x40
110#define UARTCFIFO_RXOFE 0x04
111#define UARTCFIFO_TXOFE 0x02
112#define UARTCFIFO_RXUFE 0x01
113
114#define UARTSFIFO_TXEMPT 0x80
115#define UARTSFIFO_RXEMPT 0x40
116#define UARTSFIFO_RXOF 0x04
117#define UARTSFIFO_TXOF 0x02
118#define UARTSFIFO_RXUF 0x01
119
380c966c
JL		 120/* 32-bit register defination */
121#define UARTBAUD 0x00
122#define UARTSTAT 0x04
123#define UARTCTRL 0x08
124#define UARTDATA 0x0C
125#define UARTMATCH 0x10
126#define UARTMODIR 0x14
127#define UARTFIFO 0x18
128#define UARTWATER 0x1c
129
130#define UARTBAUD_MAEN1 0x80000000
131#define UARTBAUD_MAEN2 0x40000000
132#define UARTBAUD_M10 0x20000000
133#define UARTBAUD_TDMAE 0x00800000
134#define UARTBAUD_RDMAE 0x00200000
135#define UARTBAUD_MATCFG 0x00400000
136#define UARTBAUD_BOTHEDGE 0x00020000
137#define UARTBAUD_RESYNCDIS 0x00010000
138#define UARTBAUD_LBKDIE 0x00008000
139#define UARTBAUD_RXEDGIE 0x00004000
140#define UARTBAUD_SBNS 0x00002000
141#define UARTBAUD_SBR 0x00000000
142#define UARTBAUD_SBR_MASK 0x1fff
143
144#define UARTSTAT_LBKDIF 0x80000000
145#define UARTSTAT_RXEDGIF 0x40000000
146#define UARTSTAT_MSBF 0x20000000
147#define UARTSTAT_RXINV 0x10000000
148#define UARTSTAT_RWUID 0x08000000
149#define UARTSTAT_BRK13 0x04000000
150#define UARTSTAT_LBKDE 0x02000000
151#define UARTSTAT_RAF 0x01000000
152#define UARTSTAT_TDRE 0x00800000
153#define UARTSTAT_TC 0x00400000
154#define UARTSTAT_RDRF 0x00200000
155#define UARTSTAT_IDLE 0x00100000
156#define UARTSTAT_OR 0x00080000
157#define UARTSTAT_NF 0x00040000
158#define UARTSTAT_FE 0x00020000
159#define UARTSTAT_PE 0x00010000
160#define UARTSTAT_MA1F 0x00008000
161#define UARTSTAT_M21F 0x00004000
162
163#define UARTCTRL_R8T9 0x80000000
164#define UARTCTRL_R9T8 0x40000000
165#define UARTCTRL_TXDIR 0x20000000
166#define UARTCTRL_TXINV 0x10000000
167#define UARTCTRL_ORIE 0x08000000
168#define UARTCTRL_NEIE 0x04000000
169#define UARTCTRL_FEIE 0x02000000
170#define UARTCTRL_PEIE 0x01000000
171#define UARTCTRL_TIE 0x00800000
172#define UARTCTRL_TCIE 0x00400000
173#define UARTCTRL_RIE 0x00200000
174#define UARTCTRL_ILIE 0x00100000
175#define UARTCTRL_TE 0x00080000
176#define UARTCTRL_RE 0x00040000
177#define UARTCTRL_RWU 0x00020000
178#define UARTCTRL_SBK 0x00010000
179#define UARTCTRL_MA1IE 0x00008000
180#define UARTCTRL_MA2IE 0x00004000
181#define UARTCTRL_IDLECFG 0x00000100
182#define UARTCTRL_LOOPS 0x00000080
183#define UARTCTRL_DOZEEN 0x00000040
184#define UARTCTRL_RSRC 0x00000020
185#define UARTCTRL_M 0x00000010
186#define UARTCTRL_WAKE 0x00000008
187#define UARTCTRL_ILT 0x00000004
188#define UARTCTRL_PE 0x00000002
189#define UARTCTRL_PT 0x00000001
190
191#define UARTDATA_NOISY 0x00008000
192#define UARTDATA_PARITYE 0x00004000
193#define UARTDATA_FRETSC 0x00002000
194#define UARTDATA_RXEMPT 0x00001000
195#define UARTDATA_IDLINE 0x00000800
196#define UARTDATA_MASK 0x3ff
197
198#define UARTMODIR_IREN 0x00020000
199#define UARTMODIR_TXCTSSRC 0x00000020
200#define UARTMODIR_TXCTSC 0x00000010
201#define UARTMODIR_RXRTSE 0x00000008
202#define UARTMODIR_TXRTSPOL 0x00000004
203#define UARTMODIR_TXRTSE 0x00000002
204#define UARTMODIR_TXCTSE 0x00000001
205
206#define UARTFIFO_TXEMPT 0x00800000
207#define UARTFIFO_RXEMPT 0x00400000
208#define UARTFIFO_TXOF 0x00020000
209#define UARTFIFO_RXUF 0x00010000
210#define UARTFIFO_TXFLUSH 0x00008000
211#define UARTFIFO_RXFLUSH 0x00004000
212#define UARTFIFO_TXOFE 0x00000200
213#define UARTFIFO_RXUFE 0x00000100
214#define UARTFIFO_TXFE 0x00000080
215#define UARTFIFO_FIFOSIZE_MASK 0x7
216#define UARTFIFO_TXSIZE_OFF 4
217#define UARTFIFO_RXFE 0x00000008
218#define UARTFIFO_RXSIZE_OFF 0
219
220#define UARTWATER_COUNT_MASK 0xff
221#define UARTWATER_TXCNT_OFF 8
222#define UARTWATER_RXCNT_OFF 24
223#define UARTWATER_WATER_MASK 0xff
224#define UARTWATER_TXWATER_OFF 0
225#define UARTWATER_RXWATER_OFF 16
226
f1cd8c87
YY		 227#define FSL_UART_RX_DMA_BUFFER_SIZE 64
228
c9e2e946
JL		 229#define DRIVER_NAME "fsl-lpuart"
230#define DEV_NAME "ttyLP"
231#define UART_NR 6
232
233struct lpuart_port {
234 struct uart_port port;
235 struct clk *clk;
236 unsigned int txfifo_size;
237 unsigned int rxfifo_size;
380c966c 238 bool lpuart32;
f1cd8c87 239
4a818c43
SA		 240 bool lpuart_dma_tx_use;
241 bool lpuart_dma_rx_use;
f1cd8c87
YY		 242 struct dma_chan *dma_tx_chan;
243 struct dma_chan *dma_rx_chan;
244 struct dma_async_tx_descriptor *dma_tx_desc;
245 struct dma_async_tx_descriptor *dma_rx_desc;
246 dma_addr_t dma_tx_buf_bus;
247 dma_addr_t dma_rx_buf_bus;
248 dma_cookie_t dma_tx_cookie;
249 dma_cookie_t dma_rx_cookie;
250 unsigned char *dma_tx_buf_virt;
251 unsigned char *dma_rx_buf_virt;
252 unsigned int dma_tx_bytes;
253 unsigned int dma_rx_bytes;
254 int dma_tx_in_progress;
255 int dma_rx_in_progress;
256 unsigned int dma_rx_timeout;
257 struct timer_list lpuart_timer;
c9e2e946
JL		 258};
259
ed0bb232 260static const struct of_device_id lpuart_dt_ids[] = {
c9e2e946
JL		 261 {
262 .compatible = "fsl,vf610-lpuart",
263 },
380c966c
JL		 264 {
265 .compatible = "fsl,ls1021a-lpuart",
266 },
c9e2e946
JL		 267 { /* sentinel */ }
268};
269MODULE_DEVICE_TABLE(of, lpuart_dt_ids);
270
f1cd8c87
YY		 271/* Forward declare this for the dma callbacks*/
272static void lpuart_dma_tx_complete(void *arg);
273static void lpuart_dma_rx_complete(void *arg);
274
380c966c
JL		 275static u32 lpuart32_read(void __iomem *addr)
276{
277 return ioread32be(addr);
278}
279
280static void lpuart32_write(u32 val, void __iomem *addr)
281{
282 iowrite32be(val, addr);
283}
284
c9e2e946
JL		 285static void lpuart_stop_tx(struct uart_port *port)
286{
287 unsigned char temp;
288
289 temp = readb(port->membase + UARTCR2);
290 temp &= ~(UARTCR2_TIE | UARTCR2_TCIE);
291 writeb(temp, port->membase + UARTCR2);
292}
293
380c966c
JL		 294static void lpuart32_stop_tx(struct uart_port *port)
295{
296 unsigned long temp;
297
298 temp = lpuart32_read(port->membase + UARTCTRL);
299 temp &= ~(UARTCTRL_TIE | UARTCTRL_TCIE);
300 lpuart32_write(temp, port->membase + UARTCTRL);
301}
302
c9e2e946
JL		 303static void lpuart_stop_rx(struct uart_port *port)
304{
305 unsigned char temp;
306
307 temp = readb(port->membase + UARTCR2);
308 writeb(temp & ~UARTCR2_RE, port->membase + UARTCR2);
309}
310
380c966c
JL		 311static void lpuart32_stop_rx(struct uart_port *port)
312{
313 unsigned long temp;
314
315 temp = lpuart32_read(port->membase + UARTCTRL);
316 lpuart32_write(temp & ~UARTCTRL_RE, port->membase + UARTCTRL);
317}
318
f1cd8c87
YY		 319static void lpuart_copy_rx_to_tty(struct lpuart_port *sport,
320 struct tty_port *tty, int count)
321{
322 int copied;
323
324 sport->port.icount.rx += count;
325
326 if (!tty) {
327 dev_err(sport->port.dev, "No tty port\n");
328 return;
329 }
330
331 dma_sync_single_for_cpu(sport->port.dev, sport->dma_rx_buf_bus,
332 FSL_UART_RX_DMA_BUFFER_SIZE, DMA_FROM_DEVICE);
333 copied = tty_insert_flip_string(tty,
334 ((unsigned char *)(sport->dma_rx_buf_virt)), count);
335
336 if (copied != count) {
337 WARN_ON(1);
338 dev_err(sport->port.dev, "RxData copy to tty layer failed\n");
339 }
340
341 dma_sync_single_for_device(sport->port.dev, sport->dma_rx_buf_bus,
342 FSL_UART_RX_DMA_BUFFER_SIZE, DMA_TO_DEVICE);
343}
344
345static void lpuart_pio_tx(struct lpuart_port *sport)
346{
347 struct circ_buf *xmit = &sport->port.state->xmit;
348 unsigned long flags;
349
350 spin_lock_irqsave(&sport->port.lock, flags);
351
352 while (!uart_circ_empty(xmit) &&
353 readb(sport->port.membase + UARTTCFIFO) < sport->txfifo_size) {
354 writeb(xmit->buf[xmit->tail], sport->port.membase + UARTDR);
355 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
356 sport->port.icount.tx++;
357 }
358
359 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
360 uart_write_wakeup(&sport->port);
361
362 if (uart_circ_empty(xmit))
363 writeb(readb(sport->port.membase + UARTCR5) | UARTCR5_TDMAS,
364 sport->port.membase + UARTCR5);
365
366 spin_unlock_irqrestore(&sport->port.lock, flags);
367}
368
369static int lpuart_dma_tx(struct lpuart_port *sport, unsigned long count)
370{
371 struct circ_buf *xmit = &sport->port.state->xmit;
372 dma_addr_t tx_bus_addr;
373
374 dma_sync_single_for_device(sport->port.dev, sport->dma_tx_buf_bus,
375 UART_XMIT_SIZE, DMA_TO_DEVICE);
ed9891bf 376 sport->dma_tx_bytes = count & ~(sport->txfifo_size - 1);
f1cd8c87
YY		 377 tx_bus_addr = sport->dma_tx_buf_bus + xmit->tail;
378 sport->dma_tx_desc = dmaengine_prep_slave_single(sport->dma_tx_chan,
379 tx_bus_addr, sport->dma_tx_bytes,
380 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
381
382 if (!sport->dma_tx_desc) {
383 dev_err(sport->port.dev, "Not able to get desc for tx\n");
384 return -EIO;
385 }
386
387 sport->dma_tx_desc->callback = lpuart_dma_tx_complete;
388 sport->dma_tx_desc->callback_param = sport;
389 sport->dma_tx_in_progress = 1;
390 sport->dma_tx_cookie = dmaengine_submit(sport->dma_tx_desc);
391 dma_async_issue_pending(sport->dma_tx_chan);
392
393 return 0;
394}
395
396static void lpuart_prepare_tx(struct lpuart_port *sport)
397{
398 struct circ_buf *xmit = &sport->port.state->xmit;
399 unsigned long count = CIRC_CNT_TO_END(xmit->head,
400 xmit->tail, UART_XMIT_SIZE);
401
402 if (!count)
403 return;
404
ed9891bf 405 if (count < sport->txfifo_size)
f1cd8c87
YY		 406 writeb(readb(sport->port.membase + UARTCR5) & ~UARTCR5_TDMAS,
407 sport->port.membase + UARTCR5);
408 else {
409 writeb(readb(sport->port.membase + UARTCR5) | UARTCR5_TDMAS,
410 sport->port.membase + UARTCR5);
411 lpuart_dma_tx(sport, count);
412 }
413}
414
415static void lpuart_dma_tx_complete(void *arg)
416{
417 struct lpuart_port *sport = arg;
418 struct circ_buf *xmit = &sport->port.state->xmit;
419 unsigned long flags;
420
421 async_tx_ack(sport->dma_tx_desc);
422
423 spin_lock_irqsave(&sport->port.lock, flags);
424
425 xmit->tail = (xmit->tail + sport->dma_tx_bytes) & (UART_XMIT_SIZE - 1);
426 sport->dma_tx_in_progress = 0;
427
428 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
429 uart_write_wakeup(&sport->port);
430
431 lpuart_prepare_tx(sport);
432
433 spin_unlock_irqrestore(&sport->port.lock, flags);
434}
435
436static int lpuart_dma_rx(struct lpuart_port *sport)
437{
438 dma_sync_single_for_device(sport->port.dev, sport->dma_rx_buf_bus,
439 FSL_UART_RX_DMA_BUFFER_SIZE, DMA_TO_DEVICE);
440 sport->dma_rx_desc = dmaengine_prep_slave_single(sport->dma_rx_chan,
441 sport->dma_rx_buf_bus, FSL_UART_RX_DMA_BUFFER_SIZE,
442 DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT);
443
444 if (!sport->dma_rx_desc) {
445 dev_err(sport->port.dev, "Not able to get desc for rx\n");
446 return -EIO;
447 }
448
449 sport->dma_rx_desc->callback = lpuart_dma_rx_complete;
450 sport->dma_rx_desc->callback_param = sport;
451 sport->dma_rx_in_progress = 1;
452 sport->dma_rx_cookie = dmaengine_submit(sport->dma_rx_desc);
453 dma_async_issue_pending(sport->dma_rx_chan);
454
455 return 0;
456}
457
bfc2e07f
SA		 458static void lpuart_flush_buffer(struct uart_port *port)
459{
460 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
461 if (sport->lpuart_dma_tx_use) {
462 dmaengine_terminate_all(sport->dma_tx_chan);
463 sport->dma_tx_in_progress = 0;
464 }
465}
466
f1cd8c87
YY		 467static void lpuart_dma_rx_complete(void *arg)
468{
469 struct lpuart_port *sport = arg;
470 struct tty_port *port = &sport->port.state->port;
471 unsigned long flags;
472
473 async_tx_ack(sport->dma_rx_desc);
011f5bde 474 mod_timer(&sport->lpuart_timer, jiffies + sport->dma_rx_timeout);
f1cd8c87
YY		 475
476 spin_lock_irqsave(&sport->port.lock, flags);
477
478 sport->dma_rx_in_progress = 0;
479 lpuart_copy_rx_to_tty(sport, port, FSL_UART_RX_DMA_BUFFER_SIZE);
480 tty_flip_buffer_push(port);
481 lpuart_dma_rx(sport);
482
483 spin_unlock_irqrestore(&sport->port.lock, flags);
484}
485
d6b0d2f2 486static void lpuart_dma_rx_terminate(struct lpuart_port *sport)
f1cd8c87 487{
f1cd8c87
YY		 488 struct tty_port *port = &sport->port.state->port;
489 struct dma_tx_state state;
490 unsigned long flags;
491 unsigned char temp;
492 int count;
493
494 del_timer(&sport->lpuart_timer);
495 dmaengine_pause(sport->dma_rx_chan);
496 dmaengine_tx_status(sport->dma_rx_chan, sport->dma_rx_cookie, &state);
497 dmaengine_terminate_all(sport->dma_rx_chan);
498 count = FSL_UART_RX_DMA_BUFFER_SIZE - state.residue;
499 async_tx_ack(sport->dma_rx_desc);
500
501 spin_lock_irqsave(&sport->port.lock, flags);
502
503 sport->dma_rx_in_progress = 0;
504 lpuart_copy_rx_to_tty(sport, port, count);
505 tty_flip_buffer_push(port);
506 temp = readb(sport->port.membase + UARTCR5);
507 writeb(temp & ~UARTCR5_RDMAS, sport->port.membase + UARTCR5);
508
509 spin_unlock_irqrestore(&sport->port.lock, flags);
510}
511
d6b0d2f2
SA		 512static void lpuart_timer_func(unsigned long data)
513{
514 lpuart_dma_rx_terminate((struct lpuart_port *)data);
515}
516
f1cd8c87
YY		 517static inline void lpuart_prepare_rx(struct lpuart_port *sport)
518{
519 unsigned long flags;
520 unsigned char temp;
521
522 spin_lock_irqsave(&sport->port.lock, flags);
523
f1cd8c87
YY		 524 sport->lpuart_timer.expires = jiffies + sport->dma_rx_timeout;
525 add_timer(&sport->lpuart_timer);
526
527 lpuart_dma_rx(sport);
528 temp = readb(sport->port.membase + UARTCR5);
529 writeb(temp | UARTCR5_RDMAS, sport->port.membase + UARTCR5);
530
531 spin_unlock_irqrestore(&sport->port.lock, flags);
532}
533
c9e2e946
JL		 534static inline void lpuart_transmit_buffer(struct lpuart_port *sport)
535{
536 struct circ_buf *xmit = &sport->port.state->xmit;
537
538 while (!uart_circ_empty(xmit) &&
539 (readb(sport->port.membase + UARTTCFIFO) < sport->txfifo_size)) {
540 writeb(xmit->buf[xmit->tail], sport->port.membase + UARTDR);
541 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
542 sport->port.icount.tx++;
543 }
544
545 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
546 uart_write_wakeup(&sport->port);
547
548 if (uart_circ_empty(xmit))
549 lpuart_stop_tx(&sport->port);
550}
551
380c966c
JL		 552static inline void lpuart32_transmit_buffer(struct lpuart_port *sport)
553{
554 struct circ_buf *xmit = &sport->port.state->xmit;
555 unsigned long txcnt;
556
557 txcnt = lpuart32_read(sport->port.membase + UARTWATER);
558 txcnt = txcnt >> UARTWATER_TXCNT_OFF;
559 txcnt &= UARTWATER_COUNT_MASK;
560 while (!uart_circ_empty(xmit) && (txcnt < sport->txfifo_size)) {
561 lpuart32_write(xmit->buf[xmit->tail], sport->port.membase + UARTDATA);
562 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
563 sport->port.icount.tx++;
564 txcnt = lpuart32_read(sport->port.membase + UARTWATER);
565 txcnt = txcnt >> UARTWATER_TXCNT_OFF;
566 txcnt &= UARTWATER_COUNT_MASK;
567 }
568
569 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
570 uart_write_wakeup(&sport->port);
571
572 if (uart_circ_empty(xmit))
573 lpuart32_stop_tx(&sport->port);
574}
575
c9e2e946
JL		 576static void lpuart_start_tx(struct uart_port *port)
577{
f1cd8c87
YY		 578 struct lpuart_port *sport = container_of(port,
579 struct lpuart_port, port);
580 struct circ_buf *xmit = &sport->port.state->xmit;
c9e2e946
JL		 581 unsigned char temp;
582
583 temp = readb(port->membase + UARTCR2);
584 writeb(temp | UARTCR2_TIE, port->membase + UARTCR2);
585
4a818c43 586 if (sport->lpuart_dma_tx_use) {
f1cd8c87
YY		 587 if (!uart_circ_empty(xmit) && !sport->dma_tx_in_progress)
588 lpuart_prepare_tx(sport);
589 } else {
590 if (readb(port->membase + UARTSR1) & UARTSR1_TDRE)
591 lpuart_transmit_buffer(sport);
592 }
c9e2e946
JL		 593}
594
380c966c
JL		 595static void lpuart32_start_tx(struct uart_port *port)
596{
597 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
598 unsigned long temp;
599
600 temp = lpuart32_read(port->membase + UARTCTRL);
601 lpuart32_write(temp | UARTCTRL_TIE, port->membase + UARTCTRL);
602
603 if (lpuart32_read(port->membase + UARTSTAT) & UARTSTAT_TDRE)
604 lpuart32_transmit_buffer(sport);
605}
606
c9e2e946
JL		 607static irqreturn_t lpuart_txint(int irq, void *dev_id)
608{
609 struct lpuart_port *sport = dev_id;
610 struct circ_buf *xmit = &sport->port.state->xmit;
611 unsigned long flags;
612
613 spin_lock_irqsave(&sport->port.lock, flags);
614 if (sport->port.x_char) {
380c966c
JL		 615 if (sport->lpuart32)
616 lpuart32_write(sport->port.x_char, sport->port.membase + UARTDATA);
617 else
618 writeb(sport->port.x_char, sport->port.membase + UARTDR);
c9e2e946
JL		 619 goto out;
620 }
621
622 if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) {
380c966c
JL		 623 if (sport->lpuart32)
624 lpuart32_stop_tx(&sport->port);
625 else
626 lpuart_stop_tx(&sport->port);
c9e2e946
JL		 627 goto out;
628 }
629
380c966c
JL		 630 if (sport->lpuart32)
631 lpuart32_transmit_buffer(sport);
632 else
633 lpuart_transmit_buffer(sport);
c9e2e946
JL		 634
635 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
636 uart_write_wakeup(&sport->port);
637
638out:
639 spin_unlock_irqrestore(&sport->port.lock, flags);
640 return IRQ_HANDLED;
641}
642
643static irqreturn_t lpuart_rxint(int irq, void *dev_id)
644{
645 struct lpuart_port *sport = dev_id;
646 unsigned int flg, ignored = 0;
647 struct tty_port *port = &sport->port.state->port;
648 unsigned long flags;
649 unsigned char rx, sr;
650
651 spin_lock_irqsave(&sport->port.lock, flags);
652
653 while (!(readb(sport->port.membase + UARTSFIFO) & UARTSFIFO_RXEMPT)) {
654 flg = TTY_NORMAL;
655 sport->port.icount.rx++;
656 /*
657 * to clear the FE, OR, NF, FE, PE flags,
658 * read SR1 then read DR
659 */
660 sr = readb(sport->port.membase + UARTSR1);
661 rx = readb(sport->port.membase + UARTDR);
662
663 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx))
664 continue;
665
666 if (sr & (UARTSR1_PE | UARTSR1_OR | UARTSR1_FE)) {
667 if (sr & UARTSR1_PE)
668 sport->port.icount.parity++;
669 else if (sr & UARTSR1_FE)
670 sport->port.icount.frame++;
671
672 if (sr & UARTSR1_OR)
673 sport->port.icount.overrun++;
674
675 if (sr & sport->port.ignore_status_mask) {
676 if (++ignored > 100)
677 goto out;
678 continue;
679 }
680
681 sr &= sport->port.read_status_mask;
682
683 if (sr & UARTSR1_PE)
684 flg = TTY_PARITY;
685 else if (sr & UARTSR1_FE)
686 flg = TTY_FRAME;
687
688 if (sr & UARTSR1_OR)
689 flg = TTY_OVERRUN;
690
691#ifdef SUPPORT_SYSRQ
692 sport->port.sysrq = 0;
693#endif
694 }
695
696 tty_insert_flip_char(port, rx, flg);
697 }
698
699out:
700 spin_unlock_irqrestore(&sport->port.lock, flags);
701
702 tty_flip_buffer_push(port);
703 return IRQ_HANDLED;
704}
705
380c966c
JL		 706static irqreturn_t lpuart32_rxint(int irq, void *dev_id)
707{
708 struct lpuart_port *sport = dev_id;
709 unsigned int flg, ignored = 0;
710 struct tty_port *port = &sport->port.state->port;
711 unsigned long flags;
712 unsigned long rx, sr;
713
714 spin_lock_irqsave(&sport->port.lock, flags);
715
716 while (!(lpuart32_read(sport->port.membase + UARTFIFO) & UARTFIFO_RXEMPT)) {
717 flg = TTY_NORMAL;
718 sport->port.icount.rx++;
719 /*
720 * to clear the FE, OR, NF, FE, PE flags,
721 * read STAT then read DATA reg
722 */
723 sr = lpuart32_read(sport->port.membase + UARTSTAT);
724 rx = lpuart32_read(sport->port.membase + UARTDATA);
725 rx &= 0x3ff;
726
727 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx))
728 continue;
729
730 if (sr & (UARTSTAT_PE | UARTSTAT_OR | UARTSTAT_FE)) {
731 if (sr & UARTSTAT_PE)
732 sport->port.icount.parity++;
733 else if (sr & UARTSTAT_FE)
734 sport->port.icount.frame++;
735
736 if (sr & UARTSTAT_OR)
737 sport->port.icount.overrun++;
738
739 if (sr & sport->port.ignore_status_mask) {
740 if (++ignored > 100)
741 goto out;
742 continue;
743 }
744
745 sr &= sport->port.read_status_mask;
746
747 if (sr & UARTSTAT_PE)
748 flg = TTY_PARITY;
749 else if (sr & UARTSTAT_FE)
750 flg = TTY_FRAME;
751
752 if (sr & UARTSTAT_OR)
753 flg = TTY_OVERRUN;
754
755#ifdef SUPPORT_SYSRQ
756 sport->port.sysrq = 0;
757#endif
758 }
759
760 tty_insert_flip_char(port, rx, flg);
761 }
762
763out:
764 spin_unlock_irqrestore(&sport->port.lock, flags);
765
766 tty_flip_buffer_push(port);
767 return IRQ_HANDLED;
768}
769
c9e2e946
JL		 770static irqreturn_t lpuart_int(int irq, void *dev_id)
771{
772 struct lpuart_port *sport = dev_id;
5f1437f6 773 unsigned char sts, crdma;
c9e2e946
JL		 774
775 sts = readb(sport->port.membase + UARTSR1);
5f1437f6 776 crdma = readb(sport->port.membase + UARTCR5);
c9e2e946 777
5f1437f6 778 if (sts & UARTSR1_RDRF && !(crdma & UARTCR5_RDMAS)) {
4a818c43 779 if (sport->lpuart_dma_rx_use)
f1cd8c87
YY		 780 lpuart_prepare_rx(sport);
781 else
782 lpuart_rxint(irq, dev_id);
783 }
5f1437f6 784 if (sts & UARTSR1_TDRE && !(crdma & UARTCR5_TDMAS)) {
4a818c43 785 if (sport->lpuart_dma_tx_use)
f1cd8c87
YY		 786 lpuart_pio_tx(sport);
787 else
788 lpuart_txint(irq, dev_id);
789 }
c9e2e946
JL		 790
791 return IRQ_HANDLED;
792}
793
380c966c
JL		 794static irqreturn_t lpuart32_int(int irq, void *dev_id)
795{
796 struct lpuart_port *sport = dev_id;
797 unsigned long sts, rxcount;
798
799 sts = lpuart32_read(sport->port.membase + UARTSTAT);
800 rxcount = lpuart32_read(sport->port.membase + UARTWATER);
801 rxcount = rxcount >> UARTWATER_RXCNT_OFF;
802
803 if (sts & UARTSTAT_RDRF || rxcount > 0)
804 lpuart32_rxint(irq, dev_id);
805
806 if ((sts & UARTSTAT_TDRE) &&
807 !(lpuart32_read(sport->port.membase + UARTBAUD) & UARTBAUD_TDMAE))
808 lpuart_txint(irq, dev_id);
809
810 lpuart32_write(sts, sport->port.membase + UARTSTAT);
811 return IRQ_HANDLED;
812}
813
c9e2e946
JL		 814/* return TIOCSER_TEMT when transmitter is not busy */
815static unsigned int lpuart_tx_empty(struct uart_port *port)
816{
b70b6361
SA		 817 struct lpuart_port *sport = container_of(port,
818 struct lpuart_port, port);
819 unsigned char sr1 = readb(port->membase + UARTSR1);
820 unsigned char sfifo = readb(port->membase + UARTSFIFO);
821
822 if (sport->dma_tx_in_progress)
823 return 0;
824
825 if (sr1 & UARTSR1_TC && sfifo & UARTSFIFO_TXEMPT)
826 return TIOCSER_TEMT;
827
828 return 0;
c9e2e946
JL		 829}
830
380c966c
JL		 831static unsigned int lpuart32_tx_empty(struct uart_port *port)
832{
833 return (lpuart32_read(port->membase + UARTSTAT) & UARTSTAT_TC) ?
834 TIOCSER_TEMT : 0;
835}
836
c9e2e946
JL		 837static unsigned int lpuart_get_mctrl(struct uart_port *port)
838{
839 unsigned int temp = 0;
840 unsigned char reg;
841
842 reg = readb(port->membase + UARTMODEM);
843 if (reg & UARTMODEM_TXCTSE)
844 temp |= TIOCM_CTS;
845
846 if (reg & UARTMODEM_RXRTSE)
847 temp |= TIOCM_RTS;
848
849 return temp;
850}
851
380c966c
JL		 852static unsigned int lpuart32_get_mctrl(struct uart_port *port)
853{
854 unsigned int temp = 0;
855 unsigned long reg;
856
857 reg = lpuart32_read(port->membase + UARTMODIR);
858 if (reg & UARTMODIR_TXCTSE)
859 temp |= TIOCM_CTS;
860
861 if (reg & UARTMODIR_RXRTSE)
862 temp |= TIOCM_RTS;
863
864 return temp;
865}
866
c9e2e946
JL		 867static void lpuart_set_mctrl(struct uart_port *port, unsigned int mctrl)
868{
869 unsigned char temp;
870
871 temp = readb(port->membase + UARTMODEM) &
872 ~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE);
873
874 if (mctrl & TIOCM_RTS)
875 temp |= UARTMODEM_RXRTSE;
876
877 if (mctrl & TIOCM_CTS)
878 temp |= UARTMODEM_TXCTSE;
879
880 writeb(temp, port->membase + UARTMODEM);
881}
882
380c966c
JL		 883static void lpuart32_set_mctrl(struct uart_port *port, unsigned int mctrl)
884{
885 unsigned long temp;
886
887 temp = lpuart32_read(port->membase + UARTMODIR) &
888 ~(UARTMODIR_RXRTSE | UARTMODIR_TXCTSE);
889
890 if (mctrl & TIOCM_RTS)
891 temp |= UARTMODIR_RXRTSE;
892
893 if (mctrl & TIOCM_CTS)
894 temp |= UARTMODIR_TXCTSE;
895
896 lpuart32_write(temp, port->membase + UARTMODIR);
897}
898
c9e2e946
JL		 899static void lpuart_break_ctl(struct uart_port *port, int break_state)
900{
901 unsigned char temp;
902
903 temp = readb(port->membase + UARTCR2) & ~UARTCR2_SBK;
904
905 if (break_state != 0)
906 temp |= UARTCR2_SBK;
907
908 writeb(temp, port->membase + UARTCR2);
909}
910
380c966c
JL		 911static void lpuart32_break_ctl(struct uart_port *port, int break_state)
912{
913 unsigned long temp;
914
915 temp = lpuart32_read(port->membase + UARTCTRL) & ~UARTCTRL_SBK;
916
917 if (break_state != 0)
918 temp |= UARTCTRL_SBK;
919
920 lpuart32_write(temp, port->membase + UARTCTRL);
921}
922
c9e2e946
JL		 923static void lpuart_setup_watermark(struct lpuart_port *sport)
924{
925 unsigned char val, cr2;
bc764b8f 926 unsigned char cr2_saved;
c9e2e946
JL		 927
928 cr2 = readb(sport->port.membase + UARTCR2);
bc764b8f 929 cr2_saved = cr2;
c9e2e946
JL		 930 cr2 &= ~(UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_TE |
931 UARTCR2_RIE | UARTCR2_RE);
932 writeb(cr2, sport->port.membase + UARTCR2);
933
c9e2e946 934 val = readb(sport->port.membase + UARTPFIFO);
c9e2e946
JL		 935 writeb(val | UARTPFIFO_TXFE | UARTPFIFO_RXFE,
936 sport->port.membase + UARTPFIFO);
937
8e4934c6
SA		 938 /* explicitly clear RDRF */
939 readb(sport->port.membase + UARTSR1);
940
c9e2e946
JL		 941 /* flush Tx and Rx FIFO */
942 writeb(UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH,
943 sport->port.membase + UARTCFIFO);
944
f1cd8c87 945 writeb(0, sport->port.membase + UARTTWFIFO);
c9e2e946 946 writeb(1, sport->port.membase + UARTRWFIFO);
bc764b8f
SG		 947
948 /* Restore cr2 */
949 writeb(cr2_saved, sport->port.membase + UARTCR2);
c9e2e946
JL		 950}
951
380c966c
JL		 952static void lpuart32_setup_watermark(struct lpuart_port *sport)
953{
954 unsigned long val, ctrl;
955 unsigned long ctrl_saved;
956
957 ctrl = lpuart32_read(sport->port.membase + UARTCTRL);
958 ctrl_saved = ctrl;
959 ctrl &= ~(UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_TE |
960 UARTCTRL_RIE | UARTCTRL_RE);
961 lpuart32_write(ctrl, sport->port.membase + UARTCTRL);
962
963 /* enable FIFO mode */
964 val = lpuart32_read(sport->port.membase + UARTFIFO);
965 val |= UARTFIFO_TXFE | UARTFIFO_RXFE;
966 val |= UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH;
967 lpuart32_write(val, sport->port.membase + UARTFIFO);
968
969 /* set the watermark */
970 val = (0x1 << UARTWATER_RXWATER_OFF) | (0x0 << UARTWATER_TXWATER_OFF);
971 lpuart32_write(val, sport->port.membase + UARTWATER);
972
973 /* Restore cr2 */
974 lpuart32_write(ctrl_saved, sport->port.membase + UARTCTRL);
975}
976
f1cd8c87
YY		 977static int lpuart_dma_tx_request(struct uart_port *port)
978{
979 struct lpuart_port *sport = container_of(port,
980 struct lpuart_port, port);
f1cd8c87
YY		 981 struct dma_slave_config dma_tx_sconfig;
982 dma_addr_t dma_bus;
983 unsigned char *dma_buf;
984 int ret;
985
4a818c43 986 dma_bus = dma_map_single(sport->dma_tx_chan->device->dev,
f1cd8c87
YY		 987 sport->port.state->xmit.buf,
988 UART_XMIT_SIZE, DMA_TO_DEVICE);
989
4a818c43 990 if (dma_mapping_error(sport->dma_tx_chan->device->dev, dma_bus)) {
f1cd8c87 991 dev_err(sport->port.dev, "dma_map_single tx failed\n");
f1cd8c87
YY		 992 return -ENOMEM;
993 }
994
995 dma_buf = sport->port.state->xmit.buf;
996 dma_tx_sconfig.dst_addr = sport->port.mapbase + UARTDR;
997 dma_tx_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
ed9891bf 998 dma_tx_sconfig.dst_maxburst = sport->txfifo_size;
f1cd8c87 999 dma_tx_sconfig.direction = DMA_MEM_TO_DEV;
4a818c43 1000 ret = dmaengine_slave_config(sport->dma_tx_chan, &dma_tx_sconfig);
f1cd8c87
YY		 1001
1002 if (ret < 0) {
1003 dev_err(sport->port.dev,
1004 "Dma slave config failed, err = %d\n", ret);
f1cd8c87
YY		 1005 return ret;
1006 }
1007
f1cd8c87
YY		 1008 sport->dma_tx_buf_virt = dma_buf;
1009 sport->dma_tx_buf_bus = dma_bus;
1010 sport->dma_tx_in_progress = 0;
1011
1012 return 0;
1013}
1014
1015static int lpuart_dma_rx_request(struct uart_port *port)
1016{
1017 struct lpuart_port *sport = container_of(port,
1018 struct lpuart_port, port);
f1cd8c87
YY		 1019 struct dma_slave_config dma_rx_sconfig;
1020 dma_addr_t dma_bus;
1021 unsigned char *dma_buf;
1022 int ret;
1023
f1cd8c87
YY		 1024 dma_buf = devm_kzalloc(sport->port.dev,
1025 FSL_UART_RX_DMA_BUFFER_SIZE, GFP_KERNEL);
1026
1027 if (!dma_buf) {
1028 dev_err(sport->port.dev, "Dma rx alloc failed\n");
f1cd8c87
YY		 1029 return -ENOMEM;
1030 }
1031
4a818c43 1032 dma_bus = dma_map_single(sport->dma_rx_chan->device->dev, dma_buf,
f1cd8c87
YY		 1033 FSL_UART_RX_DMA_BUFFER_SIZE, DMA_FROM_DEVICE);
1034
4a818c43 1035 if (dma_mapping_error(sport->dma_rx_chan->device->dev, dma_bus)) {
f1cd8c87 1036 dev_err(sport->port.dev, "dma_map_single rx failed\n");
f1cd8c87
YY		 1037 return -ENOMEM;
1038 }
1039
1040 dma_rx_sconfig.src_addr = sport->port.mapbase + UARTDR;
1041 dma_rx_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1042 dma_rx_sconfig.src_maxburst = 1;
1043 dma_rx_sconfig.direction = DMA_DEV_TO_MEM;
4a818c43 1044 ret = dmaengine_slave_config(sport->dma_rx_chan, &dma_rx_sconfig);
f1cd8c87
YY		 1045
1046 if (ret < 0) {
1047 dev_err(sport->port.dev,
1048 "Dma slave config failed, err = %d\n", ret);
f1cd8c87
YY		 1049 return ret;
1050 }
1051
f1cd8c87
YY		 1052 sport->dma_rx_buf_virt = dma_buf;
1053 sport->dma_rx_buf_bus = dma_bus;
1054 sport->dma_rx_in_progress = 0;
1055
f1cd8c87
YY		 1056 return 0;
1057}
1058
1059static void lpuart_dma_tx_free(struct uart_port *port)
1060{
1061 struct lpuart_port *sport = container_of(port,
1062 struct lpuart_port, port);
f1cd8c87
YY		 1063
1064 dma_unmap_single(sport->port.dev, sport->dma_tx_buf_bus,
1065 UART_XMIT_SIZE, DMA_TO_DEVICE);
4a818c43 1066
f1cd8c87
YY		 1067 sport->dma_tx_buf_bus = 0;
1068 sport->dma_tx_buf_virt = NULL;
f1cd8c87
YY		 1069}
1070
1071static void lpuart_dma_rx_free(struct uart_port *port)
1072{
1073 struct lpuart_port *sport = container_of(port,
1074 struct lpuart_port, port);
f1cd8c87
YY		 1075
1076 dma_unmap_single(sport->port.dev, sport->dma_rx_buf_bus,
1077 FSL_UART_RX_DMA_BUFFER_SIZE, DMA_FROM_DEVICE);
1078
f1cd8c87
YY		 1079 sport->dma_rx_buf_bus = 0;
1080 sport->dma_rx_buf_virt = NULL;
f1cd8c87
YY		 1081}
1082
c9e2e946
JL		 1083static int lpuart_startup(struct uart_port *port)
1084{
1085 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1086 int ret;
1087 unsigned long flags;
1088 unsigned char temp;
1089
ed9891bf
SA		 1090 /* determine FIFO size and enable FIFO mode */
1091 temp = readb(sport->port.membase + UARTPFIFO);
1092
1093 sport->txfifo_size = 0x1 << (((temp >> UARTPFIFO_TXSIZE_OFF) &
1094 UARTPFIFO_FIFOSIZE_MASK) + 1);
1095
4e8f2459
SA		 1096 sport->port.fifosize = sport->txfifo_size;
1097
ed9891bf
SA		 1098 sport->rxfifo_size = 0x1 << (((temp >> UARTPFIFO_RXSIZE_OFF) &
1099 UARTPFIFO_FIFOSIZE_MASK) + 1);
1100
4a818c43
SA		 1101 if (sport->dma_rx_chan && !lpuart_dma_rx_request(port)) {
1102 sport->lpuart_dma_rx_use = true;
4a8588a1
SA		 1103 setup_timer(&sport->lpuart_timer, lpuart_timer_func,
1104 (unsigned long)sport);
4a818c43
SA		 1105 } else
1106 sport->lpuart_dma_rx_use = false;
1107
1108
1109 if (sport->dma_tx_chan && !lpuart_dma_tx_request(port)) {
1110 sport->lpuart_dma_tx_use = true;
f1cd8c87 1111 temp = readb(port->membase + UARTCR5);
5f1437f6 1112 temp &= ~UARTCR5_RDMAS;
f1cd8c87 1113 writeb(temp | UARTCR5_TDMAS, port->membase + UARTCR5);
4a818c43
SA		 1114 } else
1115 sport->lpuart_dma_tx_use = false;
f1cd8c87 1116
c9e2e946
JL		 1117 ret = devm_request_irq(port->dev, port->irq, lpuart_int, 0,
1118 DRIVER_NAME, sport);
1119 if (ret)
1120 return ret;
1121
1122 spin_lock_irqsave(&sport->port.lock, flags);
1123
1124 lpuart_setup_watermark(sport);
1125
1126 temp = readb(sport->port.membase + UARTCR2);
1127 temp |= (UARTCR2_RIE | UARTCR2_TIE | UARTCR2_RE | UARTCR2_TE);
1128 writeb(temp, sport->port.membase + UARTCR2);
1129
1130 spin_unlock_irqrestore(&sport->port.lock, flags);
1131 return 0;
1132}
1133
380c966c
JL		 1134static int lpuart32_startup(struct uart_port *port)
1135{
1136 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1137 int ret;
1138 unsigned long flags;
1139 unsigned long temp;
1140
1141 /* determine FIFO size */
1142 temp = lpuart32_read(sport->port.membase + UARTFIFO);
1143
1144 sport->txfifo_size = 0x1 << (((temp >> UARTFIFO_TXSIZE_OFF) &
1145 UARTFIFO_FIFOSIZE_MASK) - 1);
1146
1147 sport->rxfifo_size = 0x1 << (((temp >> UARTFIFO_RXSIZE_OFF) &
1148 UARTFIFO_FIFOSIZE_MASK) - 1);
1149
1150 ret = devm_request_irq(port->dev, port->irq, lpuart32_int, 0,
1151 DRIVER_NAME, sport);
1152 if (ret)
1153 return ret;
1154
1155 spin_lock_irqsave(&sport->port.lock, flags);
1156
1157 lpuart32_setup_watermark(sport);
1158
1159 temp = lpuart32_read(sport->port.membase + UARTCTRL);
1160 temp |= (UARTCTRL_RIE | UARTCTRL_TIE | UARTCTRL_RE | UARTCTRL_TE);
1161 temp |= UARTCTRL_ILIE;
1162 lpuart32_write(temp, sport->port.membase + UARTCTRL);
1163
1164 spin_unlock_irqrestore(&sport->port.lock, flags);
1165 return 0;
1166}
1167
c9e2e946
JL		 1168static void lpuart_shutdown(struct uart_port *port)
1169{
1170 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1171 unsigned char temp;
1172 unsigned long flags;
1173
1174 spin_lock_irqsave(&port->lock, flags);
1175
1176 /* disable Rx/Tx and interrupts */
1177 temp = readb(port->membase + UARTCR2);
1178 temp &= ~(UARTCR2_TE | UARTCR2_RE |
1179 UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_RIE);
1180 writeb(temp, port->membase + UARTCR2);
1181
1182 spin_unlock_irqrestore(&port->lock, flags);
1183
1184 devm_free_irq(port->dev, port->irq, sport);
f1cd8c87 1185
4a818c43
SA		 1186 if (sport->lpuart_dma_rx_use) {
1187 lpuart_dma_rx_free(&sport->port);
4a8588a1 1188 del_timer_sync(&sport->lpuart_timer);
f1cd8c87 1189 }
4a818c43
SA		 1190
1191 if (sport->lpuart_dma_tx_use)
1192 lpuart_dma_tx_free(&sport->port);
c9e2e946
JL		 1193}
1194
380c966c
JL		 1195static void lpuart32_shutdown(struct uart_port *port)
1196{
1197 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1198 unsigned long temp;
1199 unsigned long flags;
1200
1201 spin_lock_irqsave(&port->lock, flags);
1202
1203 /* disable Rx/Tx and interrupts */
1204 temp = lpuart32_read(port->membase + UARTCTRL);
1205 temp &= ~(UARTCTRL_TE | UARTCTRL_RE |
1206 UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_RIE);
1207 lpuart32_write(temp, port->membase + UARTCTRL);
1208
1209 spin_unlock_irqrestore(&port->lock, flags);
1210
1211 devm_free_irq(port->dev, port->irq, sport);
1212}
1213
c9e2e946
JL		 1214static void
1215lpuart_set_termios(struct uart_port *port, struct ktermios *termios,
1216 struct ktermios *old)
1217{
1218 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1219 unsigned long flags;
1220 unsigned char cr1, old_cr1, old_cr2, cr4, bdh, modem;
1221 unsigned int baud;
1222 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
1223 unsigned int sbr, brfa;
1224
1225 cr1 = old_cr1 = readb(sport->port.membase + UARTCR1);
1226 old_cr2 = readb(sport->port.membase + UARTCR2);
1227 cr4 = readb(sport->port.membase + UARTCR4);
1228 bdh = readb(sport->port.membase + UARTBDH);
1229 modem = readb(sport->port.membase + UARTMODEM);
1230 /*
1231 * only support CS8 and CS7, and for CS7 must enable PE.
1232 * supported mode:
1233 * - (7,e/o,1)
1234 * - (8,n,1)
1235 * - (8,m/s,1)
1236 * - (8,e/o,1)
1237 */
1238 while ((termios->c_cflag & CSIZE) != CS8 &&
1239 (termios->c_cflag & CSIZE) != CS7) {
1240 termios->c_cflag &= ~CSIZE;
1241 termios->c_cflag |= old_csize;
1242 old_csize = CS8;
1243 }
1244
1245 if ((termios->c_cflag & CSIZE) == CS8 ||
1246 (termios->c_cflag & CSIZE) == CS7)
1247 cr1 = old_cr1 & ~UARTCR1_M;
1248
1249 if (termios->c_cflag & CMSPAR) {
1250 if ((termios->c_cflag & CSIZE) != CS8) {
1251 termios->c_cflag &= ~CSIZE;
1252 termios->c_cflag |= CS8;
1253 }
1254 cr1 |= UARTCR1_M;
1255 }
1256
1257 if (termios->c_cflag & CRTSCTS) {
1258 modem |= (UARTMODEM_RXRTSE | UARTMODEM_TXCTSE);
1259 } else {
1260 termios->c_cflag &= ~CRTSCTS;
1261 modem &= ~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE);
1262 }
1263
1264 if (termios->c_cflag & CSTOPB)
1265 termios->c_cflag &= ~CSTOPB;
1266
1267 /* parity must be enabled when CS7 to match 8-bits format */
1268 if ((termios->c_cflag & CSIZE) == CS7)
1269 termios->c_cflag |= PARENB;
1270
1271 if ((termios->c_cflag & PARENB)) {
1272 if (termios->c_cflag & CMSPAR) {
1273 cr1 &= ~UARTCR1_PE;
1274 cr1 |= UARTCR1_M;
1275 } else {
1276 cr1 |= UARTCR1_PE;
1277 if ((termios->c_cflag & CSIZE) == CS8)
1278 cr1 |= UARTCR1_M;
1279 if (termios->c_cflag & PARODD)
1280 cr1 |= UARTCR1_PT;
1281 else
1282 cr1 &= ~UARTCR1_PT;
1283 }
1284 }
1285
1286 /* ask the core to calculate the divisor */
1287 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
1288
1289 spin_lock_irqsave(&sport->port.lock, flags);
1290
1291 sport->port.read_status_mask = 0;
1292 if (termios->c_iflag & INPCK)
1293 sport->port.read_status_mask |= (UARTSR1_FE | UARTSR1_PE);
ef8b9ddc 1294 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
c9e2e946
JL		 1295 sport->port.read_status_mask |= UARTSR1_FE;
1296
1297 /* characters to ignore */
1298 sport->port.ignore_status_mask = 0;
1299 if (termios->c_iflag & IGNPAR)
1300 sport->port.ignore_status_mask |= UARTSR1_PE;
1301 if (termios->c_iflag & IGNBRK) {
1302 sport->port.ignore_status_mask |= UARTSR1_FE;
1303 /*
1304 * if we're ignoring parity and break indicators,
1305 * ignore overruns too (for real raw support).
1306 */
1307 if (termios->c_iflag & IGNPAR)
1308 sport->port.ignore_status_mask |= UARTSR1_OR;
1309 }
1310
1311 /* update the per-port timeout */
1312 uart_update_timeout(port, termios->c_cflag, baud);
1313
4a818c43 1314 if (sport->lpuart_dma_rx_use) {
90abef91
SA		 1315 /* Calculate delay for 1.5 DMA buffers */
1316 sport->dma_rx_timeout = (sport->port.timeout - HZ / 50) *
1317 FSL_UART_RX_DMA_BUFFER_SIZE * 3 /
1318 sport->rxfifo_size / 2;
1319 dev_dbg(port->dev, "DMA Rx t-out %ums, tty t-out %u jiffies\n",
1320 sport->dma_rx_timeout * 1000 / HZ, sport->port.timeout);
1321 if (sport->dma_rx_timeout < msecs_to_jiffies(20))
1322 sport->dma_rx_timeout = msecs_to_jiffies(20);
1323 }
1324
c9e2e946
JL		 1325 /* wait transmit engin complete */
1326 while (!(readb(sport->port.membase + UARTSR1) & UARTSR1_TC))
1327 barrier();
1328
1329 /* disable transmit and receive */
1330 writeb(old_cr2 & ~(UARTCR2_TE | UARTCR2_RE),
1331 sport->port.membase + UARTCR2);
1332
1333 sbr = sport->port.uartclk / (16 * baud);
1334 brfa = ((sport->port.uartclk - (16 * sbr * baud)) * 2) / baud;
1335 bdh &= ~UARTBDH_SBR_MASK;
1336 bdh |= (sbr >> 8) & 0x1F;
1337 cr4 &= ~UARTCR4_BRFA_MASK;
1338 brfa &= UARTCR4_BRFA_MASK;
1339 writeb(cr4 | brfa, sport->port.membase + UARTCR4);
1340 writeb(bdh, sport->port.membase + UARTBDH);
1341 writeb(sbr & 0xFF, sport->port.membase + UARTBDL);
1342 writeb(cr1, sport->port.membase + UARTCR1);
1343 writeb(modem, sport->port.membase + UARTMODEM);
1344
1345 /* restore control register */
1346 writeb(old_cr2, sport->port.membase + UARTCR2);
1347
1348 spin_unlock_irqrestore(&sport->port.lock, flags);
1349}
1350
380c966c
JL		 1351static void
1352lpuart32_set_termios(struct uart_port *port, struct ktermios *termios,
1353 struct ktermios *old)
1354{
1355 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1356 unsigned long flags;
1357 unsigned long ctrl, old_ctrl, bd, modem;
1358 unsigned int baud;
1359 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
1360 unsigned int sbr;
1361
1362 ctrl = old_ctrl = lpuart32_read(sport->port.membase + UARTCTRL);
1363 bd = lpuart32_read(sport->port.membase + UARTBAUD);
1364 modem = lpuart32_read(sport->port.membase + UARTMODIR);
1365 /*
1366 * only support CS8 and CS7, and for CS7 must enable PE.
1367 * supported mode:
1368 * - (7,e/o,1)
1369 * - (8,n,1)
1370 * - (8,m/s,1)
1371 * - (8,e/o,1)
1372 */
1373 while ((termios->c_cflag & CSIZE) != CS8 &&
1374 (termios->c_cflag & CSIZE) != CS7) {
1375 termios->c_cflag &= ~CSIZE;
1376 termios->c_cflag |= old_csize;
1377 old_csize = CS8;
1378 }
1379
1380 if ((termios->c_cflag & CSIZE) == CS8 ||
1381 (termios->c_cflag & CSIZE) == CS7)
1382 ctrl = old_ctrl & ~UARTCTRL_M;
1383
1384 if (termios->c_cflag & CMSPAR) {
1385 if ((termios->c_cflag & CSIZE) != CS8) {
1386 termios->c_cflag &= ~CSIZE;
1387 termios->c_cflag |= CS8;
1388 }
1389 ctrl |= UARTCTRL_M;
1390 }
1391
1392 if (termios->c_cflag & CRTSCTS) {
1393 modem |= (UARTMODEM_RXRTSE | UARTMODEM_TXCTSE);
1394 } else {
1395 termios->c_cflag &= ~CRTSCTS;
1396 modem &= ~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE);
1397 }
1398
1399 if (termios->c_cflag & CSTOPB)
1400 termios->c_cflag &= ~CSTOPB;
1401
1402 /* parity must be enabled when CS7 to match 8-bits format */
1403 if ((termios->c_cflag & CSIZE) == CS7)
1404 termios->c_cflag |= PARENB;
1405
1406 if ((termios->c_cflag & PARENB)) {
1407 if (termios->c_cflag & CMSPAR) {
1408 ctrl &= ~UARTCTRL_PE;
1409 ctrl |= UARTCTRL_M;
1410 } else {
1411 ctrl |= UARTCR1_PE;
1412 if ((termios->c_cflag & CSIZE) == CS8)
1413 ctrl |= UARTCTRL_M;
1414 if (termios->c_cflag & PARODD)
1415 ctrl |= UARTCTRL_PT;
1416 else
1417 ctrl &= ~UARTCTRL_PT;
1418 }
1419 }
1420
1421 /* ask the core to calculate the divisor */
1422 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
1423
1424 spin_lock_irqsave(&sport->port.lock, flags);
1425
1426 sport->port.read_status_mask = 0;
1427 if (termios->c_iflag & INPCK)
1428 sport->port.read_status_mask |= (UARTSTAT_FE | UARTSTAT_PE);
1429 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
1430 sport->port.read_status_mask |= UARTSTAT_FE;
1431
1432 /* characters to ignore */
1433 sport->port.ignore_status_mask = 0;
1434 if (termios->c_iflag & IGNPAR)
1435 sport->port.ignore_status_mask |= UARTSTAT_PE;
1436 if (termios->c_iflag & IGNBRK) {
1437 sport->port.ignore_status_mask |= UARTSTAT_FE;
1438 /*
1439 * if we're ignoring parity and break indicators,
1440 * ignore overruns too (for real raw support).
1441 */
1442 if (termios->c_iflag & IGNPAR)
1443 sport->port.ignore_status_mask |= UARTSTAT_OR;
1444 }
1445
1446 /* update the per-port timeout */
1447 uart_update_timeout(port, termios->c_cflag, baud);
1448
1449 /* wait transmit engin complete */
1450 while (!(lpuart32_read(sport->port.membase + UARTSTAT) & UARTSTAT_TC))
1451 barrier();
1452
1453 /* disable transmit and receive */
1454 lpuart32_write(old_ctrl & ~(UARTCTRL_TE | UARTCTRL_RE),
1455 sport->port.membase + UARTCTRL);
1456
1457 sbr = sport->port.uartclk / (16 * baud);
1458 bd &= ~UARTBAUD_SBR_MASK;
1459 bd |= sbr & UARTBAUD_SBR_MASK;
1460 bd |= UARTBAUD_BOTHEDGE;
1461 bd &= ~(UARTBAUD_TDMAE | UARTBAUD_RDMAE);
1462 lpuart32_write(bd, sport->port.membase + UARTBAUD);
1463 lpuart32_write(modem, sport->port.membase + UARTMODIR);
1464 lpuart32_write(ctrl, sport->port.membase + UARTCTRL);
1465 /* restore control register */
1466
1467 spin_unlock_irqrestore(&sport->port.lock, flags);
1468}
1469
c9e2e946
JL		 1470static const char *lpuart_type(struct uart_port *port)
1471{
1472 return "FSL_LPUART";
1473}
1474
1475static void lpuart_release_port(struct uart_port *port)
1476{
1477 /* nothing to do */
1478}
1479
1480static int lpuart_request_port(struct uart_port *port)
1481{
1482 return 0;
1483}
1484
1485/* configure/autoconfigure the port */
1486static void lpuart_config_port(struct uart_port *port, int flags)
1487{
1488 if (flags & UART_CONFIG_TYPE)
1489 port->type = PORT_LPUART;
1490}
1491
1492static int lpuart_verify_port(struct uart_port *port, struct serial_struct *ser)
1493{
1494 int ret = 0;
1495
1496 if (ser->type != PORT_UNKNOWN && ser->type != PORT_LPUART)
1497 ret = -EINVAL;
1498 if (port->irq != ser->irq)
1499 ret = -EINVAL;
1500 if (ser->io_type != UPIO_MEM)
1501 ret = -EINVAL;
1502 if (port->uartclk / 16 != ser->baud_base)
1503 ret = -EINVAL;
1504 if (port->iobase != ser->port)
1505 ret = -EINVAL;
1506 if (ser->hub6 != 0)
1507 ret = -EINVAL;
1508 return ret;
1509}
1510
1511static struct uart_ops lpuart_pops = {
1512 .tx_empty = lpuart_tx_empty,
1513 .set_mctrl = lpuart_set_mctrl,
1514 .get_mctrl = lpuart_get_mctrl,
1515 .stop_tx = lpuart_stop_tx,
1516 .start_tx = lpuart_start_tx,
1517 .stop_rx = lpuart_stop_rx,
c9e2e946
JL		 1518 .break_ctl = lpuart_break_ctl,
1519 .startup = lpuart_startup,
1520 .shutdown = lpuart_shutdown,
1521 .set_termios = lpuart_set_termios,
1522 .type = lpuart_type,
1523 .request_port = lpuart_request_port,
1524 .release_port = lpuart_release_port,
1525 .config_port = lpuart_config_port,
1526 .verify_port = lpuart_verify_port,
bfc2e07f 1527 .flush_buffer = lpuart_flush_buffer,
c9e2e946
JL		 1528};
1529
380c966c
JL		 1530static struct uart_ops lpuart32_pops = {
1531 .tx_empty = lpuart32_tx_empty,
1532 .set_mctrl = lpuart32_set_mctrl,
1533 .get_mctrl = lpuart32_get_mctrl,
1534 .stop_tx = lpuart32_stop_tx,
1535 .start_tx = lpuart32_start_tx,
1536 .stop_rx = lpuart32_stop_rx,
1537 .break_ctl = lpuart32_break_ctl,
1538 .startup = lpuart32_startup,
1539 .shutdown = lpuart32_shutdown,
1540 .set_termios = lpuart32_set_termios,
1541 .type = lpuart_type,
1542 .request_port = lpuart_request_port,
1543 .release_port = lpuart_release_port,
1544 .config_port = lpuart_config_port,
1545 .verify_port = lpuart_verify_port,
bfc2e07f 1546 .flush_buffer = lpuart_flush_buffer,
380c966c
JL		 1547};
1548
c9e2e946
JL		 1549static struct lpuart_port *lpuart_ports[UART_NR];
1550
1551#ifdef CONFIG_SERIAL_FSL_LPUART_CONSOLE
1552static void lpuart_console_putchar(struct uart_port *port, int ch)
1553{
1554 while (!(readb(port->membase + UARTSR1) & UARTSR1_TDRE))
1555 barrier();
1556
1557 writeb(ch, port->membase + UARTDR);
1558}
1559
380c966c
JL		 1560static void lpuart32_console_putchar(struct uart_port *port, int ch)
1561{
1562 while (!(lpuart32_read(port->membase + UARTSTAT) & UARTSTAT_TDRE))
1563 barrier();
1564
1565 lpuart32_write(ch, port->membase + UARTDATA);
1566}
1567
c9e2e946
JL		 1568static void
1569lpuart_console_write(struct console *co, const char *s, unsigned int count)
1570{
1571 struct lpuart_port *sport = lpuart_ports[co->index];
1572 unsigned char old_cr2, cr2;
1573
1574 /* first save CR2 and then disable interrupts */
1575 cr2 = old_cr2 = readb(sport->port.membase + UARTCR2);
1576 cr2 |= (UARTCR2_TE | UARTCR2_RE);
1577 cr2 &= ~(UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_RIE);
1578 writeb(cr2, sport->port.membase + UARTCR2);
1579
1580 uart_console_write(&sport->port, s, count, lpuart_console_putchar);
1581
1582 /* wait for transmitter finish complete and restore CR2 */
1583 while (!(readb(sport->port.membase + UARTSR1) & UARTSR1_TC))
1584 barrier();
1585
1586 writeb(old_cr2, sport->port.membase + UARTCR2);
1587}
1588
380c966c
JL		 1589static void
1590lpuart32_console_write(struct console *co, const char *s, unsigned int count)
1591{
1592 struct lpuart_port *sport = lpuart_ports[co->index];
1593 unsigned long old_cr, cr;
1594
1595 /* first save CR2 and then disable interrupts */
1596 cr = old_cr = lpuart32_read(sport->port.membase + UARTCTRL);
1597 cr |= (UARTCTRL_TE | UARTCTRL_RE);
1598 cr &= ~(UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_RIE);
1599 lpuart32_write(cr, sport->port.membase + UARTCTRL);
1600
1601 uart_console_write(&sport->port, s, count, lpuart32_console_putchar);
1602
1603 /* wait for transmitter finish complete and restore CR2 */
1604 while (!(lpuart32_read(sport->port.membase + UARTSTAT) & UARTSTAT_TC))
1605 barrier();
1606
1607 lpuart32_write(old_cr, sport->port.membase + UARTCTRL);
1608}
1609
c9e2e946
JL		 1610/*
1611 * if the port was already initialised (eg, by a boot loader),
1612 * try to determine the current setup.
1613 */
1614static void __init
1615lpuart_console_get_options(struct lpuart_port *sport, int *baud,
1616 int *parity, int *bits)
1617{
1618 unsigned char cr, bdh, bdl, brfa;
1619 unsigned int sbr, uartclk, baud_raw;
1620
1621 cr = readb(sport->port.membase + UARTCR2);
1622 cr &= UARTCR2_TE | UARTCR2_RE;
1623 if (!cr)
1624 return;
1625
1626 /* ok, the port was enabled */
1627
1628 cr = readb(sport->port.membase + UARTCR1);
1629
1630 *parity = 'n';
1631 if (cr & UARTCR1_PE) {
1632 if (cr & UARTCR1_PT)
1633 *parity = 'o';
1634 else
1635 *parity = 'e';
1636 }
1637
1638 if (cr & UARTCR1_M)
1639 *bits = 9;
1640 else
1641 *bits = 8;
1642
1643 bdh = readb(sport->port.membase + UARTBDH);
1644 bdh &= UARTBDH_SBR_MASK;
1645 bdl = readb(sport->port.membase + UARTBDL);
1646 sbr = bdh;
1647 sbr <<= 8;
1648 sbr |= bdl;
1649 brfa = readb(sport->port.membase + UARTCR4);
1650 brfa &= UARTCR4_BRFA_MASK;
1651
1652 uartclk = clk_get_rate(sport->clk);
1653 /*
1654 * baud = mod_clk/(16*(sbr[13]+(brfa)/32)
1655 */
1656 baud_raw = uartclk / (16 * (sbr + brfa / 32));
1657
1658 if (*baud != baud_raw)
1659 printk(KERN_INFO "Serial: Console lpuart rounded baud rate"
1660 "from %d to %d\n", baud_raw, *baud);
1661}
1662
380c966c
JL		 1663static void __init
1664lpuart32_console_get_options(struct lpuart_port *sport, int *baud,
1665 int *parity, int *bits)
1666{
1667 unsigned long cr, bd;
1668 unsigned int sbr, uartclk, baud_raw;
1669
1670 cr = lpuart32_read(sport->port.membase + UARTCTRL);
1671 cr &= UARTCTRL_TE | UARTCTRL_RE;
1672 if (!cr)
1673 return;
1674
1675 /* ok, the port was enabled */
1676
1677 cr = lpuart32_read(sport->port.membase + UARTCTRL);
1678
1679 *parity = 'n';
1680 if (cr & UARTCTRL_PE) {
1681 if (cr & UARTCTRL_PT)
1682 *parity = 'o';
1683 else
1684 *parity = 'e';
1685 }
1686
1687 if (cr & UARTCTRL_M)
1688 *bits = 9;
1689 else
1690 *bits = 8;
1691
1692 bd = lpuart32_read(sport->port.membase + UARTBAUD);
1693 bd &= UARTBAUD_SBR_MASK;
1694 sbr = bd;
1695 uartclk = clk_get_rate(sport->clk);
1696 /*
1697 * baud = mod_clk/(16*(sbr[13]+(brfa)/32)
1698 */
1699 baud_raw = uartclk / (16 * sbr);
1700
1701 if (*baud != baud_raw)
1702 printk(KERN_INFO "Serial: Console lpuart rounded baud rate"
1703 "from %d to %d\n", baud_raw, *baud);
1704}
1705
c9e2e946
JL		 1706static int __init lpuart_console_setup(struct console *co, char *options)
1707{
1708 struct lpuart_port *sport;
1709 int baud = 115200;
1710 int bits = 8;
1711 int parity = 'n';
1712 int flow = 'n';
1713
1714 /*
1715 * check whether an invalid uart number has been specified, and
1716 * if so, search for the first available port that does have
1717 * console support.
1718 */
1719 if (co->index == -1 || co->index >= ARRAY_SIZE(lpuart_ports))
1720 co->index = 0;
1721
1722 sport = lpuart_ports[co->index];
1723 if (sport == NULL)
1724 return -ENODEV;
1725
1726 if (options)
1727 uart_parse_options(options, &baud, &parity, &bits, &flow);
1728 else
380c966c
JL		 1729 if (sport->lpuart32)
1730 lpuart32_console_get_options(sport, &baud, &parity, &bits);
1731 else
1732 lpuart_console_get_options(sport, &baud, &parity, &bits);
c9e2e946 1733
380c966c
JL		 1734 if (sport->lpuart32)
1735 lpuart32_setup_watermark(sport);
1736 else
1737 lpuart_setup_watermark(sport);
c9e2e946
JL		 1738
1739 return uart_set_options(&sport->port, co, baud, parity, bits, flow);
1740}
1741
1742static struct uart_driver lpuart_reg;
1743static struct console lpuart_console = {
1744 .name = DEV_NAME,
1745 .write = lpuart_console_write,
1746 .device = uart_console_device,
1747 .setup = lpuart_console_setup,
1748 .flags = CON_PRINTBUFFER,
1749 .index = -1,
1750 .data = &lpuart_reg,
1751};
1752
380c966c
JL		 1753static struct console lpuart32_console = {
1754 .name = DEV_NAME,
1755 .write = lpuart32_console_write,
1756 .device = uart_console_device,
1757 .setup = lpuart_console_setup,
1758 .flags = CON_PRINTBUFFER,
1759 .index = -1,
1760 .data = &lpuart_reg,
1761};
1762
1d59b382
SA		 1763static void lpuart_early_write(struct console *con, const char *s, unsigned n)
1764{
1765 struct earlycon_device *dev = con->data;
1766
1767 uart_console_write(&dev->port, s, n, lpuart_console_putchar);
1768}
1769
1770static void lpuart32_early_write(struct console *con, const char *s, unsigned n)
1771{
1772 struct earlycon_device *dev = con->data;
1773
1774 uart_console_write(&dev->port, s, n, lpuart32_console_putchar);
1775}
1776
1777static int __init lpuart_early_console_setup(struct earlycon_device *device,
1778 const char *opt)
1779{
1780 if (!device->port.membase)
1781 return -ENODEV;
1782
1783 device->con->write = lpuart_early_write;
1784 return 0;
1785}
1786
1787static int __init lpuart32_early_console_setup(struct earlycon_device *device,
1788 const char *opt)
1789{
1790 if (!device->port.membase)
1791 return -ENODEV;
1792
1793 device->con->write = lpuart32_early_write;
1794 return 0;
1795}
1796
1797OF_EARLYCON_DECLARE(lpuart, "fsl,vf610-lpuart", lpuart_early_console_setup);
1798OF_EARLYCON_DECLARE(lpuart32, "fsl,ls1021a-lpuart", lpuart32_early_console_setup);
1799EARLYCON_DECLARE(lpuart, lpuart_early_console_setup);
1800EARLYCON_DECLARE(lpuart32, lpuart32_early_console_setup);
1801
c9e2e946 1802#define LPUART_CONSOLE (&lpuart_console)
380c966c 1803#define LPUART32_CONSOLE (&lpuart32_console)
c9e2e946
JL		 1804#else
1805#define LPUART_CONSOLE NULL
380c966c 1806#define LPUART32_CONSOLE NULL
c9e2e946
JL		 1807#endif
1808
1809static struct uart_driver lpuart_reg = {
1810 .owner = THIS_MODULE,
1811 .driver_name = DRIVER_NAME,
1812 .dev_name = DEV_NAME,
1813 .nr = ARRAY_SIZE(lpuart_ports),
1814 .cons = LPUART_CONSOLE,
1815};
1816
1817static int lpuart_probe(struct platform_device *pdev)
1818{
1819 struct device_node *np = pdev->dev.of_node;
1820 struct lpuart_port *sport;
1821 struct resource *res;
1822 int ret;
1823
1824 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);
1825 if (!sport)
1826 return -ENOMEM;
1827
1828 pdev->dev.coherent_dma_mask = 0;
1829
1830 ret = of_alias_get_id(np, "serial");
1831 if (ret < 0) {
1832 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret);
1833 return ret;
1834 }
1835 sport->port.line = ret;
380c966c 1836 sport->lpuart32 = of_device_is_compatible(np, "fsl,ls1021a-lpuart");
c9e2e946 1837
4ae612a3 1838 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
c9e2e946
JL		 1839 sport->port.membase = devm_ioremap_resource(&pdev->dev, res);
1840 if (IS_ERR(sport->port.membase))
1841 return PTR_ERR(sport->port.membase);
1842
4ae612a3 1843 sport->port.mapbase = res->start;
c9e2e946
JL		 1844 sport->port.dev = &pdev->dev;
1845 sport->port.type = PORT_LPUART;
1846 sport->port.iotype = UPIO_MEM;
394a9e2c
JS		 1847 ret = platform_get_irq(pdev, 0);
1848 if (ret < 0) {
1849 dev_err(&pdev->dev, "cannot obtain irq\n");
1850 return ret;
1851 }
1852 sport->port.irq = ret;
1853
380c966c
JL		 1854 if (sport->lpuart32)
1855 sport->port.ops = &lpuart32_pops;
1856 else
1857 sport->port.ops = &lpuart_pops;
c9e2e946
JL		 1858 sport->port.flags = UPF_BOOT_AUTOCONF;
1859
1860 sport->clk = devm_clk_get(&pdev->dev, "ipg");
1861 if (IS_ERR(sport->clk)) {
1862 ret = PTR_ERR(sport->clk);
1863 dev_err(&pdev->dev, "failed to get uart clk: %d\n", ret);
1864 return ret;
1865 }
1866
1867 ret = clk_prepare_enable(sport->clk);
1868 if (ret) {
1869 dev_err(&pdev->dev, "failed to enable uart clk: %d\n", ret);
1870 return ret;
1871 }
1872
1873 sport->port.uartclk = clk_get_rate(sport->clk);
1874
1875 lpuart_ports[sport->port.line] = sport;
1876
1877 platform_set_drvdata(pdev, &sport->port);
1878
380c966c
JL		 1879 if (sport->lpuart32)
1880 lpuart_reg.cons = LPUART32_CONSOLE;
1881 else
1882 lpuart_reg.cons = LPUART_CONSOLE;
1883
c9e2e946
JL		 1884 ret = uart_add_one_port(&lpuart_reg, &sport->port);
1885 if (ret) {
1886 clk_disable_unprepare(sport->clk);
1887 return ret;
1888 }
1889
4a818c43
SA		 1890 sport->dma_tx_chan = dma_request_slave_channel(sport->port.dev, "tx");
1891 if (!sport->dma_tx_chan)
1892 dev_info(sport->port.dev, "DMA tx channel request failed, "
1893 "operating without tx DMA\n");
1894
1895 sport->dma_rx_chan = dma_request_slave_channel(sport->port.dev, "rx");
1896 if (!sport->dma_rx_chan)
1897 dev_info(sport->port.dev, "DMA rx channel request failed, "
1898 "operating without rx DMA\n");
1899
c9e2e946
JL		 1900 return 0;
1901}
1902
1903static int lpuart_remove(struct platform_device *pdev)
1904{
1905 struct lpuart_port *sport = platform_get_drvdata(pdev);
1906
1907 uart_remove_one_port(&lpuart_reg, &sport->port);
1908
1909 clk_disable_unprepare(sport->clk);
1910
4a818c43
SA		 1911 if (sport->dma_tx_chan)
1912 dma_release_channel(sport->dma_tx_chan);
1913
1914 if (sport->dma_rx_chan)
1915 dma_release_channel(sport->dma_rx_chan);
1916
c9e2e946
JL		 1917 return 0;
1918}
1919
1920#ifdef CONFIG_PM_SLEEP
1921static int lpuart_suspend(struct device *dev)
1922{
1923 struct lpuart_port *sport = dev_get_drvdata(dev);
2fe605df
YY		 1924 unsigned long temp;
1925
1926 if (sport->lpuart32) {
1927 /* disable Rx/Tx and interrupts */
1928 temp = lpuart32_read(sport->port.membase + UARTCTRL);
1929 temp &= ~(UARTCTRL_TE | UARTCTRL_TIE | UARTCTRL_TCIE);
1930 lpuart32_write(temp, sport->port.membase + UARTCTRL);
1931 } else {
1932 /* disable Rx/Tx and interrupts */
1933 temp = readb(sport->port.membase + UARTCR2);
1934 temp &= ~(UARTCR2_TE | UARTCR2_TIE | UARTCR2_TCIE);
1935 writeb(temp, sport->port.membase + UARTCR2);
1936 }
c9e2e946 1937
d6b0d2f2
SA		 1938 if (sport->dma_rx_in_progress)
1939 lpuart_dma_rx_terminate(sport);
1940
c9e2e946 1941 uart_suspend_port(&lpuart_reg, &sport->port);
d6b0d2f2
SA		 1942 if (sport->port.suspended && !sport->port.irq_wake)
1943 clk_disable_unprepare(sport->clk);
c9e2e946
JL		 1944
1945 return 0;
1946}
1947
1948static int lpuart_resume(struct device *dev)
1949{
1950 struct lpuart_port *sport = dev_get_drvdata(dev);
08de1014
JL		 1951 unsigned long temp;
1952
d6b0d2f2
SA		 1953 if (sport->port.suspended && !sport->port.irq_wake)
1954 clk_prepare_enable(sport->clk);
1955
08de1014
JL		 1956 if (sport->lpuart32) {
1957 lpuart32_setup_watermark(sport);
1958 temp = lpuart32_read(sport->port.membase + UARTCTRL);
1959 temp |= (UARTCTRL_RIE | UARTCTRL_TIE | UARTCTRL_RE |
1960 UARTCTRL_TE | UARTCTRL_ILIE);
1961 lpuart32_write(temp, sport->port.membase + UARTCTRL);
1962 } else {
1963 lpuart_setup_watermark(sport);
1964 temp = readb(sport->port.membase + UARTCR2);
1965 temp |= (UARTCR2_RIE | UARTCR2_TIE | UARTCR2_RE | UARTCR2_TE);
1966 writeb(temp, sport->port.membase + UARTCR2);
1967 }
c9e2e946
JL		 1968
1969 uart_resume_port(&lpuart_reg, &sport->port);
1970
1971 return 0;
1972}
1973#endif
1974
1975static SIMPLE_DEV_PM_OPS(lpuart_pm_ops, lpuart_suspend, lpuart_resume);
1976
1977static struct platform_driver lpuart_driver = {
1978 .probe = lpuart_probe,
1979 .remove = lpuart_remove,
1980 .driver = {
1981 .name = "fsl-lpuart",
c9e2e946
JL		 1982 .of_match_table = lpuart_dt_ids,
1983 .pm = &lpuart_pm_ops,
1984 },
1985};
1986
1987static int __init lpuart_serial_init(void)
1988{
144c29ed 1989 int ret = uart_register_driver(&lpuart_reg);
c9e2e946 1990
c9e2e946
JL		 1991 if (ret)
1992 return ret;
1993
1994 ret = platform_driver_register(&lpuart_driver);
1995 if (ret)
1996 uart_unregister_driver(&lpuart_reg);
1997
39c34b09 1998 return ret;
c9e2e946
JL		 1999}
2000
2001static void __exit lpuart_serial_exit(void)
2002{
2003 platform_driver_unregister(&lpuart_driver);
2004 uart_unregister_driver(&lpuart_reg);
2005}
2006
2007module_init(lpuart_serial_init);
2008module_exit(lpuart_serial_exit);
2009
2010MODULE_DESCRIPTION("Freescale lpuart serial port driver");
2011MODULE_LICENSE("GPL v2");
Linux 6.x block layer and io_uring tree(s)