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tty: serial: fsl_lpuart: consider TX FIFO too in tx_empty
[linux-block.git] / drivers / tty / serial / fsl_lpuart.c
CommitLineData
c9e2e946
JL		 1/*
2 * Freescale lpuart serial port driver
3 *
380c966c 4 * Copyright 2012-2014 Freescale Semiconductor, Inc.
c9e2e946
JL		 5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 */
11
12#if defined(CONFIG_SERIAL_FSL_LPUART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
13#define SUPPORT_SYSRQ
14#endif
15
f1cd8c87
YY		 16#include <linux/clk.h>
17#include <linux/console.h>
18#include <linux/dma-mapping.h>
19#include <linux/dmaengine.h>
20#include <linux/dmapool.h>
c9e2e946
JL		 21#include <linux/io.h>
22#include <linux/irq.h>
f1cd8c87 23#include <linux/module.h>
c9e2e946
JL		 24#include <linux/of.h>
25#include <linux/of_device.h>
f1cd8c87 26#include <linux/of_dma.h>
c9e2e946 27#include <linux/serial_core.h>
f1cd8c87 28#include <linux/slab.h>
c9e2e946
JL		 29#include <linux/tty_flip.h>
30
31/* All registers are 8-bit width */
32#define UARTBDH 0x00
33#define UARTBDL 0x01
34#define UARTCR1 0x02
35#define UARTCR2 0x03
36#define UARTSR1 0x04
37#define UARTCR3 0x06
38#define UARTDR 0x07
39#define UARTCR4 0x0a
40#define UARTCR5 0x0b
41#define UARTMODEM 0x0d
42#define UARTPFIFO 0x10
43#define UARTCFIFO 0x11
44#define UARTSFIFO 0x12
45#define UARTTWFIFO 0x13
46#define UARTTCFIFO 0x14
47#define UARTRWFIFO 0x15
48
49#define UARTBDH_LBKDIE 0x80
50#define UARTBDH_RXEDGIE 0x40
51#define UARTBDH_SBR_MASK 0x1f
52
53#define UARTCR1_LOOPS 0x80
54#define UARTCR1_RSRC 0x20
55#define UARTCR1_M 0x10
56#define UARTCR1_WAKE 0x08
57#define UARTCR1_ILT 0x04
58#define UARTCR1_PE 0x02
59#define UARTCR1_PT 0x01
60
61#define UARTCR2_TIE 0x80
62#define UARTCR2_TCIE 0x40
63#define UARTCR2_RIE 0x20
64#define UARTCR2_ILIE 0x10
65#define UARTCR2_TE 0x08
66#define UARTCR2_RE 0x04
67#define UARTCR2_RWU 0x02
68#define UARTCR2_SBK 0x01
69
70#define UARTSR1_TDRE 0x80
71#define UARTSR1_TC 0x40
72#define UARTSR1_RDRF 0x20
73#define UARTSR1_IDLE 0x10
74#define UARTSR1_OR 0x08
75#define UARTSR1_NF 0x04
76#define UARTSR1_FE 0x02
77#define UARTSR1_PE 0x01
78
79#define UARTCR3_R8 0x80
80#define UARTCR3_T8 0x40
81#define UARTCR3_TXDIR 0x20
82#define UARTCR3_TXINV 0x10
83#define UARTCR3_ORIE 0x08
84#define UARTCR3_NEIE 0x04
85#define UARTCR3_FEIE 0x02
86#define UARTCR3_PEIE 0x01
87
88#define UARTCR4_MAEN1 0x80
89#define UARTCR4_MAEN2 0x40
90#define UARTCR4_M10 0x20
91#define UARTCR4_BRFA_MASK 0x1f
92#define UARTCR4_BRFA_OFF 0
93
94#define UARTCR5_TDMAS 0x80
95#define UARTCR5_RDMAS 0x20
96
97#define UARTMODEM_RXRTSE 0x08
98#define UARTMODEM_TXRTSPOL 0x04
99#define UARTMODEM_TXRTSE 0x02
100#define UARTMODEM_TXCTSE 0x01
101
102#define UARTPFIFO_TXFE 0x80
103#define UARTPFIFO_FIFOSIZE_MASK 0x7
104#define UARTPFIFO_TXSIZE_OFF 4
105#define UARTPFIFO_RXFE 0x08
106#define UARTPFIFO_RXSIZE_OFF 0
107
108#define UARTCFIFO_TXFLUSH 0x80
109#define UARTCFIFO_RXFLUSH 0x40
110#define UARTCFIFO_RXOFE 0x04
111#define UARTCFIFO_TXOFE 0x02
112#define UARTCFIFO_RXUFE 0x01
113
114#define UARTSFIFO_TXEMPT 0x80
115#define UARTSFIFO_RXEMPT 0x40
116#define UARTSFIFO_RXOF 0x04
117#define UARTSFIFO_TXOF 0x02
118#define UARTSFIFO_RXUF 0x01
119
380c966c
JL		 120/* 32-bit register defination */
121#define UARTBAUD 0x00
122#define UARTSTAT 0x04
123#define UARTCTRL 0x08
124#define UARTDATA 0x0C
125#define UARTMATCH 0x10
126#define UARTMODIR 0x14
127#define UARTFIFO 0x18
128#define UARTWATER 0x1c
129
130#define UARTBAUD_MAEN1 0x80000000
131#define UARTBAUD_MAEN2 0x40000000
132#define UARTBAUD_M10 0x20000000
133#define UARTBAUD_TDMAE 0x00800000
134#define UARTBAUD_RDMAE 0x00200000
135#define UARTBAUD_MATCFG 0x00400000
136#define UARTBAUD_BOTHEDGE 0x00020000
137#define UARTBAUD_RESYNCDIS 0x00010000
138#define UARTBAUD_LBKDIE 0x00008000
139#define UARTBAUD_RXEDGIE 0x00004000
140#define UARTBAUD_SBNS 0x00002000
141#define UARTBAUD_SBR 0x00000000
142#define UARTBAUD_SBR_MASK 0x1fff
143
144#define UARTSTAT_LBKDIF 0x80000000
145#define UARTSTAT_RXEDGIF 0x40000000
146#define UARTSTAT_MSBF 0x20000000
147#define UARTSTAT_RXINV 0x10000000
148#define UARTSTAT_RWUID 0x08000000
149#define UARTSTAT_BRK13 0x04000000
150#define UARTSTAT_LBKDE 0x02000000
151#define UARTSTAT_RAF 0x01000000
152#define UARTSTAT_TDRE 0x00800000
153#define UARTSTAT_TC 0x00400000
154#define UARTSTAT_RDRF 0x00200000
155#define UARTSTAT_IDLE 0x00100000
156#define UARTSTAT_OR 0x00080000
157#define UARTSTAT_NF 0x00040000
158#define UARTSTAT_FE 0x00020000
159#define UARTSTAT_PE 0x00010000
160#define UARTSTAT_MA1F 0x00008000
161#define UARTSTAT_M21F 0x00004000
162
163#define UARTCTRL_R8T9 0x80000000
164#define UARTCTRL_R9T8 0x40000000
165#define UARTCTRL_TXDIR 0x20000000
166#define UARTCTRL_TXINV 0x10000000
167#define UARTCTRL_ORIE 0x08000000
168#define UARTCTRL_NEIE 0x04000000
169#define UARTCTRL_FEIE 0x02000000
170#define UARTCTRL_PEIE 0x01000000
171#define UARTCTRL_TIE 0x00800000
172#define UARTCTRL_TCIE 0x00400000
173#define UARTCTRL_RIE 0x00200000
174#define UARTCTRL_ILIE 0x00100000
175#define UARTCTRL_TE 0x00080000
176#define UARTCTRL_RE 0x00040000
177#define UARTCTRL_RWU 0x00020000
178#define UARTCTRL_SBK 0x00010000
179#define UARTCTRL_MA1IE 0x00008000
180#define UARTCTRL_MA2IE 0x00004000
181#define UARTCTRL_IDLECFG 0x00000100
182#define UARTCTRL_LOOPS 0x00000080
183#define UARTCTRL_DOZEEN 0x00000040
184#define UARTCTRL_RSRC 0x00000020
185#define UARTCTRL_M 0x00000010
186#define UARTCTRL_WAKE 0x00000008
187#define UARTCTRL_ILT 0x00000004
188#define UARTCTRL_PE 0x00000002
189#define UARTCTRL_PT 0x00000001
190
191#define UARTDATA_NOISY 0x00008000
192#define UARTDATA_PARITYE 0x00004000
193#define UARTDATA_FRETSC 0x00002000
194#define UARTDATA_RXEMPT 0x00001000
195#define UARTDATA_IDLINE 0x00000800
196#define UARTDATA_MASK 0x3ff
197
198#define UARTMODIR_IREN 0x00020000
199#define UARTMODIR_TXCTSSRC 0x00000020
200#define UARTMODIR_TXCTSC 0x00000010
201#define UARTMODIR_RXRTSE 0x00000008
202#define UARTMODIR_TXRTSPOL 0x00000004
203#define UARTMODIR_TXRTSE 0x00000002
204#define UARTMODIR_TXCTSE 0x00000001
205
206#define UARTFIFO_TXEMPT 0x00800000
207#define UARTFIFO_RXEMPT 0x00400000
208#define UARTFIFO_TXOF 0x00020000
209#define UARTFIFO_RXUF 0x00010000
210#define UARTFIFO_TXFLUSH 0x00008000
211#define UARTFIFO_RXFLUSH 0x00004000
212#define UARTFIFO_TXOFE 0x00000200
213#define UARTFIFO_RXUFE 0x00000100
214#define UARTFIFO_TXFE 0x00000080
215#define UARTFIFO_FIFOSIZE_MASK 0x7
216#define UARTFIFO_TXSIZE_OFF 4
217#define UARTFIFO_RXFE 0x00000008
218#define UARTFIFO_RXSIZE_OFF 0
219
220#define UARTWATER_COUNT_MASK 0xff
221#define UARTWATER_TXCNT_OFF 8
222#define UARTWATER_RXCNT_OFF 24
223#define UARTWATER_WATER_MASK 0xff
224#define UARTWATER_TXWATER_OFF 0
225#define UARTWATER_RXWATER_OFF 16
226
f1cd8c87
YY		 227#define FSL_UART_RX_DMA_BUFFER_SIZE 64
228
c9e2e946
JL		 229#define DRIVER_NAME "fsl-lpuart"
230#define DEV_NAME "ttyLP"
231#define UART_NR 6
232
233struct lpuart_port {
234 struct uart_port port;
235 struct clk *clk;
236 unsigned int txfifo_size;
237 unsigned int rxfifo_size;
380c966c 238 bool lpuart32;
f1cd8c87 239
4a818c43
SA		 240 bool lpuart_dma_tx_use;
241 bool lpuart_dma_rx_use;
f1cd8c87
YY		 242 struct dma_chan *dma_tx_chan;
243 struct dma_chan *dma_rx_chan;
244 struct dma_async_tx_descriptor *dma_tx_desc;
245 struct dma_async_tx_descriptor *dma_rx_desc;
246 dma_addr_t dma_tx_buf_bus;
247 dma_addr_t dma_rx_buf_bus;
248 dma_cookie_t dma_tx_cookie;
249 dma_cookie_t dma_rx_cookie;
250 unsigned char *dma_tx_buf_virt;
251 unsigned char *dma_rx_buf_virt;
252 unsigned int dma_tx_bytes;
253 unsigned int dma_rx_bytes;
254 int dma_tx_in_progress;
255 int dma_rx_in_progress;
256 unsigned int dma_rx_timeout;
257 struct timer_list lpuart_timer;
c9e2e946
JL		 258};
259
ed0bb232 260static const struct of_device_id lpuart_dt_ids[] = {
c9e2e946
JL		 261 {
262 .compatible = "fsl,vf610-lpuart",
263 },
380c966c
JL		 264 {
265 .compatible = "fsl,ls1021a-lpuart",
266 },
c9e2e946
JL		 267 { /* sentinel */ }
268};
269MODULE_DEVICE_TABLE(of, lpuart_dt_ids);
270
f1cd8c87
YY		 271/* Forward declare this for the dma callbacks*/
272static void lpuart_dma_tx_complete(void *arg);
273static void lpuart_dma_rx_complete(void *arg);
274
380c966c
JL		 275static u32 lpuart32_read(void __iomem *addr)
276{
277 return ioread32be(addr);
278}
279
280static void lpuart32_write(u32 val, void __iomem *addr)
281{
282 iowrite32be(val, addr);
283}
284
c9e2e946
JL		 285static void lpuart_stop_tx(struct uart_port *port)
286{
287 unsigned char temp;
288
289 temp = readb(port->membase + UARTCR2);
290 temp &= ~(UARTCR2_TIE | UARTCR2_TCIE);
291 writeb(temp, port->membase + UARTCR2);
292}
293
380c966c
JL		 294static void lpuart32_stop_tx(struct uart_port *port)
295{
296 unsigned long temp;
297
298 temp = lpuart32_read(port->membase + UARTCTRL);
299 temp &= ~(UARTCTRL_TIE | UARTCTRL_TCIE);
300 lpuart32_write(temp, port->membase + UARTCTRL);
301}
302
c9e2e946
JL		 303static void lpuart_stop_rx(struct uart_port *port)
304{
305 unsigned char temp;
306
307 temp = readb(port->membase + UARTCR2);
308 writeb(temp & ~UARTCR2_RE, port->membase + UARTCR2);
309}
310
380c966c
JL		 311static void lpuart32_stop_rx(struct uart_port *port)
312{
313 unsigned long temp;
314
315 temp = lpuart32_read(port->membase + UARTCTRL);
316 lpuart32_write(temp & ~UARTCTRL_RE, port->membase + UARTCTRL);
317}
318
f1cd8c87
YY		 319static void lpuart_copy_rx_to_tty(struct lpuart_port *sport,
320 struct tty_port *tty, int count)
321{
322 int copied;
323
324 sport->port.icount.rx += count;
325
326 if (!tty) {
327 dev_err(sport->port.dev, "No tty port\n");
328 return;
329 }
330
331 dma_sync_single_for_cpu(sport->port.dev, sport->dma_rx_buf_bus,
332 FSL_UART_RX_DMA_BUFFER_SIZE, DMA_FROM_DEVICE);
333 copied = tty_insert_flip_string(tty,
334 ((unsigned char *)(sport->dma_rx_buf_virt)), count);
335
336 if (copied != count) {
337 WARN_ON(1);
338 dev_err(sport->port.dev, "RxData copy to tty layer failed\n");
339 }
340
341 dma_sync_single_for_device(sport->port.dev, sport->dma_rx_buf_bus,
342 FSL_UART_RX_DMA_BUFFER_SIZE, DMA_TO_DEVICE);
343}
344
345static void lpuart_pio_tx(struct lpuart_port *sport)
346{
347 struct circ_buf *xmit = &sport->port.state->xmit;
348 unsigned long flags;
349
350 spin_lock_irqsave(&sport->port.lock, flags);
351
352 while (!uart_circ_empty(xmit) &&
353 readb(sport->port.membase + UARTTCFIFO) < sport->txfifo_size) {
354 writeb(xmit->buf[xmit->tail], sport->port.membase + UARTDR);
355 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
356 sport->port.icount.tx++;
357 }
358
359 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
360 uart_write_wakeup(&sport->port);
361
362 if (uart_circ_empty(xmit))
363 writeb(readb(sport->port.membase + UARTCR5) | UARTCR5_TDMAS,
364 sport->port.membase + UARTCR5);
365
366 spin_unlock_irqrestore(&sport->port.lock, flags);
367}
368
369static int lpuart_dma_tx(struct lpuart_port *sport, unsigned long count)
370{
371 struct circ_buf *xmit = &sport->port.state->xmit;
372 dma_addr_t tx_bus_addr;
373
374 dma_sync_single_for_device(sport->port.dev, sport->dma_tx_buf_bus,
375 UART_XMIT_SIZE, DMA_TO_DEVICE);
ed9891bf 376 sport->dma_tx_bytes = count & ~(sport->txfifo_size - 1);
f1cd8c87
YY		 377 tx_bus_addr = sport->dma_tx_buf_bus + xmit->tail;
378 sport->dma_tx_desc = dmaengine_prep_slave_single(sport->dma_tx_chan,
379 tx_bus_addr, sport->dma_tx_bytes,
380 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
381
382 if (!sport->dma_tx_desc) {
383 dev_err(sport->port.dev, "Not able to get desc for tx\n");
384 return -EIO;
385 }
386
387 sport->dma_tx_desc->callback = lpuart_dma_tx_complete;
388 sport->dma_tx_desc->callback_param = sport;
389 sport->dma_tx_in_progress = 1;
390 sport->dma_tx_cookie = dmaengine_submit(sport->dma_tx_desc);
391 dma_async_issue_pending(sport->dma_tx_chan);
392
393 return 0;
394}
395
396static void lpuart_prepare_tx(struct lpuart_port *sport)
397{
398 struct circ_buf *xmit = &sport->port.state->xmit;
399 unsigned long count = CIRC_CNT_TO_END(xmit->head,
400 xmit->tail, UART_XMIT_SIZE);
401
402 if (!count)
403 return;
404
ed9891bf 405 if (count < sport->txfifo_size)
f1cd8c87
YY		 406 writeb(readb(sport->port.membase + UARTCR5) & ~UARTCR5_TDMAS,
407 sport->port.membase + UARTCR5);
408 else {
409 writeb(readb(sport->port.membase + UARTCR5) | UARTCR5_TDMAS,
410 sport->port.membase + UARTCR5);
411 lpuart_dma_tx(sport, count);
412 }
413}
414
415static void lpuart_dma_tx_complete(void *arg)
416{
417 struct lpuart_port *sport = arg;
418 struct circ_buf *xmit = &sport->port.state->xmit;
419 unsigned long flags;
420
421 async_tx_ack(sport->dma_tx_desc);
422
423 spin_lock_irqsave(&sport->port.lock, flags);
424
425 xmit->tail = (xmit->tail + sport->dma_tx_bytes) & (UART_XMIT_SIZE - 1);
426 sport->dma_tx_in_progress = 0;
427
428 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
429 uart_write_wakeup(&sport->port);
430
431 lpuart_prepare_tx(sport);
432
433 spin_unlock_irqrestore(&sport->port.lock, flags);
434}
435
436static int lpuart_dma_rx(struct lpuart_port *sport)
437{
438 dma_sync_single_for_device(sport->port.dev, sport->dma_rx_buf_bus,
439 FSL_UART_RX_DMA_BUFFER_SIZE, DMA_TO_DEVICE);
440 sport->dma_rx_desc = dmaengine_prep_slave_single(sport->dma_rx_chan,
441 sport->dma_rx_buf_bus, FSL_UART_RX_DMA_BUFFER_SIZE,
442 DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT);
443
444 if (!sport->dma_rx_desc) {
445 dev_err(sport->port.dev, "Not able to get desc for rx\n");
446 return -EIO;
447 }
448
449 sport->dma_rx_desc->callback = lpuart_dma_rx_complete;
450 sport->dma_rx_desc->callback_param = sport;
451 sport->dma_rx_in_progress = 1;
452 sport->dma_rx_cookie = dmaengine_submit(sport->dma_rx_desc);
453 dma_async_issue_pending(sport->dma_rx_chan);
454
455 return 0;
456}
457
bfc2e07f
SA		 458static void lpuart_flush_buffer(struct uart_port *port)
459{
460 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
461 if (sport->lpuart_dma_tx_use) {
462 dmaengine_terminate_all(sport->dma_tx_chan);
463 sport->dma_tx_in_progress = 0;
464 }
465}
466
f1cd8c87
YY		 467static void lpuart_dma_rx_complete(void *arg)
468{
469 struct lpuart_port *sport = arg;
470 struct tty_port *port = &sport->port.state->port;
471 unsigned long flags;
472
473 async_tx_ack(sport->dma_rx_desc);
011f5bde 474 mod_timer(&sport->lpuart_timer, jiffies + sport->dma_rx_timeout);
f1cd8c87
YY		 475
476 spin_lock_irqsave(&sport->port.lock, flags);
477
478 sport->dma_rx_in_progress = 0;
479 lpuart_copy_rx_to_tty(sport, port, FSL_UART_RX_DMA_BUFFER_SIZE);
480 tty_flip_buffer_push(port);
481 lpuart_dma_rx(sport);
482
483 spin_unlock_irqrestore(&sport->port.lock, flags);
484}
485
486static void lpuart_timer_func(unsigned long data)
487{
488 struct lpuart_port *sport = (struct lpuart_port *)data;
489 struct tty_port *port = &sport->port.state->port;
490 struct dma_tx_state state;
491 unsigned long flags;
492 unsigned char temp;
493 int count;
494
495 del_timer(&sport->lpuart_timer);
496 dmaengine_pause(sport->dma_rx_chan);
497 dmaengine_tx_status(sport->dma_rx_chan, sport->dma_rx_cookie, &state);
498 dmaengine_terminate_all(sport->dma_rx_chan);
499 count = FSL_UART_RX_DMA_BUFFER_SIZE - state.residue;
500 async_tx_ack(sport->dma_rx_desc);
501
502 spin_lock_irqsave(&sport->port.lock, flags);
503
504 sport->dma_rx_in_progress = 0;
505 lpuart_copy_rx_to_tty(sport, port, count);
506 tty_flip_buffer_push(port);
507 temp = readb(sport->port.membase + UARTCR5);
508 writeb(temp & ~UARTCR5_RDMAS, sport->port.membase + UARTCR5);
509
510 spin_unlock_irqrestore(&sport->port.lock, flags);
511}
512
513static inline void lpuart_prepare_rx(struct lpuart_port *sport)
514{
515 unsigned long flags;
516 unsigned char temp;
517
518 spin_lock_irqsave(&sport->port.lock, flags);
519
f1cd8c87
YY		 520 sport->lpuart_timer.expires = jiffies + sport->dma_rx_timeout;
521 add_timer(&sport->lpuart_timer);
522
523 lpuart_dma_rx(sport);
524 temp = readb(sport->port.membase + UARTCR5);
525 writeb(temp | UARTCR5_RDMAS, sport->port.membase + UARTCR5);
526
527 spin_unlock_irqrestore(&sport->port.lock, flags);
528}
529
c9e2e946
JL		 530static inline void lpuart_transmit_buffer(struct lpuart_port *sport)
531{
532 struct circ_buf *xmit = &sport->port.state->xmit;
533
534 while (!uart_circ_empty(xmit) &&
535 (readb(sport->port.membase + UARTTCFIFO) < sport->txfifo_size)) {
536 writeb(xmit->buf[xmit->tail], sport->port.membase + UARTDR);
537 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
538 sport->port.icount.tx++;
539 }
540
541 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
542 uart_write_wakeup(&sport->port);
543
544 if (uart_circ_empty(xmit))
545 lpuart_stop_tx(&sport->port);
546}
547
380c966c
JL		 548static inline void lpuart32_transmit_buffer(struct lpuart_port *sport)
549{
550 struct circ_buf *xmit = &sport->port.state->xmit;
551 unsigned long txcnt;
552
553 txcnt = lpuart32_read(sport->port.membase + UARTWATER);
554 txcnt = txcnt >> UARTWATER_TXCNT_OFF;
555 txcnt &= UARTWATER_COUNT_MASK;
556 while (!uart_circ_empty(xmit) && (txcnt < sport->txfifo_size)) {
557 lpuart32_write(xmit->buf[xmit->tail], sport->port.membase + UARTDATA);
558 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
559 sport->port.icount.tx++;
560 txcnt = lpuart32_read(sport->port.membase + UARTWATER);
561 txcnt = txcnt >> UARTWATER_TXCNT_OFF;
562 txcnt &= UARTWATER_COUNT_MASK;
563 }
564
565 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
566 uart_write_wakeup(&sport->port);
567
568 if (uart_circ_empty(xmit))
569 lpuart32_stop_tx(&sport->port);
570}
571
c9e2e946
JL		 572static void lpuart_start_tx(struct uart_port *port)
573{
f1cd8c87
YY		 574 struct lpuart_port *sport = container_of(port,
575 struct lpuart_port, port);
576 struct circ_buf *xmit = &sport->port.state->xmit;
c9e2e946
JL		 577 unsigned char temp;
578
579 temp = readb(port->membase + UARTCR2);
580 writeb(temp | UARTCR2_TIE, port->membase + UARTCR2);
581
4a818c43 582 if (sport->lpuart_dma_tx_use) {
f1cd8c87
YY		 583 if (!uart_circ_empty(xmit) && !sport->dma_tx_in_progress)
584 lpuart_prepare_tx(sport);
585 } else {
586 if (readb(port->membase + UARTSR1) & UARTSR1_TDRE)
587 lpuart_transmit_buffer(sport);
588 }
c9e2e946
JL		 589}
590
380c966c
JL		 591static void lpuart32_start_tx(struct uart_port *port)
592{
593 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
594 unsigned long temp;
595
596 temp = lpuart32_read(port->membase + UARTCTRL);
597 lpuart32_write(temp | UARTCTRL_TIE, port->membase + UARTCTRL);
598
599 if (lpuart32_read(port->membase + UARTSTAT) & UARTSTAT_TDRE)
600 lpuart32_transmit_buffer(sport);
601}
602
c9e2e946
JL		 603static irqreturn_t lpuart_txint(int irq, void *dev_id)
604{
605 struct lpuart_port *sport = dev_id;
606 struct circ_buf *xmit = &sport->port.state->xmit;
607 unsigned long flags;
608
609 spin_lock_irqsave(&sport->port.lock, flags);
610 if (sport->port.x_char) {
380c966c
JL		 611 if (sport->lpuart32)
612 lpuart32_write(sport->port.x_char, sport->port.membase + UARTDATA);
613 else
614 writeb(sport->port.x_char, sport->port.membase + UARTDR);
c9e2e946
JL		 615 goto out;
616 }
617
618 if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) {
380c966c
JL		 619 if (sport->lpuart32)
620 lpuart32_stop_tx(&sport->port);
621 else
622 lpuart_stop_tx(&sport->port);
c9e2e946
JL		 623 goto out;
624 }
625
380c966c
JL		 626 if (sport->lpuart32)
627 lpuart32_transmit_buffer(sport);
628 else
629 lpuart_transmit_buffer(sport);
c9e2e946
JL		 630
631 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
632 uart_write_wakeup(&sport->port);
633
634out:
635 spin_unlock_irqrestore(&sport->port.lock, flags);
636 return IRQ_HANDLED;
637}
638
639static irqreturn_t lpuart_rxint(int irq, void *dev_id)
640{
641 struct lpuart_port *sport = dev_id;
642 unsigned int flg, ignored = 0;
643 struct tty_port *port = &sport->port.state->port;
644 unsigned long flags;
645 unsigned char rx, sr;
646
647 spin_lock_irqsave(&sport->port.lock, flags);
648
649 while (!(readb(sport->port.membase + UARTSFIFO) & UARTSFIFO_RXEMPT)) {
650 flg = TTY_NORMAL;
651 sport->port.icount.rx++;
652 /*
653 * to clear the FE, OR, NF, FE, PE flags,
654 * read SR1 then read DR
655 */
656 sr = readb(sport->port.membase + UARTSR1);
657 rx = readb(sport->port.membase + UARTDR);
658
659 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx))
660 continue;
661
662 if (sr & (UARTSR1_PE | UARTSR1_OR | UARTSR1_FE)) {
663 if (sr & UARTSR1_PE)
664 sport->port.icount.parity++;
665 else if (sr & UARTSR1_FE)
666 sport->port.icount.frame++;
667
668 if (sr & UARTSR1_OR)
669 sport->port.icount.overrun++;
670
671 if (sr & sport->port.ignore_status_mask) {
672 if (++ignored > 100)
673 goto out;
674 continue;
675 }
676
677 sr &= sport->port.read_status_mask;
678
679 if (sr & UARTSR1_PE)
680 flg = TTY_PARITY;
681 else if (sr & UARTSR1_FE)
682 flg = TTY_FRAME;
683
684 if (sr & UARTSR1_OR)
685 flg = TTY_OVERRUN;
686
687#ifdef SUPPORT_SYSRQ
688 sport->port.sysrq = 0;
689#endif
690 }
691
692 tty_insert_flip_char(port, rx, flg);
693 }
694
695out:
696 spin_unlock_irqrestore(&sport->port.lock, flags);
697
698 tty_flip_buffer_push(port);
699 return IRQ_HANDLED;
700}
701
380c966c
JL		 702static irqreturn_t lpuart32_rxint(int irq, void *dev_id)
703{
704 struct lpuart_port *sport = dev_id;
705 unsigned int flg, ignored = 0;
706 struct tty_port *port = &sport->port.state->port;
707 unsigned long flags;
708 unsigned long rx, sr;
709
710 spin_lock_irqsave(&sport->port.lock, flags);
711
712 while (!(lpuart32_read(sport->port.membase + UARTFIFO) & UARTFIFO_RXEMPT)) {
713 flg = TTY_NORMAL;
714 sport->port.icount.rx++;
715 /*
716 * to clear the FE, OR, NF, FE, PE flags,
717 * read STAT then read DATA reg
718 */
719 sr = lpuart32_read(sport->port.membase + UARTSTAT);
720 rx = lpuart32_read(sport->port.membase + UARTDATA);
721 rx &= 0x3ff;
722
723 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx))
724 continue;
725
726 if (sr & (UARTSTAT_PE | UARTSTAT_OR | UARTSTAT_FE)) {
727 if (sr & UARTSTAT_PE)
728 sport->port.icount.parity++;
729 else if (sr & UARTSTAT_FE)
730 sport->port.icount.frame++;
731
732 if (sr & UARTSTAT_OR)
733 sport->port.icount.overrun++;
734
735 if (sr & sport->port.ignore_status_mask) {
736 if (++ignored > 100)
737 goto out;
738 continue;
739 }
740
741 sr &= sport->port.read_status_mask;
742
743 if (sr & UARTSTAT_PE)
744 flg = TTY_PARITY;
745 else if (sr & UARTSTAT_FE)
746 flg = TTY_FRAME;
747
748 if (sr & UARTSTAT_OR)
749 flg = TTY_OVERRUN;
750
751#ifdef SUPPORT_SYSRQ
752 sport->port.sysrq = 0;
753#endif
754 }
755
756 tty_insert_flip_char(port, rx, flg);
757 }
758
759out:
760 spin_unlock_irqrestore(&sport->port.lock, flags);
761
762 tty_flip_buffer_push(port);
763 return IRQ_HANDLED;
764}
765
c9e2e946
JL		 766static irqreturn_t lpuart_int(int irq, void *dev_id)
767{
768 struct lpuart_port *sport = dev_id;
5f1437f6 769 unsigned char sts, crdma;
c9e2e946
JL		 770
771 sts = readb(sport->port.membase + UARTSR1);
5f1437f6 772 crdma = readb(sport->port.membase + UARTCR5);
c9e2e946 773
5f1437f6 774 if (sts & UARTSR1_RDRF && !(crdma & UARTCR5_RDMAS)) {
4a818c43 775 if (sport->lpuart_dma_rx_use)
f1cd8c87
YY		 776 lpuart_prepare_rx(sport);
777 else
778 lpuart_rxint(irq, dev_id);
779 }
5f1437f6 780 if (sts & UARTSR1_TDRE && !(crdma & UARTCR5_TDMAS)) {
4a818c43 781 if (sport->lpuart_dma_tx_use)
f1cd8c87
YY		 782 lpuart_pio_tx(sport);
783 else
784 lpuart_txint(irq, dev_id);
785 }
c9e2e946
JL		 786
787 return IRQ_HANDLED;
788}
789
380c966c
JL		 790static irqreturn_t lpuart32_int(int irq, void *dev_id)
791{
792 struct lpuart_port *sport = dev_id;
793 unsigned long sts, rxcount;
794
795 sts = lpuart32_read(sport->port.membase + UARTSTAT);
796 rxcount = lpuart32_read(sport->port.membase + UARTWATER);
797 rxcount = rxcount >> UARTWATER_RXCNT_OFF;
798
799 if (sts & UARTSTAT_RDRF || rxcount > 0)
800 lpuart32_rxint(irq, dev_id);
801
802 if ((sts & UARTSTAT_TDRE) &&
803 !(lpuart32_read(sport->port.membase + UARTBAUD) & UARTBAUD_TDMAE))
804 lpuart_txint(irq, dev_id);
805
806 lpuart32_write(sts, sport->port.membase + UARTSTAT);
807 return IRQ_HANDLED;
808}
809
c9e2e946
JL		 810/* return TIOCSER_TEMT when transmitter is not busy */
811static unsigned int lpuart_tx_empty(struct uart_port *port)
812{
b70b6361
SA		 813 struct lpuart_port *sport = container_of(port,
814 struct lpuart_port, port);
815 unsigned char sr1 = readb(port->membase + UARTSR1);
816 unsigned char sfifo = readb(port->membase + UARTSFIFO);
817
818 if (sport->dma_tx_in_progress)
819 return 0;
820
821 if (sr1 & UARTSR1_TC && sfifo & UARTSFIFO_TXEMPT)
822 return TIOCSER_TEMT;
823
824 return 0;
c9e2e946
JL		 825}
826
380c966c
JL		 827static unsigned int lpuart32_tx_empty(struct uart_port *port)
828{
829 return (lpuart32_read(port->membase + UARTSTAT) & UARTSTAT_TC) ?
830 TIOCSER_TEMT : 0;
831}
832
c9e2e946
JL		 833static unsigned int lpuart_get_mctrl(struct uart_port *port)
834{
835 unsigned int temp = 0;
836 unsigned char reg;
837
838 reg = readb(port->membase + UARTMODEM);
839 if (reg & UARTMODEM_TXCTSE)
840 temp |= TIOCM_CTS;
841
842 if (reg & UARTMODEM_RXRTSE)
843 temp |= TIOCM_RTS;
844
845 return temp;
846}
847
380c966c
JL		 848static unsigned int lpuart32_get_mctrl(struct uart_port *port)
849{
850 unsigned int temp = 0;
851 unsigned long reg;
852
853 reg = lpuart32_read(port->membase + UARTMODIR);
854 if (reg & UARTMODIR_TXCTSE)
855 temp |= TIOCM_CTS;
856
857 if (reg & UARTMODIR_RXRTSE)
858 temp |= TIOCM_RTS;
859
860 return temp;
861}
862
c9e2e946
JL		 863static void lpuart_set_mctrl(struct uart_port *port, unsigned int mctrl)
864{
865 unsigned char temp;
866
867 temp = readb(port->membase + UARTMODEM) &
868 ~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE);
869
870 if (mctrl & TIOCM_RTS)
871 temp |= UARTMODEM_RXRTSE;
872
873 if (mctrl & TIOCM_CTS)
874 temp |= UARTMODEM_TXCTSE;
875
876 writeb(temp, port->membase + UARTMODEM);
877}
878
380c966c
JL		 879static void lpuart32_set_mctrl(struct uart_port *port, unsigned int mctrl)
880{
881 unsigned long temp;
882
883 temp = lpuart32_read(port->membase + UARTMODIR) &
884 ~(UARTMODIR_RXRTSE | UARTMODIR_TXCTSE);
885
886 if (mctrl & TIOCM_RTS)
887 temp |= UARTMODIR_RXRTSE;
888
889 if (mctrl & TIOCM_CTS)
890 temp |= UARTMODIR_TXCTSE;
891
892 lpuart32_write(temp, port->membase + UARTMODIR);
893}
894
c9e2e946
JL		 895static void lpuart_break_ctl(struct uart_port *port, int break_state)
896{
897 unsigned char temp;
898
899 temp = readb(port->membase + UARTCR2) & ~UARTCR2_SBK;
900
901 if (break_state != 0)
902 temp |= UARTCR2_SBK;
903
904 writeb(temp, port->membase + UARTCR2);
905}
906
380c966c
JL		 907static void lpuart32_break_ctl(struct uart_port *port, int break_state)
908{
909 unsigned long temp;
910
911 temp = lpuart32_read(port->membase + UARTCTRL) & ~UARTCTRL_SBK;
912
913 if (break_state != 0)
914 temp |= UARTCTRL_SBK;
915
916 lpuart32_write(temp, port->membase + UARTCTRL);
917}
918
c9e2e946
JL		 919static void lpuart_setup_watermark(struct lpuart_port *sport)
920{
921 unsigned char val, cr2;
bc764b8f 922 unsigned char cr2_saved;
c9e2e946
JL		 923
924 cr2 = readb(sport->port.membase + UARTCR2);
bc764b8f 925 cr2_saved = cr2;
c9e2e946
JL		 926 cr2 &= ~(UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_TE |
927 UARTCR2_RIE | UARTCR2_RE);
928 writeb(cr2, sport->port.membase + UARTCR2);
929
c9e2e946 930 val = readb(sport->port.membase + UARTPFIFO);
c9e2e946
JL		 931 writeb(val | UARTPFIFO_TXFE | UARTPFIFO_RXFE,
932 sport->port.membase + UARTPFIFO);
933
8e4934c6
SA		 934 /* explicitly clear RDRF */
935 readb(sport->port.membase + UARTSR1);
936
c9e2e946
JL		 937 /* flush Tx and Rx FIFO */
938 writeb(UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH,
939 sport->port.membase + UARTCFIFO);
940
f1cd8c87 941 writeb(0, sport->port.membase + UARTTWFIFO);
c9e2e946 942 writeb(1, sport->port.membase + UARTRWFIFO);
bc764b8f
SG		 943
944 /* Restore cr2 */
945 writeb(cr2_saved, sport->port.membase + UARTCR2);
c9e2e946
JL		 946}
947
380c966c
JL		 948static void lpuart32_setup_watermark(struct lpuart_port *sport)
949{
950 unsigned long val, ctrl;
951 unsigned long ctrl_saved;
952
953 ctrl = lpuart32_read(sport->port.membase + UARTCTRL);
954 ctrl_saved = ctrl;
955 ctrl &= ~(UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_TE |
956 UARTCTRL_RIE | UARTCTRL_RE);
957 lpuart32_write(ctrl, sport->port.membase + UARTCTRL);
958
959 /* enable FIFO mode */
960 val = lpuart32_read(sport->port.membase + UARTFIFO);
961 val |= UARTFIFO_TXFE | UARTFIFO_RXFE;
962 val |= UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH;
963 lpuart32_write(val, sport->port.membase + UARTFIFO);
964
965 /* set the watermark */
966 val = (0x1 << UARTWATER_RXWATER_OFF) | (0x0 << UARTWATER_TXWATER_OFF);
967 lpuart32_write(val, sport->port.membase + UARTWATER);
968
969 /* Restore cr2 */
970 lpuart32_write(ctrl_saved, sport->port.membase + UARTCTRL);
971}
972
f1cd8c87
YY		 973static int lpuart_dma_tx_request(struct uart_port *port)
974{
975 struct lpuart_port *sport = container_of(port,
976 struct lpuart_port, port);
f1cd8c87
YY		 977 struct dma_slave_config dma_tx_sconfig;
978 dma_addr_t dma_bus;
979 unsigned char *dma_buf;
980 int ret;
981
4a818c43 982 dma_bus = dma_map_single(sport->dma_tx_chan->device->dev,
f1cd8c87
YY		 983 sport->port.state->xmit.buf,
984 UART_XMIT_SIZE, DMA_TO_DEVICE);
985
4a818c43 986 if (dma_mapping_error(sport->dma_tx_chan->device->dev, dma_bus)) {
f1cd8c87 987 dev_err(sport->port.dev, "dma_map_single tx failed\n");
f1cd8c87
YY		 988 return -ENOMEM;
989 }
990
991 dma_buf = sport->port.state->xmit.buf;
992 dma_tx_sconfig.dst_addr = sport->port.mapbase + UARTDR;
993 dma_tx_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
ed9891bf 994 dma_tx_sconfig.dst_maxburst = sport->txfifo_size;
f1cd8c87 995 dma_tx_sconfig.direction = DMA_MEM_TO_DEV;
4a818c43 996 ret = dmaengine_slave_config(sport->dma_tx_chan, &dma_tx_sconfig);
f1cd8c87
YY		 997
998 if (ret < 0) {
999 dev_err(sport->port.dev,
1000 "Dma slave config failed, err = %d\n", ret);
f1cd8c87
YY		 1001 return ret;
1002 }
1003
f1cd8c87
YY		 1004 sport->dma_tx_buf_virt = dma_buf;
1005 sport->dma_tx_buf_bus = dma_bus;
1006 sport->dma_tx_in_progress = 0;
1007
1008 return 0;
1009}
1010
1011static int lpuart_dma_rx_request(struct uart_port *port)
1012{
1013 struct lpuart_port *sport = container_of(port,
1014 struct lpuart_port, port);
f1cd8c87
YY		 1015 struct dma_slave_config dma_rx_sconfig;
1016 dma_addr_t dma_bus;
1017 unsigned char *dma_buf;
1018 int ret;
1019
f1cd8c87
YY		 1020 dma_buf = devm_kzalloc(sport->port.dev,
1021 FSL_UART_RX_DMA_BUFFER_SIZE, GFP_KERNEL);
1022
1023 if (!dma_buf) {
1024 dev_err(sport->port.dev, "Dma rx alloc failed\n");
f1cd8c87
YY		 1025 return -ENOMEM;
1026 }
1027
4a818c43 1028 dma_bus = dma_map_single(sport->dma_rx_chan->device->dev, dma_buf,
f1cd8c87
YY		 1029 FSL_UART_RX_DMA_BUFFER_SIZE, DMA_FROM_DEVICE);
1030
4a818c43 1031 if (dma_mapping_error(sport->dma_rx_chan->device->dev, dma_bus)) {
f1cd8c87 1032 dev_err(sport->port.dev, "dma_map_single rx failed\n");
f1cd8c87
YY		 1033 return -ENOMEM;
1034 }
1035
1036 dma_rx_sconfig.src_addr = sport->port.mapbase + UARTDR;
1037 dma_rx_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1038 dma_rx_sconfig.src_maxburst = 1;
1039 dma_rx_sconfig.direction = DMA_DEV_TO_MEM;
4a818c43 1040 ret = dmaengine_slave_config(sport->dma_rx_chan, &dma_rx_sconfig);
f1cd8c87
YY		 1041
1042 if (ret < 0) {
1043 dev_err(sport->port.dev,
1044 "Dma slave config failed, err = %d\n", ret);
f1cd8c87
YY		 1045 return ret;
1046 }
1047
f1cd8c87
YY		 1048 sport->dma_rx_buf_virt = dma_buf;
1049 sport->dma_rx_buf_bus = dma_bus;
1050 sport->dma_rx_in_progress = 0;
1051
f1cd8c87
YY		 1052 return 0;
1053}
1054
1055static void lpuart_dma_tx_free(struct uart_port *port)
1056{
1057 struct lpuart_port *sport = container_of(port,
1058 struct lpuart_port, port);
f1cd8c87
YY		 1059
1060 dma_unmap_single(sport->port.dev, sport->dma_tx_buf_bus,
1061 UART_XMIT_SIZE, DMA_TO_DEVICE);
4a818c43 1062
f1cd8c87
YY		 1063 sport->dma_tx_buf_bus = 0;
1064 sport->dma_tx_buf_virt = NULL;
f1cd8c87
YY		 1065}
1066
1067static void lpuart_dma_rx_free(struct uart_port *port)
1068{
1069 struct lpuart_port *sport = container_of(port,
1070 struct lpuart_port, port);
f1cd8c87
YY		 1071
1072 dma_unmap_single(sport->port.dev, sport->dma_rx_buf_bus,
1073 FSL_UART_RX_DMA_BUFFER_SIZE, DMA_FROM_DEVICE);
1074
f1cd8c87
YY		 1075 sport->dma_rx_buf_bus = 0;
1076 sport->dma_rx_buf_virt = NULL;
f1cd8c87
YY		 1077}
1078
c9e2e946
JL		 1079static int lpuart_startup(struct uart_port *port)
1080{
1081 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1082 int ret;
1083 unsigned long flags;
1084 unsigned char temp;
1085
ed9891bf
SA		 1086 /* determine FIFO size and enable FIFO mode */
1087 temp = readb(sport->port.membase + UARTPFIFO);
1088
1089 sport->txfifo_size = 0x1 << (((temp >> UARTPFIFO_TXSIZE_OFF) &
1090 UARTPFIFO_FIFOSIZE_MASK) + 1);
1091
4e8f2459
SA		 1092 sport->port.fifosize = sport->txfifo_size;
1093
ed9891bf
SA		 1094 sport->rxfifo_size = 0x1 << (((temp >> UARTPFIFO_RXSIZE_OFF) &
1095 UARTPFIFO_FIFOSIZE_MASK) + 1);
1096
4a818c43
SA		 1097 if (sport->dma_rx_chan && !lpuart_dma_rx_request(port)) {
1098 sport->lpuart_dma_rx_use = true;
4a8588a1
SA		 1099 setup_timer(&sport->lpuart_timer, lpuart_timer_func,
1100 (unsigned long)sport);
4a818c43
SA		 1101 } else
1102 sport->lpuart_dma_rx_use = false;
1103
1104
1105 if (sport->dma_tx_chan && !lpuart_dma_tx_request(port)) {
1106 sport->lpuart_dma_tx_use = true;
f1cd8c87 1107 temp = readb(port->membase + UARTCR5);
5f1437f6 1108 temp &= ~UARTCR5_RDMAS;
f1cd8c87 1109 writeb(temp | UARTCR5_TDMAS, port->membase + UARTCR5);
4a818c43
SA		 1110 } else
1111 sport->lpuart_dma_tx_use = false;
f1cd8c87 1112
c9e2e946
JL		 1113 ret = devm_request_irq(port->dev, port->irq, lpuart_int, 0,
1114 DRIVER_NAME, sport);
1115 if (ret)
1116 return ret;
1117
1118 spin_lock_irqsave(&sport->port.lock, flags);
1119
1120 lpuart_setup_watermark(sport);
1121
1122 temp = readb(sport->port.membase + UARTCR2);
1123 temp |= (UARTCR2_RIE | UARTCR2_TIE | UARTCR2_RE | UARTCR2_TE);
1124 writeb(temp, sport->port.membase + UARTCR2);
1125
1126 spin_unlock_irqrestore(&sport->port.lock, flags);
1127 return 0;
1128}
1129
380c966c
JL		 1130static int lpuart32_startup(struct uart_port *port)
1131{
1132 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1133 int ret;
1134 unsigned long flags;
1135 unsigned long temp;
1136
1137 /* determine FIFO size */
1138 temp = lpuart32_read(sport->port.membase + UARTFIFO);
1139
1140 sport->txfifo_size = 0x1 << (((temp >> UARTFIFO_TXSIZE_OFF) &
1141 UARTFIFO_FIFOSIZE_MASK) - 1);
1142
1143 sport->rxfifo_size = 0x1 << (((temp >> UARTFIFO_RXSIZE_OFF) &
1144 UARTFIFO_FIFOSIZE_MASK) - 1);
1145
1146 ret = devm_request_irq(port->dev, port->irq, lpuart32_int, 0,
1147 DRIVER_NAME, sport);
1148 if (ret)
1149 return ret;
1150
1151 spin_lock_irqsave(&sport->port.lock, flags);
1152
1153 lpuart32_setup_watermark(sport);
1154
1155 temp = lpuart32_read(sport->port.membase + UARTCTRL);
1156 temp |= (UARTCTRL_RIE | UARTCTRL_TIE | UARTCTRL_RE | UARTCTRL_TE);
1157 temp |= UARTCTRL_ILIE;
1158 lpuart32_write(temp, sport->port.membase + UARTCTRL);
1159
1160 spin_unlock_irqrestore(&sport->port.lock, flags);
1161 return 0;
1162}
1163
c9e2e946
JL		 1164static void lpuart_shutdown(struct uart_port *port)
1165{
1166 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1167 unsigned char temp;
1168 unsigned long flags;
1169
1170 spin_lock_irqsave(&port->lock, flags);
1171
1172 /* disable Rx/Tx and interrupts */
1173 temp = readb(port->membase + UARTCR2);
1174 temp &= ~(UARTCR2_TE | UARTCR2_RE |
1175 UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_RIE);
1176 writeb(temp, port->membase + UARTCR2);
1177
1178 spin_unlock_irqrestore(&port->lock, flags);
1179
1180 devm_free_irq(port->dev, port->irq, sport);
f1cd8c87 1181
4a818c43
SA		 1182 if (sport->lpuart_dma_rx_use) {
1183 lpuart_dma_rx_free(&sport->port);
4a8588a1 1184 del_timer_sync(&sport->lpuart_timer);
f1cd8c87 1185 }
4a818c43
SA		 1186
1187 if (sport->lpuart_dma_tx_use)
1188 lpuart_dma_tx_free(&sport->port);
c9e2e946
JL		 1189}
1190
380c966c
JL		 1191static void lpuart32_shutdown(struct uart_port *port)
1192{
1193 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1194 unsigned long temp;
1195 unsigned long flags;
1196
1197 spin_lock_irqsave(&port->lock, flags);
1198
1199 /* disable Rx/Tx and interrupts */
1200 temp = lpuart32_read(port->membase + UARTCTRL);
1201 temp &= ~(UARTCTRL_TE | UARTCTRL_RE |
1202 UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_RIE);
1203 lpuart32_write(temp, port->membase + UARTCTRL);
1204
1205 spin_unlock_irqrestore(&port->lock, flags);
1206
1207 devm_free_irq(port->dev, port->irq, sport);
1208}
1209
c9e2e946
JL		 1210static void
1211lpuart_set_termios(struct uart_port *port, struct ktermios *termios,
1212 struct ktermios *old)
1213{
1214 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1215 unsigned long flags;
1216 unsigned char cr1, old_cr1, old_cr2, cr4, bdh, modem;
1217 unsigned int baud;
1218 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
1219 unsigned int sbr, brfa;
1220
1221 cr1 = old_cr1 = readb(sport->port.membase + UARTCR1);
1222 old_cr2 = readb(sport->port.membase + UARTCR2);
1223 cr4 = readb(sport->port.membase + UARTCR4);
1224 bdh = readb(sport->port.membase + UARTBDH);
1225 modem = readb(sport->port.membase + UARTMODEM);
1226 /*
1227 * only support CS8 and CS7, and for CS7 must enable PE.
1228 * supported mode:
1229 * - (7,e/o,1)
1230 * - (8,n,1)
1231 * - (8,m/s,1)
1232 * - (8,e/o,1)
1233 */
1234 while ((termios->c_cflag & CSIZE) != CS8 &&
1235 (termios->c_cflag & CSIZE) != CS7) {
1236 termios->c_cflag &= ~CSIZE;
1237 termios->c_cflag |= old_csize;
1238 old_csize = CS8;
1239 }
1240
1241 if ((termios->c_cflag & CSIZE) == CS8 ||
1242 (termios->c_cflag & CSIZE) == CS7)
1243 cr1 = old_cr1 & ~UARTCR1_M;
1244
1245 if (termios->c_cflag & CMSPAR) {
1246 if ((termios->c_cflag & CSIZE) != CS8) {
1247 termios->c_cflag &= ~CSIZE;
1248 termios->c_cflag |= CS8;
1249 }
1250 cr1 |= UARTCR1_M;
1251 }
1252
1253 if (termios->c_cflag & CRTSCTS) {
1254 modem |= (UARTMODEM_RXRTSE | UARTMODEM_TXCTSE);
1255 } else {
1256 termios->c_cflag &= ~CRTSCTS;
1257 modem &= ~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE);
1258 }
1259
1260 if (termios->c_cflag & CSTOPB)
1261 termios->c_cflag &= ~CSTOPB;
1262
1263 /* parity must be enabled when CS7 to match 8-bits format */
1264 if ((termios->c_cflag & CSIZE) == CS7)
1265 termios->c_cflag |= PARENB;
1266
1267 if ((termios->c_cflag & PARENB)) {
1268 if (termios->c_cflag & CMSPAR) {
1269 cr1 &= ~UARTCR1_PE;
1270 cr1 |= UARTCR1_M;
1271 } else {
1272 cr1 |= UARTCR1_PE;
1273 if ((termios->c_cflag & CSIZE) == CS8)
1274 cr1 |= UARTCR1_M;
1275 if (termios->c_cflag & PARODD)
1276 cr1 |= UARTCR1_PT;
1277 else
1278 cr1 &= ~UARTCR1_PT;
1279 }
1280 }
1281
1282 /* ask the core to calculate the divisor */
1283 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
1284
1285 spin_lock_irqsave(&sport->port.lock, flags);
1286
1287 sport->port.read_status_mask = 0;
1288 if (termios->c_iflag & INPCK)
1289 sport->port.read_status_mask |= (UARTSR1_FE | UARTSR1_PE);
ef8b9ddc 1290 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
c9e2e946
JL		 1291 sport->port.read_status_mask |= UARTSR1_FE;
1292
1293 /* characters to ignore */
1294 sport->port.ignore_status_mask = 0;
1295 if (termios->c_iflag & IGNPAR)
1296 sport->port.ignore_status_mask |= UARTSR1_PE;
1297 if (termios->c_iflag & IGNBRK) {
1298 sport->port.ignore_status_mask |= UARTSR1_FE;
1299 /*
1300 * if we're ignoring parity and break indicators,
1301 * ignore overruns too (for real raw support).
1302 */
1303 if (termios->c_iflag & IGNPAR)
1304 sport->port.ignore_status_mask |= UARTSR1_OR;
1305 }
1306
1307 /* update the per-port timeout */
1308 uart_update_timeout(port, termios->c_cflag, baud);
1309
4a818c43 1310 if (sport->lpuart_dma_rx_use) {
90abef91
SA		 1311 /* Calculate delay for 1.5 DMA buffers */
1312 sport->dma_rx_timeout = (sport->port.timeout - HZ / 50) *
1313 FSL_UART_RX_DMA_BUFFER_SIZE * 3 /
1314 sport->rxfifo_size / 2;
1315 dev_dbg(port->dev, "DMA Rx t-out %ums, tty t-out %u jiffies\n",
1316 sport->dma_rx_timeout * 1000 / HZ, sport->port.timeout);
1317 if (sport->dma_rx_timeout < msecs_to_jiffies(20))
1318 sport->dma_rx_timeout = msecs_to_jiffies(20);
1319 }
1320
c9e2e946
JL		 1321 /* wait transmit engin complete */
1322 while (!(readb(sport->port.membase + UARTSR1) & UARTSR1_TC))
1323 barrier();
1324
1325 /* disable transmit and receive */
1326 writeb(old_cr2 & ~(UARTCR2_TE | UARTCR2_RE),
1327 sport->port.membase + UARTCR2);
1328
1329 sbr = sport->port.uartclk / (16 * baud);
1330 brfa = ((sport->port.uartclk - (16 * sbr * baud)) * 2) / baud;
1331 bdh &= ~UARTBDH_SBR_MASK;
1332 bdh |= (sbr >> 8) & 0x1F;
1333 cr4 &= ~UARTCR4_BRFA_MASK;
1334 brfa &= UARTCR4_BRFA_MASK;
1335 writeb(cr4 | brfa, sport->port.membase + UARTCR4);
1336 writeb(bdh, sport->port.membase + UARTBDH);
1337 writeb(sbr & 0xFF, sport->port.membase + UARTBDL);
1338 writeb(cr1, sport->port.membase + UARTCR1);
1339 writeb(modem, sport->port.membase + UARTMODEM);
1340
1341 /* restore control register */
1342 writeb(old_cr2, sport->port.membase + UARTCR2);
1343
1344 spin_unlock_irqrestore(&sport->port.lock, flags);
1345}
1346
380c966c
JL		 1347static void
1348lpuart32_set_termios(struct uart_port *port, struct ktermios *termios,
1349 struct ktermios *old)
1350{
1351 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1352 unsigned long flags;
1353 unsigned long ctrl, old_ctrl, bd, modem;
1354 unsigned int baud;
1355 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
1356 unsigned int sbr;
1357
1358 ctrl = old_ctrl = lpuart32_read(sport->port.membase + UARTCTRL);
1359 bd = lpuart32_read(sport->port.membase + UARTBAUD);
1360 modem = lpuart32_read(sport->port.membase + UARTMODIR);
1361 /*
1362 * only support CS8 and CS7, and for CS7 must enable PE.
1363 * supported mode:
1364 * - (7,e/o,1)
1365 * - (8,n,1)
1366 * - (8,m/s,1)
1367 * - (8,e/o,1)
1368 */
1369 while ((termios->c_cflag & CSIZE) != CS8 &&
1370 (termios->c_cflag & CSIZE) != CS7) {
1371 termios->c_cflag &= ~CSIZE;
1372 termios->c_cflag |= old_csize;
1373 old_csize = CS8;
1374 }
1375
1376 if ((termios->c_cflag & CSIZE) == CS8 ||
1377 (termios->c_cflag & CSIZE) == CS7)
1378 ctrl = old_ctrl & ~UARTCTRL_M;
1379
1380 if (termios->c_cflag & CMSPAR) {
1381 if ((termios->c_cflag & CSIZE) != CS8) {
1382 termios->c_cflag &= ~CSIZE;
1383 termios->c_cflag |= CS8;
1384 }
1385 ctrl |= UARTCTRL_M;
1386 }
1387
1388 if (termios->c_cflag & CRTSCTS) {
1389 modem |= (UARTMODEM_RXRTSE | UARTMODEM_TXCTSE);
1390 } else {
1391 termios->c_cflag &= ~CRTSCTS;
1392 modem &= ~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE);
1393 }
1394
1395 if (termios->c_cflag & CSTOPB)
1396 termios->c_cflag &= ~CSTOPB;
1397
1398 /* parity must be enabled when CS7 to match 8-bits format */
1399 if ((termios->c_cflag & CSIZE) == CS7)
1400 termios->c_cflag |= PARENB;
1401
1402 if ((termios->c_cflag & PARENB)) {
1403 if (termios->c_cflag & CMSPAR) {
1404 ctrl &= ~UARTCTRL_PE;
1405 ctrl |= UARTCTRL_M;
1406 } else {
1407 ctrl |= UARTCR1_PE;
1408 if ((termios->c_cflag & CSIZE) == CS8)
1409 ctrl |= UARTCTRL_M;
1410 if (termios->c_cflag & PARODD)
1411 ctrl |= UARTCTRL_PT;
1412 else
1413 ctrl &= ~UARTCTRL_PT;
1414 }
1415 }
1416
1417 /* ask the core to calculate the divisor */
1418 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
1419
1420 spin_lock_irqsave(&sport->port.lock, flags);
1421
1422 sport->port.read_status_mask = 0;
1423 if (termios->c_iflag & INPCK)
1424 sport->port.read_status_mask |= (UARTSTAT_FE | UARTSTAT_PE);
1425 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
1426 sport->port.read_status_mask |= UARTSTAT_FE;
1427
1428 /* characters to ignore */
1429 sport->port.ignore_status_mask = 0;
1430 if (termios->c_iflag & IGNPAR)
1431 sport->port.ignore_status_mask |= UARTSTAT_PE;
1432 if (termios->c_iflag & IGNBRK) {
1433 sport->port.ignore_status_mask |= UARTSTAT_FE;
1434 /*
1435 * if we're ignoring parity and break indicators,
1436 * ignore overruns too (for real raw support).
1437 */
1438 if (termios->c_iflag & IGNPAR)
1439 sport->port.ignore_status_mask |= UARTSTAT_OR;
1440 }
1441
1442 /* update the per-port timeout */
1443 uart_update_timeout(port, termios->c_cflag, baud);
1444
1445 /* wait transmit engin complete */
1446 while (!(lpuart32_read(sport->port.membase + UARTSTAT) & UARTSTAT_TC))
1447 barrier();
1448
1449 /* disable transmit and receive */
1450 lpuart32_write(old_ctrl & ~(UARTCTRL_TE | UARTCTRL_RE),
1451 sport->port.membase + UARTCTRL);
1452
1453 sbr = sport->port.uartclk / (16 * baud);
1454 bd &= ~UARTBAUD_SBR_MASK;
1455 bd |= sbr & UARTBAUD_SBR_MASK;
1456 bd |= UARTBAUD_BOTHEDGE;
1457 bd &= ~(UARTBAUD_TDMAE | UARTBAUD_RDMAE);
1458 lpuart32_write(bd, sport->port.membase + UARTBAUD);
1459 lpuart32_write(modem, sport->port.membase + UARTMODIR);
1460 lpuart32_write(ctrl, sport->port.membase + UARTCTRL);
1461 /* restore control register */
1462
1463 spin_unlock_irqrestore(&sport->port.lock, flags);
1464}
1465
c9e2e946
JL		 1466static const char *lpuart_type(struct uart_port *port)
1467{
1468 return "FSL_LPUART";
1469}
1470
1471static void lpuart_release_port(struct uart_port *port)
1472{
1473 /* nothing to do */
1474}
1475
1476static int lpuart_request_port(struct uart_port *port)
1477{
1478 return 0;
1479}
1480
1481/* configure/autoconfigure the port */
1482static void lpuart_config_port(struct uart_port *port, int flags)
1483{
1484 if (flags & UART_CONFIG_TYPE)
1485 port->type = PORT_LPUART;
1486}
1487
1488static int lpuart_verify_port(struct uart_port *port, struct serial_struct *ser)
1489{
1490 int ret = 0;
1491
1492 if (ser->type != PORT_UNKNOWN && ser->type != PORT_LPUART)
1493 ret = -EINVAL;
1494 if (port->irq != ser->irq)
1495 ret = -EINVAL;
1496 if (ser->io_type != UPIO_MEM)
1497 ret = -EINVAL;
1498 if (port->uartclk / 16 != ser->baud_base)
1499 ret = -EINVAL;
1500 if (port->iobase != ser->port)
1501 ret = -EINVAL;
1502 if (ser->hub6 != 0)
1503 ret = -EINVAL;
1504 return ret;
1505}
1506
1507static struct uart_ops lpuart_pops = {
1508 .tx_empty = lpuart_tx_empty,
1509 .set_mctrl = lpuart_set_mctrl,
1510 .get_mctrl = lpuart_get_mctrl,
1511 .stop_tx = lpuart_stop_tx,
1512 .start_tx = lpuart_start_tx,
1513 .stop_rx = lpuart_stop_rx,
c9e2e946
JL		 1514 .break_ctl = lpuart_break_ctl,
1515 .startup = lpuart_startup,
1516 .shutdown = lpuart_shutdown,
1517 .set_termios = lpuart_set_termios,
1518 .type = lpuart_type,
1519 .request_port = lpuart_request_port,
1520 .release_port = lpuart_release_port,
1521 .config_port = lpuart_config_port,
1522 .verify_port = lpuart_verify_port,
bfc2e07f 1523 .flush_buffer = lpuart_flush_buffer,
c9e2e946
JL		 1524};
1525
380c966c
JL		 1526static struct uart_ops lpuart32_pops = {
1527 .tx_empty = lpuart32_tx_empty,
1528 .set_mctrl = lpuart32_set_mctrl,
1529 .get_mctrl = lpuart32_get_mctrl,
1530 .stop_tx = lpuart32_stop_tx,
1531 .start_tx = lpuart32_start_tx,
1532 .stop_rx = lpuart32_stop_rx,
1533 .break_ctl = lpuart32_break_ctl,
1534 .startup = lpuart32_startup,
1535 .shutdown = lpuart32_shutdown,
1536 .set_termios = lpuart32_set_termios,
1537 .type = lpuart_type,
1538 .request_port = lpuart_request_port,
1539 .release_port = lpuart_release_port,
1540 .config_port = lpuart_config_port,
1541 .verify_port = lpuart_verify_port,
bfc2e07f 1542 .flush_buffer = lpuart_flush_buffer,
380c966c
JL		 1543};
1544
c9e2e946
JL		 1545static struct lpuart_port *lpuart_ports[UART_NR];
1546
1547#ifdef CONFIG_SERIAL_FSL_LPUART_CONSOLE
1548static void lpuart_console_putchar(struct uart_port *port, int ch)
1549{
1550 while (!(readb(port->membase + UARTSR1) & UARTSR1_TDRE))
1551 barrier();
1552
1553 writeb(ch, port->membase + UARTDR);
1554}
1555
380c966c
JL		 1556static void lpuart32_console_putchar(struct uart_port *port, int ch)
1557{
1558 while (!(lpuart32_read(port->membase + UARTSTAT) & UARTSTAT_TDRE))
1559 barrier();
1560
1561 lpuart32_write(ch, port->membase + UARTDATA);
1562}
1563
c9e2e946
JL		 1564static void
1565lpuart_console_write(struct console *co, const char *s, unsigned int count)
1566{
1567 struct lpuart_port *sport = lpuart_ports[co->index];
1568 unsigned char old_cr2, cr2;
1569
1570 /* first save CR2 and then disable interrupts */
1571 cr2 = old_cr2 = readb(sport->port.membase + UARTCR2);
1572 cr2 |= (UARTCR2_TE | UARTCR2_RE);
1573 cr2 &= ~(UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_RIE);
1574 writeb(cr2, sport->port.membase + UARTCR2);
1575
1576 uart_console_write(&sport->port, s, count, lpuart_console_putchar);
1577
1578 /* wait for transmitter finish complete and restore CR2 */
1579 while (!(readb(sport->port.membase + UARTSR1) & UARTSR1_TC))
1580 barrier();
1581
1582 writeb(old_cr2, sport->port.membase + UARTCR2);
1583}
1584
380c966c
JL		 1585static void
1586lpuart32_console_write(struct console *co, const char *s, unsigned int count)
1587{
1588 struct lpuart_port *sport = lpuart_ports[co->index];
1589 unsigned long old_cr, cr;
1590
1591 /* first save CR2 and then disable interrupts */
1592 cr = old_cr = lpuart32_read(sport->port.membase + UARTCTRL);
1593 cr |= (UARTCTRL_TE | UARTCTRL_RE);
1594 cr &= ~(UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_RIE);
1595 lpuart32_write(cr, sport->port.membase + UARTCTRL);
1596
1597 uart_console_write(&sport->port, s, count, lpuart32_console_putchar);
1598
1599 /* wait for transmitter finish complete and restore CR2 */
1600 while (!(lpuart32_read(sport->port.membase + UARTSTAT) & UARTSTAT_TC))
1601 barrier();
1602
1603 lpuart32_write(old_cr, sport->port.membase + UARTCTRL);
1604}
1605
c9e2e946
JL		 1606/*
1607 * if the port was already initialised (eg, by a boot loader),
1608 * try to determine the current setup.
1609 */
1610static void __init
1611lpuart_console_get_options(struct lpuart_port *sport, int *baud,
1612 int *parity, int *bits)
1613{
1614 unsigned char cr, bdh, bdl, brfa;
1615 unsigned int sbr, uartclk, baud_raw;
1616
1617 cr = readb(sport->port.membase + UARTCR2);
1618 cr &= UARTCR2_TE | UARTCR2_RE;
1619 if (!cr)
1620 return;
1621
1622 /* ok, the port was enabled */
1623
1624 cr = readb(sport->port.membase + UARTCR1);
1625
1626 *parity = 'n';
1627 if (cr & UARTCR1_PE) {
1628 if (cr & UARTCR1_PT)
1629 *parity = 'o';
1630 else
1631 *parity = 'e';
1632 }
1633
1634 if (cr & UARTCR1_M)
1635 *bits = 9;
1636 else
1637 *bits = 8;
1638
1639 bdh = readb(sport->port.membase + UARTBDH);
1640 bdh &= UARTBDH_SBR_MASK;
1641 bdl = readb(sport->port.membase + UARTBDL);
1642 sbr = bdh;
1643 sbr <<= 8;
1644 sbr |= bdl;
1645 brfa = readb(sport->port.membase + UARTCR4);
1646 brfa &= UARTCR4_BRFA_MASK;
1647
1648 uartclk = clk_get_rate(sport->clk);
1649 /*
1650 * baud = mod_clk/(16*(sbr[13]+(brfa)/32)
1651 */
1652 baud_raw = uartclk / (16 * (sbr + brfa / 32));
1653
1654 if (*baud != baud_raw)
1655 printk(KERN_INFO "Serial: Console lpuart rounded baud rate"
1656 "from %d to %d\n", baud_raw, *baud);
1657}
1658
380c966c
JL		 1659static void __init
1660lpuart32_console_get_options(struct lpuart_port *sport, int *baud,
1661 int *parity, int *bits)
1662{
1663 unsigned long cr, bd;
1664 unsigned int sbr, uartclk, baud_raw;
1665
1666 cr = lpuart32_read(sport->port.membase + UARTCTRL);
1667 cr &= UARTCTRL_TE | UARTCTRL_RE;
1668 if (!cr)
1669 return;
1670
1671 /* ok, the port was enabled */
1672
1673 cr = lpuart32_read(sport->port.membase + UARTCTRL);
1674
1675 *parity = 'n';
1676 if (cr & UARTCTRL_PE) {
1677 if (cr & UARTCTRL_PT)
1678 *parity = 'o';
1679 else
1680 *parity = 'e';
1681 }
1682
1683 if (cr & UARTCTRL_M)
1684 *bits = 9;
1685 else
1686 *bits = 8;
1687
1688 bd = lpuart32_read(sport->port.membase + UARTBAUD);
1689 bd &= UARTBAUD_SBR_MASK;
1690 sbr = bd;
1691 uartclk = clk_get_rate(sport->clk);
1692 /*
1693 * baud = mod_clk/(16*(sbr[13]+(brfa)/32)
1694 */
1695 baud_raw = uartclk / (16 * sbr);
1696
1697 if (*baud != baud_raw)
1698 printk(KERN_INFO "Serial: Console lpuart rounded baud rate"
1699 "from %d to %d\n", baud_raw, *baud);
1700}
1701
c9e2e946
JL		 1702static int __init lpuart_console_setup(struct console *co, char *options)
1703{
1704 struct lpuart_port *sport;
1705 int baud = 115200;
1706 int bits = 8;
1707 int parity = 'n';
1708 int flow = 'n';
1709
1710 /*
1711 * check whether an invalid uart number has been specified, and
1712 * if so, search for the first available port that does have
1713 * console support.
1714 */
1715 if (co->index == -1 || co->index >= ARRAY_SIZE(lpuart_ports))
1716 co->index = 0;
1717
1718 sport = lpuart_ports[co->index];
1719 if (sport == NULL)
1720 return -ENODEV;
1721
1722 if (options)
1723 uart_parse_options(options, &baud, &parity, &bits, &flow);
1724 else
380c966c
JL		 1725 if (sport->lpuart32)
1726 lpuart32_console_get_options(sport, &baud, &parity, &bits);
1727 else
1728 lpuart_console_get_options(sport, &baud, &parity, &bits);
c9e2e946 1729
380c966c
JL		 1730 if (sport->lpuart32)
1731 lpuart32_setup_watermark(sport);
1732 else
1733 lpuart_setup_watermark(sport);
c9e2e946
JL		 1734
1735 return uart_set_options(&sport->port, co, baud, parity, bits, flow);
1736}
1737
1738static struct uart_driver lpuart_reg;
1739static struct console lpuart_console = {
1740 .name = DEV_NAME,
1741 .write = lpuart_console_write,
1742 .device = uart_console_device,
1743 .setup = lpuart_console_setup,
1744 .flags = CON_PRINTBUFFER,
1745 .index = -1,
1746 .data = &lpuart_reg,
1747};
1748
380c966c
JL		 1749static struct console lpuart32_console = {
1750 .name = DEV_NAME,
1751 .write = lpuart32_console_write,
1752 .device = uart_console_device,
1753 .setup = lpuart_console_setup,
1754 .flags = CON_PRINTBUFFER,
1755 .index = -1,
1756 .data = &lpuart_reg,
1757};
1758
1d59b382
SA		 1759static void lpuart_early_write(struct console *con, const char *s, unsigned n)
1760{
1761 struct earlycon_device *dev = con->data;
1762
1763 uart_console_write(&dev->port, s, n, lpuart_console_putchar);
1764}
1765
1766static void lpuart32_early_write(struct console *con, const char *s, unsigned n)
1767{
1768 struct earlycon_device *dev = con->data;
1769
1770 uart_console_write(&dev->port, s, n, lpuart32_console_putchar);
1771}
1772
1773static int __init lpuart_early_console_setup(struct earlycon_device *device,
1774 const char *opt)
1775{
1776 if (!device->port.membase)
1777 return -ENODEV;
1778
1779 device->con->write = lpuart_early_write;
1780 return 0;
1781}
1782
1783static int __init lpuart32_early_console_setup(struct earlycon_device *device,
1784 const char *opt)
1785{
1786 if (!device->port.membase)
1787 return -ENODEV;
1788
1789 device->con->write = lpuart32_early_write;
1790 return 0;
1791}
1792
1793OF_EARLYCON_DECLARE(lpuart, "fsl,vf610-lpuart", lpuart_early_console_setup);
1794OF_EARLYCON_DECLARE(lpuart32, "fsl,ls1021a-lpuart", lpuart32_early_console_setup);
1795EARLYCON_DECLARE(lpuart, lpuart_early_console_setup);
1796EARLYCON_DECLARE(lpuart32, lpuart32_early_console_setup);
1797
c9e2e946 1798#define LPUART_CONSOLE (&lpuart_console)
380c966c 1799#define LPUART32_CONSOLE (&lpuart32_console)
c9e2e946
JL		 1800#else
1801#define LPUART_CONSOLE NULL
380c966c 1802#define LPUART32_CONSOLE NULL
c9e2e946
JL		 1803#endif
1804
1805static struct uart_driver lpuart_reg = {
1806 .owner = THIS_MODULE,
1807 .driver_name = DRIVER_NAME,
1808 .dev_name = DEV_NAME,
1809 .nr = ARRAY_SIZE(lpuart_ports),
1810 .cons = LPUART_CONSOLE,
1811};
1812
1813static int lpuart_probe(struct platform_device *pdev)
1814{
1815 struct device_node *np = pdev->dev.of_node;
1816 struct lpuart_port *sport;
1817 struct resource *res;
1818 int ret;
1819
1820 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);
1821 if (!sport)
1822 return -ENOMEM;
1823
1824 pdev->dev.coherent_dma_mask = 0;
1825
1826 ret = of_alias_get_id(np, "serial");
1827 if (ret < 0) {
1828 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret);
1829 return ret;
1830 }
1831 sport->port.line = ret;
380c966c 1832 sport->lpuart32 = of_device_is_compatible(np, "fsl,ls1021a-lpuart");
c9e2e946 1833
4ae612a3 1834 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
c9e2e946
JL		 1835 sport->port.membase = devm_ioremap_resource(&pdev->dev, res);
1836 if (IS_ERR(sport->port.membase))
1837 return PTR_ERR(sport->port.membase);
1838
4ae612a3 1839 sport->port.mapbase = res->start;
c9e2e946
JL		 1840 sport->port.dev = &pdev->dev;
1841 sport->port.type = PORT_LPUART;
1842 sport->port.iotype = UPIO_MEM;
394a9e2c
JS		 1843 ret = platform_get_irq(pdev, 0);
1844 if (ret < 0) {
1845 dev_err(&pdev->dev, "cannot obtain irq\n");
1846 return ret;
1847 }
1848 sport->port.irq = ret;
1849
380c966c
JL		 1850 if (sport->lpuart32)
1851 sport->port.ops = &lpuart32_pops;
1852 else
1853 sport->port.ops = &lpuart_pops;
c9e2e946
JL		 1854 sport->port.flags = UPF_BOOT_AUTOCONF;
1855
1856 sport->clk = devm_clk_get(&pdev->dev, "ipg");
1857 if (IS_ERR(sport->clk)) {
1858 ret = PTR_ERR(sport->clk);
1859 dev_err(&pdev->dev, "failed to get uart clk: %d\n", ret);
1860 return ret;
1861 }
1862
1863 ret = clk_prepare_enable(sport->clk);
1864 if (ret) {
1865 dev_err(&pdev->dev, "failed to enable uart clk: %d\n", ret);
1866 return ret;
1867 }
1868
1869 sport->port.uartclk = clk_get_rate(sport->clk);
1870
1871 lpuart_ports[sport->port.line] = sport;
1872
1873 platform_set_drvdata(pdev, &sport->port);
1874
380c966c
JL		 1875 if (sport->lpuart32)
1876 lpuart_reg.cons = LPUART32_CONSOLE;
1877 else
1878 lpuart_reg.cons = LPUART_CONSOLE;
1879
c9e2e946
JL		 1880 ret = uart_add_one_port(&lpuart_reg, &sport->port);
1881 if (ret) {
1882 clk_disable_unprepare(sport->clk);
1883 return ret;
1884 }
1885
4a818c43
SA		 1886 sport->dma_tx_chan = dma_request_slave_channel(sport->port.dev, "tx");
1887 if (!sport->dma_tx_chan)
1888 dev_info(sport->port.dev, "DMA tx channel request failed, "
1889 "operating without tx DMA\n");
1890
1891 sport->dma_rx_chan = dma_request_slave_channel(sport->port.dev, "rx");
1892 if (!sport->dma_rx_chan)
1893 dev_info(sport->port.dev, "DMA rx channel request failed, "
1894 "operating without rx DMA\n");
1895
c9e2e946
JL		 1896 return 0;
1897}
1898
1899static int lpuart_remove(struct platform_device *pdev)
1900{
1901 struct lpuart_port *sport = platform_get_drvdata(pdev);
1902
1903 uart_remove_one_port(&lpuart_reg, &sport->port);
1904
1905 clk_disable_unprepare(sport->clk);
1906
4a818c43
SA		 1907 if (sport->dma_tx_chan)
1908 dma_release_channel(sport->dma_tx_chan);
1909
1910 if (sport->dma_rx_chan)
1911 dma_release_channel(sport->dma_rx_chan);
1912
c9e2e946
JL		 1913 return 0;
1914}
1915
1916#ifdef CONFIG_PM_SLEEP
1917static int lpuart_suspend(struct device *dev)
1918{
1919 struct lpuart_port *sport = dev_get_drvdata(dev);
2fe605df
YY		 1920 unsigned long temp;
1921
1922 if (sport->lpuart32) {
1923 /* disable Rx/Tx and interrupts */
1924 temp = lpuart32_read(sport->port.membase + UARTCTRL);
1925 temp &= ~(UARTCTRL_TE | UARTCTRL_TIE | UARTCTRL_TCIE);
1926 lpuart32_write(temp, sport->port.membase + UARTCTRL);
1927 } else {
1928 /* disable Rx/Tx and interrupts */
1929 temp = readb(sport->port.membase + UARTCR2);
1930 temp &= ~(UARTCR2_TE | UARTCR2_TIE | UARTCR2_TCIE);
1931 writeb(temp, sport->port.membase + UARTCR2);
1932 }
c9e2e946
JL		 1933
1934 uart_suspend_port(&lpuart_reg, &sport->port);
1935
1936 return 0;
1937}
1938
1939static int lpuart_resume(struct device *dev)
1940{
1941 struct lpuart_port *sport = dev_get_drvdata(dev);
08de1014
JL		 1942 unsigned long temp;
1943
1944 if (sport->lpuart32) {
1945 lpuart32_setup_watermark(sport);
1946 temp = lpuart32_read(sport->port.membase + UARTCTRL);
1947 temp |= (UARTCTRL_RIE | UARTCTRL_TIE | UARTCTRL_RE |
1948 UARTCTRL_TE | UARTCTRL_ILIE);
1949 lpuart32_write(temp, sport->port.membase + UARTCTRL);
1950 } else {
1951 lpuart_setup_watermark(sport);
1952 temp = readb(sport->port.membase + UARTCR2);
1953 temp |= (UARTCR2_RIE | UARTCR2_TIE | UARTCR2_RE | UARTCR2_TE);
1954 writeb(temp, sport->port.membase + UARTCR2);
1955 }
c9e2e946
JL		 1956
1957 uart_resume_port(&lpuart_reg, &sport->port);
1958
1959 return 0;
1960}
1961#endif
1962
1963static SIMPLE_DEV_PM_OPS(lpuart_pm_ops, lpuart_suspend, lpuart_resume);
1964
1965static struct platform_driver lpuart_driver = {
1966 .probe = lpuart_probe,
1967 .remove = lpuart_remove,
1968 .driver = {
1969 .name = "fsl-lpuart",
c9e2e946
JL		 1970 .of_match_table = lpuart_dt_ids,
1971 .pm = &lpuart_pm_ops,
1972 },
1973};
1974
1975static int __init lpuart_serial_init(void)
1976{
144c29ed 1977 int ret = uart_register_driver(&lpuart_reg);
c9e2e946 1978
c9e2e946
JL		 1979 if (ret)
1980 return ret;
1981
1982 ret = platform_driver_register(&lpuart_driver);
1983 if (ret)
1984 uart_unregister_driver(&lpuart_reg);
1985
39c34b09 1986 return ret;
c9e2e946
JL		 1987}
1988
1989static void __exit lpuart_serial_exit(void)
1990{
1991 platform_driver_unregister(&lpuart_driver);
1992 uart_unregister_driver(&lpuart_reg);
1993}
1994
1995module_init(lpuart_serial_init);
1996module_exit(lpuart_serial_exit);
1997
1998MODULE_DESCRIPTION("Freescale lpuart serial port driver");
1999MODULE_LICENSE("GPL v2");
Linux 6.x block layer and io_uring tree(s)