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tty: serial: lpuart: refactor lpuart32_{read|write} prototype
[linux-2.6-block.git] / drivers / tty / serial / fsl_lpuart.c
CommitLineData
c9e2e946
JL		 1/*
2 * Freescale lpuart serial port driver
3 *
380c966c 4 * Copyright 2012-2014 Freescale Semiconductor, Inc.
c9e2e946
JL		 5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 */
11
12#if defined(CONFIG_SERIAL_FSL_LPUART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
13#define SUPPORT_SYSRQ
14#endif
15
f1cd8c87
YY		 16#include <linux/clk.h>
17#include <linux/console.h>
18#include <linux/dma-mapping.h>
19#include <linux/dmaengine.h>
20#include <linux/dmapool.h>
c9e2e946
JL		 21#include <linux/io.h>
22#include <linux/irq.h>
f1cd8c87 23#include <linux/module.h>
c9e2e946
JL		 24#include <linux/of.h>
25#include <linux/of_device.h>
f1cd8c87 26#include <linux/of_dma.h>
c9e2e946 27#include <linux/serial_core.h>
f1cd8c87 28#include <linux/slab.h>
c9e2e946
JL		 29#include <linux/tty_flip.h>
30
31/* All registers are 8-bit width */
32#define UARTBDH 0x00
33#define UARTBDL 0x01
34#define UARTCR1 0x02
35#define UARTCR2 0x03
36#define UARTSR1 0x04
37#define UARTCR3 0x06
38#define UARTDR 0x07
39#define UARTCR4 0x0a
40#define UARTCR5 0x0b
41#define UARTMODEM 0x0d
42#define UARTPFIFO 0x10
43#define UARTCFIFO 0x11
44#define UARTSFIFO 0x12
45#define UARTTWFIFO 0x13
46#define UARTTCFIFO 0x14
47#define UARTRWFIFO 0x15
48
49#define UARTBDH_LBKDIE 0x80
50#define UARTBDH_RXEDGIE 0x40
51#define UARTBDH_SBR_MASK 0x1f
52
53#define UARTCR1_LOOPS 0x80
54#define UARTCR1_RSRC 0x20
55#define UARTCR1_M 0x10
56#define UARTCR1_WAKE 0x08
57#define UARTCR1_ILT 0x04
58#define UARTCR1_PE 0x02
59#define UARTCR1_PT 0x01
60
61#define UARTCR2_TIE 0x80
62#define UARTCR2_TCIE 0x40
63#define UARTCR2_RIE 0x20
64#define UARTCR2_ILIE 0x10
65#define UARTCR2_TE 0x08
66#define UARTCR2_RE 0x04
67#define UARTCR2_RWU 0x02
68#define UARTCR2_SBK 0x01
69
70#define UARTSR1_TDRE 0x80
71#define UARTSR1_TC 0x40
72#define UARTSR1_RDRF 0x20
73#define UARTSR1_IDLE 0x10
74#define UARTSR1_OR 0x08
75#define UARTSR1_NF 0x04
76#define UARTSR1_FE 0x02
77#define UARTSR1_PE 0x01
78
79#define UARTCR3_R8 0x80
80#define UARTCR3_T8 0x40
81#define UARTCR3_TXDIR 0x20
82#define UARTCR3_TXINV 0x10
83#define UARTCR3_ORIE 0x08
84#define UARTCR3_NEIE 0x04
85#define UARTCR3_FEIE 0x02
86#define UARTCR3_PEIE 0x01
87
88#define UARTCR4_MAEN1 0x80
89#define UARTCR4_MAEN2 0x40
90#define UARTCR4_M10 0x20
91#define UARTCR4_BRFA_MASK 0x1f
92#define UARTCR4_BRFA_OFF 0
93
94#define UARTCR5_TDMAS 0x80
95#define UARTCR5_RDMAS 0x20
96
97#define UARTMODEM_RXRTSE 0x08
98#define UARTMODEM_TXRTSPOL 0x04
99#define UARTMODEM_TXRTSE 0x02
100#define UARTMODEM_TXCTSE 0x01
101
102#define UARTPFIFO_TXFE 0x80
103#define UARTPFIFO_FIFOSIZE_MASK 0x7
104#define UARTPFIFO_TXSIZE_OFF 4
105#define UARTPFIFO_RXFE 0x08
106#define UARTPFIFO_RXSIZE_OFF 0
107
108#define UARTCFIFO_TXFLUSH 0x80
109#define UARTCFIFO_RXFLUSH 0x40
110#define UARTCFIFO_RXOFE 0x04
111#define UARTCFIFO_TXOFE 0x02
112#define UARTCFIFO_RXUFE 0x01
113
114#define UARTSFIFO_TXEMPT 0x80
115#define UARTSFIFO_RXEMPT 0x40
116#define UARTSFIFO_RXOF 0x04
117#define UARTSFIFO_TXOF 0x02
118#define UARTSFIFO_RXUF 0x01
119
380c966c
JL		 120/* 32-bit register defination */
121#define UARTBAUD 0x00
122#define UARTSTAT 0x04
123#define UARTCTRL 0x08
124#define UARTDATA 0x0C
125#define UARTMATCH 0x10
126#define UARTMODIR 0x14
127#define UARTFIFO 0x18
128#define UARTWATER 0x1c
129
130#define UARTBAUD_MAEN1 0x80000000
131#define UARTBAUD_MAEN2 0x40000000
132#define UARTBAUD_M10 0x20000000
133#define UARTBAUD_TDMAE 0x00800000
134#define UARTBAUD_RDMAE 0x00200000
135#define UARTBAUD_MATCFG 0x00400000
136#define UARTBAUD_BOTHEDGE 0x00020000
137#define UARTBAUD_RESYNCDIS 0x00010000
138#define UARTBAUD_LBKDIE 0x00008000
139#define UARTBAUD_RXEDGIE 0x00004000
140#define UARTBAUD_SBNS 0x00002000
141#define UARTBAUD_SBR 0x00000000
142#define UARTBAUD_SBR_MASK 0x1fff
143
144#define UARTSTAT_LBKDIF 0x80000000
145#define UARTSTAT_RXEDGIF 0x40000000
146#define UARTSTAT_MSBF 0x20000000
147#define UARTSTAT_RXINV 0x10000000
148#define UARTSTAT_RWUID 0x08000000
149#define UARTSTAT_BRK13 0x04000000
150#define UARTSTAT_LBKDE 0x02000000
151#define UARTSTAT_RAF 0x01000000
152#define UARTSTAT_TDRE 0x00800000
153#define UARTSTAT_TC 0x00400000
154#define UARTSTAT_RDRF 0x00200000
155#define UARTSTAT_IDLE 0x00100000
156#define UARTSTAT_OR 0x00080000
157#define UARTSTAT_NF 0x00040000
158#define UARTSTAT_FE 0x00020000
159#define UARTSTAT_PE 0x00010000
160#define UARTSTAT_MA1F 0x00008000
161#define UARTSTAT_M21F 0x00004000
162
163#define UARTCTRL_R8T9 0x80000000
164#define UARTCTRL_R9T8 0x40000000
165#define UARTCTRL_TXDIR 0x20000000
166#define UARTCTRL_TXINV 0x10000000
167#define UARTCTRL_ORIE 0x08000000
168#define UARTCTRL_NEIE 0x04000000
169#define UARTCTRL_FEIE 0x02000000
170#define UARTCTRL_PEIE 0x01000000
171#define UARTCTRL_TIE 0x00800000
172#define UARTCTRL_TCIE 0x00400000
173#define UARTCTRL_RIE 0x00200000
174#define UARTCTRL_ILIE 0x00100000
175#define UARTCTRL_TE 0x00080000
176#define UARTCTRL_RE 0x00040000
177#define UARTCTRL_RWU 0x00020000
178#define UARTCTRL_SBK 0x00010000
179#define UARTCTRL_MA1IE 0x00008000
180#define UARTCTRL_MA2IE 0x00004000
181#define UARTCTRL_IDLECFG 0x00000100
182#define UARTCTRL_LOOPS 0x00000080
183#define UARTCTRL_DOZEEN 0x00000040
184#define UARTCTRL_RSRC 0x00000020
185#define UARTCTRL_M 0x00000010
186#define UARTCTRL_WAKE 0x00000008
187#define UARTCTRL_ILT 0x00000004
188#define UARTCTRL_PE 0x00000002
189#define UARTCTRL_PT 0x00000001
190
191#define UARTDATA_NOISY 0x00008000
192#define UARTDATA_PARITYE 0x00004000
193#define UARTDATA_FRETSC 0x00002000
194#define UARTDATA_RXEMPT 0x00001000
195#define UARTDATA_IDLINE 0x00000800
196#define UARTDATA_MASK 0x3ff
197
198#define UARTMODIR_IREN 0x00020000
199#define UARTMODIR_TXCTSSRC 0x00000020
200#define UARTMODIR_TXCTSC 0x00000010
201#define UARTMODIR_RXRTSE 0x00000008
202#define UARTMODIR_TXRTSPOL 0x00000004
203#define UARTMODIR_TXRTSE 0x00000002
204#define UARTMODIR_TXCTSE 0x00000001
205
206#define UARTFIFO_TXEMPT 0x00800000
207#define UARTFIFO_RXEMPT 0x00400000
208#define UARTFIFO_TXOF 0x00020000
209#define UARTFIFO_RXUF 0x00010000
210#define UARTFIFO_TXFLUSH 0x00008000
211#define UARTFIFO_RXFLUSH 0x00004000
212#define UARTFIFO_TXOFE 0x00000200
213#define UARTFIFO_RXUFE 0x00000100
214#define UARTFIFO_TXFE 0x00000080
215#define UARTFIFO_FIFOSIZE_MASK 0x7
216#define UARTFIFO_TXSIZE_OFF 4
217#define UARTFIFO_RXFE 0x00000008
218#define UARTFIFO_RXSIZE_OFF 0
219
220#define UARTWATER_COUNT_MASK 0xff
221#define UARTWATER_TXCNT_OFF 8
222#define UARTWATER_RXCNT_OFF 24
223#define UARTWATER_WATER_MASK 0xff
224#define UARTWATER_TXWATER_OFF 0
225#define UARTWATER_RXWATER_OFF 16
226
5887ad43
BD		 227/* Rx DMA timeout in ms, which is used to calculate Rx ring buffer size */
228#define DMA_RX_TIMEOUT (10)
f1cd8c87 229
c9e2e946
JL		 230#define DRIVER_NAME "fsl-lpuart"
231#define DEV_NAME "ttyLP"
232#define UART_NR 6
233
234struct lpuart_port {
235 struct uart_port port;
236 struct clk *clk;
237 unsigned int txfifo_size;
238 unsigned int rxfifo_size;
f1cd8c87 239
4a818c43
SA		 240 bool lpuart_dma_tx_use;
241 bool lpuart_dma_rx_use;
f1cd8c87
YY		 242 struct dma_chan *dma_tx_chan;
243 struct dma_chan *dma_rx_chan;
244 struct dma_async_tx_descriptor *dma_tx_desc;
245 struct dma_async_tx_descriptor *dma_rx_desc;
f1cd8c87
YY		 246 dma_cookie_t dma_tx_cookie;
247 dma_cookie_t dma_rx_cookie;
f1cd8c87
YY		 248 unsigned int dma_tx_bytes;
249 unsigned int dma_rx_bytes;
6250cc30 250 bool dma_tx_in_progress;
f1cd8c87
YY		 251 unsigned int dma_rx_timeout;
252 struct timer_list lpuart_timer;
6250cc30 253 struct scatterlist rx_sgl, tx_sgl[2];
5887ad43
BD		 254 struct circ_buf rx_ring;
255 int rx_dma_rng_buf_len;
6250cc30
BD		 256 unsigned int dma_tx_nents;
257 wait_queue_head_t dma_wait;
c9e2e946
JL		 258};
259
0d6fce90
DA		 260struct lpuart_soc_data {
261 char iotype;
262};
263
264static const struct lpuart_soc_data vf_data = {
265 .iotype = UPIO_MEM,
266};
267
268static const struct lpuart_soc_data ls_data = {
269 .iotype = UPIO_MEM32BE,
270};
271
ed0bb232 272static const struct of_device_id lpuart_dt_ids[] = {
0d6fce90
DA		 273 { .compatible = "fsl,vf610-lpuart", .data = &vf_data, },
274 { .compatible = "fsl,ls1021a-lpuart", .data = &ls_data, },
c9e2e946
JL		 275 { /* sentinel */ }
276};
277MODULE_DEVICE_TABLE(of, lpuart_dt_ids);
278
f1cd8c87
YY		 279/* Forward declare this for the dma callbacks*/
280static void lpuart_dma_tx_complete(void *arg);
f1cd8c87 281
a0204f25 282static inline u32 lpuart32_read(struct uart_port *port, u32 reg_off)
380c966c 283{
a0204f25 284 return ioread32be(port->membase + reg_off);
380c966c
JL		 285}
286
a0204f25
DA		 287static inline void lpuart32_write(struct uart_port *port, u32 val,
288 u32 reg_off)
380c966c 289{
a0204f25 290 iowrite32be(val, port->membase + reg_off);
380c966c
JL		 291}
292
c9e2e946
JL		 293static void lpuart_stop_tx(struct uart_port *port)
294{
295 unsigned char temp;
296
297 temp = readb(port->membase + UARTCR2);
298 temp &= ~(UARTCR2_TIE | UARTCR2_TCIE);
299 writeb(temp, port->membase + UARTCR2);
300}
301
380c966c
JL		 302static void lpuart32_stop_tx(struct uart_port *port)
303{
304 unsigned long temp;
305
a0204f25 306 temp = lpuart32_read(port, UARTCTRL);
380c966c 307 temp &= ~(UARTCTRL_TIE | UARTCTRL_TCIE);
a0204f25 308 lpuart32_write(port, temp, UARTCTRL);
380c966c
JL		 309}
310
c9e2e946
JL		 311static void lpuart_stop_rx(struct uart_port *port)
312{
313 unsigned char temp;
314
315 temp = readb(port->membase + UARTCR2);
316 writeb(temp & ~UARTCR2_RE, port->membase + UARTCR2);
317}
318
380c966c
JL		 319static void lpuart32_stop_rx(struct uart_port *port)
320{
321 unsigned long temp;
322
a0204f25
DA		 323 temp = lpuart32_read(port, UARTCTRL);
324 lpuart32_write(port, temp & ~UARTCTRL_RE, UARTCTRL);
380c966c
JL		 325}
326
6250cc30 327static void lpuart_dma_tx(struct lpuart_port *sport)
f1cd8c87
YY		 328{
329 struct circ_buf *xmit = &sport->port.state->xmit;
6250cc30
BD		 330 struct scatterlist *sgl = sport->tx_sgl;
331 struct device *dev = sport->port.dev;
332 int ret;
f1cd8c87 333
6250cc30
BD		 334 if (sport->dma_tx_in_progress)
335 return;
f1cd8c87 336
6250cc30 337 sport->dma_tx_bytes = uart_circ_chars_pending(xmit);
f1cd8c87 338
d704b2d3 339 if (xmit->tail < xmit->head || xmit->head == 0) {
6250cc30
BD		 340 sport->dma_tx_nents = 1;
341 sg_init_one(sgl, xmit->buf + xmit->tail, sport->dma_tx_bytes);
342 } else {
343 sport->dma_tx_nents = 2;
344 sg_init_table(sgl, 2);
345 sg_set_buf(sgl, xmit->buf + xmit->tail,
346 UART_XMIT_SIZE - xmit->tail);
347 sg_set_buf(sgl + 1, xmit->buf, xmit->head);
348 }
f1cd8c87 349
6250cc30
BD		 350 ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
351 if (!ret) {
352 dev_err(dev, "DMA mapping error for TX.\n");
353 return;
354 }
f1cd8c87 355
6250cc30
BD		 356 sport->dma_tx_desc = dmaengine_prep_slave_sg(sport->dma_tx_chan, sgl,
357 sport->dma_tx_nents,
f1cd8c87 358 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
f1cd8c87 359 if (!sport->dma_tx_desc) {
6250cc30
BD		 360 dma_unmap_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
361 dev_err(dev, "Cannot prepare TX slave DMA!\n");
362 return;
f1cd8c87
YY		 363 }
364
365 sport->dma_tx_desc->callback = lpuart_dma_tx_complete;
366 sport->dma_tx_desc->callback_param = sport;
6250cc30 367 sport->dma_tx_in_progress = true;
f1cd8c87
YY		 368 sport->dma_tx_cookie = dmaengine_submit(sport->dma_tx_desc);
369 dma_async_issue_pending(sport->dma_tx_chan);
f1cd8c87
YY		 370}
371
372static void lpuart_dma_tx_complete(void *arg)
373{
374 struct lpuart_port *sport = arg;
6250cc30 375 struct scatterlist *sgl = &sport->tx_sgl[0];
f1cd8c87
YY		 376 struct circ_buf *xmit = &sport->port.state->xmit;
377 unsigned long flags;
378
f1cd8c87
YY		 379 spin_lock_irqsave(&sport->port.lock, flags);
380
6250cc30
BD		 381 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
382
f1cd8c87 383 xmit->tail = (xmit->tail + sport->dma_tx_bytes) & (UART_XMIT_SIZE - 1);
6250cc30
BD		 384
385 sport->port.icount.tx += sport->dma_tx_bytes;
386 sport->dma_tx_in_progress = false;
387 spin_unlock_irqrestore(&sport->port.lock, flags);
f1cd8c87
YY		 388
389 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
390 uart_write_wakeup(&sport->port);
391
6250cc30
BD		 392 if (waitqueue_active(&sport->dma_wait)) {
393 wake_up(&sport->dma_wait);
394 return;
395 }
396
397 spin_lock_irqsave(&sport->port.lock, flags);
398
399 if (!uart_circ_empty(xmit) && !uart_tx_stopped(&sport->port))
400 lpuart_dma_tx(sport);
f1cd8c87
YY		 401
402 spin_unlock_irqrestore(&sport->port.lock, flags);
403}
404
6250cc30
BD		 405static int lpuart_dma_tx_request(struct uart_port *port)
406{
407 struct lpuart_port *sport = container_of(port,
408 struct lpuart_port, port);
409 struct dma_slave_config dma_tx_sconfig = {};
410 int ret;
411
412 dma_tx_sconfig.dst_addr = sport->port.mapbase + UARTDR;
413 dma_tx_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
414 dma_tx_sconfig.dst_maxburst = 1;
415 dma_tx_sconfig.direction = DMA_MEM_TO_DEV;
416 ret = dmaengine_slave_config(sport->dma_tx_chan, &dma_tx_sconfig);
417
418 if (ret) {
419 dev_err(sport->port.dev,
420 "DMA slave config failed, err = %d\n", ret);
421 return ret;
422 }
423
424 return 0;
425}
426
bfc2e07f
SA		 427static void lpuart_flush_buffer(struct uart_port *port)
428{
429 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
6250cc30 430
bfc2e07f 431 if (sport->lpuart_dma_tx_use) {
6250cc30
BD		 432 if (sport->dma_tx_in_progress) {
433 dma_unmap_sg(sport->port.dev, &sport->tx_sgl[0],
434 sport->dma_tx_nents, DMA_TO_DEVICE);
435 sport->dma_tx_in_progress = false;
436 }
bfc2e07f 437 dmaengine_terminate_all(sport->dma_tx_chan);
bfc2e07f
SA		 438 }
439}
440
2a41bc2a
NR		 441#if defined(CONFIG_CONSOLE_POLL)
442
443static int lpuart_poll_init(struct uart_port *port)
444{
445 struct lpuart_port *sport = container_of(port,
446 struct lpuart_port, port);
447 unsigned long flags;
448 unsigned char temp;
449
450 sport->port.fifosize = 0;
451
452 spin_lock_irqsave(&sport->port.lock, flags);
453 /* Disable Rx & Tx */
454 writeb(0, sport->port.membase + UARTCR2);
455
456 temp = readb(sport->port.membase + UARTPFIFO);
457 /* Enable Rx and Tx FIFO */
458 writeb(temp | UARTPFIFO_RXFE | UARTPFIFO_TXFE,
459 sport->port.membase + UARTPFIFO);
460
461 /* flush Tx and Rx FIFO */
462 writeb(UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH,
463 sport->port.membase + UARTCFIFO);
464
465 /* explicitly clear RDRF */
466 if (readb(sport->port.membase + UARTSR1) & UARTSR1_RDRF) {
467 readb(sport->port.membase + UARTDR);
468 writeb(UARTSFIFO_RXUF, sport->port.membase + UARTSFIFO);
469 }
470
471 writeb(0, sport->port.membase + UARTTWFIFO);
472 writeb(1, sport->port.membase + UARTRWFIFO);
473
474 /* Enable Rx and Tx */
475 writeb(UARTCR2_RE | UARTCR2_TE, sport->port.membase + UARTCR2);
476 spin_unlock_irqrestore(&sport->port.lock, flags);
477
478 return 0;
479}
480
481static void lpuart_poll_put_char(struct uart_port *port, unsigned char c)
482{
2a41bc2a
NR		 483 /* drain */
484 while (!(readb(port->membase + UARTSR1) & UARTSR1_TDRE))
485 barrier();
486
487 writeb(c, port->membase + UARTDR);
488}
489
490static int lpuart_poll_get_char(struct uart_port *port)
491{
492 if (!(readb(port->membase + UARTSR1) & UARTSR1_RDRF))
493 return NO_POLL_CHAR;
494
495 return readb(port->membase + UARTDR);
496}
497
498#endif
499
c9e2e946
JL		 500static inline void lpuart_transmit_buffer(struct lpuart_port *sport)
501{
502 struct circ_buf *xmit = &sport->port.state->xmit;
503
504 while (!uart_circ_empty(xmit) &&
505 (readb(sport->port.membase + UARTTCFIFO) < sport->txfifo_size)) {
506 writeb(xmit->buf[xmit->tail], sport->port.membase + UARTDR);
507 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
508 sport->port.icount.tx++;
509 }
510
511 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
512 uart_write_wakeup(&sport->port);
513
514 if (uart_circ_empty(xmit))
515 lpuart_stop_tx(&sport->port);
516}
517
380c966c
JL		 518static inline void lpuart32_transmit_buffer(struct lpuart_port *sport)
519{
520 struct circ_buf *xmit = &sport->port.state->xmit;
521 unsigned long txcnt;
522
a0204f25 523 txcnt = lpuart32_read(&sport->port, UARTWATER);
380c966c
JL		 524 txcnt = txcnt >> UARTWATER_TXCNT_OFF;
525 txcnt &= UARTWATER_COUNT_MASK;
526 while (!uart_circ_empty(xmit) && (txcnt < sport->txfifo_size)) {
a0204f25 527 lpuart32_write(&sport->port, xmit->buf[xmit->tail], UARTDATA);
380c966c
JL		 528 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
529 sport->port.icount.tx++;
a0204f25 530 txcnt = lpuart32_read(&sport->port, UARTWATER);
380c966c
JL		 531 txcnt = txcnt >> UARTWATER_TXCNT_OFF;
532 txcnt &= UARTWATER_COUNT_MASK;
533 }
534
535 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
536 uart_write_wakeup(&sport->port);
537
538 if (uart_circ_empty(xmit))
539 lpuart32_stop_tx(&sport->port);
540}
541
c9e2e946
JL		 542static void lpuart_start_tx(struct uart_port *port)
543{
f1cd8c87
YY		 544 struct lpuart_port *sport = container_of(port,
545 struct lpuart_port, port);
546 struct circ_buf *xmit = &sport->port.state->xmit;
c9e2e946
JL		 547 unsigned char temp;
548
549 temp = readb(port->membase + UARTCR2);
550 writeb(temp | UARTCR2_TIE, port->membase + UARTCR2);
551
4a818c43 552 if (sport->lpuart_dma_tx_use) {
6250cc30
BD		 553 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port))
554 lpuart_dma_tx(sport);
f1cd8c87
YY		 555 } else {
556 if (readb(port->membase + UARTSR1) & UARTSR1_TDRE)
557 lpuart_transmit_buffer(sport);
558 }
c9e2e946
JL		 559}
560
380c966c
JL		 561static void lpuart32_start_tx(struct uart_port *port)
562{
563 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
564 unsigned long temp;
565
a0204f25
DA		 566 temp = lpuart32_read(port, UARTCTRL);
567 lpuart32_write(port, temp | UARTCTRL_TIE, UARTCTRL);
380c966c 568
a0204f25 569 if (lpuart32_read(port, UARTSTAT) & UARTSTAT_TDRE)
380c966c
JL		 570 lpuart32_transmit_buffer(sport);
571}
572
6250cc30
BD		 573/* return TIOCSER_TEMT when transmitter is not busy */
574static unsigned int lpuart_tx_empty(struct uart_port *port)
575{
576 struct lpuart_port *sport = container_of(port,
577 struct lpuart_port, port);
578 unsigned char sr1 = readb(port->membase + UARTSR1);
579 unsigned char sfifo = readb(port->membase + UARTSFIFO);
580
581 if (sport->dma_tx_in_progress)
582 return 0;
583
584 if (sr1 & UARTSR1_TC && sfifo & UARTSFIFO_TXEMPT)
585 return TIOCSER_TEMT;
586
587 return 0;
588}
589
590static unsigned int lpuart32_tx_empty(struct uart_port *port)
591{
a0204f25 592 return (lpuart32_read(port, UARTSTAT) & UARTSTAT_TC) ?
6250cc30
BD		 593 TIOCSER_TEMT : 0;
594}
595
c9e2e946
JL		 596static irqreturn_t lpuart_txint(int irq, void *dev_id)
597{
598 struct lpuart_port *sport = dev_id;
599 struct circ_buf *xmit = &sport->port.state->xmit;
600 unsigned long flags;
601
602 spin_lock_irqsave(&sport->port.lock, flags);
603 if (sport->port.x_char) {
0d6fce90 604 if (sport->port.iotype & UPIO_MEM32BE)
a0204f25 605 lpuart32_write(&sport->port, sport->port.x_char, UARTDATA);
380c966c
JL		 606 else
607 writeb(sport->port.x_char, sport->port.membase + UARTDR);
c9e2e946
JL		 608 goto out;
609 }
610
611 if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) {
0d6fce90 612 if (sport->port.iotype & UPIO_MEM32BE)
380c966c
JL		 613 lpuart32_stop_tx(&sport->port);
614 else
615 lpuart_stop_tx(&sport->port);
c9e2e946
JL		 616 goto out;
617 }
618
0d6fce90 619 if (sport->port.iotype & UPIO_MEM32BE)
380c966c
JL		 620 lpuart32_transmit_buffer(sport);
621 else
622 lpuart_transmit_buffer(sport);
c9e2e946
JL		 623
624 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
625 uart_write_wakeup(&sport->port);
626
627out:
628 spin_unlock_irqrestore(&sport->port.lock, flags);
629 return IRQ_HANDLED;
630}
631
632static irqreturn_t lpuart_rxint(int irq, void *dev_id)
633{
634 struct lpuart_port *sport = dev_id;
635 unsigned int flg, ignored = 0;
636 struct tty_port *port = &sport->port.state->port;
637 unsigned long flags;
638 unsigned char rx, sr;
639
640 spin_lock_irqsave(&sport->port.lock, flags);
641
642 while (!(readb(sport->port.membase + UARTSFIFO) & UARTSFIFO_RXEMPT)) {
643 flg = TTY_NORMAL;
644 sport->port.icount.rx++;
645 /*
646 * to clear the FE, OR, NF, FE, PE flags,
647 * read SR1 then read DR
648 */
649 sr = readb(sport->port.membase + UARTSR1);
650 rx = readb(sport->port.membase + UARTDR);
651
652 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx))
653 continue;
654
655 if (sr & (UARTSR1_PE | UARTSR1_OR | UARTSR1_FE)) {
656 if (sr & UARTSR1_PE)
657 sport->port.icount.parity++;
658 else if (sr & UARTSR1_FE)
659 sport->port.icount.frame++;
660
661 if (sr & UARTSR1_OR)
662 sport->port.icount.overrun++;
663
664 if (sr & sport->port.ignore_status_mask) {
665 if (++ignored > 100)
666 goto out;
667 continue;
668 }
669
670 sr &= sport->port.read_status_mask;
671
672 if (sr & UARTSR1_PE)
673 flg = TTY_PARITY;
674 else if (sr & UARTSR1_FE)
675 flg = TTY_FRAME;
676
677 if (sr & UARTSR1_OR)
678 flg = TTY_OVERRUN;
679
680#ifdef SUPPORT_SYSRQ
681 sport->port.sysrq = 0;
682#endif
683 }
684
685 tty_insert_flip_char(port, rx, flg);
686 }
687
688out:
689 spin_unlock_irqrestore(&sport->port.lock, flags);
690
691 tty_flip_buffer_push(port);
692 return IRQ_HANDLED;
693}
694
380c966c
JL		 695static irqreturn_t lpuart32_rxint(int irq, void *dev_id)
696{
697 struct lpuart_port *sport = dev_id;
698 unsigned int flg, ignored = 0;
699 struct tty_port *port = &sport->port.state->port;
700 unsigned long flags;
701 unsigned long rx, sr;
702
703 spin_lock_irqsave(&sport->port.lock, flags);
704
a0204f25 705 while (!(lpuart32_read(&sport->port, UARTFIFO) & UARTFIFO_RXEMPT)) {
380c966c
JL		 706 flg = TTY_NORMAL;
707 sport->port.icount.rx++;
708 /*
709 * to clear the FE, OR, NF, FE, PE flags,
710 * read STAT then read DATA reg
711 */
a0204f25
DA		 712 sr = lpuart32_read(&sport->port, UARTSTAT);
713 rx = lpuart32_read(&sport->port, UARTDATA);
380c966c
JL		 714 rx &= 0x3ff;
715
716 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx))
717 continue;
718
719 if (sr & (UARTSTAT_PE | UARTSTAT_OR | UARTSTAT_FE)) {
720 if (sr & UARTSTAT_PE)
721 sport->port.icount.parity++;
722 else if (sr & UARTSTAT_FE)
723 sport->port.icount.frame++;
724
725 if (sr & UARTSTAT_OR)
726 sport->port.icount.overrun++;
727
728 if (sr & sport->port.ignore_status_mask) {
729 if (++ignored > 100)
730 goto out;
731 continue;
732 }
733
734 sr &= sport->port.read_status_mask;
735
736 if (sr & UARTSTAT_PE)
737 flg = TTY_PARITY;
738 else if (sr & UARTSTAT_FE)
739 flg = TTY_FRAME;
740
741 if (sr & UARTSTAT_OR)
742 flg = TTY_OVERRUN;
743
744#ifdef SUPPORT_SYSRQ
745 sport->port.sysrq = 0;
746#endif
747 }
748
749 tty_insert_flip_char(port, rx, flg);
750 }
751
752out:
753 spin_unlock_irqrestore(&sport->port.lock, flags);
754
755 tty_flip_buffer_push(port);
756 return IRQ_HANDLED;
757}
758
c9e2e946
JL		 759static irqreturn_t lpuart_int(int irq, void *dev_id)
760{
761 struct lpuart_port *sport = dev_id;
5887ad43 762 unsigned char sts;
c9e2e946
JL		 763
764 sts = readb(sport->port.membase + UARTSR1);
765
5887ad43
BD		 766 if (sts & UARTSR1_RDRF)
767 lpuart_rxint(irq, dev_id);
768
6250cc30
BD		 769 if (sts & UARTSR1_TDRE)
770 lpuart_txint(irq, dev_id);
c9e2e946
JL		 771
772 return IRQ_HANDLED;
773}
774
380c966c
JL		 775static irqreturn_t lpuart32_int(int irq, void *dev_id)
776{
777 struct lpuart_port *sport = dev_id;
778 unsigned long sts, rxcount;
779
a0204f25
DA		 780 sts = lpuart32_read(&sport->port, UARTSTAT);
781 rxcount = lpuart32_read(&sport->port, UARTWATER);
380c966c
JL		 782 rxcount = rxcount >> UARTWATER_RXCNT_OFF;
783
784 if (sts & UARTSTAT_RDRF || rxcount > 0)
785 lpuart32_rxint(irq, dev_id);
786
787 if ((sts & UARTSTAT_TDRE) &&
a0204f25 788 !(lpuart32_read(&sport->port, UARTBAUD) & UARTBAUD_TDMAE))
380c966c
JL		 789 lpuart_txint(irq, dev_id);
790
a0204f25 791 lpuart32_write(&sport->port, sts, UARTSTAT);
380c966c
JL		 792 return IRQ_HANDLED;
793}
794
5887ad43
BD		 795static void lpuart_copy_rx_to_tty(struct lpuart_port *sport)
796{
797 struct tty_port *port = &sport->port.state->port;
798 struct dma_tx_state state;
799 enum dma_status dmastat;
800 struct circ_buf *ring = &sport->rx_ring;
801 unsigned long flags;
802 int count = 0;
803 unsigned char sr;
804
805 sr = readb(sport->port.membase + UARTSR1);
806
807 if (sr & (UARTSR1_PE | UARTSR1_FE)) {
808 /* Read DR to clear the error flags */
809 readb(sport->port.membase + UARTDR);
810
811 if (sr & UARTSR1_PE)
812 sport->port.icount.parity++;
813 else if (sr & UARTSR1_FE)
814 sport->port.icount.frame++;
815 }
816
817 async_tx_ack(sport->dma_rx_desc);
818
819 spin_lock_irqsave(&sport->port.lock, flags);
820
821 dmastat = dmaengine_tx_status(sport->dma_rx_chan,
822 sport->dma_rx_cookie,
823 &state);
824
825 if (dmastat == DMA_ERROR) {
826 dev_err(sport->port.dev, "Rx DMA transfer failed!\n");
827 spin_unlock_irqrestore(&sport->port.lock, flags);
828 return;
829 }
830
831 /* CPU claims ownership of RX DMA buffer */
832 dma_sync_sg_for_cpu(sport->port.dev, &sport->rx_sgl, 1, DMA_FROM_DEVICE);
833
834 /*
835 * ring->head points to the end of data already written by the DMA.
836 * ring->tail points to the beginning of data to be read by the
837 * framework.
838 * The current transfer size should not be larger than the dma buffer
839 * length.
840 */
841 ring->head = sport->rx_sgl.length - state.residue;
842 BUG_ON(ring->head > sport->rx_sgl.length);
843 /*
844 * At this point ring->head may point to the first byte right after the
845 * last byte of the dma buffer:
846 * 0 <= ring->head <= sport->rx_sgl.length
847 *
848 * However ring->tail must always points inside the dma buffer:
849 * 0 <= ring->tail <= sport->rx_sgl.length - 1
850 *
851 * Since we use a ring buffer, we have to handle the case
852 * where head is lower than tail. In such a case, we first read from
853 * tail to the end of the buffer then reset tail.
854 */
855 if (ring->head < ring->tail) {
856 count = sport->rx_sgl.length - ring->tail;
857
858 tty_insert_flip_string(port, ring->buf + ring->tail, count);
859 ring->tail = 0;
860 sport->port.icount.rx += count;
861 }
862
863 /* Finally we read data from tail to head */
864 if (ring->tail < ring->head) {
865 count = ring->head - ring->tail;
866 tty_insert_flip_string(port, ring->buf + ring->tail, count);
867 /* Wrap ring->head if needed */
868 if (ring->head >= sport->rx_sgl.length)
869 ring->head = 0;
870 ring->tail = ring->head;
871 sport->port.icount.rx += count;
872 }
873
874 dma_sync_sg_for_device(sport->port.dev, &sport->rx_sgl, 1,
875 DMA_FROM_DEVICE);
876
877 spin_unlock_irqrestore(&sport->port.lock, flags);
878
879 tty_flip_buffer_push(port);
880 mod_timer(&sport->lpuart_timer, jiffies + sport->dma_rx_timeout);
881}
882
883static void lpuart_dma_rx_complete(void *arg)
884{
885 struct lpuart_port *sport = arg;
886
887 lpuart_copy_rx_to_tty(sport);
888}
889
890static void lpuart_timer_func(unsigned long data)
891{
892 struct lpuart_port *sport = (struct lpuart_port *)data;
893
894 lpuart_copy_rx_to_tty(sport);
895}
896
897static inline int lpuart_start_rx_dma(struct lpuart_port *sport)
898{
899 struct dma_slave_config dma_rx_sconfig = {};
900 struct circ_buf *ring = &sport->rx_ring;
901 int ret, nent;
902 int bits, baud;
903 struct tty_struct *tty = tty_port_tty_get(&sport->port.state->port);
904 struct ktermios *termios = &tty->termios;
905
906 baud = tty_get_baud_rate(tty);
907
908 bits = (termios->c_cflag & CSIZE) == CS7 ? 9 : 10;
909 if (termios->c_cflag & PARENB)
910 bits++;
911
912 /*
913 * Calculate length of one DMA buffer size to keep latency below
914 * 10ms at any baud rate.
915 */
916 sport->rx_dma_rng_buf_len = (DMA_RX_TIMEOUT * baud / bits / 1000) * 2;
917 sport->rx_dma_rng_buf_len = (1 << (fls(sport->rx_dma_rng_buf_len) - 1));
918 if (sport->rx_dma_rng_buf_len < 16)
919 sport->rx_dma_rng_buf_len = 16;
920
33ddca08 921 ring->buf = kmalloc(sport->rx_dma_rng_buf_len, GFP_ATOMIC);
5887ad43
BD		 922 if (!ring->buf) {
923 dev_err(sport->port.dev, "Ring buf alloc failed\n");
924 return -ENOMEM;
925 }
926
927 sg_init_one(&sport->rx_sgl, ring->buf, sport->rx_dma_rng_buf_len);
928 sg_set_buf(&sport->rx_sgl, ring->buf, sport->rx_dma_rng_buf_len);
929 nent = dma_map_sg(sport->port.dev, &sport->rx_sgl, 1, DMA_FROM_DEVICE);
930
931 if (!nent) {
932 dev_err(sport->port.dev, "DMA Rx mapping error\n");
933 return -EINVAL;
934 }
935
936 dma_rx_sconfig.src_addr = sport->port.mapbase + UARTDR;
937 dma_rx_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
938 dma_rx_sconfig.src_maxburst = 1;
939 dma_rx_sconfig.direction = DMA_DEV_TO_MEM;
940 ret = dmaengine_slave_config(sport->dma_rx_chan, &dma_rx_sconfig);
941
942 if (ret < 0) {
943 dev_err(sport->port.dev,
944 "DMA Rx slave config failed, err = %d\n", ret);
945 return ret;
946 }
947
948 sport->dma_rx_desc = dmaengine_prep_dma_cyclic(sport->dma_rx_chan,
949 sg_dma_address(&sport->rx_sgl),
950 sport->rx_sgl.length,
951 sport->rx_sgl.length / 2,
952 DMA_DEV_TO_MEM,
953 DMA_PREP_INTERRUPT);
954 if (!sport->dma_rx_desc) {
955 dev_err(sport->port.dev, "Cannot prepare cyclic DMA\n");
956 return -EFAULT;
957 }
958
959 sport->dma_rx_desc->callback = lpuart_dma_rx_complete;
960 sport->dma_rx_desc->callback_param = sport;
961 sport->dma_rx_cookie = dmaengine_submit(sport->dma_rx_desc);
962 dma_async_issue_pending(sport->dma_rx_chan);
963
964 writeb(readb(sport->port.membase + UARTCR5) | UARTCR5_RDMAS,
965 sport->port.membase + UARTCR5);
966
967 return 0;
968}
969
5887ad43
BD		 970static void lpuart_dma_rx_free(struct uart_port *port)
971{
972 struct lpuart_port *sport = container_of(port,
973 struct lpuart_port, port);
974
975 if (sport->dma_rx_chan)
976 dmaengine_terminate_all(sport->dma_rx_chan);
977
978 dma_unmap_sg(sport->port.dev, &sport->rx_sgl, 1, DMA_FROM_DEVICE);
979 kfree(sport->rx_ring.buf);
980 sport->rx_ring.tail = 0;
981 sport->rx_ring.head = 0;
982 sport->dma_rx_desc = NULL;
983 sport->dma_rx_cookie = -EINVAL;
984}
985
03895cf4
BD		 986static int lpuart_config_rs485(struct uart_port *port,
987 struct serial_rs485 *rs485)
988{
989 struct lpuart_port *sport = container_of(port,
990 struct lpuart_port, port);
991
992 u8 modem = readb(sport->port.membase + UARTMODEM) &
993 ~(UARTMODEM_TXRTSPOL | UARTMODEM_TXRTSE);
994 writeb(modem, sport->port.membase + UARTMODEM);
995
996 if (rs485->flags & SER_RS485_ENABLED) {
997 /* Enable auto RS-485 RTS mode */
998 modem |= UARTMODEM_TXRTSE;
999
1000 /*
1001 * RTS needs to be logic HIGH either during transer _or_ after
1002 * transfer, other variants are not supported by the hardware.
1003 */
1004
1005 if (!(rs485->flags & (SER_RS485_RTS_ON_SEND |
1006 SER_RS485_RTS_AFTER_SEND)))
1007 rs485->flags |= SER_RS485_RTS_ON_SEND;
1008
1009 if (rs485->flags & SER_RS485_RTS_ON_SEND &&
1010 rs485->flags & SER_RS485_RTS_AFTER_SEND)
1011 rs485->flags &= ~SER_RS485_RTS_AFTER_SEND;
1012
1013 /*
1014 * The hardware defaults to RTS logic HIGH while transfer.
1015 * Switch polarity in case RTS shall be logic HIGH
1016 * after transfer.
1017 * Note: UART is assumed to be active high.
1018 */
1019 if (rs485->flags & SER_RS485_RTS_ON_SEND)
1020 modem &= ~UARTMODEM_TXRTSPOL;
1021 else if (rs485->flags & SER_RS485_RTS_AFTER_SEND)
1022 modem |= UARTMODEM_TXRTSPOL;
1023 }
1024
1025 /* Store the new configuration */
1026 sport->port.rs485 = *rs485;
1027
1028 writeb(modem, sport->port.membase + UARTMODEM);
1029 return 0;
1030}
1031
c9e2e946
JL		 1032static unsigned int lpuart_get_mctrl(struct uart_port *port)
1033{
1034 unsigned int temp = 0;
1035 unsigned char reg;
1036
1037 reg = readb(port->membase + UARTMODEM);
1038 if (reg & UARTMODEM_TXCTSE)
1039 temp |= TIOCM_CTS;
1040
1041 if (reg & UARTMODEM_RXRTSE)
1042 temp |= TIOCM_RTS;
1043
1044 return temp;
1045}
1046
380c966c
JL		 1047static unsigned int lpuart32_get_mctrl(struct uart_port *port)
1048{
1049 unsigned int temp = 0;
1050 unsigned long reg;
1051
a0204f25 1052 reg = lpuart32_read(port, UARTMODIR);
380c966c
JL		 1053 if (reg & UARTMODIR_TXCTSE)
1054 temp |= TIOCM_CTS;
1055
1056 if (reg & UARTMODIR_RXRTSE)
1057 temp |= TIOCM_RTS;
1058
1059 return temp;
1060}
1061
c9e2e946
JL		 1062static void lpuart_set_mctrl(struct uart_port *port, unsigned int mctrl)
1063{
1064 unsigned char temp;
03895cf4
BD		 1065 struct lpuart_port *sport = container_of(port,
1066 struct lpuart_port, port);
c9e2e946 1067
03895cf4
BD		 1068 /* Make sure RXRTSE bit is not set when RS485 is enabled */
1069 if (!(sport->port.rs485.flags & SER_RS485_ENABLED)) {
1070 temp = readb(sport->port.membase + UARTMODEM) &
c9e2e946
JL		 1071 ~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE);
1072
03895cf4
BD		 1073 if (mctrl & TIOCM_RTS)
1074 temp |= UARTMODEM_RXRTSE;
c9e2e946 1075
03895cf4
BD		 1076 if (mctrl & TIOCM_CTS)
1077 temp |= UARTMODEM_TXCTSE;
c9e2e946 1078
03895cf4
BD		 1079 writeb(temp, port->membase + UARTMODEM);
1080 }
c9e2e946
JL		 1081}
1082
380c966c
JL		 1083static void lpuart32_set_mctrl(struct uart_port *port, unsigned int mctrl)
1084{
1085 unsigned long temp;
1086
a0204f25 1087 temp = lpuart32_read(port, UARTMODIR) &
380c966c
JL		 1088 ~(UARTMODIR_RXRTSE | UARTMODIR_TXCTSE);
1089
1090 if (mctrl & TIOCM_RTS)
1091 temp |= UARTMODIR_RXRTSE;
1092
1093 if (mctrl & TIOCM_CTS)
1094 temp |= UARTMODIR_TXCTSE;
1095
a0204f25 1096 lpuart32_write(port, temp, UARTMODIR);
380c966c
JL		 1097}
1098
c9e2e946
JL		 1099static void lpuart_break_ctl(struct uart_port *port, int break_state)
1100{
1101 unsigned char temp;
1102
1103 temp = readb(port->membase + UARTCR2) & ~UARTCR2_SBK;
1104
1105 if (break_state != 0)
1106 temp |= UARTCR2_SBK;
1107
1108 writeb(temp, port->membase + UARTCR2);
1109}
1110
380c966c
JL		 1111static void lpuart32_break_ctl(struct uart_port *port, int break_state)
1112{
1113 unsigned long temp;
1114
a0204f25 1115 temp = lpuart32_read(port, UARTCTRL) & ~UARTCTRL_SBK;
380c966c
JL		 1116
1117 if (break_state != 0)
1118 temp |= UARTCTRL_SBK;
1119
a0204f25 1120 lpuart32_write(port, temp, UARTCTRL);
380c966c
JL		 1121}
1122
c9e2e946
JL		 1123static void lpuart_setup_watermark(struct lpuart_port *sport)
1124{
1125 unsigned char val, cr2;
bc764b8f 1126 unsigned char cr2_saved;
c9e2e946
JL		 1127
1128 cr2 = readb(sport->port.membase + UARTCR2);
bc764b8f 1129 cr2_saved = cr2;
c9e2e946
JL		 1130 cr2 &= ~(UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_TE |
1131 UARTCR2_RIE | UARTCR2_RE);
1132 writeb(cr2, sport->port.membase + UARTCR2);
1133
c9e2e946 1134 val = readb(sport->port.membase + UARTPFIFO);
c9e2e946
JL		 1135 writeb(val | UARTPFIFO_TXFE | UARTPFIFO_RXFE,
1136 sport->port.membase + UARTPFIFO);
1137
1138 /* flush Tx and Rx FIFO */
1139 writeb(UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH,
1140 sport->port.membase + UARTCFIFO);
1141
d68827c6
SA		 1142 /* explicitly clear RDRF */
1143 if (readb(sport->port.membase + UARTSR1) & UARTSR1_RDRF) {
1144 readb(sport->port.membase + UARTDR);
1145 writeb(UARTSFIFO_RXUF, sport->port.membase + UARTSFIFO);
1146 }
1147
f1cd8c87 1148 writeb(0, sport->port.membase + UARTTWFIFO);
c9e2e946 1149 writeb(1, sport->port.membase + UARTRWFIFO);
bc764b8f
SG		 1150
1151 /* Restore cr2 */
1152 writeb(cr2_saved, sport->port.membase + UARTCR2);
c9e2e946
JL		 1153}
1154
380c966c
JL		 1155static void lpuart32_setup_watermark(struct lpuart_port *sport)
1156{
1157 unsigned long val, ctrl;
1158 unsigned long ctrl_saved;
1159
a0204f25 1160 ctrl = lpuart32_read(&sport->port, UARTCTRL);
380c966c
JL		 1161 ctrl_saved = ctrl;
1162 ctrl &= ~(UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_TE |
1163 UARTCTRL_RIE | UARTCTRL_RE);
a0204f25 1164 lpuart32_write(&sport->port, ctrl, UARTCTRL);
380c966c
JL		 1165
1166 /* enable FIFO mode */
a0204f25 1167 val = lpuart32_read(&sport->port, UARTFIFO);
380c966c
JL		 1168 val |= UARTFIFO_TXFE | UARTFIFO_RXFE;
1169 val |= UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH;
a0204f25 1170 lpuart32_write(&sport->port, val, UARTFIFO);
380c966c
JL		 1171
1172 /* set the watermark */
1173 val = (0x1 << UARTWATER_RXWATER_OFF) | (0x0 << UARTWATER_TXWATER_OFF);
a0204f25 1174 lpuart32_write(&sport->port, val, UARTWATER);
380c966c
JL		 1175
1176 /* Restore cr2 */
a0204f25 1177 lpuart32_write(&sport->port, ctrl_saved, UARTCTRL);
380c966c
JL		 1178}
1179
5887ad43 1180static void rx_dma_timer_init(struct lpuart_port *sport)
f1cd8c87 1181{
5887ad43
BD		 1182 setup_timer(&sport->lpuart_timer, lpuart_timer_func,
1183 (unsigned long)sport);
1184 sport->lpuart_timer.expires = jiffies + sport->dma_rx_timeout;
1185 add_timer(&sport->lpuart_timer);
f1cd8c87
YY		 1186}
1187
c9e2e946
JL		 1188static int lpuart_startup(struct uart_port *port)
1189{
1190 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1191 int ret;
1192 unsigned long flags;
1193 unsigned char temp;
1194
ed9891bf
SA		 1195 /* determine FIFO size and enable FIFO mode */
1196 temp = readb(sport->port.membase + UARTPFIFO);
1197
1198 sport->txfifo_size = 0x1 << (((temp >> UARTPFIFO_TXSIZE_OFF) &
1199 UARTPFIFO_FIFOSIZE_MASK) + 1);
1200
4e8f2459
SA		 1201 sport->port.fifosize = sport->txfifo_size;
1202
ed9891bf
SA		 1203 sport->rxfifo_size = 0x1 << (((temp >> UARTPFIFO_RXSIZE_OFF) &
1204 UARTPFIFO_FIFOSIZE_MASK) + 1);
1205
c9e2e946
JL		 1206 ret = devm_request_irq(port->dev, port->irq, lpuart_int, 0,
1207 DRIVER_NAME, sport);
1208 if (ret)
1209 return ret;
1210
1211 spin_lock_irqsave(&sport->port.lock, flags);
1212
1213 lpuart_setup_watermark(sport);
1214
1215 temp = readb(sport->port.membase + UARTCR2);
1216 temp |= (UARTCR2_RIE | UARTCR2_TIE | UARTCR2_RE | UARTCR2_TE);
1217 writeb(temp, sport->port.membase + UARTCR2);
1218
5887ad43
BD		 1219 if (sport->dma_rx_chan && !lpuart_start_rx_dma(sport)) {
1220 /* set Rx DMA timeout */
1221 sport->dma_rx_timeout = msecs_to_jiffies(DMA_RX_TIMEOUT);
1222 if (!sport->dma_rx_timeout)
1223 sport->dma_rx_timeout = 1;
1224
1225 sport->lpuart_dma_rx_use = true;
1226 rx_dma_timer_init(sport);
1227 } else {
1228 sport->lpuart_dma_rx_use = false;
1229 }
1230
1231 if (sport->dma_tx_chan && !lpuart_dma_tx_request(port)) {
6250cc30 1232 init_waitqueue_head(&sport->dma_wait);
5887ad43
BD		 1233 sport->lpuart_dma_tx_use = true;
1234 temp = readb(port->membase + UARTCR5);
1235 writeb(temp | UARTCR5_TDMAS, port->membase + UARTCR5);
1236 } else {
1237 sport->lpuart_dma_tx_use = false;
1238 }
1239
c9e2e946 1240 spin_unlock_irqrestore(&sport->port.lock, flags);
5887ad43 1241
c9e2e946
JL		 1242 return 0;
1243}
1244
380c966c
JL		 1245static int lpuart32_startup(struct uart_port *port)
1246{
1247 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1248 int ret;
1249 unsigned long flags;
1250 unsigned long temp;
1251
1252 /* determine FIFO size */
a0204f25 1253 temp = lpuart32_read(&sport->port, UARTFIFO);
380c966c
JL		 1254
1255 sport->txfifo_size = 0x1 << (((temp >> UARTFIFO_TXSIZE_OFF) &
1256 UARTFIFO_FIFOSIZE_MASK) - 1);
1257
1258 sport->rxfifo_size = 0x1 << (((temp >> UARTFIFO_RXSIZE_OFF) &
1259 UARTFIFO_FIFOSIZE_MASK) - 1);
1260
1261 ret = devm_request_irq(port->dev, port->irq, lpuart32_int, 0,
1262 DRIVER_NAME, sport);
1263 if (ret)
1264 return ret;
1265
1266 spin_lock_irqsave(&sport->port.lock, flags);
1267
1268 lpuart32_setup_watermark(sport);
1269
a0204f25 1270 temp = lpuart32_read(&sport->port, UARTCTRL);
380c966c
JL		 1271 temp |= (UARTCTRL_RIE | UARTCTRL_TIE | UARTCTRL_RE | UARTCTRL_TE);
1272 temp |= UARTCTRL_ILIE;
a0204f25 1273 lpuart32_write(&sport->port, temp, UARTCTRL);
380c966c
JL		 1274
1275 spin_unlock_irqrestore(&sport->port.lock, flags);
1276 return 0;
1277}
1278
c9e2e946
JL		 1279static void lpuart_shutdown(struct uart_port *port)
1280{
1281 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1282 unsigned char temp;
1283 unsigned long flags;
1284
1285 spin_lock_irqsave(&port->lock, flags);
1286
1287 /* disable Rx/Tx and interrupts */
1288 temp = readb(port->membase + UARTCR2);
1289 temp &= ~(UARTCR2_TE | UARTCR2_RE |
1290 UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_RIE);
1291 writeb(temp, port->membase + UARTCR2);
1292
1293 spin_unlock_irqrestore(&port->lock, flags);
1294
1295 devm_free_irq(port->dev, port->irq, sport);
f1cd8c87 1296
4a818c43 1297 if (sport->lpuart_dma_rx_use) {
4a8588a1 1298 del_timer_sync(&sport->lpuart_timer);
5887ad43 1299 lpuart_dma_rx_free(&sport->port);
f1cd8c87 1300 }
4a818c43 1301
6250cc30
BD		 1302 if (sport->lpuart_dma_tx_use) {
1303 if (wait_event_interruptible(sport->dma_wait,
1304 !sport->dma_tx_in_progress) != false) {
1305 sport->dma_tx_in_progress = false;
1306 dmaengine_terminate_all(sport->dma_tx_chan);
1307 }
1308
1309 lpuart_stop_tx(port);
1310 }
c9e2e946
JL		 1311}
1312
380c966c
JL		 1313static void lpuart32_shutdown(struct uart_port *port)
1314{
1315 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1316 unsigned long temp;
1317 unsigned long flags;
1318
1319 spin_lock_irqsave(&port->lock, flags);
1320
1321 /* disable Rx/Tx and interrupts */
a0204f25 1322 temp = lpuart32_read(port, UARTCTRL);
380c966c
JL		 1323 temp &= ~(UARTCTRL_TE | UARTCTRL_RE |
1324 UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_RIE);
a0204f25 1325 lpuart32_write(port, temp, UARTCTRL);
380c966c
JL		 1326
1327 spin_unlock_irqrestore(&port->lock, flags);
1328
1329 devm_free_irq(port->dev, port->irq, sport);
1330}
1331
c9e2e946
JL		 1332static void
1333lpuart_set_termios(struct uart_port *port, struct ktermios *termios,
1334 struct ktermios *old)
1335{
1336 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1337 unsigned long flags;
aa9e7d78 1338 unsigned char cr1, old_cr1, old_cr2, cr3, cr4, bdh, modem;
c9e2e946
JL		 1339 unsigned int baud;
1340 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
1341 unsigned int sbr, brfa;
1342
1343 cr1 = old_cr1 = readb(sport->port.membase + UARTCR1);
1344 old_cr2 = readb(sport->port.membase + UARTCR2);
aa9e7d78 1345 cr3 = readb(sport->port.membase + UARTCR3);
c9e2e946
JL		 1346 cr4 = readb(sport->port.membase + UARTCR4);
1347 bdh = readb(sport->port.membase + UARTBDH);
1348 modem = readb(sport->port.membase + UARTMODEM);
1349 /*
1350 * only support CS8 and CS7, and for CS7 must enable PE.
1351 * supported mode:
1352 * - (7,e/o,1)
1353 * - (8,n,1)
1354 * - (8,m/s,1)
1355 * - (8,e/o,1)
1356 */
1357 while ((termios->c_cflag & CSIZE) != CS8 &&
1358 (termios->c_cflag & CSIZE) != CS7) {
1359 termios->c_cflag &= ~CSIZE;
1360 termios->c_cflag |= old_csize;
1361 old_csize = CS8;
1362 }
1363
1364 if ((termios->c_cflag & CSIZE) == CS8 ||
1365 (termios->c_cflag & CSIZE) == CS7)
1366 cr1 = old_cr1 & ~UARTCR1_M;
1367
1368 if (termios->c_cflag & CMSPAR) {
1369 if ((termios->c_cflag & CSIZE) != CS8) {
1370 termios->c_cflag &= ~CSIZE;
1371 termios->c_cflag |= CS8;
1372 }
1373 cr1 |= UARTCR1_M;
1374 }
1375
03895cf4
BD		 1376 /*
1377 * When auto RS-485 RTS mode is enabled,
1378 * hardware flow control need to be disabled.
1379 */
1380 if (sport->port.rs485.flags & SER_RS485_ENABLED)
1381 termios->c_cflag &= ~CRTSCTS;
1382
c9e2e946
JL		 1383 if (termios->c_cflag & CRTSCTS) {
1384 modem |= (UARTMODEM_RXRTSE | UARTMODEM_TXCTSE);
1385 } else {
1386 termios->c_cflag &= ~CRTSCTS;
1387 modem &= ~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE);
1388 }
1389
1390 if (termios->c_cflag & CSTOPB)
1391 termios->c_cflag &= ~CSTOPB;
1392
1393 /* parity must be enabled when CS7 to match 8-bits format */
1394 if ((termios->c_cflag & CSIZE) == CS7)
1395 termios->c_cflag |= PARENB;
1396
1397 if ((termios->c_cflag & PARENB)) {
1398 if (termios->c_cflag & CMSPAR) {
1399 cr1 &= ~UARTCR1_PE;
aa9e7d78
BD		 1400 if (termios->c_cflag & PARODD)
1401 cr3 |= UARTCR3_T8;
1402 else
1403 cr3 &= ~UARTCR3_T8;
c9e2e946
JL		 1404 } else {
1405 cr1 |= UARTCR1_PE;
1406 if ((termios->c_cflag & CSIZE) == CS8)
1407 cr1 |= UARTCR1_M;
1408 if (termios->c_cflag & PARODD)
1409 cr1 |= UARTCR1_PT;
1410 else
1411 cr1 &= ~UARTCR1_PT;
1412 }
1413 }
1414
1415 /* ask the core to calculate the divisor */
1416 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
1417
54a44d54
NY		 1418 /*
1419 * Need to update the Ring buffer length according to the selected
1420 * baud rate and restart Rx DMA path.
1421 *
1422 * Since timer function acqures sport->port.lock, need to stop before
1423 * acquring same lock because otherwise del_timer_sync() can deadlock.
1424 */
1425 if (old && sport->lpuart_dma_rx_use) {
1426 del_timer_sync(&sport->lpuart_timer);
1427 lpuart_dma_rx_free(&sport->port);
1428 }
1429
c9e2e946
JL		 1430 spin_lock_irqsave(&sport->port.lock, flags);
1431
1432 sport->port.read_status_mask = 0;
1433 if (termios->c_iflag & INPCK)
1434 sport->port.read_status_mask |= (UARTSR1_FE | UARTSR1_PE);
ef8b9ddc 1435 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
c9e2e946
JL		 1436 sport->port.read_status_mask |= UARTSR1_FE;
1437
1438 /* characters to ignore */
1439 sport->port.ignore_status_mask = 0;
1440 if (termios->c_iflag & IGNPAR)
1441 sport->port.ignore_status_mask |= UARTSR1_PE;
1442 if (termios->c_iflag & IGNBRK) {
1443 sport->port.ignore_status_mask |= UARTSR1_FE;
1444 /*
1445 * if we're ignoring parity and break indicators,
1446 * ignore overruns too (for real raw support).
1447 */
1448 if (termios->c_iflag & IGNPAR)
1449 sport->port.ignore_status_mask |= UARTSR1_OR;
1450 }
1451
1452 /* update the per-port timeout */
1453 uart_update_timeout(port, termios->c_cflag, baud);
1454
1455 /* wait transmit engin complete */
1456 while (!(readb(sport->port.membase + UARTSR1) & UARTSR1_TC))
1457 barrier();
1458
1459 /* disable transmit and receive */
1460 writeb(old_cr2 & ~(UARTCR2_TE | UARTCR2_RE),
1461 sport->port.membase + UARTCR2);
1462
1463 sbr = sport->port.uartclk / (16 * baud);
1464 brfa = ((sport->port.uartclk - (16 * sbr * baud)) * 2) / baud;
1465 bdh &= ~UARTBDH_SBR_MASK;
1466 bdh |= (sbr >> 8) & 0x1F;
1467 cr4 &= ~UARTCR4_BRFA_MASK;
1468 brfa &= UARTCR4_BRFA_MASK;
1469 writeb(cr4 | brfa, sport->port.membase + UARTCR4);
1470 writeb(bdh, sport->port.membase + UARTBDH);
1471 writeb(sbr & 0xFF, sport->port.membase + UARTBDL);
aa9e7d78 1472 writeb(cr3, sport->port.membase + UARTCR3);
c9e2e946
JL		 1473 writeb(cr1, sport->port.membase + UARTCR1);
1474 writeb(modem, sport->port.membase + UARTMODEM);
1475
1476 /* restore control register */
1477 writeb(old_cr2, sport->port.membase + UARTCR2);
1478
54a44d54
NY		 1479 if (old && sport->lpuart_dma_rx_use) {
1480 if (!lpuart_start_rx_dma(sport))
5887ad43 1481 rx_dma_timer_init(sport);
54a44d54 1482 else
5887ad43 1483 sport->lpuart_dma_rx_use = false;
5887ad43
BD		 1484 }
1485
c9e2e946
JL		 1486 spin_unlock_irqrestore(&sport->port.lock, flags);
1487}
1488
380c966c
JL		 1489static void
1490lpuart32_set_termios(struct uart_port *port, struct ktermios *termios,
1491 struct ktermios *old)
1492{
1493 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1494 unsigned long flags;
1495 unsigned long ctrl, old_ctrl, bd, modem;
1496 unsigned int baud;
1497 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
1498 unsigned int sbr;
1499
a0204f25
DA		 1500 ctrl = old_ctrl = lpuart32_read(&sport->port, UARTCTRL);
1501 bd = lpuart32_read(&sport->port, UARTBAUD);
1502 modem = lpuart32_read(&sport->port, UARTMODIR);
380c966c
JL		 1503 /*
1504 * only support CS8 and CS7, and for CS7 must enable PE.
1505 * supported mode:
1506 * - (7,e/o,1)
1507 * - (8,n,1)
1508 * - (8,m/s,1)
1509 * - (8,e/o,1)
1510 */
1511 while ((termios->c_cflag & CSIZE) != CS8 &&
1512 (termios->c_cflag & CSIZE) != CS7) {
1513 termios->c_cflag &= ~CSIZE;
1514 termios->c_cflag |= old_csize;
1515 old_csize = CS8;
1516 }
1517
1518 if ((termios->c_cflag & CSIZE) == CS8 ||
1519 (termios->c_cflag & CSIZE) == CS7)
1520 ctrl = old_ctrl & ~UARTCTRL_M;
1521
1522 if (termios->c_cflag & CMSPAR) {
1523 if ((termios->c_cflag & CSIZE) != CS8) {
1524 termios->c_cflag &= ~CSIZE;
1525 termios->c_cflag |= CS8;
1526 }
1527 ctrl |= UARTCTRL_M;
1528 }
1529
1530 if (termios->c_cflag & CRTSCTS) {
1531 modem |= (UARTMODEM_RXRTSE | UARTMODEM_TXCTSE);
1532 } else {
1533 termios->c_cflag &= ~CRTSCTS;
1534 modem &= ~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE);
1535 }
1536
1537 if (termios->c_cflag & CSTOPB)
1538 termios->c_cflag &= ~CSTOPB;
1539
1540 /* parity must be enabled when CS7 to match 8-bits format */
1541 if ((termios->c_cflag & CSIZE) == CS7)
1542 termios->c_cflag |= PARENB;
1543
1544 if ((termios->c_cflag & PARENB)) {
1545 if (termios->c_cflag & CMSPAR) {
1546 ctrl &= ~UARTCTRL_PE;
1547 ctrl |= UARTCTRL_M;
1548 } else {
1549 ctrl |= UARTCR1_PE;
1550 if ((termios->c_cflag & CSIZE) == CS8)
1551 ctrl |= UARTCTRL_M;
1552 if (termios->c_cflag & PARODD)
1553 ctrl |= UARTCTRL_PT;
1554 else
1555 ctrl &= ~UARTCTRL_PT;
1556 }
1557 }
1558
1559 /* ask the core to calculate the divisor */
1560 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
1561
1562 spin_lock_irqsave(&sport->port.lock, flags);
1563
1564 sport->port.read_status_mask = 0;
1565 if (termios->c_iflag & INPCK)
1566 sport->port.read_status_mask |= (UARTSTAT_FE | UARTSTAT_PE);
1567 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
1568 sport->port.read_status_mask |= UARTSTAT_FE;
1569
1570 /* characters to ignore */
1571 sport->port.ignore_status_mask = 0;
1572 if (termios->c_iflag & IGNPAR)
1573 sport->port.ignore_status_mask |= UARTSTAT_PE;
1574 if (termios->c_iflag & IGNBRK) {
1575 sport->port.ignore_status_mask |= UARTSTAT_FE;
1576 /*
1577 * if we're ignoring parity and break indicators,
1578 * ignore overruns too (for real raw support).
1579 */
1580 if (termios->c_iflag & IGNPAR)
1581 sport->port.ignore_status_mask |= UARTSTAT_OR;
1582 }
1583
1584 /* update the per-port timeout */
1585 uart_update_timeout(port, termios->c_cflag, baud);
1586
1587 /* wait transmit engin complete */
a0204f25 1588 while (!(lpuart32_read(&sport->port, UARTSTAT) & UARTSTAT_TC))
380c966c
JL		 1589 barrier();
1590
1591 /* disable transmit and receive */
a0204f25
DA		 1592 lpuart32_write(&sport->port, old_ctrl & ~(UARTCTRL_TE | UARTCTRL_RE),
1593 UARTCTRL);
380c966c
JL		 1594
1595 sbr = sport->port.uartclk / (16 * baud);
1596 bd &= ~UARTBAUD_SBR_MASK;
1597 bd |= sbr & UARTBAUD_SBR_MASK;
1598 bd |= UARTBAUD_BOTHEDGE;
1599 bd &= ~(UARTBAUD_TDMAE | UARTBAUD_RDMAE);
a0204f25
DA		 1600 lpuart32_write(&sport->port, bd, UARTBAUD);
1601 lpuart32_write(&sport->port, modem, UARTMODIR);
1602 lpuart32_write(&sport->port, ctrl, UARTCTRL);
380c966c
JL		 1603 /* restore control register */
1604
1605 spin_unlock_irqrestore(&sport->port.lock, flags);
1606}
1607
c9e2e946
JL		 1608static const char *lpuart_type(struct uart_port *port)
1609{
1610 return "FSL_LPUART";
1611}
1612
1613static void lpuart_release_port(struct uart_port *port)
1614{
1615 /* nothing to do */
1616}
1617
1618static int lpuart_request_port(struct uart_port *port)
1619{
1620 return 0;
1621}
1622
1623/* configure/autoconfigure the port */
1624static void lpuart_config_port(struct uart_port *port, int flags)
1625{
1626 if (flags & UART_CONFIG_TYPE)
1627 port->type = PORT_LPUART;
1628}
1629
1630static int lpuart_verify_port(struct uart_port *port, struct serial_struct *ser)
1631{
1632 int ret = 0;
1633
1634 if (ser->type != PORT_UNKNOWN && ser->type != PORT_LPUART)
1635 ret = -EINVAL;
1636 if (port->irq != ser->irq)
1637 ret = -EINVAL;
1638 if (ser->io_type != UPIO_MEM)
1639 ret = -EINVAL;
1640 if (port->uartclk / 16 != ser->baud_base)
1641 ret = -EINVAL;
1642 if (port->iobase != ser->port)
1643 ret = -EINVAL;
1644 if (ser->hub6 != 0)
1645 ret = -EINVAL;
1646 return ret;
1647}
1648
069a47e5 1649static const struct uart_ops lpuart_pops = {
c9e2e946
JL		 1650 .tx_empty = lpuart_tx_empty,
1651 .set_mctrl = lpuart_set_mctrl,
1652 .get_mctrl = lpuart_get_mctrl,
1653 .stop_tx = lpuart_stop_tx,
1654 .start_tx = lpuart_start_tx,
1655 .stop_rx = lpuart_stop_rx,
c9e2e946
JL		 1656 .break_ctl = lpuart_break_ctl,
1657 .startup = lpuart_startup,
1658 .shutdown = lpuart_shutdown,
1659 .set_termios = lpuart_set_termios,
1660 .type = lpuart_type,
1661 .request_port = lpuart_request_port,
1662 .release_port = lpuart_release_port,
1663 .config_port = lpuart_config_port,
1664 .verify_port = lpuart_verify_port,
bfc2e07f 1665 .flush_buffer = lpuart_flush_buffer,
2a41bc2a
NR		 1666#if defined(CONFIG_CONSOLE_POLL)
1667 .poll_init = lpuart_poll_init,
1668 .poll_get_char = lpuart_poll_get_char,
1669 .poll_put_char = lpuart_poll_put_char,
1670#endif
c9e2e946
JL		 1671};
1672
069a47e5 1673static const struct uart_ops lpuart32_pops = {
380c966c
JL		 1674 .tx_empty = lpuart32_tx_empty,
1675 .set_mctrl = lpuart32_set_mctrl,
1676 .get_mctrl = lpuart32_get_mctrl,
1677 .stop_tx = lpuart32_stop_tx,
1678 .start_tx = lpuart32_start_tx,
1679 .stop_rx = lpuart32_stop_rx,
1680 .break_ctl = lpuart32_break_ctl,
1681 .startup = lpuart32_startup,
1682 .shutdown = lpuart32_shutdown,
1683 .set_termios = lpuart32_set_termios,
1684 .type = lpuart_type,
1685 .request_port = lpuart_request_port,
1686 .release_port = lpuart_release_port,
1687 .config_port = lpuart_config_port,
1688 .verify_port = lpuart_verify_port,
bfc2e07f 1689 .flush_buffer = lpuart_flush_buffer,
380c966c
JL		 1690};
1691
c9e2e946
JL		 1692static struct lpuart_port *lpuart_ports[UART_NR];
1693
1694#ifdef CONFIG_SERIAL_FSL_LPUART_CONSOLE
1695static void lpuart_console_putchar(struct uart_port *port, int ch)
1696{
1697 while (!(readb(port->membase + UARTSR1) & UARTSR1_TDRE))
1698 barrier();
1699
1700 writeb(ch, port->membase + UARTDR);
1701}
1702
380c966c
JL		 1703static void lpuart32_console_putchar(struct uart_port *port, int ch)
1704{
a0204f25 1705 while (!(lpuart32_read(port, UARTSTAT) & UARTSTAT_TDRE))
380c966c
JL		 1706 barrier();
1707
a0204f25 1708 lpuart32_write(port, ch, UARTDATA);
380c966c
JL		 1709}
1710
c9e2e946
JL		 1711static void
1712lpuart_console_write(struct console *co, const char *s, unsigned int count)
1713{
1714 struct lpuart_port *sport = lpuart_ports[co->index];
1715 unsigned char old_cr2, cr2;
abf1e0a9
SA		 1716 unsigned long flags;
1717 int locked = 1;
1718
1719 if (sport->port.sysrq || oops_in_progress)
1720 locked = spin_trylock_irqsave(&sport->port.lock, flags);
1721 else
1722 spin_lock_irqsave(&sport->port.lock, flags);
c9e2e946
JL		 1723
1724 /* first save CR2 and then disable interrupts */
1725 cr2 = old_cr2 = readb(sport->port.membase + UARTCR2);
1726 cr2 |= (UARTCR2_TE | UARTCR2_RE);
1727 cr2 &= ~(UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_RIE);
1728 writeb(cr2, sport->port.membase + UARTCR2);
1729
1730 uart_console_write(&sport->port, s, count, lpuart_console_putchar);
1731
1732 /* wait for transmitter finish complete and restore CR2 */
1733 while (!(readb(sport->port.membase + UARTSR1) & UARTSR1_TC))
1734 barrier();
1735
1736 writeb(old_cr2, sport->port.membase + UARTCR2);
abf1e0a9
SA		 1737
1738 if (locked)
1739 spin_unlock_irqrestore(&sport->port.lock, flags);
c9e2e946
JL		 1740}
1741
380c966c
JL		 1742static void
1743lpuart32_console_write(struct console *co, const char *s, unsigned int count)
1744{
1745 struct lpuart_port *sport = lpuart_ports[co->index];
1746 unsigned long old_cr, cr;
abf1e0a9
SA		 1747 unsigned long flags;
1748 int locked = 1;
1749
1750 if (sport->port.sysrq || oops_in_progress)
1751 locked = spin_trylock_irqsave(&sport->port.lock, flags);
1752 else
1753 spin_lock_irqsave(&sport->port.lock, flags);
380c966c
JL		 1754
1755 /* first save CR2 and then disable interrupts */
a0204f25 1756 cr = old_cr = lpuart32_read(&sport->port, UARTCTRL);
380c966c
JL		 1757 cr |= (UARTCTRL_TE | UARTCTRL_RE);
1758 cr &= ~(UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_RIE);
a0204f25 1759 lpuart32_write(&sport->port, cr, UARTCTRL);
380c966c
JL		 1760
1761 uart_console_write(&sport->port, s, count, lpuart32_console_putchar);
1762
1763 /* wait for transmitter finish complete and restore CR2 */
a0204f25 1764 while (!(lpuart32_read(&sport->port, UARTSTAT) & UARTSTAT_TC))
380c966c
JL		 1765 barrier();
1766
a0204f25 1767 lpuart32_write(&sport->port, old_cr, UARTCTRL);
abf1e0a9
SA		 1768
1769 if (locked)
1770 spin_unlock_irqrestore(&sport->port.lock, flags);
380c966c
JL		 1771}
1772
c9e2e946
JL		 1773/*
1774 * if the port was already initialised (eg, by a boot loader),
1775 * try to determine the current setup.
1776 */
1777static void __init
1778lpuart_console_get_options(struct lpuart_port *sport, int *baud,
1779 int *parity, int *bits)
1780{
1781 unsigned char cr, bdh, bdl, brfa;
1782 unsigned int sbr, uartclk, baud_raw;
1783
1784 cr = readb(sport->port.membase + UARTCR2);
1785 cr &= UARTCR2_TE | UARTCR2_RE;
1786 if (!cr)
1787 return;
1788
1789 /* ok, the port was enabled */
1790
1791 cr = readb(sport->port.membase + UARTCR1);
1792
1793 *parity = 'n';
1794 if (cr & UARTCR1_PE) {
1795 if (cr & UARTCR1_PT)
1796 *parity = 'o';
1797 else
1798 *parity = 'e';
1799 }
1800
1801 if (cr & UARTCR1_M)
1802 *bits = 9;
1803 else
1804 *bits = 8;
1805
1806 bdh = readb(sport->port.membase + UARTBDH);
1807 bdh &= UARTBDH_SBR_MASK;
1808 bdl = readb(sport->port.membase + UARTBDL);
1809 sbr = bdh;
1810 sbr <<= 8;
1811 sbr |= bdl;
1812 brfa = readb(sport->port.membase + UARTCR4);
1813 brfa &= UARTCR4_BRFA_MASK;
1814
1815 uartclk = clk_get_rate(sport->clk);
1816 /*
1817 * baud = mod_clk/(16*(sbr[13]+(brfa)/32)
1818 */
1819 baud_raw = uartclk / (16 * (sbr + brfa / 32));
1820
1821 if (*baud != baud_raw)
1822 printk(KERN_INFO "Serial: Console lpuart rounded baud rate"
1823 "from %d to %d\n", baud_raw, *baud);
1824}
1825
380c966c
JL		 1826static void __init
1827lpuart32_console_get_options(struct lpuart_port *sport, int *baud,
1828 int *parity, int *bits)
1829{
1830 unsigned long cr, bd;
1831 unsigned int sbr, uartclk, baud_raw;
1832
a0204f25 1833 cr = lpuart32_read(&sport->port, UARTCTRL);
380c966c
JL		 1834 cr &= UARTCTRL_TE | UARTCTRL_RE;
1835 if (!cr)
1836 return;
1837
1838 /* ok, the port was enabled */
1839
a0204f25 1840 cr = lpuart32_read(&sport->port, UARTCTRL);
380c966c
JL		 1841
1842 *parity = 'n';
1843 if (cr & UARTCTRL_PE) {
1844 if (cr & UARTCTRL_PT)
1845 *parity = 'o';
1846 else
1847 *parity = 'e';
1848 }
1849
1850 if (cr & UARTCTRL_M)
1851 *bits = 9;
1852 else
1853 *bits = 8;
1854
a0204f25 1855 bd = lpuart32_read(&sport->port, UARTBAUD);
380c966c
JL		 1856 bd &= UARTBAUD_SBR_MASK;
1857 sbr = bd;
1858 uartclk = clk_get_rate(sport->clk);
1859 /*
1860 * baud = mod_clk/(16*(sbr[13]+(brfa)/32)
1861 */
1862 baud_raw = uartclk / (16 * sbr);
1863
1864 if (*baud != baud_raw)
1865 printk(KERN_INFO "Serial: Console lpuart rounded baud rate"
1866 "from %d to %d\n", baud_raw, *baud);
1867}
1868
c9e2e946
JL		 1869static int __init lpuart_console_setup(struct console *co, char *options)
1870{
1871 struct lpuart_port *sport;
1872 int baud = 115200;
1873 int bits = 8;
1874 int parity = 'n';
1875 int flow = 'n';
1876
1877 /*
1878 * check whether an invalid uart number has been specified, and
1879 * if so, search for the first available port that does have
1880 * console support.
1881 */
1882 if (co->index == -1 || co->index >= ARRAY_SIZE(lpuart_ports))
1883 co->index = 0;
1884
1885 sport = lpuart_ports[co->index];
1886 if (sport == NULL)
1887 return -ENODEV;
1888
1889 if (options)
1890 uart_parse_options(options, &baud, &parity, &bits, &flow);
1891 else
0d6fce90 1892 if (sport->port.iotype & UPIO_MEM32BE)
380c966c
JL		 1893 lpuart32_console_get_options(sport, &baud, &parity, &bits);
1894 else
1895 lpuart_console_get_options(sport, &baud, &parity, &bits);
c9e2e946 1896
0d6fce90 1897 if (sport->port.iotype & UPIO_MEM32BE)
380c966c
JL		 1898 lpuart32_setup_watermark(sport);
1899 else
1900 lpuart_setup_watermark(sport);
c9e2e946
JL		 1901
1902 return uart_set_options(&sport->port, co, baud, parity, bits, flow);
1903}
1904
1905static struct uart_driver lpuart_reg;
1906static struct console lpuart_console = {
1907 .name = DEV_NAME,
1908 .write = lpuart_console_write,
1909 .device = uart_console_device,
1910 .setup = lpuart_console_setup,
1911 .flags = CON_PRINTBUFFER,
1912 .index = -1,
1913 .data = &lpuart_reg,
1914};
1915
380c966c
JL		 1916static struct console lpuart32_console = {
1917 .name = DEV_NAME,
1918 .write = lpuart32_console_write,
1919 .device = uart_console_device,
1920 .setup = lpuart_console_setup,
1921 .flags = CON_PRINTBUFFER,
1922 .index = -1,
1923 .data = &lpuart_reg,
1924};
1925
1d59b382
SA		 1926static void lpuart_early_write(struct console *con, const char *s, unsigned n)
1927{
1928 struct earlycon_device *dev = con->data;
1929
1930 uart_console_write(&dev->port, s, n, lpuart_console_putchar);
1931}
1932
1933static void lpuart32_early_write(struct console *con, const char *s, unsigned n)
1934{
1935 struct earlycon_device *dev = con->data;
1936
1937 uart_console_write(&dev->port, s, n, lpuart32_console_putchar);
1938}
1939
1940static int __init lpuart_early_console_setup(struct earlycon_device *device,
1941 const char *opt)
1942{
1943 if (!device->port.membase)
1944 return -ENODEV;
1945
1946 device->con->write = lpuart_early_write;
1947 return 0;
1948}
1949
1950static int __init lpuart32_early_console_setup(struct earlycon_device *device,
1951 const char *opt)
1952{
1953 if (!device->port.membase)
1954 return -ENODEV;
1955
1956 device->con->write = lpuart32_early_write;
1957 return 0;
1958}
1959
1960OF_EARLYCON_DECLARE(lpuart, "fsl,vf610-lpuart", lpuart_early_console_setup);
1961OF_EARLYCON_DECLARE(lpuart32, "fsl,ls1021a-lpuart", lpuart32_early_console_setup);
1962EARLYCON_DECLARE(lpuart, lpuart_early_console_setup);
1963EARLYCON_DECLARE(lpuart32, lpuart32_early_console_setup);
1964
c9e2e946 1965#define LPUART_CONSOLE (&lpuart_console)
380c966c 1966#define LPUART32_CONSOLE (&lpuart32_console)
c9e2e946
JL		 1967#else
1968#define LPUART_CONSOLE NULL
380c966c 1969#define LPUART32_CONSOLE NULL
c9e2e946
JL		 1970#endif
1971
1972static struct uart_driver lpuart_reg = {
1973 .owner = THIS_MODULE,
1974 .driver_name = DRIVER_NAME,
1975 .dev_name = DEV_NAME,
1976 .nr = ARRAY_SIZE(lpuart_ports),
1977 .cons = LPUART_CONSOLE,
1978};
1979
1980static int lpuart_probe(struct platform_device *pdev)
1981{
0d6fce90
DA		 1982 const struct of_device_id *of_id = of_match_device(lpuart_dt_ids,
1983 &pdev->dev);
1984 const struct lpuart_soc_data *sdata = of_id->data;
c9e2e946
JL		 1985 struct device_node *np = pdev->dev.of_node;
1986 struct lpuart_port *sport;
1987 struct resource *res;
1988 int ret;
1989
1990 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);
1991 if (!sport)
1992 return -ENOMEM;
1993
1994 pdev->dev.coherent_dma_mask = 0;
1995
1996 ret = of_alias_get_id(np, "serial");
1997 if (ret < 0) {
1998 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret);
1999 return ret;
2000 }
2001 sport->port.line = ret;
4ae612a3 2002 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
c9e2e946
JL		 2003 sport->port.membase = devm_ioremap_resource(&pdev->dev, res);
2004 if (IS_ERR(sport->port.membase))
2005 return PTR_ERR(sport->port.membase);
2006
4ae612a3 2007 sport->port.mapbase = res->start;
c9e2e946
JL		 2008 sport->port.dev = &pdev->dev;
2009 sport->port.type = PORT_LPUART;
394a9e2c
JS		 2010 ret = platform_get_irq(pdev, 0);
2011 if (ret < 0) {
2012 dev_err(&pdev->dev, "cannot obtain irq\n");
2013 return ret;
2014 }
2015 sport->port.irq = ret;
0d6fce90
DA		 2016 sport->port.iotype = sdata->iotype;
2017 if (sport->port.iotype & UPIO_MEM32BE)
380c966c
JL		 2018 sport->port.ops = &lpuart32_pops;
2019 else
2020 sport->port.ops = &lpuart_pops;
c9e2e946
JL		 2021 sport->port.flags = UPF_BOOT_AUTOCONF;
2022
03895cf4
BD		 2023 sport->port.rs485_config = lpuart_config_rs485;
2024
c9e2e946
JL		 2025 sport->clk = devm_clk_get(&pdev->dev, "ipg");
2026 if (IS_ERR(sport->clk)) {
2027 ret = PTR_ERR(sport->clk);
2028 dev_err(&pdev->dev, "failed to get uart clk: %d\n", ret);
2029 return ret;
2030 }
2031
2032 ret = clk_prepare_enable(sport->clk);
2033 if (ret) {
2034 dev_err(&pdev->dev, "failed to enable uart clk: %d\n", ret);
2035 return ret;
2036 }
2037
2038 sport->port.uartclk = clk_get_rate(sport->clk);
2039
2040 lpuart_ports[sport->port.line] = sport;
2041
2042 platform_set_drvdata(pdev, &sport->port);
2043
0d6fce90 2044 if (sport->port.iotype & UPIO_MEM32BE)
380c966c
JL		 2045 lpuart_reg.cons = LPUART32_CONSOLE;
2046 else
2047 lpuart_reg.cons = LPUART_CONSOLE;
2048
c9e2e946
JL		 2049 ret = uart_add_one_port(&lpuart_reg, &sport->port);
2050 if (ret) {
2051 clk_disable_unprepare(sport->clk);
2052 return ret;
2053 }
2054
4a818c43
SA		 2055 sport->dma_tx_chan = dma_request_slave_channel(sport->port.dev, "tx");
2056 if (!sport->dma_tx_chan)
2057 dev_info(sport->port.dev, "DMA tx channel request failed, "
2058 "operating without tx DMA\n");
2059
2060 sport->dma_rx_chan = dma_request_slave_channel(sport->port.dev, "rx");
2061 if (!sport->dma_rx_chan)
2062 dev_info(sport->port.dev, "DMA rx channel request failed, "
2063 "operating without rx DMA\n");
2064
03895cf4
BD		 2065 if (of_property_read_bool(np, "linux,rs485-enabled-at-boot-time")) {
2066 sport->port.rs485.flags |= SER_RS485_ENABLED;
2067 sport->port.rs485.flags |= SER_RS485_RTS_ON_SEND;
2068 writeb(UARTMODEM_TXRTSE, sport->port.membase + UARTMODEM);
2069 }
2070
c9e2e946
JL		 2071 return 0;
2072}
2073
2074static int lpuart_remove(struct platform_device *pdev)
2075{
2076 struct lpuart_port *sport = platform_get_drvdata(pdev);
2077
2078 uart_remove_one_port(&lpuart_reg, &sport->port);
2079
2080 clk_disable_unprepare(sport->clk);
2081
4a818c43
SA		 2082 if (sport->dma_tx_chan)
2083 dma_release_channel(sport->dma_tx_chan);
2084
2085 if (sport->dma_rx_chan)
2086 dma_release_channel(sport->dma_rx_chan);
2087
c9e2e946
JL		 2088 return 0;
2089}
2090
2091#ifdef CONFIG_PM_SLEEP
2092static int lpuart_suspend(struct device *dev)
2093{
2094 struct lpuart_port *sport = dev_get_drvdata(dev);
2fe605df
YY		 2095 unsigned long temp;
2096
0d6fce90 2097 if (sport->port.iotype & UPIO_MEM32BE) {
2fe605df 2098 /* disable Rx/Tx and interrupts */
a0204f25 2099 temp = lpuart32_read(&sport->port, UARTCTRL);
2fe605df 2100 temp &= ~(UARTCTRL_TE | UARTCTRL_TIE | UARTCTRL_TCIE);
a0204f25 2101 lpuart32_write(&sport->port, temp, UARTCTRL);
2fe605df
YY		 2102 } else {
2103 /* disable Rx/Tx and interrupts */
2104 temp = readb(sport->port.membase + UARTCR2);
2105 temp &= ~(UARTCR2_TE | UARTCR2_TIE | UARTCR2_TCIE);
2106 writeb(temp, sport->port.membase + UARTCR2);
2107 }
c9e2e946
JL		 2108
2109 uart_suspend_port(&lpuart_reg, &sport->port);
c05efd69
BD		 2110
2111 if (sport->lpuart_dma_rx_use) {
2112 /*
2113 * EDMA driver during suspend will forcefully release any
2114 * non-idle DMA channels. If port wakeup is enabled or if port
2115 * is console port or 'no_console_suspend' is set the Rx DMA
2116 * cannot resume as as expected, hence gracefully release the
2117 * Rx DMA path before suspend and start Rx DMA path on resume.
2118 */
2119 if (sport->port.irq_wake) {
2120 del_timer_sync(&sport->lpuart_timer);
2121 lpuart_dma_rx_free(&sport->port);
2122 }
2123
2124 /* Disable Rx DMA to use UART port as wakeup source */
2125 writeb(readb(sport->port.membase + UARTCR5) & ~UARTCR5_RDMAS,
2126 sport->port.membase + UARTCR5);
2127 }
2128
2129 if (sport->lpuart_dma_tx_use) {
2130 sport->dma_tx_in_progress = false;
2131 dmaengine_terminate_all(sport->dma_tx_chan);
2132 }
2133
d6b0d2f2
SA		 2134 if (sport->port.suspended && !sport->port.irq_wake)
2135 clk_disable_unprepare(sport->clk);
c9e2e946
JL		 2136
2137 return 0;
2138}
2139
2140static int lpuart_resume(struct device *dev)
2141{
2142 struct lpuart_port *sport = dev_get_drvdata(dev);
08de1014
JL		 2143 unsigned long temp;
2144
d6b0d2f2
SA		 2145 if (sport->port.suspended && !sport->port.irq_wake)
2146 clk_prepare_enable(sport->clk);
2147
0d6fce90 2148 if (sport->port.iotype & UPIO_MEM32BE) {
08de1014 2149 lpuart32_setup_watermark(sport);
a0204f25 2150 temp = lpuart32_read(&sport->port, UARTCTRL);
08de1014
JL		 2151 temp |= (UARTCTRL_RIE | UARTCTRL_TIE | UARTCTRL_RE |
2152 UARTCTRL_TE | UARTCTRL_ILIE);
a0204f25 2153 lpuart32_write(&sport->port, temp, UARTCTRL);
08de1014
JL		 2154 } else {
2155 lpuart_setup_watermark(sport);
2156 temp = readb(sport->port.membase + UARTCR2);
2157 temp |= (UARTCR2_RIE | UARTCR2_TIE | UARTCR2_RE | UARTCR2_TE);
2158 writeb(temp, sport->port.membase + UARTCR2);
2159 }
c9e2e946 2160
c05efd69
BD		 2161 if (sport->lpuart_dma_rx_use) {
2162 if (sport->port.irq_wake) {
54a44d54 2163 if (!lpuart_start_rx_dma(sport))
c05efd69 2164 rx_dma_timer_init(sport);
54a44d54 2165 else
c05efd69 2166 sport->lpuart_dma_rx_use = false;
c05efd69
BD		 2167 }
2168 }
2169
2170 if (sport->dma_tx_chan && !lpuart_dma_tx_request(&sport->port)) {
2171 init_waitqueue_head(&sport->dma_wait);
2172 sport->lpuart_dma_tx_use = true;
2173 writeb(readb(sport->port.membase + UARTCR5) |
2174 UARTCR5_TDMAS, sport->port.membase + UARTCR5);
2175 } else {
2176 sport->lpuart_dma_tx_use = false;
2177 }
2178
c9e2e946
JL		 2179 uart_resume_port(&lpuart_reg, &sport->port);
2180
2181 return 0;
2182}
2183#endif
2184
2185static SIMPLE_DEV_PM_OPS(lpuart_pm_ops, lpuart_suspend, lpuart_resume);
2186
2187static struct platform_driver lpuart_driver = {
2188 .probe = lpuart_probe,
2189 .remove = lpuart_remove,
2190 .driver = {
2191 .name = "fsl-lpuart",
c9e2e946
JL		 2192 .of_match_table = lpuart_dt_ids,
2193 .pm = &lpuart_pm_ops,
2194 },
2195};
2196
2197static int __init lpuart_serial_init(void)
2198{
144c29ed 2199 int ret = uart_register_driver(&lpuart_reg);
c9e2e946 2200
c9e2e946
JL		 2201 if (ret)
2202 return ret;
2203
2204 ret = platform_driver_register(&lpuart_driver);
2205 if (ret)
2206 uart_unregister_driver(&lpuart_reg);
2207
39c34b09 2208 return ret;
c9e2e946
JL		 2209}
2210
2211static void __exit lpuart_serial_exit(void)
2212{
2213 platform_driver_unregister(&lpuart_driver);
2214 uart_unregister_driver(&lpuart_reg);
2215}
2216
2217module_init(lpuart_serial_init);
2218module_exit(lpuart_serial_exit);
2219
2220MODULE_DESCRIPTION("Freescale lpuart serial port driver");
2221MODULE_LICENSE("GPL v2");
Linux 6.x block layer and io_uring tree(s)