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tty: serial: fsl_lpuart: Use cyclic DMA for Rx
[linux-2.6-block.git] / drivers / tty / serial / fsl_lpuart.c
CommitLineData
c9e2e946
JL		 1/*
2 * Freescale lpuart serial port driver
3 *
380c966c 4 * Copyright 2012-2014 Freescale Semiconductor, Inc.
c9e2e946
JL		 5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 */
11
12#if defined(CONFIG_SERIAL_FSL_LPUART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
13#define SUPPORT_SYSRQ
14#endif
15
f1cd8c87
YY		 16#include <linux/clk.h>
17#include <linux/console.h>
18#include <linux/dma-mapping.h>
19#include <linux/dmaengine.h>
20#include <linux/dmapool.h>
c9e2e946
JL		 21#include <linux/io.h>
22#include <linux/irq.h>
f1cd8c87 23#include <linux/module.h>
c9e2e946
JL		 24#include <linux/of.h>
25#include <linux/of_device.h>
f1cd8c87 26#include <linux/of_dma.h>
c9e2e946 27#include <linux/serial_core.h>
f1cd8c87 28#include <linux/slab.h>
c9e2e946
JL		 29#include <linux/tty_flip.h>
30
31/* All registers are 8-bit width */
32#define UARTBDH 0x00
33#define UARTBDL 0x01
34#define UARTCR1 0x02
35#define UARTCR2 0x03
36#define UARTSR1 0x04
37#define UARTCR3 0x06
38#define UARTDR 0x07
39#define UARTCR4 0x0a
40#define UARTCR5 0x0b
41#define UARTMODEM 0x0d
42#define UARTPFIFO 0x10
43#define UARTCFIFO 0x11
44#define UARTSFIFO 0x12
45#define UARTTWFIFO 0x13
46#define UARTTCFIFO 0x14
47#define UARTRWFIFO 0x15
48
49#define UARTBDH_LBKDIE 0x80
50#define UARTBDH_RXEDGIE 0x40
51#define UARTBDH_SBR_MASK 0x1f
52
53#define UARTCR1_LOOPS 0x80
54#define UARTCR1_RSRC 0x20
55#define UARTCR1_M 0x10
56#define UARTCR1_WAKE 0x08
57#define UARTCR1_ILT 0x04
58#define UARTCR1_PE 0x02
59#define UARTCR1_PT 0x01
60
61#define UARTCR2_TIE 0x80
62#define UARTCR2_TCIE 0x40
63#define UARTCR2_RIE 0x20
64#define UARTCR2_ILIE 0x10
65#define UARTCR2_TE 0x08
66#define UARTCR2_RE 0x04
67#define UARTCR2_RWU 0x02
68#define UARTCR2_SBK 0x01
69
70#define UARTSR1_TDRE 0x80
71#define UARTSR1_TC 0x40
72#define UARTSR1_RDRF 0x20
73#define UARTSR1_IDLE 0x10
74#define UARTSR1_OR 0x08
75#define UARTSR1_NF 0x04
76#define UARTSR1_FE 0x02
77#define UARTSR1_PE 0x01
78
79#define UARTCR3_R8 0x80
80#define UARTCR3_T8 0x40
81#define UARTCR3_TXDIR 0x20
82#define UARTCR3_TXINV 0x10
83#define UARTCR3_ORIE 0x08
84#define UARTCR3_NEIE 0x04
85#define UARTCR3_FEIE 0x02
86#define UARTCR3_PEIE 0x01
87
88#define UARTCR4_MAEN1 0x80
89#define UARTCR4_MAEN2 0x40
90#define UARTCR4_M10 0x20
91#define UARTCR4_BRFA_MASK 0x1f
92#define UARTCR4_BRFA_OFF 0
93
94#define UARTCR5_TDMAS 0x80
95#define UARTCR5_RDMAS 0x20
96
97#define UARTMODEM_RXRTSE 0x08
98#define UARTMODEM_TXRTSPOL 0x04
99#define UARTMODEM_TXRTSE 0x02
100#define UARTMODEM_TXCTSE 0x01
101
102#define UARTPFIFO_TXFE 0x80
103#define UARTPFIFO_FIFOSIZE_MASK 0x7
104#define UARTPFIFO_TXSIZE_OFF 4
105#define UARTPFIFO_RXFE 0x08
106#define UARTPFIFO_RXSIZE_OFF 0
107
108#define UARTCFIFO_TXFLUSH 0x80
109#define UARTCFIFO_RXFLUSH 0x40
110#define UARTCFIFO_RXOFE 0x04
111#define UARTCFIFO_TXOFE 0x02
112#define UARTCFIFO_RXUFE 0x01
113
114#define UARTSFIFO_TXEMPT 0x80
115#define UARTSFIFO_RXEMPT 0x40
116#define UARTSFIFO_RXOF 0x04
117#define UARTSFIFO_TXOF 0x02
118#define UARTSFIFO_RXUF 0x01
119
380c966c
JL		 120/* 32-bit register defination */
121#define UARTBAUD 0x00
122#define UARTSTAT 0x04
123#define UARTCTRL 0x08
124#define UARTDATA 0x0C
125#define UARTMATCH 0x10
126#define UARTMODIR 0x14
127#define UARTFIFO 0x18
128#define UARTWATER 0x1c
129
130#define UARTBAUD_MAEN1 0x80000000
131#define UARTBAUD_MAEN2 0x40000000
132#define UARTBAUD_M10 0x20000000
133#define UARTBAUD_TDMAE 0x00800000
134#define UARTBAUD_RDMAE 0x00200000
135#define UARTBAUD_MATCFG 0x00400000
136#define UARTBAUD_BOTHEDGE 0x00020000
137#define UARTBAUD_RESYNCDIS 0x00010000
138#define UARTBAUD_LBKDIE 0x00008000
139#define UARTBAUD_RXEDGIE 0x00004000
140#define UARTBAUD_SBNS 0x00002000
141#define UARTBAUD_SBR 0x00000000
142#define UARTBAUD_SBR_MASK 0x1fff
143
144#define UARTSTAT_LBKDIF 0x80000000
145#define UARTSTAT_RXEDGIF 0x40000000
146#define UARTSTAT_MSBF 0x20000000
147#define UARTSTAT_RXINV 0x10000000
148#define UARTSTAT_RWUID 0x08000000
149#define UARTSTAT_BRK13 0x04000000
150#define UARTSTAT_LBKDE 0x02000000
151#define UARTSTAT_RAF 0x01000000
152#define UARTSTAT_TDRE 0x00800000
153#define UARTSTAT_TC 0x00400000
154#define UARTSTAT_RDRF 0x00200000
155#define UARTSTAT_IDLE 0x00100000
156#define UARTSTAT_OR 0x00080000
157#define UARTSTAT_NF 0x00040000
158#define UARTSTAT_FE 0x00020000
159#define UARTSTAT_PE 0x00010000
160#define UARTSTAT_MA1F 0x00008000
161#define UARTSTAT_M21F 0x00004000
162
163#define UARTCTRL_R8T9 0x80000000
164#define UARTCTRL_R9T8 0x40000000
165#define UARTCTRL_TXDIR 0x20000000
166#define UARTCTRL_TXINV 0x10000000
167#define UARTCTRL_ORIE 0x08000000
168#define UARTCTRL_NEIE 0x04000000
169#define UARTCTRL_FEIE 0x02000000
170#define UARTCTRL_PEIE 0x01000000
171#define UARTCTRL_TIE 0x00800000
172#define UARTCTRL_TCIE 0x00400000
173#define UARTCTRL_RIE 0x00200000
174#define UARTCTRL_ILIE 0x00100000
175#define UARTCTRL_TE 0x00080000
176#define UARTCTRL_RE 0x00040000
177#define UARTCTRL_RWU 0x00020000
178#define UARTCTRL_SBK 0x00010000
179#define UARTCTRL_MA1IE 0x00008000
180#define UARTCTRL_MA2IE 0x00004000
181#define UARTCTRL_IDLECFG 0x00000100
182#define UARTCTRL_LOOPS 0x00000080
183#define UARTCTRL_DOZEEN 0x00000040
184#define UARTCTRL_RSRC 0x00000020
185#define UARTCTRL_M 0x00000010
186#define UARTCTRL_WAKE 0x00000008
187#define UARTCTRL_ILT 0x00000004
188#define UARTCTRL_PE 0x00000002
189#define UARTCTRL_PT 0x00000001
190
191#define UARTDATA_NOISY 0x00008000
192#define UARTDATA_PARITYE 0x00004000
193#define UARTDATA_FRETSC 0x00002000
194#define UARTDATA_RXEMPT 0x00001000
195#define UARTDATA_IDLINE 0x00000800
196#define UARTDATA_MASK 0x3ff
197
198#define UARTMODIR_IREN 0x00020000
199#define UARTMODIR_TXCTSSRC 0x00000020
200#define UARTMODIR_TXCTSC 0x00000010
201#define UARTMODIR_RXRTSE 0x00000008
202#define UARTMODIR_TXRTSPOL 0x00000004
203#define UARTMODIR_TXRTSE 0x00000002
204#define UARTMODIR_TXCTSE 0x00000001
205
206#define UARTFIFO_TXEMPT 0x00800000
207#define UARTFIFO_RXEMPT 0x00400000
208#define UARTFIFO_TXOF 0x00020000
209#define UARTFIFO_RXUF 0x00010000
210#define UARTFIFO_TXFLUSH 0x00008000
211#define UARTFIFO_RXFLUSH 0x00004000
212#define UARTFIFO_TXOFE 0x00000200
213#define UARTFIFO_RXUFE 0x00000100
214#define UARTFIFO_TXFE 0x00000080
215#define UARTFIFO_FIFOSIZE_MASK 0x7
216#define UARTFIFO_TXSIZE_OFF 4
217#define UARTFIFO_RXFE 0x00000008
218#define UARTFIFO_RXSIZE_OFF 0
219
220#define UARTWATER_COUNT_MASK 0xff
221#define UARTWATER_TXCNT_OFF 8
222#define UARTWATER_RXCNT_OFF 24
223#define UARTWATER_WATER_MASK 0xff
224#define UARTWATER_TXWATER_OFF 0
225#define UARTWATER_RXWATER_OFF 16
226
5887ad43
BD		 227/* Rx DMA timeout in ms, which is used to calculate Rx ring buffer size */
228#define DMA_RX_TIMEOUT (10)
f1cd8c87 229
c9e2e946
JL		 230#define DRIVER_NAME "fsl-lpuart"
231#define DEV_NAME "ttyLP"
232#define UART_NR 6
233
234struct lpuart_port {
235 struct uart_port port;
236 struct clk *clk;
237 unsigned int txfifo_size;
238 unsigned int rxfifo_size;
380c966c 239 bool lpuart32;
f1cd8c87 240
4a818c43
SA		 241 bool lpuart_dma_tx_use;
242 bool lpuart_dma_rx_use;
f1cd8c87
YY		 243 struct dma_chan *dma_tx_chan;
244 struct dma_chan *dma_rx_chan;
245 struct dma_async_tx_descriptor *dma_tx_desc;
246 struct dma_async_tx_descriptor *dma_rx_desc;
247 dma_addr_t dma_tx_buf_bus;
f1cd8c87
YY		 248 dma_cookie_t dma_tx_cookie;
249 dma_cookie_t dma_rx_cookie;
250 unsigned char *dma_tx_buf_virt;
f1cd8c87
YY		 251 unsigned int dma_tx_bytes;
252 unsigned int dma_rx_bytes;
253 int dma_tx_in_progress;
f1cd8c87
YY		 254 unsigned int dma_rx_timeout;
255 struct timer_list lpuart_timer;
5887ad43
BD		 256 struct scatterlist rx_sgl;
257 struct circ_buf rx_ring;
258 int rx_dma_rng_buf_len;
c9e2e946
JL		 259};
260
ed0bb232 261static const struct of_device_id lpuart_dt_ids[] = {
c9e2e946
JL		 262 {
263 .compatible = "fsl,vf610-lpuart",
264 },
380c966c
JL		 265 {
266 .compatible = "fsl,ls1021a-lpuart",
267 },
c9e2e946
JL		 268 { /* sentinel */ }
269};
270MODULE_DEVICE_TABLE(of, lpuart_dt_ids);
271
f1cd8c87
YY		 272/* Forward declare this for the dma callbacks*/
273static void lpuart_dma_tx_complete(void *arg);
f1cd8c87 274
380c966c
JL		 275static u32 lpuart32_read(void __iomem *addr)
276{
277 return ioread32be(addr);
278}
279
280static void lpuart32_write(u32 val, void __iomem *addr)
281{
282 iowrite32be(val, addr);
283}
284
c9e2e946
JL		 285static void lpuart_stop_tx(struct uart_port *port)
286{
287 unsigned char temp;
288
289 temp = readb(port->membase + UARTCR2);
290 temp &= ~(UARTCR2_TIE | UARTCR2_TCIE);
291 writeb(temp, port->membase + UARTCR2);
292}
293
380c966c
JL		 294static void lpuart32_stop_tx(struct uart_port *port)
295{
296 unsigned long temp;
297
298 temp = lpuart32_read(port->membase + UARTCTRL);
299 temp &= ~(UARTCTRL_TIE | UARTCTRL_TCIE);
300 lpuart32_write(temp, port->membase + UARTCTRL);
301}
302
c9e2e946
JL		 303static void lpuart_stop_rx(struct uart_port *port)
304{
305 unsigned char temp;
306
307 temp = readb(port->membase + UARTCR2);
308 writeb(temp & ~UARTCR2_RE, port->membase + UARTCR2);
309}
310
380c966c
JL		 311static void lpuart32_stop_rx(struct uart_port *port)
312{
313 unsigned long temp;
314
315 temp = lpuart32_read(port->membase + UARTCTRL);
316 lpuart32_write(temp & ~UARTCTRL_RE, port->membase + UARTCTRL);
317}
318
f1cd8c87
YY		 319static void lpuart_pio_tx(struct lpuart_port *sport)
320{
321 struct circ_buf *xmit = &sport->port.state->xmit;
322 unsigned long flags;
323
324 spin_lock_irqsave(&sport->port.lock, flags);
325
326 while (!uart_circ_empty(xmit) &&
327 readb(sport->port.membase + UARTTCFIFO) < sport->txfifo_size) {
328 writeb(xmit->buf[xmit->tail], sport->port.membase + UARTDR);
329 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
330 sport->port.icount.tx++;
331 }
332
333 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
334 uart_write_wakeup(&sport->port);
335
336 if (uart_circ_empty(xmit))
337 writeb(readb(sport->port.membase + UARTCR5) | UARTCR5_TDMAS,
338 sport->port.membase + UARTCR5);
339
340 spin_unlock_irqrestore(&sport->port.lock, flags);
341}
342
343static int lpuart_dma_tx(struct lpuart_port *sport, unsigned long count)
344{
345 struct circ_buf *xmit = &sport->port.state->xmit;
346 dma_addr_t tx_bus_addr;
347
348 dma_sync_single_for_device(sport->port.dev, sport->dma_tx_buf_bus,
349 UART_XMIT_SIZE, DMA_TO_DEVICE);
ed9891bf 350 sport->dma_tx_bytes = count & ~(sport->txfifo_size - 1);
f1cd8c87
YY		 351 tx_bus_addr = sport->dma_tx_buf_bus + xmit->tail;
352 sport->dma_tx_desc = dmaengine_prep_slave_single(sport->dma_tx_chan,
353 tx_bus_addr, sport->dma_tx_bytes,
354 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
355
356 if (!sport->dma_tx_desc) {
357 dev_err(sport->port.dev, "Not able to get desc for tx\n");
358 return -EIO;
359 }
360
361 sport->dma_tx_desc->callback = lpuart_dma_tx_complete;
362 sport->dma_tx_desc->callback_param = sport;
363 sport->dma_tx_in_progress = 1;
364 sport->dma_tx_cookie = dmaengine_submit(sport->dma_tx_desc);
365 dma_async_issue_pending(sport->dma_tx_chan);
366
367 return 0;
368}
369
370static void lpuart_prepare_tx(struct lpuart_port *sport)
371{
372 struct circ_buf *xmit = &sport->port.state->xmit;
373 unsigned long count = CIRC_CNT_TO_END(xmit->head,
374 xmit->tail, UART_XMIT_SIZE);
375
376 if (!count)
377 return;
378
ed9891bf 379 if (count < sport->txfifo_size)
f1cd8c87
YY		 380 writeb(readb(sport->port.membase + UARTCR5) & ~UARTCR5_TDMAS,
381 sport->port.membase + UARTCR5);
382 else {
383 writeb(readb(sport->port.membase + UARTCR5) | UARTCR5_TDMAS,
384 sport->port.membase + UARTCR5);
385 lpuart_dma_tx(sport, count);
386 }
387}
388
389static void lpuart_dma_tx_complete(void *arg)
390{
391 struct lpuart_port *sport = arg;
392 struct circ_buf *xmit = &sport->port.state->xmit;
393 unsigned long flags;
394
395 async_tx_ack(sport->dma_tx_desc);
396
397 spin_lock_irqsave(&sport->port.lock, flags);
398
399 xmit->tail = (xmit->tail + sport->dma_tx_bytes) & (UART_XMIT_SIZE - 1);
400 sport->dma_tx_in_progress = 0;
401
402 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
403 uart_write_wakeup(&sport->port);
404
405 lpuart_prepare_tx(sport);
406
407 spin_unlock_irqrestore(&sport->port.lock, flags);
408}
409
bfc2e07f
SA		 410static void lpuart_flush_buffer(struct uart_port *port)
411{
412 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
413 if (sport->lpuart_dma_tx_use) {
414 dmaengine_terminate_all(sport->dma_tx_chan);
415 sport->dma_tx_in_progress = 0;
416 }
417}
418
c9e2e946
JL		 419static inline void lpuart_transmit_buffer(struct lpuart_port *sport)
420{
421 struct circ_buf *xmit = &sport->port.state->xmit;
422
423 while (!uart_circ_empty(xmit) &&
424 (readb(sport->port.membase + UARTTCFIFO) < sport->txfifo_size)) {
425 writeb(xmit->buf[xmit->tail], sport->port.membase + UARTDR);
426 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
427 sport->port.icount.tx++;
428 }
429
430 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
431 uart_write_wakeup(&sport->port);
432
433 if (uart_circ_empty(xmit))
434 lpuart_stop_tx(&sport->port);
435}
436
380c966c
JL		 437static inline void lpuart32_transmit_buffer(struct lpuart_port *sport)
438{
439 struct circ_buf *xmit = &sport->port.state->xmit;
440 unsigned long txcnt;
441
442 txcnt = lpuart32_read(sport->port.membase + UARTWATER);
443 txcnt = txcnt >> UARTWATER_TXCNT_OFF;
444 txcnt &= UARTWATER_COUNT_MASK;
445 while (!uart_circ_empty(xmit) && (txcnt < sport->txfifo_size)) {
446 lpuart32_write(xmit->buf[xmit->tail], sport->port.membase + UARTDATA);
447 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
448 sport->port.icount.tx++;
449 txcnt = lpuart32_read(sport->port.membase + UARTWATER);
450 txcnt = txcnt >> UARTWATER_TXCNT_OFF;
451 txcnt &= UARTWATER_COUNT_MASK;
452 }
453
454 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
455 uart_write_wakeup(&sport->port);
456
457 if (uart_circ_empty(xmit))
458 lpuart32_stop_tx(&sport->port);
459}
460
c9e2e946
JL		 461static void lpuart_start_tx(struct uart_port *port)
462{
f1cd8c87
YY		 463 struct lpuart_port *sport = container_of(port,
464 struct lpuart_port, port);
465 struct circ_buf *xmit = &sport->port.state->xmit;
c9e2e946
JL		 466 unsigned char temp;
467
468 temp = readb(port->membase + UARTCR2);
469 writeb(temp | UARTCR2_TIE, port->membase + UARTCR2);
470
4a818c43 471 if (sport->lpuart_dma_tx_use) {
f1cd8c87
YY		 472 if (!uart_circ_empty(xmit) && !sport->dma_tx_in_progress)
473 lpuart_prepare_tx(sport);
474 } else {
475 if (readb(port->membase + UARTSR1) & UARTSR1_TDRE)
476 lpuart_transmit_buffer(sport);
477 }
c9e2e946
JL		 478}
479
380c966c
JL		 480static void lpuart32_start_tx(struct uart_port *port)
481{
482 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
483 unsigned long temp;
484
485 temp = lpuart32_read(port->membase + UARTCTRL);
486 lpuart32_write(temp | UARTCTRL_TIE, port->membase + UARTCTRL);
487
488 if (lpuart32_read(port->membase + UARTSTAT) & UARTSTAT_TDRE)
489 lpuart32_transmit_buffer(sport);
490}
491
c9e2e946
JL		 492static irqreturn_t lpuart_txint(int irq, void *dev_id)
493{
494 struct lpuart_port *sport = dev_id;
495 struct circ_buf *xmit = &sport->port.state->xmit;
496 unsigned long flags;
497
498 spin_lock_irqsave(&sport->port.lock, flags);
499 if (sport->port.x_char) {
380c966c
JL		 500 if (sport->lpuart32)
501 lpuart32_write(sport->port.x_char, sport->port.membase + UARTDATA);
502 else
503 writeb(sport->port.x_char, sport->port.membase + UARTDR);
c9e2e946
JL		 504 goto out;
505 }
506
507 if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) {
380c966c
JL		 508 if (sport->lpuart32)
509 lpuart32_stop_tx(&sport->port);
510 else
511 lpuart_stop_tx(&sport->port);
c9e2e946
JL		 512 goto out;
513 }
514
380c966c
JL		 515 if (sport->lpuart32)
516 lpuart32_transmit_buffer(sport);
517 else
518 lpuart_transmit_buffer(sport);
c9e2e946
JL		 519
520 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
521 uart_write_wakeup(&sport->port);
522
523out:
524 spin_unlock_irqrestore(&sport->port.lock, flags);
525 return IRQ_HANDLED;
526}
527
528static irqreturn_t lpuart_rxint(int irq, void *dev_id)
529{
530 struct lpuart_port *sport = dev_id;
531 unsigned int flg, ignored = 0;
532 struct tty_port *port = &sport->port.state->port;
533 unsigned long flags;
534 unsigned char rx, sr;
535
536 spin_lock_irqsave(&sport->port.lock, flags);
537
538 while (!(readb(sport->port.membase + UARTSFIFO) & UARTSFIFO_RXEMPT)) {
539 flg = TTY_NORMAL;
540 sport->port.icount.rx++;
541 /*
542 * to clear the FE, OR, NF, FE, PE flags,
543 * read SR1 then read DR
544 */
545 sr = readb(sport->port.membase + UARTSR1);
546 rx = readb(sport->port.membase + UARTDR);
547
548 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx))
549 continue;
550
551 if (sr & (UARTSR1_PE | UARTSR1_OR | UARTSR1_FE)) {
552 if (sr & UARTSR1_PE)
553 sport->port.icount.parity++;
554 else if (sr & UARTSR1_FE)
555 sport->port.icount.frame++;
556
557 if (sr & UARTSR1_OR)
558 sport->port.icount.overrun++;
559
560 if (sr & sport->port.ignore_status_mask) {
561 if (++ignored > 100)
562 goto out;
563 continue;
564 }
565
566 sr &= sport->port.read_status_mask;
567
568 if (sr & UARTSR1_PE)
569 flg = TTY_PARITY;
570 else if (sr & UARTSR1_FE)
571 flg = TTY_FRAME;
572
573 if (sr & UARTSR1_OR)
574 flg = TTY_OVERRUN;
575
576#ifdef SUPPORT_SYSRQ
577 sport->port.sysrq = 0;
578#endif
579 }
580
581 tty_insert_flip_char(port, rx, flg);
582 }
583
584out:
585 spin_unlock_irqrestore(&sport->port.lock, flags);
586
587 tty_flip_buffer_push(port);
588 return IRQ_HANDLED;
589}
590
380c966c
JL		 591static irqreturn_t lpuart32_rxint(int irq, void *dev_id)
592{
593 struct lpuart_port *sport = dev_id;
594 unsigned int flg, ignored = 0;
595 struct tty_port *port = &sport->port.state->port;
596 unsigned long flags;
597 unsigned long rx, sr;
598
599 spin_lock_irqsave(&sport->port.lock, flags);
600
601 while (!(lpuart32_read(sport->port.membase + UARTFIFO) & UARTFIFO_RXEMPT)) {
602 flg = TTY_NORMAL;
603 sport->port.icount.rx++;
604 /*
605 * to clear the FE, OR, NF, FE, PE flags,
606 * read STAT then read DATA reg
607 */
608 sr = lpuart32_read(sport->port.membase + UARTSTAT);
609 rx = lpuart32_read(sport->port.membase + UARTDATA);
610 rx &= 0x3ff;
611
612 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx))
613 continue;
614
615 if (sr & (UARTSTAT_PE | UARTSTAT_OR | UARTSTAT_FE)) {
616 if (sr & UARTSTAT_PE)
617 sport->port.icount.parity++;
618 else if (sr & UARTSTAT_FE)
619 sport->port.icount.frame++;
620
621 if (sr & UARTSTAT_OR)
622 sport->port.icount.overrun++;
623
624 if (sr & sport->port.ignore_status_mask) {
625 if (++ignored > 100)
626 goto out;
627 continue;
628 }
629
630 sr &= sport->port.read_status_mask;
631
632 if (sr & UARTSTAT_PE)
633 flg = TTY_PARITY;
634 else if (sr & UARTSTAT_FE)
635 flg = TTY_FRAME;
636
637 if (sr & UARTSTAT_OR)
638 flg = TTY_OVERRUN;
639
640#ifdef SUPPORT_SYSRQ
641 sport->port.sysrq = 0;
642#endif
643 }
644
645 tty_insert_flip_char(port, rx, flg);
646 }
647
648out:
649 spin_unlock_irqrestore(&sport->port.lock, flags);
650
651 tty_flip_buffer_push(port);
652 return IRQ_HANDLED;
653}
654
c9e2e946
JL		 655static irqreturn_t lpuart_int(int irq, void *dev_id)
656{
657 struct lpuart_port *sport = dev_id;
5887ad43 658 unsigned char sts;
c9e2e946
JL		 659
660 sts = readb(sport->port.membase + UARTSR1);
661
5887ad43
BD		 662 if (sts & UARTSR1_RDRF)
663 lpuart_rxint(irq, dev_id);
664
665 if (sts & UARTSR1_TDRE) {
4a818c43 666 if (sport->lpuart_dma_tx_use)
f1cd8c87
YY		 667 lpuart_pio_tx(sport);
668 else
669 lpuart_txint(irq, dev_id);
670 }
c9e2e946
JL		 671
672 return IRQ_HANDLED;
673}
674
380c966c
JL		 675static irqreturn_t lpuart32_int(int irq, void *dev_id)
676{
677 struct lpuart_port *sport = dev_id;
678 unsigned long sts, rxcount;
679
680 sts = lpuart32_read(sport->port.membase + UARTSTAT);
681 rxcount = lpuart32_read(sport->port.membase + UARTWATER);
682 rxcount = rxcount >> UARTWATER_RXCNT_OFF;
683
684 if (sts & UARTSTAT_RDRF || rxcount > 0)
685 lpuart32_rxint(irq, dev_id);
686
687 if ((sts & UARTSTAT_TDRE) &&
688 !(lpuart32_read(sport->port.membase + UARTBAUD) & UARTBAUD_TDMAE))
689 lpuart_txint(irq, dev_id);
690
691 lpuart32_write(sts, sport->port.membase + UARTSTAT);
692 return IRQ_HANDLED;
693}
694
c9e2e946
JL		 695/* return TIOCSER_TEMT when transmitter is not busy */
696static unsigned int lpuart_tx_empty(struct uart_port *port)
697{
b70b6361
SA		 698 struct lpuart_port *sport = container_of(port,
699 struct lpuart_port, port);
700 unsigned char sr1 = readb(port->membase + UARTSR1);
701 unsigned char sfifo = readb(port->membase + UARTSFIFO);
702
703 if (sport->dma_tx_in_progress)
704 return 0;
705
706 if (sr1 & UARTSR1_TC && sfifo & UARTSFIFO_TXEMPT)
707 return TIOCSER_TEMT;
708
709 return 0;
c9e2e946
JL		 710}
711
380c966c
JL		 712static unsigned int lpuart32_tx_empty(struct uart_port *port)
713{
714 return (lpuart32_read(port->membase + UARTSTAT) & UARTSTAT_TC) ?
715 TIOCSER_TEMT : 0;
716}
717
5887ad43
BD		 718static void lpuart_copy_rx_to_tty(struct lpuart_port *sport)
719{
720 struct tty_port *port = &sport->port.state->port;
721 struct dma_tx_state state;
722 enum dma_status dmastat;
723 struct circ_buf *ring = &sport->rx_ring;
724 unsigned long flags;
725 int count = 0;
726 unsigned char sr;
727
728 sr = readb(sport->port.membase + UARTSR1);
729
730 if (sr & (UARTSR1_PE | UARTSR1_FE)) {
731 /* Read DR to clear the error flags */
732 readb(sport->port.membase + UARTDR);
733
734 if (sr & UARTSR1_PE)
735 sport->port.icount.parity++;
736 else if (sr & UARTSR1_FE)
737 sport->port.icount.frame++;
738 }
739
740 async_tx_ack(sport->dma_rx_desc);
741
742 spin_lock_irqsave(&sport->port.lock, flags);
743
744 dmastat = dmaengine_tx_status(sport->dma_rx_chan,
745 sport->dma_rx_cookie,
746 &state);
747
748 if (dmastat == DMA_ERROR) {
749 dev_err(sport->port.dev, "Rx DMA transfer failed!\n");
750 spin_unlock_irqrestore(&sport->port.lock, flags);
751 return;
752 }
753
754 /* CPU claims ownership of RX DMA buffer */
755 dma_sync_sg_for_cpu(sport->port.dev, &sport->rx_sgl, 1, DMA_FROM_DEVICE);
756
757 /*
758 * ring->head points to the end of data already written by the DMA.
759 * ring->tail points to the beginning of data to be read by the
760 * framework.
761 * The current transfer size should not be larger than the dma buffer
762 * length.
763 */
764 ring->head = sport->rx_sgl.length - state.residue;
765 BUG_ON(ring->head > sport->rx_sgl.length);
766 /*
767 * At this point ring->head may point to the first byte right after the
768 * last byte of the dma buffer:
769 * 0 <= ring->head <= sport->rx_sgl.length
770 *
771 * However ring->tail must always points inside the dma buffer:
772 * 0 <= ring->tail <= sport->rx_sgl.length - 1
773 *
774 * Since we use a ring buffer, we have to handle the case
775 * where head is lower than tail. In such a case, we first read from
776 * tail to the end of the buffer then reset tail.
777 */
778 if (ring->head < ring->tail) {
779 count = sport->rx_sgl.length - ring->tail;
780
781 tty_insert_flip_string(port, ring->buf + ring->tail, count);
782 ring->tail = 0;
783 sport->port.icount.rx += count;
784 }
785
786 /* Finally we read data from tail to head */
787 if (ring->tail < ring->head) {
788 count = ring->head - ring->tail;
789 tty_insert_flip_string(port, ring->buf + ring->tail, count);
790 /* Wrap ring->head if needed */
791 if (ring->head >= sport->rx_sgl.length)
792 ring->head = 0;
793 ring->tail = ring->head;
794 sport->port.icount.rx += count;
795 }
796
797 dma_sync_sg_for_device(sport->port.dev, &sport->rx_sgl, 1,
798 DMA_FROM_DEVICE);
799
800 spin_unlock_irqrestore(&sport->port.lock, flags);
801
802 tty_flip_buffer_push(port);
803 mod_timer(&sport->lpuart_timer, jiffies + sport->dma_rx_timeout);
804}
805
806static void lpuart_dma_rx_complete(void *arg)
807{
808 struct lpuart_port *sport = arg;
809
810 lpuart_copy_rx_to_tty(sport);
811}
812
813static void lpuart_timer_func(unsigned long data)
814{
815 struct lpuart_port *sport = (struct lpuart_port *)data;
816
817 lpuart_copy_rx_to_tty(sport);
818}
819
820static inline int lpuart_start_rx_dma(struct lpuart_port *sport)
821{
822 struct dma_slave_config dma_rx_sconfig = {};
823 struct circ_buf *ring = &sport->rx_ring;
824 int ret, nent;
825 int bits, baud;
826 struct tty_struct *tty = tty_port_tty_get(&sport->port.state->port);
827 struct ktermios *termios = &tty->termios;
828
829 baud = tty_get_baud_rate(tty);
830
831 bits = (termios->c_cflag & CSIZE) == CS7 ? 9 : 10;
832 if (termios->c_cflag & PARENB)
833 bits++;
834
835 /*
836 * Calculate length of one DMA buffer size to keep latency below
837 * 10ms at any baud rate.
838 */
839 sport->rx_dma_rng_buf_len = (DMA_RX_TIMEOUT * baud / bits / 1000) * 2;
840 sport->rx_dma_rng_buf_len = (1 << (fls(sport->rx_dma_rng_buf_len) - 1));
841 if (sport->rx_dma_rng_buf_len < 16)
842 sport->rx_dma_rng_buf_len = 16;
843
844 ring->buf = kmalloc(sport->rx_dma_rng_buf_len, GFP_KERNEL);
845 if (!ring->buf) {
846 dev_err(sport->port.dev, "Ring buf alloc failed\n");
847 return -ENOMEM;
848 }
849
850 sg_init_one(&sport->rx_sgl, ring->buf, sport->rx_dma_rng_buf_len);
851 sg_set_buf(&sport->rx_sgl, ring->buf, sport->rx_dma_rng_buf_len);
852 nent = dma_map_sg(sport->port.dev, &sport->rx_sgl, 1, DMA_FROM_DEVICE);
853
854 if (!nent) {
855 dev_err(sport->port.dev, "DMA Rx mapping error\n");
856 return -EINVAL;
857 }
858
859 dma_rx_sconfig.src_addr = sport->port.mapbase + UARTDR;
860 dma_rx_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
861 dma_rx_sconfig.src_maxburst = 1;
862 dma_rx_sconfig.direction = DMA_DEV_TO_MEM;
863 ret = dmaengine_slave_config(sport->dma_rx_chan, &dma_rx_sconfig);
864
865 if (ret < 0) {
866 dev_err(sport->port.dev,
867 "DMA Rx slave config failed, err = %d\n", ret);
868 return ret;
869 }
870
871 sport->dma_rx_desc = dmaengine_prep_dma_cyclic(sport->dma_rx_chan,
872 sg_dma_address(&sport->rx_sgl),
873 sport->rx_sgl.length,
874 sport->rx_sgl.length / 2,
875 DMA_DEV_TO_MEM,
876 DMA_PREP_INTERRUPT);
877 if (!sport->dma_rx_desc) {
878 dev_err(sport->port.dev, "Cannot prepare cyclic DMA\n");
879 return -EFAULT;
880 }
881
882 sport->dma_rx_desc->callback = lpuart_dma_rx_complete;
883 sport->dma_rx_desc->callback_param = sport;
884 sport->dma_rx_cookie = dmaengine_submit(sport->dma_rx_desc);
885 dma_async_issue_pending(sport->dma_rx_chan);
886
887 writeb(readb(sport->port.membase + UARTCR5) | UARTCR5_RDMAS,
888 sport->port.membase + UARTCR5);
889
890 return 0;
891}
892
893static void lpuart_dma_tx_free(struct uart_port *port)
894{
895 struct lpuart_port *sport = container_of(port,
896 struct lpuart_port, port);
897
898 dma_unmap_single(sport->port.dev, sport->dma_tx_buf_bus,
899 UART_XMIT_SIZE, DMA_TO_DEVICE);
900
901 sport->dma_tx_buf_bus = 0;
902 sport->dma_tx_buf_virt = NULL;
903}
904
905static void lpuart_dma_rx_free(struct uart_port *port)
906{
907 struct lpuart_port *sport = container_of(port,
908 struct lpuart_port, port);
909
910 if (sport->dma_rx_chan)
911 dmaengine_terminate_all(sport->dma_rx_chan);
912
913 dma_unmap_sg(sport->port.dev, &sport->rx_sgl, 1, DMA_FROM_DEVICE);
914 kfree(sport->rx_ring.buf);
915 sport->rx_ring.tail = 0;
916 sport->rx_ring.head = 0;
917 sport->dma_rx_desc = NULL;
918 sport->dma_rx_cookie = -EINVAL;
919}
920
c9e2e946
JL		 921static unsigned int lpuart_get_mctrl(struct uart_port *port)
922{
923 unsigned int temp = 0;
924 unsigned char reg;
925
926 reg = readb(port->membase + UARTMODEM);
927 if (reg & UARTMODEM_TXCTSE)
928 temp |= TIOCM_CTS;
929
930 if (reg & UARTMODEM_RXRTSE)
931 temp |= TIOCM_RTS;
932
933 return temp;
934}
935
380c966c
JL		 936static unsigned int lpuart32_get_mctrl(struct uart_port *port)
937{
938 unsigned int temp = 0;
939 unsigned long reg;
940
941 reg = lpuart32_read(port->membase + UARTMODIR);
942 if (reg & UARTMODIR_TXCTSE)
943 temp |= TIOCM_CTS;
944
945 if (reg & UARTMODIR_RXRTSE)
946 temp |= TIOCM_RTS;
947
948 return temp;
949}
950
c9e2e946
JL		 951static void lpuart_set_mctrl(struct uart_port *port, unsigned int mctrl)
952{
953 unsigned char temp;
954
955 temp = readb(port->membase + UARTMODEM) &
956 ~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE);
957
958 if (mctrl & TIOCM_RTS)
959 temp |= UARTMODEM_RXRTSE;
960
961 if (mctrl & TIOCM_CTS)
962 temp |= UARTMODEM_TXCTSE;
963
964 writeb(temp, port->membase + UARTMODEM);
965}
966
380c966c
JL		 967static void lpuart32_set_mctrl(struct uart_port *port, unsigned int mctrl)
968{
969 unsigned long temp;
970
971 temp = lpuart32_read(port->membase + UARTMODIR) &
972 ~(UARTMODIR_RXRTSE | UARTMODIR_TXCTSE);
973
974 if (mctrl & TIOCM_RTS)
975 temp |= UARTMODIR_RXRTSE;
976
977 if (mctrl & TIOCM_CTS)
978 temp |= UARTMODIR_TXCTSE;
979
980 lpuart32_write(temp, port->membase + UARTMODIR);
981}
982
c9e2e946
JL		 983static void lpuart_break_ctl(struct uart_port *port, int break_state)
984{
985 unsigned char temp;
986
987 temp = readb(port->membase + UARTCR2) & ~UARTCR2_SBK;
988
989 if (break_state != 0)
990 temp |= UARTCR2_SBK;
991
992 writeb(temp, port->membase + UARTCR2);
993}
994
380c966c
JL		 995static void lpuart32_break_ctl(struct uart_port *port, int break_state)
996{
997 unsigned long temp;
998
999 temp = lpuart32_read(port->membase + UARTCTRL) & ~UARTCTRL_SBK;
1000
1001 if (break_state != 0)
1002 temp |= UARTCTRL_SBK;
1003
1004 lpuart32_write(temp, port->membase + UARTCTRL);
1005}
1006
c9e2e946
JL		 1007static void lpuart_setup_watermark(struct lpuart_port *sport)
1008{
1009 unsigned char val, cr2;
bc764b8f 1010 unsigned char cr2_saved;
c9e2e946
JL		 1011
1012 cr2 = readb(sport->port.membase + UARTCR2);
bc764b8f 1013 cr2_saved = cr2;
c9e2e946
JL		 1014 cr2 &= ~(UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_TE |
1015 UARTCR2_RIE | UARTCR2_RE);
1016 writeb(cr2, sport->port.membase + UARTCR2);
1017
c9e2e946 1018 val = readb(sport->port.membase + UARTPFIFO);
c9e2e946
JL		 1019 writeb(val | UARTPFIFO_TXFE | UARTPFIFO_RXFE,
1020 sport->port.membase + UARTPFIFO);
1021
1022 /* flush Tx and Rx FIFO */
1023 writeb(UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH,
1024 sport->port.membase + UARTCFIFO);
1025
d68827c6
SA		 1026 /* explicitly clear RDRF */
1027 if (readb(sport->port.membase + UARTSR1) & UARTSR1_RDRF) {
1028 readb(sport->port.membase + UARTDR);
1029 writeb(UARTSFIFO_RXUF, sport->port.membase + UARTSFIFO);
1030 }
1031
f1cd8c87 1032 writeb(0, sport->port.membase + UARTTWFIFO);
c9e2e946 1033 writeb(1, sport->port.membase + UARTRWFIFO);
bc764b8f
SG		 1034
1035 /* Restore cr2 */
1036 writeb(cr2_saved, sport->port.membase + UARTCR2);
c9e2e946
JL		 1037}
1038
380c966c
JL		 1039static void lpuart32_setup_watermark(struct lpuart_port *sport)
1040{
1041 unsigned long val, ctrl;
1042 unsigned long ctrl_saved;
1043
1044 ctrl = lpuart32_read(sport->port.membase + UARTCTRL);
1045 ctrl_saved = ctrl;
1046 ctrl &= ~(UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_TE |
1047 UARTCTRL_RIE | UARTCTRL_RE);
1048 lpuart32_write(ctrl, sport->port.membase + UARTCTRL);
1049
1050 /* enable FIFO mode */
1051 val = lpuart32_read(sport->port.membase + UARTFIFO);
1052 val |= UARTFIFO_TXFE | UARTFIFO_RXFE;
1053 val |= UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH;
1054 lpuart32_write(val, sport->port.membase + UARTFIFO);
1055
1056 /* set the watermark */
1057 val = (0x1 << UARTWATER_RXWATER_OFF) | (0x0 << UARTWATER_TXWATER_OFF);
1058 lpuart32_write(val, sport->port.membase + UARTWATER);
1059
1060 /* Restore cr2 */
1061 lpuart32_write(ctrl_saved, sport->port.membase + UARTCTRL);
1062}
1063
f1cd8c87
YY		 1064static int lpuart_dma_tx_request(struct uart_port *port)
1065{
1066 struct lpuart_port *sport = container_of(port,
1067 struct lpuart_port, port);
f1cd8c87
YY		 1068 struct dma_slave_config dma_tx_sconfig;
1069 dma_addr_t dma_bus;
1070 unsigned char *dma_buf;
1071 int ret;
1072
4a818c43 1073 dma_bus = dma_map_single(sport->dma_tx_chan->device->dev,
f1cd8c87
YY		 1074 sport->port.state->xmit.buf,
1075 UART_XMIT_SIZE, DMA_TO_DEVICE);
1076
4a818c43 1077 if (dma_mapping_error(sport->dma_tx_chan->device->dev, dma_bus)) {
f1cd8c87 1078 dev_err(sport->port.dev, "dma_map_single tx failed\n");
f1cd8c87
YY		 1079 return -ENOMEM;
1080 }
1081
1082 dma_buf = sport->port.state->xmit.buf;
1083 dma_tx_sconfig.dst_addr = sport->port.mapbase + UARTDR;
1084 dma_tx_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
ed9891bf 1085 dma_tx_sconfig.dst_maxburst = sport->txfifo_size;
f1cd8c87 1086 dma_tx_sconfig.direction = DMA_MEM_TO_DEV;
4a818c43 1087 ret = dmaengine_slave_config(sport->dma_tx_chan, &dma_tx_sconfig);
f1cd8c87
YY		 1088
1089 if (ret < 0) {
1090 dev_err(sport->port.dev,
1091 "Dma slave config failed, err = %d\n", ret);
f1cd8c87
YY		 1092 return ret;
1093 }
1094
f1cd8c87
YY		 1095 sport->dma_tx_buf_virt = dma_buf;
1096 sport->dma_tx_buf_bus = dma_bus;
1097 sport->dma_tx_in_progress = 0;
1098
1099 return 0;
1100}
1101
5887ad43 1102static void rx_dma_timer_init(struct lpuart_port *sport)
f1cd8c87 1103{
5887ad43
BD		 1104 setup_timer(&sport->lpuart_timer, lpuart_timer_func,
1105 (unsigned long)sport);
1106 sport->lpuart_timer.expires = jiffies + sport->dma_rx_timeout;
1107 add_timer(&sport->lpuart_timer);
f1cd8c87
YY		 1108}
1109
c9e2e946
JL		 1110static int lpuart_startup(struct uart_port *port)
1111{
1112 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1113 int ret;
1114 unsigned long flags;
1115 unsigned char temp;
1116
ed9891bf
SA		 1117 /* determine FIFO size and enable FIFO mode */
1118 temp = readb(sport->port.membase + UARTPFIFO);
1119
1120 sport->txfifo_size = 0x1 << (((temp >> UARTPFIFO_TXSIZE_OFF) &
1121 UARTPFIFO_FIFOSIZE_MASK) + 1);
1122
4e8f2459
SA		 1123 sport->port.fifosize = sport->txfifo_size;
1124
ed9891bf
SA		 1125 sport->rxfifo_size = 0x1 << (((temp >> UARTPFIFO_RXSIZE_OFF) &
1126 UARTPFIFO_FIFOSIZE_MASK) + 1);
1127
c9e2e946
JL		 1128 ret = devm_request_irq(port->dev, port->irq, lpuart_int, 0,
1129 DRIVER_NAME, sport);
1130 if (ret)
1131 return ret;
1132
1133 spin_lock_irqsave(&sport->port.lock, flags);
1134
1135 lpuart_setup_watermark(sport);
1136
1137 temp = readb(sport->port.membase + UARTCR2);
1138 temp |= (UARTCR2_RIE | UARTCR2_TIE | UARTCR2_RE | UARTCR2_TE);
1139 writeb(temp, sport->port.membase + UARTCR2);
1140
5887ad43
BD		 1141 if (sport->dma_rx_chan && !lpuart_start_rx_dma(sport)) {
1142 /* set Rx DMA timeout */
1143 sport->dma_rx_timeout = msecs_to_jiffies(DMA_RX_TIMEOUT);
1144 if (!sport->dma_rx_timeout)
1145 sport->dma_rx_timeout = 1;
1146
1147 sport->lpuart_dma_rx_use = true;
1148 rx_dma_timer_init(sport);
1149 } else {
1150 sport->lpuart_dma_rx_use = false;
1151 }
1152
1153 if (sport->dma_tx_chan && !lpuart_dma_tx_request(port)) {
1154 sport->lpuart_dma_tx_use = true;
1155 temp = readb(port->membase + UARTCR5);
1156 writeb(temp | UARTCR5_TDMAS, port->membase + UARTCR5);
1157 } else {
1158 sport->lpuart_dma_tx_use = false;
1159 }
1160
c9e2e946 1161 spin_unlock_irqrestore(&sport->port.lock, flags);
5887ad43 1162
c9e2e946
JL		 1163 return 0;
1164}
1165
380c966c
JL		 1166static int lpuart32_startup(struct uart_port *port)
1167{
1168 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1169 int ret;
1170 unsigned long flags;
1171 unsigned long temp;
1172
1173 /* determine FIFO size */
1174 temp = lpuart32_read(sport->port.membase + UARTFIFO);
1175
1176 sport->txfifo_size = 0x1 << (((temp >> UARTFIFO_TXSIZE_OFF) &
1177 UARTFIFO_FIFOSIZE_MASK) - 1);
1178
1179 sport->rxfifo_size = 0x1 << (((temp >> UARTFIFO_RXSIZE_OFF) &
1180 UARTFIFO_FIFOSIZE_MASK) - 1);
1181
1182 ret = devm_request_irq(port->dev, port->irq, lpuart32_int, 0,
1183 DRIVER_NAME, sport);
1184 if (ret)
1185 return ret;
1186
1187 spin_lock_irqsave(&sport->port.lock, flags);
1188
1189 lpuart32_setup_watermark(sport);
1190
1191 temp = lpuart32_read(sport->port.membase + UARTCTRL);
1192 temp |= (UARTCTRL_RIE | UARTCTRL_TIE | UARTCTRL_RE | UARTCTRL_TE);
1193 temp |= UARTCTRL_ILIE;
1194 lpuart32_write(temp, sport->port.membase + UARTCTRL);
1195
1196 spin_unlock_irqrestore(&sport->port.lock, flags);
1197 return 0;
1198}
1199
c9e2e946
JL		 1200static void lpuart_shutdown(struct uart_port *port)
1201{
1202 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1203 unsigned char temp;
1204 unsigned long flags;
1205
1206 spin_lock_irqsave(&port->lock, flags);
1207
1208 /* disable Rx/Tx and interrupts */
1209 temp = readb(port->membase + UARTCR2);
1210 temp &= ~(UARTCR2_TE | UARTCR2_RE |
1211 UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_RIE);
1212 writeb(temp, port->membase + UARTCR2);
1213
1214 spin_unlock_irqrestore(&port->lock, flags);
1215
1216 devm_free_irq(port->dev, port->irq, sport);
f1cd8c87 1217
4a818c43 1218 if (sport->lpuart_dma_rx_use) {
4a8588a1 1219 del_timer_sync(&sport->lpuart_timer);
5887ad43 1220 lpuart_dma_rx_free(&sport->port);
f1cd8c87 1221 }
4a818c43
SA		 1222
1223 if (sport->lpuart_dma_tx_use)
1224 lpuart_dma_tx_free(&sport->port);
c9e2e946
JL		 1225}
1226
380c966c
JL		 1227static void lpuart32_shutdown(struct uart_port *port)
1228{
1229 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1230 unsigned long temp;
1231 unsigned long flags;
1232
1233 spin_lock_irqsave(&port->lock, flags);
1234
1235 /* disable Rx/Tx and interrupts */
1236 temp = lpuart32_read(port->membase + UARTCTRL);
1237 temp &= ~(UARTCTRL_TE | UARTCTRL_RE |
1238 UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_RIE);
1239 lpuart32_write(temp, port->membase + UARTCTRL);
1240
1241 spin_unlock_irqrestore(&port->lock, flags);
1242
1243 devm_free_irq(port->dev, port->irq, sport);
1244}
1245
c9e2e946
JL		 1246static void
1247lpuart_set_termios(struct uart_port *port, struct ktermios *termios,
1248 struct ktermios *old)
1249{
1250 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1251 unsigned long flags;
aa9e7d78 1252 unsigned char cr1, old_cr1, old_cr2, cr3, cr4, bdh, modem;
c9e2e946
JL		 1253 unsigned int baud;
1254 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
1255 unsigned int sbr, brfa;
1256
1257 cr1 = old_cr1 = readb(sport->port.membase + UARTCR1);
1258 old_cr2 = readb(sport->port.membase + UARTCR2);
aa9e7d78 1259 cr3 = readb(sport->port.membase + UARTCR3);
c9e2e946
JL		 1260 cr4 = readb(sport->port.membase + UARTCR4);
1261 bdh = readb(sport->port.membase + UARTBDH);
1262 modem = readb(sport->port.membase + UARTMODEM);
1263 /*
1264 * only support CS8 and CS7, and for CS7 must enable PE.
1265 * supported mode:
1266 * - (7,e/o,1)
1267 * - (8,n,1)
1268 * - (8,m/s,1)
1269 * - (8,e/o,1)
1270 */
1271 while ((termios->c_cflag & CSIZE) != CS8 &&
1272 (termios->c_cflag & CSIZE) != CS7) {
1273 termios->c_cflag &= ~CSIZE;
1274 termios->c_cflag |= old_csize;
1275 old_csize = CS8;
1276 }
1277
1278 if ((termios->c_cflag & CSIZE) == CS8 ||
1279 (termios->c_cflag & CSIZE) == CS7)
1280 cr1 = old_cr1 & ~UARTCR1_M;
1281
1282 if (termios->c_cflag & CMSPAR) {
1283 if ((termios->c_cflag & CSIZE) != CS8) {
1284 termios->c_cflag &= ~CSIZE;
1285 termios->c_cflag |= CS8;
1286 }
1287 cr1 |= UARTCR1_M;
1288 }
1289
1290 if (termios->c_cflag & CRTSCTS) {
1291 modem |= (UARTMODEM_RXRTSE | UARTMODEM_TXCTSE);
1292 } else {
1293 termios->c_cflag &= ~CRTSCTS;
1294 modem &= ~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE);
1295 }
1296
1297 if (termios->c_cflag & CSTOPB)
1298 termios->c_cflag &= ~CSTOPB;
1299
1300 /* parity must be enabled when CS7 to match 8-bits format */
1301 if ((termios->c_cflag & CSIZE) == CS7)
1302 termios->c_cflag |= PARENB;
1303
1304 if ((termios->c_cflag & PARENB)) {
1305 if (termios->c_cflag & CMSPAR) {
1306 cr1 &= ~UARTCR1_PE;
aa9e7d78
BD		 1307 if (termios->c_cflag & PARODD)
1308 cr3 |= UARTCR3_T8;
1309 else
1310 cr3 &= ~UARTCR3_T8;
c9e2e946
JL		 1311 } else {
1312 cr1 |= UARTCR1_PE;
1313 if ((termios->c_cflag & CSIZE) == CS8)
1314 cr1 |= UARTCR1_M;
1315 if (termios->c_cflag & PARODD)
1316 cr1 |= UARTCR1_PT;
1317 else
1318 cr1 &= ~UARTCR1_PT;
1319 }
1320 }
1321
1322 /* ask the core to calculate the divisor */
1323 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
1324
1325 spin_lock_irqsave(&sport->port.lock, flags);
1326
1327 sport->port.read_status_mask = 0;
1328 if (termios->c_iflag & INPCK)
1329 sport->port.read_status_mask |= (UARTSR1_FE | UARTSR1_PE);
ef8b9ddc 1330 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
c9e2e946
JL		 1331 sport->port.read_status_mask |= UARTSR1_FE;
1332
1333 /* characters to ignore */
1334 sport->port.ignore_status_mask = 0;
1335 if (termios->c_iflag & IGNPAR)
1336 sport->port.ignore_status_mask |= UARTSR1_PE;
1337 if (termios->c_iflag & IGNBRK) {
1338 sport->port.ignore_status_mask |= UARTSR1_FE;
1339 /*
1340 * if we're ignoring parity and break indicators,
1341 * ignore overruns too (for real raw support).
1342 */
1343 if (termios->c_iflag & IGNPAR)
1344 sport->port.ignore_status_mask |= UARTSR1_OR;
1345 }
1346
1347 /* update the per-port timeout */
1348 uart_update_timeout(port, termios->c_cflag, baud);
1349
1350 /* wait transmit engin complete */
1351 while (!(readb(sport->port.membase + UARTSR1) & UARTSR1_TC))
1352 barrier();
1353
1354 /* disable transmit and receive */
1355 writeb(old_cr2 & ~(UARTCR2_TE | UARTCR2_RE),
1356 sport->port.membase + UARTCR2);
1357
1358 sbr = sport->port.uartclk / (16 * baud);
1359 brfa = ((sport->port.uartclk - (16 * sbr * baud)) * 2) / baud;
1360 bdh &= ~UARTBDH_SBR_MASK;
1361 bdh |= (sbr >> 8) & 0x1F;
1362 cr4 &= ~UARTCR4_BRFA_MASK;
1363 brfa &= UARTCR4_BRFA_MASK;
1364 writeb(cr4 | brfa, sport->port.membase + UARTCR4);
1365 writeb(bdh, sport->port.membase + UARTBDH);
1366 writeb(sbr & 0xFF, sport->port.membase + UARTBDL);
aa9e7d78 1367 writeb(cr3, sport->port.membase + UARTCR3);
c9e2e946
JL		 1368 writeb(cr1, sport->port.membase + UARTCR1);
1369 writeb(modem, sport->port.membase + UARTMODEM);
1370
1371 /* restore control register */
1372 writeb(old_cr2, sport->port.membase + UARTCR2);
1373
5887ad43
BD		 1374 /*
1375 * If new baud rate is set, we will also need to update the Ring buffer
1376 * length according to the selected baud rate and restart Rx DMA path.
1377 */
1378 if (old) {
1379 if (sport->lpuart_dma_rx_use) {
1380 del_timer_sync(&sport->lpuart_timer);
1381 lpuart_dma_rx_free(&sport->port);
1382 }
1383
1384 if (sport->dma_rx_chan && !lpuart_start_rx_dma(sport)) {
1385 sport->lpuart_dma_rx_use = true;
1386 rx_dma_timer_init(sport);
1387 } else {
1388 sport->lpuart_dma_rx_use = false;
1389 }
1390 }
1391
c9e2e946
JL		 1392 spin_unlock_irqrestore(&sport->port.lock, flags);
1393}
1394
380c966c
JL		 1395static void
1396lpuart32_set_termios(struct uart_port *port, struct ktermios *termios,
1397 struct ktermios *old)
1398{
1399 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1400 unsigned long flags;
1401 unsigned long ctrl, old_ctrl, bd, modem;
1402 unsigned int baud;
1403 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
1404 unsigned int sbr;
1405
1406 ctrl = old_ctrl = lpuart32_read(sport->port.membase + UARTCTRL);
1407 bd = lpuart32_read(sport->port.membase + UARTBAUD);
1408 modem = lpuart32_read(sport->port.membase + UARTMODIR);
1409 /*
1410 * only support CS8 and CS7, and for CS7 must enable PE.
1411 * supported mode:
1412 * - (7,e/o,1)
1413 * - (8,n,1)
1414 * - (8,m/s,1)
1415 * - (8,e/o,1)
1416 */
1417 while ((termios->c_cflag & CSIZE) != CS8 &&
1418 (termios->c_cflag & CSIZE) != CS7) {
1419 termios->c_cflag &= ~CSIZE;
1420 termios->c_cflag |= old_csize;
1421 old_csize = CS8;
1422 }
1423
1424 if ((termios->c_cflag & CSIZE) == CS8 ||
1425 (termios->c_cflag & CSIZE) == CS7)
1426 ctrl = old_ctrl & ~UARTCTRL_M;
1427
1428 if (termios->c_cflag & CMSPAR) {
1429 if ((termios->c_cflag & CSIZE) != CS8) {
1430 termios->c_cflag &= ~CSIZE;
1431 termios->c_cflag |= CS8;
1432 }
1433 ctrl |= UARTCTRL_M;
1434 }
1435
1436 if (termios->c_cflag & CRTSCTS) {
1437 modem |= (UARTMODEM_RXRTSE | UARTMODEM_TXCTSE);
1438 } else {
1439 termios->c_cflag &= ~CRTSCTS;
1440 modem &= ~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE);
1441 }
1442
1443 if (termios->c_cflag & CSTOPB)
1444 termios->c_cflag &= ~CSTOPB;
1445
1446 /* parity must be enabled when CS7 to match 8-bits format */
1447 if ((termios->c_cflag & CSIZE) == CS7)
1448 termios->c_cflag |= PARENB;
1449
1450 if ((termios->c_cflag & PARENB)) {
1451 if (termios->c_cflag & CMSPAR) {
1452 ctrl &= ~UARTCTRL_PE;
1453 ctrl |= UARTCTRL_M;
1454 } else {
1455 ctrl |= UARTCR1_PE;
1456 if ((termios->c_cflag & CSIZE) == CS8)
1457 ctrl |= UARTCTRL_M;
1458 if (termios->c_cflag & PARODD)
1459 ctrl |= UARTCTRL_PT;
1460 else
1461 ctrl &= ~UARTCTRL_PT;
1462 }
1463 }
1464
1465 /* ask the core to calculate the divisor */
1466 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
1467
1468 spin_lock_irqsave(&sport->port.lock, flags);
1469
1470 sport->port.read_status_mask = 0;
1471 if (termios->c_iflag & INPCK)
1472 sport->port.read_status_mask |= (UARTSTAT_FE | UARTSTAT_PE);
1473 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
1474 sport->port.read_status_mask |= UARTSTAT_FE;
1475
1476 /* characters to ignore */
1477 sport->port.ignore_status_mask = 0;
1478 if (termios->c_iflag & IGNPAR)
1479 sport->port.ignore_status_mask |= UARTSTAT_PE;
1480 if (termios->c_iflag & IGNBRK) {
1481 sport->port.ignore_status_mask |= UARTSTAT_FE;
1482 /*
1483 * if we're ignoring parity and break indicators,
1484 * ignore overruns too (for real raw support).
1485 */
1486 if (termios->c_iflag & IGNPAR)
1487 sport->port.ignore_status_mask |= UARTSTAT_OR;
1488 }
1489
1490 /* update the per-port timeout */
1491 uart_update_timeout(port, termios->c_cflag, baud);
1492
1493 /* wait transmit engin complete */
1494 while (!(lpuart32_read(sport->port.membase + UARTSTAT) & UARTSTAT_TC))
1495 barrier();
1496
1497 /* disable transmit and receive */
1498 lpuart32_write(old_ctrl & ~(UARTCTRL_TE | UARTCTRL_RE),
1499 sport->port.membase + UARTCTRL);
1500
1501 sbr = sport->port.uartclk / (16 * baud);
1502 bd &= ~UARTBAUD_SBR_MASK;
1503 bd |= sbr & UARTBAUD_SBR_MASK;
1504 bd |= UARTBAUD_BOTHEDGE;
1505 bd &= ~(UARTBAUD_TDMAE | UARTBAUD_RDMAE);
1506 lpuart32_write(bd, sport->port.membase + UARTBAUD);
1507 lpuart32_write(modem, sport->port.membase + UARTMODIR);
1508 lpuart32_write(ctrl, sport->port.membase + UARTCTRL);
1509 /* restore control register */
1510
1511 spin_unlock_irqrestore(&sport->port.lock, flags);
1512}
1513
c9e2e946
JL		 1514static const char *lpuart_type(struct uart_port *port)
1515{
1516 return "FSL_LPUART";
1517}
1518
1519static void lpuart_release_port(struct uart_port *port)
1520{
1521 /* nothing to do */
1522}
1523
1524static int lpuart_request_port(struct uart_port *port)
1525{
1526 return 0;
1527}
1528
1529/* configure/autoconfigure the port */
1530static void lpuart_config_port(struct uart_port *port, int flags)
1531{
1532 if (flags & UART_CONFIG_TYPE)
1533 port->type = PORT_LPUART;
1534}
1535
1536static int lpuart_verify_port(struct uart_port *port, struct serial_struct *ser)
1537{
1538 int ret = 0;
1539
1540 if (ser->type != PORT_UNKNOWN && ser->type != PORT_LPUART)
1541 ret = -EINVAL;
1542 if (port->irq != ser->irq)
1543 ret = -EINVAL;
1544 if (ser->io_type != UPIO_MEM)
1545 ret = -EINVAL;
1546 if (port->uartclk / 16 != ser->baud_base)
1547 ret = -EINVAL;
1548 if (port->iobase != ser->port)
1549 ret = -EINVAL;
1550 if (ser->hub6 != 0)
1551 ret = -EINVAL;
1552 return ret;
1553}
1554
1555static struct uart_ops lpuart_pops = {
1556 .tx_empty = lpuart_tx_empty,
1557 .set_mctrl = lpuart_set_mctrl,
1558 .get_mctrl = lpuart_get_mctrl,
1559 .stop_tx = lpuart_stop_tx,
1560 .start_tx = lpuart_start_tx,
1561 .stop_rx = lpuart_stop_rx,
c9e2e946
JL		 1562 .break_ctl = lpuart_break_ctl,
1563 .startup = lpuart_startup,
1564 .shutdown = lpuart_shutdown,
1565 .set_termios = lpuart_set_termios,
1566 .type = lpuart_type,
1567 .request_port = lpuart_request_port,
1568 .release_port = lpuart_release_port,
1569 .config_port = lpuart_config_port,
1570 .verify_port = lpuart_verify_port,
bfc2e07f 1571 .flush_buffer = lpuart_flush_buffer,
c9e2e946
JL		 1572};
1573
380c966c
JL		 1574static struct uart_ops lpuart32_pops = {
1575 .tx_empty = lpuart32_tx_empty,
1576 .set_mctrl = lpuart32_set_mctrl,
1577 .get_mctrl = lpuart32_get_mctrl,
1578 .stop_tx = lpuart32_stop_tx,
1579 .start_tx = lpuart32_start_tx,
1580 .stop_rx = lpuart32_stop_rx,
1581 .break_ctl = lpuart32_break_ctl,
1582 .startup = lpuart32_startup,
1583 .shutdown = lpuart32_shutdown,
1584 .set_termios = lpuart32_set_termios,
1585 .type = lpuart_type,
1586 .request_port = lpuart_request_port,
1587 .release_port = lpuart_release_port,
1588 .config_port = lpuart_config_port,
1589 .verify_port = lpuart_verify_port,
bfc2e07f 1590 .flush_buffer = lpuart_flush_buffer,
380c966c
JL		 1591};
1592
c9e2e946
JL		 1593static struct lpuart_port *lpuart_ports[UART_NR];
1594
1595#ifdef CONFIG_SERIAL_FSL_LPUART_CONSOLE
1596static void lpuart_console_putchar(struct uart_port *port, int ch)
1597{
1598 while (!(readb(port->membase + UARTSR1) & UARTSR1_TDRE))
1599 barrier();
1600
1601 writeb(ch, port->membase + UARTDR);
1602}
1603
380c966c
JL		 1604static void lpuart32_console_putchar(struct uart_port *port, int ch)
1605{
1606 while (!(lpuart32_read(port->membase + UARTSTAT) & UARTSTAT_TDRE))
1607 barrier();
1608
1609 lpuart32_write(ch, port->membase + UARTDATA);
1610}
1611
c9e2e946
JL		 1612static void
1613lpuart_console_write(struct console *co, const char *s, unsigned int count)
1614{
1615 struct lpuart_port *sport = lpuart_ports[co->index];
1616 unsigned char old_cr2, cr2;
1617
1618 /* first save CR2 and then disable interrupts */
1619 cr2 = old_cr2 = readb(sport->port.membase + UARTCR2);
1620 cr2 |= (UARTCR2_TE | UARTCR2_RE);
1621 cr2 &= ~(UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_RIE);
1622 writeb(cr2, sport->port.membase + UARTCR2);
1623
1624 uart_console_write(&sport->port, s, count, lpuart_console_putchar);
1625
1626 /* wait for transmitter finish complete and restore CR2 */
1627 while (!(readb(sport->port.membase + UARTSR1) & UARTSR1_TC))
1628 barrier();
1629
1630 writeb(old_cr2, sport->port.membase + UARTCR2);
1631}
1632
380c966c
JL		 1633static void
1634lpuart32_console_write(struct console *co, const char *s, unsigned int count)
1635{
1636 struct lpuart_port *sport = lpuart_ports[co->index];
1637 unsigned long old_cr, cr;
1638
1639 /* first save CR2 and then disable interrupts */
1640 cr = old_cr = lpuart32_read(sport->port.membase + UARTCTRL);
1641 cr |= (UARTCTRL_TE | UARTCTRL_RE);
1642 cr &= ~(UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_RIE);
1643 lpuart32_write(cr, sport->port.membase + UARTCTRL);
1644
1645 uart_console_write(&sport->port, s, count, lpuart32_console_putchar);
1646
1647 /* wait for transmitter finish complete and restore CR2 */
1648 while (!(lpuart32_read(sport->port.membase + UARTSTAT) & UARTSTAT_TC))
1649 barrier();
1650
1651 lpuart32_write(old_cr, sport->port.membase + UARTCTRL);
1652}
1653
c9e2e946
JL		 1654/*
1655 * if the port was already initialised (eg, by a boot loader),
1656 * try to determine the current setup.
1657 */
1658static void __init
1659lpuart_console_get_options(struct lpuart_port *sport, int *baud,
1660 int *parity, int *bits)
1661{
1662 unsigned char cr, bdh, bdl, brfa;
1663 unsigned int sbr, uartclk, baud_raw;
1664
1665 cr = readb(sport->port.membase + UARTCR2);
1666 cr &= UARTCR2_TE | UARTCR2_RE;
1667 if (!cr)
1668 return;
1669
1670 /* ok, the port was enabled */
1671
1672 cr = readb(sport->port.membase + UARTCR1);
1673
1674 *parity = 'n';
1675 if (cr & UARTCR1_PE) {
1676 if (cr & UARTCR1_PT)
1677 *parity = 'o';
1678 else
1679 *parity = 'e';
1680 }
1681
1682 if (cr & UARTCR1_M)
1683 *bits = 9;
1684 else
1685 *bits = 8;
1686
1687 bdh = readb(sport->port.membase + UARTBDH);
1688 bdh &= UARTBDH_SBR_MASK;
1689 bdl = readb(sport->port.membase + UARTBDL);
1690 sbr = bdh;
1691 sbr <<= 8;
1692 sbr |= bdl;
1693 brfa = readb(sport->port.membase + UARTCR4);
1694 brfa &= UARTCR4_BRFA_MASK;
1695
1696 uartclk = clk_get_rate(sport->clk);
1697 /*
1698 * baud = mod_clk/(16*(sbr[13]+(brfa)/32)
1699 */
1700 baud_raw = uartclk / (16 * (sbr + brfa / 32));
1701
1702 if (*baud != baud_raw)
1703 printk(KERN_INFO "Serial: Console lpuart rounded baud rate"
1704 "from %d to %d\n", baud_raw, *baud);
1705}
1706
380c966c
JL		 1707static void __init
1708lpuart32_console_get_options(struct lpuart_port *sport, int *baud,
1709 int *parity, int *bits)
1710{
1711 unsigned long cr, bd;
1712 unsigned int sbr, uartclk, baud_raw;
1713
1714 cr = lpuart32_read(sport->port.membase + UARTCTRL);
1715 cr &= UARTCTRL_TE | UARTCTRL_RE;
1716 if (!cr)
1717 return;
1718
1719 /* ok, the port was enabled */
1720
1721 cr = lpuart32_read(sport->port.membase + UARTCTRL);
1722
1723 *parity = 'n';
1724 if (cr & UARTCTRL_PE) {
1725 if (cr & UARTCTRL_PT)
1726 *parity = 'o';
1727 else
1728 *parity = 'e';
1729 }
1730
1731 if (cr & UARTCTRL_M)
1732 *bits = 9;
1733 else
1734 *bits = 8;
1735
1736 bd = lpuart32_read(sport->port.membase + UARTBAUD);
1737 bd &= UARTBAUD_SBR_MASK;
1738 sbr = bd;
1739 uartclk = clk_get_rate(sport->clk);
1740 /*
1741 * baud = mod_clk/(16*(sbr[13]+(brfa)/32)
1742 */
1743 baud_raw = uartclk / (16 * sbr);
1744
1745 if (*baud != baud_raw)
1746 printk(KERN_INFO "Serial: Console lpuart rounded baud rate"
1747 "from %d to %d\n", baud_raw, *baud);
1748}
1749
c9e2e946
JL		 1750static int __init lpuart_console_setup(struct console *co, char *options)
1751{
1752 struct lpuart_port *sport;
1753 int baud = 115200;
1754 int bits = 8;
1755 int parity = 'n';
1756 int flow = 'n';
1757
1758 /*
1759 * check whether an invalid uart number has been specified, and
1760 * if so, search for the first available port that does have
1761 * console support.
1762 */
1763 if (co->index == -1 || co->index >= ARRAY_SIZE(lpuart_ports))
1764 co->index = 0;
1765
1766 sport = lpuart_ports[co->index];
1767 if (sport == NULL)
1768 return -ENODEV;
1769
1770 if (options)
1771 uart_parse_options(options, &baud, &parity, &bits, &flow);
1772 else
380c966c
JL		 1773 if (sport->lpuart32)
1774 lpuart32_console_get_options(sport, &baud, &parity, &bits);
1775 else
1776 lpuart_console_get_options(sport, &baud, &parity, &bits);
c9e2e946 1777
380c966c
JL		 1778 if (sport->lpuart32)
1779 lpuart32_setup_watermark(sport);
1780 else
1781 lpuart_setup_watermark(sport);
c9e2e946
JL		 1782
1783 return uart_set_options(&sport->port, co, baud, parity, bits, flow);
1784}
1785
1786static struct uart_driver lpuart_reg;
1787static struct console lpuart_console = {
1788 .name = DEV_NAME,
1789 .write = lpuart_console_write,
1790 .device = uart_console_device,
1791 .setup = lpuart_console_setup,
1792 .flags = CON_PRINTBUFFER,
1793 .index = -1,
1794 .data = &lpuart_reg,
1795};
1796
380c966c
JL		 1797static struct console lpuart32_console = {
1798 .name = DEV_NAME,
1799 .write = lpuart32_console_write,
1800 .device = uart_console_device,
1801 .setup = lpuart_console_setup,
1802 .flags = CON_PRINTBUFFER,
1803 .index = -1,
1804 .data = &lpuart_reg,
1805};
1806
1d59b382
SA		 1807static void lpuart_early_write(struct console *con, const char *s, unsigned n)
1808{
1809 struct earlycon_device *dev = con->data;
1810
1811 uart_console_write(&dev->port, s, n, lpuart_console_putchar);
1812}
1813
1814static void lpuart32_early_write(struct console *con, const char *s, unsigned n)
1815{
1816 struct earlycon_device *dev = con->data;
1817
1818 uart_console_write(&dev->port, s, n, lpuart32_console_putchar);
1819}
1820
1821static int __init lpuart_early_console_setup(struct earlycon_device *device,
1822 const char *opt)
1823{
1824 if (!device->port.membase)
1825 return -ENODEV;
1826
1827 device->con->write = lpuart_early_write;
1828 return 0;
1829}
1830
1831static int __init lpuart32_early_console_setup(struct earlycon_device *device,
1832 const char *opt)
1833{
1834 if (!device->port.membase)
1835 return -ENODEV;
1836
1837 device->con->write = lpuart32_early_write;
1838 return 0;
1839}
1840
1841OF_EARLYCON_DECLARE(lpuart, "fsl,vf610-lpuart", lpuart_early_console_setup);
1842OF_EARLYCON_DECLARE(lpuart32, "fsl,ls1021a-lpuart", lpuart32_early_console_setup);
1843EARLYCON_DECLARE(lpuart, lpuart_early_console_setup);
1844EARLYCON_DECLARE(lpuart32, lpuart32_early_console_setup);
1845
c9e2e946 1846#define LPUART_CONSOLE (&lpuart_console)
380c966c 1847#define LPUART32_CONSOLE (&lpuart32_console)
c9e2e946
JL		 1848#else
1849#define LPUART_CONSOLE NULL
380c966c 1850#define LPUART32_CONSOLE NULL
c9e2e946
JL		 1851#endif
1852
1853static struct uart_driver lpuart_reg = {
1854 .owner = THIS_MODULE,
1855 .driver_name = DRIVER_NAME,
1856 .dev_name = DEV_NAME,
1857 .nr = ARRAY_SIZE(lpuart_ports),
1858 .cons = LPUART_CONSOLE,
1859};
1860
1861static int lpuart_probe(struct platform_device *pdev)
1862{
1863 struct device_node *np = pdev->dev.of_node;
1864 struct lpuart_port *sport;
1865 struct resource *res;
1866 int ret;
1867
1868 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);
1869 if (!sport)
1870 return -ENOMEM;
1871
1872 pdev->dev.coherent_dma_mask = 0;
1873
1874 ret = of_alias_get_id(np, "serial");
1875 if (ret < 0) {
1876 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret);
1877 return ret;
1878 }
1879 sport->port.line = ret;
380c966c 1880 sport->lpuart32 = of_device_is_compatible(np, "fsl,ls1021a-lpuart");
c9e2e946 1881
4ae612a3 1882 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
c9e2e946
JL		 1883 sport->port.membase = devm_ioremap_resource(&pdev->dev, res);
1884 if (IS_ERR(sport->port.membase))
1885 return PTR_ERR(sport->port.membase);
1886
4ae612a3 1887 sport->port.mapbase = res->start;
c9e2e946
JL		 1888 sport->port.dev = &pdev->dev;
1889 sport->port.type = PORT_LPUART;
1890 sport->port.iotype = UPIO_MEM;
394a9e2c
JS		 1891 ret = platform_get_irq(pdev, 0);
1892 if (ret < 0) {
1893 dev_err(&pdev->dev, "cannot obtain irq\n");
1894 return ret;
1895 }
1896 sport->port.irq = ret;
1897
380c966c
JL		 1898 if (sport->lpuart32)
1899 sport->port.ops = &lpuart32_pops;
1900 else
1901 sport->port.ops = &lpuart_pops;
c9e2e946
JL		 1902 sport->port.flags = UPF_BOOT_AUTOCONF;
1903
1904 sport->clk = devm_clk_get(&pdev->dev, "ipg");
1905 if (IS_ERR(sport->clk)) {
1906 ret = PTR_ERR(sport->clk);
1907 dev_err(&pdev->dev, "failed to get uart clk: %d\n", ret);
1908 return ret;
1909 }
1910
1911 ret = clk_prepare_enable(sport->clk);
1912 if (ret) {
1913 dev_err(&pdev->dev, "failed to enable uart clk: %d\n", ret);
1914 return ret;
1915 }
1916
1917 sport->port.uartclk = clk_get_rate(sport->clk);
1918
1919 lpuart_ports[sport->port.line] = sport;
1920
1921 platform_set_drvdata(pdev, &sport->port);
1922
380c966c
JL		 1923 if (sport->lpuart32)
1924 lpuart_reg.cons = LPUART32_CONSOLE;
1925 else
1926 lpuart_reg.cons = LPUART_CONSOLE;
1927
c9e2e946
JL		 1928 ret = uart_add_one_port(&lpuart_reg, &sport->port);
1929 if (ret) {
1930 clk_disable_unprepare(sport->clk);
1931 return ret;
1932 }
1933
4a818c43
SA		 1934 sport->dma_tx_chan = dma_request_slave_channel(sport->port.dev, "tx");
1935 if (!sport->dma_tx_chan)
1936 dev_info(sport->port.dev, "DMA tx channel request failed, "
1937 "operating without tx DMA\n");
1938
1939 sport->dma_rx_chan = dma_request_slave_channel(sport->port.dev, "rx");
1940 if (!sport->dma_rx_chan)
1941 dev_info(sport->port.dev, "DMA rx channel request failed, "
1942 "operating without rx DMA\n");
1943
c9e2e946
JL		 1944 return 0;
1945}
1946
1947static int lpuart_remove(struct platform_device *pdev)
1948{
1949 struct lpuart_port *sport = platform_get_drvdata(pdev);
1950
1951 uart_remove_one_port(&lpuart_reg, &sport->port);
1952
1953 clk_disable_unprepare(sport->clk);
1954
4a818c43
SA		 1955 if (sport->dma_tx_chan)
1956 dma_release_channel(sport->dma_tx_chan);
1957
1958 if (sport->dma_rx_chan)
1959 dma_release_channel(sport->dma_rx_chan);
1960
c9e2e946
JL		 1961 return 0;
1962}
1963
1964#ifdef CONFIG_PM_SLEEP
1965static int lpuart_suspend(struct device *dev)
1966{
1967 struct lpuart_port *sport = dev_get_drvdata(dev);
2fe605df
YY		 1968 unsigned long temp;
1969
1970 if (sport->lpuart32) {
1971 /* disable Rx/Tx and interrupts */
1972 temp = lpuart32_read(sport->port.membase + UARTCTRL);
1973 temp &= ~(UARTCTRL_TE | UARTCTRL_TIE | UARTCTRL_TCIE);
1974 lpuart32_write(temp, sport->port.membase + UARTCTRL);
1975 } else {
1976 /* disable Rx/Tx and interrupts */
1977 temp = readb(sport->port.membase + UARTCR2);
1978 temp &= ~(UARTCR2_TE | UARTCR2_TIE | UARTCR2_TCIE);
1979 writeb(temp, sport->port.membase + UARTCR2);
1980 }
c9e2e946
JL		 1981
1982 uart_suspend_port(&lpuart_reg, &sport->port);
d6b0d2f2
SA		 1983 if (sport->port.suspended && !sport->port.irq_wake)
1984 clk_disable_unprepare(sport->clk);
c9e2e946
JL		 1985
1986 return 0;
1987}
1988
1989static int lpuart_resume(struct device *dev)
1990{
1991 struct lpuart_port *sport = dev_get_drvdata(dev);
08de1014
JL		 1992 unsigned long temp;
1993
d6b0d2f2
SA		 1994 if (sport->port.suspended && !sport->port.irq_wake)
1995 clk_prepare_enable(sport->clk);
1996
08de1014
JL		 1997 if (sport->lpuart32) {
1998 lpuart32_setup_watermark(sport);
1999 temp = lpuart32_read(sport->port.membase + UARTCTRL);
2000 temp |= (UARTCTRL_RIE | UARTCTRL_TIE | UARTCTRL_RE |
2001 UARTCTRL_TE | UARTCTRL_ILIE);
2002 lpuart32_write(temp, sport->port.membase + UARTCTRL);
2003 } else {
2004 lpuart_setup_watermark(sport);
2005 temp = readb(sport->port.membase + UARTCR2);
2006 temp |= (UARTCR2_RIE | UARTCR2_TIE | UARTCR2_RE | UARTCR2_TE);
2007 writeb(temp, sport->port.membase + UARTCR2);
2008 }
c9e2e946
JL		 2009
2010 uart_resume_port(&lpuart_reg, &sport->port);
2011
2012 return 0;
2013}
2014#endif
2015
2016static SIMPLE_DEV_PM_OPS(lpuart_pm_ops, lpuart_suspend, lpuart_resume);
2017
2018static struct platform_driver lpuart_driver = {
2019 .probe = lpuart_probe,
2020 .remove = lpuart_remove,
2021 .driver = {
2022 .name = "fsl-lpuart",
c9e2e946
JL		 2023 .of_match_table = lpuart_dt_ids,
2024 .pm = &lpuart_pm_ops,
2025 },
2026};
2027
2028static int __init lpuart_serial_init(void)
2029{
144c29ed 2030 int ret = uart_register_driver(&lpuart_reg);
c9e2e946 2031
c9e2e946
JL		 2032 if (ret)
2033 return ret;
2034
2035 ret = platform_driver_register(&lpuart_driver);
2036 if (ret)
2037 uart_unregister_driver(&lpuart_reg);
2038
39c34b09 2039 return ret;
c9e2e946
JL		 2040}
2041
2042static void __exit lpuart_serial_exit(void)
2043{
2044 platform_driver_unregister(&lpuart_driver);
2045 uart_unregister_driver(&lpuart_reg);
2046}
2047
2048module_init(lpuart_serial_init);
2049module_exit(lpuart_serial_exit);
2050
2051MODULE_DESCRIPTION("Freescale lpuart serial port driver");
2052MODULE_LICENSE("GPL v2");
Linux 6.x block layer and io_uring tree(s)