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serial: fsl_lpuart: move DMA channel request to probe
[linux-2.6-block.git] / drivers / tty / serial / fsl_lpuart.c
CommitLineData
c9e2e946
JL		 1/*
2 * Freescale lpuart serial port driver
3 *
380c966c 4 * Copyright 2012-2014 Freescale Semiconductor, Inc.
c9e2e946
JL		 5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 */
11
12#if defined(CONFIG_SERIAL_FSL_LPUART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
13#define SUPPORT_SYSRQ
14#endif
15
f1cd8c87
YY		 16#include <linux/clk.h>
17#include <linux/console.h>
18#include <linux/dma-mapping.h>
19#include <linux/dmaengine.h>
20#include <linux/dmapool.h>
c9e2e946
JL		 21#include <linux/io.h>
22#include <linux/irq.h>
f1cd8c87 23#include <linux/module.h>
c9e2e946
JL		 24#include <linux/of.h>
25#include <linux/of_device.h>
f1cd8c87 26#include <linux/of_dma.h>
c9e2e946 27#include <linux/serial_core.h>
f1cd8c87 28#include <linux/slab.h>
c9e2e946
JL		 29#include <linux/tty_flip.h>
30
31/* All registers are 8-bit width */
32#define UARTBDH 0x00
33#define UARTBDL 0x01
34#define UARTCR1 0x02
35#define UARTCR2 0x03
36#define UARTSR1 0x04
37#define UARTCR3 0x06
38#define UARTDR 0x07
39#define UARTCR4 0x0a
40#define UARTCR5 0x0b
41#define UARTMODEM 0x0d
42#define UARTPFIFO 0x10
43#define UARTCFIFO 0x11
44#define UARTSFIFO 0x12
45#define UARTTWFIFO 0x13
46#define UARTTCFIFO 0x14
47#define UARTRWFIFO 0x15
48
49#define UARTBDH_LBKDIE 0x80
50#define UARTBDH_RXEDGIE 0x40
51#define UARTBDH_SBR_MASK 0x1f
52
53#define UARTCR1_LOOPS 0x80
54#define UARTCR1_RSRC 0x20
55#define UARTCR1_M 0x10
56#define UARTCR1_WAKE 0x08
57#define UARTCR1_ILT 0x04
58#define UARTCR1_PE 0x02
59#define UARTCR1_PT 0x01
60
61#define UARTCR2_TIE 0x80
62#define UARTCR2_TCIE 0x40
63#define UARTCR2_RIE 0x20
64#define UARTCR2_ILIE 0x10
65#define UARTCR2_TE 0x08
66#define UARTCR2_RE 0x04
67#define UARTCR2_RWU 0x02
68#define UARTCR2_SBK 0x01
69
70#define UARTSR1_TDRE 0x80
71#define UARTSR1_TC 0x40
72#define UARTSR1_RDRF 0x20
73#define UARTSR1_IDLE 0x10
74#define UARTSR1_OR 0x08
75#define UARTSR1_NF 0x04
76#define UARTSR1_FE 0x02
77#define UARTSR1_PE 0x01
78
79#define UARTCR3_R8 0x80
80#define UARTCR3_T8 0x40
81#define UARTCR3_TXDIR 0x20
82#define UARTCR3_TXINV 0x10
83#define UARTCR3_ORIE 0x08
84#define UARTCR3_NEIE 0x04
85#define UARTCR3_FEIE 0x02
86#define UARTCR3_PEIE 0x01
87
88#define UARTCR4_MAEN1 0x80
89#define UARTCR4_MAEN2 0x40
90#define UARTCR4_M10 0x20
91#define UARTCR4_BRFA_MASK 0x1f
92#define UARTCR4_BRFA_OFF 0
93
94#define UARTCR5_TDMAS 0x80
95#define UARTCR5_RDMAS 0x20
96
97#define UARTMODEM_RXRTSE 0x08
98#define UARTMODEM_TXRTSPOL 0x04
99#define UARTMODEM_TXRTSE 0x02
100#define UARTMODEM_TXCTSE 0x01
101
102#define UARTPFIFO_TXFE 0x80
103#define UARTPFIFO_FIFOSIZE_MASK 0x7
104#define UARTPFIFO_TXSIZE_OFF 4
105#define UARTPFIFO_RXFE 0x08
106#define UARTPFIFO_RXSIZE_OFF 0
107
108#define UARTCFIFO_TXFLUSH 0x80
109#define UARTCFIFO_RXFLUSH 0x40
110#define UARTCFIFO_RXOFE 0x04
111#define UARTCFIFO_TXOFE 0x02
112#define UARTCFIFO_RXUFE 0x01
113
114#define UARTSFIFO_TXEMPT 0x80
115#define UARTSFIFO_RXEMPT 0x40
116#define UARTSFIFO_RXOF 0x04
117#define UARTSFIFO_TXOF 0x02
118#define UARTSFIFO_RXUF 0x01
119
380c966c
JL		 120/* 32-bit register defination */
121#define UARTBAUD 0x00
122#define UARTSTAT 0x04
123#define UARTCTRL 0x08
124#define UARTDATA 0x0C
125#define UARTMATCH 0x10
126#define UARTMODIR 0x14
127#define UARTFIFO 0x18
128#define UARTWATER 0x1c
129
130#define UARTBAUD_MAEN1 0x80000000
131#define UARTBAUD_MAEN2 0x40000000
132#define UARTBAUD_M10 0x20000000
133#define UARTBAUD_TDMAE 0x00800000
134#define UARTBAUD_RDMAE 0x00200000
135#define UARTBAUD_MATCFG 0x00400000
136#define UARTBAUD_BOTHEDGE 0x00020000
137#define UARTBAUD_RESYNCDIS 0x00010000
138#define UARTBAUD_LBKDIE 0x00008000
139#define UARTBAUD_RXEDGIE 0x00004000
140#define UARTBAUD_SBNS 0x00002000
141#define UARTBAUD_SBR 0x00000000
142#define UARTBAUD_SBR_MASK 0x1fff
143
144#define UARTSTAT_LBKDIF 0x80000000
145#define UARTSTAT_RXEDGIF 0x40000000
146#define UARTSTAT_MSBF 0x20000000
147#define UARTSTAT_RXINV 0x10000000
148#define UARTSTAT_RWUID 0x08000000
149#define UARTSTAT_BRK13 0x04000000
150#define UARTSTAT_LBKDE 0x02000000
151#define UARTSTAT_RAF 0x01000000
152#define UARTSTAT_TDRE 0x00800000
153#define UARTSTAT_TC 0x00400000
154#define UARTSTAT_RDRF 0x00200000
155#define UARTSTAT_IDLE 0x00100000
156#define UARTSTAT_OR 0x00080000
157#define UARTSTAT_NF 0x00040000
158#define UARTSTAT_FE 0x00020000
159#define UARTSTAT_PE 0x00010000
160#define UARTSTAT_MA1F 0x00008000
161#define UARTSTAT_M21F 0x00004000
162
163#define UARTCTRL_R8T9 0x80000000
164#define UARTCTRL_R9T8 0x40000000
165#define UARTCTRL_TXDIR 0x20000000
166#define UARTCTRL_TXINV 0x10000000
167#define UARTCTRL_ORIE 0x08000000
168#define UARTCTRL_NEIE 0x04000000
169#define UARTCTRL_FEIE 0x02000000
170#define UARTCTRL_PEIE 0x01000000
171#define UARTCTRL_TIE 0x00800000
172#define UARTCTRL_TCIE 0x00400000
173#define UARTCTRL_RIE 0x00200000
174#define UARTCTRL_ILIE 0x00100000
175#define UARTCTRL_TE 0x00080000
176#define UARTCTRL_RE 0x00040000
177#define UARTCTRL_RWU 0x00020000
178#define UARTCTRL_SBK 0x00010000
179#define UARTCTRL_MA1IE 0x00008000
180#define UARTCTRL_MA2IE 0x00004000
181#define UARTCTRL_IDLECFG 0x00000100
182#define UARTCTRL_LOOPS 0x00000080
183#define UARTCTRL_DOZEEN 0x00000040
184#define UARTCTRL_RSRC 0x00000020
185#define UARTCTRL_M 0x00000010
186#define UARTCTRL_WAKE 0x00000008
187#define UARTCTRL_ILT 0x00000004
188#define UARTCTRL_PE 0x00000002
189#define UARTCTRL_PT 0x00000001
190
191#define UARTDATA_NOISY 0x00008000
192#define UARTDATA_PARITYE 0x00004000
193#define UARTDATA_FRETSC 0x00002000
194#define UARTDATA_RXEMPT 0x00001000
195#define UARTDATA_IDLINE 0x00000800
196#define UARTDATA_MASK 0x3ff
197
198#define UARTMODIR_IREN 0x00020000
199#define UARTMODIR_TXCTSSRC 0x00000020
200#define UARTMODIR_TXCTSC 0x00000010
201#define UARTMODIR_RXRTSE 0x00000008
202#define UARTMODIR_TXRTSPOL 0x00000004
203#define UARTMODIR_TXRTSE 0x00000002
204#define UARTMODIR_TXCTSE 0x00000001
205
206#define UARTFIFO_TXEMPT 0x00800000
207#define UARTFIFO_RXEMPT 0x00400000
208#define UARTFIFO_TXOF 0x00020000
209#define UARTFIFO_RXUF 0x00010000
210#define UARTFIFO_TXFLUSH 0x00008000
211#define UARTFIFO_RXFLUSH 0x00004000
212#define UARTFIFO_TXOFE 0x00000200
213#define UARTFIFO_RXUFE 0x00000100
214#define UARTFIFO_TXFE 0x00000080
215#define UARTFIFO_FIFOSIZE_MASK 0x7
216#define UARTFIFO_TXSIZE_OFF 4
217#define UARTFIFO_RXFE 0x00000008
218#define UARTFIFO_RXSIZE_OFF 0
219
220#define UARTWATER_COUNT_MASK 0xff
221#define UARTWATER_TXCNT_OFF 8
222#define UARTWATER_RXCNT_OFF 24
223#define UARTWATER_WATER_MASK 0xff
224#define UARTWATER_TXWATER_OFF 0
225#define UARTWATER_RXWATER_OFF 16
226
f1cd8c87
YY		 227#define FSL_UART_RX_DMA_BUFFER_SIZE 64
228
c9e2e946
JL		 229#define DRIVER_NAME "fsl-lpuart"
230#define DEV_NAME "ttyLP"
231#define UART_NR 6
232
233struct lpuart_port {
234 struct uart_port port;
235 struct clk *clk;
236 unsigned int txfifo_size;
237 unsigned int rxfifo_size;
380c966c 238 bool lpuart32;
f1cd8c87 239
4a818c43
SA		 240 bool lpuart_dma_tx_use;
241 bool lpuart_dma_rx_use;
f1cd8c87
YY		 242 struct dma_chan *dma_tx_chan;
243 struct dma_chan *dma_rx_chan;
244 struct dma_async_tx_descriptor *dma_tx_desc;
245 struct dma_async_tx_descriptor *dma_rx_desc;
246 dma_addr_t dma_tx_buf_bus;
247 dma_addr_t dma_rx_buf_bus;
248 dma_cookie_t dma_tx_cookie;
249 dma_cookie_t dma_rx_cookie;
250 unsigned char *dma_tx_buf_virt;
251 unsigned char *dma_rx_buf_virt;
252 unsigned int dma_tx_bytes;
253 unsigned int dma_rx_bytes;
254 int dma_tx_in_progress;
255 int dma_rx_in_progress;
256 unsigned int dma_rx_timeout;
257 struct timer_list lpuart_timer;
c9e2e946
JL		 258};
259
260static struct of_device_id lpuart_dt_ids[] = {
261 {
262 .compatible = "fsl,vf610-lpuart",
263 },
380c966c
JL		 264 {
265 .compatible = "fsl,ls1021a-lpuart",
266 },
c9e2e946
JL		 267 { /* sentinel */ }
268};
269MODULE_DEVICE_TABLE(of, lpuart_dt_ids);
270
f1cd8c87
YY		 271/* Forward declare this for the dma callbacks*/
272static void lpuart_dma_tx_complete(void *arg);
273static void lpuart_dma_rx_complete(void *arg);
274
380c966c
JL		 275static u32 lpuart32_read(void __iomem *addr)
276{
277 return ioread32be(addr);
278}
279
280static void lpuart32_write(u32 val, void __iomem *addr)
281{
282 iowrite32be(val, addr);
283}
284
c9e2e946
JL		 285static void lpuart_stop_tx(struct uart_port *port)
286{
287 unsigned char temp;
288
289 temp = readb(port->membase + UARTCR2);
290 temp &= ~(UARTCR2_TIE | UARTCR2_TCIE);
291 writeb(temp, port->membase + UARTCR2);
292}
293
380c966c
JL		 294static void lpuart32_stop_tx(struct uart_port *port)
295{
296 unsigned long temp;
297
298 temp = lpuart32_read(port->membase + UARTCTRL);
299 temp &= ~(UARTCTRL_TIE | UARTCTRL_TCIE);
300 lpuart32_write(temp, port->membase + UARTCTRL);
301}
302
c9e2e946
JL		 303static void lpuart_stop_rx(struct uart_port *port)
304{
305 unsigned char temp;
306
307 temp = readb(port->membase + UARTCR2);
308 writeb(temp & ~UARTCR2_RE, port->membase + UARTCR2);
309}
310
380c966c
JL		 311static void lpuart32_stop_rx(struct uart_port *port)
312{
313 unsigned long temp;
314
315 temp = lpuart32_read(port->membase + UARTCTRL);
316 lpuart32_write(temp & ~UARTCTRL_RE, port->membase + UARTCTRL);
317}
318
f1cd8c87
YY		 319static void lpuart_copy_rx_to_tty(struct lpuart_port *sport,
320 struct tty_port *tty, int count)
321{
322 int copied;
323
324 sport->port.icount.rx += count;
325
326 if (!tty) {
327 dev_err(sport->port.dev, "No tty port\n");
328 return;
329 }
330
331 dma_sync_single_for_cpu(sport->port.dev, sport->dma_rx_buf_bus,
332 FSL_UART_RX_DMA_BUFFER_SIZE, DMA_FROM_DEVICE);
333 copied = tty_insert_flip_string(tty,
334 ((unsigned char *)(sport->dma_rx_buf_virt)), count);
335
336 if (copied != count) {
337 WARN_ON(1);
338 dev_err(sport->port.dev, "RxData copy to tty layer failed\n");
339 }
340
341 dma_sync_single_for_device(sport->port.dev, sport->dma_rx_buf_bus,
342 FSL_UART_RX_DMA_BUFFER_SIZE, DMA_TO_DEVICE);
343}
344
345static void lpuart_pio_tx(struct lpuart_port *sport)
346{
347 struct circ_buf *xmit = &sport->port.state->xmit;
348 unsigned long flags;
349
350 spin_lock_irqsave(&sport->port.lock, flags);
351
352 while (!uart_circ_empty(xmit) &&
353 readb(sport->port.membase + UARTTCFIFO) < sport->txfifo_size) {
354 writeb(xmit->buf[xmit->tail], sport->port.membase + UARTDR);
355 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
356 sport->port.icount.tx++;
357 }
358
359 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
360 uart_write_wakeup(&sport->port);
361
362 if (uart_circ_empty(xmit))
363 writeb(readb(sport->port.membase + UARTCR5) | UARTCR5_TDMAS,
364 sport->port.membase + UARTCR5);
365
366 spin_unlock_irqrestore(&sport->port.lock, flags);
367}
368
369static int lpuart_dma_tx(struct lpuart_port *sport, unsigned long count)
370{
371 struct circ_buf *xmit = &sport->port.state->xmit;
372 dma_addr_t tx_bus_addr;
373
374 dma_sync_single_for_device(sport->port.dev, sport->dma_tx_buf_bus,
375 UART_XMIT_SIZE, DMA_TO_DEVICE);
ed9891bf 376 sport->dma_tx_bytes = count & ~(sport->txfifo_size - 1);
f1cd8c87
YY		 377 tx_bus_addr = sport->dma_tx_buf_bus + xmit->tail;
378 sport->dma_tx_desc = dmaengine_prep_slave_single(sport->dma_tx_chan,
379 tx_bus_addr, sport->dma_tx_bytes,
380 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
381
382 if (!sport->dma_tx_desc) {
383 dev_err(sport->port.dev, "Not able to get desc for tx\n");
384 return -EIO;
385 }
386
387 sport->dma_tx_desc->callback = lpuart_dma_tx_complete;
388 sport->dma_tx_desc->callback_param = sport;
389 sport->dma_tx_in_progress = 1;
390 sport->dma_tx_cookie = dmaengine_submit(sport->dma_tx_desc);
391 dma_async_issue_pending(sport->dma_tx_chan);
392
393 return 0;
394}
395
396static void lpuart_prepare_tx(struct lpuart_port *sport)
397{
398 struct circ_buf *xmit = &sport->port.state->xmit;
399 unsigned long count = CIRC_CNT_TO_END(xmit->head,
400 xmit->tail, UART_XMIT_SIZE);
401
402 if (!count)
403 return;
404
ed9891bf 405 if (count < sport->txfifo_size)
f1cd8c87
YY		 406 writeb(readb(sport->port.membase + UARTCR5) & ~UARTCR5_TDMAS,
407 sport->port.membase + UARTCR5);
408 else {
409 writeb(readb(sport->port.membase + UARTCR5) | UARTCR5_TDMAS,
410 sport->port.membase + UARTCR5);
411 lpuart_dma_tx(sport, count);
412 }
413}
414
415static void lpuart_dma_tx_complete(void *arg)
416{
417 struct lpuart_port *sport = arg;
418 struct circ_buf *xmit = &sport->port.state->xmit;
419 unsigned long flags;
420
421 async_tx_ack(sport->dma_tx_desc);
422
423 spin_lock_irqsave(&sport->port.lock, flags);
424
425 xmit->tail = (xmit->tail + sport->dma_tx_bytes) & (UART_XMIT_SIZE - 1);
426 sport->dma_tx_in_progress = 0;
427
428 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
429 uart_write_wakeup(&sport->port);
430
431 lpuart_prepare_tx(sport);
432
433 spin_unlock_irqrestore(&sport->port.lock, flags);
434}
435
436static int lpuart_dma_rx(struct lpuart_port *sport)
437{
438 dma_sync_single_for_device(sport->port.dev, sport->dma_rx_buf_bus,
439 FSL_UART_RX_DMA_BUFFER_SIZE, DMA_TO_DEVICE);
440 sport->dma_rx_desc = dmaengine_prep_slave_single(sport->dma_rx_chan,
441 sport->dma_rx_buf_bus, FSL_UART_RX_DMA_BUFFER_SIZE,
442 DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT);
443
444 if (!sport->dma_rx_desc) {
445 dev_err(sport->port.dev, "Not able to get desc for rx\n");
446 return -EIO;
447 }
448
449 sport->dma_rx_desc->callback = lpuart_dma_rx_complete;
450 sport->dma_rx_desc->callback_param = sport;
451 sport->dma_rx_in_progress = 1;
452 sport->dma_rx_cookie = dmaengine_submit(sport->dma_rx_desc);
453 dma_async_issue_pending(sport->dma_rx_chan);
454
455 return 0;
456}
457
458static void lpuart_dma_rx_complete(void *arg)
459{
460 struct lpuart_port *sport = arg;
461 struct tty_port *port = &sport->port.state->port;
462 unsigned long flags;
463
464 async_tx_ack(sport->dma_rx_desc);
465
466 spin_lock_irqsave(&sport->port.lock, flags);
467
468 sport->dma_rx_in_progress = 0;
469 lpuart_copy_rx_to_tty(sport, port, FSL_UART_RX_DMA_BUFFER_SIZE);
470 tty_flip_buffer_push(port);
471 lpuart_dma_rx(sport);
472
473 spin_unlock_irqrestore(&sport->port.lock, flags);
474}
475
476static void lpuart_timer_func(unsigned long data)
477{
478 struct lpuart_port *sport = (struct lpuart_port *)data;
479 struct tty_port *port = &sport->port.state->port;
480 struct dma_tx_state state;
481 unsigned long flags;
482 unsigned char temp;
483 int count;
484
485 del_timer(&sport->lpuart_timer);
486 dmaengine_pause(sport->dma_rx_chan);
487 dmaengine_tx_status(sport->dma_rx_chan, sport->dma_rx_cookie, &state);
488 dmaengine_terminate_all(sport->dma_rx_chan);
489 count = FSL_UART_RX_DMA_BUFFER_SIZE - state.residue;
490 async_tx_ack(sport->dma_rx_desc);
491
492 spin_lock_irqsave(&sport->port.lock, flags);
493
494 sport->dma_rx_in_progress = 0;
495 lpuart_copy_rx_to_tty(sport, port, count);
496 tty_flip_buffer_push(port);
497 temp = readb(sport->port.membase + UARTCR5);
498 writeb(temp & ~UARTCR5_RDMAS, sport->port.membase + UARTCR5);
499
500 spin_unlock_irqrestore(&sport->port.lock, flags);
501}
502
503static inline void lpuart_prepare_rx(struct lpuart_port *sport)
504{
505 unsigned long flags;
506 unsigned char temp;
507
508 spin_lock_irqsave(&sport->port.lock, flags);
509
f1cd8c87
YY		 510 sport->lpuart_timer.expires = jiffies + sport->dma_rx_timeout;
511 add_timer(&sport->lpuart_timer);
512
513 lpuart_dma_rx(sport);
514 temp = readb(sport->port.membase + UARTCR5);
515 writeb(temp | UARTCR5_RDMAS, sport->port.membase + UARTCR5);
516
517 spin_unlock_irqrestore(&sport->port.lock, flags);
518}
519
c9e2e946
JL		 520static inline void lpuart_transmit_buffer(struct lpuart_port *sport)
521{
522 struct circ_buf *xmit = &sport->port.state->xmit;
523
524 while (!uart_circ_empty(xmit) &&
525 (readb(sport->port.membase + UARTTCFIFO) < sport->txfifo_size)) {
526 writeb(xmit->buf[xmit->tail], sport->port.membase + UARTDR);
527 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
528 sport->port.icount.tx++;
529 }
530
531 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
532 uart_write_wakeup(&sport->port);
533
534 if (uart_circ_empty(xmit))
535 lpuart_stop_tx(&sport->port);
536}
537
380c966c
JL		 538static inline void lpuart32_transmit_buffer(struct lpuart_port *sport)
539{
540 struct circ_buf *xmit = &sport->port.state->xmit;
541 unsigned long txcnt;
542
543 txcnt = lpuart32_read(sport->port.membase + UARTWATER);
544 txcnt = txcnt >> UARTWATER_TXCNT_OFF;
545 txcnt &= UARTWATER_COUNT_MASK;
546 while (!uart_circ_empty(xmit) && (txcnt < sport->txfifo_size)) {
547 lpuart32_write(xmit->buf[xmit->tail], sport->port.membase + UARTDATA);
548 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
549 sport->port.icount.tx++;
550 txcnt = lpuart32_read(sport->port.membase + UARTWATER);
551 txcnt = txcnt >> UARTWATER_TXCNT_OFF;
552 txcnt &= UARTWATER_COUNT_MASK;
553 }
554
555 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
556 uart_write_wakeup(&sport->port);
557
558 if (uart_circ_empty(xmit))
559 lpuart32_stop_tx(&sport->port);
560}
561
c9e2e946
JL		 562static void lpuart_start_tx(struct uart_port *port)
563{
f1cd8c87
YY		 564 struct lpuart_port *sport = container_of(port,
565 struct lpuart_port, port);
566 struct circ_buf *xmit = &sport->port.state->xmit;
c9e2e946
JL		 567 unsigned char temp;
568
569 temp = readb(port->membase + UARTCR2);
570 writeb(temp | UARTCR2_TIE, port->membase + UARTCR2);
571
4a818c43 572 if (sport->lpuart_dma_tx_use) {
f1cd8c87
YY		 573 if (!uart_circ_empty(xmit) && !sport->dma_tx_in_progress)
574 lpuart_prepare_tx(sport);
575 } else {
576 if (readb(port->membase + UARTSR1) & UARTSR1_TDRE)
577 lpuart_transmit_buffer(sport);
578 }
c9e2e946
JL		 579}
580
380c966c
JL		 581static void lpuart32_start_tx(struct uart_port *port)
582{
583 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
584 unsigned long temp;
585
586 temp = lpuart32_read(port->membase + UARTCTRL);
587 lpuart32_write(temp | UARTCTRL_TIE, port->membase + UARTCTRL);
588
589 if (lpuart32_read(port->membase + UARTSTAT) & UARTSTAT_TDRE)
590 lpuart32_transmit_buffer(sport);
591}
592
c9e2e946
JL		 593static irqreturn_t lpuart_txint(int irq, void *dev_id)
594{
595 struct lpuart_port *sport = dev_id;
596 struct circ_buf *xmit = &sport->port.state->xmit;
597 unsigned long flags;
598
599 spin_lock_irqsave(&sport->port.lock, flags);
600 if (sport->port.x_char) {
380c966c
JL		 601 if (sport->lpuart32)
602 lpuart32_write(sport->port.x_char, sport->port.membase + UARTDATA);
603 else
604 writeb(sport->port.x_char, sport->port.membase + UARTDR);
c9e2e946
JL		 605 goto out;
606 }
607
608 if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) {
380c966c
JL		 609 if (sport->lpuart32)
610 lpuart32_stop_tx(&sport->port);
611 else
612 lpuart_stop_tx(&sport->port);
c9e2e946
JL		 613 goto out;
614 }
615
380c966c
JL		 616 if (sport->lpuart32)
617 lpuart32_transmit_buffer(sport);
618 else
619 lpuart_transmit_buffer(sport);
c9e2e946
JL		 620
621 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
622 uart_write_wakeup(&sport->port);
623
624out:
625 spin_unlock_irqrestore(&sport->port.lock, flags);
626 return IRQ_HANDLED;
627}
628
629static irqreturn_t lpuart_rxint(int irq, void *dev_id)
630{
631 struct lpuart_port *sport = dev_id;
632 unsigned int flg, ignored = 0;
633 struct tty_port *port = &sport->port.state->port;
634 unsigned long flags;
635 unsigned char rx, sr;
636
637 spin_lock_irqsave(&sport->port.lock, flags);
638
639 while (!(readb(sport->port.membase + UARTSFIFO) & UARTSFIFO_RXEMPT)) {
640 flg = TTY_NORMAL;
641 sport->port.icount.rx++;
642 /*
643 * to clear the FE, OR, NF, FE, PE flags,
644 * read SR1 then read DR
645 */
646 sr = readb(sport->port.membase + UARTSR1);
647 rx = readb(sport->port.membase + UARTDR);
648
649 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx))
650 continue;
651
652 if (sr & (UARTSR1_PE | UARTSR1_OR | UARTSR1_FE)) {
653 if (sr & UARTSR1_PE)
654 sport->port.icount.parity++;
655 else if (sr & UARTSR1_FE)
656 sport->port.icount.frame++;
657
658 if (sr & UARTSR1_OR)
659 sport->port.icount.overrun++;
660
661 if (sr & sport->port.ignore_status_mask) {
662 if (++ignored > 100)
663 goto out;
664 continue;
665 }
666
667 sr &= sport->port.read_status_mask;
668
669 if (sr & UARTSR1_PE)
670 flg = TTY_PARITY;
671 else if (sr & UARTSR1_FE)
672 flg = TTY_FRAME;
673
674 if (sr & UARTSR1_OR)
675 flg = TTY_OVERRUN;
676
677#ifdef SUPPORT_SYSRQ
678 sport->port.sysrq = 0;
679#endif
680 }
681
682 tty_insert_flip_char(port, rx, flg);
683 }
684
685out:
686 spin_unlock_irqrestore(&sport->port.lock, flags);
687
688 tty_flip_buffer_push(port);
689 return IRQ_HANDLED;
690}
691
380c966c
JL		 692static irqreturn_t lpuart32_rxint(int irq, void *dev_id)
693{
694 struct lpuart_port *sport = dev_id;
695 unsigned int flg, ignored = 0;
696 struct tty_port *port = &sport->port.state->port;
697 unsigned long flags;
698 unsigned long rx, sr;
699
700 spin_lock_irqsave(&sport->port.lock, flags);
701
702 while (!(lpuart32_read(sport->port.membase + UARTFIFO) & UARTFIFO_RXEMPT)) {
703 flg = TTY_NORMAL;
704 sport->port.icount.rx++;
705 /*
706 * to clear the FE, OR, NF, FE, PE flags,
707 * read STAT then read DATA reg
708 */
709 sr = lpuart32_read(sport->port.membase + UARTSTAT);
710 rx = lpuart32_read(sport->port.membase + UARTDATA);
711 rx &= 0x3ff;
712
713 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx))
714 continue;
715
716 if (sr & (UARTSTAT_PE | UARTSTAT_OR | UARTSTAT_FE)) {
717 if (sr & UARTSTAT_PE)
718 sport->port.icount.parity++;
719 else if (sr & UARTSTAT_FE)
720 sport->port.icount.frame++;
721
722 if (sr & UARTSTAT_OR)
723 sport->port.icount.overrun++;
724
725 if (sr & sport->port.ignore_status_mask) {
726 if (++ignored > 100)
727 goto out;
728 continue;
729 }
730
731 sr &= sport->port.read_status_mask;
732
733 if (sr & UARTSTAT_PE)
734 flg = TTY_PARITY;
735 else if (sr & UARTSTAT_FE)
736 flg = TTY_FRAME;
737
738 if (sr & UARTSTAT_OR)
739 flg = TTY_OVERRUN;
740
741#ifdef SUPPORT_SYSRQ
742 sport->port.sysrq = 0;
743#endif
744 }
745
746 tty_insert_flip_char(port, rx, flg);
747 }
748
749out:
750 spin_unlock_irqrestore(&sport->port.lock, flags);
751
752 tty_flip_buffer_push(port);
753 return IRQ_HANDLED;
754}
755
c9e2e946
JL		 756static irqreturn_t lpuart_int(int irq, void *dev_id)
757{
758 struct lpuart_port *sport = dev_id;
5f1437f6 759 unsigned char sts, crdma;
c9e2e946
JL		 760
761 sts = readb(sport->port.membase + UARTSR1);
5f1437f6 762 crdma = readb(sport->port.membase + UARTCR5);
c9e2e946 763
5f1437f6 764 if (sts & UARTSR1_RDRF && !(crdma & UARTCR5_RDMAS)) {
4a818c43 765 if (sport->lpuart_dma_rx_use)
f1cd8c87
YY		 766 lpuart_prepare_rx(sport);
767 else
768 lpuart_rxint(irq, dev_id);
769 }
5f1437f6 770 if (sts & UARTSR1_TDRE && !(crdma & UARTCR5_TDMAS)) {
4a818c43 771 if (sport->lpuart_dma_tx_use)
f1cd8c87
YY		 772 lpuart_pio_tx(sport);
773 else
774 lpuart_txint(irq, dev_id);
775 }
c9e2e946
JL		 776
777 return IRQ_HANDLED;
778}
779
380c966c
JL		 780static irqreturn_t lpuart32_int(int irq, void *dev_id)
781{
782 struct lpuart_port *sport = dev_id;
783 unsigned long sts, rxcount;
784
785 sts = lpuart32_read(sport->port.membase + UARTSTAT);
786 rxcount = lpuart32_read(sport->port.membase + UARTWATER);
787 rxcount = rxcount >> UARTWATER_RXCNT_OFF;
788
789 if (sts & UARTSTAT_RDRF || rxcount > 0)
790 lpuart32_rxint(irq, dev_id);
791
792 if ((sts & UARTSTAT_TDRE) &&
793 !(lpuart32_read(sport->port.membase + UARTBAUD) & UARTBAUD_TDMAE))
794 lpuart_txint(irq, dev_id);
795
796 lpuart32_write(sts, sport->port.membase + UARTSTAT);
797 return IRQ_HANDLED;
798}
799
c9e2e946
JL		 800/* return TIOCSER_TEMT when transmitter is not busy */
801static unsigned int lpuart_tx_empty(struct uart_port *port)
802{
803 return (readb(port->membase + UARTSR1) & UARTSR1_TC) ?
804 TIOCSER_TEMT : 0;
805}
806
380c966c
JL		 807static unsigned int lpuart32_tx_empty(struct uart_port *port)
808{
809 return (lpuart32_read(port->membase + UARTSTAT) & UARTSTAT_TC) ?
810 TIOCSER_TEMT : 0;
811}
812
c9e2e946
JL		 813static unsigned int lpuart_get_mctrl(struct uart_port *port)
814{
815 unsigned int temp = 0;
816 unsigned char reg;
817
818 reg = readb(port->membase + UARTMODEM);
819 if (reg & UARTMODEM_TXCTSE)
820 temp |= TIOCM_CTS;
821
822 if (reg & UARTMODEM_RXRTSE)
823 temp |= TIOCM_RTS;
824
825 return temp;
826}
827
380c966c
JL		 828static unsigned int lpuart32_get_mctrl(struct uart_port *port)
829{
830 unsigned int temp = 0;
831 unsigned long reg;
832
833 reg = lpuart32_read(port->membase + UARTMODIR);
834 if (reg & UARTMODIR_TXCTSE)
835 temp |= TIOCM_CTS;
836
837 if (reg & UARTMODIR_RXRTSE)
838 temp |= TIOCM_RTS;
839
840 return temp;
841}
842
c9e2e946
JL		 843static void lpuart_set_mctrl(struct uart_port *port, unsigned int mctrl)
844{
845 unsigned char temp;
846
847 temp = readb(port->membase + UARTMODEM) &
848 ~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE);
849
850 if (mctrl & TIOCM_RTS)
851 temp |= UARTMODEM_RXRTSE;
852
853 if (mctrl & TIOCM_CTS)
854 temp |= UARTMODEM_TXCTSE;
855
856 writeb(temp, port->membase + UARTMODEM);
857}
858
380c966c
JL		 859static void lpuart32_set_mctrl(struct uart_port *port, unsigned int mctrl)
860{
861 unsigned long temp;
862
863 temp = lpuart32_read(port->membase + UARTMODIR) &
864 ~(UARTMODIR_RXRTSE | UARTMODIR_TXCTSE);
865
866 if (mctrl & TIOCM_RTS)
867 temp |= UARTMODIR_RXRTSE;
868
869 if (mctrl & TIOCM_CTS)
870 temp |= UARTMODIR_TXCTSE;
871
872 lpuart32_write(temp, port->membase + UARTMODIR);
873}
874
c9e2e946
JL		 875static void lpuart_break_ctl(struct uart_port *port, int break_state)
876{
877 unsigned char temp;
878
879 temp = readb(port->membase + UARTCR2) & ~UARTCR2_SBK;
880
881 if (break_state != 0)
882 temp |= UARTCR2_SBK;
883
884 writeb(temp, port->membase + UARTCR2);
885}
886
380c966c
JL		 887static void lpuart32_break_ctl(struct uart_port *port, int break_state)
888{
889 unsigned long temp;
890
891 temp = lpuart32_read(port->membase + UARTCTRL) & ~UARTCTRL_SBK;
892
893 if (break_state != 0)
894 temp |= UARTCTRL_SBK;
895
896 lpuart32_write(temp, port->membase + UARTCTRL);
897}
898
c9e2e946
JL		 899static void lpuart_setup_watermark(struct lpuart_port *sport)
900{
901 unsigned char val, cr2;
bc764b8f 902 unsigned char cr2_saved;
c9e2e946
JL		 903
904 cr2 = readb(sport->port.membase + UARTCR2);
bc764b8f 905 cr2_saved = cr2;
c9e2e946
JL		 906 cr2 &= ~(UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_TE |
907 UARTCR2_RIE | UARTCR2_RE);
908 writeb(cr2, sport->port.membase + UARTCR2);
909
c9e2e946 910 val = readb(sport->port.membase + UARTPFIFO);
c9e2e946
JL		 911 writeb(val | UARTPFIFO_TXFE | UARTPFIFO_RXFE,
912 sport->port.membase + UARTPFIFO);
913
914 /* flush Tx and Rx FIFO */
915 writeb(UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH,
916 sport->port.membase + UARTCFIFO);
917
f1cd8c87 918 writeb(0, sport->port.membase + UARTTWFIFO);
c9e2e946 919 writeb(1, sport->port.membase + UARTRWFIFO);
bc764b8f
SG		 920
921 /* Restore cr2 */
922 writeb(cr2_saved, sport->port.membase + UARTCR2);
c9e2e946
JL		 923}
924
380c966c
JL		 925static void lpuart32_setup_watermark(struct lpuart_port *sport)
926{
927 unsigned long val, ctrl;
928 unsigned long ctrl_saved;
929
930 ctrl = lpuart32_read(sport->port.membase + UARTCTRL);
931 ctrl_saved = ctrl;
932 ctrl &= ~(UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_TE |
933 UARTCTRL_RIE | UARTCTRL_RE);
934 lpuart32_write(ctrl, sport->port.membase + UARTCTRL);
935
936 /* enable FIFO mode */
937 val = lpuart32_read(sport->port.membase + UARTFIFO);
938 val |= UARTFIFO_TXFE | UARTFIFO_RXFE;
939 val |= UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH;
940 lpuart32_write(val, sport->port.membase + UARTFIFO);
941
942 /* set the watermark */
943 val = (0x1 << UARTWATER_RXWATER_OFF) | (0x0 << UARTWATER_TXWATER_OFF);
944 lpuart32_write(val, sport->port.membase + UARTWATER);
945
946 /* Restore cr2 */
947 lpuart32_write(ctrl_saved, sport->port.membase + UARTCTRL);
948}
949
f1cd8c87
YY		 950static int lpuart_dma_tx_request(struct uart_port *port)
951{
952 struct lpuart_port *sport = container_of(port,
953 struct lpuart_port, port);
f1cd8c87
YY		 954 struct dma_slave_config dma_tx_sconfig;
955 dma_addr_t dma_bus;
956 unsigned char *dma_buf;
957 int ret;
958
4a818c43 959 dma_bus = dma_map_single(sport->dma_tx_chan->device->dev,
f1cd8c87
YY		 960 sport->port.state->xmit.buf,
961 UART_XMIT_SIZE, DMA_TO_DEVICE);
962
4a818c43 963 if (dma_mapping_error(sport->dma_tx_chan->device->dev, dma_bus)) {
f1cd8c87 964 dev_err(sport->port.dev, "dma_map_single tx failed\n");
f1cd8c87
YY		 965 return -ENOMEM;
966 }
967
968 dma_buf = sport->port.state->xmit.buf;
969 dma_tx_sconfig.dst_addr = sport->port.mapbase + UARTDR;
970 dma_tx_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
ed9891bf 971 dma_tx_sconfig.dst_maxburst = sport->txfifo_size;
f1cd8c87 972 dma_tx_sconfig.direction = DMA_MEM_TO_DEV;
4a818c43 973 ret = dmaengine_slave_config(sport->dma_tx_chan, &dma_tx_sconfig);
f1cd8c87
YY		 974
975 if (ret < 0) {
976 dev_err(sport->port.dev,
977 "Dma slave config failed, err = %d\n", ret);
f1cd8c87
YY		 978 return ret;
979 }
980
f1cd8c87
YY		 981 sport->dma_tx_buf_virt = dma_buf;
982 sport->dma_tx_buf_bus = dma_bus;
983 sport->dma_tx_in_progress = 0;
984
985 return 0;
986}
987
988static int lpuart_dma_rx_request(struct uart_port *port)
989{
990 struct lpuart_port *sport = container_of(port,
991 struct lpuart_port, port);
f1cd8c87
YY		 992 struct dma_slave_config dma_rx_sconfig;
993 dma_addr_t dma_bus;
994 unsigned char *dma_buf;
995 int ret;
996
f1cd8c87
YY		 997 dma_buf = devm_kzalloc(sport->port.dev,
998 FSL_UART_RX_DMA_BUFFER_SIZE, GFP_KERNEL);
999
1000 if (!dma_buf) {
1001 dev_err(sport->port.dev, "Dma rx alloc failed\n");
f1cd8c87
YY		 1002 return -ENOMEM;
1003 }
1004
4a818c43 1005 dma_bus = dma_map_single(sport->dma_rx_chan->device->dev, dma_buf,
f1cd8c87
YY		 1006 FSL_UART_RX_DMA_BUFFER_SIZE, DMA_FROM_DEVICE);
1007
4a818c43 1008 if (dma_mapping_error(sport->dma_rx_chan->device->dev, dma_bus)) {
f1cd8c87 1009 dev_err(sport->port.dev, "dma_map_single rx failed\n");
f1cd8c87
YY		 1010 return -ENOMEM;
1011 }
1012
1013 dma_rx_sconfig.src_addr = sport->port.mapbase + UARTDR;
1014 dma_rx_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1015 dma_rx_sconfig.src_maxburst = 1;
1016 dma_rx_sconfig.direction = DMA_DEV_TO_MEM;
4a818c43 1017 ret = dmaengine_slave_config(sport->dma_rx_chan, &dma_rx_sconfig);
f1cd8c87
YY		 1018
1019 if (ret < 0) {
1020 dev_err(sport->port.dev,
1021 "Dma slave config failed, err = %d\n", ret);
f1cd8c87
YY		 1022 return ret;
1023 }
1024
f1cd8c87
YY		 1025 sport->dma_rx_buf_virt = dma_buf;
1026 sport->dma_rx_buf_bus = dma_bus;
1027 sport->dma_rx_in_progress = 0;
1028
f1cd8c87
YY		 1029 return 0;
1030}
1031
1032static void lpuart_dma_tx_free(struct uart_port *port)
1033{
1034 struct lpuart_port *sport = container_of(port,
1035 struct lpuart_port, port);
f1cd8c87
YY		 1036
1037 dma_unmap_single(sport->port.dev, sport->dma_tx_buf_bus,
1038 UART_XMIT_SIZE, DMA_TO_DEVICE);
4a818c43 1039
f1cd8c87
YY		 1040 sport->dma_tx_buf_bus = 0;
1041 sport->dma_tx_buf_virt = NULL;
f1cd8c87
YY		 1042}
1043
1044static void lpuart_dma_rx_free(struct uart_port *port)
1045{
1046 struct lpuart_port *sport = container_of(port,
1047 struct lpuart_port, port);
f1cd8c87
YY		 1048
1049 dma_unmap_single(sport->port.dev, sport->dma_rx_buf_bus,
1050 FSL_UART_RX_DMA_BUFFER_SIZE, DMA_FROM_DEVICE);
1051
f1cd8c87
YY		 1052 sport->dma_rx_buf_bus = 0;
1053 sport->dma_rx_buf_virt = NULL;
f1cd8c87
YY		 1054}
1055
c9e2e946
JL		 1056static int lpuart_startup(struct uart_port *port)
1057{
1058 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1059 int ret;
1060 unsigned long flags;
1061 unsigned char temp;
1062
ed9891bf
SA		 1063 /* determine FIFO size and enable FIFO mode */
1064 temp = readb(sport->port.membase + UARTPFIFO);
1065
1066 sport->txfifo_size = 0x1 << (((temp >> UARTPFIFO_TXSIZE_OFF) &
1067 UARTPFIFO_FIFOSIZE_MASK) + 1);
1068
1069 sport->rxfifo_size = 0x1 << (((temp >> UARTPFIFO_RXSIZE_OFF) &
1070 UARTPFIFO_FIFOSIZE_MASK) + 1);
1071
4a818c43
SA		 1072 if (sport->dma_rx_chan && !lpuart_dma_rx_request(port)) {
1073 sport->lpuart_dma_rx_use = true;
4a8588a1
SA		 1074 setup_timer(&sport->lpuart_timer, lpuart_timer_func,
1075 (unsigned long)sport);
4a818c43
SA		 1076 } else
1077 sport->lpuart_dma_rx_use = false;
1078
1079
1080 if (sport->dma_tx_chan && !lpuart_dma_tx_request(port)) {
1081 sport->lpuart_dma_tx_use = true;
f1cd8c87 1082 temp = readb(port->membase + UARTCR5);
5f1437f6 1083 temp &= ~UARTCR5_RDMAS;
f1cd8c87 1084 writeb(temp | UARTCR5_TDMAS, port->membase + UARTCR5);
4a818c43
SA		 1085 } else
1086 sport->lpuart_dma_tx_use = false;
f1cd8c87 1087
c9e2e946
JL		 1088 ret = devm_request_irq(port->dev, port->irq, lpuart_int, 0,
1089 DRIVER_NAME, sport);
1090 if (ret)
1091 return ret;
1092
1093 spin_lock_irqsave(&sport->port.lock, flags);
1094
1095 lpuart_setup_watermark(sport);
1096
1097 temp = readb(sport->port.membase + UARTCR2);
1098 temp |= (UARTCR2_RIE | UARTCR2_TIE | UARTCR2_RE | UARTCR2_TE);
1099 writeb(temp, sport->port.membase + UARTCR2);
1100
1101 spin_unlock_irqrestore(&sport->port.lock, flags);
1102 return 0;
1103}
1104
380c966c
JL		 1105static int lpuart32_startup(struct uart_port *port)
1106{
1107 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1108 int ret;
1109 unsigned long flags;
1110 unsigned long temp;
1111
1112 /* determine FIFO size */
1113 temp = lpuart32_read(sport->port.membase + UARTFIFO);
1114
1115 sport->txfifo_size = 0x1 << (((temp >> UARTFIFO_TXSIZE_OFF) &
1116 UARTFIFO_FIFOSIZE_MASK) - 1);
1117
1118 sport->rxfifo_size = 0x1 << (((temp >> UARTFIFO_RXSIZE_OFF) &
1119 UARTFIFO_FIFOSIZE_MASK) - 1);
1120
1121 ret = devm_request_irq(port->dev, port->irq, lpuart32_int, 0,
1122 DRIVER_NAME, sport);
1123 if (ret)
1124 return ret;
1125
1126 spin_lock_irqsave(&sport->port.lock, flags);
1127
1128 lpuart32_setup_watermark(sport);
1129
1130 temp = lpuart32_read(sport->port.membase + UARTCTRL);
1131 temp |= (UARTCTRL_RIE | UARTCTRL_TIE | UARTCTRL_RE | UARTCTRL_TE);
1132 temp |= UARTCTRL_ILIE;
1133 lpuart32_write(temp, sport->port.membase + UARTCTRL);
1134
1135 spin_unlock_irqrestore(&sport->port.lock, flags);
1136 return 0;
1137}
1138
c9e2e946
JL		 1139static void lpuart_shutdown(struct uart_port *port)
1140{
1141 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1142 unsigned char temp;
1143 unsigned long flags;
1144
1145 spin_lock_irqsave(&port->lock, flags);
1146
1147 /* disable Rx/Tx and interrupts */
1148 temp = readb(port->membase + UARTCR2);
1149 temp &= ~(UARTCR2_TE | UARTCR2_RE |
1150 UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_RIE);
1151 writeb(temp, port->membase + UARTCR2);
1152
1153 spin_unlock_irqrestore(&port->lock, flags);
1154
1155 devm_free_irq(port->dev, port->irq, sport);
f1cd8c87 1156
4a818c43
SA		 1157 if (sport->lpuart_dma_rx_use) {
1158 lpuart_dma_rx_free(&sport->port);
4a8588a1 1159 del_timer_sync(&sport->lpuart_timer);
f1cd8c87 1160 }
4a818c43
SA		 1161
1162 if (sport->lpuart_dma_tx_use)
1163 lpuart_dma_tx_free(&sport->port);
c9e2e946
JL		 1164}
1165
380c966c
JL		 1166static void lpuart32_shutdown(struct uart_port *port)
1167{
1168 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1169 unsigned long temp;
1170 unsigned long flags;
1171
1172 spin_lock_irqsave(&port->lock, flags);
1173
1174 /* disable Rx/Tx and interrupts */
1175 temp = lpuart32_read(port->membase + UARTCTRL);
1176 temp &= ~(UARTCTRL_TE | UARTCTRL_RE |
1177 UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_RIE);
1178 lpuart32_write(temp, port->membase + UARTCTRL);
1179
1180 spin_unlock_irqrestore(&port->lock, flags);
1181
1182 devm_free_irq(port->dev, port->irq, sport);
1183}
1184
c9e2e946
JL		 1185static void
1186lpuart_set_termios(struct uart_port *port, struct ktermios *termios,
1187 struct ktermios *old)
1188{
1189 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1190 unsigned long flags;
1191 unsigned char cr1, old_cr1, old_cr2, cr4, bdh, modem;
1192 unsigned int baud;
1193 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
1194 unsigned int sbr, brfa;
1195
1196 cr1 = old_cr1 = readb(sport->port.membase + UARTCR1);
1197 old_cr2 = readb(sport->port.membase + UARTCR2);
1198 cr4 = readb(sport->port.membase + UARTCR4);
1199 bdh = readb(sport->port.membase + UARTBDH);
1200 modem = readb(sport->port.membase + UARTMODEM);
1201 /*
1202 * only support CS8 and CS7, and for CS7 must enable PE.
1203 * supported mode:
1204 * - (7,e/o,1)
1205 * - (8,n,1)
1206 * - (8,m/s,1)
1207 * - (8,e/o,1)
1208 */
1209 while ((termios->c_cflag & CSIZE) != CS8 &&
1210 (termios->c_cflag & CSIZE) != CS7) {
1211 termios->c_cflag &= ~CSIZE;
1212 termios->c_cflag |= old_csize;
1213 old_csize = CS8;
1214 }
1215
1216 if ((termios->c_cflag & CSIZE) == CS8 ||
1217 (termios->c_cflag & CSIZE) == CS7)
1218 cr1 = old_cr1 & ~UARTCR1_M;
1219
1220 if (termios->c_cflag & CMSPAR) {
1221 if ((termios->c_cflag & CSIZE) != CS8) {
1222 termios->c_cflag &= ~CSIZE;
1223 termios->c_cflag |= CS8;
1224 }
1225 cr1 |= UARTCR1_M;
1226 }
1227
1228 if (termios->c_cflag & CRTSCTS) {
1229 modem |= (UARTMODEM_RXRTSE | UARTMODEM_TXCTSE);
1230 } else {
1231 termios->c_cflag &= ~CRTSCTS;
1232 modem &= ~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE);
1233 }
1234
1235 if (termios->c_cflag & CSTOPB)
1236 termios->c_cflag &= ~CSTOPB;
1237
1238 /* parity must be enabled when CS7 to match 8-bits format */
1239 if ((termios->c_cflag & CSIZE) == CS7)
1240 termios->c_cflag |= PARENB;
1241
1242 if ((termios->c_cflag & PARENB)) {
1243 if (termios->c_cflag & CMSPAR) {
1244 cr1 &= ~UARTCR1_PE;
1245 cr1 |= UARTCR1_M;
1246 } else {
1247 cr1 |= UARTCR1_PE;
1248 if ((termios->c_cflag & CSIZE) == CS8)
1249 cr1 |= UARTCR1_M;
1250 if (termios->c_cflag & PARODD)
1251 cr1 |= UARTCR1_PT;
1252 else
1253 cr1 &= ~UARTCR1_PT;
1254 }
1255 }
1256
1257 /* ask the core to calculate the divisor */
1258 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
1259
1260 spin_lock_irqsave(&sport->port.lock, flags);
1261
1262 sport->port.read_status_mask = 0;
1263 if (termios->c_iflag & INPCK)
1264 sport->port.read_status_mask |= (UARTSR1_FE | UARTSR1_PE);
ef8b9ddc 1265 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
c9e2e946
JL		 1266 sport->port.read_status_mask |= UARTSR1_FE;
1267
1268 /* characters to ignore */
1269 sport->port.ignore_status_mask = 0;
1270 if (termios->c_iflag & IGNPAR)
1271 sport->port.ignore_status_mask |= UARTSR1_PE;
1272 if (termios->c_iflag & IGNBRK) {
1273 sport->port.ignore_status_mask |= UARTSR1_FE;
1274 /*
1275 * if we're ignoring parity and break indicators,
1276 * ignore overruns too (for real raw support).
1277 */
1278 if (termios->c_iflag & IGNPAR)
1279 sport->port.ignore_status_mask |= UARTSR1_OR;
1280 }
1281
1282 /* update the per-port timeout */
1283 uart_update_timeout(port, termios->c_cflag, baud);
1284
4a818c43 1285 if (sport->lpuart_dma_rx_use) {
90abef91
SA		 1286 /* Calculate delay for 1.5 DMA buffers */
1287 sport->dma_rx_timeout = (sport->port.timeout - HZ / 50) *
1288 FSL_UART_RX_DMA_BUFFER_SIZE * 3 /
1289 sport->rxfifo_size / 2;
1290 dev_dbg(port->dev, "DMA Rx t-out %ums, tty t-out %u jiffies\n",
1291 sport->dma_rx_timeout * 1000 / HZ, sport->port.timeout);
1292 if (sport->dma_rx_timeout < msecs_to_jiffies(20))
1293 sport->dma_rx_timeout = msecs_to_jiffies(20);
1294 }
1295
c9e2e946
JL		 1296 /* wait transmit engin complete */
1297 while (!(readb(sport->port.membase + UARTSR1) & UARTSR1_TC))
1298 barrier();
1299
1300 /* disable transmit and receive */
1301 writeb(old_cr2 & ~(UARTCR2_TE | UARTCR2_RE),
1302 sport->port.membase + UARTCR2);
1303
1304 sbr = sport->port.uartclk / (16 * baud);
1305 brfa = ((sport->port.uartclk - (16 * sbr * baud)) * 2) / baud;
1306 bdh &= ~UARTBDH_SBR_MASK;
1307 bdh |= (sbr >> 8) & 0x1F;
1308 cr4 &= ~UARTCR4_BRFA_MASK;
1309 brfa &= UARTCR4_BRFA_MASK;
1310 writeb(cr4 | brfa, sport->port.membase + UARTCR4);
1311 writeb(bdh, sport->port.membase + UARTBDH);
1312 writeb(sbr & 0xFF, sport->port.membase + UARTBDL);
1313 writeb(cr1, sport->port.membase + UARTCR1);
1314 writeb(modem, sport->port.membase + UARTMODEM);
1315
1316 /* restore control register */
1317 writeb(old_cr2, sport->port.membase + UARTCR2);
1318
1319 spin_unlock_irqrestore(&sport->port.lock, flags);
1320}
1321
380c966c
JL		 1322static void
1323lpuart32_set_termios(struct uart_port *port, struct ktermios *termios,
1324 struct ktermios *old)
1325{
1326 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1327 unsigned long flags;
1328 unsigned long ctrl, old_ctrl, bd, modem;
1329 unsigned int baud;
1330 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
1331 unsigned int sbr;
1332
1333 ctrl = old_ctrl = lpuart32_read(sport->port.membase + UARTCTRL);
1334 bd = lpuart32_read(sport->port.membase + UARTBAUD);
1335 modem = lpuart32_read(sport->port.membase + UARTMODIR);
1336 /*
1337 * only support CS8 and CS7, and for CS7 must enable PE.
1338 * supported mode:
1339 * - (7,e/o,1)
1340 * - (8,n,1)
1341 * - (8,m/s,1)
1342 * - (8,e/o,1)
1343 */
1344 while ((termios->c_cflag & CSIZE) != CS8 &&
1345 (termios->c_cflag & CSIZE) != CS7) {
1346 termios->c_cflag &= ~CSIZE;
1347 termios->c_cflag |= old_csize;
1348 old_csize = CS8;
1349 }
1350
1351 if ((termios->c_cflag & CSIZE) == CS8 ||
1352 (termios->c_cflag & CSIZE) == CS7)
1353 ctrl = old_ctrl & ~UARTCTRL_M;
1354
1355 if (termios->c_cflag & CMSPAR) {
1356 if ((termios->c_cflag & CSIZE) != CS8) {
1357 termios->c_cflag &= ~CSIZE;
1358 termios->c_cflag |= CS8;
1359 }
1360 ctrl |= UARTCTRL_M;
1361 }
1362
1363 if (termios->c_cflag & CRTSCTS) {
1364 modem |= (UARTMODEM_RXRTSE | UARTMODEM_TXCTSE);
1365 } else {
1366 termios->c_cflag &= ~CRTSCTS;
1367 modem &= ~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE);
1368 }
1369
1370 if (termios->c_cflag & CSTOPB)
1371 termios->c_cflag &= ~CSTOPB;
1372
1373 /* parity must be enabled when CS7 to match 8-bits format */
1374 if ((termios->c_cflag & CSIZE) == CS7)
1375 termios->c_cflag |= PARENB;
1376
1377 if ((termios->c_cflag & PARENB)) {
1378 if (termios->c_cflag & CMSPAR) {
1379 ctrl &= ~UARTCTRL_PE;
1380 ctrl |= UARTCTRL_M;
1381 } else {
1382 ctrl |= UARTCR1_PE;
1383 if ((termios->c_cflag & CSIZE) == CS8)
1384 ctrl |= UARTCTRL_M;
1385 if (termios->c_cflag & PARODD)
1386 ctrl |= UARTCTRL_PT;
1387 else
1388 ctrl &= ~UARTCTRL_PT;
1389 }
1390 }
1391
1392 /* ask the core to calculate the divisor */
1393 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
1394
1395 spin_lock_irqsave(&sport->port.lock, flags);
1396
1397 sport->port.read_status_mask = 0;
1398 if (termios->c_iflag & INPCK)
1399 sport->port.read_status_mask |= (UARTSTAT_FE | UARTSTAT_PE);
1400 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
1401 sport->port.read_status_mask |= UARTSTAT_FE;
1402
1403 /* characters to ignore */
1404 sport->port.ignore_status_mask = 0;
1405 if (termios->c_iflag & IGNPAR)
1406 sport->port.ignore_status_mask |= UARTSTAT_PE;
1407 if (termios->c_iflag & IGNBRK) {
1408 sport->port.ignore_status_mask |= UARTSTAT_FE;
1409 /*
1410 * if we're ignoring parity and break indicators,
1411 * ignore overruns too (for real raw support).
1412 */
1413 if (termios->c_iflag & IGNPAR)
1414 sport->port.ignore_status_mask |= UARTSTAT_OR;
1415 }
1416
1417 /* update the per-port timeout */
1418 uart_update_timeout(port, termios->c_cflag, baud);
1419
1420 /* wait transmit engin complete */
1421 while (!(lpuart32_read(sport->port.membase + UARTSTAT) & UARTSTAT_TC))
1422 barrier();
1423
1424 /* disable transmit and receive */
1425 lpuart32_write(old_ctrl & ~(UARTCTRL_TE | UARTCTRL_RE),
1426 sport->port.membase + UARTCTRL);
1427
1428 sbr = sport->port.uartclk / (16 * baud);
1429 bd &= ~UARTBAUD_SBR_MASK;
1430 bd |= sbr & UARTBAUD_SBR_MASK;
1431 bd |= UARTBAUD_BOTHEDGE;
1432 bd &= ~(UARTBAUD_TDMAE | UARTBAUD_RDMAE);
1433 lpuart32_write(bd, sport->port.membase + UARTBAUD);
1434 lpuart32_write(modem, sport->port.membase + UARTMODIR);
1435 lpuart32_write(ctrl, sport->port.membase + UARTCTRL);
1436 /* restore control register */
1437
1438 spin_unlock_irqrestore(&sport->port.lock, flags);
1439}
1440
c9e2e946
JL		 1441static const char *lpuart_type(struct uart_port *port)
1442{
1443 return "FSL_LPUART";
1444}
1445
1446static void lpuart_release_port(struct uart_port *port)
1447{
1448 /* nothing to do */
1449}
1450
1451static int lpuart_request_port(struct uart_port *port)
1452{
1453 return 0;
1454}
1455
1456/* configure/autoconfigure the port */
1457static void lpuart_config_port(struct uart_port *port, int flags)
1458{
1459 if (flags & UART_CONFIG_TYPE)
1460 port->type = PORT_LPUART;
1461}
1462
1463static int lpuart_verify_port(struct uart_port *port, struct serial_struct *ser)
1464{
1465 int ret = 0;
1466
1467 if (ser->type != PORT_UNKNOWN && ser->type != PORT_LPUART)
1468 ret = -EINVAL;
1469 if (port->irq != ser->irq)
1470 ret = -EINVAL;
1471 if (ser->io_type != UPIO_MEM)
1472 ret = -EINVAL;
1473 if (port->uartclk / 16 != ser->baud_base)
1474 ret = -EINVAL;
1475 if (port->iobase != ser->port)
1476 ret = -EINVAL;
1477 if (ser->hub6 != 0)
1478 ret = -EINVAL;
1479 return ret;
1480}
1481
1482static struct uart_ops lpuart_pops = {
1483 .tx_empty = lpuart_tx_empty,
1484 .set_mctrl = lpuart_set_mctrl,
1485 .get_mctrl = lpuart_get_mctrl,
1486 .stop_tx = lpuart_stop_tx,
1487 .start_tx = lpuart_start_tx,
1488 .stop_rx = lpuart_stop_rx,
c9e2e946
JL		 1489 .break_ctl = lpuart_break_ctl,
1490 .startup = lpuart_startup,
1491 .shutdown = lpuart_shutdown,
1492 .set_termios = lpuart_set_termios,
1493 .type = lpuart_type,
1494 .request_port = lpuart_request_port,
1495 .release_port = lpuart_release_port,
1496 .config_port = lpuart_config_port,
1497 .verify_port = lpuart_verify_port,
1498};
1499
380c966c
JL		 1500static struct uart_ops lpuart32_pops = {
1501 .tx_empty = lpuart32_tx_empty,
1502 .set_mctrl = lpuart32_set_mctrl,
1503 .get_mctrl = lpuart32_get_mctrl,
1504 .stop_tx = lpuart32_stop_tx,
1505 .start_tx = lpuart32_start_tx,
1506 .stop_rx = lpuart32_stop_rx,
1507 .break_ctl = lpuart32_break_ctl,
1508 .startup = lpuart32_startup,
1509 .shutdown = lpuart32_shutdown,
1510 .set_termios = lpuart32_set_termios,
1511 .type = lpuart_type,
1512 .request_port = lpuart_request_port,
1513 .release_port = lpuart_release_port,
1514 .config_port = lpuart_config_port,
1515 .verify_port = lpuart_verify_port,
1516};
1517
c9e2e946
JL		 1518static struct lpuart_port *lpuart_ports[UART_NR];
1519
1520#ifdef CONFIG_SERIAL_FSL_LPUART_CONSOLE
1521static void lpuart_console_putchar(struct uart_port *port, int ch)
1522{
1523 while (!(readb(port->membase + UARTSR1) & UARTSR1_TDRE))
1524 barrier();
1525
1526 writeb(ch, port->membase + UARTDR);
1527}
1528
380c966c
JL		 1529static void lpuart32_console_putchar(struct uart_port *port, int ch)
1530{
1531 while (!(lpuart32_read(port->membase + UARTSTAT) & UARTSTAT_TDRE))
1532 barrier();
1533
1534 lpuart32_write(ch, port->membase + UARTDATA);
1535}
1536
c9e2e946
JL		 1537static void
1538lpuart_console_write(struct console *co, const char *s, unsigned int count)
1539{
1540 struct lpuart_port *sport = lpuart_ports[co->index];
1541 unsigned char old_cr2, cr2;
1542
1543 /* first save CR2 and then disable interrupts */
1544 cr2 = old_cr2 = readb(sport->port.membase + UARTCR2);
1545 cr2 |= (UARTCR2_TE | UARTCR2_RE);
1546 cr2 &= ~(UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_RIE);
1547 writeb(cr2, sport->port.membase + UARTCR2);
1548
1549 uart_console_write(&sport->port, s, count, lpuart_console_putchar);
1550
1551 /* wait for transmitter finish complete and restore CR2 */
1552 while (!(readb(sport->port.membase + UARTSR1) & UARTSR1_TC))
1553 barrier();
1554
1555 writeb(old_cr2, sport->port.membase + UARTCR2);
1556}
1557
380c966c
JL		 1558static void
1559lpuart32_console_write(struct console *co, const char *s, unsigned int count)
1560{
1561 struct lpuart_port *sport = lpuart_ports[co->index];
1562 unsigned long old_cr, cr;
1563
1564 /* first save CR2 and then disable interrupts */
1565 cr = old_cr = lpuart32_read(sport->port.membase + UARTCTRL);
1566 cr |= (UARTCTRL_TE | UARTCTRL_RE);
1567 cr &= ~(UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_RIE);
1568 lpuart32_write(cr, sport->port.membase + UARTCTRL);
1569
1570 uart_console_write(&sport->port, s, count, lpuart32_console_putchar);
1571
1572 /* wait for transmitter finish complete and restore CR2 */
1573 while (!(lpuart32_read(sport->port.membase + UARTSTAT) & UARTSTAT_TC))
1574 barrier();
1575
1576 lpuart32_write(old_cr, sport->port.membase + UARTCTRL);
1577}
1578
c9e2e946
JL		 1579/*
1580 * if the port was already initialised (eg, by a boot loader),
1581 * try to determine the current setup.
1582 */
1583static void __init
1584lpuart_console_get_options(struct lpuart_port *sport, int *baud,
1585 int *parity, int *bits)
1586{
1587 unsigned char cr, bdh, bdl, brfa;
1588 unsigned int sbr, uartclk, baud_raw;
1589
1590 cr = readb(sport->port.membase + UARTCR2);
1591 cr &= UARTCR2_TE | UARTCR2_RE;
1592 if (!cr)
1593 return;
1594
1595 /* ok, the port was enabled */
1596
1597 cr = readb(sport->port.membase + UARTCR1);
1598
1599 *parity = 'n';
1600 if (cr & UARTCR1_PE) {
1601 if (cr & UARTCR1_PT)
1602 *parity = 'o';
1603 else
1604 *parity = 'e';
1605 }
1606
1607 if (cr & UARTCR1_M)
1608 *bits = 9;
1609 else
1610 *bits = 8;
1611
1612 bdh = readb(sport->port.membase + UARTBDH);
1613 bdh &= UARTBDH_SBR_MASK;
1614 bdl = readb(sport->port.membase + UARTBDL);
1615 sbr = bdh;
1616 sbr <<= 8;
1617 sbr |= bdl;
1618 brfa = readb(sport->port.membase + UARTCR4);
1619 brfa &= UARTCR4_BRFA_MASK;
1620
1621 uartclk = clk_get_rate(sport->clk);
1622 /*
1623 * baud = mod_clk/(16*(sbr[13]+(brfa)/32)
1624 */
1625 baud_raw = uartclk / (16 * (sbr + brfa / 32));
1626
1627 if (*baud != baud_raw)
1628 printk(KERN_INFO "Serial: Console lpuart rounded baud rate"
1629 "from %d to %d\n", baud_raw, *baud);
1630}
1631
380c966c
JL		 1632static void __init
1633lpuart32_console_get_options(struct lpuart_port *sport, int *baud,
1634 int *parity, int *bits)
1635{
1636 unsigned long cr, bd;
1637 unsigned int sbr, uartclk, baud_raw;
1638
1639 cr = lpuart32_read(sport->port.membase + UARTCTRL);
1640 cr &= UARTCTRL_TE | UARTCTRL_RE;
1641 if (!cr)
1642 return;
1643
1644 /* ok, the port was enabled */
1645
1646 cr = lpuart32_read(sport->port.membase + UARTCTRL);
1647
1648 *parity = 'n';
1649 if (cr & UARTCTRL_PE) {
1650 if (cr & UARTCTRL_PT)
1651 *parity = 'o';
1652 else
1653 *parity = 'e';
1654 }
1655
1656 if (cr & UARTCTRL_M)
1657 *bits = 9;
1658 else
1659 *bits = 8;
1660
1661 bd = lpuart32_read(sport->port.membase + UARTBAUD);
1662 bd &= UARTBAUD_SBR_MASK;
1663 sbr = bd;
1664 uartclk = clk_get_rate(sport->clk);
1665 /*
1666 * baud = mod_clk/(16*(sbr[13]+(brfa)/32)
1667 */
1668 baud_raw = uartclk / (16 * sbr);
1669
1670 if (*baud != baud_raw)
1671 printk(KERN_INFO "Serial: Console lpuart rounded baud rate"
1672 "from %d to %d\n", baud_raw, *baud);
1673}
1674
c9e2e946
JL		 1675static int __init lpuart_console_setup(struct console *co, char *options)
1676{
1677 struct lpuart_port *sport;
1678 int baud = 115200;
1679 int bits = 8;
1680 int parity = 'n';
1681 int flow = 'n';
1682
1683 /*
1684 * check whether an invalid uart number has been specified, and
1685 * if so, search for the first available port that does have
1686 * console support.
1687 */
1688 if (co->index == -1 || co->index >= ARRAY_SIZE(lpuart_ports))
1689 co->index = 0;
1690
1691 sport = lpuart_ports[co->index];
1692 if (sport == NULL)
1693 return -ENODEV;
1694
1695 if (options)
1696 uart_parse_options(options, &baud, &parity, &bits, &flow);
1697 else
380c966c
JL		 1698 if (sport->lpuart32)
1699 lpuart32_console_get_options(sport, &baud, &parity, &bits);
1700 else
1701 lpuart_console_get_options(sport, &baud, &parity, &bits);
c9e2e946 1702
380c966c
JL		 1703 if (sport->lpuart32)
1704 lpuart32_setup_watermark(sport);
1705 else
1706 lpuart_setup_watermark(sport);
c9e2e946
JL		 1707
1708 return uart_set_options(&sport->port, co, baud, parity, bits, flow);
1709}
1710
1711static struct uart_driver lpuart_reg;
1712static struct console lpuart_console = {
1713 .name = DEV_NAME,
1714 .write = lpuart_console_write,
1715 .device = uart_console_device,
1716 .setup = lpuart_console_setup,
1717 .flags = CON_PRINTBUFFER,
1718 .index = -1,
1719 .data = &lpuart_reg,
1720};
1721
380c966c
JL		 1722static struct console lpuart32_console = {
1723 .name = DEV_NAME,
1724 .write = lpuart32_console_write,
1725 .device = uart_console_device,
1726 .setup = lpuart_console_setup,
1727 .flags = CON_PRINTBUFFER,
1728 .index = -1,
1729 .data = &lpuart_reg,
1730};
1731
c9e2e946 1732#define LPUART_CONSOLE (&lpuart_console)
380c966c 1733#define LPUART32_CONSOLE (&lpuart32_console)
c9e2e946
JL		 1734#else
1735#define LPUART_CONSOLE NULL
380c966c 1736#define LPUART32_CONSOLE NULL
c9e2e946
JL		 1737#endif
1738
1739static struct uart_driver lpuart_reg = {
1740 .owner = THIS_MODULE,
1741 .driver_name = DRIVER_NAME,
1742 .dev_name = DEV_NAME,
1743 .nr = ARRAY_SIZE(lpuart_ports),
1744 .cons = LPUART_CONSOLE,
1745};
1746
1747static int lpuart_probe(struct platform_device *pdev)
1748{
1749 struct device_node *np = pdev->dev.of_node;
1750 struct lpuart_port *sport;
1751 struct resource *res;
1752 int ret;
1753
1754 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);
1755 if (!sport)
1756 return -ENOMEM;
1757
1758 pdev->dev.coherent_dma_mask = 0;
1759
1760 ret = of_alias_get_id(np, "serial");
1761 if (ret < 0) {
1762 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret);
1763 return ret;
1764 }
1765 sport->port.line = ret;
380c966c 1766 sport->lpuart32 = of_device_is_compatible(np, "fsl,ls1021a-lpuart");
c9e2e946 1767
4ae612a3 1768 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
c9e2e946
JL		 1769 sport->port.membase = devm_ioremap_resource(&pdev->dev, res);
1770 if (IS_ERR(sport->port.membase))
1771 return PTR_ERR(sport->port.membase);
1772
4ae612a3 1773 sport->port.mapbase = res->start;
c9e2e946
JL		 1774 sport->port.dev = &pdev->dev;
1775 sport->port.type = PORT_LPUART;
1776 sport->port.iotype = UPIO_MEM;
1777 sport->port.irq = platform_get_irq(pdev, 0);
380c966c
JL		 1778 if (sport->lpuart32)
1779 sport->port.ops = &lpuart32_pops;
1780 else
1781 sport->port.ops = &lpuart_pops;
c9e2e946
JL		 1782 sport->port.flags = UPF_BOOT_AUTOCONF;
1783
1784 sport->clk = devm_clk_get(&pdev->dev, "ipg");
1785 if (IS_ERR(sport->clk)) {
1786 ret = PTR_ERR(sport->clk);
1787 dev_err(&pdev->dev, "failed to get uart clk: %d\n", ret);
1788 return ret;
1789 }
1790
1791 ret = clk_prepare_enable(sport->clk);
1792 if (ret) {
1793 dev_err(&pdev->dev, "failed to enable uart clk: %d\n", ret);
1794 return ret;
1795 }
1796
1797 sport->port.uartclk = clk_get_rate(sport->clk);
1798
1799 lpuart_ports[sport->port.line] = sport;
1800
1801 platform_set_drvdata(pdev, &sport->port);
1802
380c966c
JL		 1803 if (sport->lpuart32)
1804 lpuart_reg.cons = LPUART32_CONSOLE;
1805 else
1806 lpuart_reg.cons = LPUART_CONSOLE;
1807
c9e2e946
JL		 1808 ret = uart_add_one_port(&lpuart_reg, &sport->port);
1809 if (ret) {
1810 clk_disable_unprepare(sport->clk);
1811 return ret;
1812 }
1813
4a818c43
SA		 1814 sport->dma_tx_chan = dma_request_slave_channel(sport->port.dev, "tx");
1815 if (!sport->dma_tx_chan)
1816 dev_info(sport->port.dev, "DMA tx channel request failed, "
1817 "operating without tx DMA\n");
1818
1819 sport->dma_rx_chan = dma_request_slave_channel(sport->port.dev, "rx");
1820 if (!sport->dma_rx_chan)
1821 dev_info(sport->port.dev, "DMA rx channel request failed, "
1822 "operating without rx DMA\n");
1823
c9e2e946
JL		 1824 return 0;
1825}
1826
1827static int lpuart_remove(struct platform_device *pdev)
1828{
1829 struct lpuart_port *sport = platform_get_drvdata(pdev);
1830
1831 uart_remove_one_port(&lpuart_reg, &sport->port);
1832
1833 clk_disable_unprepare(sport->clk);
1834
4a818c43
SA		 1835 if (sport->dma_tx_chan)
1836 dma_release_channel(sport->dma_tx_chan);
1837
1838 if (sport->dma_rx_chan)
1839 dma_release_channel(sport->dma_rx_chan);
1840
c9e2e946
JL		 1841 return 0;
1842}
1843
1844#ifdef CONFIG_PM_SLEEP
1845static int lpuart_suspend(struct device *dev)
1846{
1847 struct lpuart_port *sport = dev_get_drvdata(dev);
1848
1849 uart_suspend_port(&lpuart_reg, &sport->port);
1850
1851 return 0;
1852}
1853
1854static int lpuart_resume(struct device *dev)
1855{
1856 struct lpuart_port *sport = dev_get_drvdata(dev);
08de1014
JL		 1857 unsigned long temp;
1858
1859 if (sport->lpuart32) {
1860 lpuart32_setup_watermark(sport);
1861 temp = lpuart32_read(sport->port.membase + UARTCTRL);
1862 temp |= (UARTCTRL_RIE | UARTCTRL_TIE | UARTCTRL_RE |
1863 UARTCTRL_TE | UARTCTRL_ILIE);
1864 lpuart32_write(temp, sport->port.membase + UARTCTRL);
1865 } else {
1866 lpuart_setup_watermark(sport);
1867 temp = readb(sport->port.membase + UARTCR2);
1868 temp |= (UARTCR2_RIE | UARTCR2_TIE | UARTCR2_RE | UARTCR2_TE);
1869 writeb(temp, sport->port.membase + UARTCR2);
1870 }
c9e2e946
JL		 1871
1872 uart_resume_port(&lpuart_reg, &sport->port);
1873
1874 return 0;
1875}
1876#endif
1877
1878static SIMPLE_DEV_PM_OPS(lpuart_pm_ops, lpuart_suspend, lpuart_resume);
1879
1880static struct platform_driver lpuart_driver = {
1881 .probe = lpuart_probe,
1882 .remove = lpuart_remove,
1883 .driver = {
1884 .name = "fsl-lpuart",
c9e2e946
JL		 1885 .of_match_table = lpuart_dt_ids,
1886 .pm = &lpuart_pm_ops,
1887 },
1888};
1889
1890static int __init lpuart_serial_init(void)
1891{
144c29ed 1892 int ret = uart_register_driver(&lpuart_reg);
c9e2e946 1893
c9e2e946
JL		 1894 if (ret)
1895 return ret;
1896
1897 ret = platform_driver_register(&lpuart_driver);
1898 if (ret)
1899 uart_unregister_driver(&lpuart_reg);
1900
39c34b09 1901 return ret;
c9e2e946
JL		 1902}
1903
1904static void __exit lpuart_serial_exit(void)
1905{
1906 platform_driver_unregister(&lpuart_driver);
1907 uart_unregister_driver(&lpuart_reg);
1908}
1909
1910module_init(lpuart_serial_init);
1911module_exit(lpuart_serial_exit);
1912
1913MODULE_DESCRIPTION("Freescale lpuart serial port driver");
1914MODULE_LICENSE("GPL v2");
Linux 6.x block layer and io_uring tree(s)