Commit | Line | Data |
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e3b3d0f5 | 1 | // SPDX-License-Identifier: GPL-2.0+ |
c9e2e946 JL |
2 | /* |
3 | * Freescale lpuart serial port driver | |
4 | * | |
380c966c | 5 | * Copyright 2012-2014 Freescale Semiconductor, Inc. |
c9e2e946 JL |
6 | */ |
7 | ||
e1d91dda SS |
8 | #include <linux/bitfield.h> |
9 | #include <linux/bits.h> | |
f1cd8c87 YY |
10 | #include <linux/clk.h> |
11 | #include <linux/console.h> | |
bd5305dc | 12 | #include <linux/delay.h> |
f1cd8c87 YY |
13 | #include <linux/dma-mapping.h> |
14 | #include <linux/dmaengine.h> | |
15 | #include <linux/dmapool.h> | |
c9e2e946 | 16 | #include <linux/io.h> |
76bad3f8 | 17 | #include <linux/iopoll.h> |
c9e2e946 | 18 | #include <linux/irq.h> |
f1cd8c87 | 19 | #include <linux/module.h> |
c9e2e946 JL |
20 | #include <linux/of.h> |
21 | #include <linux/of_device.h> | |
f1cd8c87 | 22 | #include <linux/of_dma.h> |
4f5cb8c5 | 23 | #include <linux/pinctrl/consumer.h> |
43543e6f | 24 | #include <linux/pm_runtime.h> |
c9e2e946 | 25 | #include <linux/serial_core.h> |
f1cd8c87 | 26 | #include <linux/slab.h> |
c9e2e946 JL |
27 | #include <linux/tty_flip.h> |
28 | ||
29 | /* All registers are 8-bit width */ | |
30 | #define UARTBDH 0x00 | |
31 | #define UARTBDL 0x01 | |
32 | #define UARTCR1 0x02 | |
33 | #define UARTCR2 0x03 | |
34 | #define UARTSR1 0x04 | |
35 | #define UARTCR3 0x06 | |
36 | #define UARTDR 0x07 | |
37 | #define UARTCR4 0x0a | |
38 | #define UARTCR5 0x0b | |
39 | #define UARTMODEM 0x0d | |
40 | #define UARTPFIFO 0x10 | |
41 | #define UARTCFIFO 0x11 | |
42 | #define UARTSFIFO 0x12 | |
43 | #define UARTTWFIFO 0x13 | |
44 | #define UARTTCFIFO 0x14 | |
45 | #define UARTRWFIFO 0x15 | |
46 | ||
47 | #define UARTBDH_LBKDIE 0x80 | |
48 | #define UARTBDH_RXEDGIE 0x40 | |
49 | #define UARTBDH_SBR_MASK 0x1f | |
50 | ||
51 | #define UARTCR1_LOOPS 0x80 | |
52 | #define UARTCR1_RSRC 0x20 | |
53 | #define UARTCR1_M 0x10 | |
54 | #define UARTCR1_WAKE 0x08 | |
55 | #define UARTCR1_ILT 0x04 | |
56 | #define UARTCR1_PE 0x02 | |
57 | #define UARTCR1_PT 0x01 | |
58 | ||
59 | #define UARTCR2_TIE 0x80 | |
60 | #define UARTCR2_TCIE 0x40 | |
61 | #define UARTCR2_RIE 0x20 | |
62 | #define UARTCR2_ILIE 0x10 | |
63 | #define UARTCR2_TE 0x08 | |
64 | #define UARTCR2_RE 0x04 | |
65 | #define UARTCR2_RWU 0x02 | |
66 | #define UARTCR2_SBK 0x01 | |
67 | ||
68 | #define UARTSR1_TDRE 0x80 | |
69 | #define UARTSR1_TC 0x40 | |
70 | #define UARTSR1_RDRF 0x20 | |
71 | #define UARTSR1_IDLE 0x10 | |
72 | #define UARTSR1_OR 0x08 | |
73 | #define UARTSR1_NF 0x04 | |
74 | #define UARTSR1_FE 0x02 | |
75 | #define UARTSR1_PE 0x01 | |
76 | ||
77 | #define UARTCR3_R8 0x80 | |
78 | #define UARTCR3_T8 0x40 | |
79 | #define UARTCR3_TXDIR 0x20 | |
80 | #define UARTCR3_TXINV 0x10 | |
81 | #define UARTCR3_ORIE 0x08 | |
82 | #define UARTCR3_NEIE 0x04 | |
83 | #define UARTCR3_FEIE 0x02 | |
84 | #define UARTCR3_PEIE 0x01 | |
85 | ||
86 | #define UARTCR4_MAEN1 0x80 | |
87 | #define UARTCR4_MAEN2 0x40 | |
88 | #define UARTCR4_M10 0x20 | |
89 | #define UARTCR4_BRFA_MASK 0x1f | |
90 | #define UARTCR4_BRFA_OFF 0 | |
91 | ||
92 | #define UARTCR5_TDMAS 0x80 | |
93 | #define UARTCR5_RDMAS 0x20 | |
94 | ||
95 | #define UARTMODEM_RXRTSE 0x08 | |
96 | #define UARTMODEM_TXRTSPOL 0x04 | |
97 | #define UARTMODEM_TXRTSE 0x02 | |
98 | #define UARTMODEM_TXCTSE 0x01 | |
99 | ||
100 | #define UARTPFIFO_TXFE 0x80 | |
101 | #define UARTPFIFO_FIFOSIZE_MASK 0x7 | |
102 | #define UARTPFIFO_TXSIZE_OFF 4 | |
103 | #define UARTPFIFO_RXFE 0x08 | |
104 | #define UARTPFIFO_RXSIZE_OFF 0 | |
105 | ||
106 | #define UARTCFIFO_TXFLUSH 0x80 | |
107 | #define UARTCFIFO_RXFLUSH 0x40 | |
108 | #define UARTCFIFO_RXOFE 0x04 | |
109 | #define UARTCFIFO_TXOFE 0x02 | |
110 | #define UARTCFIFO_RXUFE 0x01 | |
111 | ||
112 | #define UARTSFIFO_TXEMPT 0x80 | |
113 | #define UARTSFIFO_RXEMPT 0x40 | |
114 | #define UARTSFIFO_RXOF 0x04 | |
115 | #define UARTSFIFO_TXOF 0x02 | |
116 | #define UARTSFIFO_RXUF 0x01 | |
117 | ||
bd5305dc FD |
118 | /* 32-bit global registers only for i.MX7ULP/i.MX8x |
119 | * Used to reset all internal logic and registers, except the Global Register. | |
120 | */ | |
121 | #define UART_GLOBAL 0x8 | |
122 | ||
a5fa2660 | 123 | /* 32-bit register definition */ |
380c966c JL |
124 | #define UARTBAUD 0x00 |
125 | #define UARTSTAT 0x04 | |
126 | #define UARTCTRL 0x08 | |
127 | #define UARTDATA 0x0C | |
128 | #define UARTMATCH 0x10 | |
129 | #define UARTMODIR 0x14 | |
130 | #define UARTFIFO 0x18 | |
131 | #define UARTWATER 0x1c | |
132 | ||
133 | #define UARTBAUD_MAEN1 0x80000000 | |
134 | #define UARTBAUD_MAEN2 0x40000000 | |
135 | #define UARTBAUD_M10 0x20000000 | |
136 | #define UARTBAUD_TDMAE 0x00800000 | |
137 | #define UARTBAUD_RDMAE 0x00200000 | |
138 | #define UARTBAUD_MATCFG 0x00400000 | |
139 | #define UARTBAUD_BOTHEDGE 0x00020000 | |
140 | #define UARTBAUD_RESYNCDIS 0x00010000 | |
141 | #define UARTBAUD_LBKDIE 0x00008000 | |
142 | #define UARTBAUD_RXEDGIE 0x00004000 | |
143 | #define UARTBAUD_SBNS 0x00002000 | |
144 | #define UARTBAUD_SBR 0x00000000 | |
145 | #define UARTBAUD_SBR_MASK 0x1fff | |
a6d7514b DA |
146 | #define UARTBAUD_OSR_MASK 0x1f |
147 | #define UARTBAUD_OSR_SHIFT 24 | |
380c966c JL |
148 | |
149 | #define UARTSTAT_LBKDIF 0x80000000 | |
150 | #define UARTSTAT_RXEDGIF 0x40000000 | |
151 | #define UARTSTAT_MSBF 0x20000000 | |
152 | #define UARTSTAT_RXINV 0x10000000 | |
153 | #define UARTSTAT_RWUID 0x08000000 | |
154 | #define UARTSTAT_BRK13 0x04000000 | |
155 | #define UARTSTAT_LBKDE 0x02000000 | |
156 | #define UARTSTAT_RAF 0x01000000 | |
157 | #define UARTSTAT_TDRE 0x00800000 | |
158 | #define UARTSTAT_TC 0x00400000 | |
159 | #define UARTSTAT_RDRF 0x00200000 | |
160 | #define UARTSTAT_IDLE 0x00100000 | |
161 | #define UARTSTAT_OR 0x00080000 | |
162 | #define UARTSTAT_NF 0x00040000 | |
163 | #define UARTSTAT_FE 0x00020000 | |
164 | #define UARTSTAT_PE 0x00010000 | |
165 | #define UARTSTAT_MA1F 0x00008000 | |
166 | #define UARTSTAT_M21F 0x00004000 | |
167 | ||
168 | #define UARTCTRL_R8T9 0x80000000 | |
169 | #define UARTCTRL_R9T8 0x40000000 | |
170 | #define UARTCTRL_TXDIR 0x20000000 | |
171 | #define UARTCTRL_TXINV 0x10000000 | |
172 | #define UARTCTRL_ORIE 0x08000000 | |
173 | #define UARTCTRL_NEIE 0x04000000 | |
174 | #define UARTCTRL_FEIE 0x02000000 | |
175 | #define UARTCTRL_PEIE 0x01000000 | |
176 | #define UARTCTRL_TIE 0x00800000 | |
177 | #define UARTCTRL_TCIE 0x00400000 | |
178 | #define UARTCTRL_RIE 0x00200000 | |
179 | #define UARTCTRL_ILIE 0x00100000 | |
180 | #define UARTCTRL_TE 0x00080000 | |
181 | #define UARTCTRL_RE 0x00040000 | |
182 | #define UARTCTRL_RWU 0x00020000 | |
183 | #define UARTCTRL_SBK 0x00010000 | |
184 | #define UARTCTRL_MA1IE 0x00008000 | |
185 | #define UARTCTRL_MA2IE 0x00004000 | |
e1d91dda | 186 | #define UARTCTRL_IDLECFG GENMASK(10, 8) |
380c966c JL |
187 | #define UARTCTRL_LOOPS 0x00000080 |
188 | #define UARTCTRL_DOZEEN 0x00000040 | |
189 | #define UARTCTRL_RSRC 0x00000020 | |
190 | #define UARTCTRL_M 0x00000010 | |
191 | #define UARTCTRL_WAKE 0x00000008 | |
192 | #define UARTCTRL_ILT 0x00000004 | |
193 | #define UARTCTRL_PE 0x00000002 | |
194 | #define UARTCTRL_PT 0x00000001 | |
195 | ||
196 | #define UARTDATA_NOISY 0x00008000 | |
197 | #define UARTDATA_PARITYE 0x00004000 | |
198 | #define UARTDATA_FRETSC 0x00002000 | |
199 | #define UARTDATA_RXEMPT 0x00001000 | |
200 | #define UARTDATA_IDLINE 0x00000800 | |
201 | #define UARTDATA_MASK 0x3ff | |
202 | ||
203 | #define UARTMODIR_IREN 0x00020000 | |
204 | #define UARTMODIR_TXCTSSRC 0x00000020 | |
205 | #define UARTMODIR_TXCTSC 0x00000010 | |
206 | #define UARTMODIR_RXRTSE 0x00000008 | |
207 | #define UARTMODIR_TXRTSPOL 0x00000004 | |
208 | #define UARTMODIR_TXRTSE 0x00000002 | |
209 | #define UARTMODIR_TXCTSE 0x00000001 | |
210 | ||
211 | #define UARTFIFO_TXEMPT 0x00800000 | |
212 | #define UARTFIFO_RXEMPT 0x00400000 | |
213 | #define UARTFIFO_TXOF 0x00020000 | |
214 | #define UARTFIFO_RXUF 0x00010000 | |
215 | #define UARTFIFO_TXFLUSH 0x00008000 | |
216 | #define UARTFIFO_RXFLUSH 0x00004000 | |
217 | #define UARTFIFO_TXOFE 0x00000200 | |
218 | #define UARTFIFO_RXUFE 0x00000100 | |
219 | #define UARTFIFO_TXFE 0x00000080 | |
220 | #define UARTFIFO_FIFOSIZE_MASK 0x7 | |
221 | #define UARTFIFO_TXSIZE_OFF 4 | |
222 | #define UARTFIFO_RXFE 0x00000008 | |
223 | #define UARTFIFO_RXSIZE_OFF 0 | |
f77ebb24 | 224 | #define UARTFIFO_DEPTH(x) (0x1 << ((x) ? ((x) + 1) : 0)) |
380c966c JL |
225 | |
226 | #define UARTWATER_COUNT_MASK 0xff | |
227 | #define UARTWATER_TXCNT_OFF 8 | |
228 | #define UARTWATER_RXCNT_OFF 24 | |
229 | #define UARTWATER_WATER_MASK 0xff | |
230 | #define UARTWATER_TXWATER_OFF 0 | |
231 | #define UARTWATER_RXWATER_OFF 16 | |
232 | ||
bd5305dc FD |
233 | #define UART_GLOBAL_RST 0x2 |
234 | #define GLOBAL_RST_MIN_US 20 | |
235 | #define GLOBAL_RST_MAX_US 40 | |
236 | ||
5887ad43 BD |
237 | /* Rx DMA timeout in ms, which is used to calculate Rx ring buffer size */ |
238 | #define DMA_RX_TIMEOUT (10) | |
43543e6f | 239 | #define UART_AUTOSUSPEND_TIMEOUT 3000 |
f1cd8c87 | 240 | |
c9e2e946 JL |
241 | #define DRIVER_NAME "fsl-lpuart" |
242 | #define DEV_NAME "ttyLP" | |
243 | #define UART_NR 6 | |
244 | ||
24b1e5f0 DA |
245 | /* IMX lpuart has four extra unused regs located at the beginning */ |
246 | #define IMX_REG_OFF 0x10 | |
247 | ||
35a4ed01 FD |
248 | enum lpuart_type { |
249 | VF610_LPUART, | |
250 | LS1021A_LPUART, | |
c2f448cf | 251 | LS1028A_LPUART, |
35a4ed01 FD |
252 | IMX7ULP_LPUART, |
253 | IMX8QXP_LPUART, | |
443df57b | 254 | IMXRT1050_LPUART, |
35a4ed01 FD |
255 | }; |
256 | ||
c9e2e946 JL |
257 | struct lpuart_port { |
258 | struct uart_port port; | |
35a4ed01 FD |
259 | enum lpuart_type devtype; |
260 | struct clk *ipg_clk; | |
261 | struct clk *baud_clk; | |
c9e2e946 JL |
262 | unsigned int txfifo_size; |
263 | unsigned int rxfifo_size; | |
f1cd8c87 | 264 | |
4a818c43 SA |
265 | bool lpuart_dma_tx_use; |
266 | bool lpuart_dma_rx_use; | |
f1cd8c87 YY |
267 | struct dma_chan *dma_tx_chan; |
268 | struct dma_chan *dma_rx_chan; | |
269 | struct dma_async_tx_descriptor *dma_tx_desc; | |
270 | struct dma_async_tx_descriptor *dma_rx_desc; | |
f1cd8c87 YY |
271 | dma_cookie_t dma_tx_cookie; |
272 | dma_cookie_t dma_rx_cookie; | |
f1cd8c87 YY |
273 | unsigned int dma_tx_bytes; |
274 | unsigned int dma_rx_bytes; | |
6250cc30 | 275 | bool dma_tx_in_progress; |
f1cd8c87 YY |
276 | unsigned int dma_rx_timeout; |
277 | struct timer_list lpuart_timer; | |
6250cc30 | 278 | struct scatterlist rx_sgl, tx_sgl[2]; |
5887ad43 BD |
279 | struct circ_buf rx_ring; |
280 | int rx_dma_rng_buf_len; | |
6250cc30 BD |
281 | unsigned int dma_tx_nents; |
282 | wait_queue_head_t dma_wait; | |
070298c8 SW |
283 | bool is_cs7; /* Set to true when character size is 7 */ |
284 | /* and the parity is enabled */ | |
c9e2e946 JL |
285 | }; |
286 | ||
0d6fce90 | 287 | struct lpuart_soc_data { |
35a4ed01 FD |
288 | enum lpuart_type devtype; |
289 | char iotype; | |
290 | u8 reg_off; | |
0d6fce90 DA |
291 | }; |
292 | ||
293 | static const struct lpuart_soc_data vf_data = { | |
35a4ed01 | 294 | .devtype = VF610_LPUART, |
0d6fce90 DA |
295 | .iotype = UPIO_MEM, |
296 | }; | |
297 | ||
c2f448cf | 298 | static const struct lpuart_soc_data ls1021a_data = { |
35a4ed01 | 299 | .devtype = LS1021A_LPUART, |
0d6fce90 DA |
300 | .iotype = UPIO_MEM32BE, |
301 | }; | |
302 | ||
c2f448cf MW |
303 | static const struct lpuart_soc_data ls1028a_data = { |
304 | .devtype = LS1028A_LPUART, | |
305 | .iotype = UPIO_MEM32, | |
306 | }; | |
307 | ||
35a4ed01 FD |
308 | static struct lpuart_soc_data imx7ulp_data = { |
309 | .devtype = IMX7ULP_LPUART, | |
310 | .iotype = UPIO_MEM32, | |
311 | .reg_off = IMX_REG_OFF, | |
312 | }; | |
313 | ||
314 | static struct lpuart_soc_data imx8qxp_data = { | |
315 | .devtype = IMX8QXP_LPUART, | |
24b1e5f0 DA |
316 | .iotype = UPIO_MEM32, |
317 | .reg_off = IMX_REG_OFF, | |
318 | }; | |
443df57b JT |
319 | static struct lpuart_soc_data imxrt1050_data = { |
320 | .devtype = IMXRT1050_LPUART, | |
321 | .iotype = UPIO_MEM32, | |
322 | .reg_off = IMX_REG_OFF, | |
323 | }; | |
24b1e5f0 | 324 | |
ed0bb232 | 325 | static const struct of_device_id lpuart_dt_ids[] = { |
0d6fce90 | 326 | { .compatible = "fsl,vf610-lpuart", .data = &vf_data, }, |
c2f448cf MW |
327 | { .compatible = "fsl,ls1021a-lpuart", .data = &ls1021a_data, }, |
328 | { .compatible = "fsl,ls1028a-lpuart", .data = &ls1028a_data, }, | |
35a4ed01 FD |
329 | { .compatible = "fsl,imx7ulp-lpuart", .data = &imx7ulp_data, }, |
330 | { .compatible = "fsl,imx8qxp-lpuart", .data = &imx8qxp_data, }, | |
443df57b | 331 | { .compatible = "fsl,imxrt1050-lpuart", .data = &imxrt1050_data}, |
c9e2e946 JL |
332 | { /* sentinel */ } |
333 | }; | |
334 | MODULE_DEVICE_TABLE(of, lpuart_dt_ids); | |
335 | ||
f1cd8c87 YY |
336 | /* Forward declare this for the dma callbacks*/ |
337 | static void lpuart_dma_tx_complete(void *arg); | |
f1cd8c87 | 338 | |
c97f2a6f | 339 | static inline bool is_layerscape_lpuart(struct lpuart_port *sport) |
c2f448cf | 340 | { |
c97f2a6f VO |
341 | return (sport->devtype == LS1021A_LPUART || |
342 | sport->devtype == LS1028A_LPUART); | |
c2f448cf MW |
343 | } |
344 | ||
bd5305dc FD |
345 | static inline bool is_imx7ulp_lpuart(struct lpuart_port *sport) |
346 | { | |
347 | return sport->devtype == IMX7ULP_LPUART; | |
348 | } | |
349 | ||
35a4ed01 FD |
350 | static inline bool is_imx8qxp_lpuart(struct lpuart_port *sport) |
351 | { | |
352 | return sport->devtype == IMX8QXP_LPUART; | |
353 | } | |
354 | ||
f98e1fcd DA |
355 | static inline u32 lpuart32_read(struct uart_port *port, u32 off) |
356 | { | |
357 | switch (port->iotype) { | |
358 | case UPIO_MEM32: | |
359 | return readl(port->membase + off); | |
360 | case UPIO_MEM32BE: | |
361 | return ioread32be(port->membase + off); | |
362 | default: | |
363 | return 0; | |
364 | } | |
380c966c JL |
365 | } |
366 | ||
a0204f25 | 367 | static inline void lpuart32_write(struct uart_port *port, u32 val, |
f98e1fcd DA |
368 | u32 off) |
369 | { | |
370 | switch (port->iotype) { | |
371 | case UPIO_MEM32: | |
372 | writel(val, port->membase + off); | |
373 | break; | |
374 | case UPIO_MEM32BE: | |
375 | iowrite32be(val, port->membase + off); | |
376 | break; | |
377 | } | |
380c966c JL |
378 | } |
379 | ||
35a4ed01 FD |
380 | static int __lpuart_enable_clks(struct lpuart_port *sport, bool is_en) |
381 | { | |
382 | int ret = 0; | |
383 | ||
384 | if (is_en) { | |
385 | ret = clk_prepare_enable(sport->ipg_clk); | |
386 | if (ret) | |
387 | return ret; | |
388 | ||
389 | ret = clk_prepare_enable(sport->baud_clk); | |
390 | if (ret) { | |
391 | clk_disable_unprepare(sport->ipg_clk); | |
392 | return ret; | |
393 | } | |
394 | } else { | |
395 | clk_disable_unprepare(sport->baud_clk); | |
396 | clk_disable_unprepare(sport->ipg_clk); | |
397 | } | |
398 | ||
399 | return 0; | |
400 | } | |
401 | ||
402 | static unsigned int lpuart_get_baud_clk_rate(struct lpuart_port *sport) | |
403 | { | |
404 | if (is_imx8qxp_lpuart(sport)) | |
405 | return clk_get_rate(sport->baud_clk); | |
406 | ||
407 | return clk_get_rate(sport->ipg_clk); | |
408 | } | |
409 | ||
410 | #define lpuart_enable_clks(x) __lpuart_enable_clks(x, true) | |
411 | #define lpuart_disable_clks(x) __lpuart_enable_clks(x, false) | |
412 | ||
c9e2e946 JL |
413 | static void lpuart_stop_tx(struct uart_port *port) |
414 | { | |
415 | unsigned char temp; | |
416 | ||
417 | temp = readb(port->membase + UARTCR2); | |
418 | temp &= ~(UARTCR2_TIE | UARTCR2_TCIE); | |
419 | writeb(temp, port->membase + UARTCR2); | |
420 | } | |
421 | ||
380c966c JL |
422 | static void lpuart32_stop_tx(struct uart_port *port) |
423 | { | |
424 | unsigned long temp; | |
425 | ||
a0204f25 | 426 | temp = lpuart32_read(port, UARTCTRL); |
380c966c | 427 | temp &= ~(UARTCTRL_TIE | UARTCTRL_TCIE); |
a0204f25 | 428 | lpuart32_write(port, temp, UARTCTRL); |
380c966c JL |
429 | } |
430 | ||
c9e2e946 JL |
431 | static void lpuart_stop_rx(struct uart_port *port) |
432 | { | |
433 | unsigned char temp; | |
434 | ||
435 | temp = readb(port->membase + UARTCR2); | |
436 | writeb(temp & ~UARTCR2_RE, port->membase + UARTCR2); | |
437 | } | |
438 | ||
380c966c JL |
439 | static void lpuart32_stop_rx(struct uart_port *port) |
440 | { | |
441 | unsigned long temp; | |
442 | ||
a0204f25 DA |
443 | temp = lpuart32_read(port, UARTCTRL); |
444 | lpuart32_write(port, temp & ~UARTCTRL_RE, UARTCTRL); | |
380c966c JL |
445 | } |
446 | ||
6250cc30 | 447 | static void lpuart_dma_tx(struct lpuart_port *sport) |
f1cd8c87 YY |
448 | { |
449 | struct circ_buf *xmit = &sport->port.state->xmit; | |
6250cc30 BD |
450 | struct scatterlist *sgl = sport->tx_sgl; |
451 | struct device *dev = sport->port.dev; | |
a092ab25 | 452 | struct dma_chan *chan = sport->dma_tx_chan; |
6250cc30 | 453 | int ret; |
f1cd8c87 | 454 | |
6250cc30 BD |
455 | if (sport->dma_tx_in_progress) |
456 | return; | |
f1cd8c87 | 457 | |
6250cc30 | 458 | sport->dma_tx_bytes = uart_circ_chars_pending(xmit); |
f1cd8c87 | 459 | |
d704b2d3 | 460 | if (xmit->tail < xmit->head || xmit->head == 0) { |
6250cc30 BD |
461 | sport->dma_tx_nents = 1; |
462 | sg_init_one(sgl, xmit->buf + xmit->tail, sport->dma_tx_bytes); | |
463 | } else { | |
464 | sport->dma_tx_nents = 2; | |
465 | sg_init_table(sgl, 2); | |
466 | sg_set_buf(sgl, xmit->buf + xmit->tail, | |
467 | UART_XMIT_SIZE - xmit->tail); | |
468 | sg_set_buf(sgl + 1, xmit->buf, xmit->head); | |
469 | } | |
f1cd8c87 | 470 | |
a092ab25 MW |
471 | ret = dma_map_sg(chan->device->dev, sgl, sport->dma_tx_nents, |
472 | DMA_TO_DEVICE); | |
6250cc30 BD |
473 | if (!ret) { |
474 | dev_err(dev, "DMA mapping error for TX.\n"); | |
475 | return; | |
476 | } | |
f1cd8c87 | 477 | |
a092ab25 | 478 | sport->dma_tx_desc = dmaengine_prep_slave_sg(chan, sgl, |
487ee861 PF |
479 | ret, DMA_MEM_TO_DEV, |
480 | DMA_PREP_INTERRUPT); | |
f1cd8c87 | 481 | if (!sport->dma_tx_desc) { |
a092ab25 MW |
482 | dma_unmap_sg(chan->device->dev, sgl, sport->dma_tx_nents, |
483 | DMA_TO_DEVICE); | |
6250cc30 BD |
484 | dev_err(dev, "Cannot prepare TX slave DMA!\n"); |
485 | return; | |
f1cd8c87 YY |
486 | } |
487 | ||
488 | sport->dma_tx_desc->callback = lpuart_dma_tx_complete; | |
489 | sport->dma_tx_desc->callback_param = sport; | |
6250cc30 | 490 | sport->dma_tx_in_progress = true; |
f1cd8c87 | 491 | sport->dma_tx_cookie = dmaengine_submit(sport->dma_tx_desc); |
a092ab25 | 492 | dma_async_issue_pending(chan); |
f1cd8c87 YY |
493 | } |
494 | ||
a90fa532 AS |
495 | static bool lpuart_stopped_or_empty(struct uart_port *port) |
496 | { | |
497 | return uart_circ_empty(&port->state->xmit) || uart_tx_stopped(port); | |
498 | } | |
499 | ||
f1cd8c87 YY |
500 | static void lpuart_dma_tx_complete(void *arg) |
501 | { | |
502 | struct lpuart_port *sport = arg; | |
6250cc30 | 503 | struct scatterlist *sgl = &sport->tx_sgl[0]; |
f1cd8c87 | 504 | struct circ_buf *xmit = &sport->port.state->xmit; |
a092ab25 | 505 | struct dma_chan *chan = sport->dma_tx_chan; |
f1cd8c87 YY |
506 | unsigned long flags; |
507 | ||
f1cd8c87 | 508 | spin_lock_irqsave(&sport->port.lock, flags); |
88c1d247 FD |
509 | if (!sport->dma_tx_in_progress) { |
510 | spin_unlock_irqrestore(&sport->port.lock, flags); | |
511 | return; | |
512 | } | |
f1cd8c87 | 513 | |
a092ab25 MW |
514 | dma_unmap_sg(chan->device->dev, sgl, sport->dma_tx_nents, |
515 | DMA_TO_DEVICE); | |
6250cc30 | 516 | |
cacf7f68 | 517 | uart_xmit_advance(&sport->port, sport->dma_tx_bytes); |
6250cc30 BD |
518 | sport->dma_tx_in_progress = false; |
519 | spin_unlock_irqrestore(&sport->port.lock, flags); | |
f1cd8c87 YY |
520 | |
521 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
522 | uart_write_wakeup(&sport->port); | |
523 | ||
6250cc30 BD |
524 | if (waitqueue_active(&sport->dma_wait)) { |
525 | wake_up(&sport->dma_wait); | |
526 | return; | |
527 | } | |
528 | ||
529 | spin_lock_irqsave(&sport->port.lock, flags); | |
530 | ||
a90fa532 | 531 | if (!lpuart_stopped_or_empty(&sport->port)) |
6250cc30 | 532 | lpuart_dma_tx(sport); |
f1cd8c87 YY |
533 | |
534 | spin_unlock_irqrestore(&sport->port.lock, flags); | |
535 | } | |
536 | ||
42b68768 AN |
537 | static dma_addr_t lpuart_dma_datareg_addr(struct lpuart_port *sport) |
538 | { | |
539 | switch (sport->port.iotype) { | |
540 | case UPIO_MEM32: | |
541 | return sport->port.mapbase + UARTDATA; | |
542 | case UPIO_MEM32BE: | |
543 | return sport->port.mapbase + UARTDATA + sizeof(u32) - 1; | |
544 | } | |
545 | return sport->port.mapbase + UARTDR; | |
546 | } | |
547 | ||
6250cc30 BD |
548 | static int lpuart_dma_tx_request(struct uart_port *port) |
549 | { | |
550 | struct lpuart_port *sport = container_of(port, | |
551 | struct lpuart_port, port); | |
552 | struct dma_slave_config dma_tx_sconfig = {}; | |
553 | int ret; | |
554 | ||
42b68768 | 555 | dma_tx_sconfig.dst_addr = lpuart_dma_datareg_addr(sport); |
6250cc30 BD |
556 | dma_tx_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; |
557 | dma_tx_sconfig.dst_maxburst = 1; | |
558 | dma_tx_sconfig.direction = DMA_MEM_TO_DEV; | |
559 | ret = dmaengine_slave_config(sport->dma_tx_chan, &dma_tx_sconfig); | |
560 | ||
561 | if (ret) { | |
562 | dev_err(sport->port.dev, | |
563 | "DMA slave config failed, err = %d\n", ret); | |
564 | return ret; | |
565 | } | |
566 | ||
567 | return 0; | |
568 | } | |
569 | ||
9bc19af9 AS |
570 | static bool lpuart_is_32(struct lpuart_port *sport) |
571 | { | |
572 | return sport->port.iotype == UPIO_MEM32 || | |
573 | sport->port.iotype == UPIO_MEM32BE; | |
574 | } | |
575 | ||
bfc2e07f SA |
576 | static void lpuart_flush_buffer(struct uart_port *port) |
577 | { | |
578 | struct lpuart_port *sport = container_of(port, struct lpuart_port, port); | |
a092ab25 | 579 | struct dma_chan *chan = sport->dma_tx_chan; |
9bc19af9 | 580 | u32 val; |
6250cc30 | 581 | |
bfc2e07f | 582 | if (sport->lpuart_dma_tx_use) { |
6250cc30 | 583 | if (sport->dma_tx_in_progress) { |
a092ab25 | 584 | dma_unmap_sg(chan->device->dev, &sport->tx_sgl[0], |
6250cc30 BD |
585 | sport->dma_tx_nents, DMA_TO_DEVICE); |
586 | sport->dma_tx_in_progress = false; | |
587 | } | |
8682ab0e | 588 | dmaengine_terminate_async(chan); |
bfc2e07f | 589 | } |
9bc19af9 AS |
590 | |
591 | if (lpuart_is_32(sport)) { | |
592 | val = lpuart32_read(&sport->port, UARTFIFO); | |
593 | val |= UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH; | |
594 | lpuart32_write(&sport->port, val, UARTFIFO); | |
595 | } else { | |
5df884d4 | 596 | val = readb(sport->port.membase + UARTCFIFO); |
9bc19af9 AS |
597 | val |= UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH; |
598 | writeb(val, sport->port.membase + UARTCFIFO); | |
599 | } | |
bfc2e07f SA |
600 | } |
601 | ||
56dd627f AS |
602 | static void lpuart_wait_bit_set(struct uart_port *port, unsigned int offset, |
603 | u8 bit) | |
604 | { | |
605 | while (!(readb(port->membase + offset) & bit)) | |
f2f5e04c | 606 | cpu_relax(); |
56dd627f AS |
607 | } |
608 | ||
609 | static void lpuart32_wait_bit_set(struct uart_port *port, unsigned int offset, | |
610 | u32 bit) | |
611 | { | |
612 | while (!(lpuart32_read(port, offset) & bit)) | |
f2f5e04c | 613 | cpu_relax(); |
56dd627f AS |
614 | } |
615 | ||
2a41bc2a NR |
616 | #if defined(CONFIG_CONSOLE_POLL) |
617 | ||
618 | static int lpuart_poll_init(struct uart_port *port) | |
619 | { | |
620 | struct lpuart_port *sport = container_of(port, | |
621 | struct lpuart_port, port); | |
622 | unsigned long flags; | |
623 | unsigned char temp; | |
624 | ||
625 | sport->port.fifosize = 0; | |
626 | ||
627 | spin_lock_irqsave(&sport->port.lock, flags); | |
628 | /* Disable Rx & Tx */ | |
629 | writeb(0, sport->port.membase + UARTCR2); | |
630 | ||
631 | temp = readb(sport->port.membase + UARTPFIFO); | |
632 | /* Enable Rx and Tx FIFO */ | |
633 | writeb(temp | UARTPFIFO_RXFE | UARTPFIFO_TXFE, | |
634 | sport->port.membase + UARTPFIFO); | |
635 | ||
636 | /* flush Tx and Rx FIFO */ | |
637 | writeb(UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH, | |
638 | sport->port.membase + UARTCFIFO); | |
639 | ||
640 | /* explicitly clear RDRF */ | |
641 | if (readb(sport->port.membase + UARTSR1) & UARTSR1_RDRF) { | |
642 | readb(sport->port.membase + UARTDR); | |
643 | writeb(UARTSFIFO_RXUF, sport->port.membase + UARTSFIFO); | |
644 | } | |
645 | ||
646 | writeb(0, sport->port.membase + UARTTWFIFO); | |
647 | writeb(1, sport->port.membase + UARTRWFIFO); | |
648 | ||
649 | /* Enable Rx and Tx */ | |
650 | writeb(UARTCR2_RE | UARTCR2_TE, sport->port.membase + UARTCR2); | |
651 | spin_unlock_irqrestore(&sport->port.lock, flags); | |
652 | ||
653 | return 0; | |
654 | } | |
655 | ||
656 | static void lpuart_poll_put_char(struct uart_port *port, unsigned char c) | |
657 | { | |
2a41bc2a | 658 | /* drain */ |
56dd627f | 659 | lpuart_wait_bit_set(port, UARTSR1, UARTSR1_TDRE); |
2a41bc2a NR |
660 | writeb(c, port->membase + UARTDR); |
661 | } | |
662 | ||
663 | static int lpuart_poll_get_char(struct uart_port *port) | |
664 | { | |
665 | if (!(readb(port->membase + UARTSR1) & UARTSR1_RDRF)) | |
666 | return NO_POLL_CHAR; | |
667 | ||
668 | return readb(port->membase + UARTDR); | |
669 | } | |
670 | ||
a5fa2660 MV |
671 | static int lpuart32_poll_init(struct uart_port *port) |
672 | { | |
673 | unsigned long flags; | |
674 | struct lpuart_port *sport = container_of(port, struct lpuart_port, port); | |
675 | u32 temp; | |
676 | ||
677 | sport->port.fifosize = 0; | |
678 | ||
679 | spin_lock_irqsave(&sport->port.lock, flags); | |
680 | ||
681 | /* Disable Rx & Tx */ | |
9ea40db4 | 682 | lpuart32_write(&sport->port, 0, UARTCTRL); |
a5fa2660 | 683 | |
1da17d7c | 684 | temp = lpuart32_read(&sport->port, UARTFIFO); |
a5fa2660 MV |
685 | |
686 | /* Enable Rx and Tx FIFO */ | |
9ea40db4 | 687 | lpuart32_write(&sport->port, temp | UARTFIFO_RXFE | UARTFIFO_TXFE, UARTFIFO); |
a5fa2660 MV |
688 | |
689 | /* flush Tx and Rx FIFO */ | |
9ea40db4 | 690 | lpuart32_write(&sport->port, UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH, UARTFIFO); |
a5fa2660 MV |
691 | |
692 | /* explicitly clear RDRF */ | |
1da17d7c AS |
693 | if (lpuart32_read(&sport->port, UARTSTAT) & UARTSTAT_RDRF) { |
694 | lpuart32_read(&sport->port, UARTDATA); | |
9ea40db4 | 695 | lpuart32_write(&sport->port, UARTFIFO_RXUF, UARTFIFO); |
a5fa2660 MV |
696 | } |
697 | ||
698 | /* Enable Rx and Tx */ | |
9ea40db4 | 699 | lpuart32_write(&sport->port, UARTCTRL_RE | UARTCTRL_TE, UARTCTRL); |
a5fa2660 MV |
700 | spin_unlock_irqrestore(&sport->port.lock, flags); |
701 | ||
702 | return 0; | |
703 | } | |
704 | ||
705 | static void lpuart32_poll_put_char(struct uart_port *port, unsigned char c) | |
706 | { | |
56dd627f | 707 | lpuart32_wait_bit_set(port, UARTSTAT, UARTSTAT_TDRE); |
9ea40db4 | 708 | lpuart32_write(port, c, UARTDATA); |
a5fa2660 MV |
709 | } |
710 | ||
711 | static int lpuart32_poll_get_char(struct uart_port *port) | |
712 | { | |
29788ab1 | 713 | if (!(lpuart32_read(port, UARTWATER) >> UARTWATER_RXCNT_OFF)) |
a5fa2660 MV |
714 | return NO_POLL_CHAR; |
715 | ||
1da17d7c | 716 | return lpuart32_read(port, UARTDATA); |
a5fa2660 | 717 | } |
2a41bc2a NR |
718 | #endif |
719 | ||
c9e2e946 JL |
720 | static inline void lpuart_transmit_buffer(struct lpuart_port *sport) |
721 | { | |
2d141e68 JSS |
722 | struct uart_port *port = &sport->port; |
723 | u8 ch; | |
c9e2e946 | 724 | |
2d141e68 JSS |
725 | uart_port_tx(port, ch, |
726 | readb(port->membase + UARTTCFIFO) < sport->txfifo_size, | |
727 | writeb(ch, port->membase + UARTDR)); | |
c9e2e946 JL |
728 | } |
729 | ||
380c966c JL |
730 | static inline void lpuart32_transmit_buffer(struct lpuart_port *sport) |
731 | { | |
732 | struct circ_buf *xmit = &sport->port.state->xmit; | |
733 | unsigned long txcnt; | |
734 | ||
93b9523a AS |
735 | if (sport->port.x_char) { |
736 | lpuart32_write(&sport->port, sport->port.x_char, UARTDATA); | |
737 | sport->port.icount.tx++; | |
738 | sport->port.x_char = 0; | |
739 | return; | |
740 | } | |
741 | ||
a90fa532 | 742 | if (lpuart_stopped_or_empty(&sport->port)) { |
93b9523a AS |
743 | lpuart32_stop_tx(&sport->port); |
744 | return; | |
745 | } | |
746 | ||
a0204f25 | 747 | txcnt = lpuart32_read(&sport->port, UARTWATER); |
380c966c JL |
748 | txcnt = txcnt >> UARTWATER_TXCNT_OFF; |
749 | txcnt &= UARTWATER_COUNT_MASK; | |
750 | while (!uart_circ_empty(xmit) && (txcnt < sport->txfifo_size)) { | |
a0204f25 | 751 | lpuart32_write(&sport->port, xmit->buf[xmit->tail], UARTDATA); |
cacf7f68 | 752 | uart_xmit_advance(&sport->port, 1); |
a0204f25 | 753 | txcnt = lpuart32_read(&sport->port, UARTWATER); |
380c966c JL |
754 | txcnt = txcnt >> UARTWATER_TXCNT_OFF; |
755 | txcnt &= UARTWATER_COUNT_MASK; | |
756 | } | |
757 | ||
758 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
759 | uart_write_wakeup(&sport->port); | |
760 | ||
761 | if (uart_circ_empty(xmit)) | |
762 | lpuart32_stop_tx(&sport->port); | |
763 | } | |
764 | ||
c9e2e946 JL |
765 | static void lpuart_start_tx(struct uart_port *port) |
766 | { | |
f1cd8c87 YY |
767 | struct lpuart_port *sport = container_of(port, |
768 | struct lpuart_port, port); | |
c9e2e946 JL |
769 | unsigned char temp; |
770 | ||
771 | temp = readb(port->membase + UARTCR2); | |
772 | writeb(temp | UARTCR2_TIE, port->membase + UARTCR2); | |
773 | ||
4a818c43 | 774 | if (sport->lpuart_dma_tx_use) { |
a90fa532 | 775 | if (!lpuart_stopped_or_empty(port)) |
6250cc30 | 776 | lpuart_dma_tx(sport); |
f1cd8c87 YY |
777 | } else { |
778 | if (readb(port->membase + UARTSR1) & UARTSR1_TDRE) | |
779 | lpuart_transmit_buffer(sport); | |
780 | } | |
c9e2e946 JL |
781 | } |
782 | ||
380c966c JL |
783 | static void lpuart32_start_tx(struct uart_port *port) |
784 | { | |
785 | struct lpuart_port *sport = container_of(port, struct lpuart_port, port); | |
786 | unsigned long temp; | |
787 | ||
42b68768 | 788 | if (sport->lpuart_dma_tx_use) { |
a90fa532 | 789 | if (!lpuart_stopped_or_empty(port)) |
42b68768 AN |
790 | lpuart_dma_tx(sport); |
791 | } else { | |
792 | temp = lpuart32_read(port, UARTCTRL); | |
793 | lpuart32_write(port, temp | UARTCTRL_TIE, UARTCTRL); | |
380c966c | 794 | |
42b68768 AN |
795 | if (lpuart32_read(port, UARTSTAT) & UARTSTAT_TDRE) |
796 | lpuart32_transmit_buffer(sport); | |
797 | } | |
380c966c JL |
798 | } |
799 | ||
43543e6f SS |
800 | static void |
801 | lpuart_uart_pm(struct uart_port *port, unsigned int state, unsigned int oldstate) | |
802 | { | |
803 | switch (state) { | |
804 | case UART_PM_STATE_OFF: | |
805 | pm_runtime_mark_last_busy(port->dev); | |
806 | pm_runtime_put_autosuspend(port->dev); | |
807 | break; | |
808 | default: | |
809 | pm_runtime_get_sync(port->dev); | |
810 | break; | |
811 | } | |
812 | } | |
813 | ||
6250cc30 BD |
814 | /* return TIOCSER_TEMT when transmitter is not busy */ |
815 | static unsigned int lpuart_tx_empty(struct uart_port *port) | |
816 | { | |
817 | struct lpuart_port *sport = container_of(port, | |
818 | struct lpuart_port, port); | |
819 | unsigned char sr1 = readb(port->membase + UARTSR1); | |
820 | unsigned char sfifo = readb(port->membase + UARTSFIFO); | |
821 | ||
822 | if (sport->dma_tx_in_progress) | |
823 | return 0; | |
824 | ||
825 | if (sr1 & UARTSR1_TC && sfifo & UARTSFIFO_TXEMPT) | |
826 | return TIOCSER_TEMT; | |
827 | ||
828 | return 0; | |
829 | } | |
830 | ||
831 | static unsigned int lpuart32_tx_empty(struct uart_port *port) | |
832 | { | |
46dd6d77 AN |
833 | struct lpuart_port *sport = container_of(port, |
834 | struct lpuart_port, port); | |
835 | unsigned long stat = lpuart32_read(port, UARTSTAT); | |
836 | unsigned long sfifo = lpuart32_read(port, UARTFIFO); | |
837 | ||
838 | if (sport->dma_tx_in_progress) | |
839 | return 0; | |
840 | ||
841 | if (stat & UARTSTAT_TC && sfifo & UARTFIFO_TXEMPT) | |
842 | return TIOCSER_TEMT; | |
843 | ||
844 | return 0; | |
6250cc30 BD |
845 | } |
846 | ||
3993ddc2 | 847 | static void lpuart_txint(struct lpuart_port *sport) |
c9e2e946 | 848 | { |
0d84f622 | 849 | spin_lock(&sport->port.lock); |
93b9523a | 850 | lpuart_transmit_buffer(sport); |
0d84f622 | 851 | spin_unlock(&sport->port.lock); |
c9e2e946 JL |
852 | } |
853 | ||
3993ddc2 | 854 | static void lpuart_rxint(struct lpuart_port *sport) |
c9e2e946 | 855 | { |
cc584ab8 | 856 | unsigned int flg, ignored = 0, overrun = 0; |
c9e2e946 | 857 | struct tty_port *port = &sport->port.state->port; |
c9e2e946 JL |
858 | unsigned char rx, sr; |
859 | ||
0d84f622 | 860 | spin_lock(&sport->port.lock); |
c9e2e946 JL |
861 | |
862 | while (!(readb(sport->port.membase + UARTSFIFO) & UARTSFIFO_RXEMPT)) { | |
863 | flg = TTY_NORMAL; | |
864 | sport->port.icount.rx++; | |
865 | /* | |
866 | * to clear the FE, OR, NF, FE, PE flags, | |
867 | * read SR1 then read DR | |
868 | */ | |
869 | sr = readb(sport->port.membase + UARTSR1); | |
870 | rx = readb(sport->port.membase + UARTDR); | |
871 | ||
5697df73 | 872 | if (uart_prepare_sysrq_char(&sport->port, rx)) |
c9e2e946 JL |
873 | continue; |
874 | ||
875 | if (sr & (UARTSR1_PE | UARTSR1_OR | UARTSR1_FE)) { | |
876 | if (sr & UARTSR1_PE) | |
877 | sport->port.icount.parity++; | |
878 | else if (sr & UARTSR1_FE) | |
879 | sport->port.icount.frame++; | |
880 | ||
881 | if (sr & UARTSR1_OR) | |
cc584ab8 | 882 | overrun++; |
c9e2e946 JL |
883 | |
884 | if (sr & sport->port.ignore_status_mask) { | |
885 | if (++ignored > 100) | |
886 | goto out; | |
887 | continue; | |
888 | } | |
889 | ||
890 | sr &= sport->port.read_status_mask; | |
891 | ||
892 | if (sr & UARTSR1_PE) | |
893 | flg = TTY_PARITY; | |
894 | else if (sr & UARTSR1_FE) | |
895 | flg = TTY_FRAME; | |
896 | ||
897 | if (sr & UARTSR1_OR) | |
898 | flg = TTY_OVERRUN; | |
899 | ||
c9e2e946 | 900 | sport->port.sysrq = 0; |
c9e2e946 JL |
901 | } |
902 | ||
93cf538e SS |
903 | if (tty_insert_flip_char(port, rx, flg) == 0) |
904 | sport->port.icount.buf_overrun++; | |
c9e2e946 JL |
905 | } |
906 | ||
907 | out: | |
cc584ab8 SA |
908 | if (overrun) { |
909 | sport->port.icount.overrun += overrun; | |
910 | ||
911 | /* | |
912 | * Overruns cause FIFO pointers to become missaligned. | |
913 | * Flushing the receive FIFO reinitializes the pointers. | |
914 | */ | |
915 | writeb(UARTCFIFO_RXFLUSH, sport->port.membase + UARTCFIFO); | |
916 | writeb(UARTSFIFO_RXOF, sport->port.membase + UARTSFIFO); | |
917 | } | |
918 | ||
5697df73 | 919 | uart_unlock_and_check_sysrq(&sport->port); |
c9e2e946 JL |
920 | |
921 | tty_flip_buffer_push(port); | |
c9e2e946 JL |
922 | } |
923 | ||
93b9523a AS |
924 | static void lpuart32_txint(struct lpuart_port *sport) |
925 | { | |
0d84f622 | 926 | spin_lock(&sport->port.lock); |
93b9523a | 927 | lpuart32_transmit_buffer(sport); |
0d84f622 | 928 | spin_unlock(&sport->port.lock); |
93b9523a AS |
929 | } |
930 | ||
3993ddc2 | 931 | static void lpuart32_rxint(struct lpuart_port *sport) |
380c966c | 932 | { |
380c966c JL |
933 | unsigned int flg, ignored = 0; |
934 | struct tty_port *port = &sport->port.state->port; | |
380c966c | 935 | unsigned long rx, sr; |
5541a9ba | 936 | bool is_break; |
380c966c | 937 | |
0d84f622 | 938 | spin_lock(&sport->port.lock); |
380c966c | 939 | |
a0204f25 | 940 | while (!(lpuart32_read(&sport->port, UARTFIFO) & UARTFIFO_RXEMPT)) { |
380c966c JL |
941 | flg = TTY_NORMAL; |
942 | sport->port.icount.rx++; | |
943 | /* | |
944 | * to clear the FE, OR, NF, FE, PE flags, | |
945 | * read STAT then read DATA reg | |
946 | */ | |
a0204f25 DA |
947 | sr = lpuart32_read(&sport->port, UARTSTAT); |
948 | rx = lpuart32_read(&sport->port, UARTDATA); | |
ec22c3ee | 949 | rx &= UARTDATA_MASK; |
380c966c | 950 | |
5541a9ba MW |
951 | /* |
952 | * The LPUART can't distinguish between a break and a framing error, | |
953 | * thus we assume it is a break if the received data is zero. | |
954 | */ | |
955 | is_break = (sr & UARTSTAT_FE) && !rx; | |
956 | ||
957 | if (is_break && uart_handle_break(&sport->port)) | |
958 | continue; | |
959 | ||
5697df73 | 960 | if (uart_prepare_sysrq_char(&sport->port, rx)) |
380c966c JL |
961 | continue; |
962 | ||
963 | if (sr & (UARTSTAT_PE | UARTSTAT_OR | UARTSTAT_FE)) { | |
5541a9ba | 964 | if (sr & UARTSTAT_PE) { |
707f816f SS |
965 | sport->port.icount.parity++; |
966 | } else if (sr & UARTSTAT_FE) { | |
5541a9ba MW |
967 | if (is_break) |
968 | sport->port.icount.brk++; | |
969 | else | |
707f816f | 970 | sport->port.icount.frame++; |
5541a9ba | 971 | } |
380c966c JL |
972 | |
973 | if (sr & UARTSTAT_OR) | |
974 | sport->port.icount.overrun++; | |
975 | ||
976 | if (sr & sport->port.ignore_status_mask) { | |
977 | if (++ignored > 100) | |
978 | goto out; | |
979 | continue; | |
980 | } | |
981 | ||
982 | sr &= sport->port.read_status_mask; | |
983 | ||
5541a9ba | 984 | if (sr & UARTSTAT_PE) { |
707f816f SS |
985 | flg = TTY_PARITY; |
986 | } else if (sr & UARTSTAT_FE) { | |
5541a9ba MW |
987 | if (is_break) |
988 | flg = TTY_BREAK; | |
989 | else | |
707f816f | 990 | flg = TTY_FRAME; |
5541a9ba | 991 | } |
380c966c JL |
992 | |
993 | if (sr & UARTSTAT_OR) | |
994 | flg = TTY_OVERRUN; | |
380c966c JL |
995 | } |
996 | ||
070298c8 SW |
997 | if (sport->is_cs7) |
998 | rx &= 0x7F; | |
999 | ||
93cf538e SS |
1000 | if (tty_insert_flip_char(port, rx, flg) == 0) |
1001 | sport->port.icount.buf_overrun++; | |
380c966c JL |
1002 | } |
1003 | ||
1004 | out: | |
5697df73 | 1005 | uart_unlock_and_check_sysrq(&sport->port); |
380c966c JL |
1006 | |
1007 | tty_flip_buffer_push(port); | |
380c966c JL |
1008 | } |
1009 | ||
c9e2e946 JL |
1010 | static irqreturn_t lpuart_int(int irq, void *dev_id) |
1011 | { | |
1012 | struct lpuart_port *sport = dev_id; | |
5887ad43 | 1013 | unsigned char sts; |
c9e2e946 JL |
1014 | |
1015 | sts = readb(sport->port.membase + UARTSR1); | |
1016 | ||
f4eef224 AD |
1017 | /* SysRq, using dma, check for linebreak by framing err. */ |
1018 | if (sts & UARTSR1_FE && sport->lpuart_dma_rx_use) { | |
1019 | readb(sport->port.membase + UARTDR); | |
1020 | uart_handle_break(&sport->port); | |
1021 | /* linebreak produces some garbage, removing it */ | |
1022 | writeb(UARTCFIFO_RXFLUSH, sport->port.membase + UARTCFIFO); | |
1023 | return IRQ_HANDLED; | |
1024 | } | |
1025 | ||
6798e901 | 1026 | if (sts & UARTSR1_RDRF && !sport->lpuart_dma_rx_use) |
3993ddc2 | 1027 | lpuart_rxint(sport); |
5887ad43 | 1028 | |
6798e901 | 1029 | if (sts & UARTSR1_TDRE && !sport->lpuart_dma_tx_use) |
3993ddc2 | 1030 | lpuart_txint(sport); |
c9e2e946 JL |
1031 | |
1032 | return IRQ_HANDLED; | |
1033 | } | |
1034 | ||
380c966c JL |
1035 | static irqreturn_t lpuart32_int(int irq, void *dev_id) |
1036 | { | |
1037 | struct lpuart_port *sport = dev_id; | |
1038 | unsigned long sts, rxcount; | |
1039 | ||
a0204f25 DA |
1040 | sts = lpuart32_read(&sport->port, UARTSTAT); |
1041 | rxcount = lpuart32_read(&sport->port, UARTWATER); | |
380c966c JL |
1042 | rxcount = rxcount >> UARTWATER_RXCNT_OFF; |
1043 | ||
42b68768 | 1044 | if ((sts & UARTSTAT_RDRF || rxcount > 0) && !sport->lpuart_dma_rx_use) |
3993ddc2 | 1045 | lpuart32_rxint(sport); |
380c966c | 1046 | |
42b68768 | 1047 | if ((sts & UARTSTAT_TDRE) && !sport->lpuart_dma_tx_use) |
93b9523a | 1048 | lpuart32_txint(sport); |
380c966c | 1049 | |
a0204f25 | 1050 | lpuart32_write(&sport->port, sts, UARTSTAT); |
380c966c JL |
1051 | return IRQ_HANDLED; |
1052 | } | |
1053 | ||
f4eef224 AD |
1054 | |
1055 | static inline void lpuart_handle_sysrq_chars(struct uart_port *port, | |
1056 | unsigned char *p, int count) | |
1057 | { | |
1058 | while (count--) { | |
1059 | if (*p && uart_handle_sysrq_char(port, *p)) | |
1060 | return; | |
1061 | p++; | |
1062 | } | |
1063 | } | |
1064 | ||
1065 | static void lpuart_handle_sysrq(struct lpuart_port *sport) | |
1066 | { | |
1067 | struct circ_buf *ring = &sport->rx_ring; | |
1068 | int count; | |
1069 | ||
1070 | if (ring->head < ring->tail) { | |
1071 | count = sport->rx_sgl.length - ring->tail; | |
1072 | lpuart_handle_sysrq_chars(&sport->port, | |
1073 | ring->buf + ring->tail, count); | |
1074 | ring->tail = 0; | |
1075 | } | |
1076 | ||
1077 | if (ring->head > ring->tail) { | |
1078 | count = ring->head - ring->tail; | |
1079 | lpuart_handle_sysrq_chars(&sport->port, | |
1080 | ring->buf + ring->tail, count); | |
1081 | ring->tail = ring->head; | |
1082 | } | |
1083 | } | |
1084 | ||
070298c8 SW |
1085 | static int lpuart_tty_insert_flip_string(struct tty_port *port, |
1086 | unsigned char *chars, size_t size, bool is_cs7) | |
1087 | { | |
1088 | int i; | |
1089 | ||
1090 | if (is_cs7) | |
1091 | for (i = 0; i < size; i++) | |
1092 | chars[i] &= 0x7F; | |
1093 | return tty_insert_flip_string(port, chars, size); | |
1094 | } | |
1095 | ||
5887ad43 BD |
1096 | static void lpuart_copy_rx_to_tty(struct lpuart_port *sport) |
1097 | { | |
1098 | struct tty_port *port = &sport->port.state->port; | |
1099 | struct dma_tx_state state; | |
1100 | enum dma_status dmastat; | |
a092ab25 | 1101 | struct dma_chan *chan = sport->dma_rx_chan; |
5887ad43 BD |
1102 | struct circ_buf *ring = &sport->rx_ring; |
1103 | unsigned long flags; | |
c1b41481 | 1104 | int count, copied; |
5887ad43 | 1105 | |
42b68768 AN |
1106 | if (lpuart_is_32(sport)) { |
1107 | unsigned long sr = lpuart32_read(&sport->port, UARTSTAT); | |
5887ad43 | 1108 | |
42b68768 AN |
1109 | if (sr & (UARTSTAT_PE | UARTSTAT_FE)) { |
1110 | /* Read DR to clear the error flags */ | |
1111 | lpuart32_read(&sport->port, UARTDATA); | |
1112 | ||
1113 | if (sr & UARTSTAT_PE) | |
1114 | sport->port.icount.parity++; | |
1115 | else if (sr & UARTSTAT_FE) | |
1116 | sport->port.icount.frame++; | |
1117 | } | |
1118 | } else { | |
1119 | unsigned char sr = readb(sport->port.membase + UARTSR1); | |
1120 | ||
1121 | if (sr & (UARTSR1_PE | UARTSR1_FE)) { | |
65632179 SA |
1122 | unsigned char cr2; |
1123 | ||
1124 | /* Disable receiver during this operation... */ | |
1125 | cr2 = readb(sport->port.membase + UARTCR2); | |
1126 | cr2 &= ~UARTCR2_RE; | |
1127 | writeb(cr2, sport->port.membase + UARTCR2); | |
1128 | ||
42b68768 AN |
1129 | /* Read DR to clear the error flags */ |
1130 | readb(sport->port.membase + UARTDR); | |
5887ad43 | 1131 | |
42b68768 AN |
1132 | if (sr & UARTSR1_PE) |
1133 | sport->port.icount.parity++; | |
1134 | else if (sr & UARTSR1_FE) | |
1135 | sport->port.icount.frame++; | |
65632179 SA |
1136 | /* |
1137 | * At this point parity/framing error is | |
1138 | * cleared However, since the DMA already read | |
1139 | * the data register and we had to read it | |
1140 | * again after reading the status register to | |
1141 | * properly clear the flags, the FIFO actually | |
1142 | * underflowed... This requires a clearing of | |
1143 | * the FIFO... | |
1144 | */ | |
1145 | if (readb(sport->port.membase + UARTSFIFO) & | |
1146 | UARTSFIFO_RXUF) { | |
1147 | writeb(UARTSFIFO_RXUF, | |
1148 | sport->port.membase + UARTSFIFO); | |
1149 | writeb(UARTCFIFO_RXFLUSH, | |
1150 | sport->port.membase + UARTCFIFO); | |
1151 | } | |
1152 | ||
1153 | cr2 |= UARTCR2_RE; | |
1154 | writeb(cr2, sport->port.membase + UARTCR2); | |
42b68768 | 1155 | } |
5887ad43 BD |
1156 | } |
1157 | ||
1158 | async_tx_ack(sport->dma_rx_desc); | |
1159 | ||
1160 | spin_lock_irqsave(&sport->port.lock, flags); | |
1161 | ||
a092ab25 | 1162 | dmastat = dmaengine_tx_status(chan, sport->dma_rx_cookie, &state); |
5887ad43 BD |
1163 | if (dmastat == DMA_ERROR) { |
1164 | dev_err(sport->port.dev, "Rx DMA transfer failed!\n"); | |
1165 | spin_unlock_irqrestore(&sport->port.lock, flags); | |
1166 | return; | |
1167 | } | |
1168 | ||
1169 | /* CPU claims ownership of RX DMA buffer */ | |
a092ab25 MW |
1170 | dma_sync_sg_for_cpu(chan->device->dev, &sport->rx_sgl, 1, |
1171 | DMA_FROM_DEVICE); | |
5887ad43 BD |
1172 | |
1173 | /* | |
1174 | * ring->head points to the end of data already written by the DMA. | |
1175 | * ring->tail points to the beginning of data to be read by the | |
1176 | * framework. | |
1177 | * The current transfer size should not be larger than the dma buffer | |
1178 | * length. | |
1179 | */ | |
1180 | ring->head = sport->rx_sgl.length - state.residue; | |
1181 | BUG_ON(ring->head > sport->rx_sgl.length); | |
f4eef224 AD |
1182 | |
1183 | /* | |
1184 | * Silent handling of keys pressed in the sysrq timeframe | |
1185 | */ | |
1186 | if (sport->port.sysrq) { | |
1187 | lpuart_handle_sysrq(sport); | |
1188 | goto exit; | |
1189 | } | |
1190 | ||
5887ad43 BD |
1191 | /* |
1192 | * At this point ring->head may point to the first byte right after the | |
1193 | * last byte of the dma buffer: | |
1194 | * 0 <= ring->head <= sport->rx_sgl.length | |
1195 | * | |
1196 | * However ring->tail must always points inside the dma buffer: | |
1197 | * 0 <= ring->tail <= sport->rx_sgl.length - 1 | |
1198 | * | |
1199 | * Since we use a ring buffer, we have to handle the case | |
1200 | * where head is lower than tail. In such a case, we first read from | |
1201 | * tail to the end of the buffer then reset tail. | |
1202 | */ | |
1203 | if (ring->head < ring->tail) { | |
1204 | count = sport->rx_sgl.length - ring->tail; | |
1205 | ||
070298c8 SW |
1206 | copied = lpuart_tty_insert_flip_string(port, ring->buf + ring->tail, |
1207 | count, sport->is_cs7); | |
93cf538e SS |
1208 | if (copied != count) |
1209 | sport->port.icount.buf_overrun++; | |
5887ad43 | 1210 | ring->tail = 0; |
93cf538e | 1211 | sport->port.icount.rx += copied; |
5887ad43 BD |
1212 | } |
1213 | ||
1214 | /* Finally we read data from tail to head */ | |
1215 | if (ring->tail < ring->head) { | |
1216 | count = ring->head - ring->tail; | |
070298c8 SW |
1217 | copied = lpuart_tty_insert_flip_string(port, ring->buf + ring->tail, |
1218 | count, sport->is_cs7); | |
93cf538e SS |
1219 | if (copied != count) |
1220 | sport->port.icount.buf_overrun++; | |
5887ad43 BD |
1221 | /* Wrap ring->head if needed */ |
1222 | if (ring->head >= sport->rx_sgl.length) | |
1223 | ring->head = 0; | |
1224 | ring->tail = ring->head; | |
93cf538e | 1225 | sport->port.icount.rx += copied; |
5887ad43 BD |
1226 | } |
1227 | ||
f4eef224 | 1228 | exit: |
a092ab25 | 1229 | dma_sync_sg_for_device(chan->device->dev, &sport->rx_sgl, 1, |
5887ad43 BD |
1230 | DMA_FROM_DEVICE); |
1231 | ||
1232 | spin_unlock_irqrestore(&sport->port.lock, flags); | |
1233 | ||
1234 | tty_flip_buffer_push(port); | |
1235 | mod_timer(&sport->lpuart_timer, jiffies + sport->dma_rx_timeout); | |
1236 | } | |
1237 | ||
1238 | static void lpuart_dma_rx_complete(void *arg) | |
1239 | { | |
1240 | struct lpuart_port *sport = arg; | |
1241 | ||
1242 | lpuart_copy_rx_to_tty(sport); | |
1243 | } | |
1244 | ||
e99e88a9 | 1245 | static void lpuart_timer_func(struct timer_list *t) |
5887ad43 | 1246 | { |
e99e88a9 | 1247 | struct lpuart_port *sport = from_timer(sport, t, lpuart_timer); |
5887ad43 BD |
1248 | |
1249 | lpuart_copy_rx_to_tty(sport); | |
1250 | } | |
1251 | ||
1252 | static inline int lpuart_start_rx_dma(struct lpuart_port *sport) | |
1253 | { | |
1254 | struct dma_slave_config dma_rx_sconfig = {}; | |
1255 | struct circ_buf *ring = &sport->rx_ring; | |
1256 | int ret, nent; | |
3216c622 SA |
1257 | struct tty_port *port = &sport->port.state->port; |
1258 | struct tty_struct *tty = port->tty; | |
5887ad43 | 1259 | struct ktermios *termios = &tty->termios; |
a092ab25 | 1260 | struct dma_chan *chan = sport->dma_rx_chan; |
d4be10c8 IJ |
1261 | unsigned int bits = tty_get_frame_size(termios->c_cflag); |
1262 | unsigned int baud = tty_get_baud_rate(tty); | |
5887ad43 BD |
1263 | |
1264 | /* | |
1265 | * Calculate length of one DMA buffer size to keep latency below | |
1266 | * 10ms at any baud rate. | |
1267 | */ | |
1268 | sport->rx_dma_rng_buf_len = (DMA_RX_TIMEOUT * baud / bits / 1000) * 2; | |
1269 | sport->rx_dma_rng_buf_len = (1 << (fls(sport->rx_dma_rng_buf_len) - 1)); | |
1270 | if (sport->rx_dma_rng_buf_len < 16) | |
1271 | sport->rx_dma_rng_buf_len = 16; | |
1272 | ||
ca8d92f6 | 1273 | ring->buf = kzalloc(sport->rx_dma_rng_buf_len, GFP_ATOMIC); |
099f79c0 | 1274 | if (!ring->buf) |
5887ad43 | 1275 | return -ENOMEM; |
5887ad43 BD |
1276 | |
1277 | sg_init_one(&sport->rx_sgl, ring->buf, sport->rx_dma_rng_buf_len); | |
a092ab25 MW |
1278 | nent = dma_map_sg(chan->device->dev, &sport->rx_sgl, 1, |
1279 | DMA_FROM_DEVICE); | |
5887ad43 BD |
1280 | |
1281 | if (!nent) { | |
1282 | dev_err(sport->port.dev, "DMA Rx mapping error\n"); | |
1283 | return -EINVAL; | |
1284 | } | |
1285 | ||
42b68768 | 1286 | dma_rx_sconfig.src_addr = lpuart_dma_datareg_addr(sport); |
5887ad43 BD |
1287 | dma_rx_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; |
1288 | dma_rx_sconfig.src_maxburst = 1; | |
1289 | dma_rx_sconfig.direction = DMA_DEV_TO_MEM; | |
a092ab25 | 1290 | ret = dmaengine_slave_config(chan, &dma_rx_sconfig); |
5887ad43 BD |
1291 | |
1292 | if (ret < 0) { | |
1293 | dev_err(sport->port.dev, | |
1294 | "DMA Rx slave config failed, err = %d\n", ret); | |
1295 | return ret; | |
1296 | } | |
1297 | ||
a092ab25 | 1298 | sport->dma_rx_desc = dmaengine_prep_dma_cyclic(chan, |
5887ad43 BD |
1299 | sg_dma_address(&sport->rx_sgl), |
1300 | sport->rx_sgl.length, | |
1301 | sport->rx_sgl.length / 2, | |
1302 | DMA_DEV_TO_MEM, | |
1303 | DMA_PREP_INTERRUPT); | |
1304 | if (!sport->dma_rx_desc) { | |
1305 | dev_err(sport->port.dev, "Cannot prepare cyclic DMA\n"); | |
1306 | return -EFAULT; | |
1307 | } | |
1308 | ||
1309 | sport->dma_rx_desc->callback = lpuart_dma_rx_complete; | |
1310 | sport->dma_rx_desc->callback_param = sport; | |
1311 | sport->dma_rx_cookie = dmaengine_submit(sport->dma_rx_desc); | |
a092ab25 | 1312 | dma_async_issue_pending(chan); |
5887ad43 | 1313 | |
42b68768 AN |
1314 | if (lpuart_is_32(sport)) { |
1315 | unsigned long temp = lpuart32_read(&sport->port, UARTBAUD); | |
1316 | ||
1317 | lpuart32_write(&sport->port, temp | UARTBAUD_RDMAE, UARTBAUD); | |
1318 | } else { | |
1319 | writeb(readb(sport->port.membase + UARTCR5) | UARTCR5_RDMAS, | |
1320 | sport->port.membase + UARTCR5); | |
1321 | } | |
5887ad43 BD |
1322 | |
1323 | return 0; | |
1324 | } | |
1325 | ||
5887ad43 BD |
1326 | static void lpuart_dma_rx_free(struct uart_port *port) |
1327 | { | |
1328 | struct lpuart_port *sport = container_of(port, | |
1329 | struct lpuart_port, port); | |
a092ab25 | 1330 | struct dma_chan *chan = sport->dma_rx_chan; |
5887ad43 | 1331 | |
8682ab0e | 1332 | dmaengine_terminate_sync(chan); |
a092ab25 | 1333 | dma_unmap_sg(chan->device->dev, &sport->rx_sgl, 1, DMA_FROM_DEVICE); |
5887ad43 BD |
1334 | kfree(sport->rx_ring.buf); |
1335 | sport->rx_ring.tail = 0; | |
1336 | sport->rx_ring.head = 0; | |
1337 | sport->dma_rx_desc = NULL; | |
1338 | sport->dma_rx_cookie = -EINVAL; | |
1339 | } | |
1340 | ||
ae50bb27 | 1341 | static int lpuart_config_rs485(struct uart_port *port, struct ktermios *termios, |
03895cf4 BD |
1342 | struct serial_rs485 *rs485) |
1343 | { | |
1344 | struct lpuart_port *sport = container_of(port, | |
1345 | struct lpuart_port, port); | |
1346 | ||
1347 | u8 modem = readb(sport->port.membase + UARTMODEM) & | |
1348 | ~(UARTMODEM_TXRTSPOL | UARTMODEM_TXRTSE); | |
1349 | writeb(modem, sport->port.membase + UARTMODEM); | |
1350 | ||
1351 | if (rs485->flags & SER_RS485_ENABLED) { | |
1352 | /* Enable auto RS-485 RTS mode */ | |
1353 | modem |= UARTMODEM_TXRTSE; | |
1354 | ||
03895cf4 BD |
1355 | /* |
1356 | * The hardware defaults to RTS logic HIGH while transfer. | |
1357 | * Switch polarity in case RTS shall be logic HIGH | |
1358 | * after transfer. | |
1359 | * Note: UART is assumed to be active high. | |
1360 | */ | |
1361 | if (rs485->flags & SER_RS485_RTS_ON_SEND) | |
03895cf4 | 1362 | modem |= UARTMODEM_TXRTSPOL; |
846651ec SW |
1363 | else if (rs485->flags & SER_RS485_RTS_AFTER_SEND) |
1364 | modem &= ~UARTMODEM_TXRTSPOL; | |
03895cf4 BD |
1365 | } |
1366 | ||
03895cf4 BD |
1367 | writeb(modem, sport->port.membase + UARTMODEM); |
1368 | return 0; | |
1369 | } | |
1370 | ||
ae50bb27 | 1371 | static int lpuart32_config_rs485(struct uart_port *port, struct ktermios *termios, |
67b01837 PS |
1372 | struct serial_rs485 *rs485) |
1373 | { | |
1374 | struct lpuart_port *sport = container_of(port, | |
1375 | struct lpuart_port, port); | |
1376 | ||
1377 | unsigned long modem = lpuart32_read(&sport->port, UARTMODIR) | |
1378 | & ~(UARTMODEM_TXRTSPOL | UARTMODEM_TXRTSE); | |
1379 | lpuart32_write(&sport->port, modem, UARTMODIR); | |
1380 | ||
67b01837 PS |
1381 | if (rs485->flags & SER_RS485_ENABLED) { |
1382 | /* Enable auto RS-485 RTS mode */ | |
1383 | modem |= UARTMODEM_TXRTSE; | |
1384 | ||
67b01837 PS |
1385 | /* |
1386 | * The hardware defaults to RTS logic HIGH while transfer. | |
1387 | * Switch polarity in case RTS shall be logic HIGH | |
1388 | * after transfer. | |
1389 | * Note: UART is assumed to be active high. | |
1390 | */ | |
1391 | if (rs485->flags & SER_RS485_RTS_ON_SEND) | |
1392 | modem &= ~UARTMODEM_TXRTSPOL; | |
1393 | else if (rs485->flags & SER_RS485_RTS_AFTER_SEND) | |
1394 | modem |= UARTMODEM_TXRTSPOL; | |
1395 | } | |
1396 | ||
67b01837 PS |
1397 | lpuart32_write(&sport->port, modem, UARTMODIR); |
1398 | return 0; | |
1399 | } | |
1400 | ||
c9e2e946 JL |
1401 | static unsigned int lpuart_get_mctrl(struct uart_port *port) |
1402 | { | |
8a0c810d MW |
1403 | unsigned int mctrl = 0; |
1404 | u8 reg; | |
1405 | ||
1406 | reg = readb(port->membase + UARTCR1); | |
1407 | if (reg & UARTCR1_LOOPS) | |
1408 | mctrl |= TIOCM_LOOP; | |
1409 | ||
1410 | return mctrl; | |
c9e2e946 JL |
1411 | } |
1412 | ||
380c966c JL |
1413 | static unsigned int lpuart32_get_mctrl(struct uart_port *port) |
1414 | { | |
06e91df1 | 1415 | unsigned int mctrl = TIOCM_CAR | TIOCM_DSR | TIOCM_CTS; |
8a0c810d MW |
1416 | u32 reg; |
1417 | ||
1418 | reg = lpuart32_read(port, UARTCTRL); | |
1419 | if (reg & UARTCTRL_LOOPS) | |
1420 | mctrl |= TIOCM_LOOP; | |
1421 | ||
1422 | return mctrl; | |
380c966c JL |
1423 | } |
1424 | ||
c9e2e946 JL |
1425 | static void lpuart_set_mctrl(struct uart_port *port, unsigned int mctrl) |
1426 | { | |
8a0c810d MW |
1427 | u8 reg; |
1428 | ||
1429 | reg = readb(port->membase + UARTCR1); | |
1430 | ||
1431 | /* for internal loopback we need LOOPS=1 and RSRC=0 */ | |
1432 | reg &= ~(UARTCR1_LOOPS | UARTCR1_RSRC); | |
1433 | if (mctrl & TIOCM_LOOP) | |
1434 | reg |= UARTCR1_LOOPS; | |
c9e2e946 | 1435 | |
8a0c810d | 1436 | writeb(reg, port->membase + UARTCR1); |
c9e2e946 JL |
1437 | } |
1438 | ||
380c966c JL |
1439 | static void lpuart32_set_mctrl(struct uart_port *port, unsigned int mctrl) |
1440 | { | |
8a0c810d MW |
1441 | u32 reg; |
1442 | ||
1443 | reg = lpuart32_read(port, UARTCTRL); | |
1444 | ||
1445 | /* for internal loopback we need LOOPS=1 and RSRC=0 */ | |
1446 | reg &= ~(UARTCTRL_LOOPS | UARTCTRL_RSRC); | |
1447 | if (mctrl & TIOCM_LOOP) | |
1448 | reg |= UARTCTRL_LOOPS; | |
380c966c | 1449 | |
8a0c810d | 1450 | lpuart32_write(port, reg, UARTCTRL); |
380c966c JL |
1451 | } |
1452 | ||
c9e2e946 JL |
1453 | static void lpuart_break_ctl(struct uart_port *port, int break_state) |
1454 | { | |
1455 | unsigned char temp; | |
1456 | ||
1457 | temp = readb(port->membase + UARTCR2) & ~UARTCR2_SBK; | |
1458 | ||
1459 | if (break_state != 0) | |
1460 | temp |= UARTCR2_SBK; | |
1461 | ||
1462 | writeb(temp, port->membase + UARTCR2); | |
1463 | } | |
1464 | ||
380c966c JL |
1465 | static void lpuart32_break_ctl(struct uart_port *port, int break_state) |
1466 | { | |
1467 | unsigned long temp; | |
1468 | ||
a0204f25 | 1469 | temp = lpuart32_read(port, UARTCTRL) & ~UARTCTRL_SBK; |
380c966c JL |
1470 | |
1471 | if (break_state != 0) | |
1472 | temp |= UARTCTRL_SBK; | |
1473 | ||
a0204f25 | 1474 | lpuart32_write(port, temp, UARTCTRL); |
380c966c JL |
1475 | } |
1476 | ||
c9e2e946 JL |
1477 | static void lpuart_setup_watermark(struct lpuart_port *sport) |
1478 | { | |
1479 | unsigned char val, cr2; | |
bc764b8f | 1480 | unsigned char cr2_saved; |
c9e2e946 JL |
1481 | |
1482 | cr2 = readb(sport->port.membase + UARTCR2); | |
bc764b8f | 1483 | cr2_saved = cr2; |
c9e2e946 JL |
1484 | cr2 &= ~(UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_TE | |
1485 | UARTCR2_RIE | UARTCR2_RE); | |
1486 | writeb(cr2, sport->port.membase + UARTCR2); | |
1487 | ||
c9e2e946 | 1488 | val = readb(sport->port.membase + UARTPFIFO); |
c9e2e946 JL |
1489 | writeb(val | UARTPFIFO_TXFE | UARTPFIFO_RXFE, |
1490 | sport->port.membase + UARTPFIFO); | |
1491 | ||
1492 | /* flush Tx and Rx FIFO */ | |
1493 | writeb(UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH, | |
1494 | sport->port.membase + UARTCFIFO); | |
1495 | ||
d68827c6 SA |
1496 | /* explicitly clear RDRF */ |
1497 | if (readb(sport->port.membase + UARTSR1) & UARTSR1_RDRF) { | |
1498 | readb(sport->port.membase + UARTDR); | |
1499 | writeb(UARTSFIFO_RXUF, sport->port.membase + UARTSFIFO); | |
1500 | } | |
1501 | ||
f1cd8c87 | 1502 | writeb(0, sport->port.membase + UARTTWFIFO); |
c9e2e946 | 1503 | writeb(1, sport->port.membase + UARTRWFIFO); |
bc764b8f SG |
1504 | |
1505 | /* Restore cr2 */ | |
1506 | writeb(cr2_saved, sport->port.membase + UARTCR2); | |
c9e2e946 JL |
1507 | } |
1508 | ||
352bd55e AS |
1509 | static void lpuart_setup_watermark_enable(struct lpuart_port *sport) |
1510 | { | |
1511 | unsigned char cr2; | |
1512 | ||
1513 | lpuart_setup_watermark(sport); | |
1514 | ||
1515 | cr2 = readb(sport->port.membase + UARTCR2); | |
f7ec1721 | 1516 | cr2 |= UARTCR2_RIE | UARTCR2_RE | UARTCR2_TE; |
352bd55e AS |
1517 | writeb(cr2, sport->port.membase + UARTCR2); |
1518 | } | |
1519 | ||
380c966c JL |
1520 | static void lpuart32_setup_watermark(struct lpuart_port *sport) |
1521 | { | |
1522 | unsigned long val, ctrl; | |
1523 | unsigned long ctrl_saved; | |
1524 | ||
a0204f25 | 1525 | ctrl = lpuart32_read(&sport->port, UARTCTRL); |
380c966c JL |
1526 | ctrl_saved = ctrl; |
1527 | ctrl &= ~(UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_TE | | |
e1d91dda | 1528 | UARTCTRL_RIE | UARTCTRL_RE | UARTCTRL_ILIE); |
a0204f25 | 1529 | lpuart32_write(&sport->port, ctrl, UARTCTRL); |
380c966c JL |
1530 | |
1531 | /* enable FIFO mode */ | |
a0204f25 | 1532 | val = lpuart32_read(&sport->port, UARTFIFO); |
380c966c JL |
1533 | val |= UARTFIFO_TXFE | UARTFIFO_RXFE; |
1534 | val |= UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH; | |
a0204f25 | 1535 | lpuart32_write(&sport->port, val, UARTFIFO); |
380c966c JL |
1536 | |
1537 | /* set the watermark */ | |
1538 | val = (0x1 << UARTWATER_RXWATER_OFF) | (0x0 << UARTWATER_TXWATER_OFF); | |
a0204f25 | 1539 | lpuart32_write(&sport->port, val, UARTWATER); |
380c966c JL |
1540 | |
1541 | /* Restore cr2 */ | |
a0204f25 | 1542 | lpuart32_write(&sport->port, ctrl_saved, UARTCTRL); |
380c966c JL |
1543 | } |
1544 | ||
352bd55e AS |
1545 | static void lpuart32_setup_watermark_enable(struct lpuart_port *sport) |
1546 | { | |
1547 | u32 temp; | |
1548 | ||
1549 | lpuart32_setup_watermark(sport); | |
1550 | ||
1551 | temp = lpuart32_read(&sport->port, UARTCTRL); | |
e1d91dda SS |
1552 | temp |= UARTCTRL_RE | UARTCTRL_TE; |
1553 | temp |= FIELD_PREP(UARTCTRL_IDLECFG, 0x7); | |
352bd55e AS |
1554 | lpuart32_write(&sport->port, temp, UARTCTRL); |
1555 | } | |
1556 | ||
5887ad43 | 1557 | static void rx_dma_timer_init(struct lpuart_port *sport) |
f1cd8c87 | 1558 | { |
834a9741 AS |
1559 | timer_setup(&sport->lpuart_timer, lpuart_timer_func, 0); |
1560 | sport->lpuart_timer.expires = jiffies + sport->dma_rx_timeout; | |
1561 | add_timer(&sport->lpuart_timer); | |
f1cd8c87 YY |
1562 | } |
1563 | ||
d0e7600b | 1564 | static void lpuart_request_dma(struct lpuart_port *sport) |
5982199c | 1565 | { |
159381df MW |
1566 | sport->dma_tx_chan = dma_request_chan(sport->port.dev, "tx"); |
1567 | if (IS_ERR(sport->dma_tx_chan)) { | |
44da0362 FE |
1568 | dev_dbg_once(sport->port.dev, |
1569 | "DMA tx channel request failed, operating without tx DMA (%ld)\n", | |
1570 | PTR_ERR(sport->dma_tx_chan)); | |
159381df | 1571 | sport->dma_tx_chan = NULL; |
159381df MW |
1572 | } |
1573 | ||
d0e7600b MW |
1574 | sport->dma_rx_chan = dma_request_chan(sport->port.dev, "rx"); |
1575 | if (IS_ERR(sport->dma_rx_chan)) { | |
44da0362 FE |
1576 | dev_dbg_once(sport->port.dev, |
1577 | "DMA rx channel request failed, operating without rx DMA (%ld)\n", | |
1578 | PTR_ERR(sport->dma_rx_chan)); | |
d0e7600b MW |
1579 | sport->dma_rx_chan = NULL; |
1580 | } | |
1581 | } | |
1582 | ||
1583 | static void lpuart_tx_dma_startup(struct lpuart_port *sport) | |
1584 | { | |
1585 | u32 uartbaud; | |
1586 | int ret; | |
1587 | ||
8cac2f6e MW |
1588 | if (uart_console(&sport->port)) |
1589 | goto err; | |
1590 | ||
d0e7600b MW |
1591 | if (!sport->dma_tx_chan) |
1592 | goto err; | |
1593 | ||
159381df | 1594 | ret = lpuart_dma_tx_request(&sport->port); |
d7c53fb0 | 1595 | if (ret) |
159381df MW |
1596 | goto err; |
1597 | ||
1598 | init_waitqueue_head(&sport->dma_wait); | |
1599 | sport->lpuart_dma_tx_use = true; | |
1600 | if (lpuart_is_32(sport)) { | |
1601 | uartbaud = lpuart32_read(&sport->port, UARTBAUD); | |
1602 | lpuart32_write(&sport->port, | |
1603 | uartbaud | UARTBAUD_TDMAE, UARTBAUD); | |
5982199c | 1604 | } else { |
159381df MW |
1605 | writeb(readb(sport->port.membase + UARTCR5) | |
1606 | UARTCR5_TDMAS, sport->port.membase + UARTCR5); | |
5982199c | 1607 | } |
159381df MW |
1608 | |
1609 | return; | |
1610 | ||
1611 | err: | |
1612 | sport->lpuart_dma_tx_use = false; | |
5982199c AS |
1613 | } |
1614 | ||
fd60e8e4 AS |
1615 | static void lpuart_rx_dma_startup(struct lpuart_port *sport) |
1616 | { | |
159381df | 1617 | int ret; |
f4eef224 | 1618 | unsigned char cr3; |
fd60e8e4 | 1619 | |
8cac2f6e MW |
1620 | if (uart_console(&sport->port)) |
1621 | goto err; | |
1622 | ||
d0e7600b | 1623 | if (!sport->dma_rx_chan) |
159381df | 1624 | goto err; |
159381df MW |
1625 | |
1626 | ret = lpuart_start_rx_dma(sport); | |
1627 | if (ret) | |
1628 | goto err; | |
1629 | ||
1630 | /* set Rx DMA timeout */ | |
1631 | sport->dma_rx_timeout = msecs_to_jiffies(DMA_RX_TIMEOUT); | |
1632 | if (!sport->dma_rx_timeout) | |
1633 | sport->dma_rx_timeout = 1; | |
1634 | ||
1635 | sport->lpuart_dma_rx_use = true; | |
1636 | rx_dma_timer_init(sport); | |
1637 | ||
ccf08fd1 | 1638 | if (sport->port.has_sysrq && !lpuart_is_32(sport)) { |
f4eef224 AD |
1639 | cr3 = readb(sport->port.membase + UARTCR3); |
1640 | cr3 |= UARTCR3_FEIE; | |
1641 | writeb(cr3, sport->port.membase + UARTCR3); | |
1642 | } | |
1643 | ||
159381df MW |
1644 | return; |
1645 | ||
1646 | err: | |
1647 | sport->lpuart_dma_rx_use = false; | |
fd60e8e4 AS |
1648 | } |
1649 | ||
4f5cb8c5 SS |
1650 | static void lpuart_hw_setup(struct lpuart_port *sport) |
1651 | { | |
1652 | unsigned long flags; | |
1653 | ||
1654 | spin_lock_irqsave(&sport->port.lock, flags); | |
1655 | ||
1656 | lpuart_setup_watermark_enable(sport); | |
1657 | ||
1658 | lpuart_rx_dma_startup(sport); | |
1659 | lpuart_tx_dma_startup(sport); | |
1660 | ||
1661 | spin_unlock_irqrestore(&sport->port.lock, flags); | |
1662 | } | |
1663 | ||
c9e2e946 JL |
1664 | static int lpuart_startup(struct uart_port *port) |
1665 | { | |
1666 | struct lpuart_port *sport = container_of(port, struct lpuart_port, port); | |
c9e2e946 JL |
1667 | unsigned char temp; |
1668 | ||
ed9891bf SA |
1669 | /* determine FIFO size and enable FIFO mode */ |
1670 | temp = readb(sport->port.membase + UARTPFIFO); | |
1671 | ||
f77ebb24 FD |
1672 | sport->txfifo_size = UARTFIFO_DEPTH((temp >> UARTPFIFO_TXSIZE_OFF) & |
1673 | UARTPFIFO_FIFOSIZE_MASK); | |
4e8f2459 SA |
1674 | sport->port.fifosize = sport->txfifo_size; |
1675 | ||
f77ebb24 FD |
1676 | sport->rxfifo_size = UARTFIFO_DEPTH((temp >> UARTPFIFO_RXSIZE_OFF) & |
1677 | UARTPFIFO_FIFOSIZE_MASK); | |
ed9891bf | 1678 | |
d0e7600b | 1679 | lpuart_request_dma(sport); |
4f5cb8c5 | 1680 | lpuart_hw_setup(sport); |
5887ad43 | 1681 | |
c9e2e946 JL |
1682 | return 0; |
1683 | } | |
1684 | ||
4ff69041 AS |
1685 | static void lpuart32_configure(struct lpuart_port *sport) |
1686 | { | |
1687 | unsigned long temp; | |
1688 | ||
1689 | if (sport->lpuart_dma_rx_use) { | |
1690 | /* RXWATER must be 0 */ | |
1691 | temp = lpuart32_read(&sport->port, UARTWATER); | |
1692 | temp &= ~(UARTWATER_WATER_MASK << UARTWATER_RXWATER_OFF); | |
1693 | lpuart32_write(&sport->port, temp, UARTWATER); | |
1694 | } | |
1695 | temp = lpuart32_read(&sport->port, UARTCTRL); | |
1696 | if (!sport->lpuart_dma_rx_use) | |
e1d91dda | 1697 | temp |= UARTCTRL_RIE | UARTCTRL_ILIE; |
4ff69041 AS |
1698 | if (!sport->lpuart_dma_tx_use) |
1699 | temp |= UARTCTRL_TIE; | |
1700 | lpuart32_write(&sport->port, temp, UARTCTRL); | |
1701 | } | |
1702 | ||
4f5cb8c5 SS |
1703 | static void lpuart32_hw_setup(struct lpuart_port *sport) |
1704 | { | |
1705 | unsigned long flags; | |
1706 | ||
1707 | spin_lock_irqsave(&sport->port.lock, flags); | |
1708 | ||
1709 | lpuart32_setup_watermark_enable(sport); | |
1710 | ||
1711 | lpuart_rx_dma_startup(sport); | |
1712 | lpuart_tx_dma_startup(sport); | |
1713 | ||
1714 | lpuart32_configure(sport); | |
1715 | ||
1716 | spin_unlock_irqrestore(&sport->port.lock, flags); | |
1717 | } | |
1718 | ||
380c966c JL |
1719 | static int lpuart32_startup(struct uart_port *port) |
1720 | { | |
1721 | struct lpuart_port *sport = container_of(port, struct lpuart_port, port); | |
380c966c JL |
1722 | unsigned long temp; |
1723 | ||
1724 | /* determine FIFO size */ | |
a0204f25 | 1725 | temp = lpuart32_read(&sport->port, UARTFIFO); |
380c966c | 1726 | |
f77ebb24 FD |
1727 | sport->txfifo_size = UARTFIFO_DEPTH((temp >> UARTFIFO_TXSIZE_OFF) & |
1728 | UARTFIFO_FIFOSIZE_MASK); | |
b0b2735a AN |
1729 | sport->port.fifosize = sport->txfifo_size; |
1730 | ||
f77ebb24 FD |
1731 | sport->rxfifo_size = UARTFIFO_DEPTH((temp >> UARTFIFO_RXSIZE_OFF) & |
1732 | UARTFIFO_FIFOSIZE_MASK); | |
380c966c | 1733 | |
c2f448cf | 1734 | /* |
c97f2a6f VO |
1735 | * The LS1021A and LS1028A have a fixed FIFO depth of 16 words. |
1736 | * Although they support the RX/TXSIZE fields, their encoding is | |
1737 | * different. Eg the reference manual states 0b101 is 16 words. | |
c2f448cf | 1738 | */ |
c97f2a6f | 1739 | if (is_layerscape_lpuart(sport)) { |
c2f448cf MW |
1740 | sport->rxfifo_size = 16; |
1741 | sport->txfifo_size = 16; | |
1742 | sport->port.fifosize = sport->txfifo_size; | |
1743 | } | |
1744 | ||
d0e7600b | 1745 | lpuart_request_dma(sport); |
4f5cb8c5 | 1746 | lpuart32_hw_setup(sport); |
d0e7600b | 1747 | |
380c966c JL |
1748 | return 0; |
1749 | } | |
1750 | ||
769d55c5 AS |
1751 | static void lpuart_dma_shutdown(struct lpuart_port *sport) |
1752 | { | |
1753 | if (sport->lpuart_dma_rx_use) { | |
1754 | del_timer_sync(&sport->lpuart_timer); | |
1755 | lpuart_dma_rx_free(&sport->port); | |
316ae95c | 1756 | sport->lpuart_dma_rx_use = false; |
769d55c5 AS |
1757 | } |
1758 | ||
1759 | if (sport->lpuart_dma_tx_use) { | |
ffccc78a SS |
1760 | if (wait_event_interruptible_timeout(sport->dma_wait, |
1761 | !sport->dma_tx_in_progress, msecs_to_jiffies(300)) <= 0) { | |
769d55c5 | 1762 | sport->dma_tx_in_progress = false; |
8682ab0e | 1763 | dmaengine_terminate_sync(sport->dma_tx_chan); |
769d55c5 | 1764 | } |
316ae95c | 1765 | sport->lpuart_dma_tx_use = false; |
769d55c5 | 1766 | } |
159381df MW |
1767 | |
1768 | if (sport->dma_tx_chan) | |
1769 | dma_release_channel(sport->dma_tx_chan); | |
1770 | if (sport->dma_rx_chan) | |
1771 | dma_release_channel(sport->dma_rx_chan); | |
769d55c5 AS |
1772 | } |
1773 | ||
c9e2e946 JL |
1774 | static void lpuart_shutdown(struct uart_port *port) |
1775 | { | |
1776 | struct lpuart_port *sport = container_of(port, struct lpuart_port, port); | |
1777 | unsigned char temp; | |
1778 | unsigned long flags; | |
1779 | ||
1780 | spin_lock_irqsave(&port->lock, flags); | |
1781 | ||
1782 | /* disable Rx/Tx and interrupts */ | |
1783 | temp = readb(port->membase + UARTCR2); | |
1784 | temp &= ~(UARTCR2_TE | UARTCR2_RE | | |
1785 | UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_RIE); | |
1786 | writeb(temp, port->membase + UARTCR2); | |
1787 | ||
1788 | spin_unlock_irqrestore(&port->lock, flags); | |
1789 | ||
769d55c5 | 1790 | lpuart_dma_shutdown(sport); |
c9e2e946 JL |
1791 | } |
1792 | ||
380c966c JL |
1793 | static void lpuart32_shutdown(struct uart_port *port) |
1794 | { | |
42b68768 AN |
1795 | struct lpuart_port *sport = |
1796 | container_of(port, struct lpuart_port, port); | |
380c966c JL |
1797 | unsigned long temp; |
1798 | unsigned long flags; | |
1799 | ||
1800 | spin_lock_irqsave(&port->lock, flags); | |
1801 | ||
4029dfc0 SS |
1802 | /* clear status */ |
1803 | temp = lpuart32_read(&sport->port, UARTSTAT); | |
1804 | lpuart32_write(&sport->port, temp, UARTSTAT); | |
1805 | ||
1d4bd0e4 SS |
1806 | /* disable Rx/Tx DMA */ |
1807 | temp = lpuart32_read(port, UARTBAUD); | |
1808 | temp &= ~(UARTBAUD_TDMAE | UARTBAUD_RDMAE); | |
1809 | lpuart32_write(port, temp, UARTBAUD); | |
1810 | ||
380c966c | 1811 | /* disable Rx/Tx and interrupts */ |
a0204f25 | 1812 | temp = lpuart32_read(port, UARTCTRL); |
e1d91dda | 1813 | temp &= ~(UARTCTRL_TE | UARTCTRL_RE | UARTCTRL_ILIE | |
380c966c | 1814 | UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_RIE); |
a0204f25 | 1815 | lpuart32_write(port, temp, UARTCTRL); |
380c966c JL |
1816 | |
1817 | spin_unlock_irqrestore(&port->lock, flags); | |
42b68768 | 1818 | |
769d55c5 | 1819 | lpuart_dma_shutdown(sport); |
380c966c JL |
1820 | } |
1821 | ||
c9e2e946 JL |
1822 | static void |
1823 | lpuart_set_termios(struct uart_port *port, struct ktermios *termios, | |
bec5b814 | 1824 | const struct ktermios *old) |
c9e2e946 JL |
1825 | { |
1826 | struct lpuart_port *sport = container_of(port, struct lpuart_port, port); | |
1827 | unsigned long flags; | |
aa9e7d78 | 1828 | unsigned char cr1, old_cr1, old_cr2, cr3, cr4, bdh, modem; |
c9e2e946 JL |
1829 | unsigned int baud; |
1830 | unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8; | |
1831 | unsigned int sbr, brfa; | |
1832 | ||
1833 | cr1 = old_cr1 = readb(sport->port.membase + UARTCR1); | |
1834 | old_cr2 = readb(sport->port.membase + UARTCR2); | |
aa9e7d78 | 1835 | cr3 = readb(sport->port.membase + UARTCR3); |
c9e2e946 JL |
1836 | cr4 = readb(sport->port.membase + UARTCR4); |
1837 | bdh = readb(sport->port.membase + UARTBDH); | |
1838 | modem = readb(sport->port.membase + UARTMODEM); | |
1839 | /* | |
1840 | * only support CS8 and CS7, and for CS7 must enable PE. | |
1841 | * supported mode: | |
1842 | * - (7,e/o,1) | |
1843 | * - (8,n,1) | |
1844 | * - (8,m/s,1) | |
1845 | * - (8,e/o,1) | |
1846 | */ | |
1847 | while ((termios->c_cflag & CSIZE) != CS8 && | |
1848 | (termios->c_cflag & CSIZE) != CS7) { | |
1849 | termios->c_cflag &= ~CSIZE; | |
1850 | termios->c_cflag |= old_csize; | |
1851 | old_csize = CS8; | |
1852 | } | |
1853 | ||
1854 | if ((termios->c_cflag & CSIZE) == CS8 || | |
1855 | (termios->c_cflag & CSIZE) == CS7) | |
1856 | cr1 = old_cr1 & ~UARTCR1_M; | |
1857 | ||
1858 | if (termios->c_cflag & CMSPAR) { | |
1859 | if ((termios->c_cflag & CSIZE) != CS8) { | |
1860 | termios->c_cflag &= ~CSIZE; | |
1861 | termios->c_cflag |= CS8; | |
1862 | } | |
1863 | cr1 |= UARTCR1_M; | |
1864 | } | |
1865 | ||
03895cf4 BD |
1866 | /* |
1867 | * When auto RS-485 RTS mode is enabled, | |
1868 | * hardware flow control need to be disabled. | |
1869 | */ | |
1870 | if (sport->port.rs485.flags & SER_RS485_ENABLED) | |
1871 | termios->c_cflag &= ~CRTSCTS; | |
1872 | ||
d26454ee | 1873 | if (termios->c_cflag & CRTSCTS) |
bcfa46bf | 1874 | modem |= UARTMODEM_RXRTSE | UARTMODEM_TXCTSE; |
d26454ee | 1875 | else |
c9e2e946 | 1876 | modem &= ~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE); |
c9e2e946 | 1877 | |
76e3f2ac | 1878 | termios->c_cflag &= ~CSTOPB; |
c9e2e946 JL |
1879 | |
1880 | /* parity must be enabled when CS7 to match 8-bits format */ | |
1881 | if ((termios->c_cflag & CSIZE) == CS7) | |
1882 | termios->c_cflag |= PARENB; | |
1883 | ||
bcfa46bf | 1884 | if (termios->c_cflag & PARENB) { |
c9e2e946 JL |
1885 | if (termios->c_cflag & CMSPAR) { |
1886 | cr1 &= ~UARTCR1_PE; | |
aa9e7d78 BD |
1887 | if (termios->c_cflag & PARODD) |
1888 | cr3 |= UARTCR3_T8; | |
1889 | else | |
1890 | cr3 &= ~UARTCR3_T8; | |
c9e2e946 JL |
1891 | } else { |
1892 | cr1 |= UARTCR1_PE; | |
1893 | if ((termios->c_cflag & CSIZE) == CS8) | |
1894 | cr1 |= UARTCR1_M; | |
1895 | if (termios->c_cflag & PARODD) | |
1896 | cr1 |= UARTCR1_PT; | |
1897 | else | |
1898 | cr1 &= ~UARTCR1_PT; | |
1899 | } | |
397bd921 AD |
1900 | } else { |
1901 | cr1 &= ~UARTCR1_PE; | |
c9e2e946 JL |
1902 | } |
1903 | ||
1904 | /* ask the core to calculate the divisor */ | |
1905 | baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16); | |
1906 | ||
54a44d54 NY |
1907 | /* |
1908 | * Need to update the Ring buffer length according to the selected | |
1909 | * baud rate and restart Rx DMA path. | |
1910 | * | |
1911 | * Since timer function acqures sport->port.lock, need to stop before | |
1912 | * acquring same lock because otherwise del_timer_sync() can deadlock. | |
1913 | */ | |
1914 | if (old && sport->lpuart_dma_rx_use) { | |
1915 | del_timer_sync(&sport->lpuart_timer); | |
1916 | lpuart_dma_rx_free(&sport->port); | |
1917 | } | |
1918 | ||
c9e2e946 JL |
1919 | spin_lock_irqsave(&sport->port.lock, flags); |
1920 | ||
1921 | sport->port.read_status_mask = 0; | |
1922 | if (termios->c_iflag & INPCK) | |
bcfa46bf | 1923 | sport->port.read_status_mask |= UARTSR1_FE | UARTSR1_PE; |
ef8b9ddc | 1924 | if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) |
c9e2e946 JL |
1925 | sport->port.read_status_mask |= UARTSR1_FE; |
1926 | ||
1927 | /* characters to ignore */ | |
1928 | sport->port.ignore_status_mask = 0; | |
1929 | if (termios->c_iflag & IGNPAR) | |
1930 | sport->port.ignore_status_mask |= UARTSR1_PE; | |
1931 | if (termios->c_iflag & IGNBRK) { | |
1932 | sport->port.ignore_status_mask |= UARTSR1_FE; | |
1933 | /* | |
1934 | * if we're ignoring parity and break indicators, | |
1935 | * ignore overruns too (for real raw support). | |
1936 | */ | |
1937 | if (termios->c_iflag & IGNPAR) | |
1938 | sport->port.ignore_status_mask |= UARTSR1_OR; | |
1939 | } | |
1940 | ||
1941 | /* update the per-port timeout */ | |
1942 | uart_update_timeout(port, termios->c_cflag, baud); | |
1943 | ||
1944 | /* wait transmit engin complete */ | |
56dd627f | 1945 | lpuart_wait_bit_set(&sport->port, UARTSR1, UARTSR1_TC); |
c9e2e946 JL |
1946 | |
1947 | /* disable transmit and receive */ | |
1948 | writeb(old_cr2 & ~(UARTCR2_TE | UARTCR2_RE), | |
1949 | sport->port.membase + UARTCR2); | |
1950 | ||
1951 | sbr = sport->port.uartclk / (16 * baud); | |
1952 | brfa = ((sport->port.uartclk - (16 * sbr * baud)) * 2) / baud; | |
1953 | bdh &= ~UARTBDH_SBR_MASK; | |
1954 | bdh |= (sbr >> 8) & 0x1F; | |
1955 | cr4 &= ~UARTCR4_BRFA_MASK; | |
1956 | brfa &= UARTCR4_BRFA_MASK; | |
1957 | writeb(cr4 | brfa, sport->port.membase + UARTCR4); | |
1958 | writeb(bdh, sport->port.membase + UARTBDH); | |
1959 | writeb(sbr & 0xFF, sport->port.membase + UARTBDL); | |
aa9e7d78 | 1960 | writeb(cr3, sport->port.membase + UARTCR3); |
c9e2e946 JL |
1961 | writeb(cr1, sport->port.membase + UARTCR1); |
1962 | writeb(modem, sport->port.membase + UARTMODEM); | |
1963 | ||
1964 | /* restore control register */ | |
1965 | writeb(old_cr2, sport->port.membase + UARTCR2); | |
1966 | ||
54a44d54 NY |
1967 | if (old && sport->lpuart_dma_rx_use) { |
1968 | if (!lpuart_start_rx_dma(sport)) | |
5887ad43 | 1969 | rx_dma_timer_init(sport); |
54a44d54 | 1970 | else |
5887ad43 | 1971 | sport->lpuart_dma_rx_use = false; |
5887ad43 BD |
1972 | } |
1973 | ||
c9e2e946 JL |
1974 | spin_unlock_irqrestore(&sport->port.lock, flags); |
1975 | } | |
1976 | ||
e33253f3 MW |
1977 | static void __lpuart32_serial_setbrg(struct uart_port *port, |
1978 | unsigned int baudrate, bool use_rx_dma, | |
1979 | bool use_tx_dma) | |
a6d7514b DA |
1980 | { |
1981 | u32 sbr, osr, baud_diff, tmp_osr, tmp_sbr, tmp_diff, tmp; | |
e33253f3 | 1982 | u32 clk = port->uartclk; |
a6d7514b DA |
1983 | |
1984 | /* | |
1985 | * The idea is to use the best OSR (over-sampling rate) possible. | |
1986 | * Note, OSR is typically hard-set to 16 in other LPUART instantiations. | |
1987 | * Loop to find the best OSR value possible, one that generates minimum | |
1988 | * baud_diff iterate through the rest of the supported values of OSR. | |
1989 | * | |
1990 | * Calculation Formula: | |
1991 | * Baud Rate = baud clock / ((OSR+1) × SBR) | |
1992 | */ | |
1993 | baud_diff = baudrate; | |
1994 | osr = 0; | |
1995 | sbr = 0; | |
1996 | ||
1997 | for (tmp_osr = 4; tmp_osr <= 32; tmp_osr++) { | |
1998 | /* calculate the temporary sbr value */ | |
1999 | tmp_sbr = (clk / (baudrate * tmp_osr)); | |
2000 | if (tmp_sbr == 0) | |
2001 | tmp_sbr = 1; | |
2002 | ||
2003 | /* | |
2004 | * calculate the baud rate difference based on the temporary | |
2005 | * osr and sbr values | |
2006 | */ | |
2007 | tmp_diff = clk / (tmp_osr * tmp_sbr) - baudrate; | |
2008 | ||
2009 | /* select best values between sbr and sbr+1 */ | |
2010 | tmp = clk / (tmp_osr * (tmp_sbr + 1)); | |
2011 | if (tmp_diff > (baudrate - tmp)) { | |
2012 | tmp_diff = baudrate - tmp; | |
2013 | tmp_sbr++; | |
2014 | } | |
2015 | ||
d10ee1d1 VS |
2016 | if (tmp_sbr > UARTBAUD_SBR_MASK) |
2017 | continue; | |
2018 | ||
a6d7514b DA |
2019 | if (tmp_diff <= baud_diff) { |
2020 | baud_diff = tmp_diff; | |
2021 | osr = tmp_osr; | |
2022 | sbr = tmp_sbr; | |
2023 | ||
2024 | if (!baud_diff) | |
2025 | break; | |
2026 | } | |
2027 | } | |
2028 | ||
2029 | /* handle buadrate outside acceptable rate */ | |
2030 | if (baud_diff > ((baudrate / 100) * 3)) | |
e33253f3 | 2031 | dev_warn(port->dev, |
a6d7514b DA |
2032 | "unacceptable baud rate difference of more than 3%%\n"); |
2033 | ||
e33253f3 | 2034 | tmp = lpuart32_read(port, UARTBAUD); |
a6d7514b DA |
2035 | |
2036 | if ((osr > 3) && (osr < 8)) | |
2037 | tmp |= UARTBAUD_BOTHEDGE; | |
2038 | ||
2039 | tmp &= ~(UARTBAUD_OSR_MASK << UARTBAUD_OSR_SHIFT); | |
bcfa46bf | 2040 | tmp |= ((osr-1) & UARTBAUD_OSR_MASK) << UARTBAUD_OSR_SHIFT; |
a6d7514b DA |
2041 | |
2042 | tmp &= ~UARTBAUD_SBR_MASK; | |
2043 | tmp |= sbr & UARTBAUD_SBR_MASK; | |
2044 | ||
e33253f3 | 2045 | if (!use_rx_dma) |
42b68768 | 2046 | tmp &= ~UARTBAUD_RDMAE; |
e33253f3 | 2047 | if (!use_tx_dma) |
42b68768 | 2048 | tmp &= ~UARTBAUD_TDMAE; |
a6d7514b | 2049 | |
e33253f3 MW |
2050 | lpuart32_write(port, tmp, UARTBAUD); |
2051 | } | |
2052 | ||
2053 | static void lpuart32_serial_setbrg(struct lpuart_port *sport, | |
2054 | unsigned int baudrate) | |
2055 | { | |
2056 | __lpuart32_serial_setbrg(&sport->port, baudrate, | |
2057 | sport->lpuart_dma_rx_use, | |
2058 | sport->lpuart_dma_tx_use); | |
a6d7514b DA |
2059 | } |
2060 | ||
e33253f3 | 2061 | |
380c966c JL |
2062 | static void |
2063 | lpuart32_set_termios(struct uart_port *port, struct ktermios *termios, | |
bec5b814 | 2064 | const struct ktermios *old) |
380c966c JL |
2065 | { |
2066 | struct lpuart_port *sport = container_of(port, struct lpuart_port, port); | |
2067 | unsigned long flags; | |
48422152 | 2068 | unsigned long ctrl, old_ctrl, bd, modem; |
380c966c JL |
2069 | unsigned int baud; |
2070 | unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8; | |
380c966c | 2071 | |
a0204f25 | 2072 | ctrl = old_ctrl = lpuart32_read(&sport->port, UARTCTRL); |
48422152 | 2073 | bd = lpuart32_read(&sport->port, UARTBAUD); |
a0204f25 | 2074 | modem = lpuart32_read(&sport->port, UARTMODIR); |
070298c8 | 2075 | sport->is_cs7 = false; |
380c966c JL |
2076 | /* |
2077 | * only support CS8 and CS7, and for CS7 must enable PE. | |
2078 | * supported mode: | |
2079 | * - (7,e/o,1) | |
2080 | * - (8,n,1) | |
2081 | * - (8,m/s,1) | |
2082 | * - (8,e/o,1) | |
2083 | */ | |
2084 | while ((termios->c_cflag & CSIZE) != CS8 && | |
2085 | (termios->c_cflag & CSIZE) != CS7) { | |
2086 | termios->c_cflag &= ~CSIZE; | |
2087 | termios->c_cflag |= old_csize; | |
2088 | old_csize = CS8; | |
2089 | } | |
2090 | ||
2091 | if ((termios->c_cflag & CSIZE) == CS8 || | |
2092 | (termios->c_cflag & CSIZE) == CS7) | |
2093 | ctrl = old_ctrl & ~UARTCTRL_M; | |
2094 | ||
2095 | if (termios->c_cflag & CMSPAR) { | |
2096 | if ((termios->c_cflag & CSIZE) != CS8) { | |
2097 | termios->c_cflag &= ~CSIZE; | |
2098 | termios->c_cflag |= CS8; | |
2099 | } | |
2100 | ctrl |= UARTCTRL_M; | |
2101 | } | |
2102 | ||
67b01837 PS |
2103 | /* |
2104 | * When auto RS-485 RTS mode is enabled, | |
2105 | * hardware flow control need to be disabled. | |
2106 | */ | |
2107 | if (sport->port.rs485.flags & SER_RS485_ENABLED) | |
2108 | termios->c_cflag &= ~CRTSCTS; | |
2109 | ||
503f418b IJ |
2110 | if (termios->c_cflag & CRTSCTS) |
2111 | modem |= UARTMODIR_RXRTSE | UARTMODIR_TXCTSE; | |
2112 | else | |
e3553fee | 2113 | modem &= ~(UARTMODIR_RXRTSE | UARTMODIR_TXCTSE); |
380c966c JL |
2114 | |
2115 | if (termios->c_cflag & CSTOPB) | |
48422152 FD |
2116 | bd |= UARTBAUD_SBNS; |
2117 | else | |
2118 | bd &= ~UARTBAUD_SBNS; | |
380c966c JL |
2119 | |
2120 | /* parity must be enabled when CS7 to match 8-bits format */ | |
2121 | if ((termios->c_cflag & CSIZE) == CS7) | |
2122 | termios->c_cflag |= PARENB; | |
2123 | ||
2124 | if ((termios->c_cflag & PARENB)) { | |
2125 | if (termios->c_cflag & CMSPAR) { | |
2126 | ctrl &= ~UARTCTRL_PE; | |
2127 | ctrl |= UARTCTRL_M; | |
2128 | } else { | |
61e169ee | 2129 | ctrl |= UARTCTRL_PE; |
380c966c JL |
2130 | if ((termios->c_cflag & CSIZE) == CS8) |
2131 | ctrl |= UARTCTRL_M; | |
2132 | if (termios->c_cflag & PARODD) | |
2133 | ctrl |= UARTCTRL_PT; | |
2134 | else | |
2135 | ctrl &= ~UARTCTRL_PT; | |
2136 | } | |
397bd921 AD |
2137 | } else { |
2138 | ctrl &= ~UARTCTRL_PE; | |
380c966c JL |
2139 | } |
2140 | ||
2141 | /* ask the core to calculate the divisor */ | |
815d835b | 2142 | baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 4); |
380c966c | 2143 | |
42b68768 AN |
2144 | /* |
2145 | * Need to update the Ring buffer length according to the selected | |
2146 | * baud rate and restart Rx DMA path. | |
2147 | * | |
2148 | * Since timer function acqures sport->port.lock, need to stop before | |
2149 | * acquring same lock because otherwise del_timer_sync() can deadlock. | |
2150 | */ | |
2151 | if (old && sport->lpuart_dma_rx_use) { | |
2152 | del_timer_sync(&sport->lpuart_timer); | |
2153 | lpuart_dma_rx_free(&sport->port); | |
2154 | } | |
2155 | ||
380c966c JL |
2156 | spin_lock_irqsave(&sport->port.lock, flags); |
2157 | ||
2158 | sport->port.read_status_mask = 0; | |
2159 | if (termios->c_iflag & INPCK) | |
bcfa46bf | 2160 | sport->port.read_status_mask |= UARTSTAT_FE | UARTSTAT_PE; |
380c966c JL |
2161 | if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) |
2162 | sport->port.read_status_mask |= UARTSTAT_FE; | |
2163 | ||
2164 | /* characters to ignore */ | |
2165 | sport->port.ignore_status_mask = 0; | |
2166 | if (termios->c_iflag & IGNPAR) | |
2167 | sport->port.ignore_status_mask |= UARTSTAT_PE; | |
2168 | if (termios->c_iflag & IGNBRK) { | |
2169 | sport->port.ignore_status_mask |= UARTSTAT_FE; | |
2170 | /* | |
2171 | * if we're ignoring parity and break indicators, | |
2172 | * ignore overruns too (for real raw support). | |
2173 | */ | |
2174 | if (termios->c_iflag & IGNPAR) | |
2175 | sport->port.ignore_status_mask |= UARTSTAT_OR; | |
2176 | } | |
2177 | ||
2178 | /* update the per-port timeout */ | |
2179 | uart_update_timeout(port, termios->c_cflag, baud); | |
2180 | ||
2181 | /* wait transmit engin complete */ | |
d5a2e083 | 2182 | lpuart32_write(&sport->port, 0, UARTMODIR); |
56dd627f | 2183 | lpuart32_wait_bit_set(&sport->port, UARTSTAT, UARTSTAT_TC); |
380c966c JL |
2184 | |
2185 | /* disable transmit and receive */ | |
a0204f25 DA |
2186 | lpuart32_write(&sport->port, old_ctrl & ~(UARTCTRL_TE | UARTCTRL_RE), |
2187 | UARTCTRL); | |
380c966c | 2188 | |
48422152 | 2189 | lpuart32_write(&sport->port, bd, UARTBAUD); |
a6d7514b | 2190 | lpuart32_serial_setbrg(sport, baud); |
a0204f25 DA |
2191 | lpuart32_write(&sport->port, modem, UARTMODIR); |
2192 | lpuart32_write(&sport->port, ctrl, UARTCTRL); | |
380c966c JL |
2193 | /* restore control register */ |
2194 | ||
070298c8 SW |
2195 | if ((ctrl & (UARTCTRL_PE | UARTCTRL_M)) == UARTCTRL_PE) |
2196 | sport->is_cs7 = true; | |
2197 | ||
42b68768 AN |
2198 | if (old && sport->lpuart_dma_rx_use) { |
2199 | if (!lpuart_start_rx_dma(sport)) | |
2200 | rx_dma_timer_init(sport); | |
2201 | else | |
2202 | sport->lpuart_dma_rx_use = false; | |
2203 | } | |
2204 | ||
380c966c JL |
2205 | spin_unlock_irqrestore(&sport->port.lock, flags); |
2206 | } | |
2207 | ||
c9e2e946 JL |
2208 | static const char *lpuart_type(struct uart_port *port) |
2209 | { | |
2210 | return "FSL_LPUART"; | |
2211 | } | |
2212 | ||
2213 | static void lpuart_release_port(struct uart_port *port) | |
2214 | { | |
2215 | /* nothing to do */ | |
2216 | } | |
2217 | ||
2218 | static int lpuart_request_port(struct uart_port *port) | |
2219 | { | |
2220 | return 0; | |
2221 | } | |
2222 | ||
2223 | /* configure/autoconfigure the port */ | |
2224 | static void lpuart_config_port(struct uart_port *port, int flags) | |
2225 | { | |
2226 | if (flags & UART_CONFIG_TYPE) | |
2227 | port->type = PORT_LPUART; | |
2228 | } | |
2229 | ||
2230 | static int lpuart_verify_port(struct uart_port *port, struct serial_struct *ser) | |
2231 | { | |
2232 | int ret = 0; | |
2233 | ||
2234 | if (ser->type != PORT_UNKNOWN && ser->type != PORT_LPUART) | |
2235 | ret = -EINVAL; | |
2236 | if (port->irq != ser->irq) | |
2237 | ret = -EINVAL; | |
2238 | if (ser->io_type != UPIO_MEM) | |
2239 | ret = -EINVAL; | |
2240 | if (port->uartclk / 16 != ser->baud_base) | |
2241 | ret = -EINVAL; | |
2242 | if (port->iobase != ser->port) | |
2243 | ret = -EINVAL; | |
2244 | if (ser->hub6 != 0) | |
2245 | ret = -EINVAL; | |
2246 | return ret; | |
2247 | } | |
2248 | ||
069a47e5 | 2249 | static const struct uart_ops lpuart_pops = { |
c9e2e946 JL |
2250 | .tx_empty = lpuart_tx_empty, |
2251 | .set_mctrl = lpuart_set_mctrl, | |
2252 | .get_mctrl = lpuart_get_mctrl, | |
2253 | .stop_tx = lpuart_stop_tx, | |
2254 | .start_tx = lpuart_start_tx, | |
2255 | .stop_rx = lpuart_stop_rx, | |
c9e2e946 JL |
2256 | .break_ctl = lpuart_break_ctl, |
2257 | .startup = lpuart_startup, | |
2258 | .shutdown = lpuart_shutdown, | |
2259 | .set_termios = lpuart_set_termios, | |
43543e6f | 2260 | .pm = lpuart_uart_pm, |
c9e2e946 JL |
2261 | .type = lpuart_type, |
2262 | .request_port = lpuart_request_port, | |
2263 | .release_port = lpuart_release_port, | |
2264 | .config_port = lpuart_config_port, | |
2265 | .verify_port = lpuart_verify_port, | |
bfc2e07f | 2266 | .flush_buffer = lpuart_flush_buffer, |
2a41bc2a NR |
2267 | #if defined(CONFIG_CONSOLE_POLL) |
2268 | .poll_init = lpuart_poll_init, | |
2269 | .poll_get_char = lpuart_poll_get_char, | |
2270 | .poll_put_char = lpuart_poll_put_char, | |
2271 | #endif | |
c9e2e946 JL |
2272 | }; |
2273 | ||
069a47e5 | 2274 | static const struct uart_ops lpuart32_pops = { |
380c966c JL |
2275 | .tx_empty = lpuart32_tx_empty, |
2276 | .set_mctrl = lpuart32_set_mctrl, | |
2277 | .get_mctrl = lpuart32_get_mctrl, | |
2278 | .stop_tx = lpuart32_stop_tx, | |
2279 | .start_tx = lpuart32_start_tx, | |
2280 | .stop_rx = lpuart32_stop_rx, | |
2281 | .break_ctl = lpuart32_break_ctl, | |
2282 | .startup = lpuart32_startup, | |
2283 | .shutdown = lpuart32_shutdown, | |
2284 | .set_termios = lpuart32_set_termios, | |
43543e6f | 2285 | .pm = lpuart_uart_pm, |
380c966c JL |
2286 | .type = lpuart_type, |
2287 | .request_port = lpuart_request_port, | |
2288 | .release_port = lpuart_release_port, | |
2289 | .config_port = lpuart_config_port, | |
2290 | .verify_port = lpuart_verify_port, | |
bfc2e07f | 2291 | .flush_buffer = lpuart_flush_buffer, |
a5fa2660 MV |
2292 | #if defined(CONFIG_CONSOLE_POLL) |
2293 | .poll_init = lpuart32_poll_init, | |
2294 | .poll_get_char = lpuart32_poll_get_char, | |
2295 | .poll_put_char = lpuart32_poll_put_char, | |
2296 | #endif | |
380c966c JL |
2297 | }; |
2298 | ||
c9e2e946 JL |
2299 | static struct lpuart_port *lpuart_ports[UART_NR]; |
2300 | ||
2301 | #ifdef CONFIG_SERIAL_FSL_LPUART_CONSOLE | |
3f8bab17 | 2302 | static void lpuart_console_putchar(struct uart_port *port, unsigned char ch) |
c9e2e946 | 2303 | { |
56dd627f | 2304 | lpuart_wait_bit_set(port, UARTSR1, UARTSR1_TDRE); |
c9e2e946 JL |
2305 | writeb(ch, port->membase + UARTDR); |
2306 | } | |
2307 | ||
3f8bab17 | 2308 | static void lpuart32_console_putchar(struct uart_port *port, unsigned char ch) |
380c966c | 2309 | { |
56dd627f | 2310 | lpuart32_wait_bit_set(port, UARTSTAT, UARTSTAT_TDRE); |
a0204f25 | 2311 | lpuart32_write(port, ch, UARTDATA); |
380c966c JL |
2312 | } |
2313 | ||
c9e2e946 JL |
2314 | static void |
2315 | lpuart_console_write(struct console *co, const char *s, unsigned int count) | |
2316 | { | |
2317 | struct lpuart_port *sport = lpuart_ports[co->index]; | |
2318 | unsigned char old_cr2, cr2; | |
abf1e0a9 SA |
2319 | unsigned long flags; |
2320 | int locked = 1; | |
2321 | ||
5697df73 | 2322 | if (oops_in_progress) |
abf1e0a9 SA |
2323 | locked = spin_trylock_irqsave(&sport->port.lock, flags); |
2324 | else | |
2325 | spin_lock_irqsave(&sport->port.lock, flags); | |
c9e2e946 JL |
2326 | |
2327 | /* first save CR2 and then disable interrupts */ | |
2328 | cr2 = old_cr2 = readb(sport->port.membase + UARTCR2); | |
bcfa46bf | 2329 | cr2 |= UARTCR2_TE | UARTCR2_RE; |
c9e2e946 JL |
2330 | cr2 &= ~(UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_RIE); |
2331 | writeb(cr2, sport->port.membase + UARTCR2); | |
2332 | ||
2333 | uart_console_write(&sport->port, s, count, lpuart_console_putchar); | |
2334 | ||
2335 | /* wait for transmitter finish complete and restore CR2 */ | |
56dd627f | 2336 | lpuart_wait_bit_set(&sport->port, UARTSR1, UARTSR1_TC); |
c9e2e946 JL |
2337 | |
2338 | writeb(old_cr2, sport->port.membase + UARTCR2); | |
abf1e0a9 SA |
2339 | |
2340 | if (locked) | |
2341 | spin_unlock_irqrestore(&sport->port.lock, flags); | |
c9e2e946 JL |
2342 | } |
2343 | ||
380c966c JL |
2344 | static void |
2345 | lpuart32_console_write(struct console *co, const char *s, unsigned int count) | |
2346 | { | |
2347 | struct lpuart_port *sport = lpuart_ports[co->index]; | |
2348 | unsigned long old_cr, cr; | |
abf1e0a9 SA |
2349 | unsigned long flags; |
2350 | int locked = 1; | |
2351 | ||
5697df73 | 2352 | if (oops_in_progress) |
abf1e0a9 SA |
2353 | locked = spin_trylock_irqsave(&sport->port.lock, flags); |
2354 | else | |
2355 | spin_lock_irqsave(&sport->port.lock, flags); | |
380c966c JL |
2356 | |
2357 | /* first save CR2 and then disable interrupts */ | |
a0204f25 | 2358 | cr = old_cr = lpuart32_read(&sport->port, UARTCTRL); |
bcfa46bf | 2359 | cr |= UARTCTRL_TE | UARTCTRL_RE; |
380c966c | 2360 | cr &= ~(UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_RIE); |
a0204f25 | 2361 | lpuart32_write(&sport->port, cr, UARTCTRL); |
380c966c JL |
2362 | |
2363 | uart_console_write(&sport->port, s, count, lpuart32_console_putchar); | |
2364 | ||
2365 | /* wait for transmitter finish complete and restore CR2 */ | |
56dd627f | 2366 | lpuart32_wait_bit_set(&sport->port, UARTSTAT, UARTSTAT_TC); |
380c966c | 2367 | |
a0204f25 | 2368 | lpuart32_write(&sport->port, old_cr, UARTCTRL); |
abf1e0a9 SA |
2369 | |
2370 | if (locked) | |
2371 | spin_unlock_irqrestore(&sport->port.lock, flags); | |
380c966c JL |
2372 | } |
2373 | ||
c9e2e946 JL |
2374 | /* |
2375 | * if the port was already initialised (eg, by a boot loader), | |
2376 | * try to determine the current setup. | |
2377 | */ | |
2378 | static void __init | |
2379 | lpuart_console_get_options(struct lpuart_port *sport, int *baud, | |
2380 | int *parity, int *bits) | |
2381 | { | |
2382 | unsigned char cr, bdh, bdl, brfa; | |
2383 | unsigned int sbr, uartclk, baud_raw; | |
2384 | ||
2385 | cr = readb(sport->port.membase + UARTCR2); | |
2386 | cr &= UARTCR2_TE | UARTCR2_RE; | |
2387 | if (!cr) | |
2388 | return; | |
2389 | ||
2390 | /* ok, the port was enabled */ | |
2391 | ||
2392 | cr = readb(sport->port.membase + UARTCR1); | |
2393 | ||
2394 | *parity = 'n'; | |
2395 | if (cr & UARTCR1_PE) { | |
2396 | if (cr & UARTCR1_PT) | |
2397 | *parity = 'o'; | |
2398 | else | |
2399 | *parity = 'e'; | |
2400 | } | |
2401 | ||
2402 | if (cr & UARTCR1_M) | |
2403 | *bits = 9; | |
2404 | else | |
2405 | *bits = 8; | |
2406 | ||
2407 | bdh = readb(sport->port.membase + UARTBDH); | |
2408 | bdh &= UARTBDH_SBR_MASK; | |
2409 | bdl = readb(sport->port.membase + UARTBDL); | |
2410 | sbr = bdh; | |
2411 | sbr <<= 8; | |
2412 | sbr |= bdl; | |
2413 | brfa = readb(sport->port.membase + UARTCR4); | |
2414 | brfa &= UARTCR4_BRFA_MASK; | |
2415 | ||
35a4ed01 | 2416 | uartclk = lpuart_get_baud_clk_rate(sport); |
c9e2e946 JL |
2417 | /* |
2418 | * baud = mod_clk/(16*(sbr[13]+(brfa)/32) | |
2419 | */ | |
2420 | baud_raw = uartclk / (16 * (sbr + brfa / 32)); | |
2421 | ||
2422 | if (*baud != baud_raw) | |
9edaf50b | 2423 | dev_info(sport->port.dev, "Serial: Console lpuart rounded baud rate" |
c9e2e946 JL |
2424 | "from %d to %d\n", baud_raw, *baud); |
2425 | } | |
2426 | ||
380c966c JL |
2427 | static void __init |
2428 | lpuart32_console_get_options(struct lpuart_port *sport, int *baud, | |
2429 | int *parity, int *bits) | |
2430 | { | |
2431 | unsigned long cr, bd; | |
2432 | unsigned int sbr, uartclk, baud_raw; | |
2433 | ||
a0204f25 | 2434 | cr = lpuart32_read(&sport->port, UARTCTRL); |
380c966c JL |
2435 | cr &= UARTCTRL_TE | UARTCTRL_RE; |
2436 | if (!cr) | |
2437 | return; | |
2438 | ||
2439 | /* ok, the port was enabled */ | |
2440 | ||
a0204f25 | 2441 | cr = lpuart32_read(&sport->port, UARTCTRL); |
380c966c JL |
2442 | |
2443 | *parity = 'n'; | |
2444 | if (cr & UARTCTRL_PE) { | |
2445 | if (cr & UARTCTRL_PT) | |
2446 | *parity = 'o'; | |
2447 | else | |
2448 | *parity = 'e'; | |
2449 | } | |
2450 | ||
2451 | if (cr & UARTCTRL_M) | |
2452 | *bits = 9; | |
2453 | else | |
2454 | *bits = 8; | |
2455 | ||
a0204f25 | 2456 | bd = lpuart32_read(&sport->port, UARTBAUD); |
380c966c | 2457 | bd &= UARTBAUD_SBR_MASK; |
fcb10ee2 SS |
2458 | if (!bd) |
2459 | return; | |
2460 | ||
380c966c | 2461 | sbr = bd; |
35a4ed01 | 2462 | uartclk = lpuart_get_baud_clk_rate(sport); |
380c966c JL |
2463 | /* |
2464 | * baud = mod_clk/(16*(sbr[13]+(brfa)/32) | |
2465 | */ | |
2466 | baud_raw = uartclk / (16 * sbr); | |
2467 | ||
2468 | if (*baud != baud_raw) | |
9edaf50b | 2469 | dev_info(sport->port.dev, "Serial: Console lpuart rounded baud rate" |
380c966c JL |
2470 | "from %d to %d\n", baud_raw, *baud); |
2471 | } | |
2472 | ||
c9e2e946 JL |
2473 | static int __init lpuart_console_setup(struct console *co, char *options) |
2474 | { | |
2475 | struct lpuart_port *sport; | |
2476 | int baud = 115200; | |
2477 | int bits = 8; | |
2478 | int parity = 'n'; | |
2479 | int flow = 'n'; | |
2480 | ||
2481 | /* | |
2482 | * check whether an invalid uart number has been specified, and | |
2483 | * if so, search for the first available port that does have | |
2484 | * console support. | |
2485 | */ | |
2486 | if (co->index == -1 || co->index >= ARRAY_SIZE(lpuart_ports)) | |
2487 | co->index = 0; | |
2488 | ||
2489 | sport = lpuart_ports[co->index]; | |
2490 | if (sport == NULL) | |
2491 | return -ENODEV; | |
2492 | ||
2493 | if (options) | |
2494 | uart_parse_options(options, &baud, &parity, &bits, &flow); | |
2495 | else | |
3ee5447e | 2496 | if (lpuart_is_32(sport)) |
380c966c JL |
2497 | lpuart32_console_get_options(sport, &baud, &parity, &bits); |
2498 | else | |
2499 | lpuart_console_get_options(sport, &baud, &parity, &bits); | |
c9e2e946 | 2500 | |
3ee5447e | 2501 | if (lpuart_is_32(sport)) |
380c966c JL |
2502 | lpuart32_setup_watermark(sport); |
2503 | else | |
2504 | lpuart_setup_watermark(sport); | |
c9e2e946 JL |
2505 | |
2506 | return uart_set_options(&sport->port, co, baud, parity, bits, flow); | |
2507 | } | |
2508 | ||
2509 | static struct uart_driver lpuart_reg; | |
2510 | static struct console lpuart_console = { | |
2511 | .name = DEV_NAME, | |
2512 | .write = lpuart_console_write, | |
2513 | .device = uart_console_device, | |
2514 | .setup = lpuart_console_setup, | |
2515 | .flags = CON_PRINTBUFFER, | |
2516 | .index = -1, | |
2517 | .data = &lpuart_reg, | |
2518 | }; | |
2519 | ||
380c966c JL |
2520 | static struct console lpuart32_console = { |
2521 | .name = DEV_NAME, | |
2522 | .write = lpuart32_console_write, | |
2523 | .device = uart_console_device, | |
2524 | .setup = lpuart_console_setup, | |
2525 | .flags = CON_PRINTBUFFER, | |
2526 | .index = -1, | |
2527 | .data = &lpuart_reg, | |
2528 | }; | |
2529 | ||
1d59b382 SA |
2530 | static void lpuart_early_write(struct console *con, const char *s, unsigned n) |
2531 | { | |
2532 | struct earlycon_device *dev = con->data; | |
2533 | ||
2534 | uart_console_write(&dev->port, s, n, lpuart_console_putchar); | |
2535 | } | |
2536 | ||
2537 | static void lpuart32_early_write(struct console *con, const char *s, unsigned n) | |
2538 | { | |
2539 | struct earlycon_device *dev = con->data; | |
2540 | ||
2541 | uart_console_write(&dev->port, s, n, lpuart32_console_putchar); | |
2542 | } | |
2543 | ||
2544 | static int __init lpuart_early_console_setup(struct earlycon_device *device, | |
2545 | const char *opt) | |
2546 | { | |
2547 | if (!device->port.membase) | |
2548 | return -ENODEV; | |
2549 | ||
2550 | device->con->write = lpuart_early_write; | |
2551 | return 0; | |
2552 | } | |
2553 | ||
2554 | static int __init lpuart32_early_console_setup(struct earlycon_device *device, | |
2555 | const char *opt) | |
2556 | { | |
2557 | if (!device->port.membase) | |
2558 | return -ENODEV; | |
2559 | ||
3966f084 PF |
2560 | if (device->port.iotype != UPIO_MEM32) |
2561 | device->port.iotype = UPIO_MEM32BE; | |
2562 | ||
1d59b382 SA |
2563 | device->con->write = lpuart32_early_write; |
2564 | return 0; | |
2565 | } | |
2566 | ||
e33253f3 MW |
2567 | static int __init ls1028a_early_console_setup(struct earlycon_device *device, |
2568 | const char *opt) | |
2569 | { | |
2570 | u32 cr; | |
2571 | ||
2572 | if (!device->port.membase) | |
2573 | return -ENODEV; | |
2574 | ||
2575 | device->port.iotype = UPIO_MEM32; | |
2576 | device->con->write = lpuart32_early_write; | |
2577 | ||
2578 | /* set the baudrate */ | |
2579 | if (device->port.uartclk && device->baud) | |
2580 | __lpuart32_serial_setbrg(&device->port, device->baud, | |
2581 | false, false); | |
2582 | ||
2583 | /* enable transmitter */ | |
2584 | cr = lpuart32_read(&device->port, UARTCTRL); | |
2585 | cr |= UARTCTRL_TE; | |
2586 | lpuart32_write(&device->port, cr, UARTCTRL); | |
2587 | ||
2588 | return 0; | |
2589 | } | |
2590 | ||
97d6f353 DA |
2591 | static int __init lpuart32_imx_early_console_setup(struct earlycon_device *device, |
2592 | const char *opt) | |
2593 | { | |
2594 | if (!device->port.membase) | |
2595 | return -ENODEV; | |
2596 | ||
2597 | device->port.iotype = UPIO_MEM32; | |
2598 | device->port.membase += IMX_REG_OFF; | |
2599 | device->con->write = lpuart32_early_write; | |
2600 | ||
2601 | return 0; | |
2602 | } | |
1d59b382 SA |
2603 | OF_EARLYCON_DECLARE(lpuart, "fsl,vf610-lpuart", lpuart_early_console_setup); |
2604 | OF_EARLYCON_DECLARE(lpuart32, "fsl,ls1021a-lpuart", lpuart32_early_console_setup); | |
e33253f3 | 2605 | OF_EARLYCON_DECLARE(lpuart32, "fsl,ls1028a-lpuart", ls1028a_early_console_setup); |
97d6f353 | 2606 | OF_EARLYCON_DECLARE(lpuart32, "fsl,imx7ulp-lpuart", lpuart32_imx_early_console_setup); |
4e967973 | 2607 | OF_EARLYCON_DECLARE(lpuart32, "fsl,imx8qxp-lpuart", lpuart32_imx_early_console_setup); |
443df57b | 2608 | OF_EARLYCON_DECLARE(lpuart32, "fsl,imxrt1050-lpuart", lpuart32_imx_early_console_setup); |
0e28ed6c MW |
2609 | EARLYCON_DECLARE(lpuart, lpuart_early_console_setup); |
2610 | EARLYCON_DECLARE(lpuart32, lpuart32_early_console_setup); | |
1d59b382 | 2611 | |
c9e2e946 | 2612 | #define LPUART_CONSOLE (&lpuart_console) |
380c966c | 2613 | #define LPUART32_CONSOLE (&lpuart32_console) |
c9e2e946 JL |
2614 | #else |
2615 | #define LPUART_CONSOLE NULL | |
380c966c | 2616 | #define LPUART32_CONSOLE NULL |
c9e2e946 JL |
2617 | #endif |
2618 | ||
2619 | static struct uart_driver lpuart_reg = { | |
2620 | .owner = THIS_MODULE, | |
2621 | .driver_name = DRIVER_NAME, | |
2622 | .dev_name = DEV_NAME, | |
2623 | .nr = ARRAY_SIZE(lpuart_ports), | |
2624 | .cons = LPUART_CONSOLE, | |
2625 | }; | |
2626 | ||
07481f44 IJ |
2627 | static const struct serial_rs485 lpuart_rs485_supported = { |
2628 | .flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND | SER_RS485_RTS_AFTER_SEND, | |
2629 | /* delay_rts_* and RX_DURING_TX are not supported */ | |
2630 | }; | |
2631 | ||
76bad3f8 SS |
2632 | static int lpuart_global_reset(struct lpuart_port *sport) |
2633 | { | |
2634 | struct uart_port *port = &sport->port; | |
2635 | void __iomem *global_addr; | |
2636 | unsigned long ctrl, bd; | |
2637 | unsigned int val = 0; | |
2638 | int ret; | |
2639 | ||
2640 | ret = clk_prepare_enable(sport->ipg_clk); | |
2641 | if (ret) { | |
2642 | dev_err(sport->port.dev, "failed to enable uart ipg clk: %d\n", ret); | |
2643 | return ret; | |
2644 | } | |
2645 | ||
2646 | if (is_imx7ulp_lpuart(sport) || is_imx8qxp_lpuart(sport)) { | |
2647 | /* | |
2648 | * If the transmitter is used by earlycon, wait for transmit engine to | |
2649 | * complete and then reset. | |
2650 | */ | |
2651 | ctrl = lpuart32_read(port, UARTCTRL); | |
2652 | if (ctrl & UARTCTRL_TE) { | |
2653 | bd = lpuart32_read(&sport->port, UARTBAUD); | |
2654 | if (read_poll_timeout(lpuart32_tx_empty, val, val, 1, 100000, false, | |
2655 | port)) { | |
2656 | dev_warn(sport->port.dev, | |
2657 | "timeout waiting for transmit engine to complete\n"); | |
2658 | clk_disable_unprepare(sport->ipg_clk); | |
2659 | return 0; | |
2660 | } | |
2661 | } | |
2662 | ||
2663 | global_addr = port->membase + UART_GLOBAL - IMX_REG_OFF; | |
2664 | writel(UART_GLOBAL_RST, global_addr); | |
2665 | usleep_range(GLOBAL_RST_MIN_US, GLOBAL_RST_MAX_US); | |
2666 | writel(0, global_addr); | |
2667 | usleep_range(GLOBAL_RST_MIN_US, GLOBAL_RST_MAX_US); | |
2668 | ||
2669 | /* Recover the transmitter for earlycon. */ | |
2670 | if (ctrl & UARTCTRL_TE) { | |
2671 | lpuart32_write(port, bd, UARTBAUD); | |
2672 | lpuart32_write(port, ctrl, UARTCTRL); | |
2673 | } | |
2674 | } | |
2675 | ||
2676 | clk_disable_unprepare(sport->ipg_clk); | |
2677 | return 0; | |
2678 | } | |
2679 | ||
c9e2e946 JL |
2680 | static int lpuart_probe(struct platform_device *pdev) |
2681 | { | |
e8372c4f | 2682 | const struct lpuart_soc_data *sdata = of_device_get_match_data(&pdev->dev); |
c9e2e946 JL |
2683 | struct device_node *np = pdev->dev.of_node; |
2684 | struct lpuart_port *sport; | |
2685 | struct resource *res; | |
401fb66a | 2686 | irq_handler_t handler; |
c9e2e946 JL |
2687 | int ret; |
2688 | ||
2689 | sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL); | |
2690 | if (!sport) | |
2691 | return -ENOMEM; | |
2692 | ||
4ae612a3 | 2693 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
c9e2e946 JL |
2694 | sport->port.membase = devm_ioremap_resource(&pdev->dev, res); |
2695 | if (IS_ERR(sport->port.membase)) | |
2696 | return PTR_ERR(sport->port.membase); | |
2697 | ||
24b1e5f0 | 2698 | sport->port.membase += sdata->reg_off; |
d5c38948 | 2699 | sport->port.mapbase = res->start + sdata->reg_off; |
c9e2e946 JL |
2700 | sport->port.dev = &pdev->dev; |
2701 | sport->port.type = PORT_LPUART; | |
35a4ed01 | 2702 | sport->devtype = sdata->devtype; |
394a9e2c | 2703 | ret = platform_get_irq(pdev, 0); |
1df21786 | 2704 | if (ret < 0) |
394a9e2c | 2705 | return ret; |
394a9e2c | 2706 | sport->port.irq = ret; |
0d6fce90 | 2707 | sport->port.iotype = sdata->iotype; |
3ee5447e | 2708 | if (lpuart_is_32(sport)) |
380c966c JL |
2709 | sport->port.ops = &lpuart32_pops; |
2710 | else | |
2711 | sport->port.ops = &lpuart_pops; | |
4d9ec1c0 | 2712 | sport->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_FSL_LPUART_CONSOLE); |
c9e2e946 JL |
2713 | sport->port.flags = UPF_BOOT_AUTOCONF; |
2714 | ||
67b01837 PS |
2715 | if (lpuart_is_32(sport)) |
2716 | sport->port.rs485_config = lpuart32_config_rs485; | |
2717 | else | |
2718 | sport->port.rs485_config = lpuart_config_rs485; | |
0139da50 | 2719 | sport->port.rs485_supported = lpuart_rs485_supported; |
03895cf4 | 2720 | |
35a4ed01 FD |
2721 | sport->ipg_clk = devm_clk_get(&pdev->dev, "ipg"); |
2722 | if (IS_ERR(sport->ipg_clk)) { | |
2723 | ret = PTR_ERR(sport->ipg_clk); | |
2724 | dev_err(&pdev->dev, "failed to get uart ipg clk: %d\n", ret); | |
c9e2e946 JL |
2725 | return ret; |
2726 | } | |
2727 | ||
35a4ed01 FD |
2728 | sport->baud_clk = NULL; |
2729 | if (is_imx8qxp_lpuart(sport)) { | |
2730 | sport->baud_clk = devm_clk_get(&pdev->dev, "baud"); | |
2731 | if (IS_ERR(sport->baud_clk)) { | |
2732 | ret = PTR_ERR(sport->baud_clk); | |
2733 | dev_err(&pdev->dev, "failed to get uart baud clk: %d\n", ret); | |
2734 | return ret; | |
2735 | } | |
c9e2e946 JL |
2736 | } |
2737 | ||
2b2e71fe MW |
2738 | ret = of_alias_get_id(np, "serial"); |
2739 | if (ret < 0) { | |
f398e0aa SS |
2740 | dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret); |
2741 | return ret; | |
2b2e71fe MW |
2742 | } |
2743 | if (ret >= ARRAY_SIZE(lpuart_ports)) { | |
2744 | dev_err(&pdev->dev, "serial%d out of range\n", ret); | |
f398e0aa | 2745 | return -EINVAL; |
2b2e71fe MW |
2746 | } |
2747 | sport->port.line = ret; | |
2748 | ||
35a4ed01 FD |
2749 | ret = lpuart_enable_clks(sport); |
2750 | if (ret) | |
f398e0aa | 2751 | return ret; |
35a4ed01 | 2752 | sport->port.uartclk = lpuart_get_baud_clk_rate(sport); |
c9e2e946 JL |
2753 | |
2754 | lpuart_ports[sport->port.line] = sport; | |
2755 | ||
2756 | platform_set_drvdata(pdev, &sport->port); | |
2757 | ||
9d7ee0e2 | 2758 | if (lpuart_is_32(sport)) { |
380c966c | 2759 | lpuart_reg.cons = LPUART32_CONSOLE; |
401fb66a | 2760 | handler = lpuart32_int; |
9d7ee0e2 | 2761 | } else { |
380c966c | 2762 | lpuart_reg.cons = LPUART_CONSOLE; |
401fb66a | 2763 | handler = lpuart_int; |
9d7ee0e2 | 2764 | } |
c9e2e946 | 2765 | |
43543e6f SS |
2766 | pm_runtime_use_autosuspend(&pdev->dev); |
2767 | pm_runtime_set_autosuspend_delay(&pdev->dev, UART_AUTOSUSPEND_TIMEOUT); | |
2768 | pm_runtime_set_active(&pdev->dev); | |
2769 | pm_runtime_enable(&pdev->dev); | |
2770 | ||
bd5305dc FD |
2771 | ret = lpuart_global_reset(sport); |
2772 | if (ret) | |
2773 | goto failed_reset; | |
2774 | ||
c150c0f3 LW |
2775 | ret = uart_get_rs485_mode(&sport->port); |
2776 | if (ret) | |
2777 | goto failed_get_rs485; | |
dde18d53 | 2778 | |
7c7f9bc9 LW |
2779 | ret = uart_add_one_port(&lpuart_reg, &sport->port); |
2780 | if (ret) | |
2781 | goto failed_attach_port; | |
dde18d53 | 2782 | |
401fb66a IZ |
2783 | ret = devm_request_irq(&pdev->dev, sport->port.irq, handler, 0, |
2784 | DRIVER_NAME, sport); | |
2785 | if (ret) | |
2786 | goto failed_irq_request; | |
2787 | ||
c9e2e946 | 2788 | return 0; |
9d7ee0e2 | 2789 | |
401fb66a | 2790 | failed_irq_request: |
bd5305dc | 2791 | uart_remove_one_port(&lpuart_reg, &sport->port); |
9d7ee0e2 | 2792 | failed_attach_port: |
7c7f9bc9 | 2793 | failed_get_rs485: |
60f36172 | 2794 | failed_reset: |
43543e6f SS |
2795 | pm_runtime_disable(&pdev->dev); |
2796 | pm_runtime_set_suspended(&pdev->dev); | |
2797 | pm_runtime_dont_use_autosuspend(&pdev->dev); | |
35a4ed01 | 2798 | lpuart_disable_clks(sport); |
9d7ee0e2 | 2799 | return ret; |
c9e2e946 JL |
2800 | } |
2801 | ||
2802 | static int lpuart_remove(struct platform_device *pdev) | |
2803 | { | |
2804 | struct lpuart_port *sport = platform_get_drvdata(pdev); | |
2805 | ||
2806 | uart_remove_one_port(&lpuart_reg, &sport->port); | |
2807 | ||
35a4ed01 | 2808 | lpuart_disable_clks(sport); |
c9e2e946 | 2809 | |
4a818c43 SA |
2810 | if (sport->dma_tx_chan) |
2811 | dma_release_channel(sport->dma_tx_chan); | |
2812 | ||
2813 | if (sport->dma_rx_chan) | |
2814 | dma_release_channel(sport->dma_rx_chan); | |
2815 | ||
43543e6f SS |
2816 | pm_runtime_disable(&pdev->dev); |
2817 | pm_runtime_set_suspended(&pdev->dev); | |
2818 | pm_runtime_dont_use_autosuspend(&pdev->dev); | |
c9e2e946 JL |
2819 | return 0; |
2820 | } | |
2821 | ||
22cf92bb | 2822 | static int lpuart_runtime_suspend(struct device *dev) |
43543e6f SS |
2823 | { |
2824 | struct platform_device *pdev = to_platform_device(dev); | |
2825 | struct lpuart_port *sport = platform_get_drvdata(pdev); | |
2826 | ||
2827 | lpuart_disable_clks(sport); | |
2828 | ||
2829 | return 0; | |
2830 | }; | |
2831 | ||
22cf92bb | 2832 | static int lpuart_runtime_resume(struct device *dev) |
43543e6f SS |
2833 | { |
2834 | struct platform_device *pdev = to_platform_device(dev); | |
2835 | struct lpuart_port *sport = platform_get_drvdata(pdev); | |
2836 | ||
2837 | return lpuart_enable_clks(sport); | |
2838 | }; | |
2839 | ||
4f5cb8c5 | 2840 | static void serial_lpuart_enable_wakeup(struct lpuart_port *sport, bool on) |
c9e2e946 | 2841 | { |
4f5cb8c5 | 2842 | unsigned int val, baud; |
2fe605df | 2843 | |
3ee5447e | 2844 | if (lpuart_is_32(sport)) { |
4f5cb8c5 SS |
2845 | val = lpuart32_read(&sport->port, UARTCTRL); |
2846 | baud = lpuart32_read(&sport->port, UARTBAUD); | |
2847 | if (on) { | |
2848 | /* set rx_watermark to 0 in wakeup source mode */ | |
2849 | lpuart32_write(&sport->port, 0, UARTWATER); | |
2850 | val |= UARTCTRL_RIE; | |
2851 | /* clear RXEDGIF flag before enable RXEDGIE interrupt */ | |
2852 | lpuart32_write(&sport->port, UARTSTAT_RXEDGIF, UARTSTAT); | |
2853 | baud |= UARTBAUD_RXEDGIE; | |
2854 | } else { | |
2855 | val &= ~UARTCTRL_RIE; | |
2856 | baud &= ~UARTBAUD_RXEDGIE; | |
2857 | } | |
2858 | lpuart32_write(&sport->port, val, UARTCTRL); | |
2859 | lpuart32_write(&sport->port, baud, UARTBAUD); | |
2fe605df | 2860 | } else { |
4f5cb8c5 SS |
2861 | val = readb(sport->port.membase + UARTCR2); |
2862 | if (on) | |
2863 | val |= UARTCR2_RIE; | |
2864 | else | |
2865 | val &= ~UARTCR2_RIE; | |
2866 | writeb(val, sport->port.membase + UARTCR2); | |
2fe605df | 2867 | } |
4f5cb8c5 | 2868 | } |
c9e2e946 | 2869 | |
4f5cb8c5 SS |
2870 | static bool lpuart_uport_is_active(struct lpuart_port *sport) |
2871 | { | |
2872 | struct tty_port *port = &sport->port.state->port; | |
2873 | struct tty_struct *tty; | |
2874 | struct device *tty_dev; | |
2875 | int may_wake = 0; | |
c05efd69 | 2876 | |
4f5cb8c5 SS |
2877 | tty = tty_port_tty_get(port); |
2878 | if (tty) { | |
2879 | tty_dev = tty->dev; | |
2880 | may_wake = device_may_wakeup(tty_dev); | |
2881 | tty_kref_put(tty); | |
2882 | } | |
3d6bcddf | 2883 | |
4f5cb8c5 SS |
2884 | if ((tty_port_initialized(port) && may_wake) || |
2885 | (!console_suspend_enabled && uart_console(&sport->port))) | |
2886 | return true; | |
2887 | ||
2888 | return false; | |
2889 | } | |
2890 | ||
22cf92bb | 2891 | static int lpuart_suspend_noirq(struct device *dev) |
4f5cb8c5 SS |
2892 | { |
2893 | struct lpuart_port *sport = dev_get_drvdata(dev); | |
2894 | bool irq_wake = irqd_is_wakeup_set(irq_get_irq_data(sport->port.irq)); | |
2895 | ||
2896 | if (lpuart_uport_is_active(sport)) | |
2897 | serial_lpuart_enable_wakeup(sport, !!irq_wake); | |
2898 | ||
2899 | pinctrl_pm_select_sleep_state(dev); | |
2900 | ||
2901 | return 0; | |
2902 | } | |
2903 | ||
22cf92bb | 2904 | static int lpuart_resume_noirq(struct device *dev) |
4f5cb8c5 SS |
2905 | { |
2906 | struct lpuart_port *sport = dev_get_drvdata(dev); | |
2907 | unsigned int val; | |
2908 | ||
2909 | pinctrl_pm_select_default_state(dev); | |
2910 | ||
2911 | if (lpuart_uport_is_active(sport)) { | |
2912 | serial_lpuart_enable_wakeup(sport, false); | |
c05efd69 | 2913 | |
4f5cb8c5 | 2914 | /* clear the wakeup flags */ |
42b68768 | 2915 | if (lpuart_is_32(sport)) { |
4f5cb8c5 SS |
2916 | val = lpuart32_read(&sport->port, UARTSTAT); |
2917 | lpuart32_write(&sport->port, val, UARTSTAT); | |
42b68768 | 2918 | } |
c05efd69 BD |
2919 | } |
2920 | ||
c9e2e946 JL |
2921 | return 0; |
2922 | } | |
2923 | ||
22cf92bb | 2924 | static int lpuart_suspend(struct device *dev) |
c9e2e946 JL |
2925 | { |
2926 | struct lpuart_port *sport = dev_get_drvdata(dev); | |
4f5cb8c5 | 2927 | unsigned long temp, flags; |
08de1014 | 2928 | |
4f5cb8c5 | 2929 | uart_suspend_port(&lpuart_reg, &sport->port); |
d6b0d2f2 | 2930 | |
4f5cb8c5 SS |
2931 | if (lpuart_uport_is_active(sport)) { |
2932 | spin_lock_irqsave(&sport->port.lock, flags); | |
2933 | if (lpuart_is_32(sport)) { | |
2934 | /* disable Rx/Tx and interrupts */ | |
2935 | temp = lpuart32_read(&sport->port, UARTCTRL); | |
2936 | temp &= ~(UARTCTRL_TE | UARTCTRL_TIE | UARTCTRL_TCIE); | |
2937 | lpuart32_write(&sport->port, temp, UARTCTRL); | |
2938 | } else { | |
2939 | /* disable Rx/Tx and interrupts */ | |
2940 | temp = readb(sport->port.membase + UARTCR2); | |
2941 | temp &= ~(UARTCR2_TE | UARTCR2_TIE | UARTCR2_TCIE); | |
2942 | writeb(temp, sport->port.membase + UARTCR2); | |
2943 | } | |
2944 | spin_unlock_irqrestore(&sport->port.lock, flags); | |
c9e2e946 | 2945 | |
4f5cb8c5 SS |
2946 | if (sport->lpuart_dma_rx_use) { |
2947 | /* | |
2948 | * EDMA driver during suspend will forcefully release any | |
2949 | * non-idle DMA channels. If port wakeup is enabled or if port | |
2950 | * is console port or 'no_console_suspend' is set the Rx DMA | |
2951 | * cannot resume as expected, hence gracefully release the | |
2952 | * Rx DMA path before suspend and start Rx DMA path on resume. | |
2953 | */ | |
2954 | del_timer_sync(&sport->lpuart_timer); | |
2955 | lpuart_dma_rx_free(&sport->port); | |
2956 | ||
2957 | /* Disable Rx DMA to use UART port as wakeup source */ | |
2958 | spin_lock_irqsave(&sport->port.lock, flags); | |
2959 | if (lpuart_is_32(sport)) { | |
2960 | temp = lpuart32_read(&sport->port, UARTBAUD); | |
2961 | lpuart32_write(&sport->port, temp & ~UARTBAUD_RDMAE, | |
2962 | UARTBAUD); | |
2963 | } else { | |
2964 | writeb(readb(sport->port.membase + UARTCR5) & | |
2965 | ~UARTCR5_RDMAS, sport->port.membase + UARTCR5); | |
2966 | } | |
2967 | spin_unlock_irqrestore(&sport->port.lock, flags); | |
2968 | } | |
2969 | ||
2970 | if (sport->lpuart_dma_tx_use) { | |
2971 | spin_lock_irqsave(&sport->port.lock, flags); | |
2972 | if (lpuart_is_32(sport)) { | |
2973 | temp = lpuart32_read(&sport->port, UARTBAUD); | |
2974 | temp &= ~UARTBAUD_TDMAE; | |
2975 | lpuart32_write(&sport->port, temp, UARTBAUD); | |
2976 | } else { | |
2977 | temp = readb(sport->port.membase + UARTCR5); | |
2978 | temp &= ~UARTCR5_TDMAS; | |
2979 | writeb(temp, sport->port.membase + UARTCR5); | |
2980 | } | |
2981 | spin_unlock_irqrestore(&sport->port.lock, flags); | |
2982 | sport->dma_tx_in_progress = false; | |
8682ab0e | 2983 | dmaengine_terminate_sync(sport->dma_tx_chan); |
c05efd69 | 2984 | } |
43543e6f SS |
2985 | } else if (pm_runtime_active(sport->port.dev)) { |
2986 | lpuart_disable_clks(sport); | |
2987 | pm_runtime_disable(sport->port.dev); | |
2988 | pm_runtime_set_suspended(sport->port.dev); | |
c05efd69 BD |
2989 | } |
2990 | ||
4f5cb8c5 SS |
2991 | return 0; |
2992 | } | |
c05efd69 | 2993 | |
4f5cb8c5 SS |
2994 | static void lpuart_console_fixup(struct lpuart_port *sport) |
2995 | { | |
2996 | struct tty_port *port = &sport->port.state->port; | |
2997 | struct uart_port *uport = &sport->port; | |
2998 | struct ktermios termios; | |
2999 | ||
3000 | /* i.MX7ULP enter VLLS mode that lpuart module power off and registers | |
3001 | * all lost no matter the port is wakeup source. | |
3002 | * For console port, console baud rate setting lost and print messy | |
3003 | * log when enable the console port as wakeup source. To avoid the | |
3004 | * issue happen, user should not enable uart port as wakeup source | |
3005 | * in VLLS mode, or restore console setting here. | |
3006 | */ | |
3007 | if (is_imx7ulp_lpuart(sport) && lpuart_uport_is_active(sport) && | |
3008 | console_suspend_enabled && uart_console(&sport->port)) { | |
3009 | ||
3010 | mutex_lock(&port->mutex); | |
3011 | memset(&termios, 0, sizeof(struct ktermios)); | |
3012 | termios.c_cflag = uport->cons->cflag; | |
3013 | if (port->tty && termios.c_cflag == 0) | |
3014 | termios = port->tty->termios; | |
3015 | uport->ops->set_termios(uport, &termios, NULL); | |
3016 | mutex_unlock(&port->mutex); | |
3017 | } | |
3018 | } | |
3019 | ||
22cf92bb | 3020 | static int lpuart_resume(struct device *dev) |
4f5cb8c5 SS |
3021 | { |
3022 | struct lpuart_port *sport = dev_get_drvdata(dev); | |
43543e6f | 3023 | int ret; |
4f5cb8c5 SS |
3024 | |
3025 | if (lpuart_uport_is_active(sport)) { | |
3026 | if (lpuart_is_32(sport)) | |
3027 | lpuart32_hw_setup(sport); | |
3028 | else | |
3029 | lpuart_hw_setup(sport); | |
43543e6f SS |
3030 | } else if (pm_runtime_active(sport->port.dev)) { |
3031 | ret = lpuart_enable_clks(sport); | |
3032 | if (ret) | |
3033 | return ret; | |
3034 | pm_runtime_set_active(sport->port.dev); | |
3035 | pm_runtime_enable(sport->port.dev); | |
4f5cb8c5 | 3036 | } |
42b68768 | 3037 | |
4f5cb8c5 | 3038 | lpuart_console_fixup(sport); |
c9e2e946 JL |
3039 | uart_resume_port(&lpuart_reg, &sport->port); |
3040 | ||
3041 | return 0; | |
3042 | } | |
c9e2e946 | 3043 | |
4f5cb8c5 | 3044 | static const struct dev_pm_ops lpuart_pm_ops = { |
22cf92bb | 3045 | RUNTIME_PM_OPS(lpuart_runtime_suspend, |
43543e6f | 3046 | lpuart_runtime_resume, NULL) |
22cf92bb | 3047 | NOIRQ_SYSTEM_SLEEP_PM_OPS(lpuart_suspend_noirq, |
4f5cb8c5 | 3048 | lpuart_resume_noirq) |
22cf92bb | 3049 | SYSTEM_SLEEP_PM_OPS(lpuart_suspend, lpuart_resume) |
4f5cb8c5 | 3050 | }; |
c9e2e946 JL |
3051 | |
3052 | static struct platform_driver lpuart_driver = { | |
3053 | .probe = lpuart_probe, | |
3054 | .remove = lpuart_remove, | |
3055 | .driver = { | |
3056 | .name = "fsl-lpuart", | |
c9e2e946 | 3057 | .of_match_table = lpuart_dt_ids, |
22cf92bb | 3058 | .pm = pm_ptr(&lpuart_pm_ops), |
c9e2e946 JL |
3059 | }, |
3060 | }; | |
3061 | ||
3062 | static int __init lpuart_serial_init(void) | |
3063 | { | |
144c29ed | 3064 | int ret = uart_register_driver(&lpuart_reg); |
c9e2e946 | 3065 | |
c9e2e946 JL |
3066 | if (ret) |
3067 | return ret; | |
3068 | ||
3069 | ret = platform_driver_register(&lpuart_driver); | |
3070 | if (ret) | |
3071 | uart_unregister_driver(&lpuart_reg); | |
3072 | ||
39c34b09 | 3073 | return ret; |
c9e2e946 JL |
3074 | } |
3075 | ||
3076 | static void __exit lpuart_serial_exit(void) | |
3077 | { | |
3078 | platform_driver_unregister(&lpuart_driver); | |
3079 | uart_unregister_driver(&lpuart_reg); | |
3080 | } | |
3081 | ||
3082 | module_init(lpuart_serial_init); | |
3083 | module_exit(lpuart_serial_exit); | |
3084 | ||
3085 | MODULE_DESCRIPTION("Freescale lpuart serial port driver"); | |
3086 | MODULE_LICENSE("GPL v2"); |