Commit | Line | Data |
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e3b3d0f5 | 1 | // SPDX-License-Identifier: GPL-2.0+ |
c9e2e946 JL |
2 | /* |
3 | * Freescale lpuart serial port driver | |
4 | * | |
380c966c | 5 | * Copyright 2012-2014 Freescale Semiconductor, Inc. |
c9e2e946 JL |
6 | */ |
7 | ||
e1d91dda SS |
8 | #include <linux/bitfield.h> |
9 | #include <linux/bits.h> | |
f1cd8c87 YY |
10 | #include <linux/clk.h> |
11 | #include <linux/console.h> | |
bd5305dc | 12 | #include <linux/delay.h> |
f1cd8c87 YY |
13 | #include <linux/dma-mapping.h> |
14 | #include <linux/dmaengine.h> | |
15 | #include <linux/dmapool.h> | |
c9e2e946 | 16 | #include <linux/io.h> |
76bad3f8 | 17 | #include <linux/iopoll.h> |
c9e2e946 | 18 | #include <linux/irq.h> |
f1cd8c87 | 19 | #include <linux/module.h> |
c9e2e946 | 20 | #include <linux/of.h> |
f1cd8c87 | 21 | #include <linux/of_dma.h> |
4f5cb8c5 | 22 | #include <linux/pinctrl/consumer.h> |
29e5c442 | 23 | #include <linux/platform_device.h> |
43543e6f | 24 | #include <linux/pm_runtime.h> |
c9e2e946 | 25 | #include <linux/serial_core.h> |
f1cd8c87 | 26 | #include <linux/slab.h> |
c9e2e946 JL |
27 | #include <linux/tty_flip.h> |
28 | ||
29 | /* All registers are 8-bit width */ | |
30 | #define UARTBDH 0x00 | |
31 | #define UARTBDL 0x01 | |
32 | #define UARTCR1 0x02 | |
33 | #define UARTCR2 0x03 | |
34 | #define UARTSR1 0x04 | |
35 | #define UARTCR3 0x06 | |
36 | #define UARTDR 0x07 | |
37 | #define UARTCR4 0x0a | |
38 | #define UARTCR5 0x0b | |
39 | #define UARTMODEM 0x0d | |
40 | #define UARTPFIFO 0x10 | |
41 | #define UARTCFIFO 0x11 | |
42 | #define UARTSFIFO 0x12 | |
43 | #define UARTTWFIFO 0x13 | |
44 | #define UARTTCFIFO 0x14 | |
45 | #define UARTRWFIFO 0x15 | |
46 | ||
47 | #define UARTBDH_LBKDIE 0x80 | |
48 | #define UARTBDH_RXEDGIE 0x40 | |
49 | #define UARTBDH_SBR_MASK 0x1f | |
50 | ||
51 | #define UARTCR1_LOOPS 0x80 | |
52 | #define UARTCR1_RSRC 0x20 | |
53 | #define UARTCR1_M 0x10 | |
54 | #define UARTCR1_WAKE 0x08 | |
55 | #define UARTCR1_ILT 0x04 | |
56 | #define UARTCR1_PE 0x02 | |
57 | #define UARTCR1_PT 0x01 | |
58 | ||
59 | #define UARTCR2_TIE 0x80 | |
60 | #define UARTCR2_TCIE 0x40 | |
61 | #define UARTCR2_RIE 0x20 | |
62 | #define UARTCR2_ILIE 0x10 | |
63 | #define UARTCR2_TE 0x08 | |
64 | #define UARTCR2_RE 0x04 | |
65 | #define UARTCR2_RWU 0x02 | |
66 | #define UARTCR2_SBK 0x01 | |
67 | ||
68 | #define UARTSR1_TDRE 0x80 | |
69 | #define UARTSR1_TC 0x40 | |
70 | #define UARTSR1_RDRF 0x20 | |
71 | #define UARTSR1_IDLE 0x10 | |
72 | #define UARTSR1_OR 0x08 | |
73 | #define UARTSR1_NF 0x04 | |
74 | #define UARTSR1_FE 0x02 | |
75 | #define UARTSR1_PE 0x01 | |
76 | ||
77 | #define UARTCR3_R8 0x80 | |
78 | #define UARTCR3_T8 0x40 | |
79 | #define UARTCR3_TXDIR 0x20 | |
80 | #define UARTCR3_TXINV 0x10 | |
81 | #define UARTCR3_ORIE 0x08 | |
82 | #define UARTCR3_NEIE 0x04 | |
83 | #define UARTCR3_FEIE 0x02 | |
84 | #define UARTCR3_PEIE 0x01 | |
85 | ||
86 | #define UARTCR4_MAEN1 0x80 | |
87 | #define UARTCR4_MAEN2 0x40 | |
88 | #define UARTCR4_M10 0x20 | |
89 | #define UARTCR4_BRFA_MASK 0x1f | |
90 | #define UARTCR4_BRFA_OFF 0 | |
91 | ||
92 | #define UARTCR5_TDMAS 0x80 | |
93 | #define UARTCR5_RDMAS 0x20 | |
94 | ||
95 | #define UARTMODEM_RXRTSE 0x08 | |
96 | #define UARTMODEM_TXRTSPOL 0x04 | |
97 | #define UARTMODEM_TXRTSE 0x02 | |
98 | #define UARTMODEM_TXCTSE 0x01 | |
99 | ||
100 | #define UARTPFIFO_TXFE 0x80 | |
101 | #define UARTPFIFO_FIFOSIZE_MASK 0x7 | |
102 | #define UARTPFIFO_TXSIZE_OFF 4 | |
103 | #define UARTPFIFO_RXFE 0x08 | |
104 | #define UARTPFIFO_RXSIZE_OFF 0 | |
105 | ||
106 | #define UARTCFIFO_TXFLUSH 0x80 | |
107 | #define UARTCFIFO_RXFLUSH 0x40 | |
108 | #define UARTCFIFO_RXOFE 0x04 | |
109 | #define UARTCFIFO_TXOFE 0x02 | |
110 | #define UARTCFIFO_RXUFE 0x01 | |
111 | ||
112 | #define UARTSFIFO_TXEMPT 0x80 | |
113 | #define UARTSFIFO_RXEMPT 0x40 | |
114 | #define UARTSFIFO_RXOF 0x04 | |
115 | #define UARTSFIFO_TXOF 0x02 | |
116 | #define UARTSFIFO_RXUF 0x01 | |
117 | ||
bd5305dc FD |
118 | /* 32-bit global registers only for i.MX7ULP/i.MX8x |
119 | * Used to reset all internal logic and registers, except the Global Register. | |
120 | */ | |
121 | #define UART_GLOBAL 0x8 | |
122 | ||
a5fa2660 | 123 | /* 32-bit register definition */ |
380c966c JL |
124 | #define UARTBAUD 0x00 |
125 | #define UARTSTAT 0x04 | |
126 | #define UARTCTRL 0x08 | |
127 | #define UARTDATA 0x0C | |
128 | #define UARTMATCH 0x10 | |
129 | #define UARTMODIR 0x14 | |
130 | #define UARTFIFO 0x18 | |
131 | #define UARTWATER 0x1c | |
132 | ||
133 | #define UARTBAUD_MAEN1 0x80000000 | |
134 | #define UARTBAUD_MAEN2 0x40000000 | |
135 | #define UARTBAUD_M10 0x20000000 | |
136 | #define UARTBAUD_TDMAE 0x00800000 | |
137 | #define UARTBAUD_RDMAE 0x00200000 | |
138 | #define UARTBAUD_MATCFG 0x00400000 | |
139 | #define UARTBAUD_BOTHEDGE 0x00020000 | |
140 | #define UARTBAUD_RESYNCDIS 0x00010000 | |
141 | #define UARTBAUD_LBKDIE 0x00008000 | |
142 | #define UARTBAUD_RXEDGIE 0x00004000 | |
143 | #define UARTBAUD_SBNS 0x00002000 | |
144 | #define UARTBAUD_SBR 0x00000000 | |
145 | #define UARTBAUD_SBR_MASK 0x1fff | |
a6d7514b DA |
146 | #define UARTBAUD_OSR_MASK 0x1f |
147 | #define UARTBAUD_OSR_SHIFT 24 | |
380c966c JL |
148 | |
149 | #define UARTSTAT_LBKDIF 0x80000000 | |
150 | #define UARTSTAT_RXEDGIF 0x40000000 | |
151 | #define UARTSTAT_MSBF 0x20000000 | |
152 | #define UARTSTAT_RXINV 0x10000000 | |
153 | #define UARTSTAT_RWUID 0x08000000 | |
154 | #define UARTSTAT_BRK13 0x04000000 | |
155 | #define UARTSTAT_LBKDE 0x02000000 | |
156 | #define UARTSTAT_RAF 0x01000000 | |
157 | #define UARTSTAT_TDRE 0x00800000 | |
158 | #define UARTSTAT_TC 0x00400000 | |
159 | #define UARTSTAT_RDRF 0x00200000 | |
160 | #define UARTSTAT_IDLE 0x00100000 | |
161 | #define UARTSTAT_OR 0x00080000 | |
162 | #define UARTSTAT_NF 0x00040000 | |
163 | #define UARTSTAT_FE 0x00020000 | |
164 | #define UARTSTAT_PE 0x00010000 | |
165 | #define UARTSTAT_MA1F 0x00008000 | |
166 | #define UARTSTAT_M21F 0x00004000 | |
167 | ||
168 | #define UARTCTRL_R8T9 0x80000000 | |
169 | #define UARTCTRL_R9T8 0x40000000 | |
170 | #define UARTCTRL_TXDIR 0x20000000 | |
171 | #define UARTCTRL_TXINV 0x10000000 | |
172 | #define UARTCTRL_ORIE 0x08000000 | |
173 | #define UARTCTRL_NEIE 0x04000000 | |
174 | #define UARTCTRL_FEIE 0x02000000 | |
175 | #define UARTCTRL_PEIE 0x01000000 | |
176 | #define UARTCTRL_TIE 0x00800000 | |
177 | #define UARTCTRL_TCIE 0x00400000 | |
178 | #define UARTCTRL_RIE 0x00200000 | |
179 | #define UARTCTRL_ILIE 0x00100000 | |
180 | #define UARTCTRL_TE 0x00080000 | |
181 | #define UARTCTRL_RE 0x00040000 | |
182 | #define UARTCTRL_RWU 0x00020000 | |
183 | #define UARTCTRL_SBK 0x00010000 | |
184 | #define UARTCTRL_MA1IE 0x00008000 | |
185 | #define UARTCTRL_MA2IE 0x00004000 | |
e1d91dda | 186 | #define UARTCTRL_IDLECFG GENMASK(10, 8) |
380c966c JL |
187 | #define UARTCTRL_LOOPS 0x00000080 |
188 | #define UARTCTRL_DOZEEN 0x00000040 | |
189 | #define UARTCTRL_RSRC 0x00000020 | |
190 | #define UARTCTRL_M 0x00000010 | |
191 | #define UARTCTRL_WAKE 0x00000008 | |
192 | #define UARTCTRL_ILT 0x00000004 | |
193 | #define UARTCTRL_PE 0x00000002 | |
194 | #define UARTCTRL_PT 0x00000001 | |
195 | ||
196 | #define UARTDATA_NOISY 0x00008000 | |
197 | #define UARTDATA_PARITYE 0x00004000 | |
198 | #define UARTDATA_FRETSC 0x00002000 | |
199 | #define UARTDATA_RXEMPT 0x00001000 | |
200 | #define UARTDATA_IDLINE 0x00000800 | |
201 | #define UARTDATA_MASK 0x3ff | |
202 | ||
203 | #define UARTMODIR_IREN 0x00020000 | |
ecba98f9 | 204 | #define UARTMODIR_RTSWATER GENMASK(10, 8) |
380c966c JL |
205 | #define UARTMODIR_TXCTSSRC 0x00000020 |
206 | #define UARTMODIR_TXCTSC 0x00000010 | |
207 | #define UARTMODIR_RXRTSE 0x00000008 | |
208 | #define UARTMODIR_TXRTSPOL 0x00000004 | |
209 | #define UARTMODIR_TXRTSE 0x00000002 | |
210 | #define UARTMODIR_TXCTSE 0x00000001 | |
211 | ||
212 | #define UARTFIFO_TXEMPT 0x00800000 | |
213 | #define UARTFIFO_RXEMPT 0x00400000 | |
214 | #define UARTFIFO_TXOF 0x00020000 | |
215 | #define UARTFIFO_RXUF 0x00010000 | |
216 | #define UARTFIFO_TXFLUSH 0x00008000 | |
217 | #define UARTFIFO_RXFLUSH 0x00004000 | |
96f54fd4 | 218 | #define UARTFIFO_RXIDEN GENMASK(12, 10) |
380c966c JL |
219 | #define UARTFIFO_TXOFE 0x00000200 |
220 | #define UARTFIFO_RXUFE 0x00000100 | |
221 | #define UARTFIFO_TXFE 0x00000080 | |
222 | #define UARTFIFO_FIFOSIZE_MASK 0x7 | |
223 | #define UARTFIFO_TXSIZE_OFF 4 | |
224 | #define UARTFIFO_RXFE 0x00000008 | |
225 | #define UARTFIFO_RXSIZE_OFF 0 | |
f77ebb24 | 226 | #define UARTFIFO_DEPTH(x) (0x1 << ((x) ? ((x) + 1) : 0)) |
380c966c JL |
227 | |
228 | #define UARTWATER_COUNT_MASK 0xff | |
229 | #define UARTWATER_TXCNT_OFF 8 | |
230 | #define UARTWATER_RXCNT_OFF 24 | |
231 | #define UARTWATER_WATER_MASK 0xff | |
232 | #define UARTWATER_TXWATER_OFF 0 | |
233 | #define UARTWATER_RXWATER_OFF 16 | |
234 | ||
bd5305dc FD |
235 | #define UART_GLOBAL_RST 0x2 |
236 | #define GLOBAL_RST_MIN_US 20 | |
237 | #define GLOBAL_RST_MAX_US 40 | |
238 | ||
5887ad43 BD |
239 | /* Rx DMA timeout in ms, which is used to calculate Rx ring buffer size */ |
240 | #define DMA_RX_TIMEOUT (10) | |
cf9aa72d | 241 | #define DMA_RX_IDLE_CHARS 8 |
43543e6f | 242 | #define UART_AUTOSUSPEND_TIMEOUT 3000 |
f1cd8c87 | 243 | |
c9e2e946 JL |
244 | #define DRIVER_NAME "fsl-lpuart" |
245 | #define DEV_NAME "ttyLP" | |
885692ae | 246 | #define UART_NR 8 |
c9e2e946 | 247 | |
24b1e5f0 DA |
248 | /* IMX lpuart has four extra unused regs located at the beginning */ |
249 | #define IMX_REG_OFF 0x10 | |
250 | ||
35a4ed01 FD |
251 | enum lpuart_type { |
252 | VF610_LPUART, | |
253 | LS1021A_LPUART, | |
c2f448cf | 254 | LS1028A_LPUART, |
35a4ed01 | 255 | IMX7ULP_LPUART, |
ed35d9dc | 256 | IMX8ULP_LPUART, |
35a4ed01 | 257 | IMX8QXP_LPUART, |
443df57b | 258 | IMXRT1050_LPUART, |
35a4ed01 FD |
259 | }; |
260 | ||
c9e2e946 JL |
261 | struct lpuart_port { |
262 | struct uart_port port; | |
35a4ed01 FD |
263 | enum lpuart_type devtype; |
264 | struct clk *ipg_clk; | |
265 | struct clk *baud_clk; | |
c9e2e946 JL |
266 | unsigned int txfifo_size; |
267 | unsigned int rxfifo_size; | |
f1cd8c87 | 268 | |
34ebb26f | 269 | u8 rx_watermark; |
4a818c43 SA |
270 | bool lpuart_dma_tx_use; |
271 | bool lpuart_dma_rx_use; | |
f1cd8c87 YY |
272 | struct dma_chan *dma_tx_chan; |
273 | struct dma_chan *dma_rx_chan; | |
274 | struct dma_async_tx_descriptor *dma_tx_desc; | |
275 | struct dma_async_tx_descriptor *dma_rx_desc; | |
f1cd8c87 YY |
276 | dma_cookie_t dma_tx_cookie; |
277 | dma_cookie_t dma_rx_cookie; | |
f1cd8c87 YY |
278 | unsigned int dma_tx_bytes; |
279 | unsigned int dma_rx_bytes; | |
6250cc30 | 280 | bool dma_tx_in_progress; |
f1cd8c87 YY |
281 | unsigned int dma_rx_timeout; |
282 | struct timer_list lpuart_timer; | |
6250cc30 | 283 | struct scatterlist rx_sgl, tx_sgl[2]; |
5887ad43 BD |
284 | struct circ_buf rx_ring; |
285 | int rx_dma_rng_buf_len; | |
cf9aa72d | 286 | int last_residue; |
6250cc30 BD |
287 | unsigned int dma_tx_nents; |
288 | wait_queue_head_t dma_wait; | |
070298c8 SW |
289 | bool is_cs7; /* Set to true when character size is 7 */ |
290 | /* and the parity is enabled */ | |
d9219528 | 291 | bool dma_idle_int; |
c9e2e946 JL |
292 | }; |
293 | ||
0d6fce90 | 294 | struct lpuart_soc_data { |
35a4ed01 FD |
295 | enum lpuart_type devtype; |
296 | char iotype; | |
297 | u8 reg_off; | |
34ebb26f | 298 | u8 rx_watermark; |
0d6fce90 DA |
299 | }; |
300 | ||
301 | static const struct lpuart_soc_data vf_data = { | |
35a4ed01 | 302 | .devtype = VF610_LPUART, |
0d6fce90 | 303 | .iotype = UPIO_MEM, |
34ebb26f | 304 | .rx_watermark = 1, |
0d6fce90 DA |
305 | }; |
306 | ||
c2f448cf | 307 | static const struct lpuart_soc_data ls1021a_data = { |
35a4ed01 | 308 | .devtype = LS1021A_LPUART, |
0d6fce90 | 309 | .iotype = UPIO_MEM32BE, |
34ebb26f | 310 | .rx_watermark = 1, |
0d6fce90 DA |
311 | }; |
312 | ||
c2f448cf MW |
313 | static const struct lpuart_soc_data ls1028a_data = { |
314 | .devtype = LS1028A_LPUART, | |
315 | .iotype = UPIO_MEM32, | |
a82c3df9 | 316 | .rx_watermark = 0, |
c2f448cf MW |
317 | }; |
318 | ||
35a4ed01 FD |
319 | static struct lpuart_soc_data imx7ulp_data = { |
320 | .devtype = IMX7ULP_LPUART, | |
321 | .iotype = UPIO_MEM32, | |
322 | .reg_off = IMX_REG_OFF, | |
34ebb26f | 323 | .rx_watermark = 1, |
35a4ed01 FD |
324 | }; |
325 | ||
ed35d9dc SS |
326 | static struct lpuart_soc_data imx8ulp_data = { |
327 | .devtype = IMX8ULP_LPUART, | |
328 | .iotype = UPIO_MEM32, | |
329 | .reg_off = IMX_REG_OFF, | |
330 | .rx_watermark = 3, | |
331 | }; | |
332 | ||
35a4ed01 FD |
333 | static struct lpuart_soc_data imx8qxp_data = { |
334 | .devtype = IMX8QXP_LPUART, | |
24b1e5f0 DA |
335 | .iotype = UPIO_MEM32, |
336 | .reg_off = IMX_REG_OFF, | |
cf9aa72d | 337 | .rx_watermark = 7, /* A lower watermark is ideal for low baud rates. */ |
24b1e5f0 | 338 | }; |
443df57b JT |
339 | static struct lpuart_soc_data imxrt1050_data = { |
340 | .devtype = IMXRT1050_LPUART, | |
341 | .iotype = UPIO_MEM32, | |
342 | .reg_off = IMX_REG_OFF, | |
34ebb26f | 343 | .rx_watermark = 1, |
443df57b | 344 | }; |
24b1e5f0 | 345 | |
ed0bb232 | 346 | static const struct of_device_id lpuart_dt_ids[] = { |
0d6fce90 | 347 | { .compatible = "fsl,vf610-lpuart", .data = &vf_data, }, |
c2f448cf MW |
348 | { .compatible = "fsl,ls1021a-lpuart", .data = &ls1021a_data, }, |
349 | { .compatible = "fsl,ls1028a-lpuart", .data = &ls1028a_data, }, | |
35a4ed01 | 350 | { .compatible = "fsl,imx7ulp-lpuart", .data = &imx7ulp_data, }, |
ed35d9dc | 351 | { .compatible = "fsl,imx8ulp-lpuart", .data = &imx8ulp_data, }, |
35a4ed01 | 352 | { .compatible = "fsl,imx8qxp-lpuart", .data = &imx8qxp_data, }, |
443df57b | 353 | { .compatible = "fsl,imxrt1050-lpuart", .data = &imxrt1050_data}, |
c9e2e946 JL |
354 | { /* sentinel */ } |
355 | }; | |
356 | MODULE_DEVICE_TABLE(of, lpuart_dt_ids); | |
357 | ||
f1cd8c87 YY |
358 | /* Forward declare this for the dma callbacks*/ |
359 | static void lpuart_dma_tx_complete(void *arg); | |
f1cd8c87 | 360 | |
c97f2a6f | 361 | static inline bool is_layerscape_lpuart(struct lpuart_port *sport) |
c2f448cf | 362 | { |
c97f2a6f VO |
363 | return (sport->devtype == LS1021A_LPUART || |
364 | sport->devtype == LS1028A_LPUART); | |
c2f448cf MW |
365 | } |
366 | ||
bd5305dc FD |
367 | static inline bool is_imx7ulp_lpuart(struct lpuart_port *sport) |
368 | { | |
369 | return sport->devtype == IMX7ULP_LPUART; | |
370 | } | |
371 | ||
ed35d9dc SS |
372 | static inline bool is_imx8ulp_lpuart(struct lpuart_port *sport) |
373 | { | |
374 | return sport->devtype == IMX8ULP_LPUART; | |
375 | } | |
376 | ||
35a4ed01 FD |
377 | static inline bool is_imx8qxp_lpuart(struct lpuart_port *sport) |
378 | { | |
379 | return sport->devtype == IMX8QXP_LPUART; | |
380 | } | |
381 | ||
f98e1fcd DA |
382 | static inline u32 lpuart32_read(struct uart_port *port, u32 off) |
383 | { | |
384 | switch (port->iotype) { | |
385 | case UPIO_MEM32: | |
386 | return readl(port->membase + off); | |
387 | case UPIO_MEM32BE: | |
388 | return ioread32be(port->membase + off); | |
389 | default: | |
390 | return 0; | |
391 | } | |
380c966c JL |
392 | } |
393 | ||
a0204f25 | 394 | static inline void lpuart32_write(struct uart_port *port, u32 val, |
f98e1fcd DA |
395 | u32 off) |
396 | { | |
397 | switch (port->iotype) { | |
398 | case UPIO_MEM32: | |
399 | writel(val, port->membase + off); | |
400 | break; | |
401 | case UPIO_MEM32BE: | |
402 | iowrite32be(val, port->membase + off); | |
403 | break; | |
404 | } | |
380c966c JL |
405 | } |
406 | ||
35a4ed01 FD |
407 | static int __lpuart_enable_clks(struct lpuart_port *sport, bool is_en) |
408 | { | |
409 | int ret = 0; | |
410 | ||
411 | if (is_en) { | |
412 | ret = clk_prepare_enable(sport->ipg_clk); | |
413 | if (ret) | |
414 | return ret; | |
415 | ||
416 | ret = clk_prepare_enable(sport->baud_clk); | |
417 | if (ret) { | |
418 | clk_disable_unprepare(sport->ipg_clk); | |
419 | return ret; | |
420 | } | |
421 | } else { | |
422 | clk_disable_unprepare(sport->baud_clk); | |
423 | clk_disable_unprepare(sport->ipg_clk); | |
424 | } | |
425 | ||
426 | return 0; | |
427 | } | |
428 | ||
429 | static unsigned int lpuart_get_baud_clk_rate(struct lpuart_port *sport) | |
430 | { | |
431 | if (is_imx8qxp_lpuart(sport)) | |
432 | return clk_get_rate(sport->baud_clk); | |
433 | ||
434 | return clk_get_rate(sport->ipg_clk); | |
435 | } | |
436 | ||
437 | #define lpuart_enable_clks(x) __lpuart_enable_clks(x, true) | |
438 | #define lpuart_disable_clks(x) __lpuart_enable_clks(x, false) | |
439 | ||
c9e2e946 JL |
440 | static void lpuart_stop_tx(struct uart_port *port) |
441 | { | |
442 | unsigned char temp; | |
443 | ||
444 | temp = readb(port->membase + UARTCR2); | |
445 | temp &= ~(UARTCR2_TIE | UARTCR2_TCIE); | |
446 | writeb(temp, port->membase + UARTCR2); | |
447 | } | |
448 | ||
380c966c JL |
449 | static void lpuart32_stop_tx(struct uart_port *port) |
450 | { | |
451 | unsigned long temp; | |
452 | ||
a0204f25 | 453 | temp = lpuart32_read(port, UARTCTRL); |
380c966c | 454 | temp &= ~(UARTCTRL_TIE | UARTCTRL_TCIE); |
a0204f25 | 455 | lpuart32_write(port, temp, UARTCTRL); |
380c966c JL |
456 | } |
457 | ||
c9e2e946 JL |
458 | static void lpuart_stop_rx(struct uart_port *port) |
459 | { | |
460 | unsigned char temp; | |
461 | ||
462 | temp = readb(port->membase + UARTCR2); | |
463 | writeb(temp & ~UARTCR2_RE, port->membase + UARTCR2); | |
464 | } | |
465 | ||
380c966c JL |
466 | static void lpuart32_stop_rx(struct uart_port *port) |
467 | { | |
468 | unsigned long temp; | |
469 | ||
a0204f25 DA |
470 | temp = lpuart32_read(port, UARTCTRL); |
471 | lpuart32_write(port, temp & ~UARTCTRL_RE, UARTCTRL); | |
380c966c JL |
472 | } |
473 | ||
6250cc30 | 474 | static void lpuart_dma_tx(struct lpuart_port *sport) |
f1cd8c87 YY |
475 | { |
476 | struct circ_buf *xmit = &sport->port.state->xmit; | |
6250cc30 BD |
477 | struct scatterlist *sgl = sport->tx_sgl; |
478 | struct device *dev = sport->port.dev; | |
a092ab25 | 479 | struct dma_chan *chan = sport->dma_tx_chan; |
6250cc30 | 480 | int ret; |
f1cd8c87 | 481 | |
6250cc30 BD |
482 | if (sport->dma_tx_in_progress) |
483 | return; | |
f1cd8c87 | 484 | |
6250cc30 | 485 | sport->dma_tx_bytes = uart_circ_chars_pending(xmit); |
f1cd8c87 | 486 | |
d704b2d3 | 487 | if (xmit->tail < xmit->head || xmit->head == 0) { |
6250cc30 BD |
488 | sport->dma_tx_nents = 1; |
489 | sg_init_one(sgl, xmit->buf + xmit->tail, sport->dma_tx_bytes); | |
490 | } else { | |
491 | sport->dma_tx_nents = 2; | |
492 | sg_init_table(sgl, 2); | |
493 | sg_set_buf(sgl, xmit->buf + xmit->tail, | |
494 | UART_XMIT_SIZE - xmit->tail); | |
495 | sg_set_buf(sgl + 1, xmit->buf, xmit->head); | |
496 | } | |
f1cd8c87 | 497 | |
a092ab25 MW |
498 | ret = dma_map_sg(chan->device->dev, sgl, sport->dma_tx_nents, |
499 | DMA_TO_DEVICE); | |
6250cc30 BD |
500 | if (!ret) { |
501 | dev_err(dev, "DMA mapping error for TX.\n"); | |
502 | return; | |
503 | } | |
f1cd8c87 | 504 | |
a092ab25 | 505 | sport->dma_tx_desc = dmaengine_prep_slave_sg(chan, sgl, |
487ee861 PF |
506 | ret, DMA_MEM_TO_DEV, |
507 | DMA_PREP_INTERRUPT); | |
f1cd8c87 | 508 | if (!sport->dma_tx_desc) { |
a092ab25 MW |
509 | dma_unmap_sg(chan->device->dev, sgl, sport->dma_tx_nents, |
510 | DMA_TO_DEVICE); | |
6250cc30 BD |
511 | dev_err(dev, "Cannot prepare TX slave DMA!\n"); |
512 | return; | |
f1cd8c87 YY |
513 | } |
514 | ||
515 | sport->dma_tx_desc->callback = lpuart_dma_tx_complete; | |
516 | sport->dma_tx_desc->callback_param = sport; | |
6250cc30 | 517 | sport->dma_tx_in_progress = true; |
f1cd8c87 | 518 | sport->dma_tx_cookie = dmaengine_submit(sport->dma_tx_desc); |
a092ab25 | 519 | dma_async_issue_pending(chan); |
f1cd8c87 YY |
520 | } |
521 | ||
a90fa532 AS |
522 | static bool lpuart_stopped_or_empty(struct uart_port *port) |
523 | { | |
524 | return uart_circ_empty(&port->state->xmit) || uart_tx_stopped(port); | |
525 | } | |
526 | ||
f1cd8c87 YY |
527 | static void lpuart_dma_tx_complete(void *arg) |
528 | { | |
529 | struct lpuart_port *sport = arg; | |
6250cc30 | 530 | struct scatterlist *sgl = &sport->tx_sgl[0]; |
f1cd8c87 | 531 | struct circ_buf *xmit = &sport->port.state->xmit; |
a092ab25 | 532 | struct dma_chan *chan = sport->dma_tx_chan; |
f1cd8c87 YY |
533 | unsigned long flags; |
534 | ||
92f4e05b | 535 | uart_port_lock_irqsave(&sport->port, &flags); |
88c1d247 | 536 | if (!sport->dma_tx_in_progress) { |
92f4e05b | 537 | uart_port_unlock_irqrestore(&sport->port, flags); |
88c1d247 FD |
538 | return; |
539 | } | |
f1cd8c87 | 540 | |
a092ab25 MW |
541 | dma_unmap_sg(chan->device->dev, sgl, sport->dma_tx_nents, |
542 | DMA_TO_DEVICE); | |
6250cc30 | 543 | |
cacf7f68 | 544 | uart_xmit_advance(&sport->port, sport->dma_tx_bytes); |
6250cc30 | 545 | sport->dma_tx_in_progress = false; |
92f4e05b | 546 | uart_port_unlock_irqrestore(&sport->port, flags); |
f1cd8c87 YY |
547 | |
548 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
549 | uart_write_wakeup(&sport->port); | |
550 | ||
6250cc30 BD |
551 | if (waitqueue_active(&sport->dma_wait)) { |
552 | wake_up(&sport->dma_wait); | |
553 | return; | |
554 | } | |
555 | ||
92f4e05b | 556 | uart_port_lock_irqsave(&sport->port, &flags); |
6250cc30 | 557 | |
a90fa532 | 558 | if (!lpuart_stopped_or_empty(&sport->port)) |
6250cc30 | 559 | lpuart_dma_tx(sport); |
f1cd8c87 | 560 | |
92f4e05b | 561 | uart_port_unlock_irqrestore(&sport->port, flags); |
f1cd8c87 YY |
562 | } |
563 | ||
42b68768 AN |
564 | static dma_addr_t lpuart_dma_datareg_addr(struct lpuart_port *sport) |
565 | { | |
566 | switch (sport->port.iotype) { | |
567 | case UPIO_MEM32: | |
568 | return sport->port.mapbase + UARTDATA; | |
569 | case UPIO_MEM32BE: | |
570 | return sport->port.mapbase + UARTDATA + sizeof(u32) - 1; | |
571 | } | |
572 | return sport->port.mapbase + UARTDR; | |
573 | } | |
574 | ||
6250cc30 BD |
575 | static int lpuart_dma_tx_request(struct uart_port *port) |
576 | { | |
577 | struct lpuart_port *sport = container_of(port, | |
578 | struct lpuart_port, port); | |
579 | struct dma_slave_config dma_tx_sconfig = {}; | |
580 | int ret; | |
581 | ||
42b68768 | 582 | dma_tx_sconfig.dst_addr = lpuart_dma_datareg_addr(sport); |
6250cc30 BD |
583 | dma_tx_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; |
584 | dma_tx_sconfig.dst_maxburst = 1; | |
585 | dma_tx_sconfig.direction = DMA_MEM_TO_DEV; | |
586 | ret = dmaengine_slave_config(sport->dma_tx_chan, &dma_tx_sconfig); | |
587 | ||
588 | if (ret) { | |
589 | dev_err(sport->port.dev, | |
590 | "DMA slave config failed, err = %d\n", ret); | |
591 | return ret; | |
592 | } | |
593 | ||
594 | return 0; | |
595 | } | |
596 | ||
9bc19af9 AS |
597 | static bool lpuart_is_32(struct lpuart_port *sport) |
598 | { | |
599 | return sport->port.iotype == UPIO_MEM32 || | |
600 | sport->port.iotype == UPIO_MEM32BE; | |
601 | } | |
602 | ||
bfc2e07f SA |
603 | static void lpuart_flush_buffer(struct uart_port *port) |
604 | { | |
605 | struct lpuart_port *sport = container_of(port, struct lpuart_port, port); | |
a092ab25 | 606 | struct dma_chan *chan = sport->dma_tx_chan; |
9bc19af9 | 607 | u32 val; |
6250cc30 | 608 | |
bfc2e07f | 609 | if (sport->lpuart_dma_tx_use) { |
6250cc30 | 610 | if (sport->dma_tx_in_progress) { |
a092ab25 | 611 | dma_unmap_sg(chan->device->dev, &sport->tx_sgl[0], |
6250cc30 BD |
612 | sport->dma_tx_nents, DMA_TO_DEVICE); |
613 | sport->dma_tx_in_progress = false; | |
614 | } | |
8682ab0e | 615 | dmaengine_terminate_async(chan); |
bfc2e07f | 616 | } |
9bc19af9 AS |
617 | |
618 | if (lpuart_is_32(sport)) { | |
619 | val = lpuart32_read(&sport->port, UARTFIFO); | |
620 | val |= UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH; | |
621 | lpuart32_write(&sport->port, val, UARTFIFO); | |
622 | } else { | |
5df884d4 | 623 | val = readb(sport->port.membase + UARTCFIFO); |
9bc19af9 AS |
624 | val |= UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH; |
625 | writeb(val, sport->port.membase + UARTCFIFO); | |
626 | } | |
bfc2e07f SA |
627 | } |
628 | ||
56dd627f AS |
629 | static void lpuart_wait_bit_set(struct uart_port *port, unsigned int offset, |
630 | u8 bit) | |
631 | { | |
632 | while (!(readb(port->membase + offset) & bit)) | |
f2f5e04c | 633 | cpu_relax(); |
56dd627f AS |
634 | } |
635 | ||
636 | static void lpuart32_wait_bit_set(struct uart_port *port, unsigned int offset, | |
637 | u32 bit) | |
638 | { | |
639 | while (!(lpuart32_read(port, offset) & bit)) | |
f2f5e04c | 640 | cpu_relax(); |
56dd627f AS |
641 | } |
642 | ||
2a41bc2a NR |
643 | #if defined(CONFIG_CONSOLE_POLL) |
644 | ||
645 | static int lpuart_poll_init(struct uart_port *port) | |
646 | { | |
647 | struct lpuart_port *sport = container_of(port, | |
648 | struct lpuart_port, port); | |
649 | unsigned long flags; | |
650 | unsigned char temp; | |
651 | ||
652 | sport->port.fifosize = 0; | |
653 | ||
92f4e05b | 654 | uart_port_lock_irqsave(&sport->port, &flags); |
2a41bc2a NR |
655 | /* Disable Rx & Tx */ |
656 | writeb(0, sport->port.membase + UARTCR2); | |
657 | ||
658 | temp = readb(sport->port.membase + UARTPFIFO); | |
659 | /* Enable Rx and Tx FIFO */ | |
660 | writeb(temp | UARTPFIFO_RXFE | UARTPFIFO_TXFE, | |
661 | sport->port.membase + UARTPFIFO); | |
662 | ||
663 | /* flush Tx and Rx FIFO */ | |
664 | writeb(UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH, | |
665 | sport->port.membase + UARTCFIFO); | |
666 | ||
667 | /* explicitly clear RDRF */ | |
668 | if (readb(sport->port.membase + UARTSR1) & UARTSR1_RDRF) { | |
669 | readb(sport->port.membase + UARTDR); | |
670 | writeb(UARTSFIFO_RXUF, sport->port.membase + UARTSFIFO); | |
671 | } | |
672 | ||
673 | writeb(0, sport->port.membase + UARTTWFIFO); | |
674 | writeb(1, sport->port.membase + UARTRWFIFO); | |
675 | ||
676 | /* Enable Rx and Tx */ | |
677 | writeb(UARTCR2_RE | UARTCR2_TE, sport->port.membase + UARTCR2); | |
92f4e05b | 678 | uart_port_unlock_irqrestore(&sport->port, flags); |
2a41bc2a NR |
679 | |
680 | return 0; | |
681 | } | |
682 | ||
683 | static void lpuart_poll_put_char(struct uart_port *port, unsigned char c) | |
684 | { | |
2a41bc2a | 685 | /* drain */ |
56dd627f | 686 | lpuart_wait_bit_set(port, UARTSR1, UARTSR1_TDRE); |
2a41bc2a NR |
687 | writeb(c, port->membase + UARTDR); |
688 | } | |
689 | ||
690 | static int lpuart_poll_get_char(struct uart_port *port) | |
691 | { | |
692 | if (!(readb(port->membase + UARTSR1) & UARTSR1_RDRF)) | |
693 | return NO_POLL_CHAR; | |
694 | ||
695 | return readb(port->membase + UARTDR); | |
696 | } | |
697 | ||
a5fa2660 MV |
698 | static int lpuart32_poll_init(struct uart_port *port) |
699 | { | |
700 | unsigned long flags; | |
701 | struct lpuart_port *sport = container_of(port, struct lpuart_port, port); | |
702 | u32 temp; | |
703 | ||
704 | sport->port.fifosize = 0; | |
705 | ||
92f4e05b | 706 | uart_port_lock_irqsave(&sport->port, &flags); |
a5fa2660 MV |
707 | |
708 | /* Disable Rx & Tx */ | |
9ea40db4 | 709 | lpuart32_write(&sport->port, 0, UARTCTRL); |
a5fa2660 | 710 | |
1da17d7c | 711 | temp = lpuart32_read(&sport->port, UARTFIFO); |
a5fa2660 MV |
712 | |
713 | /* Enable Rx and Tx FIFO */ | |
9ea40db4 | 714 | lpuart32_write(&sport->port, temp | UARTFIFO_RXFE | UARTFIFO_TXFE, UARTFIFO); |
a5fa2660 MV |
715 | |
716 | /* flush Tx and Rx FIFO */ | |
9ea40db4 | 717 | lpuart32_write(&sport->port, UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH, UARTFIFO); |
a5fa2660 MV |
718 | |
719 | /* explicitly clear RDRF */ | |
1da17d7c AS |
720 | if (lpuart32_read(&sport->port, UARTSTAT) & UARTSTAT_RDRF) { |
721 | lpuart32_read(&sport->port, UARTDATA); | |
9ea40db4 | 722 | lpuart32_write(&sport->port, UARTFIFO_RXUF, UARTFIFO); |
a5fa2660 MV |
723 | } |
724 | ||
725 | /* Enable Rx and Tx */ | |
9ea40db4 | 726 | lpuart32_write(&sport->port, UARTCTRL_RE | UARTCTRL_TE, UARTCTRL); |
92f4e05b | 727 | uart_port_unlock_irqrestore(&sport->port, flags); |
a5fa2660 MV |
728 | |
729 | return 0; | |
730 | } | |
731 | ||
732 | static void lpuart32_poll_put_char(struct uart_port *port, unsigned char c) | |
733 | { | |
56dd627f | 734 | lpuart32_wait_bit_set(port, UARTSTAT, UARTSTAT_TDRE); |
9ea40db4 | 735 | lpuart32_write(port, c, UARTDATA); |
a5fa2660 MV |
736 | } |
737 | ||
738 | static int lpuart32_poll_get_char(struct uart_port *port) | |
739 | { | |
29788ab1 | 740 | if (!(lpuart32_read(port, UARTWATER) >> UARTWATER_RXCNT_OFF)) |
a5fa2660 MV |
741 | return NO_POLL_CHAR; |
742 | ||
1da17d7c | 743 | return lpuart32_read(port, UARTDATA); |
a5fa2660 | 744 | } |
2a41bc2a NR |
745 | #endif |
746 | ||
c9e2e946 JL |
747 | static inline void lpuart_transmit_buffer(struct lpuart_port *sport) |
748 | { | |
2d141e68 JSS |
749 | struct uart_port *port = &sport->port; |
750 | u8 ch; | |
c9e2e946 | 751 | |
2d141e68 JSS |
752 | uart_port_tx(port, ch, |
753 | readb(port->membase + UARTTCFIFO) < sport->txfifo_size, | |
754 | writeb(ch, port->membase + UARTDR)); | |
c9e2e946 JL |
755 | } |
756 | ||
380c966c JL |
757 | static inline void lpuart32_transmit_buffer(struct lpuart_port *sport) |
758 | { | |
759 | struct circ_buf *xmit = &sport->port.state->xmit; | |
760 | unsigned long txcnt; | |
761 | ||
93b9523a AS |
762 | if (sport->port.x_char) { |
763 | lpuart32_write(&sport->port, sport->port.x_char, UARTDATA); | |
764 | sport->port.icount.tx++; | |
765 | sport->port.x_char = 0; | |
766 | return; | |
767 | } | |
768 | ||
a90fa532 | 769 | if (lpuart_stopped_or_empty(&sport->port)) { |
93b9523a AS |
770 | lpuart32_stop_tx(&sport->port); |
771 | return; | |
772 | } | |
773 | ||
a0204f25 | 774 | txcnt = lpuart32_read(&sport->port, UARTWATER); |
380c966c JL |
775 | txcnt = txcnt >> UARTWATER_TXCNT_OFF; |
776 | txcnt &= UARTWATER_COUNT_MASK; | |
777 | while (!uart_circ_empty(xmit) && (txcnt < sport->txfifo_size)) { | |
a0204f25 | 778 | lpuart32_write(&sport->port, xmit->buf[xmit->tail], UARTDATA); |
cacf7f68 | 779 | uart_xmit_advance(&sport->port, 1); |
a0204f25 | 780 | txcnt = lpuart32_read(&sport->port, UARTWATER); |
380c966c JL |
781 | txcnt = txcnt >> UARTWATER_TXCNT_OFF; |
782 | txcnt &= UARTWATER_COUNT_MASK; | |
783 | } | |
784 | ||
785 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
786 | uart_write_wakeup(&sport->port); | |
787 | ||
788 | if (uart_circ_empty(xmit)) | |
789 | lpuart32_stop_tx(&sport->port); | |
790 | } | |
791 | ||
c9e2e946 JL |
792 | static void lpuart_start_tx(struct uart_port *port) |
793 | { | |
f1cd8c87 YY |
794 | struct lpuart_port *sport = container_of(port, |
795 | struct lpuart_port, port); | |
c9e2e946 JL |
796 | unsigned char temp; |
797 | ||
798 | temp = readb(port->membase + UARTCR2); | |
799 | writeb(temp | UARTCR2_TIE, port->membase + UARTCR2); | |
800 | ||
4a818c43 | 801 | if (sport->lpuart_dma_tx_use) { |
a90fa532 | 802 | if (!lpuart_stopped_or_empty(port)) |
6250cc30 | 803 | lpuart_dma_tx(sport); |
f1cd8c87 YY |
804 | } else { |
805 | if (readb(port->membase + UARTSR1) & UARTSR1_TDRE) | |
806 | lpuart_transmit_buffer(sport); | |
807 | } | |
c9e2e946 JL |
808 | } |
809 | ||
380c966c JL |
810 | static void lpuart32_start_tx(struct uart_port *port) |
811 | { | |
812 | struct lpuart_port *sport = container_of(port, struct lpuart_port, port); | |
813 | unsigned long temp; | |
814 | ||
42b68768 | 815 | if (sport->lpuart_dma_tx_use) { |
a90fa532 | 816 | if (!lpuart_stopped_or_empty(port)) |
42b68768 AN |
817 | lpuart_dma_tx(sport); |
818 | } else { | |
819 | temp = lpuart32_read(port, UARTCTRL); | |
820 | lpuart32_write(port, temp | UARTCTRL_TIE, UARTCTRL); | |
380c966c | 821 | |
42b68768 AN |
822 | if (lpuart32_read(port, UARTSTAT) & UARTSTAT_TDRE) |
823 | lpuart32_transmit_buffer(sport); | |
824 | } | |
380c966c JL |
825 | } |
826 | ||
43543e6f SS |
827 | static void |
828 | lpuart_uart_pm(struct uart_port *port, unsigned int state, unsigned int oldstate) | |
829 | { | |
830 | switch (state) { | |
831 | case UART_PM_STATE_OFF: | |
832 | pm_runtime_mark_last_busy(port->dev); | |
833 | pm_runtime_put_autosuspend(port->dev); | |
834 | break; | |
835 | default: | |
836 | pm_runtime_get_sync(port->dev); | |
837 | break; | |
838 | } | |
839 | } | |
840 | ||
6250cc30 BD |
841 | /* return TIOCSER_TEMT when transmitter is not busy */ |
842 | static unsigned int lpuart_tx_empty(struct uart_port *port) | |
843 | { | |
844 | struct lpuart_port *sport = container_of(port, | |
845 | struct lpuart_port, port); | |
846 | unsigned char sr1 = readb(port->membase + UARTSR1); | |
847 | unsigned char sfifo = readb(port->membase + UARTSFIFO); | |
848 | ||
849 | if (sport->dma_tx_in_progress) | |
850 | return 0; | |
851 | ||
852 | if (sr1 & UARTSR1_TC && sfifo & UARTSFIFO_TXEMPT) | |
853 | return TIOCSER_TEMT; | |
854 | ||
855 | return 0; | |
856 | } | |
857 | ||
858 | static unsigned int lpuart32_tx_empty(struct uart_port *port) | |
859 | { | |
46dd6d77 AN |
860 | struct lpuart_port *sport = container_of(port, |
861 | struct lpuart_port, port); | |
862 | unsigned long stat = lpuart32_read(port, UARTSTAT); | |
863 | unsigned long sfifo = lpuart32_read(port, UARTFIFO); | |
9425914f | 864 | unsigned long ctrl = lpuart32_read(port, UARTCTRL); |
46dd6d77 AN |
865 | |
866 | if (sport->dma_tx_in_progress) | |
867 | return 0; | |
868 | ||
9425914f SS |
869 | /* |
870 | * LPUART Transmission Complete Flag may never be set while queuing a break | |
871 | * character, so avoid checking for transmission complete when UARTCTRL_SBK | |
872 | * is asserted. | |
873 | */ | |
874 | if ((stat & UARTSTAT_TC && sfifo & UARTFIFO_TXEMPT) || ctrl & UARTCTRL_SBK) | |
46dd6d77 AN |
875 | return TIOCSER_TEMT; |
876 | ||
877 | return 0; | |
6250cc30 BD |
878 | } |
879 | ||
3993ddc2 | 880 | static void lpuart_txint(struct lpuart_port *sport) |
c9e2e946 | 881 | { |
92f4e05b | 882 | uart_port_lock(&sport->port); |
93b9523a | 883 | lpuart_transmit_buffer(sport); |
92f4e05b | 884 | uart_port_unlock(&sport->port); |
c9e2e946 JL |
885 | } |
886 | ||
3993ddc2 | 887 | static void lpuart_rxint(struct lpuart_port *sport) |
c9e2e946 | 888 | { |
cc584ab8 | 889 | unsigned int flg, ignored = 0, overrun = 0; |
c9e2e946 | 890 | struct tty_port *port = &sport->port.state->port; |
c9e2e946 JL |
891 | unsigned char rx, sr; |
892 | ||
92f4e05b | 893 | uart_port_lock(&sport->port); |
c9e2e946 JL |
894 | |
895 | while (!(readb(sport->port.membase + UARTSFIFO) & UARTSFIFO_RXEMPT)) { | |
896 | flg = TTY_NORMAL; | |
897 | sport->port.icount.rx++; | |
898 | /* | |
899 | * to clear the FE, OR, NF, FE, PE flags, | |
900 | * read SR1 then read DR | |
901 | */ | |
902 | sr = readb(sport->port.membase + UARTSR1); | |
903 | rx = readb(sport->port.membase + UARTDR); | |
904 | ||
5697df73 | 905 | if (uart_prepare_sysrq_char(&sport->port, rx)) |
c9e2e946 JL |
906 | continue; |
907 | ||
908 | if (sr & (UARTSR1_PE | UARTSR1_OR | UARTSR1_FE)) { | |
909 | if (sr & UARTSR1_PE) | |
910 | sport->port.icount.parity++; | |
911 | else if (sr & UARTSR1_FE) | |
912 | sport->port.icount.frame++; | |
913 | ||
914 | if (sr & UARTSR1_OR) | |
cc584ab8 | 915 | overrun++; |
c9e2e946 JL |
916 | |
917 | if (sr & sport->port.ignore_status_mask) { | |
918 | if (++ignored > 100) | |
919 | goto out; | |
920 | continue; | |
921 | } | |
922 | ||
923 | sr &= sport->port.read_status_mask; | |
924 | ||
925 | if (sr & UARTSR1_PE) | |
926 | flg = TTY_PARITY; | |
927 | else if (sr & UARTSR1_FE) | |
928 | flg = TTY_FRAME; | |
929 | ||
930 | if (sr & UARTSR1_OR) | |
931 | flg = TTY_OVERRUN; | |
932 | ||
c9e2e946 | 933 | sport->port.sysrq = 0; |
c9e2e946 JL |
934 | } |
935 | ||
93cf538e SS |
936 | if (tty_insert_flip_char(port, rx, flg) == 0) |
937 | sport->port.icount.buf_overrun++; | |
c9e2e946 JL |
938 | } |
939 | ||
940 | out: | |
cc584ab8 SA |
941 | if (overrun) { |
942 | sport->port.icount.overrun += overrun; | |
943 | ||
944 | /* | |
945 | * Overruns cause FIFO pointers to become missaligned. | |
946 | * Flushing the receive FIFO reinitializes the pointers. | |
947 | */ | |
948 | writeb(UARTCFIFO_RXFLUSH, sport->port.membase + UARTCFIFO); | |
949 | writeb(UARTSFIFO_RXOF, sport->port.membase + UARTSFIFO); | |
950 | } | |
951 | ||
5697df73 | 952 | uart_unlock_and_check_sysrq(&sport->port); |
c9e2e946 JL |
953 | |
954 | tty_flip_buffer_push(port); | |
c9e2e946 JL |
955 | } |
956 | ||
93b9523a AS |
957 | static void lpuart32_txint(struct lpuart_port *sport) |
958 | { | |
92f4e05b | 959 | uart_port_lock(&sport->port); |
93b9523a | 960 | lpuart32_transmit_buffer(sport); |
92f4e05b | 961 | uart_port_unlock(&sport->port); |
93b9523a AS |
962 | } |
963 | ||
3993ddc2 | 964 | static void lpuart32_rxint(struct lpuart_port *sport) |
380c966c | 965 | { |
380c966c JL |
966 | unsigned int flg, ignored = 0; |
967 | struct tty_port *port = &sport->port.state->port; | |
380c966c | 968 | unsigned long rx, sr; |
5541a9ba | 969 | bool is_break; |
380c966c | 970 | |
92f4e05b | 971 | uart_port_lock(&sport->port); |
380c966c | 972 | |
a0204f25 | 973 | while (!(lpuart32_read(&sport->port, UARTFIFO) & UARTFIFO_RXEMPT)) { |
380c966c JL |
974 | flg = TTY_NORMAL; |
975 | sport->port.icount.rx++; | |
976 | /* | |
977 | * to clear the FE, OR, NF, FE, PE flags, | |
978 | * read STAT then read DATA reg | |
979 | */ | |
a0204f25 DA |
980 | sr = lpuart32_read(&sport->port, UARTSTAT); |
981 | rx = lpuart32_read(&sport->port, UARTDATA); | |
ec22c3ee | 982 | rx &= UARTDATA_MASK; |
380c966c | 983 | |
5541a9ba MW |
984 | /* |
985 | * The LPUART can't distinguish between a break and a framing error, | |
986 | * thus we assume it is a break if the received data is zero. | |
987 | */ | |
988 | is_break = (sr & UARTSTAT_FE) && !rx; | |
989 | ||
990 | if (is_break && uart_handle_break(&sport->port)) | |
991 | continue; | |
992 | ||
5697df73 | 993 | if (uart_prepare_sysrq_char(&sport->port, rx)) |
380c966c JL |
994 | continue; |
995 | ||
996 | if (sr & (UARTSTAT_PE | UARTSTAT_OR | UARTSTAT_FE)) { | |
5541a9ba | 997 | if (sr & UARTSTAT_PE) { |
707f816f SS |
998 | sport->port.icount.parity++; |
999 | } else if (sr & UARTSTAT_FE) { | |
5541a9ba MW |
1000 | if (is_break) |
1001 | sport->port.icount.brk++; | |
1002 | else | |
707f816f | 1003 | sport->port.icount.frame++; |
5541a9ba | 1004 | } |
380c966c JL |
1005 | |
1006 | if (sr & UARTSTAT_OR) | |
1007 | sport->port.icount.overrun++; | |
1008 | ||
1009 | if (sr & sport->port.ignore_status_mask) { | |
1010 | if (++ignored > 100) | |
1011 | goto out; | |
1012 | continue; | |
1013 | } | |
1014 | ||
1015 | sr &= sport->port.read_status_mask; | |
1016 | ||
5541a9ba | 1017 | if (sr & UARTSTAT_PE) { |
707f816f SS |
1018 | flg = TTY_PARITY; |
1019 | } else if (sr & UARTSTAT_FE) { | |
5541a9ba MW |
1020 | if (is_break) |
1021 | flg = TTY_BREAK; | |
1022 | else | |
707f816f | 1023 | flg = TTY_FRAME; |
5541a9ba | 1024 | } |
380c966c JL |
1025 | |
1026 | if (sr & UARTSTAT_OR) | |
1027 | flg = TTY_OVERRUN; | |
380c966c JL |
1028 | } |
1029 | ||
070298c8 SW |
1030 | if (sport->is_cs7) |
1031 | rx &= 0x7F; | |
1032 | ||
93cf538e SS |
1033 | if (tty_insert_flip_char(port, rx, flg) == 0) |
1034 | sport->port.icount.buf_overrun++; | |
380c966c JL |
1035 | } |
1036 | ||
1037 | out: | |
5697df73 | 1038 | uart_unlock_and_check_sysrq(&sport->port); |
380c966c JL |
1039 | |
1040 | tty_flip_buffer_push(port); | |
380c966c JL |
1041 | } |
1042 | ||
c9e2e946 JL |
1043 | static irqreturn_t lpuart_int(int irq, void *dev_id) |
1044 | { | |
1045 | struct lpuart_port *sport = dev_id; | |
5887ad43 | 1046 | unsigned char sts; |
c9e2e946 JL |
1047 | |
1048 | sts = readb(sport->port.membase + UARTSR1); | |
1049 | ||
f4eef224 AD |
1050 | /* SysRq, using dma, check for linebreak by framing err. */ |
1051 | if (sts & UARTSR1_FE && sport->lpuart_dma_rx_use) { | |
1052 | readb(sport->port.membase + UARTDR); | |
1053 | uart_handle_break(&sport->port); | |
1054 | /* linebreak produces some garbage, removing it */ | |
1055 | writeb(UARTCFIFO_RXFLUSH, sport->port.membase + UARTCFIFO); | |
1056 | return IRQ_HANDLED; | |
1057 | } | |
1058 | ||
6798e901 | 1059 | if (sts & UARTSR1_RDRF && !sport->lpuart_dma_rx_use) |
3993ddc2 | 1060 | lpuart_rxint(sport); |
5887ad43 | 1061 | |
6798e901 | 1062 | if (sts & UARTSR1_TDRE && !sport->lpuart_dma_tx_use) |
3993ddc2 | 1063 | lpuart_txint(sport); |
c9e2e946 JL |
1064 | |
1065 | return IRQ_HANDLED; | |
1066 | } | |
1067 | ||
f4eef224 AD |
1068 | static inline void lpuart_handle_sysrq_chars(struct uart_port *port, |
1069 | unsigned char *p, int count) | |
1070 | { | |
1071 | while (count--) { | |
1072 | if (*p && uart_handle_sysrq_char(port, *p)) | |
1073 | return; | |
1074 | p++; | |
1075 | } | |
1076 | } | |
1077 | ||
1078 | static void lpuart_handle_sysrq(struct lpuart_port *sport) | |
1079 | { | |
1080 | struct circ_buf *ring = &sport->rx_ring; | |
1081 | int count; | |
1082 | ||
1083 | if (ring->head < ring->tail) { | |
1084 | count = sport->rx_sgl.length - ring->tail; | |
1085 | lpuart_handle_sysrq_chars(&sport->port, | |
1086 | ring->buf + ring->tail, count); | |
1087 | ring->tail = 0; | |
1088 | } | |
1089 | ||
1090 | if (ring->head > ring->tail) { | |
1091 | count = ring->head - ring->tail; | |
1092 | lpuart_handle_sysrq_chars(&sport->port, | |
1093 | ring->buf + ring->tail, count); | |
1094 | ring->tail = ring->head; | |
1095 | } | |
1096 | } | |
1097 | ||
070298c8 SW |
1098 | static int lpuart_tty_insert_flip_string(struct tty_port *port, |
1099 | unsigned char *chars, size_t size, bool is_cs7) | |
1100 | { | |
1101 | int i; | |
1102 | ||
1103 | if (is_cs7) | |
1104 | for (i = 0; i < size; i++) | |
1105 | chars[i] &= 0x7F; | |
1106 | return tty_insert_flip_string(port, chars, size); | |
1107 | } | |
1108 | ||
5887ad43 BD |
1109 | static void lpuart_copy_rx_to_tty(struct lpuart_port *sport) |
1110 | { | |
1111 | struct tty_port *port = &sport->port.state->port; | |
1112 | struct dma_tx_state state; | |
1113 | enum dma_status dmastat; | |
a092ab25 | 1114 | struct dma_chan *chan = sport->dma_rx_chan; |
5887ad43 BD |
1115 | struct circ_buf *ring = &sport->rx_ring; |
1116 | unsigned long flags; | |
c1b41481 | 1117 | int count, copied; |
5887ad43 | 1118 | |
42b68768 AN |
1119 | if (lpuart_is_32(sport)) { |
1120 | unsigned long sr = lpuart32_read(&sport->port, UARTSTAT); | |
5887ad43 | 1121 | |
42b68768 | 1122 | if (sr & (UARTSTAT_PE | UARTSTAT_FE)) { |
28206984 SS |
1123 | /* Clear the error flags */ |
1124 | lpuart32_write(&sport->port, sr, UARTSTAT); | |
42b68768 AN |
1125 | |
1126 | if (sr & UARTSTAT_PE) | |
1127 | sport->port.icount.parity++; | |
1128 | else if (sr & UARTSTAT_FE) | |
1129 | sport->port.icount.frame++; | |
1130 | } | |
1131 | } else { | |
1132 | unsigned char sr = readb(sport->port.membase + UARTSR1); | |
1133 | ||
1134 | if (sr & (UARTSR1_PE | UARTSR1_FE)) { | |
65632179 SA |
1135 | unsigned char cr2; |
1136 | ||
1137 | /* Disable receiver during this operation... */ | |
1138 | cr2 = readb(sport->port.membase + UARTCR2); | |
1139 | cr2 &= ~UARTCR2_RE; | |
1140 | writeb(cr2, sport->port.membase + UARTCR2); | |
1141 | ||
42b68768 AN |
1142 | /* Read DR to clear the error flags */ |
1143 | readb(sport->port.membase + UARTDR); | |
5887ad43 | 1144 | |
42b68768 AN |
1145 | if (sr & UARTSR1_PE) |
1146 | sport->port.icount.parity++; | |
1147 | else if (sr & UARTSR1_FE) | |
1148 | sport->port.icount.frame++; | |
65632179 SA |
1149 | /* |
1150 | * At this point parity/framing error is | |
1151 | * cleared However, since the DMA already read | |
1152 | * the data register and we had to read it | |
1153 | * again after reading the status register to | |
1154 | * properly clear the flags, the FIFO actually | |
1155 | * underflowed... This requires a clearing of | |
1156 | * the FIFO... | |
1157 | */ | |
1158 | if (readb(sport->port.membase + UARTSFIFO) & | |
1159 | UARTSFIFO_RXUF) { | |
1160 | writeb(UARTSFIFO_RXUF, | |
1161 | sport->port.membase + UARTSFIFO); | |
1162 | writeb(UARTCFIFO_RXFLUSH, | |
1163 | sport->port.membase + UARTCFIFO); | |
1164 | } | |
1165 | ||
1166 | cr2 |= UARTCR2_RE; | |
1167 | writeb(cr2, sport->port.membase + UARTCR2); | |
42b68768 | 1168 | } |
5887ad43 BD |
1169 | } |
1170 | ||
1171 | async_tx_ack(sport->dma_rx_desc); | |
1172 | ||
92f4e05b | 1173 | uart_port_lock_irqsave(&sport->port, &flags); |
5887ad43 | 1174 | |
a092ab25 | 1175 | dmastat = dmaengine_tx_status(chan, sport->dma_rx_cookie, &state); |
5887ad43 BD |
1176 | if (dmastat == DMA_ERROR) { |
1177 | dev_err(sport->port.dev, "Rx DMA transfer failed!\n"); | |
92f4e05b | 1178 | uart_port_unlock_irqrestore(&sport->port, flags); |
5887ad43 BD |
1179 | return; |
1180 | } | |
1181 | ||
1182 | /* CPU claims ownership of RX DMA buffer */ | |
a092ab25 MW |
1183 | dma_sync_sg_for_cpu(chan->device->dev, &sport->rx_sgl, 1, |
1184 | DMA_FROM_DEVICE); | |
5887ad43 BD |
1185 | |
1186 | /* | |
1187 | * ring->head points to the end of data already written by the DMA. | |
1188 | * ring->tail points to the beginning of data to be read by the | |
1189 | * framework. | |
1190 | * The current transfer size should not be larger than the dma buffer | |
1191 | * length. | |
1192 | */ | |
1193 | ring->head = sport->rx_sgl.length - state.residue; | |
1194 | BUG_ON(ring->head > sport->rx_sgl.length); | |
f4eef224 AD |
1195 | |
1196 | /* | |
1197 | * Silent handling of keys pressed in the sysrq timeframe | |
1198 | */ | |
1199 | if (sport->port.sysrq) { | |
1200 | lpuart_handle_sysrq(sport); | |
1201 | goto exit; | |
1202 | } | |
1203 | ||
5887ad43 BD |
1204 | /* |
1205 | * At this point ring->head may point to the first byte right after the | |
1206 | * last byte of the dma buffer: | |
1207 | * 0 <= ring->head <= sport->rx_sgl.length | |
1208 | * | |
1209 | * However ring->tail must always points inside the dma buffer: | |
1210 | * 0 <= ring->tail <= sport->rx_sgl.length - 1 | |
1211 | * | |
1212 | * Since we use a ring buffer, we have to handle the case | |
1213 | * where head is lower than tail. In such a case, we first read from | |
1214 | * tail to the end of the buffer then reset tail. | |
1215 | */ | |
1216 | if (ring->head < ring->tail) { | |
1217 | count = sport->rx_sgl.length - ring->tail; | |
1218 | ||
070298c8 SW |
1219 | copied = lpuart_tty_insert_flip_string(port, ring->buf + ring->tail, |
1220 | count, sport->is_cs7); | |
93cf538e SS |
1221 | if (copied != count) |
1222 | sport->port.icount.buf_overrun++; | |
5887ad43 | 1223 | ring->tail = 0; |
93cf538e | 1224 | sport->port.icount.rx += copied; |
5887ad43 BD |
1225 | } |
1226 | ||
1227 | /* Finally we read data from tail to head */ | |
1228 | if (ring->tail < ring->head) { | |
1229 | count = ring->head - ring->tail; | |
070298c8 SW |
1230 | copied = lpuart_tty_insert_flip_string(port, ring->buf + ring->tail, |
1231 | count, sport->is_cs7); | |
93cf538e SS |
1232 | if (copied != count) |
1233 | sport->port.icount.buf_overrun++; | |
5887ad43 BD |
1234 | /* Wrap ring->head if needed */ |
1235 | if (ring->head >= sport->rx_sgl.length) | |
1236 | ring->head = 0; | |
1237 | ring->tail = ring->head; | |
93cf538e | 1238 | sport->port.icount.rx += copied; |
5887ad43 BD |
1239 | } |
1240 | ||
cf9aa72d SW |
1241 | sport->last_residue = state.residue; |
1242 | ||
f4eef224 | 1243 | exit: |
a092ab25 | 1244 | dma_sync_sg_for_device(chan->device->dev, &sport->rx_sgl, 1, |
5887ad43 BD |
1245 | DMA_FROM_DEVICE); |
1246 | ||
92f4e05b | 1247 | uart_port_unlock_irqrestore(&sport->port, flags); |
5887ad43 BD |
1248 | |
1249 | tty_flip_buffer_push(port); | |
d9219528 SS |
1250 | if (!sport->dma_idle_int) |
1251 | mod_timer(&sport->lpuart_timer, jiffies + sport->dma_rx_timeout); | |
5887ad43 BD |
1252 | } |
1253 | ||
1254 | static void lpuart_dma_rx_complete(void *arg) | |
1255 | { | |
1256 | struct lpuart_port *sport = arg; | |
1257 | ||
1258 | lpuart_copy_rx_to_tty(sport); | |
1259 | } | |
1260 | ||
d9219528 SS |
1261 | static void lpuart32_dma_idleint(struct lpuart_port *sport) |
1262 | { | |
1263 | enum dma_status dmastat; | |
1264 | struct dma_chan *chan = sport->dma_rx_chan; | |
1265 | struct circ_buf *ring = &sport->rx_ring; | |
1266 | struct dma_tx_state state; | |
1267 | int count = 0; | |
1268 | ||
1269 | dmastat = dmaengine_tx_status(chan, sport->dma_rx_cookie, &state); | |
1270 | if (dmastat == DMA_ERROR) { | |
1271 | dev_err(sport->port.dev, "Rx DMA transfer failed!\n"); | |
1272 | return; | |
1273 | } | |
1274 | ||
1275 | ring->head = sport->rx_sgl.length - state.residue; | |
1276 | count = CIRC_CNT(ring->head, ring->tail, sport->rx_sgl.length); | |
1277 | ||
1278 | /* Check if new data received before copying */ | |
1279 | if (count) | |
1280 | lpuart_copy_rx_to_tty(sport); | |
1281 | } | |
1282 | ||
9cb31a28 SS |
1283 | static irqreturn_t lpuart32_int(int irq, void *dev_id) |
1284 | { | |
1285 | struct lpuart_port *sport = dev_id; | |
1286 | unsigned long sts, rxcount; | |
1287 | ||
1288 | sts = lpuart32_read(&sport->port, UARTSTAT); | |
1289 | rxcount = lpuart32_read(&sport->port, UARTWATER); | |
1290 | rxcount = rxcount >> UARTWATER_RXCNT_OFF; | |
1291 | ||
1292 | if ((sts & UARTSTAT_RDRF || rxcount > 0) && !sport->lpuart_dma_rx_use) | |
1293 | lpuart32_rxint(sport); | |
1294 | ||
1295 | if ((sts & UARTSTAT_TDRE) && !sport->lpuart_dma_tx_use) | |
1296 | lpuart32_txint(sport); | |
1297 | ||
d9219528 SS |
1298 | if ((sts & UARTSTAT_IDLE) && sport->lpuart_dma_rx_use && sport->dma_idle_int) |
1299 | lpuart32_dma_idleint(sport); | |
1300 | ||
9cb31a28 SS |
1301 | lpuart32_write(&sport->port, sts, UARTSTAT); |
1302 | return IRQ_HANDLED; | |
1303 | } | |
1304 | ||
cf9aa72d SW |
1305 | /* |
1306 | * Timer function to simulate the hardware EOP (End Of Package) event. | |
1307 | * The timer callback is to check for new RX data and copy to TTY buffer. | |
1308 | * If no new data are received since last interval, the EOP condition is | |
1309 | * met, complete the DMA transfer by copying the data. Otherwise, just | |
1310 | * restart timer. | |
1311 | */ | |
e99e88a9 | 1312 | static void lpuart_timer_func(struct timer_list *t) |
5887ad43 | 1313 | { |
e99e88a9 | 1314 | struct lpuart_port *sport = from_timer(sport, t, lpuart_timer); |
20ec397d | 1315 | enum dma_status dmastat; |
cf9aa72d SW |
1316 | struct dma_chan *chan = sport->dma_rx_chan; |
1317 | struct circ_buf *ring = &sport->rx_ring; | |
1318 | struct dma_tx_state state; | |
1319 | unsigned long flags; | |
1320 | int count; | |
5887ad43 | 1321 | |
20ec397d SS |
1322 | dmastat = dmaengine_tx_status(chan, sport->dma_rx_cookie, &state); |
1323 | if (dmastat == DMA_ERROR) { | |
1324 | dev_err(sport->port.dev, "Rx DMA transfer failed!\n"); | |
1325 | return; | |
1326 | } | |
1327 | ||
cf9aa72d SW |
1328 | ring->head = sport->rx_sgl.length - state.residue; |
1329 | count = CIRC_CNT(ring->head, ring->tail, sport->rx_sgl.length); | |
1330 | ||
1331 | /* Check if new data received before copying */ | |
1332 | if ((count != 0) && (sport->last_residue == state.residue)) | |
1333 | lpuart_copy_rx_to_tty(sport); | |
1334 | else | |
1335 | mod_timer(&sport->lpuart_timer, | |
1336 | jiffies + sport->dma_rx_timeout); | |
1337 | ||
92f4e05b | 1338 | if (uart_port_trylock_irqsave(&sport->port, &flags)) { |
cf9aa72d | 1339 | sport->last_residue = state.residue; |
92f4e05b | 1340 | uart_port_unlock_irqrestore(&sport->port, flags); |
cf9aa72d | 1341 | } |
5887ad43 BD |
1342 | } |
1343 | ||
1344 | static inline int lpuart_start_rx_dma(struct lpuart_port *sport) | |
1345 | { | |
1346 | struct dma_slave_config dma_rx_sconfig = {}; | |
1347 | struct circ_buf *ring = &sport->rx_ring; | |
1348 | int ret, nent; | |
3216c622 SA |
1349 | struct tty_port *port = &sport->port.state->port; |
1350 | struct tty_struct *tty = port->tty; | |
5887ad43 | 1351 | struct ktermios *termios = &tty->termios; |
a092ab25 | 1352 | struct dma_chan *chan = sport->dma_rx_chan; |
d4be10c8 IJ |
1353 | unsigned int bits = tty_get_frame_size(termios->c_cflag); |
1354 | unsigned int baud = tty_get_baud_rate(tty); | |
5887ad43 BD |
1355 | |
1356 | /* | |
1357 | * Calculate length of one DMA buffer size to keep latency below | |
1358 | * 10ms at any baud rate. | |
1359 | */ | |
1360 | sport->rx_dma_rng_buf_len = (DMA_RX_TIMEOUT * baud / bits / 1000) * 2; | |
f73fd750 | 1361 | sport->rx_dma_rng_buf_len = (1 << fls(sport->rx_dma_rng_buf_len)); |
cf9aa72d SW |
1362 | sport->rx_dma_rng_buf_len = max_t(int, |
1363 | sport->rxfifo_size * 2, | |
1364 | sport->rx_dma_rng_buf_len); | |
1365 | /* | |
1366 | * Keep this condition check in case rxfifo_size is unavailable | |
1367 | * for some SoCs. | |
1368 | */ | |
5887ad43 BD |
1369 | if (sport->rx_dma_rng_buf_len < 16) |
1370 | sport->rx_dma_rng_buf_len = 16; | |
1371 | ||
cf9aa72d SW |
1372 | sport->last_residue = 0; |
1373 | sport->dma_rx_timeout = max(nsecs_to_jiffies( | |
1374 | sport->port.frame_time * DMA_RX_IDLE_CHARS), 1UL); | |
1375 | ||
ca8d92f6 | 1376 | ring->buf = kzalloc(sport->rx_dma_rng_buf_len, GFP_ATOMIC); |
099f79c0 | 1377 | if (!ring->buf) |
5887ad43 | 1378 | return -ENOMEM; |
5887ad43 BD |
1379 | |
1380 | sg_init_one(&sport->rx_sgl, ring->buf, sport->rx_dma_rng_buf_len); | |
a092ab25 MW |
1381 | nent = dma_map_sg(chan->device->dev, &sport->rx_sgl, 1, |
1382 | DMA_FROM_DEVICE); | |
5887ad43 BD |
1383 | |
1384 | if (!nent) { | |
1385 | dev_err(sport->port.dev, "DMA Rx mapping error\n"); | |
1386 | return -EINVAL; | |
1387 | } | |
1388 | ||
42b68768 | 1389 | dma_rx_sconfig.src_addr = lpuart_dma_datareg_addr(sport); |
5887ad43 BD |
1390 | dma_rx_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; |
1391 | dma_rx_sconfig.src_maxburst = 1; | |
1392 | dma_rx_sconfig.direction = DMA_DEV_TO_MEM; | |
a092ab25 | 1393 | ret = dmaengine_slave_config(chan, &dma_rx_sconfig); |
5887ad43 BD |
1394 | |
1395 | if (ret < 0) { | |
1396 | dev_err(sport->port.dev, | |
1397 | "DMA Rx slave config failed, err = %d\n", ret); | |
1398 | return ret; | |
1399 | } | |
1400 | ||
a092ab25 | 1401 | sport->dma_rx_desc = dmaengine_prep_dma_cyclic(chan, |
5887ad43 BD |
1402 | sg_dma_address(&sport->rx_sgl), |
1403 | sport->rx_sgl.length, | |
1404 | sport->rx_sgl.length / 2, | |
1405 | DMA_DEV_TO_MEM, | |
1406 | DMA_PREP_INTERRUPT); | |
1407 | if (!sport->dma_rx_desc) { | |
1408 | dev_err(sport->port.dev, "Cannot prepare cyclic DMA\n"); | |
1409 | return -EFAULT; | |
1410 | } | |
1411 | ||
1412 | sport->dma_rx_desc->callback = lpuart_dma_rx_complete; | |
1413 | sport->dma_rx_desc->callback_param = sport; | |
1414 | sport->dma_rx_cookie = dmaengine_submit(sport->dma_rx_desc); | |
a092ab25 | 1415 | dma_async_issue_pending(chan); |
5887ad43 | 1416 | |
42b68768 AN |
1417 | if (lpuart_is_32(sport)) { |
1418 | unsigned long temp = lpuart32_read(&sport->port, UARTBAUD); | |
1419 | ||
1420 | lpuart32_write(&sport->port, temp | UARTBAUD_RDMAE, UARTBAUD); | |
d9219528 SS |
1421 | |
1422 | if (sport->dma_idle_int) { | |
1423 | unsigned long ctrl = lpuart32_read(&sport->port, UARTCTRL); | |
1424 | ||
1425 | lpuart32_write(&sport->port, ctrl | UARTCTRL_ILIE, UARTCTRL); | |
1426 | } | |
42b68768 AN |
1427 | } else { |
1428 | writeb(readb(sport->port.membase + UARTCR5) | UARTCR5_RDMAS, | |
1429 | sport->port.membase + UARTCR5); | |
1430 | } | |
5887ad43 BD |
1431 | |
1432 | return 0; | |
1433 | } | |
1434 | ||
5887ad43 BD |
1435 | static void lpuart_dma_rx_free(struct uart_port *port) |
1436 | { | |
1437 | struct lpuart_port *sport = container_of(port, | |
1438 | struct lpuart_port, port); | |
a092ab25 | 1439 | struct dma_chan *chan = sport->dma_rx_chan; |
5887ad43 | 1440 | |
8682ab0e | 1441 | dmaengine_terminate_sync(chan); |
d9219528 SS |
1442 | if (!sport->dma_idle_int) |
1443 | del_timer_sync(&sport->lpuart_timer); | |
1444 | ||
a092ab25 | 1445 | dma_unmap_sg(chan->device->dev, &sport->rx_sgl, 1, DMA_FROM_DEVICE); |
5887ad43 BD |
1446 | kfree(sport->rx_ring.buf); |
1447 | sport->rx_ring.tail = 0; | |
1448 | sport->rx_ring.head = 0; | |
1449 | sport->dma_rx_desc = NULL; | |
1450 | sport->dma_rx_cookie = -EINVAL; | |
1451 | } | |
1452 | ||
ae50bb27 | 1453 | static int lpuart_config_rs485(struct uart_port *port, struct ktermios *termios, |
03895cf4 BD |
1454 | struct serial_rs485 *rs485) |
1455 | { | |
1456 | struct lpuart_port *sport = container_of(port, | |
1457 | struct lpuart_port, port); | |
1458 | ||
1459 | u8 modem = readb(sport->port.membase + UARTMODEM) & | |
1460 | ~(UARTMODEM_TXRTSPOL | UARTMODEM_TXRTSE); | |
1461 | writeb(modem, sport->port.membase + UARTMODEM); | |
1462 | ||
1463 | if (rs485->flags & SER_RS485_ENABLED) { | |
1464 | /* Enable auto RS-485 RTS mode */ | |
1465 | modem |= UARTMODEM_TXRTSE; | |
1466 | ||
03895cf4 BD |
1467 | /* |
1468 | * The hardware defaults to RTS logic HIGH while transfer. | |
1469 | * Switch polarity in case RTS shall be logic HIGH | |
1470 | * after transfer. | |
1471 | * Note: UART is assumed to be active high. | |
1472 | */ | |
1473 | if (rs485->flags & SER_RS485_RTS_ON_SEND) | |
03895cf4 | 1474 | modem |= UARTMODEM_TXRTSPOL; |
846651ec SW |
1475 | else if (rs485->flags & SER_RS485_RTS_AFTER_SEND) |
1476 | modem &= ~UARTMODEM_TXRTSPOL; | |
03895cf4 BD |
1477 | } |
1478 | ||
03895cf4 BD |
1479 | writeb(modem, sport->port.membase + UARTMODEM); |
1480 | return 0; | |
1481 | } | |
1482 | ||
ae50bb27 | 1483 | static int lpuart32_config_rs485(struct uart_port *port, struct ktermios *termios, |
67b01837 PS |
1484 | struct serial_rs485 *rs485) |
1485 | { | |
1486 | struct lpuart_port *sport = container_of(port, | |
1487 | struct lpuart_port, port); | |
1488 | ||
1489 | unsigned long modem = lpuart32_read(&sport->port, UARTMODIR) | |
d57d56e4 | 1490 | & ~(UARTMODIR_TXRTSPOL | UARTMODIR_TXRTSE); |
67b01837 PS |
1491 | lpuart32_write(&sport->port, modem, UARTMODIR); |
1492 | ||
67b01837 PS |
1493 | if (rs485->flags & SER_RS485_ENABLED) { |
1494 | /* Enable auto RS-485 RTS mode */ | |
d57d56e4 | 1495 | modem |= UARTMODIR_TXRTSE; |
67b01837 | 1496 | |
67b01837 PS |
1497 | /* |
1498 | * The hardware defaults to RTS logic HIGH while transfer. | |
1499 | * Switch polarity in case RTS shall be logic HIGH | |
1500 | * after transfer. | |
1501 | * Note: UART is assumed to be active high. | |
1502 | */ | |
1503 | if (rs485->flags & SER_RS485_RTS_ON_SEND) | |
d57d56e4 | 1504 | modem |= UARTMODIR_TXRTSPOL; |
3957b950 | 1505 | else if (rs485->flags & SER_RS485_RTS_AFTER_SEND) |
d57d56e4 | 1506 | modem &= ~UARTMODIR_TXRTSPOL; |
67b01837 PS |
1507 | } |
1508 | ||
67b01837 PS |
1509 | lpuart32_write(&sport->port, modem, UARTMODIR); |
1510 | return 0; | |
1511 | } | |
1512 | ||
c9e2e946 JL |
1513 | static unsigned int lpuart_get_mctrl(struct uart_port *port) |
1514 | { | |
8a0c810d MW |
1515 | unsigned int mctrl = 0; |
1516 | u8 reg; | |
1517 | ||
1518 | reg = readb(port->membase + UARTCR1); | |
1519 | if (reg & UARTCR1_LOOPS) | |
1520 | mctrl |= TIOCM_LOOP; | |
1521 | ||
1522 | return mctrl; | |
c9e2e946 JL |
1523 | } |
1524 | ||
380c966c JL |
1525 | static unsigned int lpuart32_get_mctrl(struct uart_port *port) |
1526 | { | |
06e91df1 | 1527 | unsigned int mctrl = TIOCM_CAR | TIOCM_DSR | TIOCM_CTS; |
8a0c810d MW |
1528 | u32 reg; |
1529 | ||
1530 | reg = lpuart32_read(port, UARTCTRL); | |
1531 | if (reg & UARTCTRL_LOOPS) | |
1532 | mctrl |= TIOCM_LOOP; | |
1533 | ||
1534 | return mctrl; | |
380c966c JL |
1535 | } |
1536 | ||
c9e2e946 JL |
1537 | static void lpuart_set_mctrl(struct uart_port *port, unsigned int mctrl) |
1538 | { | |
8a0c810d MW |
1539 | u8 reg; |
1540 | ||
1541 | reg = readb(port->membase + UARTCR1); | |
1542 | ||
1543 | /* for internal loopback we need LOOPS=1 and RSRC=0 */ | |
1544 | reg &= ~(UARTCR1_LOOPS | UARTCR1_RSRC); | |
1545 | if (mctrl & TIOCM_LOOP) | |
1546 | reg |= UARTCR1_LOOPS; | |
c9e2e946 | 1547 | |
8a0c810d | 1548 | writeb(reg, port->membase + UARTCR1); |
c9e2e946 JL |
1549 | } |
1550 | ||
380c966c JL |
1551 | static void lpuart32_set_mctrl(struct uart_port *port, unsigned int mctrl) |
1552 | { | |
8a0c810d MW |
1553 | u32 reg; |
1554 | ||
1555 | reg = lpuart32_read(port, UARTCTRL); | |
1556 | ||
1557 | /* for internal loopback we need LOOPS=1 and RSRC=0 */ | |
1558 | reg &= ~(UARTCTRL_LOOPS | UARTCTRL_RSRC); | |
1559 | if (mctrl & TIOCM_LOOP) | |
1560 | reg |= UARTCTRL_LOOPS; | |
380c966c | 1561 | |
8a0c810d | 1562 | lpuart32_write(port, reg, UARTCTRL); |
380c966c JL |
1563 | } |
1564 | ||
c9e2e946 JL |
1565 | static void lpuart_break_ctl(struct uart_port *port, int break_state) |
1566 | { | |
1567 | unsigned char temp; | |
1568 | ||
1569 | temp = readb(port->membase + UARTCR2) & ~UARTCR2_SBK; | |
1570 | ||
1571 | if (break_state != 0) | |
1572 | temp |= UARTCR2_SBK; | |
1573 | ||
1574 | writeb(temp, port->membase + UARTCR2); | |
1575 | } | |
1576 | ||
380c966c JL |
1577 | static void lpuart32_break_ctl(struct uart_port *port, int break_state) |
1578 | { | |
2474e054 | 1579 | unsigned long temp; |
380c966c | 1580 | |
2474e054 | 1581 | temp = lpuart32_read(port, UARTCTRL); |
380c966c | 1582 | |
2474e054 SS |
1583 | /* |
1584 | * LPUART IP now has two known bugs, one is CTS has higher priority than the | |
1585 | * break signal, which causes the break signal sending through UARTCTRL_SBK | |
1586 | * may impacted by the CTS input if the HW flow control is enabled. It | |
1587 | * exists on all platforms we support in this driver. | |
1588 | * Another bug is i.MX8QM LPUART may have an additional break character | |
1589 | * being sent after SBK was cleared. | |
1590 | * To avoid above two bugs, we use Transmit Data Inversion function to send | |
1591 | * the break signal instead of UARTCTRL_SBK. | |
1592 | */ | |
c4c81db5 | 1593 | if (break_state != 0) { |
c4c81db5 | 1594 | /* |
2474e054 SS |
1595 | * Disable the transmitter to prevent any data from being sent out |
1596 | * during break, then invert the TX line to send break. | |
c4c81db5 | 1597 | */ |
2474e054 SS |
1598 | temp &= ~UARTCTRL_TE; |
1599 | lpuart32_write(port, temp, UARTCTRL); | |
1600 | temp |= UARTCTRL_TXINV; | |
1601 | lpuart32_write(port, temp, UARTCTRL); | |
c4c81db5 | 1602 | } else { |
2474e054 SS |
1603 | /* Disable the TXINV to turn off break and re-enable transmitter. */ |
1604 | temp &= ~UARTCTRL_TXINV; | |
1605 | lpuart32_write(port, temp, UARTCTRL); | |
1606 | temp |= UARTCTRL_TE; | |
1607 | lpuart32_write(port, temp, UARTCTRL); | |
c4c81db5 | 1608 | } |
380c966c JL |
1609 | } |
1610 | ||
c9e2e946 JL |
1611 | static void lpuart_setup_watermark(struct lpuart_port *sport) |
1612 | { | |
1613 | unsigned char val, cr2; | |
bc764b8f | 1614 | unsigned char cr2_saved; |
c9e2e946 JL |
1615 | |
1616 | cr2 = readb(sport->port.membase + UARTCR2); | |
bc764b8f | 1617 | cr2_saved = cr2; |
c9e2e946 JL |
1618 | cr2 &= ~(UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_TE | |
1619 | UARTCR2_RIE | UARTCR2_RE); | |
1620 | writeb(cr2, sport->port.membase + UARTCR2); | |
1621 | ||
c9e2e946 | 1622 | val = readb(sport->port.membase + UARTPFIFO); |
c9e2e946 JL |
1623 | writeb(val | UARTPFIFO_TXFE | UARTPFIFO_RXFE, |
1624 | sport->port.membase + UARTPFIFO); | |
1625 | ||
1626 | /* flush Tx and Rx FIFO */ | |
1627 | writeb(UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH, | |
1628 | sport->port.membase + UARTCFIFO); | |
1629 | ||
d68827c6 SA |
1630 | /* explicitly clear RDRF */ |
1631 | if (readb(sport->port.membase + UARTSR1) & UARTSR1_RDRF) { | |
1632 | readb(sport->port.membase + UARTDR); | |
1633 | writeb(UARTSFIFO_RXUF, sport->port.membase + UARTSFIFO); | |
1634 | } | |
1635 | ||
7c010590 SS |
1636 | if (uart_console(&sport->port)) |
1637 | sport->rx_watermark = 1; | |
f1cd8c87 | 1638 | writeb(0, sport->port.membase + UARTTWFIFO); |
34ebb26f | 1639 | writeb(sport->rx_watermark, sport->port.membase + UARTRWFIFO); |
bc764b8f SG |
1640 | |
1641 | /* Restore cr2 */ | |
1642 | writeb(cr2_saved, sport->port.membase + UARTCR2); | |
c9e2e946 JL |
1643 | } |
1644 | ||
352bd55e AS |
1645 | static void lpuart_setup_watermark_enable(struct lpuart_port *sport) |
1646 | { | |
1647 | unsigned char cr2; | |
1648 | ||
1649 | lpuart_setup_watermark(sport); | |
1650 | ||
1651 | cr2 = readb(sport->port.membase + UARTCR2); | |
f7ec1721 | 1652 | cr2 |= UARTCR2_RIE | UARTCR2_RE | UARTCR2_TE; |
352bd55e AS |
1653 | writeb(cr2, sport->port.membase + UARTCR2); |
1654 | } | |
1655 | ||
380c966c JL |
1656 | static void lpuart32_setup_watermark(struct lpuart_port *sport) |
1657 | { | |
1658 | unsigned long val, ctrl; | |
1659 | unsigned long ctrl_saved; | |
1660 | ||
a0204f25 | 1661 | ctrl = lpuart32_read(&sport->port, UARTCTRL); |
380c966c JL |
1662 | ctrl_saved = ctrl; |
1663 | ctrl &= ~(UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_TE | | |
e1d91dda | 1664 | UARTCTRL_RIE | UARTCTRL_RE | UARTCTRL_ILIE); |
a0204f25 | 1665 | lpuart32_write(&sport->port, ctrl, UARTCTRL); |
380c966c JL |
1666 | |
1667 | /* enable FIFO mode */ | |
a0204f25 | 1668 | val = lpuart32_read(&sport->port, UARTFIFO); |
380c966c JL |
1669 | val |= UARTFIFO_TXFE | UARTFIFO_RXFE; |
1670 | val |= UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH; | |
96f54fd4 | 1671 | val |= FIELD_PREP(UARTFIFO_RXIDEN, 0x3); |
a0204f25 | 1672 | lpuart32_write(&sport->port, val, UARTFIFO); |
380c966c JL |
1673 | |
1674 | /* set the watermark */ | |
7c010590 SS |
1675 | if (uart_console(&sport->port)) |
1676 | sport->rx_watermark = 1; | |
34ebb26f SS |
1677 | val = (sport->rx_watermark << UARTWATER_RXWATER_OFF) | |
1678 | (0x0 << UARTWATER_TXWATER_OFF); | |
a0204f25 | 1679 | lpuart32_write(&sport->port, val, UARTWATER); |
380c966c | 1680 | |
ecba98f9 SS |
1681 | /* set RTS watermark */ |
1682 | if (!uart_console(&sport->port)) { | |
1683 | val = lpuart32_read(&sport->port, UARTMODIR); | |
1684 | val |= FIELD_PREP(UARTMODIR_RTSWATER, sport->rxfifo_size >> 1); | |
1685 | lpuart32_write(&sport->port, val, UARTMODIR); | |
1686 | } | |
1687 | ||
380c966c | 1688 | /* Restore cr2 */ |
a0204f25 | 1689 | lpuart32_write(&sport->port, ctrl_saved, UARTCTRL); |
380c966c JL |
1690 | } |
1691 | ||
352bd55e AS |
1692 | static void lpuart32_setup_watermark_enable(struct lpuart_port *sport) |
1693 | { | |
1694 | u32 temp; | |
1695 | ||
1696 | lpuart32_setup_watermark(sport); | |
1697 | ||
1698 | temp = lpuart32_read(&sport->port, UARTCTRL); | |
e1d91dda SS |
1699 | temp |= UARTCTRL_RE | UARTCTRL_TE; |
1700 | temp |= FIELD_PREP(UARTCTRL_IDLECFG, 0x7); | |
352bd55e AS |
1701 | lpuart32_write(&sport->port, temp, UARTCTRL); |
1702 | } | |
1703 | ||
5887ad43 | 1704 | static void rx_dma_timer_init(struct lpuart_port *sport) |
f1cd8c87 | 1705 | { |
d9219528 SS |
1706 | if (sport->dma_idle_int) |
1707 | return; | |
1708 | ||
834a9741 AS |
1709 | timer_setup(&sport->lpuart_timer, lpuart_timer_func, 0); |
1710 | sport->lpuart_timer.expires = jiffies + sport->dma_rx_timeout; | |
1711 | add_timer(&sport->lpuart_timer); | |
f1cd8c87 YY |
1712 | } |
1713 | ||
d0e7600b | 1714 | static void lpuart_request_dma(struct lpuart_port *sport) |
5982199c | 1715 | { |
159381df MW |
1716 | sport->dma_tx_chan = dma_request_chan(sport->port.dev, "tx"); |
1717 | if (IS_ERR(sport->dma_tx_chan)) { | |
44da0362 FE |
1718 | dev_dbg_once(sport->port.dev, |
1719 | "DMA tx channel request failed, operating without tx DMA (%ld)\n", | |
1720 | PTR_ERR(sport->dma_tx_chan)); | |
159381df | 1721 | sport->dma_tx_chan = NULL; |
159381df MW |
1722 | } |
1723 | ||
d0e7600b MW |
1724 | sport->dma_rx_chan = dma_request_chan(sport->port.dev, "rx"); |
1725 | if (IS_ERR(sport->dma_rx_chan)) { | |
44da0362 FE |
1726 | dev_dbg_once(sport->port.dev, |
1727 | "DMA rx channel request failed, operating without rx DMA (%ld)\n", | |
1728 | PTR_ERR(sport->dma_rx_chan)); | |
d0e7600b MW |
1729 | sport->dma_rx_chan = NULL; |
1730 | } | |
1731 | } | |
1732 | ||
1733 | static void lpuart_tx_dma_startup(struct lpuart_port *sport) | |
1734 | { | |
1735 | u32 uartbaud; | |
1736 | int ret; | |
1737 | ||
8cac2f6e MW |
1738 | if (uart_console(&sport->port)) |
1739 | goto err; | |
1740 | ||
d0e7600b MW |
1741 | if (!sport->dma_tx_chan) |
1742 | goto err; | |
1743 | ||
159381df | 1744 | ret = lpuart_dma_tx_request(&sport->port); |
d7c53fb0 | 1745 | if (ret) |
159381df MW |
1746 | goto err; |
1747 | ||
1748 | init_waitqueue_head(&sport->dma_wait); | |
1749 | sport->lpuart_dma_tx_use = true; | |
1750 | if (lpuart_is_32(sport)) { | |
1751 | uartbaud = lpuart32_read(&sport->port, UARTBAUD); | |
1752 | lpuart32_write(&sport->port, | |
1753 | uartbaud | UARTBAUD_TDMAE, UARTBAUD); | |
5982199c | 1754 | } else { |
159381df MW |
1755 | writeb(readb(sport->port.membase + UARTCR5) | |
1756 | UARTCR5_TDMAS, sport->port.membase + UARTCR5); | |
5982199c | 1757 | } |
159381df MW |
1758 | |
1759 | return; | |
1760 | ||
1761 | err: | |
1762 | sport->lpuart_dma_tx_use = false; | |
5982199c AS |
1763 | } |
1764 | ||
fd60e8e4 AS |
1765 | static void lpuart_rx_dma_startup(struct lpuart_port *sport) |
1766 | { | |
159381df | 1767 | int ret; |
f4eef224 | 1768 | unsigned char cr3; |
fd60e8e4 | 1769 | |
8cac2f6e MW |
1770 | if (uart_console(&sport->port)) |
1771 | goto err; | |
1772 | ||
d0e7600b | 1773 | if (!sport->dma_rx_chan) |
159381df | 1774 | goto err; |
159381df | 1775 | |
cf9aa72d SW |
1776 | /* set default Rx DMA timeout */ |
1777 | sport->dma_rx_timeout = msecs_to_jiffies(DMA_RX_TIMEOUT); | |
1778 | ||
159381df MW |
1779 | ret = lpuart_start_rx_dma(sport); |
1780 | if (ret) | |
1781 | goto err; | |
1782 | ||
159381df MW |
1783 | if (!sport->dma_rx_timeout) |
1784 | sport->dma_rx_timeout = 1; | |
1785 | ||
1786 | sport->lpuart_dma_rx_use = true; | |
1787 | rx_dma_timer_init(sport); | |
1788 | ||
ccf08fd1 | 1789 | if (sport->port.has_sysrq && !lpuart_is_32(sport)) { |
f4eef224 AD |
1790 | cr3 = readb(sport->port.membase + UARTCR3); |
1791 | cr3 |= UARTCR3_FEIE; | |
1792 | writeb(cr3, sport->port.membase + UARTCR3); | |
1793 | } | |
1794 | ||
159381df MW |
1795 | return; |
1796 | ||
1797 | err: | |
1798 | sport->lpuart_dma_rx_use = false; | |
fd60e8e4 AS |
1799 | } |
1800 | ||
4f5cb8c5 SS |
1801 | static void lpuart_hw_setup(struct lpuart_port *sport) |
1802 | { | |
1803 | unsigned long flags; | |
1804 | ||
92f4e05b | 1805 | uart_port_lock_irqsave(&sport->port, &flags); |
4f5cb8c5 SS |
1806 | |
1807 | lpuart_setup_watermark_enable(sport); | |
1808 | ||
1809 | lpuart_rx_dma_startup(sport); | |
1810 | lpuart_tx_dma_startup(sport); | |
1811 | ||
92f4e05b | 1812 | uart_port_unlock_irqrestore(&sport->port, flags); |
4f5cb8c5 SS |
1813 | } |
1814 | ||
c9e2e946 JL |
1815 | static int lpuart_startup(struct uart_port *port) |
1816 | { | |
1817 | struct lpuart_port *sport = container_of(port, struct lpuart_port, port); | |
c9e2e946 JL |
1818 | unsigned char temp; |
1819 | ||
ed9891bf SA |
1820 | /* determine FIFO size and enable FIFO mode */ |
1821 | temp = readb(sport->port.membase + UARTPFIFO); | |
1822 | ||
f77ebb24 FD |
1823 | sport->txfifo_size = UARTFIFO_DEPTH((temp >> UARTPFIFO_TXSIZE_OFF) & |
1824 | UARTPFIFO_FIFOSIZE_MASK); | |
4e8f2459 SA |
1825 | sport->port.fifosize = sport->txfifo_size; |
1826 | ||
f77ebb24 FD |
1827 | sport->rxfifo_size = UARTFIFO_DEPTH((temp >> UARTPFIFO_RXSIZE_OFF) & |
1828 | UARTPFIFO_FIFOSIZE_MASK); | |
ed9891bf | 1829 | |
d0e7600b | 1830 | lpuart_request_dma(sport); |
4f5cb8c5 | 1831 | lpuart_hw_setup(sport); |
5887ad43 | 1832 | |
c9e2e946 JL |
1833 | return 0; |
1834 | } | |
1835 | ||
8a79052c SS |
1836 | static void lpuart32_hw_disable(struct lpuart_port *sport) |
1837 | { | |
1838 | unsigned long temp; | |
1839 | ||
1840 | temp = lpuart32_read(&sport->port, UARTCTRL); | |
1841 | temp &= ~(UARTCTRL_RIE | UARTCTRL_ILIE | UARTCTRL_RE | | |
1842 | UARTCTRL_TIE | UARTCTRL_TE); | |
1843 | lpuart32_write(&sport->port, temp, UARTCTRL); | |
1844 | } | |
1845 | ||
4ff69041 AS |
1846 | static void lpuart32_configure(struct lpuart_port *sport) |
1847 | { | |
1848 | unsigned long temp; | |
1849 | ||
4ff69041 AS |
1850 | temp = lpuart32_read(&sport->port, UARTCTRL); |
1851 | if (!sport->lpuart_dma_rx_use) | |
e1d91dda | 1852 | temp |= UARTCTRL_RIE | UARTCTRL_ILIE; |
4ff69041 AS |
1853 | if (!sport->lpuart_dma_tx_use) |
1854 | temp |= UARTCTRL_TIE; | |
1855 | lpuart32_write(&sport->port, temp, UARTCTRL); | |
1856 | } | |
1857 | ||
4f5cb8c5 SS |
1858 | static void lpuart32_hw_setup(struct lpuart_port *sport) |
1859 | { | |
1860 | unsigned long flags; | |
1861 | ||
92f4e05b | 1862 | uart_port_lock_irqsave(&sport->port, &flags); |
4f5cb8c5 | 1863 | |
8a79052c | 1864 | lpuart32_hw_disable(sport); |
4f5cb8c5 SS |
1865 | |
1866 | lpuart_rx_dma_startup(sport); | |
1867 | lpuart_tx_dma_startup(sport); | |
1868 | ||
8a79052c | 1869 | lpuart32_setup_watermark_enable(sport); |
4f5cb8c5 SS |
1870 | lpuart32_configure(sport); |
1871 | ||
92f4e05b | 1872 | uart_port_unlock_irqrestore(&sport->port, flags); |
4f5cb8c5 SS |
1873 | } |
1874 | ||
380c966c JL |
1875 | static int lpuart32_startup(struct uart_port *port) |
1876 | { | |
1877 | struct lpuart_port *sport = container_of(port, struct lpuart_port, port); | |
380c966c JL |
1878 | unsigned long temp; |
1879 | ||
1880 | /* determine FIFO size */ | |
a0204f25 | 1881 | temp = lpuart32_read(&sport->port, UARTFIFO); |
380c966c | 1882 | |
f77ebb24 FD |
1883 | sport->txfifo_size = UARTFIFO_DEPTH((temp >> UARTFIFO_TXSIZE_OFF) & |
1884 | UARTFIFO_FIFOSIZE_MASK); | |
b0b2735a AN |
1885 | sport->port.fifosize = sport->txfifo_size; |
1886 | ||
f77ebb24 FD |
1887 | sport->rxfifo_size = UARTFIFO_DEPTH((temp >> UARTFIFO_RXSIZE_OFF) & |
1888 | UARTFIFO_FIFOSIZE_MASK); | |
380c966c | 1889 | |
c2f448cf | 1890 | /* |
c97f2a6f VO |
1891 | * The LS1021A and LS1028A have a fixed FIFO depth of 16 words. |
1892 | * Although they support the RX/TXSIZE fields, their encoding is | |
1893 | * different. Eg the reference manual states 0b101 is 16 words. | |
c2f448cf | 1894 | */ |
c97f2a6f | 1895 | if (is_layerscape_lpuart(sport)) { |
c2f448cf MW |
1896 | sport->rxfifo_size = 16; |
1897 | sport->txfifo_size = 16; | |
1898 | sport->port.fifosize = sport->txfifo_size; | |
1899 | } | |
1900 | ||
d0e7600b | 1901 | lpuart_request_dma(sport); |
4f5cb8c5 | 1902 | lpuart32_hw_setup(sport); |
d0e7600b | 1903 | |
380c966c JL |
1904 | return 0; |
1905 | } | |
1906 | ||
769d55c5 AS |
1907 | static void lpuart_dma_shutdown(struct lpuart_port *sport) |
1908 | { | |
1909 | if (sport->lpuart_dma_rx_use) { | |
769d55c5 | 1910 | lpuart_dma_rx_free(&sport->port); |
316ae95c | 1911 | sport->lpuart_dma_rx_use = false; |
769d55c5 AS |
1912 | } |
1913 | ||
1914 | if (sport->lpuart_dma_tx_use) { | |
ffccc78a SS |
1915 | if (wait_event_interruptible_timeout(sport->dma_wait, |
1916 | !sport->dma_tx_in_progress, msecs_to_jiffies(300)) <= 0) { | |
769d55c5 | 1917 | sport->dma_tx_in_progress = false; |
8682ab0e | 1918 | dmaengine_terminate_sync(sport->dma_tx_chan); |
769d55c5 | 1919 | } |
316ae95c | 1920 | sport->lpuart_dma_tx_use = false; |
769d55c5 | 1921 | } |
159381df MW |
1922 | |
1923 | if (sport->dma_tx_chan) | |
1924 | dma_release_channel(sport->dma_tx_chan); | |
1925 | if (sport->dma_rx_chan) | |
1926 | dma_release_channel(sport->dma_rx_chan); | |
769d55c5 AS |
1927 | } |
1928 | ||
c9e2e946 JL |
1929 | static void lpuart_shutdown(struct uart_port *port) |
1930 | { | |
1931 | struct lpuart_port *sport = container_of(port, struct lpuart_port, port); | |
1932 | unsigned char temp; | |
1933 | unsigned long flags; | |
1934 | ||
92f4e05b | 1935 | uart_port_lock_irqsave(port, &flags); |
c9e2e946 JL |
1936 | |
1937 | /* disable Rx/Tx and interrupts */ | |
1938 | temp = readb(port->membase + UARTCR2); | |
1939 | temp &= ~(UARTCR2_TE | UARTCR2_RE | | |
1940 | UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_RIE); | |
1941 | writeb(temp, port->membase + UARTCR2); | |
1942 | ||
92f4e05b | 1943 | uart_port_unlock_irqrestore(port, flags); |
c9e2e946 | 1944 | |
769d55c5 | 1945 | lpuart_dma_shutdown(sport); |
c9e2e946 JL |
1946 | } |
1947 | ||
380c966c JL |
1948 | static void lpuart32_shutdown(struct uart_port *port) |
1949 | { | |
42b68768 AN |
1950 | struct lpuart_port *sport = |
1951 | container_of(port, struct lpuart_port, port); | |
380c966c JL |
1952 | unsigned long temp; |
1953 | unsigned long flags; | |
1954 | ||
92f4e05b | 1955 | uart_port_lock_irqsave(port, &flags); |
380c966c | 1956 | |
4029dfc0 SS |
1957 | /* clear status */ |
1958 | temp = lpuart32_read(&sport->port, UARTSTAT); | |
1959 | lpuart32_write(&sport->port, temp, UARTSTAT); | |
1960 | ||
1d4bd0e4 SS |
1961 | /* disable Rx/Tx DMA */ |
1962 | temp = lpuart32_read(port, UARTBAUD); | |
1963 | temp &= ~(UARTBAUD_TDMAE | UARTBAUD_RDMAE); | |
1964 | lpuart32_write(port, temp, UARTBAUD); | |
1965 | ||
10929eac | 1966 | /* disable Rx/Tx and interrupts and break condition */ |
a0204f25 | 1967 | temp = lpuart32_read(port, UARTCTRL); |
e1d91dda | 1968 | temp &= ~(UARTCTRL_TE | UARTCTRL_RE | UARTCTRL_ILIE | |
10929eac | 1969 | UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_RIE | UARTCTRL_SBK); |
a0204f25 | 1970 | lpuart32_write(port, temp, UARTCTRL); |
380c966c | 1971 | |
92f4e05b | 1972 | uart_port_unlock_irqrestore(port, flags); |
42b68768 | 1973 | |
769d55c5 | 1974 | lpuart_dma_shutdown(sport); |
380c966c JL |
1975 | } |
1976 | ||
c9e2e946 JL |
1977 | static void |
1978 | lpuart_set_termios(struct uart_port *port, struct ktermios *termios, | |
bec5b814 | 1979 | const struct ktermios *old) |
c9e2e946 JL |
1980 | { |
1981 | struct lpuart_port *sport = container_of(port, struct lpuart_port, port); | |
1982 | unsigned long flags; | |
aa9e7d78 | 1983 | unsigned char cr1, old_cr1, old_cr2, cr3, cr4, bdh, modem; |
c9e2e946 JL |
1984 | unsigned int baud; |
1985 | unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8; | |
1986 | unsigned int sbr, brfa; | |
1987 | ||
1988 | cr1 = old_cr1 = readb(sport->port.membase + UARTCR1); | |
1989 | old_cr2 = readb(sport->port.membase + UARTCR2); | |
aa9e7d78 | 1990 | cr3 = readb(sport->port.membase + UARTCR3); |
c9e2e946 JL |
1991 | cr4 = readb(sport->port.membase + UARTCR4); |
1992 | bdh = readb(sport->port.membase + UARTBDH); | |
1993 | modem = readb(sport->port.membase + UARTMODEM); | |
1994 | /* | |
1995 | * only support CS8 and CS7, and for CS7 must enable PE. | |
1996 | * supported mode: | |
1997 | * - (7,e/o,1) | |
1998 | * - (8,n,1) | |
1999 | * - (8,m/s,1) | |
2000 | * - (8,e/o,1) | |
2001 | */ | |
2002 | while ((termios->c_cflag & CSIZE) != CS8 && | |
2003 | (termios->c_cflag & CSIZE) != CS7) { | |
2004 | termios->c_cflag &= ~CSIZE; | |
2005 | termios->c_cflag |= old_csize; | |
2006 | old_csize = CS8; | |
2007 | } | |
2008 | ||
2009 | if ((termios->c_cflag & CSIZE) == CS8 || | |
2010 | (termios->c_cflag & CSIZE) == CS7) | |
2011 | cr1 = old_cr1 & ~UARTCR1_M; | |
2012 | ||
2013 | if (termios->c_cflag & CMSPAR) { | |
2014 | if ((termios->c_cflag & CSIZE) != CS8) { | |
2015 | termios->c_cflag &= ~CSIZE; | |
2016 | termios->c_cflag |= CS8; | |
2017 | } | |
2018 | cr1 |= UARTCR1_M; | |
2019 | } | |
2020 | ||
03895cf4 BD |
2021 | /* |
2022 | * When auto RS-485 RTS mode is enabled, | |
2023 | * hardware flow control need to be disabled. | |
2024 | */ | |
2025 | if (sport->port.rs485.flags & SER_RS485_ENABLED) | |
2026 | termios->c_cflag &= ~CRTSCTS; | |
2027 | ||
d26454ee | 2028 | if (termios->c_cflag & CRTSCTS) |
bcfa46bf | 2029 | modem |= UARTMODEM_RXRTSE | UARTMODEM_TXCTSE; |
d26454ee | 2030 | else |
c9e2e946 | 2031 | modem &= ~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE); |
c9e2e946 | 2032 | |
76e3f2ac | 2033 | termios->c_cflag &= ~CSTOPB; |
c9e2e946 JL |
2034 | |
2035 | /* parity must be enabled when CS7 to match 8-bits format */ | |
2036 | if ((termios->c_cflag & CSIZE) == CS7) | |
2037 | termios->c_cflag |= PARENB; | |
2038 | ||
bcfa46bf | 2039 | if (termios->c_cflag & PARENB) { |
c9e2e946 JL |
2040 | if (termios->c_cflag & CMSPAR) { |
2041 | cr1 &= ~UARTCR1_PE; | |
aa9e7d78 BD |
2042 | if (termios->c_cflag & PARODD) |
2043 | cr3 |= UARTCR3_T8; | |
2044 | else | |
2045 | cr3 &= ~UARTCR3_T8; | |
c9e2e946 JL |
2046 | } else { |
2047 | cr1 |= UARTCR1_PE; | |
2048 | if ((termios->c_cflag & CSIZE) == CS8) | |
2049 | cr1 |= UARTCR1_M; | |
2050 | if (termios->c_cflag & PARODD) | |
2051 | cr1 |= UARTCR1_PT; | |
2052 | else | |
2053 | cr1 &= ~UARTCR1_PT; | |
2054 | } | |
397bd921 AD |
2055 | } else { |
2056 | cr1 &= ~UARTCR1_PE; | |
c9e2e946 JL |
2057 | } |
2058 | ||
2059 | /* ask the core to calculate the divisor */ | |
2060 | baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16); | |
2061 | ||
54a44d54 NY |
2062 | /* |
2063 | * Need to update the Ring buffer length according to the selected | |
2064 | * baud rate and restart Rx DMA path. | |
2065 | * | |
2066 | * Since timer function acqures sport->port.lock, need to stop before | |
2067 | * acquring same lock because otherwise del_timer_sync() can deadlock. | |
2068 | */ | |
1be6f2b1 | 2069 | if (old && sport->lpuart_dma_rx_use) |
54a44d54 | 2070 | lpuart_dma_rx_free(&sport->port); |
54a44d54 | 2071 | |
92f4e05b | 2072 | uart_port_lock_irqsave(&sport->port, &flags); |
c9e2e946 JL |
2073 | |
2074 | sport->port.read_status_mask = 0; | |
2075 | if (termios->c_iflag & INPCK) | |
bcfa46bf | 2076 | sport->port.read_status_mask |= UARTSR1_FE | UARTSR1_PE; |
ef8b9ddc | 2077 | if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) |
c9e2e946 JL |
2078 | sport->port.read_status_mask |= UARTSR1_FE; |
2079 | ||
2080 | /* characters to ignore */ | |
2081 | sport->port.ignore_status_mask = 0; | |
2082 | if (termios->c_iflag & IGNPAR) | |
2083 | sport->port.ignore_status_mask |= UARTSR1_PE; | |
2084 | if (termios->c_iflag & IGNBRK) { | |
2085 | sport->port.ignore_status_mask |= UARTSR1_FE; | |
2086 | /* | |
2087 | * if we're ignoring parity and break indicators, | |
2088 | * ignore overruns too (for real raw support). | |
2089 | */ | |
2090 | if (termios->c_iflag & IGNPAR) | |
2091 | sport->port.ignore_status_mask |= UARTSR1_OR; | |
2092 | } | |
2093 | ||
2094 | /* update the per-port timeout */ | |
2095 | uart_update_timeout(port, termios->c_cflag, baud); | |
2096 | ||
2097 | /* wait transmit engin complete */ | |
56dd627f | 2098 | lpuart_wait_bit_set(&sport->port, UARTSR1, UARTSR1_TC); |
c9e2e946 JL |
2099 | |
2100 | /* disable transmit and receive */ | |
2101 | writeb(old_cr2 & ~(UARTCR2_TE | UARTCR2_RE), | |
2102 | sport->port.membase + UARTCR2); | |
2103 | ||
2104 | sbr = sport->port.uartclk / (16 * baud); | |
2105 | brfa = ((sport->port.uartclk - (16 * sbr * baud)) * 2) / baud; | |
2106 | bdh &= ~UARTBDH_SBR_MASK; | |
2107 | bdh |= (sbr >> 8) & 0x1F; | |
2108 | cr4 &= ~UARTCR4_BRFA_MASK; | |
2109 | brfa &= UARTCR4_BRFA_MASK; | |
2110 | writeb(cr4 | brfa, sport->port.membase + UARTCR4); | |
2111 | writeb(bdh, sport->port.membase + UARTBDH); | |
2112 | writeb(sbr & 0xFF, sport->port.membase + UARTBDL); | |
aa9e7d78 | 2113 | writeb(cr3, sport->port.membase + UARTCR3); |
c9e2e946 JL |
2114 | writeb(cr1, sport->port.membase + UARTCR1); |
2115 | writeb(modem, sport->port.membase + UARTMODEM); | |
2116 | ||
2117 | /* restore control register */ | |
2118 | writeb(old_cr2, sport->port.membase + UARTCR2); | |
2119 | ||
54a44d54 NY |
2120 | if (old && sport->lpuart_dma_rx_use) { |
2121 | if (!lpuart_start_rx_dma(sport)) | |
5887ad43 | 2122 | rx_dma_timer_init(sport); |
54a44d54 | 2123 | else |
5887ad43 | 2124 | sport->lpuart_dma_rx_use = false; |
5887ad43 BD |
2125 | } |
2126 | ||
92f4e05b | 2127 | uart_port_unlock_irqrestore(&sport->port, flags); |
c9e2e946 JL |
2128 | } |
2129 | ||
e33253f3 MW |
2130 | static void __lpuart32_serial_setbrg(struct uart_port *port, |
2131 | unsigned int baudrate, bool use_rx_dma, | |
2132 | bool use_tx_dma) | |
a6d7514b DA |
2133 | { |
2134 | u32 sbr, osr, baud_diff, tmp_osr, tmp_sbr, tmp_diff, tmp; | |
e33253f3 | 2135 | u32 clk = port->uartclk; |
a6d7514b DA |
2136 | |
2137 | /* | |
2138 | * The idea is to use the best OSR (over-sampling rate) possible. | |
2139 | * Note, OSR is typically hard-set to 16 in other LPUART instantiations. | |
2140 | * Loop to find the best OSR value possible, one that generates minimum | |
2141 | * baud_diff iterate through the rest of the supported values of OSR. | |
2142 | * | |
2143 | * Calculation Formula: | |
2144 | * Baud Rate = baud clock / ((OSR+1) × SBR) | |
2145 | */ | |
2146 | baud_diff = baudrate; | |
2147 | osr = 0; | |
2148 | sbr = 0; | |
2149 | ||
2150 | for (tmp_osr = 4; tmp_osr <= 32; tmp_osr++) { | |
2151 | /* calculate the temporary sbr value */ | |
2152 | tmp_sbr = (clk / (baudrate * tmp_osr)); | |
2153 | if (tmp_sbr == 0) | |
2154 | tmp_sbr = 1; | |
2155 | ||
2156 | /* | |
2157 | * calculate the baud rate difference based on the temporary | |
2158 | * osr and sbr values | |
2159 | */ | |
2160 | tmp_diff = clk / (tmp_osr * tmp_sbr) - baudrate; | |
2161 | ||
2162 | /* select best values between sbr and sbr+1 */ | |
2163 | tmp = clk / (tmp_osr * (tmp_sbr + 1)); | |
2164 | if (tmp_diff > (baudrate - tmp)) { | |
2165 | tmp_diff = baudrate - tmp; | |
2166 | tmp_sbr++; | |
2167 | } | |
2168 | ||
d10ee1d1 VS |
2169 | if (tmp_sbr > UARTBAUD_SBR_MASK) |
2170 | continue; | |
2171 | ||
a6d7514b DA |
2172 | if (tmp_diff <= baud_diff) { |
2173 | baud_diff = tmp_diff; | |
2174 | osr = tmp_osr; | |
2175 | sbr = tmp_sbr; | |
2176 | ||
2177 | if (!baud_diff) | |
2178 | break; | |
2179 | } | |
2180 | } | |
2181 | ||
2182 | /* handle buadrate outside acceptable rate */ | |
2183 | if (baud_diff > ((baudrate / 100) * 3)) | |
e33253f3 | 2184 | dev_warn(port->dev, |
a6d7514b DA |
2185 | "unacceptable baud rate difference of more than 3%%\n"); |
2186 | ||
e33253f3 | 2187 | tmp = lpuart32_read(port, UARTBAUD); |
a6d7514b DA |
2188 | |
2189 | if ((osr > 3) && (osr < 8)) | |
2190 | tmp |= UARTBAUD_BOTHEDGE; | |
2191 | ||
2192 | tmp &= ~(UARTBAUD_OSR_MASK << UARTBAUD_OSR_SHIFT); | |
bcfa46bf | 2193 | tmp |= ((osr-1) & UARTBAUD_OSR_MASK) << UARTBAUD_OSR_SHIFT; |
a6d7514b DA |
2194 | |
2195 | tmp &= ~UARTBAUD_SBR_MASK; | |
2196 | tmp |= sbr & UARTBAUD_SBR_MASK; | |
2197 | ||
e33253f3 | 2198 | if (!use_rx_dma) |
42b68768 | 2199 | tmp &= ~UARTBAUD_RDMAE; |
e33253f3 | 2200 | if (!use_tx_dma) |
42b68768 | 2201 | tmp &= ~UARTBAUD_TDMAE; |
a6d7514b | 2202 | |
e33253f3 MW |
2203 | lpuart32_write(port, tmp, UARTBAUD); |
2204 | } | |
2205 | ||
2206 | static void lpuart32_serial_setbrg(struct lpuart_port *sport, | |
2207 | unsigned int baudrate) | |
2208 | { | |
2209 | __lpuart32_serial_setbrg(&sport->port, baudrate, | |
2210 | sport->lpuart_dma_rx_use, | |
2211 | sport->lpuart_dma_tx_use); | |
a6d7514b DA |
2212 | } |
2213 | ||
e33253f3 | 2214 | |
380c966c JL |
2215 | static void |
2216 | lpuart32_set_termios(struct uart_port *port, struct ktermios *termios, | |
bec5b814 | 2217 | const struct ktermios *old) |
380c966c JL |
2218 | { |
2219 | struct lpuart_port *sport = container_of(port, struct lpuart_port, port); | |
2220 | unsigned long flags; | |
48422152 | 2221 | unsigned long ctrl, old_ctrl, bd, modem; |
380c966c JL |
2222 | unsigned int baud; |
2223 | unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8; | |
380c966c | 2224 | |
a0204f25 | 2225 | ctrl = old_ctrl = lpuart32_read(&sport->port, UARTCTRL); |
48422152 | 2226 | bd = lpuart32_read(&sport->port, UARTBAUD); |
a0204f25 | 2227 | modem = lpuart32_read(&sport->port, UARTMODIR); |
070298c8 | 2228 | sport->is_cs7 = false; |
380c966c JL |
2229 | /* |
2230 | * only support CS8 and CS7, and for CS7 must enable PE. | |
2231 | * supported mode: | |
2232 | * - (7,e/o,1) | |
2233 | * - (8,n,1) | |
2234 | * - (8,m/s,1) | |
2235 | * - (8,e/o,1) | |
2236 | */ | |
2237 | while ((termios->c_cflag & CSIZE) != CS8 && | |
2238 | (termios->c_cflag & CSIZE) != CS7) { | |
2239 | termios->c_cflag &= ~CSIZE; | |
2240 | termios->c_cflag |= old_csize; | |
2241 | old_csize = CS8; | |
2242 | } | |
2243 | ||
2244 | if ((termios->c_cflag & CSIZE) == CS8 || | |
2245 | (termios->c_cflag & CSIZE) == CS7) | |
2246 | ctrl = old_ctrl & ~UARTCTRL_M; | |
2247 | ||
2248 | if (termios->c_cflag & CMSPAR) { | |
2249 | if ((termios->c_cflag & CSIZE) != CS8) { | |
2250 | termios->c_cflag &= ~CSIZE; | |
2251 | termios->c_cflag |= CS8; | |
2252 | } | |
2253 | ctrl |= UARTCTRL_M; | |
2254 | } | |
2255 | ||
67b01837 PS |
2256 | /* |
2257 | * When auto RS-485 RTS mode is enabled, | |
2258 | * hardware flow control need to be disabled. | |
2259 | */ | |
2260 | if (sport->port.rs485.flags & SER_RS485_ENABLED) | |
2261 | termios->c_cflag &= ~CRTSCTS; | |
2262 | ||
503f418b IJ |
2263 | if (termios->c_cflag & CRTSCTS) |
2264 | modem |= UARTMODIR_RXRTSE | UARTMODIR_TXCTSE; | |
2265 | else | |
e3553fee | 2266 | modem &= ~(UARTMODIR_RXRTSE | UARTMODIR_TXCTSE); |
380c966c JL |
2267 | |
2268 | if (termios->c_cflag & CSTOPB) | |
48422152 FD |
2269 | bd |= UARTBAUD_SBNS; |
2270 | else | |
2271 | bd &= ~UARTBAUD_SBNS; | |
380c966c JL |
2272 | |
2273 | /* parity must be enabled when CS7 to match 8-bits format */ | |
2274 | if ((termios->c_cflag & CSIZE) == CS7) | |
2275 | termios->c_cflag |= PARENB; | |
2276 | ||
2277 | if ((termios->c_cflag & PARENB)) { | |
2278 | if (termios->c_cflag & CMSPAR) { | |
2279 | ctrl &= ~UARTCTRL_PE; | |
2280 | ctrl |= UARTCTRL_M; | |
2281 | } else { | |
61e169ee | 2282 | ctrl |= UARTCTRL_PE; |
380c966c JL |
2283 | if ((termios->c_cflag & CSIZE) == CS8) |
2284 | ctrl |= UARTCTRL_M; | |
2285 | if (termios->c_cflag & PARODD) | |
2286 | ctrl |= UARTCTRL_PT; | |
2287 | else | |
2288 | ctrl &= ~UARTCTRL_PT; | |
2289 | } | |
397bd921 AD |
2290 | } else { |
2291 | ctrl &= ~UARTCTRL_PE; | |
380c966c JL |
2292 | } |
2293 | ||
2294 | /* ask the core to calculate the divisor */ | |
815d835b | 2295 | baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 4); |
380c966c | 2296 | |
42b68768 AN |
2297 | /* |
2298 | * Need to update the Ring buffer length according to the selected | |
2299 | * baud rate and restart Rx DMA path. | |
2300 | * | |
2301 | * Since timer function acqures sport->port.lock, need to stop before | |
2302 | * acquring same lock because otherwise del_timer_sync() can deadlock. | |
2303 | */ | |
1be6f2b1 | 2304 | if (old && sport->lpuart_dma_rx_use) |
42b68768 | 2305 | lpuart_dma_rx_free(&sport->port); |
42b68768 | 2306 | |
92f4e05b | 2307 | uart_port_lock_irqsave(&sport->port, &flags); |
380c966c JL |
2308 | |
2309 | sport->port.read_status_mask = 0; | |
2310 | if (termios->c_iflag & INPCK) | |
bcfa46bf | 2311 | sport->port.read_status_mask |= UARTSTAT_FE | UARTSTAT_PE; |
380c966c JL |
2312 | if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) |
2313 | sport->port.read_status_mask |= UARTSTAT_FE; | |
2314 | ||
2315 | /* characters to ignore */ | |
2316 | sport->port.ignore_status_mask = 0; | |
2317 | if (termios->c_iflag & IGNPAR) | |
2318 | sport->port.ignore_status_mask |= UARTSTAT_PE; | |
2319 | if (termios->c_iflag & IGNBRK) { | |
2320 | sport->port.ignore_status_mask |= UARTSTAT_FE; | |
2321 | /* | |
2322 | * if we're ignoring parity and break indicators, | |
2323 | * ignore overruns too (for real raw support). | |
2324 | */ | |
2325 | if (termios->c_iflag & IGNPAR) | |
2326 | sport->port.ignore_status_mask |= UARTSTAT_OR; | |
2327 | } | |
2328 | ||
2329 | /* update the per-port timeout */ | |
2330 | uart_update_timeout(port, termios->c_cflag, baud); | |
2331 | ||
2411fd94 SS |
2332 | /* |
2333 | * LPUART Transmission Complete Flag may never be set while queuing a break | |
2334 | * character, so skip waiting for transmission complete when UARTCTRL_SBK is | |
2335 | * asserted. | |
2336 | */ | |
2337 | if (!(old_ctrl & UARTCTRL_SBK)) { | |
2338 | lpuart32_write(&sport->port, 0, UARTMODIR); | |
2339 | lpuart32_wait_bit_set(&sport->port, UARTSTAT, UARTSTAT_TC); | |
2340 | } | |
380c966c JL |
2341 | |
2342 | /* disable transmit and receive */ | |
a0204f25 DA |
2343 | lpuart32_write(&sport->port, old_ctrl & ~(UARTCTRL_TE | UARTCTRL_RE), |
2344 | UARTCTRL); | |
380c966c | 2345 | |
48422152 | 2346 | lpuart32_write(&sport->port, bd, UARTBAUD); |
a6d7514b | 2347 | lpuart32_serial_setbrg(sport, baud); |
74cb7e03 SS |
2348 | /* disable CTS before enabling UARTCTRL_TE to avoid pending idle preamble */ |
2349 | lpuart32_write(&sport->port, modem & ~UARTMODIR_TXCTSE, UARTMODIR); | |
380c966c | 2350 | /* restore control register */ |
74cb7e03 SS |
2351 | lpuart32_write(&sport->port, ctrl, UARTCTRL); |
2352 | /* re-enable the CTS if needed */ | |
2353 | lpuart32_write(&sport->port, modem, UARTMODIR); | |
380c966c | 2354 | |
070298c8 SW |
2355 | if ((ctrl & (UARTCTRL_PE | UARTCTRL_M)) == UARTCTRL_PE) |
2356 | sport->is_cs7 = true; | |
2357 | ||
42b68768 AN |
2358 | if (old && sport->lpuart_dma_rx_use) { |
2359 | if (!lpuart_start_rx_dma(sport)) | |
2360 | rx_dma_timer_init(sport); | |
2361 | else | |
2362 | sport->lpuart_dma_rx_use = false; | |
2363 | } | |
2364 | ||
92f4e05b | 2365 | uart_port_unlock_irqrestore(&sport->port, flags); |
380c966c JL |
2366 | } |
2367 | ||
c9e2e946 JL |
2368 | static const char *lpuart_type(struct uart_port *port) |
2369 | { | |
2370 | return "FSL_LPUART"; | |
2371 | } | |
2372 | ||
2373 | static void lpuart_release_port(struct uart_port *port) | |
2374 | { | |
2375 | /* nothing to do */ | |
2376 | } | |
2377 | ||
2378 | static int lpuart_request_port(struct uart_port *port) | |
2379 | { | |
2380 | return 0; | |
2381 | } | |
2382 | ||
2383 | /* configure/autoconfigure the port */ | |
2384 | static void lpuart_config_port(struct uart_port *port, int flags) | |
2385 | { | |
2386 | if (flags & UART_CONFIG_TYPE) | |
2387 | port->type = PORT_LPUART; | |
2388 | } | |
2389 | ||
2390 | static int lpuart_verify_port(struct uart_port *port, struct serial_struct *ser) | |
2391 | { | |
2392 | int ret = 0; | |
2393 | ||
2394 | if (ser->type != PORT_UNKNOWN && ser->type != PORT_LPUART) | |
2395 | ret = -EINVAL; | |
2396 | if (port->irq != ser->irq) | |
2397 | ret = -EINVAL; | |
2398 | if (ser->io_type != UPIO_MEM) | |
2399 | ret = -EINVAL; | |
2400 | if (port->uartclk / 16 != ser->baud_base) | |
2401 | ret = -EINVAL; | |
2402 | if (port->iobase != ser->port) | |
2403 | ret = -EINVAL; | |
2404 | if (ser->hub6 != 0) | |
2405 | ret = -EINVAL; | |
2406 | return ret; | |
2407 | } | |
2408 | ||
069a47e5 | 2409 | static const struct uart_ops lpuart_pops = { |
c9e2e946 JL |
2410 | .tx_empty = lpuart_tx_empty, |
2411 | .set_mctrl = lpuart_set_mctrl, | |
2412 | .get_mctrl = lpuart_get_mctrl, | |
2413 | .stop_tx = lpuart_stop_tx, | |
2414 | .start_tx = lpuart_start_tx, | |
2415 | .stop_rx = lpuart_stop_rx, | |
c9e2e946 JL |
2416 | .break_ctl = lpuart_break_ctl, |
2417 | .startup = lpuart_startup, | |
2418 | .shutdown = lpuart_shutdown, | |
2419 | .set_termios = lpuart_set_termios, | |
43543e6f | 2420 | .pm = lpuart_uart_pm, |
c9e2e946 JL |
2421 | .type = lpuart_type, |
2422 | .request_port = lpuart_request_port, | |
2423 | .release_port = lpuart_release_port, | |
2424 | .config_port = lpuart_config_port, | |
2425 | .verify_port = lpuart_verify_port, | |
bfc2e07f | 2426 | .flush_buffer = lpuart_flush_buffer, |
2a41bc2a NR |
2427 | #if defined(CONFIG_CONSOLE_POLL) |
2428 | .poll_init = lpuart_poll_init, | |
2429 | .poll_get_char = lpuart_poll_get_char, | |
2430 | .poll_put_char = lpuart_poll_put_char, | |
2431 | #endif | |
c9e2e946 JL |
2432 | }; |
2433 | ||
069a47e5 | 2434 | static const struct uart_ops lpuart32_pops = { |
380c966c JL |
2435 | .tx_empty = lpuart32_tx_empty, |
2436 | .set_mctrl = lpuart32_set_mctrl, | |
2437 | .get_mctrl = lpuart32_get_mctrl, | |
2438 | .stop_tx = lpuart32_stop_tx, | |
2439 | .start_tx = lpuart32_start_tx, | |
2440 | .stop_rx = lpuart32_stop_rx, | |
2441 | .break_ctl = lpuart32_break_ctl, | |
2442 | .startup = lpuart32_startup, | |
2443 | .shutdown = lpuart32_shutdown, | |
2444 | .set_termios = lpuart32_set_termios, | |
43543e6f | 2445 | .pm = lpuart_uart_pm, |
380c966c JL |
2446 | .type = lpuart_type, |
2447 | .request_port = lpuart_request_port, | |
2448 | .release_port = lpuart_release_port, | |
2449 | .config_port = lpuart_config_port, | |
2450 | .verify_port = lpuart_verify_port, | |
bfc2e07f | 2451 | .flush_buffer = lpuart_flush_buffer, |
a5fa2660 MV |
2452 | #if defined(CONFIG_CONSOLE_POLL) |
2453 | .poll_init = lpuart32_poll_init, | |
2454 | .poll_get_char = lpuart32_poll_get_char, | |
2455 | .poll_put_char = lpuart32_poll_put_char, | |
2456 | #endif | |
380c966c JL |
2457 | }; |
2458 | ||
c9e2e946 JL |
2459 | static struct lpuart_port *lpuart_ports[UART_NR]; |
2460 | ||
2461 | #ifdef CONFIG_SERIAL_FSL_LPUART_CONSOLE | |
3f8bab17 | 2462 | static void lpuart_console_putchar(struct uart_port *port, unsigned char ch) |
c9e2e946 | 2463 | { |
56dd627f | 2464 | lpuart_wait_bit_set(port, UARTSR1, UARTSR1_TDRE); |
c9e2e946 JL |
2465 | writeb(ch, port->membase + UARTDR); |
2466 | } | |
2467 | ||
3f8bab17 | 2468 | static void lpuart32_console_putchar(struct uart_port *port, unsigned char ch) |
380c966c | 2469 | { |
56dd627f | 2470 | lpuart32_wait_bit_set(port, UARTSTAT, UARTSTAT_TDRE); |
a0204f25 | 2471 | lpuart32_write(port, ch, UARTDATA); |
380c966c JL |
2472 | } |
2473 | ||
c9e2e946 JL |
2474 | static void |
2475 | lpuart_console_write(struct console *co, const char *s, unsigned int count) | |
2476 | { | |
2477 | struct lpuart_port *sport = lpuart_ports[co->index]; | |
2478 | unsigned char old_cr2, cr2; | |
abf1e0a9 SA |
2479 | unsigned long flags; |
2480 | int locked = 1; | |
2481 | ||
5697df73 | 2482 | if (oops_in_progress) |
92f4e05b | 2483 | locked = uart_port_trylock_irqsave(&sport->port, &flags); |
abf1e0a9 | 2484 | else |
92f4e05b | 2485 | uart_port_lock_irqsave(&sport->port, &flags); |
c9e2e946 JL |
2486 | |
2487 | /* first save CR2 and then disable interrupts */ | |
2488 | cr2 = old_cr2 = readb(sport->port.membase + UARTCR2); | |
bcfa46bf | 2489 | cr2 |= UARTCR2_TE | UARTCR2_RE; |
c9e2e946 JL |
2490 | cr2 &= ~(UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_RIE); |
2491 | writeb(cr2, sport->port.membase + UARTCR2); | |
2492 | ||
2493 | uart_console_write(&sport->port, s, count, lpuart_console_putchar); | |
2494 | ||
2495 | /* wait for transmitter finish complete and restore CR2 */ | |
56dd627f | 2496 | lpuart_wait_bit_set(&sport->port, UARTSR1, UARTSR1_TC); |
c9e2e946 JL |
2497 | |
2498 | writeb(old_cr2, sport->port.membase + UARTCR2); | |
abf1e0a9 SA |
2499 | |
2500 | if (locked) | |
92f4e05b | 2501 | uart_port_unlock_irqrestore(&sport->port, flags); |
c9e2e946 JL |
2502 | } |
2503 | ||
380c966c JL |
2504 | static void |
2505 | lpuart32_console_write(struct console *co, const char *s, unsigned int count) | |
2506 | { | |
2507 | struct lpuart_port *sport = lpuart_ports[co->index]; | |
2508 | unsigned long old_cr, cr; | |
abf1e0a9 SA |
2509 | unsigned long flags; |
2510 | int locked = 1; | |
2511 | ||
5697df73 | 2512 | if (oops_in_progress) |
92f4e05b | 2513 | locked = uart_port_trylock_irqsave(&sport->port, &flags); |
abf1e0a9 | 2514 | else |
92f4e05b | 2515 | uart_port_lock_irqsave(&sport->port, &flags); |
380c966c JL |
2516 | |
2517 | /* first save CR2 and then disable interrupts */ | |
a0204f25 | 2518 | cr = old_cr = lpuart32_read(&sport->port, UARTCTRL); |
bcfa46bf | 2519 | cr |= UARTCTRL_TE | UARTCTRL_RE; |
380c966c | 2520 | cr &= ~(UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_RIE); |
a0204f25 | 2521 | lpuart32_write(&sport->port, cr, UARTCTRL); |
380c966c JL |
2522 | |
2523 | uart_console_write(&sport->port, s, count, lpuart32_console_putchar); | |
2524 | ||
2525 | /* wait for transmitter finish complete and restore CR2 */ | |
56dd627f | 2526 | lpuart32_wait_bit_set(&sport->port, UARTSTAT, UARTSTAT_TC); |
380c966c | 2527 | |
a0204f25 | 2528 | lpuart32_write(&sport->port, old_cr, UARTCTRL); |
abf1e0a9 SA |
2529 | |
2530 | if (locked) | |
92f4e05b | 2531 | uart_port_unlock_irqrestore(&sport->port, flags); |
380c966c JL |
2532 | } |
2533 | ||
c9e2e946 JL |
2534 | /* |
2535 | * if the port was already initialised (eg, by a boot loader), | |
2536 | * try to determine the current setup. | |
2537 | */ | |
2538 | static void __init | |
2539 | lpuart_console_get_options(struct lpuart_port *sport, int *baud, | |
2540 | int *parity, int *bits) | |
2541 | { | |
2542 | unsigned char cr, bdh, bdl, brfa; | |
2543 | unsigned int sbr, uartclk, baud_raw; | |
2544 | ||
2545 | cr = readb(sport->port.membase + UARTCR2); | |
2546 | cr &= UARTCR2_TE | UARTCR2_RE; | |
2547 | if (!cr) | |
2548 | return; | |
2549 | ||
2550 | /* ok, the port was enabled */ | |
2551 | ||
2552 | cr = readb(sport->port.membase + UARTCR1); | |
2553 | ||
2554 | *parity = 'n'; | |
2555 | if (cr & UARTCR1_PE) { | |
2556 | if (cr & UARTCR1_PT) | |
2557 | *parity = 'o'; | |
2558 | else | |
2559 | *parity = 'e'; | |
2560 | } | |
2561 | ||
2562 | if (cr & UARTCR1_M) | |
2563 | *bits = 9; | |
2564 | else | |
2565 | *bits = 8; | |
2566 | ||
2567 | bdh = readb(sport->port.membase + UARTBDH); | |
2568 | bdh &= UARTBDH_SBR_MASK; | |
2569 | bdl = readb(sport->port.membase + UARTBDL); | |
2570 | sbr = bdh; | |
2571 | sbr <<= 8; | |
2572 | sbr |= bdl; | |
2573 | brfa = readb(sport->port.membase + UARTCR4); | |
2574 | brfa &= UARTCR4_BRFA_MASK; | |
2575 | ||
35a4ed01 | 2576 | uartclk = lpuart_get_baud_clk_rate(sport); |
c9e2e946 JL |
2577 | /* |
2578 | * baud = mod_clk/(16*(sbr[13]+(brfa)/32) | |
2579 | */ | |
2580 | baud_raw = uartclk / (16 * (sbr + brfa / 32)); | |
2581 | ||
2582 | if (*baud != baud_raw) | |
9edaf50b | 2583 | dev_info(sport->port.dev, "Serial: Console lpuart rounded baud rate" |
c9e2e946 JL |
2584 | "from %d to %d\n", baud_raw, *baud); |
2585 | } | |
2586 | ||
380c966c JL |
2587 | static void __init |
2588 | lpuart32_console_get_options(struct lpuart_port *sport, int *baud, | |
2589 | int *parity, int *bits) | |
2590 | { | |
2591 | unsigned long cr, bd; | |
2592 | unsigned int sbr, uartclk, baud_raw; | |
2593 | ||
a0204f25 | 2594 | cr = lpuart32_read(&sport->port, UARTCTRL); |
380c966c JL |
2595 | cr &= UARTCTRL_TE | UARTCTRL_RE; |
2596 | if (!cr) | |
2597 | return; | |
2598 | ||
2599 | /* ok, the port was enabled */ | |
2600 | ||
a0204f25 | 2601 | cr = lpuart32_read(&sport->port, UARTCTRL); |
380c966c JL |
2602 | |
2603 | *parity = 'n'; | |
2604 | if (cr & UARTCTRL_PE) { | |
2605 | if (cr & UARTCTRL_PT) | |
2606 | *parity = 'o'; | |
2607 | else | |
2608 | *parity = 'e'; | |
2609 | } | |
2610 | ||
2611 | if (cr & UARTCTRL_M) | |
2612 | *bits = 9; | |
2613 | else | |
2614 | *bits = 8; | |
2615 | ||
a0204f25 | 2616 | bd = lpuart32_read(&sport->port, UARTBAUD); |
380c966c | 2617 | bd &= UARTBAUD_SBR_MASK; |
fcb10ee2 SS |
2618 | if (!bd) |
2619 | return; | |
2620 | ||
380c966c | 2621 | sbr = bd; |
35a4ed01 | 2622 | uartclk = lpuart_get_baud_clk_rate(sport); |
380c966c JL |
2623 | /* |
2624 | * baud = mod_clk/(16*(sbr[13]+(brfa)/32) | |
2625 | */ | |
2626 | baud_raw = uartclk / (16 * sbr); | |
2627 | ||
2628 | if (*baud != baud_raw) | |
9edaf50b | 2629 | dev_info(sport->port.dev, "Serial: Console lpuart rounded baud rate" |
380c966c JL |
2630 | "from %d to %d\n", baud_raw, *baud); |
2631 | } | |
2632 | ||
c9e2e946 JL |
2633 | static int __init lpuart_console_setup(struct console *co, char *options) |
2634 | { | |
2635 | struct lpuart_port *sport; | |
2636 | int baud = 115200; | |
2637 | int bits = 8; | |
2638 | int parity = 'n'; | |
2639 | int flow = 'n'; | |
2640 | ||
2641 | /* | |
2642 | * check whether an invalid uart number has been specified, and | |
2643 | * if so, search for the first available port that does have | |
2644 | * console support. | |
2645 | */ | |
2646 | if (co->index == -1 || co->index >= ARRAY_SIZE(lpuart_ports)) | |
2647 | co->index = 0; | |
2648 | ||
2649 | sport = lpuart_ports[co->index]; | |
2650 | if (sport == NULL) | |
2651 | return -ENODEV; | |
2652 | ||
2653 | if (options) | |
2654 | uart_parse_options(options, &baud, &parity, &bits, &flow); | |
2655 | else | |
3ee5447e | 2656 | if (lpuart_is_32(sport)) |
380c966c JL |
2657 | lpuart32_console_get_options(sport, &baud, &parity, &bits); |
2658 | else | |
2659 | lpuart_console_get_options(sport, &baud, &parity, &bits); | |
c9e2e946 | 2660 | |
3ee5447e | 2661 | if (lpuart_is_32(sport)) |
380c966c JL |
2662 | lpuart32_setup_watermark(sport); |
2663 | else | |
2664 | lpuart_setup_watermark(sport); | |
c9e2e946 JL |
2665 | |
2666 | return uart_set_options(&sport->port, co, baud, parity, bits, flow); | |
2667 | } | |
2668 | ||
2669 | static struct uart_driver lpuart_reg; | |
2670 | static struct console lpuart_console = { | |
2671 | .name = DEV_NAME, | |
2672 | .write = lpuart_console_write, | |
2673 | .device = uart_console_device, | |
2674 | .setup = lpuart_console_setup, | |
2675 | .flags = CON_PRINTBUFFER, | |
2676 | .index = -1, | |
2677 | .data = &lpuart_reg, | |
2678 | }; | |
2679 | ||
380c966c JL |
2680 | static struct console lpuart32_console = { |
2681 | .name = DEV_NAME, | |
2682 | .write = lpuart32_console_write, | |
2683 | .device = uart_console_device, | |
2684 | .setup = lpuart_console_setup, | |
2685 | .flags = CON_PRINTBUFFER, | |
2686 | .index = -1, | |
2687 | .data = &lpuart_reg, | |
2688 | }; | |
2689 | ||
1d59b382 SA |
2690 | static void lpuart_early_write(struct console *con, const char *s, unsigned n) |
2691 | { | |
2692 | struct earlycon_device *dev = con->data; | |
2693 | ||
2694 | uart_console_write(&dev->port, s, n, lpuart_console_putchar); | |
2695 | } | |
2696 | ||
2697 | static void lpuart32_early_write(struct console *con, const char *s, unsigned n) | |
2698 | { | |
2699 | struct earlycon_device *dev = con->data; | |
2700 | ||
2701 | uart_console_write(&dev->port, s, n, lpuart32_console_putchar); | |
2702 | } | |
2703 | ||
2704 | static int __init lpuart_early_console_setup(struct earlycon_device *device, | |
2705 | const char *opt) | |
2706 | { | |
2707 | if (!device->port.membase) | |
2708 | return -ENODEV; | |
2709 | ||
2710 | device->con->write = lpuart_early_write; | |
2711 | return 0; | |
2712 | } | |
2713 | ||
2714 | static int __init lpuart32_early_console_setup(struct earlycon_device *device, | |
2715 | const char *opt) | |
2716 | { | |
2717 | if (!device->port.membase) | |
2718 | return -ENODEV; | |
2719 | ||
3966f084 PF |
2720 | if (device->port.iotype != UPIO_MEM32) |
2721 | device->port.iotype = UPIO_MEM32BE; | |
2722 | ||
1d59b382 SA |
2723 | device->con->write = lpuart32_early_write; |
2724 | return 0; | |
2725 | } | |
2726 | ||
e33253f3 MW |
2727 | static int __init ls1028a_early_console_setup(struct earlycon_device *device, |
2728 | const char *opt) | |
2729 | { | |
2730 | u32 cr; | |
2731 | ||
2732 | if (!device->port.membase) | |
2733 | return -ENODEV; | |
2734 | ||
2735 | device->port.iotype = UPIO_MEM32; | |
2736 | device->con->write = lpuart32_early_write; | |
2737 | ||
2738 | /* set the baudrate */ | |
2739 | if (device->port.uartclk && device->baud) | |
2740 | __lpuart32_serial_setbrg(&device->port, device->baud, | |
2741 | false, false); | |
2742 | ||
2743 | /* enable transmitter */ | |
2744 | cr = lpuart32_read(&device->port, UARTCTRL); | |
2745 | cr |= UARTCTRL_TE; | |
2746 | lpuart32_write(&device->port, cr, UARTCTRL); | |
2747 | ||
2748 | return 0; | |
2749 | } | |
2750 | ||
97d6f353 DA |
2751 | static int __init lpuart32_imx_early_console_setup(struct earlycon_device *device, |
2752 | const char *opt) | |
2753 | { | |
2754 | if (!device->port.membase) | |
2755 | return -ENODEV; | |
2756 | ||
2757 | device->port.iotype = UPIO_MEM32; | |
2758 | device->port.membase += IMX_REG_OFF; | |
2759 | device->con->write = lpuart32_early_write; | |
2760 | ||
2761 | return 0; | |
2762 | } | |
1d59b382 SA |
2763 | OF_EARLYCON_DECLARE(lpuart, "fsl,vf610-lpuart", lpuart_early_console_setup); |
2764 | OF_EARLYCON_DECLARE(lpuart32, "fsl,ls1021a-lpuart", lpuart32_early_console_setup); | |
e33253f3 | 2765 | OF_EARLYCON_DECLARE(lpuart32, "fsl,ls1028a-lpuart", ls1028a_early_console_setup); |
97d6f353 | 2766 | OF_EARLYCON_DECLARE(lpuart32, "fsl,imx7ulp-lpuart", lpuart32_imx_early_console_setup); |
e0edfdc1 | 2767 | OF_EARLYCON_DECLARE(lpuart32, "fsl,imx8ulp-lpuart", lpuart32_imx_early_console_setup); |
4e967973 | 2768 | OF_EARLYCON_DECLARE(lpuart32, "fsl,imx8qxp-lpuart", lpuart32_imx_early_console_setup); |
443df57b | 2769 | OF_EARLYCON_DECLARE(lpuart32, "fsl,imxrt1050-lpuart", lpuart32_imx_early_console_setup); |
0e28ed6c MW |
2770 | EARLYCON_DECLARE(lpuart, lpuart_early_console_setup); |
2771 | EARLYCON_DECLARE(lpuart32, lpuart32_early_console_setup); | |
1d59b382 | 2772 | |
c9e2e946 | 2773 | #define LPUART_CONSOLE (&lpuart_console) |
380c966c | 2774 | #define LPUART32_CONSOLE (&lpuart32_console) |
c9e2e946 JL |
2775 | #else |
2776 | #define LPUART_CONSOLE NULL | |
380c966c | 2777 | #define LPUART32_CONSOLE NULL |
c9e2e946 JL |
2778 | #endif |
2779 | ||
2780 | static struct uart_driver lpuart_reg = { | |
2781 | .owner = THIS_MODULE, | |
2782 | .driver_name = DRIVER_NAME, | |
2783 | .dev_name = DEV_NAME, | |
2784 | .nr = ARRAY_SIZE(lpuart_ports), | |
2785 | .cons = LPUART_CONSOLE, | |
2786 | }; | |
2787 | ||
07481f44 IJ |
2788 | static const struct serial_rs485 lpuart_rs485_supported = { |
2789 | .flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND | SER_RS485_RTS_AFTER_SEND, | |
2790 | /* delay_rts_* and RX_DURING_TX are not supported */ | |
2791 | }; | |
2792 | ||
76bad3f8 SS |
2793 | static int lpuart_global_reset(struct lpuart_port *sport) |
2794 | { | |
2795 | struct uart_port *port = &sport->port; | |
2796 | void __iomem *global_addr; | |
2797 | unsigned long ctrl, bd; | |
2798 | unsigned int val = 0; | |
2799 | int ret; | |
2800 | ||
2801 | ret = clk_prepare_enable(sport->ipg_clk); | |
2802 | if (ret) { | |
2803 | dev_err(sport->port.dev, "failed to enable uart ipg clk: %d\n", ret); | |
2804 | return ret; | |
2805 | } | |
2806 | ||
ed35d9dc | 2807 | if (is_imx7ulp_lpuart(sport) || is_imx8ulp_lpuart(sport) || is_imx8qxp_lpuart(sport)) { |
76bad3f8 SS |
2808 | /* |
2809 | * If the transmitter is used by earlycon, wait for transmit engine to | |
2810 | * complete and then reset. | |
2811 | */ | |
2812 | ctrl = lpuart32_read(port, UARTCTRL); | |
2813 | if (ctrl & UARTCTRL_TE) { | |
2814 | bd = lpuart32_read(&sport->port, UARTBAUD); | |
2815 | if (read_poll_timeout(lpuart32_tx_empty, val, val, 1, 100000, false, | |
2816 | port)) { | |
2817 | dev_warn(sport->port.dev, | |
2818 | "timeout waiting for transmit engine to complete\n"); | |
2819 | clk_disable_unprepare(sport->ipg_clk); | |
2820 | return 0; | |
2821 | } | |
2822 | } | |
2823 | ||
2824 | global_addr = port->membase + UART_GLOBAL - IMX_REG_OFF; | |
2825 | writel(UART_GLOBAL_RST, global_addr); | |
2826 | usleep_range(GLOBAL_RST_MIN_US, GLOBAL_RST_MAX_US); | |
2827 | writel(0, global_addr); | |
2828 | usleep_range(GLOBAL_RST_MIN_US, GLOBAL_RST_MAX_US); | |
2829 | ||
2830 | /* Recover the transmitter for earlycon. */ | |
2831 | if (ctrl & UARTCTRL_TE) { | |
2832 | lpuart32_write(port, bd, UARTBAUD); | |
2833 | lpuart32_write(port, ctrl, UARTCTRL); | |
2834 | } | |
2835 | } | |
2836 | ||
2837 | clk_disable_unprepare(sport->ipg_clk); | |
2838 | return 0; | |
2839 | } | |
2840 | ||
c9e2e946 JL |
2841 | static int lpuart_probe(struct platform_device *pdev) |
2842 | { | |
e8372c4f | 2843 | const struct lpuart_soc_data *sdata = of_device_get_match_data(&pdev->dev); |
c9e2e946 JL |
2844 | struct device_node *np = pdev->dev.of_node; |
2845 | struct lpuart_port *sport; | |
2846 | struct resource *res; | |
401fb66a | 2847 | irq_handler_t handler; |
c9e2e946 JL |
2848 | int ret; |
2849 | ||
2850 | sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL); | |
2851 | if (!sport) | |
2852 | return -ENOMEM; | |
2853 | ||
8f3c8d81 | 2854 | sport->port.membase = devm_platform_get_and_ioremap_resource(pdev, 0, &res); |
c9e2e946 JL |
2855 | if (IS_ERR(sport->port.membase)) |
2856 | return PTR_ERR(sport->port.membase); | |
2857 | ||
24b1e5f0 | 2858 | sport->port.membase += sdata->reg_off; |
d5c38948 | 2859 | sport->port.mapbase = res->start + sdata->reg_off; |
c9e2e946 JL |
2860 | sport->port.dev = &pdev->dev; |
2861 | sport->port.type = PORT_LPUART; | |
35a4ed01 | 2862 | sport->devtype = sdata->devtype; |
34ebb26f | 2863 | sport->rx_watermark = sdata->rx_watermark; |
d9219528 SS |
2864 | sport->dma_idle_int = is_imx7ulp_lpuart(sport) || is_imx8ulp_lpuart(sport) || |
2865 | is_imx8qxp_lpuart(sport); | |
394a9e2c | 2866 | ret = platform_get_irq(pdev, 0); |
1df21786 | 2867 | if (ret < 0) |
394a9e2c | 2868 | return ret; |
394a9e2c | 2869 | sport->port.irq = ret; |
0d6fce90 | 2870 | sport->port.iotype = sdata->iotype; |
3ee5447e | 2871 | if (lpuart_is_32(sport)) |
380c966c JL |
2872 | sport->port.ops = &lpuart32_pops; |
2873 | else | |
2874 | sport->port.ops = &lpuart_pops; | |
4d9ec1c0 | 2875 | sport->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_FSL_LPUART_CONSOLE); |
c9e2e946 JL |
2876 | sport->port.flags = UPF_BOOT_AUTOCONF; |
2877 | ||
67b01837 PS |
2878 | if (lpuart_is_32(sport)) |
2879 | sport->port.rs485_config = lpuart32_config_rs485; | |
2880 | else | |
2881 | sport->port.rs485_config = lpuart_config_rs485; | |
0139da50 | 2882 | sport->port.rs485_supported = lpuart_rs485_supported; |
03895cf4 | 2883 | |
35a4ed01 FD |
2884 | sport->ipg_clk = devm_clk_get(&pdev->dev, "ipg"); |
2885 | if (IS_ERR(sport->ipg_clk)) { | |
2886 | ret = PTR_ERR(sport->ipg_clk); | |
2887 | dev_err(&pdev->dev, "failed to get uart ipg clk: %d\n", ret); | |
c9e2e946 JL |
2888 | return ret; |
2889 | } | |
2890 | ||
35a4ed01 FD |
2891 | sport->baud_clk = NULL; |
2892 | if (is_imx8qxp_lpuart(sport)) { | |
2893 | sport->baud_clk = devm_clk_get(&pdev->dev, "baud"); | |
2894 | if (IS_ERR(sport->baud_clk)) { | |
2895 | ret = PTR_ERR(sport->baud_clk); | |
2896 | dev_err(&pdev->dev, "failed to get uart baud clk: %d\n", ret); | |
2897 | return ret; | |
2898 | } | |
c9e2e946 JL |
2899 | } |
2900 | ||
2b2e71fe MW |
2901 | ret = of_alias_get_id(np, "serial"); |
2902 | if (ret < 0) { | |
f398e0aa SS |
2903 | dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret); |
2904 | return ret; | |
2b2e71fe MW |
2905 | } |
2906 | if (ret >= ARRAY_SIZE(lpuart_ports)) { | |
2907 | dev_err(&pdev->dev, "serial%d out of range\n", ret); | |
f398e0aa | 2908 | return -EINVAL; |
2b2e71fe MW |
2909 | } |
2910 | sport->port.line = ret; | |
2911 | ||
35a4ed01 FD |
2912 | ret = lpuart_enable_clks(sport); |
2913 | if (ret) | |
f398e0aa | 2914 | return ret; |
35a4ed01 | 2915 | sport->port.uartclk = lpuart_get_baud_clk_rate(sport); |
c9e2e946 JL |
2916 | |
2917 | lpuart_ports[sport->port.line] = sport; | |
2918 | ||
2919 | platform_set_drvdata(pdev, &sport->port); | |
2920 | ||
9d7ee0e2 | 2921 | if (lpuart_is_32(sport)) { |
380c966c | 2922 | lpuart_reg.cons = LPUART32_CONSOLE; |
401fb66a | 2923 | handler = lpuart32_int; |
9d7ee0e2 | 2924 | } else { |
380c966c | 2925 | lpuart_reg.cons = LPUART_CONSOLE; |
401fb66a | 2926 | handler = lpuart_int; |
9d7ee0e2 | 2927 | } |
c9e2e946 | 2928 | |
43543e6f SS |
2929 | pm_runtime_use_autosuspend(&pdev->dev); |
2930 | pm_runtime_set_autosuspend_delay(&pdev->dev, UART_AUTOSUSPEND_TIMEOUT); | |
2931 | pm_runtime_set_active(&pdev->dev); | |
2932 | pm_runtime_enable(&pdev->dev); | |
2933 | ||
bd5305dc FD |
2934 | ret = lpuart_global_reset(sport); |
2935 | if (ret) | |
2936 | goto failed_reset; | |
2937 | ||
c150c0f3 LW |
2938 | ret = uart_get_rs485_mode(&sport->port); |
2939 | if (ret) | |
2940 | goto failed_get_rs485; | |
dde18d53 | 2941 | |
7c7f9bc9 LW |
2942 | ret = uart_add_one_port(&lpuart_reg, &sport->port); |
2943 | if (ret) | |
2944 | goto failed_attach_port; | |
dde18d53 | 2945 | |
401fb66a IZ |
2946 | ret = devm_request_irq(&pdev->dev, sport->port.irq, handler, 0, |
2947 | DRIVER_NAME, sport); | |
2948 | if (ret) | |
2949 | goto failed_irq_request; | |
2950 | ||
c9e2e946 | 2951 | return 0; |
9d7ee0e2 | 2952 | |
401fb66a | 2953 | failed_irq_request: |
bd5305dc | 2954 | uart_remove_one_port(&lpuart_reg, &sport->port); |
9d7ee0e2 | 2955 | failed_attach_port: |
7c7f9bc9 | 2956 | failed_get_rs485: |
60f36172 | 2957 | failed_reset: |
43543e6f SS |
2958 | pm_runtime_disable(&pdev->dev); |
2959 | pm_runtime_set_suspended(&pdev->dev); | |
2960 | pm_runtime_dont_use_autosuspend(&pdev->dev); | |
35a4ed01 | 2961 | lpuart_disable_clks(sport); |
9d7ee0e2 | 2962 | return ret; |
c9e2e946 JL |
2963 | } |
2964 | ||
6b02503f | 2965 | static void lpuart_remove(struct platform_device *pdev) |
c9e2e946 JL |
2966 | { |
2967 | struct lpuart_port *sport = platform_get_drvdata(pdev); | |
2968 | ||
2969 | uart_remove_one_port(&lpuart_reg, &sport->port); | |
2970 | ||
35a4ed01 | 2971 | lpuart_disable_clks(sport); |
c9e2e946 | 2972 | |
4a818c43 SA |
2973 | if (sport->dma_tx_chan) |
2974 | dma_release_channel(sport->dma_tx_chan); | |
2975 | ||
2976 | if (sport->dma_rx_chan) | |
2977 | dma_release_channel(sport->dma_rx_chan); | |
2978 | ||
43543e6f SS |
2979 | pm_runtime_disable(&pdev->dev); |
2980 | pm_runtime_set_suspended(&pdev->dev); | |
2981 | pm_runtime_dont_use_autosuspend(&pdev->dev); | |
c9e2e946 JL |
2982 | } |
2983 | ||
22cf92bb | 2984 | static int lpuart_runtime_suspend(struct device *dev) |
43543e6f SS |
2985 | { |
2986 | struct platform_device *pdev = to_platform_device(dev); | |
2987 | struct lpuart_port *sport = platform_get_drvdata(pdev); | |
2988 | ||
2989 | lpuart_disable_clks(sport); | |
2990 | ||
2991 | return 0; | |
2992 | }; | |
2993 | ||
22cf92bb | 2994 | static int lpuart_runtime_resume(struct device *dev) |
43543e6f SS |
2995 | { |
2996 | struct platform_device *pdev = to_platform_device(dev); | |
2997 | struct lpuart_port *sport = platform_get_drvdata(pdev); | |
2998 | ||
2999 | return lpuart_enable_clks(sport); | |
3000 | }; | |
3001 | ||
4f5cb8c5 | 3002 | static void serial_lpuart_enable_wakeup(struct lpuart_port *sport, bool on) |
c9e2e946 | 3003 | { |
4f5cb8c5 | 3004 | unsigned int val, baud; |
2fe605df | 3005 | |
3ee5447e | 3006 | if (lpuart_is_32(sport)) { |
4f5cb8c5 SS |
3007 | val = lpuart32_read(&sport->port, UARTCTRL); |
3008 | baud = lpuart32_read(&sport->port, UARTBAUD); | |
3009 | if (on) { | |
3010 | /* set rx_watermark to 0 in wakeup source mode */ | |
3011 | lpuart32_write(&sport->port, 0, UARTWATER); | |
3012 | val |= UARTCTRL_RIE; | |
3013 | /* clear RXEDGIF flag before enable RXEDGIE interrupt */ | |
3014 | lpuart32_write(&sport->port, UARTSTAT_RXEDGIF, UARTSTAT); | |
3015 | baud |= UARTBAUD_RXEDGIE; | |
3016 | } else { | |
3017 | val &= ~UARTCTRL_RIE; | |
3018 | baud &= ~UARTBAUD_RXEDGIE; | |
3019 | } | |
3020 | lpuart32_write(&sport->port, val, UARTCTRL); | |
3021 | lpuart32_write(&sport->port, baud, UARTBAUD); | |
2fe605df | 3022 | } else { |
4f5cb8c5 SS |
3023 | val = readb(sport->port.membase + UARTCR2); |
3024 | if (on) | |
3025 | val |= UARTCR2_RIE; | |
3026 | else | |
3027 | val &= ~UARTCR2_RIE; | |
3028 | writeb(val, sport->port.membase + UARTCR2); | |
2fe605df | 3029 | } |
4f5cb8c5 | 3030 | } |
c9e2e946 | 3031 | |
4f5cb8c5 SS |
3032 | static bool lpuart_uport_is_active(struct lpuart_port *sport) |
3033 | { | |
3034 | struct tty_port *port = &sport->port.state->port; | |
3035 | struct tty_struct *tty; | |
3036 | struct device *tty_dev; | |
3037 | int may_wake = 0; | |
c05efd69 | 3038 | |
4f5cb8c5 SS |
3039 | tty = tty_port_tty_get(port); |
3040 | if (tty) { | |
3041 | tty_dev = tty->dev; | |
178e00f3 | 3042 | may_wake = tty_dev && device_may_wakeup(tty_dev); |
4f5cb8c5 SS |
3043 | tty_kref_put(tty); |
3044 | } | |
3d6bcddf | 3045 | |
4f5cb8c5 SS |
3046 | if ((tty_port_initialized(port) && may_wake) || |
3047 | (!console_suspend_enabled && uart_console(&sport->port))) | |
3048 | return true; | |
3049 | ||
3050 | return false; | |
3051 | } | |
3052 | ||
22cf92bb | 3053 | static int lpuart_suspend_noirq(struct device *dev) |
4f5cb8c5 SS |
3054 | { |
3055 | struct lpuart_port *sport = dev_get_drvdata(dev); | |
3056 | bool irq_wake = irqd_is_wakeup_set(irq_get_irq_data(sport->port.irq)); | |
3057 | ||
3058 | if (lpuart_uport_is_active(sport)) | |
3059 | serial_lpuart_enable_wakeup(sport, !!irq_wake); | |
3060 | ||
3061 | pinctrl_pm_select_sleep_state(dev); | |
3062 | ||
3063 | return 0; | |
3064 | } | |
3065 | ||
22cf92bb | 3066 | static int lpuart_resume_noirq(struct device *dev) |
4f5cb8c5 SS |
3067 | { |
3068 | struct lpuart_port *sport = dev_get_drvdata(dev); | |
3069 | unsigned int val; | |
3070 | ||
3071 | pinctrl_pm_select_default_state(dev); | |
3072 | ||
3073 | if (lpuart_uport_is_active(sport)) { | |
3074 | serial_lpuart_enable_wakeup(sport, false); | |
c05efd69 | 3075 | |
4f5cb8c5 | 3076 | /* clear the wakeup flags */ |
42b68768 | 3077 | if (lpuart_is_32(sport)) { |
4f5cb8c5 SS |
3078 | val = lpuart32_read(&sport->port, UARTSTAT); |
3079 | lpuart32_write(&sport->port, val, UARTSTAT); | |
42b68768 | 3080 | } |
c05efd69 BD |
3081 | } |
3082 | ||
c9e2e946 JL |
3083 | return 0; |
3084 | } | |
3085 | ||
22cf92bb | 3086 | static int lpuart_suspend(struct device *dev) |
c9e2e946 JL |
3087 | { |
3088 | struct lpuart_port *sport = dev_get_drvdata(dev); | |
4f5cb8c5 | 3089 | unsigned long temp, flags; |
08de1014 | 3090 | |
4f5cb8c5 | 3091 | uart_suspend_port(&lpuart_reg, &sport->port); |
d6b0d2f2 | 3092 | |
4f5cb8c5 | 3093 | if (lpuart_uport_is_active(sport)) { |
92f4e05b | 3094 | uart_port_lock_irqsave(&sport->port, &flags); |
4f5cb8c5 SS |
3095 | if (lpuart_is_32(sport)) { |
3096 | /* disable Rx/Tx and interrupts */ | |
3097 | temp = lpuart32_read(&sport->port, UARTCTRL); | |
3098 | temp &= ~(UARTCTRL_TE | UARTCTRL_TIE | UARTCTRL_TCIE); | |
3099 | lpuart32_write(&sport->port, temp, UARTCTRL); | |
3100 | } else { | |
3101 | /* disable Rx/Tx and interrupts */ | |
3102 | temp = readb(sport->port.membase + UARTCR2); | |
3103 | temp &= ~(UARTCR2_TE | UARTCR2_TIE | UARTCR2_TCIE); | |
3104 | writeb(temp, sport->port.membase + UARTCR2); | |
3105 | } | |
92f4e05b | 3106 | uart_port_unlock_irqrestore(&sport->port, flags); |
c9e2e946 | 3107 | |
4f5cb8c5 SS |
3108 | if (sport->lpuart_dma_rx_use) { |
3109 | /* | |
3110 | * EDMA driver during suspend will forcefully release any | |
3111 | * non-idle DMA channels. If port wakeup is enabled or if port | |
3112 | * is console port or 'no_console_suspend' is set the Rx DMA | |
3113 | * cannot resume as expected, hence gracefully release the | |
3114 | * Rx DMA path before suspend and start Rx DMA path on resume. | |
3115 | */ | |
4f5cb8c5 SS |
3116 | lpuart_dma_rx_free(&sport->port); |
3117 | ||
3118 | /* Disable Rx DMA to use UART port as wakeup source */ | |
92f4e05b | 3119 | uart_port_lock_irqsave(&sport->port, &flags); |
4f5cb8c5 SS |
3120 | if (lpuart_is_32(sport)) { |
3121 | temp = lpuart32_read(&sport->port, UARTBAUD); | |
3122 | lpuart32_write(&sport->port, temp & ~UARTBAUD_RDMAE, | |
3123 | UARTBAUD); | |
3124 | } else { | |
3125 | writeb(readb(sport->port.membase + UARTCR5) & | |
3126 | ~UARTCR5_RDMAS, sport->port.membase + UARTCR5); | |
3127 | } | |
92f4e05b | 3128 | uart_port_unlock_irqrestore(&sport->port, flags); |
4f5cb8c5 SS |
3129 | } |
3130 | ||
3131 | if (sport->lpuart_dma_tx_use) { | |
92f4e05b | 3132 | uart_port_lock_irqsave(&sport->port, &flags); |
4f5cb8c5 SS |
3133 | if (lpuart_is_32(sport)) { |
3134 | temp = lpuart32_read(&sport->port, UARTBAUD); | |
3135 | temp &= ~UARTBAUD_TDMAE; | |
3136 | lpuart32_write(&sport->port, temp, UARTBAUD); | |
3137 | } else { | |
3138 | temp = readb(sport->port.membase + UARTCR5); | |
3139 | temp &= ~UARTCR5_TDMAS; | |
3140 | writeb(temp, sport->port.membase + UARTCR5); | |
3141 | } | |
92f4e05b | 3142 | uart_port_unlock_irqrestore(&sport->port, flags); |
4f5cb8c5 | 3143 | sport->dma_tx_in_progress = false; |
8682ab0e | 3144 | dmaengine_terminate_sync(sport->dma_tx_chan); |
c05efd69 | 3145 | } |
43543e6f SS |
3146 | } else if (pm_runtime_active(sport->port.dev)) { |
3147 | lpuart_disable_clks(sport); | |
3148 | pm_runtime_disable(sport->port.dev); | |
3149 | pm_runtime_set_suspended(sport->port.dev); | |
c05efd69 BD |
3150 | } |
3151 | ||
4f5cb8c5 SS |
3152 | return 0; |
3153 | } | |
c05efd69 | 3154 | |
4f5cb8c5 SS |
3155 | static void lpuart_console_fixup(struct lpuart_port *sport) |
3156 | { | |
3157 | struct tty_port *port = &sport->port.state->port; | |
3158 | struct uart_port *uport = &sport->port; | |
3159 | struct ktermios termios; | |
3160 | ||
3161 | /* i.MX7ULP enter VLLS mode that lpuart module power off and registers | |
3162 | * all lost no matter the port is wakeup source. | |
3163 | * For console port, console baud rate setting lost and print messy | |
3164 | * log when enable the console port as wakeup source. To avoid the | |
3165 | * issue happen, user should not enable uart port as wakeup source | |
3166 | * in VLLS mode, or restore console setting here. | |
3167 | */ | |
3168 | if (is_imx7ulp_lpuart(sport) && lpuart_uport_is_active(sport) && | |
3169 | console_suspend_enabled && uart_console(&sport->port)) { | |
3170 | ||
3171 | mutex_lock(&port->mutex); | |
3172 | memset(&termios, 0, sizeof(struct ktermios)); | |
3173 | termios.c_cflag = uport->cons->cflag; | |
3174 | if (port->tty && termios.c_cflag == 0) | |
3175 | termios = port->tty->termios; | |
3176 | uport->ops->set_termios(uport, &termios, NULL); | |
3177 | mutex_unlock(&port->mutex); | |
3178 | } | |
3179 | } | |
3180 | ||
22cf92bb | 3181 | static int lpuart_resume(struct device *dev) |
4f5cb8c5 SS |
3182 | { |
3183 | struct lpuart_port *sport = dev_get_drvdata(dev); | |
43543e6f | 3184 | int ret; |
4f5cb8c5 SS |
3185 | |
3186 | if (lpuart_uport_is_active(sport)) { | |
3187 | if (lpuart_is_32(sport)) | |
3188 | lpuart32_hw_setup(sport); | |
3189 | else | |
3190 | lpuart_hw_setup(sport); | |
43543e6f SS |
3191 | } else if (pm_runtime_active(sport->port.dev)) { |
3192 | ret = lpuart_enable_clks(sport); | |
3193 | if (ret) | |
3194 | return ret; | |
3195 | pm_runtime_set_active(sport->port.dev); | |
3196 | pm_runtime_enable(sport->port.dev); | |
4f5cb8c5 | 3197 | } |
42b68768 | 3198 | |
4f5cb8c5 | 3199 | lpuart_console_fixup(sport); |
c9e2e946 JL |
3200 | uart_resume_port(&lpuart_reg, &sport->port); |
3201 | ||
3202 | return 0; | |
3203 | } | |
c9e2e946 | 3204 | |
4f5cb8c5 | 3205 | static const struct dev_pm_ops lpuart_pm_ops = { |
22cf92bb | 3206 | RUNTIME_PM_OPS(lpuart_runtime_suspend, |
43543e6f | 3207 | lpuart_runtime_resume, NULL) |
22cf92bb | 3208 | NOIRQ_SYSTEM_SLEEP_PM_OPS(lpuart_suspend_noirq, |
4f5cb8c5 | 3209 | lpuart_resume_noirq) |
22cf92bb | 3210 | SYSTEM_SLEEP_PM_OPS(lpuart_suspend, lpuart_resume) |
4f5cb8c5 | 3211 | }; |
c9e2e946 JL |
3212 | |
3213 | static struct platform_driver lpuart_driver = { | |
3214 | .probe = lpuart_probe, | |
6b02503f | 3215 | .remove_new = lpuart_remove, |
c9e2e946 JL |
3216 | .driver = { |
3217 | .name = "fsl-lpuart", | |
c9e2e946 | 3218 | .of_match_table = lpuart_dt_ids, |
22cf92bb | 3219 | .pm = pm_ptr(&lpuart_pm_ops), |
c9e2e946 JL |
3220 | }, |
3221 | }; | |
3222 | ||
3223 | static int __init lpuart_serial_init(void) | |
3224 | { | |
144c29ed | 3225 | int ret = uart_register_driver(&lpuart_reg); |
c9e2e946 | 3226 | |
c9e2e946 JL |
3227 | if (ret) |
3228 | return ret; | |
3229 | ||
3230 | ret = platform_driver_register(&lpuart_driver); | |
3231 | if (ret) | |
3232 | uart_unregister_driver(&lpuart_reg); | |
3233 | ||
39c34b09 | 3234 | return ret; |
c9e2e946 JL |
3235 | } |
3236 | ||
3237 | static void __exit lpuart_serial_exit(void) | |
3238 | { | |
3239 | platform_driver_unregister(&lpuart_driver); | |
3240 | uart_unregister_driver(&lpuart_reg); | |
3241 | } | |
3242 | ||
3243 | module_init(lpuart_serial_init); | |
3244 | module_exit(lpuart_serial_exit); | |
3245 | ||
3246 | MODULE_DESCRIPTION("Freescale lpuart serial port driver"); | |
3247 | MODULE_LICENSE("GPL v2"); |