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serial: bcm63xx: fix timing issue.
[linux-2.6-block.git] / drivers / tty / serial / fsl_lpuart.c
CommitLineData
c9e2e946
JL		 1/*
2 * Freescale lpuart serial port driver
3 *
380c966c 4 * Copyright 2012-2014 Freescale Semiconductor, Inc.
c9e2e946
JL		 5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 */
11
12#if defined(CONFIG_SERIAL_FSL_LPUART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
13#define SUPPORT_SYSRQ
14#endif
15
f1cd8c87
YY		 16#include <linux/clk.h>
17#include <linux/console.h>
18#include <linux/dma-mapping.h>
19#include <linux/dmaengine.h>
20#include <linux/dmapool.h>
c9e2e946
JL		 21#include <linux/io.h>
22#include <linux/irq.h>
f1cd8c87 23#include <linux/module.h>
c9e2e946
JL		 24#include <linux/of.h>
25#include <linux/of_device.h>
f1cd8c87 26#include <linux/of_dma.h>
c9e2e946 27#include <linux/serial_core.h>
f1cd8c87 28#include <linux/slab.h>
c9e2e946
JL		 29#include <linux/tty_flip.h>
30
31/* All registers are 8-bit width */
32#define UARTBDH 0x00
33#define UARTBDL 0x01
34#define UARTCR1 0x02
35#define UARTCR2 0x03
36#define UARTSR1 0x04
37#define UARTCR3 0x06
38#define UARTDR 0x07
39#define UARTCR4 0x0a
40#define UARTCR5 0x0b
41#define UARTMODEM 0x0d
42#define UARTPFIFO 0x10
43#define UARTCFIFO 0x11
44#define UARTSFIFO 0x12
45#define UARTTWFIFO 0x13
46#define UARTTCFIFO 0x14
47#define UARTRWFIFO 0x15
48
49#define UARTBDH_LBKDIE 0x80
50#define UARTBDH_RXEDGIE 0x40
51#define UARTBDH_SBR_MASK 0x1f
52
53#define UARTCR1_LOOPS 0x80
54#define UARTCR1_RSRC 0x20
55#define UARTCR1_M 0x10
56#define UARTCR1_WAKE 0x08
57#define UARTCR1_ILT 0x04
58#define UARTCR1_PE 0x02
59#define UARTCR1_PT 0x01
60
61#define UARTCR2_TIE 0x80
62#define UARTCR2_TCIE 0x40
63#define UARTCR2_RIE 0x20
64#define UARTCR2_ILIE 0x10
65#define UARTCR2_TE 0x08
66#define UARTCR2_RE 0x04
67#define UARTCR2_RWU 0x02
68#define UARTCR2_SBK 0x01
69
70#define UARTSR1_TDRE 0x80
71#define UARTSR1_TC 0x40
72#define UARTSR1_RDRF 0x20
73#define UARTSR1_IDLE 0x10
74#define UARTSR1_OR 0x08
75#define UARTSR1_NF 0x04
76#define UARTSR1_FE 0x02
77#define UARTSR1_PE 0x01
78
79#define UARTCR3_R8 0x80
80#define UARTCR3_T8 0x40
81#define UARTCR3_TXDIR 0x20
82#define UARTCR3_TXINV 0x10
83#define UARTCR3_ORIE 0x08
84#define UARTCR3_NEIE 0x04
85#define UARTCR3_FEIE 0x02
86#define UARTCR3_PEIE 0x01
87
88#define UARTCR4_MAEN1 0x80
89#define UARTCR4_MAEN2 0x40
90#define UARTCR4_M10 0x20
91#define UARTCR4_BRFA_MASK 0x1f
92#define UARTCR4_BRFA_OFF 0
93
94#define UARTCR5_TDMAS 0x80
95#define UARTCR5_RDMAS 0x20
96
97#define UARTMODEM_RXRTSE 0x08
98#define UARTMODEM_TXRTSPOL 0x04
99#define UARTMODEM_TXRTSE 0x02
100#define UARTMODEM_TXCTSE 0x01
101
102#define UARTPFIFO_TXFE 0x80
103#define UARTPFIFO_FIFOSIZE_MASK 0x7
104#define UARTPFIFO_TXSIZE_OFF 4
105#define UARTPFIFO_RXFE 0x08
106#define UARTPFIFO_RXSIZE_OFF 0
107
108#define UARTCFIFO_TXFLUSH 0x80
109#define UARTCFIFO_RXFLUSH 0x40
110#define UARTCFIFO_RXOFE 0x04
111#define UARTCFIFO_TXOFE 0x02
112#define UARTCFIFO_RXUFE 0x01
113
114#define UARTSFIFO_TXEMPT 0x80
115#define UARTSFIFO_RXEMPT 0x40
116#define UARTSFIFO_RXOF 0x04
117#define UARTSFIFO_TXOF 0x02
118#define UARTSFIFO_RXUF 0x01
119
a5fa2660 120/* 32-bit register definition */
380c966c
JL		 121#define UARTBAUD 0x00
122#define UARTSTAT 0x04
123#define UARTCTRL 0x08
124#define UARTDATA 0x0C
125#define UARTMATCH 0x10
126#define UARTMODIR 0x14
127#define UARTFIFO 0x18
128#define UARTWATER 0x1c
129
130#define UARTBAUD_MAEN1 0x80000000
131#define UARTBAUD_MAEN2 0x40000000
132#define UARTBAUD_M10 0x20000000
133#define UARTBAUD_TDMAE 0x00800000
134#define UARTBAUD_RDMAE 0x00200000
135#define UARTBAUD_MATCFG 0x00400000
136#define UARTBAUD_BOTHEDGE 0x00020000
137#define UARTBAUD_RESYNCDIS 0x00010000
138#define UARTBAUD_LBKDIE 0x00008000
139#define UARTBAUD_RXEDGIE 0x00004000
140#define UARTBAUD_SBNS 0x00002000
141#define UARTBAUD_SBR 0x00000000
142#define UARTBAUD_SBR_MASK 0x1fff
a6d7514b
DA		 143#define UARTBAUD_OSR_MASK 0x1f
144#define UARTBAUD_OSR_SHIFT 24
380c966c
JL		 145
146#define UARTSTAT_LBKDIF 0x80000000
147#define UARTSTAT_RXEDGIF 0x40000000
148#define UARTSTAT_MSBF 0x20000000
149#define UARTSTAT_RXINV 0x10000000
150#define UARTSTAT_RWUID 0x08000000
151#define UARTSTAT_BRK13 0x04000000
152#define UARTSTAT_LBKDE 0x02000000
153#define UARTSTAT_RAF 0x01000000
154#define UARTSTAT_TDRE 0x00800000
155#define UARTSTAT_TC 0x00400000
156#define UARTSTAT_RDRF 0x00200000
157#define UARTSTAT_IDLE 0x00100000
158#define UARTSTAT_OR 0x00080000
159#define UARTSTAT_NF 0x00040000
160#define UARTSTAT_FE 0x00020000
161#define UARTSTAT_PE 0x00010000
162#define UARTSTAT_MA1F 0x00008000
163#define UARTSTAT_M21F 0x00004000
164
165#define UARTCTRL_R8T9 0x80000000
166#define UARTCTRL_R9T8 0x40000000
167#define UARTCTRL_TXDIR 0x20000000
168#define UARTCTRL_TXINV 0x10000000
169#define UARTCTRL_ORIE 0x08000000
170#define UARTCTRL_NEIE 0x04000000
171#define UARTCTRL_FEIE 0x02000000
172#define UARTCTRL_PEIE 0x01000000
173#define UARTCTRL_TIE 0x00800000
174#define UARTCTRL_TCIE 0x00400000
175#define UARTCTRL_RIE 0x00200000
176#define UARTCTRL_ILIE 0x00100000
177#define UARTCTRL_TE 0x00080000
178#define UARTCTRL_RE 0x00040000
179#define UARTCTRL_RWU 0x00020000
180#define UARTCTRL_SBK 0x00010000
181#define UARTCTRL_MA1IE 0x00008000
182#define UARTCTRL_MA2IE 0x00004000
183#define UARTCTRL_IDLECFG 0x00000100
184#define UARTCTRL_LOOPS 0x00000080
185#define UARTCTRL_DOZEEN 0x00000040
186#define UARTCTRL_RSRC 0x00000020
187#define UARTCTRL_M 0x00000010
188#define UARTCTRL_WAKE 0x00000008
189#define UARTCTRL_ILT 0x00000004
190#define UARTCTRL_PE 0x00000002
191#define UARTCTRL_PT 0x00000001
192
193#define UARTDATA_NOISY 0x00008000
194#define UARTDATA_PARITYE 0x00004000
195#define UARTDATA_FRETSC 0x00002000
196#define UARTDATA_RXEMPT 0x00001000
197#define UARTDATA_IDLINE 0x00000800
198#define UARTDATA_MASK 0x3ff
199
200#define UARTMODIR_IREN 0x00020000
201#define UARTMODIR_TXCTSSRC 0x00000020
202#define UARTMODIR_TXCTSC 0x00000010
203#define UARTMODIR_RXRTSE 0x00000008
204#define UARTMODIR_TXRTSPOL 0x00000004
205#define UARTMODIR_TXRTSE 0x00000002
206#define UARTMODIR_TXCTSE 0x00000001
207
208#define UARTFIFO_TXEMPT 0x00800000
209#define UARTFIFO_RXEMPT 0x00400000
210#define UARTFIFO_TXOF 0x00020000
211#define UARTFIFO_RXUF 0x00010000
212#define UARTFIFO_TXFLUSH 0x00008000
213#define UARTFIFO_RXFLUSH 0x00004000
214#define UARTFIFO_TXOFE 0x00000200
215#define UARTFIFO_RXUFE 0x00000100
216#define UARTFIFO_TXFE 0x00000080
217#define UARTFIFO_FIFOSIZE_MASK 0x7
218#define UARTFIFO_TXSIZE_OFF 4
219#define UARTFIFO_RXFE 0x00000008
220#define UARTFIFO_RXSIZE_OFF 0
221
222#define UARTWATER_COUNT_MASK 0xff
223#define UARTWATER_TXCNT_OFF 8
224#define UARTWATER_RXCNT_OFF 24
225#define UARTWATER_WATER_MASK 0xff
226#define UARTWATER_TXWATER_OFF 0
227#define UARTWATER_RXWATER_OFF 16
228
5887ad43
BD		 229/* Rx DMA timeout in ms, which is used to calculate Rx ring buffer size */
230#define DMA_RX_TIMEOUT (10)
f1cd8c87 231
c9e2e946
JL		 232#define DRIVER_NAME "fsl-lpuart"
233#define DEV_NAME "ttyLP"
234#define UART_NR 6
235
24b1e5f0
DA		 236/* IMX lpuart has four extra unused regs located at the beginning */
237#define IMX_REG_OFF 0x10
238
c9e2e946
JL		 239struct lpuart_port {
240 struct uart_port port;
241 struct clk *clk;
242 unsigned int txfifo_size;
243 unsigned int rxfifo_size;
f1cd8c87 244
4a818c43
SA		 245 bool lpuart_dma_tx_use;
246 bool lpuart_dma_rx_use;
f1cd8c87
YY		 247 struct dma_chan *dma_tx_chan;
248 struct dma_chan *dma_rx_chan;
249 struct dma_async_tx_descriptor *dma_tx_desc;
250 struct dma_async_tx_descriptor *dma_rx_desc;
f1cd8c87
YY		 251 dma_cookie_t dma_tx_cookie;
252 dma_cookie_t dma_rx_cookie;
f1cd8c87
YY		 253 unsigned int dma_tx_bytes;
254 unsigned int dma_rx_bytes;
6250cc30 255 bool dma_tx_in_progress;
f1cd8c87
YY		 256 unsigned int dma_rx_timeout;
257 struct timer_list lpuart_timer;
6250cc30 258 struct scatterlist rx_sgl, tx_sgl[2];
5887ad43
BD		 259 struct circ_buf rx_ring;
260 int rx_dma_rng_buf_len;
6250cc30
BD		 261 unsigned int dma_tx_nents;
262 wait_queue_head_t dma_wait;
c9e2e946
JL		 263};
264
0d6fce90
DA		 265struct lpuart_soc_data {
266 char iotype;
24b1e5f0 267 u8 reg_off;
0d6fce90
DA		 268};
269
270static const struct lpuart_soc_data vf_data = {
271 .iotype = UPIO_MEM,
272};
273
274static const struct lpuart_soc_data ls_data = {
275 .iotype = UPIO_MEM32BE,
276};
277
24b1e5f0
DA		 278static struct lpuart_soc_data imx_data = {
279 .iotype = UPIO_MEM32,
280 .reg_off = IMX_REG_OFF,
281};
282
ed0bb232 283static const struct of_device_id lpuart_dt_ids[] = {
0d6fce90
DA		 284 { .compatible = "fsl,vf610-lpuart", .data = &vf_data, },
285 { .compatible = "fsl,ls1021a-lpuart", .data = &ls_data, },
24b1e5f0 286 { .compatible = "fsl,imx7ulp-lpuart", .data = &imx_data, },
c9e2e946
JL		 287 { /* sentinel */ }
288};
289MODULE_DEVICE_TABLE(of, lpuart_dt_ids);
290
f1cd8c87
YY		 291/* Forward declare this for the dma callbacks*/
292static void lpuart_dma_tx_complete(void *arg);
f1cd8c87 293
f98e1fcd
DA		 294static inline u32 lpuart32_read(struct uart_port *port, u32 off)
295{
296 switch (port->iotype) {
297 case UPIO_MEM32:
298 return readl(port->membase + off);
299 case UPIO_MEM32BE:
300 return ioread32be(port->membase + off);
301 default:
302 return 0;
303 }
380c966c
JL		 304}
305
a0204f25 306static inline void lpuart32_write(struct uart_port *port, u32 val,
f98e1fcd
DA		 307 u32 off)
308{
309 switch (port->iotype) {
310 case UPIO_MEM32:
311 writel(val, port->membase + off);
312 break;
313 case UPIO_MEM32BE:
314 iowrite32be(val, port->membase + off);
315 break;
316 }
380c966c
JL		 317}
318
c9e2e946
JL		 319static void lpuart_stop_tx(struct uart_port *port)
320{
321 unsigned char temp;
322
323 temp = readb(port->membase + UARTCR2);
324 temp &= ~(UARTCR2_TIE | UARTCR2_TCIE);
325 writeb(temp, port->membase + UARTCR2);
326}
327
380c966c
JL		 328static void lpuart32_stop_tx(struct uart_port *port)
329{
330 unsigned long temp;
331
a0204f25 332 temp = lpuart32_read(port, UARTCTRL);
380c966c 333 temp &= ~(UARTCTRL_TIE | UARTCTRL_TCIE);
a0204f25 334 lpuart32_write(port, temp, UARTCTRL);
380c966c
JL		 335}
336
c9e2e946
JL		 337static void lpuart_stop_rx(struct uart_port *port)
338{
339 unsigned char temp;
340
341 temp = readb(port->membase + UARTCR2);
342 writeb(temp & ~UARTCR2_RE, port->membase + UARTCR2);
343}
344
380c966c
JL		 345static void lpuart32_stop_rx(struct uart_port *port)
346{
347 unsigned long temp;
348
a0204f25
DA		 349 temp = lpuart32_read(port, UARTCTRL);
350 lpuart32_write(port, temp & ~UARTCTRL_RE, UARTCTRL);
380c966c
JL		 351}
352
6250cc30 353static void lpuart_dma_tx(struct lpuart_port *sport)
f1cd8c87
YY		 354{
355 struct circ_buf *xmit = &sport->port.state->xmit;
6250cc30
BD		 356 struct scatterlist *sgl = sport->tx_sgl;
357 struct device *dev = sport->port.dev;
358 int ret;
f1cd8c87 359
6250cc30
BD		 360 if (sport->dma_tx_in_progress)
361 return;
f1cd8c87 362
6250cc30 363 sport->dma_tx_bytes = uart_circ_chars_pending(xmit);
f1cd8c87 364
d704b2d3 365 if (xmit->tail < xmit->head || xmit->head == 0) {
6250cc30
BD		 366 sport->dma_tx_nents = 1;
367 sg_init_one(sgl, xmit->buf + xmit->tail, sport->dma_tx_bytes);
368 } else {
369 sport->dma_tx_nents = 2;
370 sg_init_table(sgl, 2);
371 sg_set_buf(sgl, xmit->buf + xmit->tail,
372 UART_XMIT_SIZE - xmit->tail);
373 sg_set_buf(sgl + 1, xmit->buf, xmit->head);
374 }
f1cd8c87 375
6250cc30
BD		 376 ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
377 if (!ret) {
378 dev_err(dev, "DMA mapping error for TX.\n");
379 return;
380 }
f1cd8c87 381
6250cc30
BD		 382 sport->dma_tx_desc = dmaengine_prep_slave_sg(sport->dma_tx_chan, sgl,
383 sport->dma_tx_nents,
f1cd8c87 384 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
f1cd8c87 385 if (!sport->dma_tx_desc) {
6250cc30
BD		 386 dma_unmap_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
387 dev_err(dev, "Cannot prepare TX slave DMA!\n");
388 return;
f1cd8c87
YY		 389 }
390
391 sport->dma_tx_desc->callback = lpuart_dma_tx_complete;
392 sport->dma_tx_desc->callback_param = sport;
6250cc30 393 sport->dma_tx_in_progress = true;
f1cd8c87
YY		 394 sport->dma_tx_cookie = dmaengine_submit(sport->dma_tx_desc);
395 dma_async_issue_pending(sport->dma_tx_chan);
f1cd8c87
YY		 396}
397
398static void lpuart_dma_tx_complete(void *arg)
399{
400 struct lpuart_port *sport = arg;
6250cc30 401 struct scatterlist *sgl = &sport->tx_sgl[0];
f1cd8c87
YY		 402 struct circ_buf *xmit = &sport->port.state->xmit;
403 unsigned long flags;
404
f1cd8c87
YY		 405 spin_lock_irqsave(&sport->port.lock, flags);
406
6250cc30
BD		 407 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
408
f1cd8c87 409 xmit->tail = (xmit->tail + sport->dma_tx_bytes) & (UART_XMIT_SIZE - 1);
6250cc30
BD		 410
411 sport->port.icount.tx += sport->dma_tx_bytes;
412 sport->dma_tx_in_progress = false;
413 spin_unlock_irqrestore(&sport->port.lock, flags);
f1cd8c87
YY		 414
415 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
416 uart_write_wakeup(&sport->port);
417
6250cc30
BD		 418 if (waitqueue_active(&sport->dma_wait)) {
419 wake_up(&sport->dma_wait);
420 return;
421 }
422
423 spin_lock_irqsave(&sport->port.lock, flags);
424
425 if (!uart_circ_empty(xmit) && !uart_tx_stopped(&sport->port))
426 lpuart_dma_tx(sport);
f1cd8c87
YY		 427
428 spin_unlock_irqrestore(&sport->port.lock, flags);
429}
430
6250cc30
BD		 431static int lpuart_dma_tx_request(struct uart_port *port)
432{
433 struct lpuart_port *sport = container_of(port,
434 struct lpuart_port, port);
435 struct dma_slave_config dma_tx_sconfig = {};
436 int ret;
437
438 dma_tx_sconfig.dst_addr = sport->port.mapbase + UARTDR;
439 dma_tx_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
440 dma_tx_sconfig.dst_maxburst = 1;
441 dma_tx_sconfig.direction = DMA_MEM_TO_DEV;
442 ret = dmaengine_slave_config(sport->dma_tx_chan, &dma_tx_sconfig);
443
444 if (ret) {
445 dev_err(sport->port.dev,
446 "DMA slave config failed, err = %d\n", ret);
447 return ret;
448 }
449
450 return 0;
451}
452
bfc2e07f
SA		 453static void lpuart_flush_buffer(struct uart_port *port)
454{
455 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
6250cc30 456
bfc2e07f 457 if (sport->lpuart_dma_tx_use) {
6250cc30
BD		 458 if (sport->dma_tx_in_progress) {
459 dma_unmap_sg(sport->port.dev, &sport->tx_sgl[0],
460 sport->dma_tx_nents, DMA_TO_DEVICE);
461 sport->dma_tx_in_progress = false;
462 }
bfc2e07f 463 dmaengine_terminate_all(sport->dma_tx_chan);
bfc2e07f
SA		 464 }
465}
466
2a41bc2a
NR		 467#if defined(CONFIG_CONSOLE_POLL)
468
469static int lpuart_poll_init(struct uart_port *port)
470{
471 struct lpuart_port *sport = container_of(port,
472 struct lpuart_port, port);
473 unsigned long flags;
474 unsigned char temp;
475
476 sport->port.fifosize = 0;
477
478 spin_lock_irqsave(&sport->port.lock, flags);
479 /* Disable Rx & Tx */
480 writeb(0, sport->port.membase + UARTCR2);
481
482 temp = readb(sport->port.membase + UARTPFIFO);
483 /* Enable Rx and Tx FIFO */
484 writeb(temp | UARTPFIFO_RXFE | UARTPFIFO_TXFE,
485 sport->port.membase + UARTPFIFO);
486
487 /* flush Tx and Rx FIFO */
488 writeb(UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH,
489 sport->port.membase + UARTCFIFO);
490
491 /* explicitly clear RDRF */
492 if (readb(sport->port.membase + UARTSR1) & UARTSR1_RDRF) {
493 readb(sport->port.membase + UARTDR);
494 writeb(UARTSFIFO_RXUF, sport->port.membase + UARTSFIFO);
495 }
496
497 writeb(0, sport->port.membase + UARTTWFIFO);
498 writeb(1, sport->port.membase + UARTRWFIFO);
499
500 /* Enable Rx and Tx */
501 writeb(UARTCR2_RE | UARTCR2_TE, sport->port.membase + UARTCR2);
502 spin_unlock_irqrestore(&sport->port.lock, flags);
503
504 return 0;
505}
506
507static void lpuart_poll_put_char(struct uart_port *port, unsigned char c)
508{
2a41bc2a
NR		 509 /* drain */
510 while (!(readb(port->membase + UARTSR1) & UARTSR1_TDRE))
511 barrier();
512
513 writeb(c, port->membase + UARTDR);
514}
515
516static int lpuart_poll_get_char(struct uart_port *port)
517{
518 if (!(readb(port->membase + UARTSR1) & UARTSR1_RDRF))
519 return NO_POLL_CHAR;
520
521 return readb(port->membase + UARTDR);
522}
523
a5fa2660
MV		 524static int lpuart32_poll_init(struct uart_port *port)
525{
526 unsigned long flags;
527 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
528 u32 temp;
529
530 sport->port.fifosize = 0;
531
532 spin_lock_irqsave(&sport->port.lock, flags);
533
534 /* Disable Rx & Tx */
535 writel(0, sport->port.membase + UARTCTRL);
536
537 temp = readl(sport->port.membase + UARTFIFO);
538
539 /* Enable Rx and Tx FIFO */
540 writel(temp | UARTFIFO_RXFE | UARTFIFO_TXFE,
541 sport->port.membase + UARTFIFO);
542
543 /* flush Tx and Rx FIFO */
544 writel(UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH,
545 sport->port.membase + UARTFIFO);
546
547 /* explicitly clear RDRF */
548 if (readl(sport->port.membase + UARTSTAT) & UARTSTAT_RDRF) {
549 readl(sport->port.membase + UARTDATA);
550 writel(UARTFIFO_RXUF, sport->port.membase + UARTFIFO);
551 }
552
553 /* Enable Rx and Tx */
554 writel(UARTCTRL_RE | UARTCTRL_TE, sport->port.membase + UARTCTRL);
555 spin_unlock_irqrestore(&sport->port.lock, flags);
556
557 return 0;
558}
559
560static void lpuart32_poll_put_char(struct uart_port *port, unsigned char c)
561{
562 while (!(readl(port->membase + UARTSTAT) & UARTSTAT_TDRE))
563 barrier();
564
565 writel(c, port->membase + UARTDATA);
566}
567
568static int lpuart32_poll_get_char(struct uart_port *port)
569{
570 if (!(readl(port->membase + UARTSTAT) & UARTSTAT_RDRF))
571 return NO_POLL_CHAR;
572
573 return readl(port->membase + UARTDATA);
574}
2a41bc2a
NR		 575#endif
576
c9e2e946
JL		 577static inline void lpuart_transmit_buffer(struct lpuart_port *sport)
578{
579 struct circ_buf *xmit = &sport->port.state->xmit;
580
581 while (!uart_circ_empty(xmit) &&
582 (readb(sport->port.membase + UARTTCFIFO) < sport->txfifo_size)) {
583 writeb(xmit->buf[xmit->tail], sport->port.membase + UARTDR);
584 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
585 sport->port.icount.tx++;
586 }
587
588 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
589 uart_write_wakeup(&sport->port);
590
591 if (uart_circ_empty(xmit))
592 lpuart_stop_tx(&sport->port);
593}
594
380c966c
JL		 595static inline void lpuart32_transmit_buffer(struct lpuart_port *sport)
596{
597 struct circ_buf *xmit = &sport->port.state->xmit;
598 unsigned long txcnt;
599
a0204f25 600 txcnt = lpuart32_read(&sport->port, UARTWATER);
380c966c
JL		 601 txcnt = txcnt >> UARTWATER_TXCNT_OFF;
602 txcnt &= UARTWATER_COUNT_MASK;
603 while (!uart_circ_empty(xmit) && (txcnt < sport->txfifo_size)) {
a0204f25 604 lpuart32_write(&sport->port, xmit->buf[xmit->tail], UARTDATA);
380c966c
JL		 605 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
606 sport->port.icount.tx++;
a0204f25 607 txcnt = lpuart32_read(&sport->port, UARTWATER);
380c966c
JL		 608 txcnt = txcnt >> UARTWATER_TXCNT_OFF;
609 txcnt &= UARTWATER_COUNT_MASK;
610 }
611
612 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
613 uart_write_wakeup(&sport->port);
614
615 if (uart_circ_empty(xmit))
616 lpuart32_stop_tx(&sport->port);
617}
618
c9e2e946
JL		 619static void lpuart_start_tx(struct uart_port *port)
620{
f1cd8c87
YY		 621 struct lpuart_port *sport = container_of(port,
622 struct lpuart_port, port);
623 struct circ_buf *xmit = &sport->port.state->xmit;
c9e2e946
JL		 624 unsigned char temp;
625
626 temp = readb(port->membase + UARTCR2);
627 writeb(temp | UARTCR2_TIE, port->membase + UARTCR2);
628
4a818c43 629 if (sport->lpuart_dma_tx_use) {
6250cc30
BD		 630 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port))
631 lpuart_dma_tx(sport);
f1cd8c87
YY		 632 } else {
633 if (readb(port->membase + UARTSR1) & UARTSR1_TDRE)
634 lpuart_transmit_buffer(sport);
635 }
c9e2e946
JL		 636}
637
380c966c
JL		 638static void lpuart32_start_tx(struct uart_port *port)
639{
640 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
641 unsigned long temp;
642
a0204f25
DA		 643 temp = lpuart32_read(port, UARTCTRL);
644 lpuart32_write(port, temp | UARTCTRL_TIE, UARTCTRL);
380c966c 645
a0204f25 646 if (lpuart32_read(port, UARTSTAT) & UARTSTAT_TDRE)
380c966c
JL		 647 lpuart32_transmit_buffer(sport);
648}
649
6250cc30
BD		 650/* return TIOCSER_TEMT when transmitter is not busy */
651static unsigned int lpuart_tx_empty(struct uart_port *port)
652{
653 struct lpuart_port *sport = container_of(port,
654 struct lpuart_port, port);
655 unsigned char sr1 = readb(port->membase + UARTSR1);
656 unsigned char sfifo = readb(port->membase + UARTSFIFO);
657
658 if (sport->dma_tx_in_progress)
659 return 0;
660
661 if (sr1 & UARTSR1_TC && sfifo & UARTSFIFO_TXEMPT)
662 return TIOCSER_TEMT;
663
664 return 0;
665}
666
667static unsigned int lpuart32_tx_empty(struct uart_port *port)
668{
a0204f25 669 return (lpuart32_read(port, UARTSTAT) & UARTSTAT_TC) ?
6250cc30
BD		 670 TIOCSER_TEMT : 0;
671}
672
3ee5447e
FE		 673static bool lpuart_is_32(struct lpuart_port *sport)
674{
675 return sport->port.iotype == UPIO_MEM32 ||
676 sport->port.iotype == UPIO_MEM32BE;
677}
678
c9e2e946
JL		 679static irqreturn_t lpuart_txint(int irq, void *dev_id)
680{
681 struct lpuart_port *sport = dev_id;
682 struct circ_buf *xmit = &sport->port.state->xmit;
683 unsigned long flags;
684
685 spin_lock_irqsave(&sport->port.lock, flags);
686 if (sport->port.x_char) {
3ee5447e 687 if (lpuart_is_32(sport))
a0204f25 688 lpuart32_write(&sport->port, sport->port.x_char, UARTDATA);
380c966c
JL		 689 else
690 writeb(sport->port.x_char, sport->port.membase + UARTDR);
c9e2e946
JL		 691 goto out;
692 }
693
694 if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) {
3ee5447e 695 if (lpuart_is_32(sport))
380c966c
JL		 696 lpuart32_stop_tx(&sport->port);
697 else
698 lpuart_stop_tx(&sport->port);
c9e2e946
JL		 699 goto out;
700 }
701
3ee5447e 702 if (lpuart_is_32(sport))
380c966c
JL		 703 lpuart32_transmit_buffer(sport);
704 else
705 lpuart_transmit_buffer(sport);
c9e2e946
JL		 706
707 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
708 uart_write_wakeup(&sport->port);
709
710out:
711 spin_unlock_irqrestore(&sport->port.lock, flags);
712 return IRQ_HANDLED;
713}
714
715static irqreturn_t lpuart_rxint(int irq, void *dev_id)
716{
717 struct lpuart_port *sport = dev_id;
718 unsigned int flg, ignored = 0;
719 struct tty_port *port = &sport->port.state->port;
720 unsigned long flags;
721 unsigned char rx, sr;
722
723 spin_lock_irqsave(&sport->port.lock, flags);
724
725 while (!(readb(sport->port.membase + UARTSFIFO) & UARTSFIFO_RXEMPT)) {
726 flg = TTY_NORMAL;
727 sport->port.icount.rx++;
728 /*
729 * to clear the FE, OR, NF, FE, PE flags,
730 * read SR1 then read DR
731 */
732 sr = readb(sport->port.membase + UARTSR1);
733 rx = readb(sport->port.membase + UARTDR);
734
735 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx))
736 continue;
737
738 if (sr & (UARTSR1_PE | UARTSR1_OR | UARTSR1_FE)) {
739 if (sr & UARTSR1_PE)
740 sport->port.icount.parity++;
741 else if (sr & UARTSR1_FE)
742 sport->port.icount.frame++;
743
744 if (sr & UARTSR1_OR)
745 sport->port.icount.overrun++;
746
747 if (sr & sport->port.ignore_status_mask) {
748 if (++ignored > 100)
749 goto out;
750 continue;
751 }
752
753 sr &= sport->port.read_status_mask;
754
755 if (sr & UARTSR1_PE)
756 flg = TTY_PARITY;
757 else if (sr & UARTSR1_FE)
758 flg = TTY_FRAME;
759
760 if (sr & UARTSR1_OR)
761 flg = TTY_OVERRUN;
762
763#ifdef SUPPORT_SYSRQ
764 sport->port.sysrq = 0;
765#endif
766 }
767
768 tty_insert_flip_char(port, rx, flg);
769 }
770
771out:
772 spin_unlock_irqrestore(&sport->port.lock, flags);
773
774 tty_flip_buffer_push(port);
775 return IRQ_HANDLED;
776}
777
380c966c
JL		 778static irqreturn_t lpuart32_rxint(int irq, void *dev_id)
779{
780 struct lpuart_port *sport = dev_id;
781 unsigned int flg, ignored = 0;
782 struct tty_port *port = &sport->port.state->port;
783 unsigned long flags;
784 unsigned long rx, sr;
785
786 spin_lock_irqsave(&sport->port.lock, flags);
787
a0204f25 788 while (!(lpuart32_read(&sport->port, UARTFIFO) & UARTFIFO_RXEMPT)) {
380c966c
JL		 789 flg = TTY_NORMAL;
790 sport->port.icount.rx++;
791 /*
792 * to clear the FE, OR, NF, FE, PE flags,
793 * read STAT then read DATA reg
794 */
a0204f25
DA		 795 sr = lpuart32_read(&sport->port, UARTSTAT);
796 rx = lpuart32_read(&sport->port, UARTDATA);
380c966c
JL		 797 rx &= 0x3ff;
798
799 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx))
800 continue;
801
802 if (sr & (UARTSTAT_PE | UARTSTAT_OR | UARTSTAT_FE)) {
803 if (sr & UARTSTAT_PE)
804 sport->port.icount.parity++;
805 else if (sr & UARTSTAT_FE)
806 sport->port.icount.frame++;
807
808 if (sr & UARTSTAT_OR)
809 sport->port.icount.overrun++;
810
811 if (sr & sport->port.ignore_status_mask) {
812 if (++ignored > 100)
813 goto out;
814 continue;
815 }
816
817 sr &= sport->port.read_status_mask;
818
819 if (sr & UARTSTAT_PE)
820 flg = TTY_PARITY;
821 else if (sr & UARTSTAT_FE)
822 flg = TTY_FRAME;
823
824 if (sr & UARTSTAT_OR)
825 flg = TTY_OVERRUN;
826
827#ifdef SUPPORT_SYSRQ
828 sport->port.sysrq = 0;
829#endif
830 }
831
832 tty_insert_flip_char(port, rx, flg);
833 }
834
835out:
836 spin_unlock_irqrestore(&sport->port.lock, flags);
837
838 tty_flip_buffer_push(port);
839 return IRQ_HANDLED;
840}
841
c9e2e946
JL		 842static irqreturn_t lpuart_int(int irq, void *dev_id)
843{
844 struct lpuart_port *sport = dev_id;
5887ad43 845 unsigned char sts;
c9e2e946
JL		 846
847 sts = readb(sport->port.membase + UARTSR1);
848
5887ad43
BD		 849 if (sts & UARTSR1_RDRF)
850 lpuart_rxint(irq, dev_id);
851
6250cc30
BD		 852 if (sts & UARTSR1_TDRE)
853 lpuart_txint(irq, dev_id);
c9e2e946
JL		 854
855 return IRQ_HANDLED;
856}
857
380c966c
JL		 858static irqreturn_t lpuart32_int(int irq, void *dev_id)
859{
860 struct lpuart_port *sport = dev_id;
861 unsigned long sts, rxcount;
862
a0204f25
DA		 863 sts = lpuart32_read(&sport->port, UARTSTAT);
864 rxcount = lpuart32_read(&sport->port, UARTWATER);
380c966c
JL		 865 rxcount = rxcount >> UARTWATER_RXCNT_OFF;
866
867 if (sts & UARTSTAT_RDRF || rxcount > 0)
868 lpuart32_rxint(irq, dev_id);
869
870 if ((sts & UARTSTAT_TDRE) &&
a0204f25 871 !(lpuart32_read(&sport->port, UARTBAUD) & UARTBAUD_TDMAE))
380c966c
JL		 872 lpuart_txint(irq, dev_id);
873
a0204f25 874 lpuart32_write(&sport->port, sts, UARTSTAT);
380c966c
JL		 875 return IRQ_HANDLED;
876}
877
5887ad43
BD		 878static void lpuart_copy_rx_to_tty(struct lpuart_port *sport)
879{
880 struct tty_port *port = &sport->port.state->port;
881 struct dma_tx_state state;
882 enum dma_status dmastat;
883 struct circ_buf *ring = &sport->rx_ring;
884 unsigned long flags;
885 int count = 0;
886 unsigned char sr;
887
888 sr = readb(sport->port.membase + UARTSR1);
889
890 if (sr & (UARTSR1_PE | UARTSR1_FE)) {
891 /* Read DR to clear the error flags */
892 readb(sport->port.membase + UARTDR);
893
894 if (sr & UARTSR1_PE)
895 sport->port.icount.parity++;
896 else if (sr & UARTSR1_FE)
897 sport->port.icount.frame++;
898 }
899
900 async_tx_ack(sport->dma_rx_desc);
901
902 spin_lock_irqsave(&sport->port.lock, flags);
903
904 dmastat = dmaengine_tx_status(sport->dma_rx_chan,
905 sport->dma_rx_cookie,
906 &state);
907
908 if (dmastat == DMA_ERROR) {
909 dev_err(sport->port.dev, "Rx DMA transfer failed!\n");
910 spin_unlock_irqrestore(&sport->port.lock, flags);
911 return;
912 }
913
914 /* CPU claims ownership of RX DMA buffer */
915 dma_sync_sg_for_cpu(sport->port.dev, &sport->rx_sgl, 1, DMA_FROM_DEVICE);
916
917 /*
918 * ring->head points to the end of data already written by the DMA.
919 * ring->tail points to the beginning of data to be read by the
920 * framework.
921 * The current transfer size should not be larger than the dma buffer
922 * length.
923 */
924 ring->head = sport->rx_sgl.length - state.residue;
925 BUG_ON(ring->head > sport->rx_sgl.length);
926 /*
927 * At this point ring->head may point to the first byte right after the
928 * last byte of the dma buffer:
929 * 0 <= ring->head <= sport->rx_sgl.length
930 *
931 * However ring->tail must always points inside the dma buffer:
932 * 0 <= ring->tail <= sport->rx_sgl.length - 1
933 *
934 * Since we use a ring buffer, we have to handle the case
935 * where head is lower than tail. In such a case, we first read from
936 * tail to the end of the buffer then reset tail.
937 */
938 if (ring->head < ring->tail) {
939 count = sport->rx_sgl.length - ring->tail;
940
941 tty_insert_flip_string(port, ring->buf + ring->tail, count);
942 ring->tail = 0;
943 sport->port.icount.rx += count;
944 }
945
946 /* Finally we read data from tail to head */
947 if (ring->tail < ring->head) {
948 count = ring->head - ring->tail;
949 tty_insert_flip_string(port, ring->buf + ring->tail, count);
950 /* Wrap ring->head if needed */
951 if (ring->head >= sport->rx_sgl.length)
952 ring->head = 0;
953 ring->tail = ring->head;
954 sport->port.icount.rx += count;
955 }
956
957 dma_sync_sg_for_device(sport->port.dev, &sport->rx_sgl, 1,
958 DMA_FROM_DEVICE);
959
960 spin_unlock_irqrestore(&sport->port.lock, flags);
961
962 tty_flip_buffer_push(port);
963 mod_timer(&sport->lpuart_timer, jiffies + sport->dma_rx_timeout);
964}
965
966static void lpuart_dma_rx_complete(void *arg)
967{
968 struct lpuart_port *sport = arg;
969
970 lpuart_copy_rx_to_tty(sport);
971}
972
973static void lpuart_timer_func(unsigned long data)
974{
975 struct lpuart_port *sport = (struct lpuart_port *)data;
976
977 lpuart_copy_rx_to_tty(sport);
978}
979
980static inline int lpuart_start_rx_dma(struct lpuart_port *sport)
981{
982 struct dma_slave_config dma_rx_sconfig = {};
983 struct circ_buf *ring = &sport->rx_ring;
984 int ret, nent;
985 int bits, baud;
986 struct tty_struct *tty = tty_port_tty_get(&sport->port.state->port);
987 struct ktermios *termios = &tty->termios;
988
989 baud = tty_get_baud_rate(tty);
990
991 bits = (termios->c_cflag & CSIZE) == CS7 ? 9 : 10;
992 if (termios->c_cflag & PARENB)
993 bits++;
994
995 /*
996 * Calculate length of one DMA buffer size to keep latency below
997 * 10ms at any baud rate.
998 */
999 sport->rx_dma_rng_buf_len = (DMA_RX_TIMEOUT * baud / bits / 1000) * 2;
1000 sport->rx_dma_rng_buf_len = (1 << (fls(sport->rx_dma_rng_buf_len) - 1));
1001 if (sport->rx_dma_rng_buf_len < 16)
1002 sport->rx_dma_rng_buf_len = 16;
1003
33ddca08 1004 ring->buf = kmalloc(sport->rx_dma_rng_buf_len, GFP_ATOMIC);
5887ad43
BD		 1005 if (!ring->buf) {
1006 dev_err(sport->port.dev, "Ring buf alloc failed\n");
1007 return -ENOMEM;
1008 }
1009
1010 sg_init_one(&sport->rx_sgl, ring->buf, sport->rx_dma_rng_buf_len);
1011 sg_set_buf(&sport->rx_sgl, ring->buf, sport->rx_dma_rng_buf_len);
1012 nent = dma_map_sg(sport->port.dev, &sport->rx_sgl, 1, DMA_FROM_DEVICE);
1013
1014 if (!nent) {
1015 dev_err(sport->port.dev, "DMA Rx mapping error\n");
1016 return -EINVAL;
1017 }
1018
1019 dma_rx_sconfig.src_addr = sport->port.mapbase + UARTDR;
1020 dma_rx_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1021 dma_rx_sconfig.src_maxburst = 1;
1022 dma_rx_sconfig.direction = DMA_DEV_TO_MEM;
1023 ret = dmaengine_slave_config(sport->dma_rx_chan, &dma_rx_sconfig);
1024
1025 if (ret < 0) {
1026 dev_err(sport->port.dev,
1027 "DMA Rx slave config failed, err = %d\n", ret);
1028 return ret;
1029 }
1030
1031 sport->dma_rx_desc = dmaengine_prep_dma_cyclic(sport->dma_rx_chan,
1032 sg_dma_address(&sport->rx_sgl),
1033 sport->rx_sgl.length,
1034 sport->rx_sgl.length / 2,
1035 DMA_DEV_TO_MEM,
1036 DMA_PREP_INTERRUPT);
1037 if (!sport->dma_rx_desc) {
1038 dev_err(sport->port.dev, "Cannot prepare cyclic DMA\n");
1039 return -EFAULT;
1040 }
1041
1042 sport->dma_rx_desc->callback = lpuart_dma_rx_complete;
1043 sport->dma_rx_desc->callback_param = sport;
1044 sport->dma_rx_cookie = dmaengine_submit(sport->dma_rx_desc);
1045 dma_async_issue_pending(sport->dma_rx_chan);
1046
1047 writeb(readb(sport->port.membase + UARTCR5) | UARTCR5_RDMAS,
1048 sport->port.membase + UARTCR5);
1049
1050 return 0;
1051}
1052
5887ad43
BD		 1053static void lpuart_dma_rx_free(struct uart_port *port)
1054{
1055 struct lpuart_port *sport = container_of(port,
1056 struct lpuart_port, port);
1057
1058 if (sport->dma_rx_chan)
1059 dmaengine_terminate_all(sport->dma_rx_chan);
1060
1061 dma_unmap_sg(sport->port.dev, &sport->rx_sgl, 1, DMA_FROM_DEVICE);
1062 kfree(sport->rx_ring.buf);
1063 sport->rx_ring.tail = 0;
1064 sport->rx_ring.head = 0;
1065 sport->dma_rx_desc = NULL;
1066 sport->dma_rx_cookie = -EINVAL;
1067}
1068
03895cf4
BD		 1069static int lpuart_config_rs485(struct uart_port *port,
1070 struct serial_rs485 *rs485)
1071{
1072 struct lpuart_port *sport = container_of(port,
1073 struct lpuart_port, port);
1074
1075 u8 modem = readb(sport->port.membase + UARTMODEM) &
1076 ~(UARTMODEM_TXRTSPOL | UARTMODEM_TXRTSE);
1077 writeb(modem, sport->port.membase + UARTMODEM);
1078
68c338ea
UKK		 1079 /* clear unsupported configurations */
1080 rs485->delay_rts_before_send = 0;
1081 rs485->delay_rts_after_send = 0;
1082 rs485->flags &= ~SER_RS485_RX_DURING_TX;
1083
03895cf4
BD		 1084 if (rs485->flags & SER_RS485_ENABLED) {
1085 /* Enable auto RS-485 RTS mode */
1086 modem |= UARTMODEM_TXRTSE;
1087
1088 /*
1089 * RTS needs to be logic HIGH either during transer _or_ after
1090 * transfer, other variants are not supported by the hardware.
1091 */
1092
1093 if (!(rs485->flags & (SER_RS485_RTS_ON_SEND |
1094 SER_RS485_RTS_AFTER_SEND)))
1095 rs485->flags |= SER_RS485_RTS_ON_SEND;
1096
1097 if (rs485->flags & SER_RS485_RTS_ON_SEND &&
1098 rs485->flags & SER_RS485_RTS_AFTER_SEND)
1099 rs485->flags &= ~SER_RS485_RTS_AFTER_SEND;
1100
1101 /*
1102 * The hardware defaults to RTS logic HIGH while transfer.
1103 * Switch polarity in case RTS shall be logic HIGH
1104 * after transfer.
1105 * Note: UART is assumed to be active high.
1106 */
1107 if (rs485->flags & SER_RS485_RTS_ON_SEND)
1108 modem &= ~UARTMODEM_TXRTSPOL;
1109 else if (rs485->flags & SER_RS485_RTS_AFTER_SEND)
1110 modem |= UARTMODEM_TXRTSPOL;
1111 }
1112
1113 /* Store the new configuration */
1114 sport->port.rs485 = *rs485;
1115
1116 writeb(modem, sport->port.membase + UARTMODEM);
1117 return 0;
1118}
1119
c9e2e946
JL		 1120static unsigned int lpuart_get_mctrl(struct uart_port *port)
1121{
1122 unsigned int temp = 0;
1123 unsigned char reg;
1124
1125 reg = readb(port->membase + UARTMODEM);
1126 if (reg & UARTMODEM_TXCTSE)
1127 temp |= TIOCM_CTS;
1128
1129 if (reg & UARTMODEM_RXRTSE)
1130 temp |= TIOCM_RTS;
1131
1132 return temp;
1133}
1134
380c966c
JL		 1135static unsigned int lpuart32_get_mctrl(struct uart_port *port)
1136{
1137 unsigned int temp = 0;
1138 unsigned long reg;
1139
a0204f25 1140 reg = lpuart32_read(port, UARTMODIR);
380c966c
JL		 1141 if (reg & UARTMODIR_TXCTSE)
1142 temp |= TIOCM_CTS;
1143
1144 if (reg & UARTMODIR_RXRTSE)
1145 temp |= TIOCM_RTS;
1146
1147 return temp;
1148}
1149
c9e2e946
JL		 1150static void lpuart_set_mctrl(struct uart_port *port, unsigned int mctrl)
1151{
1152 unsigned char temp;
03895cf4
BD		 1153 struct lpuart_port *sport = container_of(port,
1154 struct lpuart_port, port);
c9e2e946 1155
03895cf4
BD		 1156 /* Make sure RXRTSE bit is not set when RS485 is enabled */
1157 if (!(sport->port.rs485.flags & SER_RS485_ENABLED)) {
1158 temp = readb(sport->port.membase + UARTMODEM) &
c9e2e946
JL		 1159 ~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE);
1160
03895cf4
BD		 1161 if (mctrl & TIOCM_RTS)
1162 temp |= UARTMODEM_RXRTSE;
c9e2e946 1163
03895cf4
BD		 1164 if (mctrl & TIOCM_CTS)
1165 temp |= UARTMODEM_TXCTSE;
c9e2e946 1166
03895cf4
BD		 1167 writeb(temp, port->membase + UARTMODEM);
1168 }
c9e2e946
JL		 1169}
1170
380c966c
JL		 1171static void lpuart32_set_mctrl(struct uart_port *port, unsigned int mctrl)
1172{
1173 unsigned long temp;
1174
a0204f25 1175 temp = lpuart32_read(port, UARTMODIR) &
380c966c
JL		 1176 ~(UARTMODIR_RXRTSE | UARTMODIR_TXCTSE);
1177
1178 if (mctrl & TIOCM_RTS)
1179 temp |= UARTMODIR_RXRTSE;
1180
1181 if (mctrl & TIOCM_CTS)
1182 temp |= UARTMODIR_TXCTSE;
1183
a0204f25 1184 lpuart32_write(port, temp, UARTMODIR);
380c966c
JL		 1185}
1186
c9e2e946
JL		 1187static void lpuart_break_ctl(struct uart_port *port, int break_state)
1188{
1189 unsigned char temp;
1190
1191 temp = readb(port->membase + UARTCR2) & ~UARTCR2_SBK;
1192
1193 if (break_state != 0)
1194 temp |= UARTCR2_SBK;
1195
1196 writeb(temp, port->membase + UARTCR2);
1197}
1198
380c966c
JL		 1199static void lpuart32_break_ctl(struct uart_port *port, int break_state)
1200{
1201 unsigned long temp;
1202
a0204f25 1203 temp = lpuart32_read(port, UARTCTRL) & ~UARTCTRL_SBK;
380c966c
JL		 1204
1205 if (break_state != 0)
1206 temp |= UARTCTRL_SBK;
1207
a0204f25 1208 lpuart32_write(port, temp, UARTCTRL);
380c966c
JL		 1209}
1210
c9e2e946
JL		 1211static void lpuart_setup_watermark(struct lpuart_port *sport)
1212{
1213 unsigned char val, cr2;
bc764b8f 1214 unsigned char cr2_saved;
c9e2e946
JL		 1215
1216 cr2 = readb(sport->port.membase + UARTCR2);
bc764b8f 1217 cr2_saved = cr2;
c9e2e946
JL		 1218 cr2 &= ~(UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_TE |
1219 UARTCR2_RIE | UARTCR2_RE);
1220 writeb(cr2, sport->port.membase + UARTCR2);
1221
c9e2e946 1222 val = readb(sport->port.membase + UARTPFIFO);
c9e2e946
JL		 1223 writeb(val | UARTPFIFO_TXFE | UARTPFIFO_RXFE,
1224 sport->port.membase + UARTPFIFO);
1225
1226 /* flush Tx and Rx FIFO */
1227 writeb(UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH,
1228 sport->port.membase + UARTCFIFO);
1229
d68827c6
SA		 1230 /* explicitly clear RDRF */
1231 if (readb(sport->port.membase + UARTSR1) & UARTSR1_RDRF) {
1232 readb(sport->port.membase + UARTDR);
1233 writeb(UARTSFIFO_RXUF, sport->port.membase + UARTSFIFO);
1234 }
1235
f1cd8c87 1236 writeb(0, sport->port.membase + UARTTWFIFO);
c9e2e946 1237 writeb(1, sport->port.membase + UARTRWFIFO);
bc764b8f
SG		 1238
1239 /* Restore cr2 */
1240 writeb(cr2_saved, sport->port.membase + UARTCR2);
c9e2e946
JL		 1241}
1242
380c966c
JL		 1243static void lpuart32_setup_watermark(struct lpuart_port *sport)
1244{
1245 unsigned long val, ctrl;
1246 unsigned long ctrl_saved;
1247
a0204f25 1248 ctrl = lpuart32_read(&sport->port, UARTCTRL);
380c966c
JL		 1249 ctrl_saved = ctrl;
1250 ctrl &= ~(UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_TE |
1251 UARTCTRL_RIE | UARTCTRL_RE);
a0204f25 1252 lpuart32_write(&sport->port, ctrl, UARTCTRL);
380c966c
JL		 1253
1254 /* enable FIFO mode */
a0204f25 1255 val = lpuart32_read(&sport->port, UARTFIFO);
380c966c
JL		 1256 val |= UARTFIFO_TXFE | UARTFIFO_RXFE;
1257 val |= UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH;
a0204f25 1258 lpuart32_write(&sport->port, val, UARTFIFO);
380c966c
JL		 1259
1260 /* set the watermark */
1261 val = (0x1 << UARTWATER_RXWATER_OFF) | (0x0 << UARTWATER_TXWATER_OFF);
a0204f25 1262 lpuart32_write(&sport->port, val, UARTWATER);
380c966c
JL		 1263
1264 /* Restore cr2 */
a0204f25 1265 lpuart32_write(&sport->port, ctrl_saved, UARTCTRL);
380c966c
JL		 1266}
1267
5887ad43 1268static void rx_dma_timer_init(struct lpuart_port *sport)
f1cd8c87 1269{
5887ad43
BD		 1270 setup_timer(&sport->lpuart_timer, lpuart_timer_func,
1271 (unsigned long)sport);
1272 sport->lpuart_timer.expires = jiffies + sport->dma_rx_timeout;
1273 add_timer(&sport->lpuart_timer);
f1cd8c87
YY		 1274}
1275
c9e2e946
JL		 1276static int lpuart_startup(struct uart_port *port)
1277{
1278 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1279 int ret;
1280 unsigned long flags;
1281 unsigned char temp;
1282
ed9891bf
SA		 1283 /* determine FIFO size and enable FIFO mode */
1284 temp = readb(sport->port.membase + UARTPFIFO);
1285
1286 sport->txfifo_size = 0x1 << (((temp >> UARTPFIFO_TXSIZE_OFF) &
1287 UARTPFIFO_FIFOSIZE_MASK) + 1);
1288
4e8f2459
SA		 1289 sport->port.fifosize = sport->txfifo_size;
1290
ed9891bf
SA		 1291 sport->rxfifo_size = 0x1 << (((temp >> UARTPFIFO_RXSIZE_OFF) &
1292 UARTPFIFO_FIFOSIZE_MASK) + 1);
1293
c9e2e946
JL		 1294 ret = devm_request_irq(port->dev, port->irq, lpuart_int, 0,
1295 DRIVER_NAME, sport);
1296 if (ret)
1297 return ret;
1298
1299 spin_lock_irqsave(&sport->port.lock, flags);
1300
1301 lpuart_setup_watermark(sport);
1302
1303 temp = readb(sport->port.membase + UARTCR2);
1304 temp |= (UARTCR2_RIE | UARTCR2_TIE | UARTCR2_RE | UARTCR2_TE);
1305 writeb(temp, sport->port.membase + UARTCR2);
1306
5887ad43
BD		 1307 if (sport->dma_rx_chan && !lpuart_start_rx_dma(sport)) {
1308 /* set Rx DMA timeout */
1309 sport->dma_rx_timeout = msecs_to_jiffies(DMA_RX_TIMEOUT);
1310 if (!sport->dma_rx_timeout)
1311 sport->dma_rx_timeout = 1;
1312
1313 sport->lpuart_dma_rx_use = true;
1314 rx_dma_timer_init(sport);
1315 } else {
1316 sport->lpuart_dma_rx_use = false;
1317 }
1318
1319 if (sport->dma_tx_chan && !lpuart_dma_tx_request(port)) {
6250cc30 1320 init_waitqueue_head(&sport->dma_wait);
5887ad43
BD		 1321 sport->lpuart_dma_tx_use = true;
1322 temp = readb(port->membase + UARTCR5);
1323 writeb(temp | UARTCR5_TDMAS, port->membase + UARTCR5);
1324 } else {
1325 sport->lpuart_dma_tx_use = false;
1326 }
1327
c9e2e946 1328 spin_unlock_irqrestore(&sport->port.lock, flags);
5887ad43 1329
c9e2e946
JL		 1330 return 0;
1331}
1332
380c966c
JL		 1333static int lpuart32_startup(struct uart_port *port)
1334{
1335 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1336 int ret;
1337 unsigned long flags;
1338 unsigned long temp;
1339
1340 /* determine FIFO size */
a0204f25 1341 temp = lpuart32_read(&sport->port, UARTFIFO);
380c966c
JL		 1342
1343 sport->txfifo_size = 0x1 << (((temp >> UARTFIFO_TXSIZE_OFF) &
1344 UARTFIFO_FIFOSIZE_MASK) - 1);
1345
1346 sport->rxfifo_size = 0x1 << (((temp >> UARTFIFO_RXSIZE_OFF) &
1347 UARTFIFO_FIFOSIZE_MASK) - 1);
1348
1349 ret = devm_request_irq(port->dev, port->irq, lpuart32_int, 0,
1350 DRIVER_NAME, sport);
1351 if (ret)
1352 return ret;
1353
1354 spin_lock_irqsave(&sport->port.lock, flags);
1355
1356 lpuart32_setup_watermark(sport);
1357
a0204f25 1358 temp = lpuart32_read(&sport->port, UARTCTRL);
380c966c
JL		 1359 temp |= (UARTCTRL_RIE | UARTCTRL_TIE | UARTCTRL_RE | UARTCTRL_TE);
1360 temp |= UARTCTRL_ILIE;
a0204f25 1361 lpuart32_write(&sport->port, temp, UARTCTRL);
380c966c
JL		 1362
1363 spin_unlock_irqrestore(&sport->port.lock, flags);
1364 return 0;
1365}
1366
c9e2e946
JL		 1367static void lpuart_shutdown(struct uart_port *port)
1368{
1369 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1370 unsigned char temp;
1371 unsigned long flags;
1372
1373 spin_lock_irqsave(&port->lock, flags);
1374
1375 /* disable Rx/Tx and interrupts */
1376 temp = readb(port->membase + UARTCR2);
1377 temp &= ~(UARTCR2_TE | UARTCR2_RE |
1378 UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_RIE);
1379 writeb(temp, port->membase + UARTCR2);
1380
1381 spin_unlock_irqrestore(&port->lock, flags);
1382
1383 devm_free_irq(port->dev, port->irq, sport);
f1cd8c87 1384
4a818c43 1385 if (sport->lpuart_dma_rx_use) {
4a8588a1 1386 del_timer_sync(&sport->lpuart_timer);
5887ad43 1387 lpuart_dma_rx_free(&sport->port);
f1cd8c87 1388 }
4a818c43 1389
6250cc30
BD		 1390 if (sport->lpuart_dma_tx_use) {
1391 if (wait_event_interruptible(sport->dma_wait,
1392 !sport->dma_tx_in_progress) != false) {
1393 sport->dma_tx_in_progress = false;
1394 dmaengine_terminate_all(sport->dma_tx_chan);
1395 }
1396
1397 lpuart_stop_tx(port);
1398 }
c9e2e946
JL		 1399}
1400
380c966c
JL		 1401static void lpuart32_shutdown(struct uart_port *port)
1402{
1403 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1404 unsigned long temp;
1405 unsigned long flags;
1406
1407 spin_lock_irqsave(&port->lock, flags);
1408
1409 /* disable Rx/Tx and interrupts */
a0204f25 1410 temp = lpuart32_read(port, UARTCTRL);
380c966c
JL		 1411 temp &= ~(UARTCTRL_TE | UARTCTRL_RE |
1412 UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_RIE);
a0204f25 1413 lpuart32_write(port, temp, UARTCTRL);
380c966c
JL		 1414
1415 spin_unlock_irqrestore(&port->lock, flags);
1416
1417 devm_free_irq(port->dev, port->irq, sport);
1418}
1419
c9e2e946
JL		 1420static void
1421lpuart_set_termios(struct uart_port *port, struct ktermios *termios,
1422 struct ktermios *old)
1423{
1424 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1425 unsigned long flags;
aa9e7d78 1426 unsigned char cr1, old_cr1, old_cr2, cr3, cr4, bdh, modem;
c9e2e946
JL		 1427 unsigned int baud;
1428 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
1429 unsigned int sbr, brfa;
1430
1431 cr1 = old_cr1 = readb(sport->port.membase + UARTCR1);
1432 old_cr2 = readb(sport->port.membase + UARTCR2);
aa9e7d78 1433 cr3 = readb(sport->port.membase + UARTCR3);
c9e2e946
JL		 1434 cr4 = readb(sport->port.membase + UARTCR4);
1435 bdh = readb(sport->port.membase + UARTBDH);
1436 modem = readb(sport->port.membase + UARTMODEM);
1437 /*
1438 * only support CS8 and CS7, and for CS7 must enable PE.
1439 * supported mode:
1440 * - (7,e/o,1)
1441 * - (8,n,1)
1442 * - (8,m/s,1)
1443 * - (8,e/o,1)
1444 */
1445 while ((termios->c_cflag & CSIZE) != CS8 &&
1446 (termios->c_cflag & CSIZE) != CS7) {
1447 termios->c_cflag &= ~CSIZE;
1448 termios->c_cflag |= old_csize;
1449 old_csize = CS8;
1450 }
1451
1452 if ((termios->c_cflag & CSIZE) == CS8 ||
1453 (termios->c_cflag & CSIZE) == CS7)
1454 cr1 = old_cr1 & ~UARTCR1_M;
1455
1456 if (termios->c_cflag & CMSPAR) {
1457 if ((termios->c_cflag & CSIZE) != CS8) {
1458 termios->c_cflag &= ~CSIZE;
1459 termios->c_cflag |= CS8;
1460 }
1461 cr1 |= UARTCR1_M;
1462 }
1463
03895cf4
BD		 1464 /*
1465 * When auto RS-485 RTS mode is enabled,
1466 * hardware flow control need to be disabled.
1467 */
1468 if (sport->port.rs485.flags & SER_RS485_ENABLED)
1469 termios->c_cflag &= ~CRTSCTS;
1470
c9e2e946
JL		 1471 if (termios->c_cflag & CRTSCTS) {
1472 modem |= (UARTMODEM_RXRTSE | UARTMODEM_TXCTSE);
1473 } else {
1474 termios->c_cflag &= ~CRTSCTS;
1475 modem &= ~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE);
1476 }
1477
1478 if (termios->c_cflag & CSTOPB)
1479 termios->c_cflag &= ~CSTOPB;
1480
1481 /* parity must be enabled when CS7 to match 8-bits format */
1482 if ((termios->c_cflag & CSIZE) == CS7)
1483 termios->c_cflag |= PARENB;
1484
1485 if ((termios->c_cflag & PARENB)) {
1486 if (termios->c_cflag & CMSPAR) {
1487 cr1 &= ~UARTCR1_PE;
aa9e7d78
BD		 1488 if (termios->c_cflag & PARODD)
1489 cr3 |= UARTCR3_T8;
1490 else
1491 cr3 &= ~UARTCR3_T8;
c9e2e946
JL		 1492 } else {
1493 cr1 |= UARTCR1_PE;
1494 if ((termios->c_cflag & CSIZE) == CS8)
1495 cr1 |= UARTCR1_M;
1496 if (termios->c_cflag & PARODD)
1497 cr1 |= UARTCR1_PT;
1498 else
1499 cr1 &= ~UARTCR1_PT;
1500 }
1501 }
1502
1503 /* ask the core to calculate the divisor */
1504 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
1505
54a44d54
NY		 1506 /*
1507 * Need to update the Ring buffer length according to the selected
1508 * baud rate and restart Rx DMA path.
1509 *
1510 * Since timer function acqures sport->port.lock, need to stop before
1511 * acquring same lock because otherwise del_timer_sync() can deadlock.
1512 */
1513 if (old && sport->lpuart_dma_rx_use) {
1514 del_timer_sync(&sport->lpuart_timer);
1515 lpuart_dma_rx_free(&sport->port);
1516 }
1517
c9e2e946
JL		 1518 spin_lock_irqsave(&sport->port.lock, flags);
1519
1520 sport->port.read_status_mask = 0;
1521 if (termios->c_iflag & INPCK)
1522 sport->port.read_status_mask |= (UARTSR1_FE | UARTSR1_PE);
ef8b9ddc 1523 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
c9e2e946
JL		 1524 sport->port.read_status_mask |= UARTSR1_FE;
1525
1526 /* characters to ignore */
1527 sport->port.ignore_status_mask = 0;
1528 if (termios->c_iflag & IGNPAR)
1529 sport->port.ignore_status_mask |= UARTSR1_PE;
1530 if (termios->c_iflag & IGNBRK) {
1531 sport->port.ignore_status_mask |= UARTSR1_FE;
1532 /*
1533 * if we're ignoring parity and break indicators,
1534 * ignore overruns too (for real raw support).
1535 */
1536 if (termios->c_iflag & IGNPAR)
1537 sport->port.ignore_status_mask |= UARTSR1_OR;
1538 }
1539
1540 /* update the per-port timeout */
1541 uart_update_timeout(port, termios->c_cflag, baud);
1542
1543 /* wait transmit engin complete */
1544 while (!(readb(sport->port.membase + UARTSR1) & UARTSR1_TC))
1545 barrier();
1546
1547 /* disable transmit and receive */
1548 writeb(old_cr2 & ~(UARTCR2_TE | UARTCR2_RE),
1549 sport->port.membase + UARTCR2);
1550
1551 sbr = sport->port.uartclk / (16 * baud);
1552 brfa = ((sport->port.uartclk - (16 * sbr * baud)) * 2) / baud;
1553 bdh &= ~UARTBDH_SBR_MASK;
1554 bdh |= (sbr >> 8) & 0x1F;
1555 cr4 &= ~UARTCR4_BRFA_MASK;
1556 brfa &= UARTCR4_BRFA_MASK;
1557 writeb(cr4 | brfa, sport->port.membase + UARTCR4);
1558 writeb(bdh, sport->port.membase + UARTBDH);
1559 writeb(sbr & 0xFF, sport->port.membase + UARTBDL);
aa9e7d78 1560 writeb(cr3, sport->port.membase + UARTCR3);
c9e2e946
JL		 1561 writeb(cr1, sport->port.membase + UARTCR1);
1562 writeb(modem, sport->port.membase + UARTMODEM);
1563
1564 /* restore control register */
1565 writeb(old_cr2, sport->port.membase + UARTCR2);
1566
54a44d54
NY		 1567 if (old && sport->lpuart_dma_rx_use) {
1568 if (!lpuart_start_rx_dma(sport))
5887ad43 1569 rx_dma_timer_init(sport);
54a44d54 1570 else
5887ad43 1571 sport->lpuart_dma_rx_use = false;
5887ad43
BD		 1572 }
1573
c9e2e946
JL		 1574 spin_unlock_irqrestore(&sport->port.lock, flags);
1575}
1576
a6d7514b
DA		 1577static void
1578lpuart32_serial_setbrg(struct lpuart_port *sport, unsigned int baudrate)
1579{
1580 u32 sbr, osr, baud_diff, tmp_osr, tmp_sbr, tmp_diff, tmp;
1581 u32 clk = sport->port.uartclk;
1582
1583 /*
1584 * The idea is to use the best OSR (over-sampling rate) possible.
1585 * Note, OSR is typically hard-set to 16 in other LPUART instantiations.
1586 * Loop to find the best OSR value possible, one that generates minimum
1587 * baud_diff iterate through the rest of the supported values of OSR.
1588 *
1589 * Calculation Formula:
1590 * Baud Rate = baud clock / ((OSR+1) × SBR)
1591 */
1592 baud_diff = baudrate;
1593 osr = 0;
1594 sbr = 0;
1595
1596 for (tmp_osr = 4; tmp_osr <= 32; tmp_osr++) {
1597 /* calculate the temporary sbr value */
1598 tmp_sbr = (clk / (baudrate * tmp_osr));
1599 if (tmp_sbr == 0)
1600 tmp_sbr = 1;
1601
1602 /*
1603 * calculate the baud rate difference based on the temporary
1604 * osr and sbr values
1605 */
1606 tmp_diff = clk / (tmp_osr * tmp_sbr) - baudrate;
1607
1608 /* select best values between sbr and sbr+1 */
1609 tmp = clk / (tmp_osr * (tmp_sbr + 1));
1610 if (tmp_diff > (baudrate - tmp)) {
1611 tmp_diff = baudrate - tmp;
1612 tmp_sbr++;
1613 }
1614
1615 if (tmp_diff <= baud_diff) {
1616 baud_diff = tmp_diff;
1617 osr = tmp_osr;
1618 sbr = tmp_sbr;
1619
1620 if (!baud_diff)
1621 break;
1622 }
1623 }
1624
1625 /* handle buadrate outside acceptable rate */
1626 if (baud_diff > ((baudrate / 100) * 3))
1627 dev_warn(sport->port.dev,
1628 "unacceptable baud rate difference of more than 3%%\n");
1629
1630 tmp = lpuart32_read(&sport->port, UARTBAUD);
1631
1632 if ((osr > 3) && (osr < 8))
1633 tmp |= UARTBAUD_BOTHEDGE;
1634
1635 tmp &= ~(UARTBAUD_OSR_MASK << UARTBAUD_OSR_SHIFT);
1636 tmp |= (((osr-1) & UARTBAUD_OSR_MASK) << UARTBAUD_OSR_SHIFT);
1637
1638 tmp &= ~UARTBAUD_SBR_MASK;
1639 tmp |= sbr & UARTBAUD_SBR_MASK;
1640
1641 tmp &= ~(UARTBAUD_TDMAE | UARTBAUD_RDMAE);
1642
1643 lpuart32_write(&sport->port, tmp, UARTBAUD);
1644}
1645
380c966c
JL		 1646static void
1647lpuart32_set_termios(struct uart_port *port, struct ktermios *termios,
1648 struct ktermios *old)
1649{
1650 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1651 unsigned long flags;
1652 unsigned long ctrl, old_ctrl, bd, modem;
1653 unsigned int baud;
1654 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
380c966c 1655
a0204f25
DA		 1656 ctrl = old_ctrl = lpuart32_read(&sport->port, UARTCTRL);
1657 bd = lpuart32_read(&sport->port, UARTBAUD);
1658 modem = lpuart32_read(&sport->port, UARTMODIR);
380c966c
JL		 1659 /*
1660 * only support CS8 and CS7, and for CS7 must enable PE.
1661 * supported mode:
1662 * - (7,e/o,1)
1663 * - (8,n,1)
1664 * - (8,m/s,1)
1665 * - (8,e/o,1)
1666 */
1667 while ((termios->c_cflag & CSIZE) != CS8 &&
1668 (termios->c_cflag & CSIZE) != CS7) {
1669 termios->c_cflag &= ~CSIZE;
1670 termios->c_cflag |= old_csize;
1671 old_csize = CS8;
1672 }
1673
1674 if ((termios->c_cflag & CSIZE) == CS8 ||
1675 (termios->c_cflag & CSIZE) == CS7)
1676 ctrl = old_ctrl & ~UARTCTRL_M;
1677
1678 if (termios->c_cflag & CMSPAR) {
1679 if ((termios->c_cflag & CSIZE) != CS8) {
1680 termios->c_cflag &= ~CSIZE;
1681 termios->c_cflag |= CS8;
1682 }
1683 ctrl |= UARTCTRL_M;
1684 }
1685
1686 if (termios->c_cflag & CRTSCTS) {
1687 modem |= (UARTMODEM_RXRTSE | UARTMODEM_TXCTSE);
1688 } else {
1689 termios->c_cflag &= ~CRTSCTS;
1690 modem &= ~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE);
1691 }
1692
1693 if (termios->c_cflag & CSTOPB)
1694 termios->c_cflag &= ~CSTOPB;
1695
1696 /* parity must be enabled when CS7 to match 8-bits format */
1697 if ((termios->c_cflag & CSIZE) == CS7)
1698 termios->c_cflag |= PARENB;
1699
1700 if ((termios->c_cflag & PARENB)) {
1701 if (termios->c_cflag & CMSPAR) {
1702 ctrl &= ~UARTCTRL_PE;
1703 ctrl |= UARTCTRL_M;
1704 } else {
1705 ctrl |= UARTCR1_PE;
1706 if ((termios->c_cflag & CSIZE) == CS8)
1707 ctrl |= UARTCTRL_M;
1708 if (termios->c_cflag & PARODD)
1709 ctrl |= UARTCTRL_PT;
1710 else
1711 ctrl &= ~UARTCTRL_PT;
1712 }
1713 }
1714
1715 /* ask the core to calculate the divisor */
1716 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
1717
1718 spin_lock_irqsave(&sport->port.lock, flags);
1719
1720 sport->port.read_status_mask = 0;
1721 if (termios->c_iflag & INPCK)
1722 sport->port.read_status_mask |= (UARTSTAT_FE | UARTSTAT_PE);
1723 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
1724 sport->port.read_status_mask |= UARTSTAT_FE;
1725
1726 /* characters to ignore */
1727 sport->port.ignore_status_mask = 0;
1728 if (termios->c_iflag & IGNPAR)
1729 sport->port.ignore_status_mask |= UARTSTAT_PE;
1730 if (termios->c_iflag & IGNBRK) {
1731 sport->port.ignore_status_mask |= UARTSTAT_FE;
1732 /*
1733 * if we're ignoring parity and break indicators,
1734 * ignore overruns too (for real raw support).
1735 */
1736 if (termios->c_iflag & IGNPAR)
1737 sport->port.ignore_status_mask |= UARTSTAT_OR;
1738 }
1739
1740 /* update the per-port timeout */
1741 uart_update_timeout(port, termios->c_cflag, baud);
1742
1743 /* wait transmit engin complete */
a0204f25 1744 while (!(lpuart32_read(&sport->port, UARTSTAT) & UARTSTAT_TC))
380c966c
JL		 1745 barrier();
1746
1747 /* disable transmit and receive */
a0204f25
DA		 1748 lpuart32_write(&sport->port, old_ctrl & ~(UARTCTRL_TE | UARTCTRL_RE),
1749 UARTCTRL);
380c966c 1750
a6d7514b 1751 lpuart32_serial_setbrg(sport, baud);
a0204f25
DA		 1752 lpuart32_write(&sport->port, modem, UARTMODIR);
1753 lpuart32_write(&sport->port, ctrl, UARTCTRL);
380c966c
JL		 1754 /* restore control register */
1755
1756 spin_unlock_irqrestore(&sport->port.lock, flags);
1757}
1758
c9e2e946
JL		 1759static const char *lpuart_type(struct uart_port *port)
1760{
1761 return "FSL_LPUART";
1762}
1763
1764static void lpuart_release_port(struct uart_port *port)
1765{
1766 /* nothing to do */
1767}
1768
1769static int lpuart_request_port(struct uart_port *port)
1770{
1771 return 0;
1772}
1773
1774/* configure/autoconfigure the port */
1775static void lpuart_config_port(struct uart_port *port, int flags)
1776{
1777 if (flags & UART_CONFIG_TYPE)
1778 port->type = PORT_LPUART;
1779}
1780
1781static int lpuart_verify_port(struct uart_port *port, struct serial_struct *ser)
1782{
1783 int ret = 0;
1784
1785 if (ser->type != PORT_UNKNOWN && ser->type != PORT_LPUART)
1786 ret = -EINVAL;
1787 if (port->irq != ser->irq)
1788 ret = -EINVAL;
1789 if (ser->io_type != UPIO_MEM)
1790 ret = -EINVAL;
1791 if (port->uartclk / 16 != ser->baud_base)
1792 ret = -EINVAL;
1793 if (port->iobase != ser->port)
1794 ret = -EINVAL;
1795 if (ser->hub6 != 0)
1796 ret = -EINVAL;
1797 return ret;
1798}
1799
069a47e5 1800static const struct uart_ops lpuart_pops = {
c9e2e946
JL		 1801 .tx_empty = lpuart_tx_empty,
1802 .set_mctrl = lpuart_set_mctrl,
1803 .get_mctrl = lpuart_get_mctrl,
1804 .stop_tx = lpuart_stop_tx,
1805 .start_tx = lpuart_start_tx,
1806 .stop_rx = lpuart_stop_rx,
c9e2e946
JL		 1807 .break_ctl = lpuart_break_ctl,
1808 .startup = lpuart_startup,
1809 .shutdown = lpuart_shutdown,
1810 .set_termios = lpuart_set_termios,
1811 .type = lpuart_type,
1812 .request_port = lpuart_request_port,
1813 .release_port = lpuart_release_port,
1814 .config_port = lpuart_config_port,
1815 .verify_port = lpuart_verify_port,
bfc2e07f 1816 .flush_buffer = lpuart_flush_buffer,
2a41bc2a
NR		 1817#if defined(CONFIG_CONSOLE_POLL)
1818 .poll_init = lpuart_poll_init,
1819 .poll_get_char = lpuart_poll_get_char,
1820 .poll_put_char = lpuart_poll_put_char,
1821#endif
c9e2e946
JL		 1822};
1823
069a47e5 1824static const struct uart_ops lpuart32_pops = {
380c966c
JL		 1825 .tx_empty = lpuart32_tx_empty,
1826 .set_mctrl = lpuart32_set_mctrl,
1827 .get_mctrl = lpuart32_get_mctrl,
1828 .stop_tx = lpuart32_stop_tx,
1829 .start_tx = lpuart32_start_tx,
1830 .stop_rx = lpuart32_stop_rx,
1831 .break_ctl = lpuart32_break_ctl,
1832 .startup = lpuart32_startup,
1833 .shutdown = lpuart32_shutdown,
1834 .set_termios = lpuart32_set_termios,
1835 .type = lpuart_type,
1836 .request_port = lpuart_request_port,
1837 .release_port = lpuart_release_port,
1838 .config_port = lpuart_config_port,
1839 .verify_port = lpuart_verify_port,
bfc2e07f 1840 .flush_buffer = lpuart_flush_buffer,
a5fa2660
MV		 1841#if defined(CONFIG_CONSOLE_POLL)
1842 .poll_init = lpuart32_poll_init,
1843 .poll_get_char = lpuart32_poll_get_char,
1844 .poll_put_char = lpuart32_poll_put_char,
1845#endif
380c966c
JL		 1846};
1847
c9e2e946
JL		 1848static struct lpuart_port *lpuart_ports[UART_NR];
1849
1850#ifdef CONFIG_SERIAL_FSL_LPUART_CONSOLE
1851static void lpuart_console_putchar(struct uart_port *port, int ch)
1852{
1853 while (!(readb(port->membase + UARTSR1) & UARTSR1_TDRE))
1854 barrier();
1855
1856 writeb(ch, port->membase + UARTDR);
1857}
1858
380c966c
JL		 1859static void lpuart32_console_putchar(struct uart_port *port, int ch)
1860{
a0204f25 1861 while (!(lpuart32_read(port, UARTSTAT) & UARTSTAT_TDRE))
380c966c
JL		 1862 barrier();
1863
a0204f25 1864 lpuart32_write(port, ch, UARTDATA);
380c966c
JL		 1865}
1866
c9e2e946
JL		 1867static void
1868lpuart_console_write(struct console *co, const char *s, unsigned int count)
1869{
1870 struct lpuart_port *sport = lpuart_ports[co->index];
1871 unsigned char old_cr2, cr2;
abf1e0a9
SA		 1872 unsigned long flags;
1873 int locked = 1;
1874
1875 if (sport->port.sysrq || oops_in_progress)
1876 locked = spin_trylock_irqsave(&sport->port.lock, flags);
1877 else
1878 spin_lock_irqsave(&sport->port.lock, flags);
c9e2e946
JL		 1879
1880 /* first save CR2 and then disable interrupts */
1881 cr2 = old_cr2 = readb(sport->port.membase + UARTCR2);
1882 cr2 |= (UARTCR2_TE | UARTCR2_RE);
1883 cr2 &= ~(UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_RIE);
1884 writeb(cr2, sport->port.membase + UARTCR2);
1885
1886 uart_console_write(&sport->port, s, count, lpuart_console_putchar);
1887
1888 /* wait for transmitter finish complete and restore CR2 */
1889 while (!(readb(sport->port.membase + UARTSR1) & UARTSR1_TC))
1890 barrier();
1891
1892 writeb(old_cr2, sport->port.membase + UARTCR2);
abf1e0a9
SA		 1893
1894 if (locked)
1895 spin_unlock_irqrestore(&sport->port.lock, flags);
c9e2e946
JL		 1896}
1897
380c966c
JL		 1898static void
1899lpuart32_console_write(struct console *co, const char *s, unsigned int count)
1900{
1901 struct lpuart_port *sport = lpuart_ports[co->index];
1902 unsigned long old_cr, cr;
abf1e0a9
SA		 1903 unsigned long flags;
1904 int locked = 1;
1905
1906 if (sport->port.sysrq || oops_in_progress)
1907 locked = spin_trylock_irqsave(&sport->port.lock, flags);
1908 else
1909 spin_lock_irqsave(&sport->port.lock, flags);
380c966c
JL		 1910
1911 /* first save CR2 and then disable interrupts */
a0204f25 1912 cr = old_cr = lpuart32_read(&sport->port, UARTCTRL);
380c966c
JL		 1913 cr |= (UARTCTRL_TE | UARTCTRL_RE);
1914 cr &= ~(UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_RIE);
a0204f25 1915 lpuart32_write(&sport->port, cr, UARTCTRL);
380c966c
JL		 1916
1917 uart_console_write(&sport->port, s, count, lpuart32_console_putchar);
1918
1919 /* wait for transmitter finish complete and restore CR2 */
a0204f25 1920 while (!(lpuart32_read(&sport->port, UARTSTAT) & UARTSTAT_TC))
380c966c
JL		 1921 barrier();
1922
a0204f25 1923 lpuart32_write(&sport->port, old_cr, UARTCTRL);
abf1e0a9
SA		 1924
1925 if (locked)
1926 spin_unlock_irqrestore(&sport->port.lock, flags);
380c966c
JL		 1927}
1928
c9e2e946
JL		 1929/*
1930 * if the port was already initialised (eg, by a boot loader),
1931 * try to determine the current setup.
1932 */
1933static void __init
1934lpuart_console_get_options(struct lpuart_port *sport, int *baud,
1935 int *parity, int *bits)
1936{
1937 unsigned char cr, bdh, bdl, brfa;
1938 unsigned int sbr, uartclk, baud_raw;
1939
1940 cr = readb(sport->port.membase + UARTCR2);
1941 cr &= UARTCR2_TE | UARTCR2_RE;
1942 if (!cr)
1943 return;
1944
1945 /* ok, the port was enabled */
1946
1947 cr = readb(sport->port.membase + UARTCR1);
1948
1949 *parity = 'n';
1950 if (cr & UARTCR1_PE) {
1951 if (cr & UARTCR1_PT)
1952 *parity = 'o';
1953 else
1954 *parity = 'e';
1955 }
1956
1957 if (cr & UARTCR1_M)
1958 *bits = 9;
1959 else
1960 *bits = 8;
1961
1962 bdh = readb(sport->port.membase + UARTBDH);
1963 bdh &= UARTBDH_SBR_MASK;
1964 bdl = readb(sport->port.membase + UARTBDL);
1965 sbr = bdh;
1966 sbr <<= 8;
1967 sbr |= bdl;
1968 brfa = readb(sport->port.membase + UARTCR4);
1969 brfa &= UARTCR4_BRFA_MASK;
1970
1971 uartclk = clk_get_rate(sport->clk);
1972 /*
1973 * baud = mod_clk/(16*(sbr[13]+(brfa)/32)
1974 */
1975 baud_raw = uartclk / (16 * (sbr + brfa / 32));
1976
1977 if (*baud != baud_raw)
1978 printk(KERN_INFO "Serial: Console lpuart rounded baud rate"
1979 "from %d to %d\n", baud_raw, *baud);
1980}
1981
380c966c
JL		 1982static void __init
1983lpuart32_console_get_options(struct lpuart_port *sport, int *baud,
1984 int *parity, int *bits)
1985{
1986 unsigned long cr, bd;
1987 unsigned int sbr, uartclk, baud_raw;
1988
a0204f25 1989 cr = lpuart32_read(&sport->port, UARTCTRL);
380c966c
JL		 1990 cr &= UARTCTRL_TE | UARTCTRL_RE;
1991 if (!cr)
1992 return;
1993
1994 /* ok, the port was enabled */
1995
a0204f25 1996 cr = lpuart32_read(&sport->port, UARTCTRL);
380c966c
JL		 1997
1998 *parity = 'n';
1999 if (cr & UARTCTRL_PE) {
2000 if (cr & UARTCTRL_PT)
2001 *parity = 'o';
2002 else
2003 *parity = 'e';
2004 }
2005
2006 if (cr & UARTCTRL_M)
2007 *bits = 9;
2008 else
2009 *bits = 8;
2010
a0204f25 2011 bd = lpuart32_read(&sport->port, UARTBAUD);
380c966c
JL		 2012 bd &= UARTBAUD_SBR_MASK;
2013 sbr = bd;
2014 uartclk = clk_get_rate(sport->clk);
2015 /*
2016 * baud = mod_clk/(16*(sbr[13]+(brfa)/32)
2017 */
2018 baud_raw = uartclk / (16 * sbr);
2019
2020 if (*baud != baud_raw)
2021 printk(KERN_INFO "Serial: Console lpuart rounded baud rate"
2022 "from %d to %d\n", baud_raw, *baud);
2023}
2024
c9e2e946
JL		 2025static int __init lpuart_console_setup(struct console *co, char *options)
2026{
2027 struct lpuart_port *sport;
2028 int baud = 115200;
2029 int bits = 8;
2030 int parity = 'n';
2031 int flow = 'n';
2032
2033 /*
2034 * check whether an invalid uart number has been specified, and
2035 * if so, search for the first available port that does have
2036 * console support.
2037 */
2038 if (co->index == -1 || co->index >= ARRAY_SIZE(lpuart_ports))
2039 co->index = 0;
2040
2041 sport = lpuart_ports[co->index];
2042 if (sport == NULL)
2043 return -ENODEV;
2044
2045 if (options)
2046 uart_parse_options(options, &baud, &parity, &bits, &flow);
2047 else
3ee5447e 2048 if (lpuart_is_32(sport))
380c966c
JL		 2049 lpuart32_console_get_options(sport, &baud, &parity, &bits);
2050 else
2051 lpuart_console_get_options(sport, &baud, &parity, &bits);
c9e2e946 2052
3ee5447e 2053 if (lpuart_is_32(sport))
380c966c
JL		 2054 lpuart32_setup_watermark(sport);
2055 else
2056 lpuart_setup_watermark(sport);
c9e2e946
JL		 2057
2058 return uart_set_options(&sport->port, co, baud, parity, bits, flow);
2059}
2060
2061static struct uart_driver lpuart_reg;
2062static struct console lpuart_console = {
2063 .name = DEV_NAME,
2064 .write = lpuart_console_write,
2065 .device = uart_console_device,
2066 .setup = lpuart_console_setup,
2067 .flags = CON_PRINTBUFFER,
2068 .index = -1,
2069 .data = &lpuart_reg,
2070};
2071
380c966c
JL		 2072static struct console lpuart32_console = {
2073 .name = DEV_NAME,
2074 .write = lpuart32_console_write,
2075 .device = uart_console_device,
2076 .setup = lpuart_console_setup,
2077 .flags = CON_PRINTBUFFER,
2078 .index = -1,
2079 .data = &lpuart_reg,
2080};
2081
1d59b382
SA		 2082static void lpuart_early_write(struct console *con, const char *s, unsigned n)
2083{
2084 struct earlycon_device *dev = con->data;
2085
2086 uart_console_write(&dev->port, s, n, lpuart_console_putchar);
2087}
2088
2089static void lpuart32_early_write(struct console *con, const char *s, unsigned n)
2090{
2091 struct earlycon_device *dev = con->data;
2092
2093 uart_console_write(&dev->port, s, n, lpuart32_console_putchar);
2094}
2095
2096static int __init lpuart_early_console_setup(struct earlycon_device *device,
2097 const char *opt)
2098{
2099 if (!device->port.membase)
2100 return -ENODEV;
2101
2102 device->con->write = lpuart_early_write;
2103 return 0;
2104}
2105
2106static int __init lpuart32_early_console_setup(struct earlycon_device *device,
2107 const char *opt)
2108{
2109 if (!device->port.membase)
2110 return -ENODEV;
2111
f98e1fcd 2112 device->port.iotype = UPIO_MEM32BE;
1d59b382
SA		 2113 device->con->write = lpuart32_early_write;
2114 return 0;
2115}
2116
97d6f353
DA		 2117static int __init lpuart32_imx_early_console_setup(struct earlycon_device *device,
2118 const char *opt)
2119{
2120 if (!device->port.membase)
2121 return -ENODEV;
2122
2123 device->port.iotype = UPIO_MEM32;
2124 device->port.membase += IMX_REG_OFF;
2125 device->con->write = lpuart32_early_write;
2126
2127 return 0;
2128}
1d59b382
SA		 2129OF_EARLYCON_DECLARE(lpuart, "fsl,vf610-lpuart", lpuart_early_console_setup);
2130OF_EARLYCON_DECLARE(lpuart32, "fsl,ls1021a-lpuart", lpuart32_early_console_setup);
97d6f353 2131OF_EARLYCON_DECLARE(lpuart32, "fsl,imx7ulp-lpuart", lpuart32_imx_early_console_setup);
1d59b382
SA		 2132EARLYCON_DECLARE(lpuart, lpuart_early_console_setup);
2133EARLYCON_DECLARE(lpuart32, lpuart32_early_console_setup);
2134
c9e2e946 2135#define LPUART_CONSOLE (&lpuart_console)
380c966c 2136#define LPUART32_CONSOLE (&lpuart32_console)
c9e2e946
JL		 2137#else
2138#define LPUART_CONSOLE NULL
380c966c 2139#define LPUART32_CONSOLE NULL
c9e2e946
JL		 2140#endif
2141
2142static struct uart_driver lpuart_reg = {
2143 .owner = THIS_MODULE,
2144 .driver_name = DRIVER_NAME,
2145 .dev_name = DEV_NAME,
2146 .nr = ARRAY_SIZE(lpuart_ports),
2147 .cons = LPUART_CONSOLE,
2148};
2149
2150static int lpuart_probe(struct platform_device *pdev)
2151{
0d6fce90
DA		 2152 const struct of_device_id *of_id = of_match_device(lpuart_dt_ids,
2153 &pdev->dev);
2154 const struct lpuart_soc_data *sdata = of_id->data;
c9e2e946
JL		 2155 struct device_node *np = pdev->dev.of_node;
2156 struct lpuart_port *sport;
2157 struct resource *res;
2158 int ret;
2159
2160 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);
2161 if (!sport)
2162 return -ENOMEM;
2163
2164 pdev->dev.coherent_dma_mask = 0;
2165
2166 ret = of_alias_get_id(np, "serial");
2167 if (ret < 0) {
2168 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret);
2169 return ret;
2170 }
2171 sport->port.line = ret;
4ae612a3 2172 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
c9e2e946
JL		 2173 sport->port.membase = devm_ioremap_resource(&pdev->dev, res);
2174 if (IS_ERR(sport->port.membase))
2175 return PTR_ERR(sport->port.membase);
2176
24b1e5f0 2177 sport->port.membase += sdata->reg_off;
4ae612a3 2178 sport->port.mapbase = res->start;
c9e2e946
JL		 2179 sport->port.dev = &pdev->dev;
2180 sport->port.type = PORT_LPUART;
394a9e2c
JS		 2181 ret = platform_get_irq(pdev, 0);
2182 if (ret < 0) {
2183 dev_err(&pdev->dev, "cannot obtain irq\n");
2184 return ret;
2185 }
2186 sport->port.irq = ret;
0d6fce90 2187 sport->port.iotype = sdata->iotype;
3ee5447e 2188 if (lpuart_is_32(sport))
380c966c
JL		 2189 sport->port.ops = &lpuart32_pops;
2190 else
2191 sport->port.ops = &lpuart_pops;
c9e2e946
JL		 2192 sport->port.flags = UPF_BOOT_AUTOCONF;
2193
03895cf4
BD		 2194 sport->port.rs485_config = lpuart_config_rs485;
2195
c9e2e946
JL		 2196 sport->clk = devm_clk_get(&pdev->dev, "ipg");
2197 if (IS_ERR(sport->clk)) {
2198 ret = PTR_ERR(sport->clk);
2199 dev_err(&pdev->dev, "failed to get uart clk: %d\n", ret);
2200 return ret;
2201 }
2202
2203 ret = clk_prepare_enable(sport->clk);
2204 if (ret) {
2205 dev_err(&pdev->dev, "failed to enable uart clk: %d\n", ret);
2206 return ret;
2207 }
2208
2209 sport->port.uartclk = clk_get_rate(sport->clk);
2210
2211 lpuart_ports[sport->port.line] = sport;
2212
2213 platform_set_drvdata(pdev, &sport->port);
2214
3ee5447e 2215 if (lpuart_is_32(sport))
380c966c
JL		 2216 lpuart_reg.cons = LPUART32_CONSOLE;
2217 else
2218 lpuart_reg.cons = LPUART_CONSOLE;
2219
c9e2e946
JL		 2220 ret = uart_add_one_port(&lpuart_reg, &sport->port);
2221 if (ret) {
2222 clk_disable_unprepare(sport->clk);
2223 return ret;
2224 }
2225
4a818c43
SA		 2226 sport->dma_tx_chan = dma_request_slave_channel(sport->port.dev, "tx");
2227 if (!sport->dma_tx_chan)
2228 dev_info(sport->port.dev, "DMA tx channel request failed, "
2229 "operating without tx DMA\n");
2230
2231 sport->dma_rx_chan = dma_request_slave_channel(sport->port.dev, "rx");
2232 if (!sport->dma_rx_chan)
2233 dev_info(sport->port.dev, "DMA rx channel request failed, "
2234 "operating without rx DMA\n");
2235
03895cf4
BD		 2236 if (of_property_read_bool(np, "linux,rs485-enabled-at-boot-time")) {
2237 sport->port.rs485.flags |= SER_RS485_ENABLED;
2238 sport->port.rs485.flags |= SER_RS485_RTS_ON_SEND;
2239 writeb(UARTMODEM_TXRTSE, sport->port.membase + UARTMODEM);
2240 }
2241
c9e2e946
JL		 2242 return 0;
2243}
2244
2245static int lpuart_remove(struct platform_device *pdev)
2246{
2247 struct lpuart_port *sport = platform_get_drvdata(pdev);
2248
2249 uart_remove_one_port(&lpuart_reg, &sport->port);
2250
2251 clk_disable_unprepare(sport->clk);
2252
4a818c43
SA		 2253 if (sport->dma_tx_chan)
2254 dma_release_channel(sport->dma_tx_chan);
2255
2256 if (sport->dma_rx_chan)
2257 dma_release_channel(sport->dma_rx_chan);
2258
c9e2e946
JL		 2259 return 0;
2260}
2261
2262#ifdef CONFIG_PM_SLEEP
2263static int lpuart_suspend(struct device *dev)
2264{
2265 struct lpuart_port *sport = dev_get_drvdata(dev);
2fe605df 2266 unsigned long temp;
3d6bcddf 2267 bool irq_wake;
2fe605df 2268
3ee5447e 2269 if (lpuart_is_32(sport)) {
2fe605df 2270 /* disable Rx/Tx and interrupts */
a0204f25 2271 temp = lpuart32_read(&sport->port, UARTCTRL);
2fe605df 2272 temp &= ~(UARTCTRL_TE | UARTCTRL_TIE | UARTCTRL_TCIE);
a0204f25 2273 lpuart32_write(&sport->port, temp, UARTCTRL);
2fe605df
YY		 2274 } else {
2275 /* disable Rx/Tx and interrupts */
2276 temp = readb(sport->port.membase + UARTCR2);
2277 temp &= ~(UARTCR2_TE | UARTCR2_TIE | UARTCR2_TCIE);
2278 writeb(temp, sport->port.membase + UARTCR2);
2279 }
c9e2e946
JL		 2280
2281 uart_suspend_port(&lpuart_reg, &sport->port);
c05efd69 2282
3d6bcddf
AS		 2283 /* uart_suspend_port() might set wakeup flag */
2284 irq_wake = irqd_is_wakeup_set(irq_get_irq_data(sport->port.irq));
2285
c05efd69
BD		 2286 if (sport->lpuart_dma_rx_use) {
2287 /*
2288 * EDMA driver during suspend will forcefully release any
2289 * non-idle DMA channels. If port wakeup is enabled or if port
2290 * is console port or 'no_console_suspend' is set the Rx DMA
2291 * cannot resume as as expected, hence gracefully release the
2292 * Rx DMA path before suspend and start Rx DMA path on resume.
2293 */
3d6bcddf 2294 if (irq_wake) {
c05efd69
BD		 2295 del_timer_sync(&sport->lpuart_timer);
2296 lpuart_dma_rx_free(&sport->port);
2297 }
2298
2299 /* Disable Rx DMA to use UART port as wakeup source */
2300 writeb(readb(sport->port.membase + UARTCR5) & ~UARTCR5_RDMAS,
2301 sport->port.membase + UARTCR5);
2302 }
2303
2304 if (sport->lpuart_dma_tx_use) {
2305 sport->dma_tx_in_progress = false;
2306 dmaengine_terminate_all(sport->dma_tx_chan);
2307 }
2308
3d6bcddf 2309 if (sport->port.suspended && !irq_wake)
d6b0d2f2 2310 clk_disable_unprepare(sport->clk);
c9e2e946
JL		 2311
2312 return 0;
2313}
2314
2315static int lpuart_resume(struct device *dev)
2316{
2317 struct lpuart_port *sport = dev_get_drvdata(dev);
3d6bcddf 2318 bool irq_wake = irqd_is_wakeup_set(irq_get_irq_data(sport->port.irq));
08de1014
JL		 2319 unsigned long temp;
2320
3d6bcddf 2321 if (sport->port.suspended && !irq_wake)
d6b0d2f2
SA		 2322 clk_prepare_enable(sport->clk);
2323
3ee5447e 2324 if (lpuart_is_32(sport)) {
08de1014 2325 lpuart32_setup_watermark(sport);
a0204f25 2326 temp = lpuart32_read(&sport->port, UARTCTRL);
08de1014
JL		 2327 temp |= (UARTCTRL_RIE | UARTCTRL_TIE | UARTCTRL_RE |
2328 UARTCTRL_TE | UARTCTRL_ILIE);
a0204f25 2329 lpuart32_write(&sport->port, temp, UARTCTRL);
08de1014
JL		 2330 } else {
2331 lpuart_setup_watermark(sport);
2332 temp = readb(sport->port.membase + UARTCR2);
2333 temp |= (UARTCR2_RIE | UARTCR2_TIE | UARTCR2_RE | UARTCR2_TE);
2334 writeb(temp, sport->port.membase + UARTCR2);
2335 }
c9e2e946 2336
c05efd69 2337 if (sport->lpuart_dma_rx_use) {
3d6bcddf 2338 if (irq_wake) {
54a44d54 2339 if (!lpuart_start_rx_dma(sport))
c05efd69 2340 rx_dma_timer_init(sport);
54a44d54 2341 else
c05efd69 2342 sport->lpuart_dma_rx_use = false;
c05efd69
BD		 2343 }
2344 }
2345
2346 if (sport->dma_tx_chan && !lpuart_dma_tx_request(&sport->port)) {
2347 init_waitqueue_head(&sport->dma_wait);
2348 sport->lpuart_dma_tx_use = true;
2349 writeb(readb(sport->port.membase + UARTCR5) |
2350 UARTCR5_TDMAS, sport->port.membase + UARTCR5);
2351 } else {
2352 sport->lpuart_dma_tx_use = false;
2353 }
2354
c9e2e946
JL		 2355 uart_resume_port(&lpuart_reg, &sport->port);
2356
2357 return 0;
2358}
2359#endif
2360
2361static SIMPLE_DEV_PM_OPS(lpuart_pm_ops, lpuart_suspend, lpuart_resume);
2362
2363static struct platform_driver lpuart_driver = {
2364 .probe = lpuart_probe,
2365 .remove = lpuart_remove,
2366 .driver = {
2367 .name = "fsl-lpuart",
c9e2e946
JL		 2368 .of_match_table = lpuart_dt_ids,
2369 .pm = &lpuart_pm_ops,
2370 },
2371};
2372
2373static int __init lpuart_serial_init(void)
2374{
144c29ed 2375 int ret = uart_register_driver(&lpuart_reg);
c9e2e946 2376
c9e2e946
JL		 2377 if (ret)
2378 return ret;
2379
2380 ret = platform_driver_register(&lpuart_driver);
2381 if (ret)
2382 uart_unregister_driver(&lpuart_reg);
2383
39c34b09 2384 return ret;
c9e2e946
JL		 2385}
2386
2387static void __exit lpuart_serial_exit(void)
2388{
2389 platform_driver_unregister(&lpuart_driver);
2390 uart_unregister_driver(&lpuart_reg);
2391}
2392
2393module_init(lpuart_serial_init);
2394module_exit(lpuart_serial_exit);
2395
2396MODULE_DESCRIPTION("Freescale lpuart serial port driver");
2397MODULE_LICENSE("GPL v2");
Linux 6.x block layer and io_uring tree(s)