Commit | Line | Data |
---|---|---|
e3b3d0f5 | 1 | // SPDX-License-Identifier: GPL-2.0+ |
1da177e4 | 2 | /* |
1da177e4 LT |
3 | * Driver for CPM (SCC/SMC) serial ports; core driver |
4 | * | |
5 | * Based on arch/ppc/cpm2_io/uart.c by Dan Malek | |
6 | * Based on ppc8xx.c by Thomas Gleixner | |
7 | * Based on drivers/serial/amba.c by Russell King | |
8 | * | |
4c8d3d99 | 9 | * Maintainer: Kumar Gala (galak@kernel.crashing.org) (CPM2) |
1da177e4 | 10 | * Pantelis Antoniou (panto@intracom.gr) (CPM1) |
311c4627 | 11 | * |
7ae87036 | 12 | * Copyright (C) 2004, 2007 Freescale Semiconductor, Inc. |
1da177e4 | 13 | * (C) 2004 Intracom, S.A. |
6e197696 | 14 | * (C) 2005-2006 MontaVista Software, Inc. |
0d844065 | 15 | * Vitaly Bordug <vbordug@ru.mvista.com> |
1da177e4 LT |
16 | */ |
17 | ||
1da177e4 LT |
18 | #include <linux/module.h> |
19 | #include <linux/tty.h> | |
ee160a38 | 20 | #include <linux/tty_flip.h> |
1da177e4 LT |
21 | #include <linux/ioport.h> |
22 | #include <linux/init.h> | |
23 | #include <linux/serial.h> | |
24 | #include <linux/console.h> | |
25 | #include <linux/sysrq.h> | |
26 | #include <linux/device.h> | |
57c8a661 | 27 | #include <linux/memblock.h> |
1da177e4 | 28 | #include <linux/dma-mapping.h> |
e27987cd | 29 | #include <linux/fs_uart_pd.h> |
5af50730 RH |
30 | #include <linux/of_address.h> |
31 | #include <linux/of_irq.h> | |
0b2a2e5b | 32 | #include <linux/of_platform.h> |
7485d26b LP |
33 | #include <linux/gpio.h> |
34 | #include <linux/of_gpio.h> | |
80776554 | 35 | #include <linux/clk.h> |
1da177e4 LT |
36 | |
37 | #include <asm/io.h> | |
38 | #include <asm/irq.h> | |
39 | #include <asm/delay.h> | |
3dd0dcbe | 40 | #include <asm/fs_pd.h> |
7ae87036 SW |
41 | #include <asm/udbg.h> |
42 | ||
1da177e4 LT |
43 | #if defined(CONFIG_SERIAL_CPM_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) |
44 | #define SUPPORT_SYSRQ | |
45 | #endif | |
46 | ||
47 | #include <linux/serial_core.h> | |
48 | #include <linux/kernel.h> | |
49 | ||
50 | #include "cpm_uart.h" | |
51 | ||
1da177e4 LT |
52 | |
53 | /**************************************************************/ | |
54 | ||
55 | static int cpm_uart_tx_pump(struct uart_port *port); | |
56 | static void cpm_uart_init_smc(struct uart_cpm_port *pinfo); | |
57 | static void cpm_uart_init_scc(struct uart_cpm_port *pinfo); | |
58 | static void cpm_uart_initbd(struct uart_cpm_port *pinfo); | |
59 | ||
60 | /**************************************************************/ | |
61 | ||
59733ef7 | 62 | #define HW_BUF_SPD_THRESHOLD 2400 |
5b04ec4a | 63 | |
1da177e4 | 64 | /* |
311c4627 | 65 | * Check, if transmit buffers are processed |
1da177e4 LT |
66 | */ |
67 | static unsigned int cpm_uart_tx_empty(struct uart_port *port) | |
68 | { | |
e789d268 FF |
69 | struct uart_cpm_port *pinfo = |
70 | container_of(port, struct uart_cpm_port, port); | |
c1dcfd9d | 71 | cbd_t __iomem *bdp = pinfo->tx_bd_base; |
1da177e4 LT |
72 | int ret = 0; |
73 | ||
74 | while (1) { | |
c1dcfd9d | 75 | if (in_be16(&bdp->cbd_sc) & BD_SC_READY) |
1da177e4 LT |
76 | break; |
77 | ||
c1dcfd9d | 78 | if (in_be16(&bdp->cbd_sc) & BD_SC_WRAP) { |
1da177e4 LT |
79 | ret = TIOCSER_TEMT; |
80 | break; | |
81 | } | |
82 | bdp++; | |
83 | } | |
84 | ||
85 | pr_debug("CPM uart[%d]:tx_empty: %d\n", port->line, ret); | |
86 | ||
87 | return ret; | |
88 | } | |
89 | ||
90 | static void cpm_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) | |
91 | { | |
e789d268 FF |
92 | struct uart_cpm_port *pinfo = |
93 | container_of(port, struct uart_cpm_port, port); | |
7485d26b LP |
94 | |
95 | if (pinfo->gpios[GPIO_RTS] >= 0) | |
96 | gpio_set_value(pinfo->gpios[GPIO_RTS], !(mctrl & TIOCM_RTS)); | |
97 | ||
98 | if (pinfo->gpios[GPIO_DTR] >= 0) | |
99 | gpio_set_value(pinfo->gpios[GPIO_DTR], !(mctrl & TIOCM_DTR)); | |
1da177e4 LT |
100 | } |
101 | ||
102 | static unsigned int cpm_uart_get_mctrl(struct uart_port *port) | |
103 | { | |
e789d268 FF |
104 | struct uart_cpm_port *pinfo = |
105 | container_of(port, struct uart_cpm_port, port); | |
7485d26b LP |
106 | unsigned int mctrl = TIOCM_CTS | TIOCM_DSR | TIOCM_CAR; |
107 | ||
108 | if (pinfo->gpios[GPIO_CTS] >= 0) { | |
109 | if (gpio_get_value(pinfo->gpios[GPIO_CTS])) | |
110 | mctrl &= ~TIOCM_CTS; | |
111 | } | |
112 | ||
113 | if (pinfo->gpios[GPIO_DSR] >= 0) { | |
114 | if (gpio_get_value(pinfo->gpios[GPIO_DSR])) | |
115 | mctrl &= ~TIOCM_DSR; | |
116 | } | |
117 | ||
118 | if (pinfo->gpios[GPIO_DCD] >= 0) { | |
119 | if (gpio_get_value(pinfo->gpios[GPIO_DCD])) | |
120 | mctrl &= ~TIOCM_CAR; | |
121 | } | |
122 | ||
123 | if (pinfo->gpios[GPIO_RI] >= 0) { | |
124 | if (!gpio_get_value(pinfo->gpios[GPIO_RI])) | |
125 | mctrl |= TIOCM_RNG; | |
126 | } | |
127 | ||
128 | return mctrl; | |
1da177e4 LT |
129 | } |
130 | ||
131 | /* | |
132 | * Stop transmitter | |
133 | */ | |
b129a8cc | 134 | static void cpm_uart_stop_tx(struct uart_port *port) |
1da177e4 | 135 | { |
e789d268 FF |
136 | struct uart_cpm_port *pinfo = |
137 | container_of(port, struct uart_cpm_port, port); | |
c1dcfd9d SW |
138 | smc_t __iomem *smcp = pinfo->smcp; |
139 | scc_t __iomem *sccp = pinfo->sccp; | |
1da177e4 LT |
140 | |
141 | pr_debug("CPM uart[%d]:stop tx\n", port->line); | |
142 | ||
143 | if (IS_SMC(pinfo)) | |
c1dcfd9d | 144 | clrbits8(&smcp->smc_smcm, SMCM_TX); |
1da177e4 | 145 | else |
c1dcfd9d | 146 | clrbits16(&sccp->scc_sccm, UART_SCCM_TX); |
1da177e4 LT |
147 | } |
148 | ||
149 | /* | |
150 | * Start transmitter | |
151 | */ | |
b129a8cc | 152 | static void cpm_uart_start_tx(struct uart_port *port) |
1da177e4 | 153 | { |
e789d268 FF |
154 | struct uart_cpm_port *pinfo = |
155 | container_of(port, struct uart_cpm_port, port); | |
c1dcfd9d SW |
156 | smc_t __iomem *smcp = pinfo->smcp; |
157 | scc_t __iomem *sccp = pinfo->sccp; | |
1da177e4 LT |
158 | |
159 | pr_debug("CPM uart[%d]:start tx\n", port->line); | |
160 | ||
161 | if (IS_SMC(pinfo)) { | |
c1dcfd9d | 162 | if (in_8(&smcp->smc_smcm) & SMCM_TX) |
1da177e4 LT |
163 | return; |
164 | } else { | |
c1dcfd9d | 165 | if (in_be16(&sccp->scc_sccm) & UART_SCCM_TX) |
1da177e4 LT |
166 | return; |
167 | } | |
168 | ||
169 | if (cpm_uart_tx_pump(port) != 0) { | |
311c4627 | 170 | if (IS_SMC(pinfo)) { |
c1dcfd9d | 171 | setbits8(&smcp->smc_smcm, SMCM_TX); |
311c4627 | 172 | } else { |
c1dcfd9d | 173 | setbits16(&sccp->scc_sccm, UART_SCCM_TX); |
311c4627 | 174 | } |
1da177e4 LT |
175 | } |
176 | } | |
177 | ||
178 | /* | |
311c4627 | 179 | * Stop receiver |
1da177e4 LT |
180 | */ |
181 | static void cpm_uart_stop_rx(struct uart_port *port) | |
182 | { | |
e789d268 FF |
183 | struct uart_cpm_port *pinfo = |
184 | container_of(port, struct uart_cpm_port, port); | |
c1dcfd9d SW |
185 | smc_t __iomem *smcp = pinfo->smcp; |
186 | scc_t __iomem *sccp = pinfo->sccp; | |
1da177e4 LT |
187 | |
188 | pr_debug("CPM uart[%d]:stop rx\n", port->line); | |
189 | ||
190 | if (IS_SMC(pinfo)) | |
c1dcfd9d | 191 | clrbits8(&smcp->smc_smcm, SMCM_RX); |
1da177e4 | 192 | else |
c1dcfd9d | 193 | clrbits16(&sccp->scc_sccm, UART_SCCM_RX); |
1da177e4 LT |
194 | } |
195 | ||
1da177e4 | 196 | /* |
311c4627 | 197 | * Generate a break. |
1da177e4 LT |
198 | */ |
199 | static void cpm_uart_break_ctl(struct uart_port *port, int break_state) | |
200 | { | |
e789d268 FF |
201 | struct uart_cpm_port *pinfo = |
202 | container_of(port, struct uart_cpm_port, port); | |
1da177e4 LT |
203 | |
204 | pr_debug("CPM uart[%d]:break ctrl, break_state: %d\n", port->line, | |
205 | break_state); | |
206 | ||
207 | if (break_state) | |
7ae87036 | 208 | cpm_line_cr_cmd(pinfo, CPM_CR_STOP_TX); |
1da177e4 | 209 | else |
7ae87036 | 210 | cpm_line_cr_cmd(pinfo, CPM_CR_RESTART_TX); |
1da177e4 LT |
211 | } |
212 | ||
213 | /* | |
214 | * Transmit characters, refill buffer descriptor, if possible | |
215 | */ | |
7d12e780 | 216 | static void cpm_uart_int_tx(struct uart_port *port) |
1da177e4 LT |
217 | { |
218 | pr_debug("CPM uart[%d]:TX INT\n", port->line); | |
219 | ||
220 | cpm_uart_tx_pump(port); | |
221 | } | |
222 | ||
8e21d04c JW |
223 | #ifdef CONFIG_CONSOLE_POLL |
224 | static int serial_polled; | |
225 | #endif | |
226 | ||
1da177e4 LT |
227 | /* |
228 | * Receive characters | |
229 | */ | |
7d12e780 | 230 | static void cpm_uart_int_rx(struct uart_port *port) |
1da177e4 LT |
231 | { |
232 | int i; | |
c1dcfd9d SW |
233 | unsigned char ch; |
234 | u8 *cp; | |
227434f8 | 235 | struct tty_port *tport = &port->state->port; |
e789d268 FF |
236 | struct uart_cpm_port *pinfo = |
237 | container_of(port, struct uart_cpm_port, port); | |
c1dcfd9d | 238 | cbd_t __iomem *bdp; |
1da177e4 LT |
239 | u16 status; |
240 | unsigned int flg; | |
241 | ||
242 | pr_debug("CPM uart[%d]:RX INT\n", port->line); | |
243 | ||
244 | /* Just loop through the closed BDs and copy the characters into | |
245 | * the buffer. | |
246 | */ | |
247 | bdp = pinfo->rx_cur; | |
248 | for (;;) { | |
8e21d04c JW |
249 | #ifdef CONFIG_CONSOLE_POLL |
250 | if (unlikely(serial_polled)) { | |
251 | serial_polled = 0; | |
252 | return; | |
253 | } | |
254 | #endif | |
1da177e4 | 255 | /* get status */ |
c1dcfd9d | 256 | status = in_be16(&bdp->cbd_sc); |
1da177e4 LT |
257 | /* If this one is empty, return happy */ |
258 | if (status & BD_SC_EMPTY) | |
259 | break; | |
260 | ||
261 | /* get number of characters, and check spce in flip-buffer */ | |
c1dcfd9d | 262 | i = in_be16(&bdp->cbd_datlen); |
1da177e4 | 263 | |
311c4627 | 264 | /* If we have not enough room in tty flip buffer, then we try |
1da177e4 LT |
265 | * later, which will be the next rx-interrupt or a timeout |
266 | */ | |
227434f8 | 267 | if (tty_buffer_request_room(tport, i) < i) { |
76a55431 VB |
268 | printk(KERN_WARNING "No room in flip buffer\n"); |
269 | return; | |
1da177e4 LT |
270 | } |
271 | ||
272 | /* get pointer */ | |
c1dcfd9d | 273 | cp = cpm2cpu_addr(in_be32(&bdp->cbd_bufaddr), pinfo); |
1da177e4 LT |
274 | |
275 | /* loop through the buffer */ | |
276 | while (i-- > 0) { | |
277 | ch = *cp++; | |
278 | port->icount.rx++; | |
279 | flg = TTY_NORMAL; | |
280 | ||
281 | if (status & | |
282 | (BD_SC_BR | BD_SC_FR | BD_SC_PR | BD_SC_OV)) | |
283 | goto handle_error; | |
7d12e780 | 284 | if (uart_handle_sysrq_char(port, ch)) |
1da177e4 | 285 | continue; |
8e21d04c JW |
286 | #ifdef CONFIG_CONSOLE_POLL |
287 | if (unlikely(serial_polled)) { | |
288 | serial_polled = 0; | |
289 | return; | |
290 | } | |
291 | #endif | |
1da177e4 | 292 | error_return: |
92a19f9c | 293 | tty_insert_flip_char(tport, ch, flg); |
1da177e4 LT |
294 | |
295 | } /* End while (i--) */ | |
296 | ||
297 | /* This BD is ready to be used again. Clear status. get next */ | |
c1dcfd9d SW |
298 | clrbits16(&bdp->cbd_sc, BD_SC_BR | BD_SC_FR | BD_SC_PR | |
299 | BD_SC_OV | BD_SC_ID); | |
300 | setbits16(&bdp->cbd_sc, BD_SC_EMPTY); | |
1da177e4 | 301 | |
c1dcfd9d | 302 | if (in_be16(&bdp->cbd_sc) & BD_SC_WRAP) |
1da177e4 LT |
303 | bdp = pinfo->rx_bd_base; |
304 | else | |
305 | bdp++; | |
311c4627 | 306 | |
1da177e4 LT |
307 | } /* End for (;;) */ |
308 | ||
309 | /* Write back buffer pointer */ | |
c1dcfd9d | 310 | pinfo->rx_cur = bdp; |
1da177e4 LT |
311 | |
312 | /* activate BH processing */ | |
2e124b4a | 313 | tty_flip_buffer_push(tport); |
1da177e4 LT |
314 | |
315 | return; | |
316 | ||
317 | /* Error processing */ | |
318 | ||
319 | handle_error: | |
320 | /* Statistics */ | |
321 | if (status & BD_SC_BR) | |
322 | port->icount.brk++; | |
323 | if (status & BD_SC_PR) | |
324 | port->icount.parity++; | |
325 | if (status & BD_SC_FR) | |
326 | port->icount.frame++; | |
327 | if (status & BD_SC_OV) | |
328 | port->icount.overrun++; | |
329 | ||
330 | /* Mask out ignored conditions */ | |
331 | status &= port->read_status_mask; | |
332 | ||
333 | /* Handle the remaining ones */ | |
334 | if (status & BD_SC_BR) | |
335 | flg = TTY_BREAK; | |
336 | else if (status & BD_SC_PR) | |
337 | flg = TTY_PARITY; | |
338 | else if (status & BD_SC_FR) | |
339 | flg = TTY_FRAME; | |
340 | ||
341 | /* overrun does not affect the current character ! */ | |
342 | if (status & BD_SC_OV) { | |
343 | ch = 0; | |
344 | flg = TTY_OVERRUN; | |
345 | /* We skip this buffer */ | |
346 | /* CHECK: Is really nothing senseful there */ | |
347 | /* ASSUMPTION: it contains nothing valid */ | |
348 | i = 0; | |
349 | } | |
350 | #ifdef SUPPORT_SYSRQ | |
351 | port->sysrq = 0; | |
352 | #endif | |
353 | goto error_return; | |
354 | } | |
355 | ||
356 | /* | |
357 | * Asynchron mode interrupt handler | |
358 | */ | |
7d12e780 | 359 | static irqreturn_t cpm_uart_int(int irq, void *data) |
1da177e4 LT |
360 | { |
361 | u8 events; | |
15aafa2f | 362 | struct uart_port *port = data; |
1da177e4 | 363 | struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port; |
c1dcfd9d SW |
364 | smc_t __iomem *smcp = pinfo->smcp; |
365 | scc_t __iomem *sccp = pinfo->sccp; | |
1da177e4 LT |
366 | |
367 | pr_debug("CPM uart[%d]:IRQ\n", port->line); | |
368 | ||
369 | if (IS_SMC(pinfo)) { | |
c1dcfd9d SW |
370 | events = in_8(&smcp->smc_smce); |
371 | out_8(&smcp->smc_smce, events); | |
1da177e4 LT |
372 | if (events & SMCM_BRKE) |
373 | uart_handle_break(port); | |
374 | if (events & SMCM_RX) | |
7d12e780 | 375 | cpm_uart_int_rx(port); |
1da177e4 | 376 | if (events & SMCM_TX) |
7d12e780 | 377 | cpm_uart_int_tx(port); |
1da177e4 | 378 | } else { |
c1dcfd9d SW |
379 | events = in_be16(&sccp->scc_scce); |
380 | out_be16(&sccp->scc_scce, events); | |
1da177e4 LT |
381 | if (events & UART_SCCM_BRKE) |
382 | uart_handle_break(port); | |
383 | if (events & UART_SCCM_RX) | |
7d12e780 | 384 | cpm_uart_int_rx(port); |
1da177e4 | 385 | if (events & UART_SCCM_TX) |
7d12e780 | 386 | cpm_uart_int_tx(port); |
1da177e4 LT |
387 | } |
388 | return (events) ? IRQ_HANDLED : IRQ_NONE; | |
389 | } | |
390 | ||
391 | static int cpm_uart_startup(struct uart_port *port) | |
392 | { | |
393 | int retval; | |
e789d268 FF |
394 | struct uart_cpm_port *pinfo = |
395 | container_of(port, struct uart_cpm_port, port); | |
1da177e4 LT |
396 | |
397 | pr_debug("CPM uart[%d]:startup\n", port->line); | |
398 | ||
9ab92120 XF |
399 | /* If the port is not the console, make sure rx is disabled. */ |
400 | if (!(pinfo->flags & FLAG_CONSOLE)) { | |
401 | /* Disable UART rx */ | |
402 | if (IS_SMC(pinfo)) { | |
403 | clrbits16(&pinfo->smcp->smc_smcmr, SMCMR_REN); | |
404 | clrbits8(&pinfo->smcp->smc_smcm, SMCM_RX); | |
405 | } else { | |
406 | clrbits32(&pinfo->sccp->scc_gsmrl, SCC_GSMRL_ENR); | |
407 | clrbits16(&pinfo->sccp->scc_sccm, UART_SCCM_RX); | |
408 | } | |
725ef4a3 | 409 | cpm_uart_initbd(pinfo); |
9ab92120 XF |
410 | cpm_line_cr_cmd(pinfo, CPM_CR_INIT_TRX); |
411 | } | |
1da177e4 LT |
412 | /* Install interrupt handler. */ |
413 | retval = request_irq(port->irq, cpm_uart_int, 0, "cpm_uart", port); | |
414 | if (retval) | |
415 | return retval; | |
416 | ||
417 | /* Startup rx-int */ | |
418 | if (IS_SMC(pinfo)) { | |
c1dcfd9d SW |
419 | setbits8(&pinfo->smcp->smc_smcm, SMCM_RX); |
420 | setbits16(&pinfo->smcp->smc_smcmr, (SMCMR_REN | SMCMR_TEN)); | |
1da177e4 | 421 | } else { |
c1dcfd9d SW |
422 | setbits16(&pinfo->sccp->scc_sccm, UART_SCCM_RX); |
423 | setbits32(&pinfo->sccp->scc_gsmrl, (SCC_GSMRL_ENR | SCC_GSMRL_ENT)); | |
1da177e4 LT |
424 | } |
425 | ||
426 | return 0; | |
427 | } | |
428 | ||
311c4627 KG |
429 | inline void cpm_uart_wait_until_send(struct uart_cpm_port *pinfo) |
430 | { | |
638861d5 KG |
431 | set_current_state(TASK_UNINTERRUPTIBLE); |
432 | schedule_timeout(pinfo->wait_closing); | |
311c4627 KG |
433 | } |
434 | ||
1da177e4 LT |
435 | /* |
436 | * Shutdown the uart | |
437 | */ | |
438 | static void cpm_uart_shutdown(struct uart_port *port) | |
439 | { | |
e789d268 FF |
440 | struct uart_cpm_port *pinfo = |
441 | container_of(port, struct uart_cpm_port, port); | |
1da177e4 LT |
442 | |
443 | pr_debug("CPM uart[%d]:shutdown\n", port->line); | |
444 | ||
445 | /* free interrupt handler */ | |
446 | free_irq(port->irq, port); | |
447 | ||
448 | /* If the port is not the console, disable Rx and Tx. */ | |
449 | if (!(pinfo->flags & FLAG_CONSOLE)) { | |
311c4627 | 450 | /* Wait for all the BDs marked sent */ |
638861d5 KG |
451 | while(!cpm_uart_tx_empty(port)) { |
452 | set_current_state(TASK_UNINTERRUPTIBLE); | |
311c4627 | 453 | schedule_timeout(2); |
638861d5 KG |
454 | } |
455 | ||
456 | if (pinfo->wait_closing) | |
311c4627 KG |
457 | cpm_uart_wait_until_send(pinfo); |
458 | ||
1da177e4 LT |
459 | /* Stop uarts */ |
460 | if (IS_SMC(pinfo)) { | |
c1dcfd9d SW |
461 | smc_t __iomem *smcp = pinfo->smcp; |
462 | clrbits16(&smcp->smc_smcmr, SMCMR_REN | SMCMR_TEN); | |
463 | clrbits8(&smcp->smc_smcm, SMCM_RX | SMCM_TX); | |
1da177e4 | 464 | } else { |
c1dcfd9d SW |
465 | scc_t __iomem *sccp = pinfo->sccp; |
466 | clrbits32(&sccp->scc_gsmrl, SCC_GSMRL_ENR | SCC_GSMRL_ENT); | |
467 | clrbits16(&sccp->scc_sccm, UART_SCCM_TX | UART_SCCM_RX); | |
1da177e4 LT |
468 | } |
469 | ||
470 | /* Shut them really down and reinit buffer descriptors */ | |
ae2d4c39 NL |
471 | if (IS_SMC(pinfo)) { |
472 | out_be16(&pinfo->smcup->smc_brkcr, 0); | |
7ae87036 | 473 | cpm_line_cr_cmd(pinfo, CPM_CR_STOP_TX); |
ae2d4c39 NL |
474 | } else { |
475 | out_be16(&pinfo->sccup->scc_brkcr, 0); | |
7ae87036 | 476 | cpm_line_cr_cmd(pinfo, CPM_CR_GRA_STOP_TX); |
ae2d4c39 | 477 | } |
61f5657c | 478 | |
1da177e4 LT |
479 | cpm_uart_initbd(pinfo); |
480 | } | |
481 | } | |
482 | ||
483 | static void cpm_uart_set_termios(struct uart_port *port, | |
1bda8f30 SW |
484 | struct ktermios *termios, |
485 | struct ktermios *old) | |
1da177e4 LT |
486 | { |
487 | int baud; | |
488 | unsigned long flags; | |
489 | u16 cval, scval, prev_mode; | |
490 | int bits, sbits; | |
e789d268 FF |
491 | struct uart_cpm_port *pinfo = |
492 | container_of(port, struct uart_cpm_port, port); | |
c1dcfd9d SW |
493 | smc_t __iomem *smcp = pinfo->smcp; |
494 | scc_t __iomem *sccp = pinfo->sccp; | |
6e62bdc0 | 495 | int maxidl; |
1da177e4 LT |
496 | |
497 | pr_debug("CPM uart[%d]:set_termios\n", port->line); | |
498 | ||
499 | baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16); | |
59733ef7 | 500 | if (baud < HW_BUF_SPD_THRESHOLD || |
d6c53c0e | 501 | (pinfo->port.state && pinfo->port.state->port.low_latency)) |
5b04ec4a BI |
502 | pinfo->rx_fifosize = 1; |
503 | else | |
504 | pinfo->rx_fifosize = RX_BUF_SIZE; | |
1da177e4 | 505 | |
6e62bdc0 CL |
506 | /* MAXIDL is the timeout after which a receive buffer is closed |
507 | * when not full if no more characters are received. | |
508 | * We calculate it from the baudrate so that the duration is | |
509 | * always the same at standard rates: about 4ms. | |
510 | */ | |
511 | maxidl = baud / 2400; | |
512 | if (maxidl < 1) | |
513 | maxidl = 1; | |
514 | if (maxidl > 0x10) | |
515 | maxidl = 0x10; | |
516 | ||
1da177e4 LT |
517 | /* Character length programmed into the mode register is the |
518 | * sum of: 1 start bit, number of data bits, 0 or 1 parity bit, | |
519 | * 1 or 2 stop bits, minus 1. | |
520 | * The value 'bits' counts this for us. | |
521 | */ | |
522 | cval = 0; | |
523 | scval = 0; | |
524 | ||
525 | /* byte size */ | |
526 | switch (termios->c_cflag & CSIZE) { | |
527 | case CS5: | |
528 | bits = 5; | |
529 | break; | |
530 | case CS6: | |
531 | bits = 6; | |
532 | break; | |
533 | case CS7: | |
534 | bits = 7; | |
535 | break; | |
536 | case CS8: | |
537 | bits = 8; | |
538 | break; | |
539 | /* Never happens, but GCC is too dumb to figure it out */ | |
540 | default: | |
541 | bits = 8; | |
542 | break; | |
543 | } | |
544 | sbits = bits - 5; | |
545 | ||
546 | if (termios->c_cflag & CSTOPB) { | |
547 | cval |= SMCMR_SL; /* Two stops */ | |
548 | scval |= SCU_PSMR_SL; | |
549 | bits++; | |
550 | } | |
551 | ||
552 | if (termios->c_cflag & PARENB) { | |
553 | cval |= SMCMR_PEN; | |
554 | scval |= SCU_PSMR_PEN; | |
555 | bits++; | |
556 | if (!(termios->c_cflag & PARODD)) { | |
557 | cval |= SMCMR_PM_EVEN; | |
558 | scval |= (SCU_PSMR_REVP | SCU_PSMR_TEVP); | |
559 | } | |
560 | } | |
561 | ||
dc320815 LP |
562 | /* |
563 | * Update the timeout | |
564 | */ | |
565 | uart_update_timeout(port, termios->c_cflag, baud); | |
566 | ||
1da177e4 LT |
567 | /* |
568 | * Set up parity check flag | |
569 | */ | |
570 | #define RELEVANT_IFLAG(iflag) (iflag & (IGNBRK|BRKINT|IGNPAR|PARMRK|INPCK)) | |
571 | ||
572 | port->read_status_mask = (BD_SC_EMPTY | BD_SC_OV); | |
573 | if (termios->c_iflag & INPCK) | |
574 | port->read_status_mask |= BD_SC_FR | BD_SC_PR; | |
575 | if ((termios->c_iflag & BRKINT) || (termios->c_iflag & PARMRK)) | |
576 | port->read_status_mask |= BD_SC_BR; | |
577 | ||
578 | /* | |
579 | * Characters to ignore | |
580 | */ | |
581 | port->ignore_status_mask = 0; | |
582 | if (termios->c_iflag & IGNPAR) | |
583 | port->ignore_status_mask |= BD_SC_PR | BD_SC_FR; | |
584 | if (termios->c_iflag & IGNBRK) { | |
585 | port->ignore_status_mask |= BD_SC_BR; | |
586 | /* | |
587 | * If we're ignore parity and break indicators, ignore | |
588 | * overruns too. (For real raw support). | |
589 | */ | |
590 | if (termios->c_iflag & IGNPAR) | |
591 | port->ignore_status_mask |= BD_SC_OV; | |
592 | } | |
593 | /* | |
594 | * !!! ignore all characters if CREAD is not set | |
595 | */ | |
596 | if ((termios->c_cflag & CREAD) == 0) | |
597 | port->read_status_mask &= ~BD_SC_EMPTY; | |
311c4627 | 598 | |
1da177e4 LT |
599 | spin_lock_irqsave(&port->lock, flags); |
600 | ||
601 | /* Start bit has not been added (so don't, because we would just | |
602 | * subtract it later), and we need to add one for the number of | |
603 | * stops bits (there is always at least one). | |
604 | */ | |
605 | bits++; | |
606 | if (IS_SMC(pinfo)) { | |
5b04ec4a BI |
607 | /* |
608 | * MRBLR can be changed while an SMC/SCC is operating only | |
609 | * if it is done in a single bus cycle with one 16-bit move | |
610 | * (not two 8-bit bus cycles back-to-back). This occurs when | |
611 | * the cp shifts control to the next RxBD, so the change does | |
612 | * not take effect immediately. To guarantee the exact RxBD | |
613 | * on which the change occurs, change MRBLR only while the | |
614 | * SMC/SCC receiver is disabled. | |
615 | */ | |
616 | out_be16(&pinfo->smcup->smc_mrblr, pinfo->rx_fifosize); | |
6e62bdc0 | 617 | out_be16(&pinfo->smcup->smc_maxidl, maxidl); |
5b04ec4a | 618 | |
1da177e4 LT |
619 | /* Set the mode register. We want to keep a copy of the |
620 | * enables, because we want to put them back if they were | |
621 | * present. | |
622 | */ | |
ae2d4c39 NL |
623 | prev_mode = in_be16(&smcp->smc_smcmr) & (SMCMR_REN | SMCMR_TEN); |
624 | /* Output in *one* operation, so we don't interrupt RX/TX if they | |
625 | * were already enabled. */ | |
626 | out_be16(&smcp->smc_smcmr, smcr_mk_clen(bits) | cval | | |
627 | SMCMR_SM_UART | prev_mode); | |
1da177e4 | 628 | } else { |
5b04ec4a | 629 | out_be16(&pinfo->sccup->scc_genscc.scc_mrblr, pinfo->rx_fifosize); |
6e62bdc0 | 630 | out_be16(&pinfo->sccup->scc_maxidl, maxidl); |
c1dcfd9d | 631 | out_be16(&sccp->scc_psmr, (sbits << 12) | scval); |
1da177e4 LT |
632 | } |
633 | ||
80776554 LP |
634 | if (pinfo->clk) |
635 | clk_set_rate(pinfo->clk, baud); | |
636 | else | |
637 | cpm_set_brg(pinfo->brg - 1, baud); | |
1da177e4 | 638 | spin_unlock_irqrestore(&port->lock, flags); |
1da177e4 LT |
639 | } |
640 | ||
641 | static const char *cpm_uart_type(struct uart_port *port) | |
642 | { | |
643 | pr_debug("CPM uart[%d]:uart_type\n", port->line); | |
644 | ||
645 | return port->type == PORT_CPM ? "CPM UART" : NULL; | |
646 | } | |
647 | ||
648 | /* | |
649 | * verify the new serial_struct (for TIOCSSERIAL). | |
650 | */ | |
651 | static int cpm_uart_verify_port(struct uart_port *port, | |
652 | struct serial_struct *ser) | |
653 | { | |
654 | int ret = 0; | |
655 | ||
656 | pr_debug("CPM uart[%d]:verify_port\n", port->line); | |
657 | ||
658 | if (ser->type != PORT_UNKNOWN && ser->type != PORT_CPM) | |
659 | ret = -EINVAL; | |
a62c4133 | 660 | if (ser->irq < 0 || ser->irq >= nr_irqs) |
1da177e4 LT |
661 | ret = -EINVAL; |
662 | if (ser->baud_base < 9600) | |
663 | ret = -EINVAL; | |
664 | return ret; | |
665 | } | |
666 | ||
667 | /* | |
668 | * Transmit characters, refill buffer descriptor, if possible | |
669 | */ | |
670 | static int cpm_uart_tx_pump(struct uart_port *port) | |
671 | { | |
c1dcfd9d SW |
672 | cbd_t __iomem *bdp; |
673 | u8 *p; | |
1da177e4 | 674 | int count; |
e789d268 FF |
675 | struct uart_cpm_port *pinfo = |
676 | container_of(port, struct uart_cpm_port, port); | |
09dd3fc1 | 677 | struct circ_buf *xmit = &port->state->xmit; |
1da177e4 LT |
678 | |
679 | /* Handle xon/xoff */ | |
680 | if (port->x_char) { | |
681 | /* Pick next descriptor and fill from buffer */ | |
682 | bdp = pinfo->tx_cur; | |
683 | ||
c1dcfd9d | 684 | p = cpm2cpu_addr(in_be32(&bdp->cbd_bufaddr), pinfo); |
311c4627 | 685 | |
03929c76 | 686 | *p++ = port->x_char; |
c1dcfd9d SW |
687 | |
688 | out_be16(&bdp->cbd_datlen, 1); | |
689 | setbits16(&bdp->cbd_sc, BD_SC_READY); | |
1da177e4 | 690 | /* Get next BD. */ |
c1dcfd9d | 691 | if (in_be16(&bdp->cbd_sc) & BD_SC_WRAP) |
1da177e4 LT |
692 | bdp = pinfo->tx_bd_base; |
693 | else | |
694 | bdp++; | |
695 | pinfo->tx_cur = bdp; | |
696 | ||
697 | port->icount.tx++; | |
698 | port->x_char = 0; | |
699 | return 1; | |
700 | } | |
701 | ||
702 | if (uart_circ_empty(xmit) || uart_tx_stopped(port)) { | |
b129a8cc | 703 | cpm_uart_stop_tx(port); |
1da177e4 LT |
704 | return 0; |
705 | } | |
706 | ||
707 | /* Pick next descriptor and fill from buffer */ | |
708 | bdp = pinfo->tx_cur; | |
709 | ||
c1dcfd9d SW |
710 | while (!(in_be16(&bdp->cbd_sc) & BD_SC_READY) && |
711 | xmit->tail != xmit->head) { | |
1da177e4 | 712 | count = 0; |
c1dcfd9d | 713 | p = cpm2cpu_addr(in_be32(&bdp->cbd_bufaddr), pinfo); |
1da177e4 LT |
714 | while (count < pinfo->tx_fifosize) { |
715 | *p++ = xmit->buf[xmit->tail]; | |
716 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); | |
717 | port->icount.tx++; | |
718 | count++; | |
719 | if (xmit->head == xmit->tail) | |
720 | break; | |
721 | } | |
c1dcfd9d SW |
722 | out_be16(&bdp->cbd_datlen, count); |
723 | setbits16(&bdp->cbd_sc, BD_SC_READY); | |
1da177e4 | 724 | /* Get next BD. */ |
c1dcfd9d | 725 | if (in_be16(&bdp->cbd_sc) & BD_SC_WRAP) |
1da177e4 LT |
726 | bdp = pinfo->tx_bd_base; |
727 | else | |
728 | bdp++; | |
729 | } | |
730 | pinfo->tx_cur = bdp; | |
731 | ||
732 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
733 | uart_write_wakeup(port); | |
734 | ||
735 | if (uart_circ_empty(xmit)) { | |
b129a8cc | 736 | cpm_uart_stop_tx(port); |
1da177e4 LT |
737 | return 0; |
738 | } | |
739 | ||
740 | return 1; | |
741 | } | |
742 | ||
743 | /* | |
744 | * init buffer descriptors | |
745 | */ | |
746 | static void cpm_uart_initbd(struct uart_cpm_port *pinfo) | |
747 | { | |
748 | int i; | |
749 | u8 *mem_addr; | |
c1dcfd9d | 750 | cbd_t __iomem *bdp; |
1da177e4 LT |
751 | |
752 | pr_debug("CPM uart[%d]:initbd\n", pinfo->port.line); | |
753 | ||
754 | /* Set the physical address of the host memory | |
755 | * buffers in the buffer descriptors, and the | |
756 | * virtual address for us to work with. | |
757 | */ | |
758 | mem_addr = pinfo->mem_addr; | |
759 | bdp = pinfo->rx_cur = pinfo->rx_bd_base; | |
760 | for (i = 0; i < (pinfo->rx_nrfifos - 1); i++, bdp++) { | |
c1dcfd9d SW |
761 | out_be32(&bdp->cbd_bufaddr, cpu2cpm_addr(mem_addr, pinfo)); |
762 | out_be16(&bdp->cbd_sc, BD_SC_EMPTY | BD_SC_INTRPT); | |
1da177e4 LT |
763 | mem_addr += pinfo->rx_fifosize; |
764 | } | |
311c4627 | 765 | |
c1dcfd9d SW |
766 | out_be32(&bdp->cbd_bufaddr, cpu2cpm_addr(mem_addr, pinfo)); |
767 | out_be16(&bdp->cbd_sc, BD_SC_WRAP | BD_SC_EMPTY | BD_SC_INTRPT); | |
1da177e4 LT |
768 | |
769 | /* Set the physical address of the host memory | |
770 | * buffers in the buffer descriptors, and the | |
771 | * virtual address for us to work with. | |
772 | */ | |
773 | mem_addr = pinfo->mem_addr + L1_CACHE_ALIGN(pinfo->rx_nrfifos * pinfo->rx_fifosize); | |
774 | bdp = pinfo->tx_cur = pinfo->tx_bd_base; | |
775 | for (i = 0; i < (pinfo->tx_nrfifos - 1); i++, bdp++) { | |
c1dcfd9d SW |
776 | out_be32(&bdp->cbd_bufaddr, cpu2cpm_addr(mem_addr, pinfo)); |
777 | out_be16(&bdp->cbd_sc, BD_SC_INTRPT); | |
1da177e4 LT |
778 | mem_addr += pinfo->tx_fifosize; |
779 | } | |
311c4627 | 780 | |
c1dcfd9d SW |
781 | out_be32(&bdp->cbd_bufaddr, cpu2cpm_addr(mem_addr, pinfo)); |
782 | out_be16(&bdp->cbd_sc, BD_SC_WRAP | BD_SC_INTRPT); | |
1da177e4 LT |
783 | } |
784 | ||
785 | static void cpm_uart_init_scc(struct uart_cpm_port *pinfo) | |
786 | { | |
c1dcfd9d SW |
787 | scc_t __iomem *scp; |
788 | scc_uart_t __iomem *sup; | |
1da177e4 LT |
789 | |
790 | pr_debug("CPM uart[%d]:init_scc\n", pinfo->port.line); | |
791 | ||
792 | scp = pinfo->sccp; | |
793 | sup = pinfo->sccup; | |
794 | ||
795 | /* Store address */ | |
c1dcfd9d SW |
796 | out_be16(&pinfo->sccup->scc_genscc.scc_rbase, |
797 | (u8 __iomem *)pinfo->rx_bd_base - DPRAM_BASE); | |
798 | out_be16(&pinfo->sccup->scc_genscc.scc_tbase, | |
799 | (u8 __iomem *)pinfo->tx_bd_base - DPRAM_BASE); | |
1da177e4 LT |
800 | |
801 | /* Set up the uart parameters in the | |
802 | * parameter ram. | |
803 | */ | |
804 | ||
805 | cpm_set_scc_fcr(sup); | |
806 | ||
c1dcfd9d | 807 | out_be16(&sup->scc_genscc.scc_mrblr, pinfo->rx_fifosize); |
fbbb9d96 | 808 | out_be16(&sup->scc_maxidl, 0x10); |
c1dcfd9d SW |
809 | out_be16(&sup->scc_brkcr, 1); |
810 | out_be16(&sup->scc_parec, 0); | |
811 | out_be16(&sup->scc_frmec, 0); | |
812 | out_be16(&sup->scc_nosec, 0); | |
813 | out_be16(&sup->scc_brkec, 0); | |
814 | out_be16(&sup->scc_uaddr1, 0); | |
815 | out_be16(&sup->scc_uaddr2, 0); | |
816 | out_be16(&sup->scc_toseq, 0); | |
817 | out_be16(&sup->scc_char1, 0x8000); | |
818 | out_be16(&sup->scc_char2, 0x8000); | |
819 | out_be16(&sup->scc_char3, 0x8000); | |
820 | out_be16(&sup->scc_char4, 0x8000); | |
821 | out_be16(&sup->scc_char5, 0x8000); | |
822 | out_be16(&sup->scc_char6, 0x8000); | |
823 | out_be16(&sup->scc_char7, 0x8000); | |
824 | out_be16(&sup->scc_char8, 0x8000); | |
825 | out_be16(&sup->scc_rccm, 0xc0ff); | |
1da177e4 LT |
826 | |
827 | /* Send the CPM an initialize command. | |
828 | */ | |
7ae87036 | 829 | cpm_line_cr_cmd(pinfo, CPM_CR_INIT_TRX); |
1da177e4 LT |
830 | |
831 | /* Set UART mode, 8 bit, no parity, one stop. | |
832 | * Enable receive and transmit. | |
833 | */ | |
c1dcfd9d SW |
834 | out_be32(&scp->scc_gsmrh, 0); |
835 | out_be32(&scp->scc_gsmrl, | |
836 | SCC_GSMRL_MODE_UART | SCC_GSMRL_TDCR_16 | SCC_GSMRL_RDCR_16); | |
1da177e4 LT |
837 | |
838 | /* Enable rx interrupts and clear all pending events. */ | |
c1dcfd9d SW |
839 | out_be16(&scp->scc_sccm, 0); |
840 | out_be16(&scp->scc_scce, 0xffff); | |
841 | out_be16(&scp->scc_dsr, 0x7e7e); | |
842 | out_be16(&scp->scc_psmr, 0x3000); | |
1da177e4 | 843 | |
c1dcfd9d | 844 | setbits32(&scp->scc_gsmrl, SCC_GSMRL_ENR | SCC_GSMRL_ENT); |
1da177e4 LT |
845 | } |
846 | ||
847 | static void cpm_uart_init_smc(struct uart_cpm_port *pinfo) | |
848 | { | |
c1dcfd9d SW |
849 | smc_t __iomem *sp; |
850 | smc_uart_t __iomem *up; | |
1da177e4 LT |
851 | |
852 | pr_debug("CPM uart[%d]:init_smc\n", pinfo->port.line); | |
853 | ||
854 | sp = pinfo->smcp; | |
855 | up = pinfo->smcup; | |
856 | ||
857 | /* Store address */ | |
c1dcfd9d SW |
858 | out_be16(&pinfo->smcup->smc_rbase, |
859 | (u8 __iomem *)pinfo->rx_bd_base - DPRAM_BASE); | |
860 | out_be16(&pinfo->smcup->smc_tbase, | |
861 | (u8 __iomem *)pinfo->tx_bd_base - DPRAM_BASE); | |
1da177e4 LT |
862 | |
863 | /* | |
864 | * In case SMC1 is being relocated... | |
865 | */ | |
866 | #if defined (CONFIG_I2C_SPI_SMC1_UCODE_PATCH) | |
c1dcfd9d SW |
867 | out_be16(&up->smc_rbptr, in_be16(&pinfo->smcup->smc_rbase)); |
868 | out_be16(&up->smc_tbptr, in_be16(&pinfo->smcup->smc_tbase)); | |
869 | out_be32(&up->smc_rstate, 0); | |
870 | out_be32(&up->smc_tstate, 0); | |
871 | out_be16(&up->smc_brkcr, 1); /* number of break chars */ | |
872 | out_be16(&up->smc_brkec, 0); | |
1da177e4 LT |
873 | #endif |
874 | ||
875 | /* Set up the uart parameters in the | |
876 | * parameter ram. | |
877 | */ | |
878 | cpm_set_smc_fcr(up); | |
879 | ||
b770ffd4 | 880 | /* Using idle character time requires some additional tuning. */ |
c1dcfd9d | 881 | out_be16(&up->smc_mrblr, pinfo->rx_fifosize); |
fbbb9d96 | 882 | out_be16(&up->smc_maxidl, 0x10); |
c1dcfd9d SW |
883 | out_be16(&up->smc_brklen, 0); |
884 | out_be16(&up->smc_brkec, 0); | |
885 | out_be16(&up->smc_brkcr, 1); | |
1da177e4 | 886 | |
7ae87036 | 887 | cpm_line_cr_cmd(pinfo, CPM_CR_INIT_TRX); |
1da177e4 LT |
888 | |
889 | /* Set UART mode, 8 bit, no parity, one stop. | |
890 | * Enable receive and transmit. | |
891 | */ | |
c1dcfd9d | 892 | out_be16(&sp->smc_smcmr, smcr_mk_clen(9) | SMCMR_SM_UART); |
1da177e4 LT |
893 | |
894 | /* Enable only rx interrupts clear all pending events. */ | |
c1dcfd9d SW |
895 | out_8(&sp->smc_smcm, 0); |
896 | out_8(&sp->smc_smce, 0xff); | |
1da177e4 | 897 | |
c1dcfd9d | 898 | setbits16(&sp->smc_smcmr, SMCMR_REN | SMCMR_TEN); |
1da177e4 LT |
899 | } |
900 | ||
901 | /* | |
902 | * Initialize port. This is called from early_console stuff | |
903 | * so we have to be careful here ! | |
904 | */ | |
905 | static int cpm_uart_request_port(struct uart_port *port) | |
906 | { | |
e789d268 FF |
907 | struct uart_cpm_port *pinfo = |
908 | container_of(port, struct uart_cpm_port, port); | |
1da177e4 LT |
909 | int ret; |
910 | ||
911 | pr_debug("CPM uart[%d]:request port\n", port->line); | |
912 | ||
913 | if (pinfo->flags & FLAG_CONSOLE) | |
914 | return 0; | |
915 | ||
1da177e4 | 916 | if (IS_SMC(pinfo)) { |
c1dcfd9d SW |
917 | clrbits8(&pinfo->smcp->smc_smcm, SMCM_RX | SMCM_TX); |
918 | clrbits16(&pinfo->smcp->smc_smcmr, SMCMR_REN | SMCMR_TEN); | |
1da177e4 | 919 | } else { |
c1dcfd9d SW |
920 | clrbits16(&pinfo->sccp->scc_sccm, UART_SCCM_TX | UART_SCCM_RX); |
921 | clrbits32(&pinfo->sccp->scc_gsmrl, SCC_GSMRL_ENR | SCC_GSMRL_ENT); | |
1da177e4 LT |
922 | } |
923 | ||
924 | ret = cpm_uart_allocbuf(pinfo, 0); | |
925 | ||
926 | if (ret) | |
927 | return ret; | |
928 | ||
929 | cpm_uart_initbd(pinfo); | |
311c4627 KG |
930 | if (IS_SMC(pinfo)) |
931 | cpm_uart_init_smc(pinfo); | |
932 | else | |
933 | cpm_uart_init_scc(pinfo); | |
1da177e4 LT |
934 | |
935 | return 0; | |
936 | } | |
937 | ||
938 | static void cpm_uart_release_port(struct uart_port *port) | |
939 | { | |
e789d268 FF |
940 | struct uart_cpm_port *pinfo = |
941 | container_of(port, struct uart_cpm_port, port); | |
1da177e4 LT |
942 | |
943 | if (!(pinfo->flags & FLAG_CONSOLE)) | |
944 | cpm_uart_freebuf(pinfo); | |
945 | } | |
946 | ||
947 | /* | |
948 | * Configure/autoconfigure the port. | |
949 | */ | |
950 | static void cpm_uart_config_port(struct uart_port *port, int flags) | |
951 | { | |
952 | pr_debug("CPM uart[%d]:config_port\n", port->line); | |
953 | ||
954 | if (flags & UART_CONFIG_TYPE) { | |
955 | port->type = PORT_CPM; | |
956 | cpm_uart_request_port(port); | |
957 | } | |
958 | } | |
8e21d04c | 959 | |
8cd774ad DD |
960 | #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_CPM_CONSOLE) |
961 | /* | |
962 | * Write a string to the serial port | |
963 | * Note that this is called with interrupts already disabled | |
964 | */ | |
965 | static void cpm_uart_early_write(struct uart_cpm_port *pinfo, | |
2fe686eb | 966 | const char *string, u_int count, bool handle_linefeed) |
8cd774ad DD |
967 | { |
968 | unsigned int i; | |
969 | cbd_t __iomem *bdp, *bdbase; | |
970 | unsigned char *cpm_outp_addr; | |
971 | ||
972 | /* Get the address of the host memory buffer. | |
973 | */ | |
974 | bdp = pinfo->tx_cur; | |
975 | bdbase = pinfo->tx_bd_base; | |
976 | ||
977 | /* | |
978 | * Now, do each character. This is not as bad as it looks | |
979 | * since this is a holding FIFO and not a transmitting FIFO. | |
980 | * We could add the complexity of filling the entire transmit | |
981 | * buffer, but we would just wait longer between accesses...... | |
982 | */ | |
983 | for (i = 0; i < count; i++, string++) { | |
984 | /* Wait for transmitter fifo to empty. | |
985 | * Ready indicates output is ready, and xmt is doing | |
986 | * that, not that it is ready for us to send. | |
987 | */ | |
988 | while ((in_be16(&bdp->cbd_sc) & BD_SC_READY) != 0) | |
989 | ; | |
990 | ||
991 | /* Send the character out. | |
992 | * If the buffer address is in the CPM DPRAM, don't | |
993 | * convert it. | |
994 | */ | |
995 | cpm_outp_addr = cpm2cpu_addr(in_be32(&bdp->cbd_bufaddr), | |
996 | pinfo); | |
997 | *cpm_outp_addr = *string; | |
998 | ||
999 | out_be16(&bdp->cbd_datlen, 1); | |
1000 | setbits16(&bdp->cbd_sc, BD_SC_READY); | |
1001 | ||
1002 | if (in_be16(&bdp->cbd_sc) & BD_SC_WRAP) | |
1003 | bdp = bdbase; | |
1004 | else | |
1005 | bdp++; | |
1006 | ||
1007 | /* if a LF, also do CR... */ | |
2fe686eb | 1008 | if (handle_linefeed && *string == 10) { |
8cd774ad DD |
1009 | while ((in_be16(&bdp->cbd_sc) & BD_SC_READY) != 0) |
1010 | ; | |
1011 | ||
1012 | cpm_outp_addr = cpm2cpu_addr(in_be32(&bdp->cbd_bufaddr), | |
1013 | pinfo); | |
1014 | *cpm_outp_addr = 13; | |
1015 | ||
1016 | out_be16(&bdp->cbd_datlen, 1); | |
1017 | setbits16(&bdp->cbd_sc, BD_SC_READY); | |
1018 | ||
1019 | if (in_be16(&bdp->cbd_sc) & BD_SC_WRAP) | |
1020 | bdp = bdbase; | |
1021 | else | |
1022 | bdp++; | |
1023 | } | |
1024 | } | |
1025 | ||
1026 | /* | |
1027 | * Finally, Wait for transmitter & holding register to empty | |
1028 | * and restore the IER | |
1029 | */ | |
1030 | while ((in_be16(&bdp->cbd_sc) & BD_SC_READY) != 0) | |
1031 | ; | |
1032 | ||
1033 | pinfo->tx_cur = bdp; | |
1034 | } | |
1035 | #endif | |
1036 | ||
8e21d04c JW |
1037 | #ifdef CONFIG_CONSOLE_POLL |
1038 | /* Serial polling routines for writing and reading from the uart while | |
1039 | * in an interrupt or debug context. | |
1040 | */ | |
1041 | ||
1042 | #define GDB_BUF_SIZE 512 /* power of 2, please */ | |
1043 | ||
1044 | static char poll_buf[GDB_BUF_SIZE]; | |
1045 | static char *pollp; | |
1046 | static int poll_chars; | |
1047 | ||
1048 | static int poll_wait_key(char *obuf, struct uart_cpm_port *pinfo) | |
1049 | { | |
1050 | u_char c, *cp; | |
1051 | volatile cbd_t *bdp; | |
1052 | int i; | |
1053 | ||
1054 | /* Get the address of the host memory buffer. | |
1055 | */ | |
1056 | bdp = pinfo->rx_cur; | |
be28c1e3 CL |
1057 | if (bdp->cbd_sc & BD_SC_EMPTY) |
1058 | return NO_POLL_CHAR; | |
8e21d04c JW |
1059 | |
1060 | /* If the buffer address is in the CPM DPRAM, don't | |
1061 | * convert it. | |
1062 | */ | |
1063 | cp = cpm2cpu_addr(bdp->cbd_bufaddr, pinfo); | |
1064 | ||
1065 | if (obuf) { | |
1066 | i = c = bdp->cbd_datlen; | |
1067 | while (i-- > 0) | |
1068 | *obuf++ = *cp++; | |
1069 | } else | |
1070 | c = *cp; | |
1071 | bdp->cbd_sc &= ~(BD_SC_BR | BD_SC_FR | BD_SC_PR | BD_SC_OV | BD_SC_ID); | |
1072 | bdp->cbd_sc |= BD_SC_EMPTY; | |
1073 | ||
1074 | if (bdp->cbd_sc & BD_SC_WRAP) | |
1075 | bdp = pinfo->rx_bd_base; | |
1076 | else | |
1077 | bdp++; | |
1078 | pinfo->rx_cur = (cbd_t *)bdp; | |
1079 | ||
1080 | return (int)c; | |
1081 | } | |
1082 | ||
1083 | static int cpm_get_poll_char(struct uart_port *port) | |
1084 | { | |
e789d268 FF |
1085 | struct uart_cpm_port *pinfo = |
1086 | container_of(port, struct uart_cpm_port, port); | |
8e21d04c JW |
1087 | |
1088 | if (!serial_polled) { | |
1089 | serial_polled = 1; | |
1090 | poll_chars = 0; | |
1091 | } | |
1092 | if (poll_chars <= 0) { | |
be28c1e3 CL |
1093 | int ret = poll_wait_key(poll_buf, pinfo); |
1094 | ||
1095 | if (ret == NO_POLL_CHAR) | |
1096 | return ret; | |
1097 | poll_chars = ret; | |
8e21d04c JW |
1098 | pollp = poll_buf; |
1099 | } | |
1100 | poll_chars--; | |
1101 | return *pollp++; | |
1102 | } | |
1103 | ||
1104 | static void cpm_put_poll_char(struct uart_port *port, | |
1105 | unsigned char c) | |
1106 | { | |
e789d268 FF |
1107 | struct uart_cpm_port *pinfo = |
1108 | container_of(port, struct uart_cpm_port, port); | |
8e21d04c JW |
1109 | static char ch[2]; |
1110 | ||
1111 | ch[0] = (char)c; | |
2fe686eb | 1112 | cpm_uart_early_write(pinfo, ch, 1, false); |
8e21d04c JW |
1113 | } |
1114 | #endif /* CONFIG_CONSOLE_POLL */ | |
1115 | ||
5848eeae | 1116 | static const struct uart_ops cpm_uart_pops = { |
1da177e4 LT |
1117 | .tx_empty = cpm_uart_tx_empty, |
1118 | .set_mctrl = cpm_uart_set_mctrl, | |
1119 | .get_mctrl = cpm_uart_get_mctrl, | |
1120 | .stop_tx = cpm_uart_stop_tx, | |
1121 | .start_tx = cpm_uart_start_tx, | |
1122 | .stop_rx = cpm_uart_stop_rx, | |
1da177e4 LT |
1123 | .break_ctl = cpm_uart_break_ctl, |
1124 | .startup = cpm_uart_startup, | |
1125 | .shutdown = cpm_uart_shutdown, | |
1126 | .set_termios = cpm_uart_set_termios, | |
1127 | .type = cpm_uart_type, | |
1128 | .release_port = cpm_uart_release_port, | |
1129 | .request_port = cpm_uart_request_port, | |
1130 | .config_port = cpm_uart_config_port, | |
1131 | .verify_port = cpm_uart_verify_port, | |
8e21d04c JW |
1132 | #ifdef CONFIG_CONSOLE_POLL |
1133 | .poll_get_char = cpm_get_poll_char, | |
1134 | .poll_put_char = cpm_put_poll_char, | |
1135 | #endif | |
1da177e4 LT |
1136 | }; |
1137 | ||
7ae87036 SW |
1138 | struct uart_cpm_port cpm_uart_ports[UART_NR]; |
1139 | ||
c1dcfd9d SW |
1140 | static int cpm_uart_init_port(struct device_node *np, |
1141 | struct uart_cpm_port *pinfo) | |
7ae87036 SW |
1142 | { |
1143 | const u32 *data; | |
c1dcfd9d | 1144 | void __iomem *mem, *pram; |
7ae87036 SW |
1145 | int len; |
1146 | int ret; | |
7485d26b | 1147 | int i; |
7ae87036 | 1148 | |
80776554 LP |
1149 | data = of_get_property(np, "clock", NULL); |
1150 | if (data) { | |
1151 | struct clk *clk = clk_get(NULL, (const char*)data); | |
1152 | if (!IS_ERR(clk)) | |
1153 | pinfo->clk = clk; | |
1154 | } | |
1155 | if (!pinfo->clk) { | |
1156 | data = of_get_property(np, "fsl,cpm-brg", &len); | |
1157 | if (!data || len != 4) { | |
fff10721 RH |
1158 | printk(KERN_ERR "CPM UART %pOFn has no/invalid " |
1159 | "fsl,cpm-brg property.\n", np); | |
80776554 LP |
1160 | return -EINVAL; |
1161 | } | |
1162 | pinfo->brg = *data; | |
7ae87036 | 1163 | } |
7ae87036 SW |
1164 | |
1165 | data = of_get_property(np, "fsl,cpm-command", &len); | |
1166 | if (!data || len != 4) { | |
fff10721 RH |
1167 | printk(KERN_ERR "CPM UART %pOFn has no/invalid " |
1168 | "fsl,cpm-command property.\n", np); | |
7ae87036 SW |
1169 | return -EINVAL; |
1170 | } | |
1171 | pinfo->command = *data; | |
1172 | ||
1173 | mem = of_iomap(np, 0); | |
1174 | if (!mem) | |
1175 | return -ENOMEM; | |
1176 | ||
7ae87036 SW |
1177 | if (of_device_is_compatible(np, "fsl,cpm1-scc-uart") || |
1178 | of_device_is_compatible(np, "fsl,cpm2-scc-uart")) { | |
1179 | pinfo->sccp = mem; | |
d464df26 | 1180 | pinfo->sccup = pram = cpm_uart_map_pram(pinfo, np); |
7ae87036 SW |
1181 | } else if (of_device_is_compatible(np, "fsl,cpm1-smc-uart") || |
1182 | of_device_is_compatible(np, "fsl,cpm2-smc-uart")) { | |
1183 | pinfo->flags |= FLAG_SMC; | |
1184 | pinfo->smcp = mem; | |
d464df26 | 1185 | pinfo->smcup = pram = cpm_uart_map_pram(pinfo, np); |
7ae87036 SW |
1186 | } else { |
1187 | ret = -ENODEV; | |
d464df26 LP |
1188 | goto out_mem; |
1189 | } | |
1190 | ||
1191 | if (!pram) { | |
1192 | ret = -ENOMEM; | |
1193 | goto out_mem; | |
7ae87036 SW |
1194 | } |
1195 | ||
1196 | pinfo->tx_nrfifos = TX_NUM_FIFO; | |
1197 | pinfo->tx_fifosize = TX_BUF_SIZE; | |
1198 | pinfo->rx_nrfifos = RX_NUM_FIFO; | |
1199 | pinfo->rx_fifosize = RX_BUF_SIZE; | |
1200 | ||
1201 | pinfo->port.uartclk = ppc_proc_freq; | |
1202 | pinfo->port.mapbase = (unsigned long)mem; | |
1203 | pinfo->port.type = PORT_CPM; | |
1204 | pinfo->port.ops = &cpm_uart_pops, | |
1205 | pinfo->port.iotype = UPIO_MEM; | |
dc320815 | 1206 | pinfo->port.fifosize = pinfo->tx_nrfifos * pinfo->tx_fifosize; |
7ae87036 SW |
1207 | spin_lock_init(&pinfo->port.lock); |
1208 | ||
f7578496 | 1209 | pinfo->port.irq = irq_of_parse_and_map(np, 0); |
7ae87036 SW |
1210 | if (pinfo->port.irq == NO_IRQ) { |
1211 | ret = -EINVAL; | |
1212 | goto out_pram; | |
1213 | } | |
1214 | ||
a416bfa2 CL |
1215 | for (i = 0; i < NUM_GPIOS; i++) { |
1216 | int gpio; | |
1217 | ||
1218 | pinfo->gpios[i] = -1; | |
1219 | ||
1220 | gpio = of_get_gpio(np, i); | |
1221 | ||
1222 | if (gpio_is_valid(gpio)) { | |
1223 | ret = gpio_request(gpio, "cpm_uart"); | |
1224 | if (ret) { | |
1225 | pr_err("can't request gpio #%d: %d\n", i, ret); | |
1226 | continue; | |
1227 | } | |
1228 | if (i == GPIO_RTS || i == GPIO_DTR) | |
1229 | ret = gpio_direction_output(gpio, 0); | |
1230 | else | |
1231 | ret = gpio_direction_input(gpio); | |
1232 | if (ret) { | |
1233 | pr_err("can't set direction for gpio #%d: %d\n", | |
1234 | i, ret); | |
1235 | gpio_free(gpio); | |
1236 | continue; | |
1237 | } | |
1238 | pinfo->gpios[i] = gpio; | |
1239 | } | |
1240 | } | |
7485d26b | 1241 | |
4d8107f4 SW |
1242 | #ifdef CONFIG_PPC_EARLY_DEBUG_CPM |
1243 | udbg_putc = NULL; | |
1244 | #endif | |
1245 | ||
7ae87036 SW |
1246 | return cpm_uart_request_port(&pinfo->port); |
1247 | ||
1248 | out_pram: | |
d464df26 | 1249 | cpm_uart_unmap_pram(pinfo, pram); |
7ae87036 SW |
1250 | out_mem: |
1251 | iounmap(mem); | |
1252 | return ret; | |
1253 | } | |
1254 | ||
1da177e4 LT |
1255 | #ifdef CONFIG_SERIAL_CPM_CONSOLE |
1256 | /* | |
1257 | * Print a string to the serial port trying not to disturb | |
1258 | * any possible real use of the port... | |
1259 | * | |
1260 | * Note that this is called with interrupts already disabled | |
1261 | */ | |
1262 | static void cpm_uart_console_write(struct console *co, const char *s, | |
1263 | u_int count) | |
1264 | { | |
7ae87036 | 1265 | struct uart_cpm_port *pinfo = &cpm_uart_ports[co->index]; |
491a7a43 RT |
1266 | unsigned long flags; |
1267 | int nolock = oops_in_progress; | |
1268 | ||
1269 | if (unlikely(nolock)) { | |
1270 | local_irq_save(flags); | |
1271 | } else { | |
1272 | spin_lock_irqsave(&pinfo->port.lock, flags); | |
1273 | } | |
1da177e4 | 1274 | |
2fe686eb | 1275 | cpm_uart_early_write(pinfo, s, count, true); |
491a7a43 RT |
1276 | |
1277 | if (unlikely(nolock)) { | |
1278 | local_irq_restore(flags); | |
1279 | } else { | |
1280 | spin_unlock_irqrestore(&pinfo->port.lock, flags); | |
1281 | } | |
1da177e4 LT |
1282 | } |
1283 | ||
e27987cd | 1284 | |
1da177e4 LT |
1285 | static int __init cpm_uart_console_setup(struct console *co, char *options) |
1286 | { | |
1da177e4 LT |
1287 | int baud = 38400; |
1288 | int bits = 8; | |
1289 | int parity = 'n'; | |
1290 | int flow = 'n'; | |
1291 | int ret; | |
7ae87036 SW |
1292 | struct uart_cpm_port *pinfo; |
1293 | struct uart_port *port; | |
1294 | ||
0832a462 | 1295 | struct device_node *np; |
7ae87036 SW |
1296 | int i = 0; |
1297 | ||
1298 | if (co->index >= UART_NR) { | |
1299 | printk(KERN_ERR "cpm_uart: console index %d too high\n", | |
1300 | co->index); | |
1301 | return -ENODEV; | |
1302 | } | |
1303 | ||
0832a462 | 1304 | for_each_node_by_type(np, "serial") { |
7ae87036 SW |
1305 | if (!of_device_is_compatible(np, "fsl,cpm1-smc-uart") && |
1306 | !of_device_is_compatible(np, "fsl,cpm1-scc-uart") && | |
1307 | !of_device_is_compatible(np, "fsl,cpm2-smc-uart") && | |
1308 | !of_device_is_compatible(np, "fsl,cpm2-scc-uart")) | |
0832a462 DT |
1309 | continue; |
1310 | ||
1311 | if (i++ == co->index) | |
1312 | break; | |
1313 | } | |
1314 | ||
1315 | if (!np) | |
1316 | return -ENODEV; | |
7ae87036 SW |
1317 | |
1318 | pinfo = &cpm_uart_ports[co->index]; | |
1319 | ||
1320 | pinfo->flags |= FLAG_CONSOLE; | |
1321 | port = &pinfo->port; | |
1322 | ||
1323 | ret = cpm_uart_init_port(np, pinfo); | |
1324 | of_node_put(np); | |
1325 | if (ret) | |
1326 | return ret; | |
1327 | ||
1da177e4 LT |
1328 | if (options) { |
1329 | uart_parse_options(options, &baud, &parity, &bits, &flow); | |
1330 | } else { | |
3dd0dcbe | 1331 | if ((baud = uart_baudrate()) == -1) |
1da177e4 LT |
1332 | baud = 9600; |
1333 | } | |
1334 | ||
1da177e4 | 1335 | if (IS_SMC(pinfo)) { |
ae2d4c39 NL |
1336 | out_be16(&pinfo->smcup->smc_brkcr, 0); |
1337 | cpm_line_cr_cmd(pinfo, CPM_CR_STOP_TX); | |
c1dcfd9d SW |
1338 | clrbits8(&pinfo->smcp->smc_smcm, SMCM_RX | SMCM_TX); |
1339 | clrbits16(&pinfo->smcp->smc_smcmr, SMCMR_REN | SMCMR_TEN); | |
1da177e4 | 1340 | } else { |
ae2d4c39 NL |
1341 | out_be16(&pinfo->sccup->scc_brkcr, 0); |
1342 | cpm_line_cr_cmd(pinfo, CPM_CR_GRA_STOP_TX); | |
c1dcfd9d SW |
1343 | clrbits16(&pinfo->sccp->scc_sccm, UART_SCCM_TX | UART_SCCM_RX); |
1344 | clrbits32(&pinfo->sccp->scc_gsmrl, SCC_GSMRL_ENR | SCC_GSMRL_ENT); | |
1da177e4 LT |
1345 | } |
1346 | ||
1347 | ret = cpm_uart_allocbuf(pinfo, 1); | |
1348 | ||
1349 | if (ret) | |
1350 | return ret; | |
1351 | ||
1352 | cpm_uart_initbd(pinfo); | |
1353 | ||
1354 | if (IS_SMC(pinfo)) | |
1355 | cpm_uart_init_smc(pinfo); | |
1356 | else | |
1357 | cpm_uart_init_scc(pinfo); | |
1358 | ||
1359 | uart_set_options(port, co, baud, parity, bits, flow); | |
d948a29e | 1360 | cpm_line_cr_cmd(pinfo, CPM_CR_RESTART_TX); |
1da177e4 LT |
1361 | |
1362 | return 0; | |
1363 | } | |
1364 | ||
36d2f5a1 | 1365 | static struct uart_driver cpm_reg; |
1da177e4 | 1366 | static struct console cpm_scc_uart_console = { |
36d2f5a1 KG |
1367 | .name = "ttyCPM", |
1368 | .write = cpm_uart_console_write, | |
1369 | .device = uart_console_device, | |
1370 | .setup = cpm_uart_console_setup, | |
1371 | .flags = CON_PRINTBUFFER, | |
1372 | .index = -1, | |
1da177e4 LT |
1373 | .data = &cpm_reg, |
1374 | }; | |
1375 | ||
c1dcfd9d | 1376 | static int __init cpm_uart_console_init(void) |
1da177e4 | 1377 | { |
e27987cd VB |
1378 | register_console(&cpm_scc_uart_console); |
1379 | return 0; | |
1da177e4 LT |
1380 | } |
1381 | ||
1382 | console_initcall(cpm_uart_console_init); | |
1383 | ||
1384 | #define CPM_UART_CONSOLE &cpm_scc_uart_console | |
1385 | #else | |
1386 | #define CPM_UART_CONSOLE NULL | |
1387 | #endif | |
1388 | ||
1389 | static struct uart_driver cpm_reg = { | |
1390 | .owner = THIS_MODULE, | |
1391 | .driver_name = "ttyCPM", | |
1392 | .dev_name = "ttyCPM", | |
1393 | .major = SERIAL_CPM_MAJOR, | |
1394 | .minor = SERIAL_CPM_MINOR, | |
1395 | .cons = CPM_UART_CONSOLE, | |
7ae87036 SW |
1396 | .nr = UART_NR, |
1397 | }; | |
1398 | ||
7ae87036 SW |
1399 | static int probe_index; |
1400 | ||
9671f099 | 1401 | static int cpm_uart_probe(struct platform_device *ofdev) |
7ae87036 SW |
1402 | { |
1403 | int index = probe_index++; | |
1404 | struct uart_cpm_port *pinfo = &cpm_uart_ports[index]; | |
1405 | int ret; | |
1406 | ||
1407 | pinfo->port.line = index; | |
1408 | ||
1409 | if (index >= UART_NR) | |
1410 | return -ENODEV; | |
1411 | ||
696faedd | 1412 | platform_set_drvdata(ofdev, pinfo); |
7ae87036 | 1413 | |
bd86ef37 SW |
1414 | /* initialize the device pointer for the port */ |
1415 | pinfo->port.dev = &ofdev->dev; | |
1416 | ||
61c7a080 | 1417 | ret = cpm_uart_init_port(ofdev->dev.of_node, pinfo); |
7ae87036 SW |
1418 | if (ret) |
1419 | return ret; | |
1420 | ||
1421 | return uart_add_one_port(&cpm_reg, &pinfo->port); | |
1422 | } | |
1423 | ||
ae8d8a14 | 1424 | static int cpm_uart_remove(struct platform_device *ofdev) |
7ae87036 | 1425 | { |
696faedd | 1426 | struct uart_cpm_port *pinfo = platform_get_drvdata(ofdev); |
7ae87036 SW |
1427 | return uart_remove_one_port(&cpm_reg, &pinfo->port); |
1428 | } | |
1429 | ||
ed0bb232 | 1430 | static const struct of_device_id cpm_uart_match[] = { |
7ae87036 SW |
1431 | { |
1432 | .compatible = "fsl,cpm1-smc-uart", | |
1433 | }, | |
1434 | { | |
1435 | .compatible = "fsl,cpm1-scc-uart", | |
1436 | }, | |
1437 | { | |
1438 | .compatible = "fsl,cpm2-smc-uart", | |
1439 | }, | |
1440 | { | |
1441 | .compatible = "fsl,cpm2-scc-uart", | |
1442 | }, | |
1443 | {} | |
1da177e4 | 1444 | }; |
618bbaa2 | 1445 | MODULE_DEVICE_TABLE(of, cpm_uart_match); |
7ae87036 | 1446 | |
793218df | 1447 | static struct platform_driver cpm_uart_driver = { |
4018294b GL |
1448 | .driver = { |
1449 | .name = "cpm_uart", | |
4018294b GL |
1450 | .of_match_table = cpm_uart_match, |
1451 | }, | |
7ae87036 SW |
1452 | .probe = cpm_uart_probe, |
1453 | .remove = cpm_uart_remove, | |
1454 | }; | |
1455 | ||
1456 | static int __init cpm_uart_init(void) | |
1457 | { | |
1458 | int ret = uart_register_driver(&cpm_reg); | |
1459 | if (ret) | |
1460 | return ret; | |
1461 | ||
793218df | 1462 | ret = platform_driver_register(&cpm_uart_driver); |
7ae87036 SW |
1463 | if (ret) |
1464 | uart_unregister_driver(&cpm_reg); | |
1465 | ||
1466 | return ret; | |
1467 | } | |
1468 | ||
1469 | static void __exit cpm_uart_exit(void) | |
1470 | { | |
793218df | 1471 | platform_driver_unregister(&cpm_uart_driver); |
7ae87036 SW |
1472 | uart_unregister_driver(&cpm_reg); |
1473 | } | |
1da177e4 LT |
1474 | |
1475 | module_init(cpm_uart_init); | |
1476 | module_exit(cpm_uart_exit); | |
1477 | ||
1478 | MODULE_AUTHOR("Kumar Gala/Antoniou Pantelis"); | |
1479 | MODULE_DESCRIPTION("CPM SCC/SMC port driver $Revision: 0.01 $"); | |
1480 | MODULE_LICENSE("GPL"); | |
1481 | MODULE_ALIAS_CHARDEV(SERIAL_CPM_MAJOR, SERIAL_CPM_MINOR); |