Commit | Line | Data |
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e3b3d0f5 | 1 | // SPDX-License-Identifier: GPL-2.0+ |
1da177e4 | 2 | /* |
1da177e4 LT |
3 | * Driver for CLPS711x serial ports |
4 | * | |
5 | * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. | |
6 | * | |
7 | * Copyright 1999 ARM Limited | |
8 | * Copyright (C) 2000 Deep Blue Solutions Ltd. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; either version 2 of the License, or | |
13 | * (at your option) any later version. | |
1da177e4 | 14 | */ |
1da177e4 LT |
15 | |
16 | #if defined(CONFIG_SERIAL_CLPS711X_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) | |
17 | #define SUPPORT_SYSRQ | |
18 | #endif | |
19 | ||
20 | #include <linux/module.h> | |
1da177e4 | 21 | #include <linux/device.h> |
a1c25f2b | 22 | #include <linux/console.h> |
1da177e4 LT |
23 | #include <linux/serial_core.h> |
24 | #include <linux/serial.h> | |
c08f0153 | 25 | #include <linux/clk.h> |
bc000245 | 26 | #include <linux/io.h> |
a1c25f2b AS |
27 | #include <linux/tty.h> |
28 | #include <linux/tty_flip.h> | |
29 | #include <linux/ioport.h> | |
bc000245 | 30 | #include <linux/of.h> |
95113728 | 31 | #include <linux/platform_device.h> |
bc000245 | 32 | #include <linux/regmap.h> |
1da177e4 | 33 | |
bc000245 AS |
34 | #include <linux/mfd/syscon.h> |
35 | #include <linux/mfd/syscon/clps711x.h> | |
1da177e4 | 36 | |
62b0a1b3 AS |
37 | #include "serial_mctrl_gpio.h" |
38 | ||
bc000245 | 39 | #define UART_CLPS711X_DEVNAME "ttyCL" |
117d5d42 AS |
40 | #define UART_CLPS711X_NR 2 |
41 | #define UART_CLPS711X_MAJOR 204 | |
42 | #define UART_CLPS711X_MINOR 40 | |
95113728 | 43 | |
bc000245 AS |
44 | #define UARTDR_OFFSET (0x00) |
45 | #define UBRLCR_OFFSET (0x40) | |
46 | ||
47 | #define UARTDR_FRMERR (1 << 8) | |
48 | #define UARTDR_PARERR (1 << 9) | |
49 | #define UARTDR_OVERR (1 << 10) | |
50 | ||
51 | #define UBRLCR_BAUD_MASK ((1 << 12) - 1) | |
52 | #define UBRLCR_BREAK (1 << 12) | |
53 | #define UBRLCR_PRTEN (1 << 13) | |
54 | #define UBRLCR_EVENPRT (1 << 14) | |
55 | #define UBRLCR_XSTOP (1 << 15) | |
56 | #define UBRLCR_FIFOEN (1 << 16) | |
57 | #define UBRLCR_WRDLEN5 (0 << 17) | |
58 | #define UBRLCR_WRDLEN6 (1 << 17) | |
59 | #define UBRLCR_WRDLEN7 (2 << 17) | |
60 | #define UBRLCR_WRDLEN8 (3 << 17) | |
61 | #define UBRLCR_WRDLEN_MASK (3 << 17) | |
1da177e4 | 62 | |
117d5d42 | 63 | struct clps711x_port { |
bc000245 AS |
64 | struct uart_port port; |
65 | unsigned int tx_enabled; | |
66 | int rx_irq; | |
67 | struct regmap *syscon; | |
62b0a1b3 | 68 | struct mctrl_gpios *gpios; |
bc000245 AS |
69 | }; |
70 | ||
71 | static struct uart_driver clps711x_uart = { | |
72 | .owner = THIS_MODULE, | |
73 | .driver_name = UART_CLPS711X_DEVNAME, | |
74 | .dev_name = UART_CLPS711X_DEVNAME, | |
75 | .major = UART_CLPS711X_MAJOR, | |
76 | .minor = UART_CLPS711X_MINOR, | |
77 | .nr = UART_CLPS711X_NR, | |
117d5d42 AS |
78 | }; |
79 | ||
a1c25f2b | 80 | static void uart_clps711x_stop_tx(struct uart_port *port) |
1da177e4 | 81 | { |
3c7e9eb1 AS |
82 | struct clps711x_port *s = dev_get_drvdata(port->dev); |
83 | ||
bc000245 AS |
84 | if (s->tx_enabled) { |
85 | disable_irq(port->irq); | |
86 | s->tx_enabled = 0; | |
1da177e4 LT |
87 | } |
88 | } | |
89 | ||
a1c25f2b | 90 | static void uart_clps711x_start_tx(struct uart_port *port) |
1da177e4 | 91 | { |
3c7e9eb1 AS |
92 | struct clps711x_port *s = dev_get_drvdata(port->dev); |
93 | ||
bc000245 AS |
94 | if (!s->tx_enabled) { |
95 | s->tx_enabled = 1; | |
96 | enable_irq(port->irq); | |
1da177e4 LT |
97 | } |
98 | } | |
99 | ||
135cc790 | 100 | static irqreturn_t uart_clps711x_int_rx(int irq, void *dev_id) |
1da177e4 LT |
101 | { |
102 | struct uart_port *port = dev_id; | |
bc000245 AS |
103 | struct clps711x_port *s = dev_get_drvdata(port->dev); |
104 | unsigned int status, flg; | |
bc000245 | 105 | u16 ch; |
1da177e4 | 106 | |
f27de95c | 107 | for (;;) { |
093a9e2a AS |
108 | u32 sysflg = 0; |
109 | ||
bc000245 AS |
110 | regmap_read(s->syscon, SYSFLG_OFFSET, &sysflg); |
111 | if (sysflg & SYSFLG_URXFE) | |
f27de95c | 112 | break; |
1da177e4 | 113 | |
093a9e2a | 114 | ch = readw(port->membase + UARTDR_OFFSET); |
f27de95c AS |
115 | status = ch & (UARTDR_FRMERR | UARTDR_PARERR | UARTDR_OVERR); |
116 | ch &= 0xff; | |
117 | ||
118 | port->icount.rx++; | |
1da177e4 LT |
119 | flg = TTY_NORMAL; |
120 | ||
f27de95c AS |
121 | if (unlikely(status)) { |
122 | if (status & UARTDR_PARERR) | |
2a9604b8 | 123 | port->icount.parity++; |
f27de95c | 124 | else if (status & UARTDR_FRMERR) |
2a9604b8 | 125 | port->icount.frame++; |
f27de95c | 126 | else if (status & UARTDR_OVERR) |
2a9604b8 | 127 | port->icount.overrun++; |
1da177e4 | 128 | |
f27de95c | 129 | status &= port->read_status_mask; |
1da177e4 | 130 | |
f27de95c | 131 | if (status & UARTDR_PARERR) |
2a9604b8 | 132 | flg = TTY_PARITY; |
f27de95c | 133 | else if (status & UARTDR_FRMERR) |
2a9604b8 | 134 | flg = TTY_FRAME; |
f27de95c AS |
135 | else if (status & UARTDR_OVERR) |
136 | flg = TTY_OVERRUN; | |
2a9604b8 | 137 | } |
1da177e4 | 138 | |
7d12e780 | 139 | if (uart_handle_sysrq_char(port, ch)) |
f27de95c | 140 | continue; |
1da177e4 | 141 | |
f27de95c AS |
142 | if (status & port->ignore_status_mask) |
143 | continue; | |
2a9604b8 | 144 | |
f27de95c | 145 | uart_insert_char(port, status, UARTDR_OVERR, ch, flg); |
1da177e4 | 146 | } |
f27de95c | 147 | |
2e124b4a | 148 | tty_flip_buffer_push(&port->state->port); |
f27de95c | 149 | |
2a9604b8 | 150 | return IRQ_HANDLED; |
1da177e4 LT |
151 | } |
152 | ||
135cc790 | 153 | static irqreturn_t uart_clps711x_int_tx(int irq, void *dev_id) |
1da177e4 LT |
154 | { |
155 | struct uart_port *port = dev_id; | |
3c7e9eb1 | 156 | struct clps711x_port *s = dev_get_drvdata(port->dev); |
ebd2c8f6 | 157 | struct circ_buf *xmit = &port->state->xmit; |
1da177e4 LT |
158 | |
159 | if (port->x_char) { | |
093a9e2a | 160 | writew(port->x_char, port->membase + UARTDR_OFFSET); |
1da177e4 LT |
161 | port->icount.tx++; |
162 | port->x_char = 0; | |
163 | return IRQ_HANDLED; | |
164 | } | |
7a6fbc9a | 165 | |
3c7e9eb1 | 166 | if (uart_circ_empty(xmit) || uart_tx_stopped(port)) { |
bc000245 AS |
167 | if (s->tx_enabled) { |
168 | disable_irq_nosync(port->irq); | |
169 | s->tx_enabled = 0; | |
170 | } | |
3c7e9eb1 AS |
171 | return IRQ_HANDLED; |
172 | } | |
1da177e4 | 173 | |
cf03a884 | 174 | while (!uart_circ_empty(xmit)) { |
093a9e2a AS |
175 | u32 sysflg = 0; |
176 | ||
177 | writew(xmit->buf[xmit->tail], port->membase + UARTDR_OFFSET); | |
1da177e4 LT |
178 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); |
179 | port->icount.tx++; | |
bc000245 AS |
180 | |
181 | regmap_read(s->syscon, SYSFLG_OFFSET, &sysflg); | |
182 | if (sysflg & SYSFLG_UTXFF) | |
1da177e4 | 183 | break; |
cf03a884 | 184 | } |
1da177e4 LT |
185 | |
186 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
187 | uart_write_wakeup(port); | |
188 | ||
1da177e4 LT |
189 | return IRQ_HANDLED; |
190 | } | |
191 | ||
a1c25f2b | 192 | static unsigned int uart_clps711x_tx_empty(struct uart_port *port) |
1da177e4 | 193 | { |
bc000245 | 194 | struct clps711x_port *s = dev_get_drvdata(port->dev); |
093a9e2a | 195 | u32 sysflg = 0; |
bc000245 AS |
196 | |
197 | regmap_read(s->syscon, SYSFLG_OFFSET, &sysflg); | |
198 | ||
199 | return (sysflg & SYSFLG_UBUSY) ? 0 : TIOCSER_TEMT; | |
1da177e4 LT |
200 | } |
201 | ||
a1c25f2b | 202 | static unsigned int uart_clps711x_get_mctrl(struct uart_port *port) |
1da177e4 | 203 | { |
62b0a1b3 | 204 | unsigned int result = TIOCM_DSR | TIOCM_CTS | TIOCM_CAR; |
bc000245 | 205 | struct clps711x_port *s = dev_get_drvdata(port->dev); |
1da177e4 | 206 | |
62b0a1b3 | 207 | return mctrl_gpio_get(s->gpios, &result); |
1da177e4 LT |
208 | } |
209 | ||
a1c25f2b | 210 | static void uart_clps711x_set_mctrl(struct uart_port *port, unsigned int mctrl) |
1da177e4 | 211 | { |
62b0a1b3 AS |
212 | struct clps711x_port *s = dev_get_drvdata(port->dev); |
213 | ||
214 | mctrl_gpio_set(s->gpios, mctrl); | |
1da177e4 LT |
215 | } |
216 | ||
a1c25f2b | 217 | static void uart_clps711x_break_ctl(struct uart_port *port, int break_state) |
1da177e4 | 218 | { |
1da177e4 LT |
219 | unsigned int ubrlcr; |
220 | ||
093a9e2a | 221 | ubrlcr = readl(port->membase + UBRLCR_OFFSET); |
ec335526 | 222 | if (break_state) |
1da177e4 LT |
223 | ubrlcr |= UBRLCR_BREAK; |
224 | else | |
225 | ubrlcr &= ~UBRLCR_BREAK; | |
093a9e2a | 226 | writel(ubrlcr, port->membase + UBRLCR_OFFSET); |
1da177e4 LT |
227 | } |
228 | ||
732a84a0 PH |
229 | static void uart_clps711x_set_ldisc(struct uart_port *port, |
230 | struct ktermios *termios) | |
71b9e8c6 AS |
231 | { |
232 | if (!port->line) { | |
233 | struct clps711x_port *s = dev_get_drvdata(port->dev); | |
234 | ||
235 | regmap_update_bits(s->syscon, SYSCON_OFFSET, SYSCON1_SIREN, | |
732a84a0 | 236 | (termios->c_line == N_IRDA) ? SYSCON1_SIREN : 0); |
71b9e8c6 AS |
237 | } |
238 | } | |
239 | ||
a1c25f2b | 240 | static int uart_clps711x_startup(struct uart_port *port) |
1da177e4 | 241 | { |
3c7e9eb1 | 242 | struct clps711x_port *s = dev_get_drvdata(port->dev); |
1da177e4 | 243 | |
f52ede2a | 244 | /* Disable break */ |
093a9e2a AS |
245 | writel(readl(port->membase + UBRLCR_OFFSET) & ~UBRLCR_BREAK, |
246 | port->membase + UBRLCR_OFFSET); | |
f52ede2a AS |
247 | |
248 | /* Enable the port */ | |
bc000245 AS |
249 | return regmap_update_bits(s->syscon, SYSCON_OFFSET, |
250 | SYSCON_UARTEN, SYSCON_UARTEN); | |
1da177e4 LT |
251 | } |
252 | ||
a1c25f2b | 253 | static void uart_clps711x_shutdown(struct uart_port *port) |
1da177e4 | 254 | { |
bc000245 | 255 | struct clps711x_port *s = dev_get_drvdata(port->dev); |
1da177e4 | 256 | |
f52ede2a | 257 | /* Disable the port */ |
bc000245 | 258 | regmap_update_bits(s->syscon, SYSCON_OFFSET, SYSCON_UARTEN, 0); |
1da177e4 LT |
259 | } |
260 | ||
a1c25f2b AS |
261 | static void uart_clps711x_set_termios(struct uart_port *port, |
262 | struct ktermios *termios, | |
263 | struct ktermios *old) | |
1da177e4 | 264 | { |
bc000245 AS |
265 | u32 ubrlcr; |
266 | unsigned int baud, quot; | |
1da177e4 | 267 | |
7ae75e94 AS |
268 | /* Mask termios capabilities we don't support */ |
269 | termios->c_cflag &= ~CMSPAR; | |
270 | termios->c_iflag &= ~(BRKINT | IGNBRK); | |
1da177e4 | 271 | |
c08f0153 AS |
272 | /* Ask the core to calculate the divisor for us */ |
273 | baud = uart_get_baud_rate(port, termios, old, port->uartclk / 4096, | |
274 | port->uartclk / 16); | |
1da177e4 LT |
275 | quot = uart_get_divisor(port, baud); |
276 | ||
277 | switch (termios->c_cflag & CSIZE) { | |
278 | case CS5: | |
279 | ubrlcr = UBRLCR_WRDLEN5; | |
280 | break; | |
281 | case CS6: | |
282 | ubrlcr = UBRLCR_WRDLEN6; | |
283 | break; | |
284 | case CS7: | |
285 | ubrlcr = UBRLCR_WRDLEN7; | |
286 | break; | |
a1c25f2b AS |
287 | case CS8: |
288 | default: | |
1da177e4 LT |
289 | ubrlcr = UBRLCR_WRDLEN8; |
290 | break; | |
291 | } | |
7ae75e94 | 292 | |
1da177e4 LT |
293 | if (termios->c_cflag & CSTOPB) |
294 | ubrlcr |= UBRLCR_XSTOP; | |
7ae75e94 | 295 | |
1da177e4 LT |
296 | if (termios->c_cflag & PARENB) { |
297 | ubrlcr |= UBRLCR_PRTEN; | |
298 | if (!(termios->c_cflag & PARODD)) | |
299 | ubrlcr |= UBRLCR_EVENPRT; | |
300 | } | |
cf03a884 AS |
301 | |
302 | /* Enable FIFO */ | |
303 | ubrlcr |= UBRLCR_FIFOEN; | |
1da177e4 | 304 | |
7ae75e94 | 305 | /* Set read status mask */ |
1da177e4 LT |
306 | port->read_status_mask = UARTDR_OVERR; |
307 | if (termios->c_iflag & INPCK) | |
308 | port->read_status_mask |= UARTDR_PARERR | UARTDR_FRMERR; | |
309 | ||
7ae75e94 | 310 | /* Set status ignore mask */ |
1da177e4 | 311 | port->ignore_status_mask = 0; |
7ae75e94 AS |
312 | if (!(termios->c_cflag & CREAD)) |
313 | port->ignore_status_mask |= UARTDR_OVERR | UARTDR_PARERR | | |
314 | UARTDR_FRMERR; | |
1da177e4 | 315 | |
7ae75e94 | 316 | uart_update_timeout(port, termios->c_cflag, baud); |
1da177e4 | 317 | |
093a9e2a | 318 | writel(ubrlcr | (quot - 1), port->membase + UBRLCR_OFFSET); |
1da177e4 LT |
319 | } |
320 | ||
a1c25f2b | 321 | static const char *uart_clps711x_type(struct uart_port *port) |
1da177e4 | 322 | { |
a1c25f2b | 323 | return (port->type == PORT_CLPS711X) ? "CLPS711X" : NULL; |
1da177e4 LT |
324 | } |
325 | ||
a1c25f2b | 326 | static void uart_clps711x_config_port(struct uart_port *port, int flags) |
1da177e4 LT |
327 | { |
328 | if (flags & UART_CONFIG_TYPE) | |
329 | port->type = PORT_CLPS711X; | |
330 | } | |
331 | ||
bc000245 | 332 | static void uart_clps711x_nop_void(struct uart_port *port) |
1da177e4 LT |
333 | { |
334 | } | |
335 | ||
bc000245 | 336 | static int uart_clps711x_nop_int(struct uart_port *port) |
1da177e4 LT |
337 | { |
338 | return 0; | |
339 | } | |
340 | ||
a1c25f2b AS |
341 | static const struct uart_ops uart_clps711x_ops = { |
342 | .tx_empty = uart_clps711x_tx_empty, | |
343 | .set_mctrl = uart_clps711x_set_mctrl, | |
344 | .get_mctrl = uart_clps711x_get_mctrl, | |
345 | .stop_tx = uart_clps711x_stop_tx, | |
346 | .start_tx = uart_clps711x_start_tx, | |
bc000245 | 347 | .stop_rx = uart_clps711x_nop_void, |
a1c25f2b | 348 | .break_ctl = uart_clps711x_break_ctl, |
71b9e8c6 | 349 | .set_ldisc = uart_clps711x_set_ldisc, |
a1c25f2b AS |
350 | .startup = uart_clps711x_startup, |
351 | .shutdown = uart_clps711x_shutdown, | |
352 | .set_termios = uart_clps711x_set_termios, | |
353 | .type = uart_clps711x_type, | |
354 | .config_port = uart_clps711x_config_port, | |
bc000245 AS |
355 | .release_port = uart_clps711x_nop_void, |
356 | .request_port = uart_clps711x_nop_int, | |
1da177e4 LT |
357 | }; |
358 | ||
1da177e4 | 359 | #ifdef CONFIG_SERIAL_CLPS711X_CONSOLE |
117d5d42 | 360 | static void uart_clps711x_console_putchar(struct uart_port *port, int ch) |
d358788f | 361 | { |
bc000245 | 362 | struct clps711x_port *s = dev_get_drvdata(port->dev); |
2f310b8e | 363 | u32 sysflg = 0; |
bc000245 | 364 | |
63e3ad32 | 365 | /* Wait for FIFO is not full */ |
2f310b8e | 366 | do { |
bc000245 | 367 | regmap_read(s->syscon, SYSFLG_OFFSET, &sysflg); |
2f310b8e | 368 | } while (sysflg & SYSFLG_UTXFF); |
117d5d42 | 369 | |
093a9e2a | 370 | writew(ch, port->membase + UARTDR_OFFSET); |
d358788f RK |
371 | } |
372 | ||
117d5d42 AS |
373 | static void uart_clps711x_console_write(struct console *co, const char *c, |
374 | unsigned n) | |
1da177e4 | 375 | { |
bc000245 AS |
376 | struct uart_port *port = clps711x_uart.state[co->index].uart_port; |
377 | struct clps711x_port *s = dev_get_drvdata(port->dev); | |
2f310b8e | 378 | u32 sysflg = 0; |
1da177e4 | 379 | |
117d5d42 | 380 | uart_console_write(port, c, n, uart_clps711x_console_putchar); |
1da177e4 | 381 | |
117d5d42 | 382 | /* Wait for transmitter to become empty */ |
2f310b8e | 383 | do { |
bc000245 | 384 | regmap_read(s->syscon, SYSFLG_OFFSET, &sysflg); |
2f310b8e | 385 | } while (sysflg & SYSFLG_UBUSY); |
1da177e4 LT |
386 | } |
387 | ||
bc000245 | 388 | static int uart_clps711x_console_setup(struct console *co, char *options) |
1da177e4 | 389 | { |
bc000245 AS |
390 | int baud = 38400, bits = 8, parity = 'n', flow = 'n'; |
391 | int ret, index = co->index; | |
392 | struct clps711x_port *s; | |
393 | struct uart_port *port; | |
bc000245 | 394 | unsigned int quot; |
093a9e2a | 395 | u32 ubrlcr; |
1da177e4 | 396 | |
bc000245 AS |
397 | if (index < 0 || index >= UART_CLPS711X_NR) |
398 | return -EINVAL; | |
1da177e4 | 399 | |
bc000245 AS |
400 | port = clps711x_uart.state[index].uart_port; |
401 | if (!port) | |
402 | return -ENODEV; | |
1da177e4 | 403 | |
bc000245 | 404 | s = dev_get_drvdata(port->dev); |
1da177e4 | 405 | |
bc000245 | 406 | if (!options) { |
093a9e2a AS |
407 | u32 syscon = 0; |
408 | ||
bc000245 AS |
409 | regmap_read(s->syscon, SYSCON_OFFSET, &syscon); |
410 | if (syscon & SYSCON_UARTEN) { | |
093a9e2a | 411 | ubrlcr = readl(port->membase + UBRLCR_OFFSET); |
1da177e4 | 412 | |
bc000245 AS |
413 | if (ubrlcr & UBRLCR_PRTEN) { |
414 | if (ubrlcr & UBRLCR_EVENPRT) | |
415 | parity = 'e'; | |
416 | else | |
417 | parity = 'o'; | |
418 | } | |
1da177e4 | 419 | |
bc000245 AS |
420 | if ((ubrlcr & UBRLCR_WRDLEN_MASK) == UBRLCR_WRDLEN7) |
421 | bits = 7; | |
422 | ||
423 | quot = ubrlcr & UBRLCR_BAUD_MASK; | |
424 | baud = port->uartclk / (16 * (quot + 1)); | |
425 | } | |
426 | } else | |
1da177e4 | 427 | uart_parse_options(options, &baud, &parity, &bits, &flow); |
1da177e4 | 428 | |
bc000245 AS |
429 | ret = uart_set_options(port, co, baud, parity, bits, flow); |
430 | if (ret) | |
431 | return ret; | |
432 | ||
433 | return regmap_update_bits(s->syscon, SYSCON_OFFSET, | |
434 | SYSCON_UARTEN, SYSCON_UARTEN); | |
1da177e4 | 435 | } |
bc000245 AS |
436 | |
437 | static struct console clps711x_console = { | |
438 | .name = UART_CLPS711X_DEVNAME, | |
439 | .device = uart_console_device, | |
440 | .write = uart_clps711x_console_write, | |
441 | .setup = uart_clps711x_console_setup, | |
442 | .flags = CON_PRINTBUFFER, | |
443 | .index = -1, | |
444 | }; | |
1da177e4 LT |
445 | #endif |
446 | ||
9671f099 | 447 | static int uart_clps711x_probe(struct platform_device *pdev) |
1da177e4 | 448 | { |
bc000245 AS |
449 | struct device_node *np = pdev->dev.of_node; |
450 | int ret, index = np ? of_alias_get_id(np, "serial") : pdev->id; | |
117d5d42 | 451 | struct clps711x_port *s; |
bc000245 AS |
452 | struct resource *res; |
453 | struct clk *uart_clk; | |
8f5405c9 | 454 | int irq; |
1da177e4 | 455 | |
bc000245 AS |
456 | if (index < 0 || index >= UART_CLPS711X_NR) |
457 | return -EINVAL; | |
458 | ||
459 | s = devm_kzalloc(&pdev->dev, sizeof(*s), GFP_KERNEL); | |
460 | if (!s) | |
117d5d42 | 461 | return -ENOMEM; |
bc000245 AS |
462 | |
463 | uart_clk = devm_clk_get(&pdev->dev, NULL); | |
464 | if (IS_ERR(uart_clk)) | |
465 | return PTR_ERR(uart_clk); | |
466 | ||
467 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
468 | s->port.membase = devm_ioremap_resource(&pdev->dev, res); | |
469 | if (IS_ERR(s->port.membase)) | |
470 | return PTR_ERR(s->port.membase); | |
471 | ||
8f5405c9 GR |
472 | irq = platform_get_irq(pdev, 0); |
473 | if (irq < 0) | |
474 | return irq; | |
475 | s->port.irq = irq; | |
bc000245 AS |
476 | |
477 | s->rx_irq = platform_get_irq(pdev, 1); | |
8f5405c9 | 478 | if (s->rx_irq < 0) |
bc000245 AS |
479 | return s->rx_irq; |
480 | ||
481 | if (!np) { | |
482 | char syscon_name[9]; | |
483 | ||
484 | sprintf(syscon_name, "syscon.%i", index + 1); | |
485 | s->syscon = syscon_regmap_lookup_by_pdevname(syscon_name); | |
486 | if (IS_ERR(s->syscon)) | |
487 | return PTR_ERR(s->syscon); | |
bc000245 AS |
488 | } else { |
489 | s->syscon = syscon_regmap_lookup_by_phandle(np, "syscon"); | |
490 | if (IS_ERR(s->syscon)) | |
491 | return PTR_ERR(s->syscon); | |
117d5d42 | 492 | } |
bc000245 AS |
493 | |
494 | s->port.line = index; | |
495 | s->port.dev = &pdev->dev; | |
496 | s->port.iotype = UPIO_MEM32; | |
497 | s->port.mapbase = res->start; | |
498 | s->port.type = PORT_CLPS711X; | |
499 | s->port.fifosize = 16; | |
500 | s->port.flags = UPF_SKIP_TEST | UPF_FIXED_TYPE; | |
501 | s->port.uartclk = clk_get_rate(uart_clk); | |
502 | s->port.ops = &uart_clps711x_ops; | |
503 | ||
117d5d42 | 504 | platform_set_drvdata(pdev, s); |
1da177e4 | 505 | |
7d8c70d8 | 506 | s->gpios = mctrl_gpio_init_noauto(&pdev->dev, 0); |
f059a455 UKK |
507 | if (IS_ERR(s->gpios)) |
508 | return PTR_ERR(s->gpios); | |
62b0a1b3 | 509 | |
bc000245 AS |
510 | ret = uart_add_one_port(&clps711x_uart, &s->port); |
511 | if (ret) | |
512 | return ret; | |
c08f0153 | 513 | |
bc000245 AS |
514 | /* Disable port */ |
515 | if (!uart_console(&s->port)) | |
516 | regmap_update_bits(s->syscon, SYSCON_OFFSET, SYSCON_UARTEN, 0); | |
517 | ||
518 | s->tx_enabled = 1; | |
519 | ||
520 | ret = devm_request_irq(&pdev->dev, s->port.irq, uart_clps711x_int_tx, 0, | |
521 | dev_name(&pdev->dev), &s->port); | |
117d5d42 | 522 | if (ret) { |
bc000245 | 523 | uart_remove_one_port(&clps711x_uart, &s->port); |
43b829b3 | 524 | return ret; |
117d5d42 | 525 | } |
1da177e4 | 526 | |
bc000245 AS |
527 | ret = devm_request_irq(&pdev->dev, s->rx_irq, uart_clps711x_int_rx, 0, |
528 | dev_name(&pdev->dev), &s->port); | |
529 | if (ret) | |
530 | uart_remove_one_port(&clps711x_uart, &s->port); | |
1da177e4 | 531 | |
bc000245 | 532 | return ret; |
1da177e4 LT |
533 | } |
534 | ||
ae8d8a14 | 535 | static int uart_clps711x_remove(struct platform_device *pdev) |
1da177e4 | 536 | { |
117d5d42 | 537 | struct clps711x_port *s = platform_get_drvdata(pdev); |
95113728 | 538 | |
bc000245 | 539 | return uart_remove_one_port(&clps711x_uart, &s->port); |
1da177e4 LT |
540 | } |
541 | ||
bc000245 | 542 | static const struct of_device_id __maybe_unused clps711x_uart_dt_ids[] = { |
d305345c | 543 | { .compatible = "cirrus,ep7209-uart", }, |
bc000245 AS |
544 | { } |
545 | }; | |
546 | MODULE_DEVICE_TABLE(of, clps711x_uart_dt_ids); | |
547 | ||
548 | static struct platform_driver clps711x_uart_platform = { | |
95113728 | 549 | .driver = { |
bc000245 | 550 | .name = "clps711x-uart", |
bc000245 | 551 | .of_match_table = of_match_ptr(clps711x_uart_dt_ids), |
95113728 AS |
552 | }, |
553 | .probe = uart_clps711x_probe, | |
2d47b716 | 554 | .remove = uart_clps711x_remove, |
95113728 | 555 | }; |
95113728 AS |
556 | |
557 | static int __init uart_clps711x_init(void) | |
558 | { | |
bc000245 AS |
559 | int ret; |
560 | ||
561 | #ifdef CONFIG_SERIAL_CLPS711X_CONSOLE | |
562 | clps711x_uart.cons = &clps711x_console; | |
563 | clps711x_console.data = &clps711x_uart; | |
564 | #endif | |
565 | ||
566 | ret = uart_register_driver(&clps711x_uart); | |
567 | if (ret) | |
568 | return ret; | |
569 | ||
570 | return platform_driver_register(&clps711x_uart_platform); | |
95113728 AS |
571 | } |
572 | module_init(uart_clps711x_init); | |
573 | ||
574 | static void __exit uart_clps711x_exit(void) | |
575 | { | |
bc000245 AS |
576 | platform_driver_unregister(&clps711x_uart_platform); |
577 | uart_unregister_driver(&clps711x_uart); | |
95113728 AS |
578 | } |
579 | module_exit(uart_clps711x_exit); | |
1da177e4 LT |
580 | |
581 | MODULE_AUTHOR("Deep Blue Solutions Ltd"); | |
95113728 | 582 | MODULE_DESCRIPTION("CLPS711X serial driver"); |
1da177e4 | 583 | MODULE_LICENSE("GPL"); |