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Merge tag 'stable/for-linus-3.19-rc0-tag' of git://git.kernel.org/pub/scm/linux/kerne...
[linux-2.6-block.git] / drivers / tty / serial / bfin_uart.c
CommitLineData
194de561 1/*
1ba7a3ee 2 * Blackfin On-Chip Serial Driver
194de561 3 *
b06d2f20 4 * Copyright 2006-2011 Analog Devices Inc.
194de561 5 *
1ba7a3ee 6 * Enter bugs at http://blackfin.uclinux.org/
194de561 7 *
1ba7a3ee 8 * Licensed under the GPL-2 or later.
194de561
BW		 9 */
10
11#if defined(CONFIG_SERIAL_BFIN_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
12#define SUPPORT_SYSRQ
13#endif
14
57afb399
SZ		 15#define DRIVER_NAME "bfin-uart"
16#define pr_fmt(fmt) DRIVER_NAME ": " fmt
17
194de561
BW		 18#include <linux/module.h>
19#include <linux/ioport.h>
5a0e3ad6 20#include <linux/gfp.h>
599b714c 21#include <linux/io.h>
194de561
BW		 22#include <linux/init.h>
23#include <linux/console.h>
24#include <linux/sysrq.h>
25#include <linux/platform_device.h>
26#include <linux/tty.h>
27#include <linux/tty_flip.h>
28#include <linux/serial_core.h>
57afb399
SZ		 29#include <linux/gpio.h>
30#include <linux/irq.h>
474f1a66 31#include <linux/kgdb.h>
57afb399
SZ		 32#include <linux/slab.h>
33#include <linux/dma-mapping.h>
194de561 34
57afb399 35#include <asm/portmux.h>
194de561 36#include <asm/cacheflush.h>
57afb399 37#include <asm/dma.h>
57afb399 38#include <asm/bfin_serial.h>
194de561 39
607c268e
MF		 40#ifdef CONFIG_SERIAL_BFIN_MODULE
41# undef CONFIG_EARLY_PRINTK
42#endif
43
194de561 44/* UART name and device definitions */
57afb399 45#define BFIN_SERIAL_DEV_NAME "ttyBF"
194de561
BW		 46#define BFIN_SERIAL_MAJOR 204
47#define BFIN_SERIAL_MINOR 64
48
57afb399 49static struct bfin_serial_port *bfin_serial_ports[BFIN_UART_NR_PORTS];
c9607ecc 50
52e15f0e
SZ		 51#if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \
52 defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE)
53
54# ifndef CONFIG_SERIAL_BFIN_PIO
55# error KGDB only support UART in PIO mode.
56# endif
57
58static int kgdboc_port_line;
59static int kgdboc_break_enabled;
60#endif
194de561
BW		 61/*
62 * Setup for console. Argument comes from the menuconfig
63 */
64#define DMA_RX_XCOUNT 512
65#define DMA_RX_YCOUNT (PAGE_SIZE / DMA_RX_XCOUNT)
66
0aef4564 67#define DMA_RX_FLUSH_JIFFIES (HZ / 50)
194de561
BW		 68
69#ifdef CONFIG_SERIAL_BFIN_DMA
70static void bfin_serial_dma_tx_chars(struct bfin_serial_port *uart);
71#else
194de561 72static void bfin_serial_tx_chars(struct bfin_serial_port *uart);
194de561
BW		 73#endif
74
80d5c474
GY		 75static void bfin_serial_reset_irda(struct uart_port *port);
76
d307d36a
SZ		 77#if defined(CONFIG_SERIAL_BFIN_CTSRTS) || \
78 defined(CONFIG_SERIAL_BFIN_HARD_CTSRTS)
79static unsigned int bfin_serial_get_mctrl(struct uart_port *port)
80{
81 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
82 if (uart->cts_pin < 0)
83 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
84
85 /* CTS PIN is negative assertive. */
86 if (UART_GET_CTS(uart))
87 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
88 else
89 return TIOCM_DSR | TIOCM_CAR;
90}
91
92static void bfin_serial_set_mctrl(struct uart_port *port, unsigned int mctrl)
93{
94 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
95 if (uart->rts_pin < 0)
96 return;
97
98 /* RTS PIN is negative assertive. */
99 if (mctrl & TIOCM_RTS)
100 UART_ENABLE_RTS(uart);
101 else
102 UART_DISABLE_RTS(uart);
103}
104
105/*
106 * Handle any change of modem status signal.
107 */
108static irqreturn_t bfin_serial_mctrl_cts_int(int irq, void *dev_id)
109{
110 struct bfin_serial_port *uart = dev_id;
d01f4d18
PH		 111 struct uart_port *uport = &uart->port;
112 unsigned int status = bfin_serial_get_mctrl(uport);
d307d36a 113#ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
64851636 114
d307d36a 115 UART_CLEAR_SCTS(uart);
d01f4d18 116 if (uport->hw_stopped) {
64851636 117 if (status) {
d01f4d18
PH		 118 uport->hw_stopped = 0;
119 uart_write_wakeup(uport);
64851636
SZ		 120 }
121 } else {
122 if (!status)
d01f4d18 123 uport->hw_stopped = 1;
64851636 124 }
8620d3e5 125#else
d01f4d18 126 uart_handle_cts_change(uport, status & TIOCM_CTS);
8620d3e5 127#endif
d307d36a
SZ		 128
129 return IRQ_HANDLED;
130}
131#else
132static unsigned int bfin_serial_get_mctrl(struct uart_port *port)
133{
134 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
135}
136
137static void bfin_serial_set_mctrl(struct uart_port *port, unsigned int mctrl)
138{
139}
140#endif
141
194de561
BW		 142/*
143 * interrupts are disabled on entry
144 */
145static void bfin_serial_stop_tx(struct uart_port *port)
146{
147 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
68a784cb 148#ifdef CONFIG_SERIAL_BFIN_DMA
ebd2c8f6 149 struct circ_buf *xmit = &uart->port.state->xmit;
68a784cb 150#endif
194de561 151
f4d640c9 152 while (!(UART_GET_LSR(uart) & TEMT))
0711d857 153 cpu_relax();
f4d640c9 154
194de561
BW		 155#ifdef CONFIG_SERIAL_BFIN_DMA
156 disable_dma(uart->tx_dma_channel);
0711d857
SZ		 157 xmit->tail = (xmit->tail + uart->tx_count) & (UART_XMIT_SIZE - 1);
158 uart->port.icount.tx += uart->tx_count;
159 uart->tx_count = 0;
160 uart->tx_done = 1;
f4d640c9 161#else
b06d2f20 162#if defined(CONFIG_BF54x) || defined(CONFIG_BF60x)
f4d640c9
RH		 163 /* Clear TFI bit */
164 UART_PUT_LSR(uart, TFI);
194de561 165#endif
89bf6dc5 166 UART_CLEAR_IER(uart, ETBEI);
f4d640c9 167#endif
194de561
BW		 168}
169
170/*
171 * port is locked and interrupts are disabled
172 */
173static void bfin_serial_start_tx(struct uart_port *port)
174{
175 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
ebd2c8f6 176 struct tty_struct *tty = uart->port.state->port.tty;
80d5c474
GY		 177
178 /*
179 * To avoid losting RX interrupt, we reset IR function
180 * before sending data.
181 */
adc8d746 182 if (tty->termios.c_line == N_IRDA)
80d5c474 183 bfin_serial_reset_irda(port);
194de561
BW		 184
185#ifdef CONFIG_SERIAL_BFIN_DMA
0711d857
SZ		 186 if (uart->tx_done)
187 bfin_serial_dma_tx_chars(uart);
f4d640c9 188#else
f4d640c9 189 UART_SET_IER(uart, ETBEI);
a359cca7 190 bfin_serial_tx_chars(uart);
f4d640c9 191#endif
194de561
BW		 192}
193
194/*
195 * Interrupts are enabled
196 */
197static void bfin_serial_stop_rx(struct uart_port *port)
198{
199 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
52e15f0e 200
f4d640c9 201 UART_CLEAR_IER(uart, ERBFI);
194de561
BW		 202}
203
50e2e15a 204#if ANOMALY_05000363 && defined(CONFIG_SERIAL_BFIN_PIO)
8851c71e
MF		 205# define UART_GET_ANOMALY_THRESHOLD(uart) ((uart)->anomaly_threshold)
206# define UART_SET_ANOMALY_THRESHOLD(uart, v) ((uart)->anomaly_threshold = (v))
207#else
208# define UART_GET_ANOMALY_THRESHOLD(uart) 0
209# define UART_SET_ANOMALY_THRESHOLD(uart, v)
210#endif
211
194de561 212#ifdef CONFIG_SERIAL_BFIN_PIO
194de561
BW		 213static void bfin_serial_rx_chars(struct bfin_serial_port *uart)
214{
194de561 215 unsigned int status, ch, flg;
8851c71e 216 static struct timeval anomaly_start = { .tv_sec = 0 };
194de561 217
759eb040 218 status = UART_GET_LSR(uart);
0bcfd70e
MF		 219 UART_CLEAR_LSR(uart);
220
bb7e58f8
SZ		 221 ch = UART_GET_CHAR(uart);
222 uart->port.icount.rx++;
194de561 223
52e15f0e
SZ		 224#if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \
225 defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE)
cdc592d5
SZ		 226 if (kgdb_connected && kgdboc_port_line == uart->port.line
227 && kgdboc_break_enabled)
52e15f0e
SZ		 228 if (ch == 0x3) {/* Ctrl + C */
229 kgdb_breakpoint();
474f1a66 230 return;
474f1a66 231 }
52e15f0e 232
2e124b4a 233 if (!uart->port.state)
52e15f0e 234 return;
474f1a66 235#endif
50e2e15a 236 if (ANOMALY_05000363) {
8851c71e
MF		 237 /* The BF533 (and BF561) family of processors have a nice anomaly
238 * where they continuously generate characters for a "single" break.
bbf275f0 239 * We have to basically ignore this flood until the "next" valid
8851c71e
MF		 240 * character comes across. Due to the nature of the flood, it is
241 * not possible to reliably catch bytes that are sent too quickly
242 * after this break. So application code talking to the Blackfin
243 * which sends a break signal must allow at least 1.5 character
244 * times after the end of the break for things to stabilize. This
245 * timeout was picked as it must absolutely be larger than 1
246 * character time +/- some percent. So 1.5 sounds good. All other
247 * Blackfin families operate properly. Woo.
bbf275f0 248 */
8851c71e
MF		 249 if (anomaly_start.tv_sec) {
250 struct timeval curr;
251 suseconds_t usecs;
252
253 if ((~ch & (~ch + 1)) & 0xff)
254 goto known_good_char;
255
256 do_gettimeofday(&curr);
257 if (curr.tv_sec - anomaly_start.tv_sec > 1)
258 goto known_good_char;
259
260 usecs = 0;
261 if (curr.tv_sec != anomaly_start.tv_sec)
262 usecs += USEC_PER_SEC;
263 usecs += curr.tv_usec - anomaly_start.tv_usec;
264
265 if (usecs > UART_GET_ANOMALY_THRESHOLD(uart))
266 goto known_good_char;
267
268 if (ch)
269 anomaly_start.tv_sec = 0;
270 else
271 anomaly_start = curr;
272
273 return;
274
275 known_good_char:
e482a237 276 status &= ~BI;
8851c71e 277 anomaly_start.tv_sec = 0;
bbf275f0 278 }
194de561 279 }
194de561
BW		 280
281 if (status & BI) {
50e2e15a 282 if (ANOMALY_05000363)
8851c71e
MF		 283 if (bfin_revid() < 5)
284 do_gettimeofday(&anomaly_start);
194de561
BW		 285 uart->port.icount.brk++;
286 if (uart_handle_break(&uart->port))
287 goto ignore_char;
9808901b 288 status &= ~(PE | FE);
2ac5ee47
MF		 289 }
290 if (status & PE)
194de561 291 uart->port.icount.parity++;
2ac5ee47 292 if (status & OE)
194de561 293 uart->port.icount.overrun++;
2ac5ee47 294 if (status & FE)
194de561 295 uart->port.icount.frame++;
2ac5ee47
MF		 296
297 status &= uart->port.read_status_mask;
298
299 if (status & BI)
300 flg = TTY_BREAK;
301 else if (status & PE)
302 flg = TTY_PARITY;
303 else if (status & FE)
304 flg = TTY_FRAME;
305 else
194de561
BW		 306 flg = TTY_NORMAL;
307
308 if (uart_handle_sysrq_char(&uart->port, ch))
309 goto ignore_char;
194de561 310
2ac5ee47
MF		 311 uart_insert_char(&uart->port, status, OE, ch, flg);
312
313 ignore_char:
2e124b4a 314 tty_flip_buffer_push(&uart->port.state->port);
194de561
BW		 315}
316
317static void bfin_serial_tx_chars(struct bfin_serial_port *uart)
318{
ebd2c8f6 319 struct circ_buf *xmit = &uart->port.state->xmit;
194de561 320
194de561 321 if (uart_circ_empty(xmit) || uart_tx_stopped(&uart->port)) {
b06d2f20 322#if defined(CONFIG_BF54x) || defined(CONFIG_BF60x)
5ffdeea2
SZ		 323 /* Clear TFI bit */
324 UART_PUT_LSR(uart, TFI);
325#endif
0efa4f2c
SZ		 326 /* Anomaly notes:
327 * 05000215 - we always clear ETBEI within last UART TX
328 * interrupt to end a string. It is always set
329 * when start a new tx.
330 */
5ffdeea2 331 UART_CLEAR_IER(uart, ETBEI);
194de561
BW		 332 return;
333 }
334
f30ac0ce
SZ		 335 if (uart->port.x_char) {
336 UART_PUT_CHAR(uart, uart->port.x_char);
337 uart->port.icount.tx++;
338 uart->port.x_char = 0;
339 }
340
759eb040
SZ		 341 while ((UART_GET_LSR(uart) & THRE) && xmit->tail != xmit->head) {
342 UART_PUT_CHAR(uart, xmit->buf[xmit->tail]);
343 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
344 uart->port.icount.tx++;
759eb040 345 }
194de561
BW		 346
347 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
348 uart_write_wakeup(&uart->port);
194de561
BW		 349}
350
5c4e472b
AL		 351static irqreturn_t bfin_serial_rx_int(int irq, void *dev_id)
352{
353 struct bfin_serial_port *uart = dev_id;
354
0bcfd70e 355 while (UART_GET_LSR(uart) & DR)
f4d640c9 356 bfin_serial_rx_chars(uart);
759eb040 357
5c4e472b
AL		 358 return IRQ_HANDLED;
359}
360
361static irqreturn_t bfin_serial_tx_int(int irq, void *dev_id)
194de561
BW		 362{
363 struct bfin_serial_port *uart = dev_id;
194de561 364
f4d640c9 365 spin_lock(&uart->port.lock);
0bcfd70e 366 if (UART_GET_LSR(uart) & THRE)
f4d640c9 367 bfin_serial_tx_chars(uart);
f4d640c9 368 spin_unlock(&uart->port.lock);
759eb040 369
194de561
BW		 370 return IRQ_HANDLED;
371}
4cb4f22b 372#endif
194de561 373
194de561
BW		 374#ifdef CONFIG_SERIAL_BFIN_DMA
375static void bfin_serial_dma_tx_chars(struct bfin_serial_port *uart)
376{
ebd2c8f6 377 struct circ_buf *xmit = &uart->port.state->xmit;
194de561 378
194de561
BW		 379 uart->tx_done = 0;
380
1b73351c 381 if (uart_circ_empty(xmit) || uart_tx_stopped(&uart->port)) {
0711d857 382 uart->tx_count = 0;
1b73351c
SZ		 383 uart->tx_done = 1;
384 return;
385 }
386
194de561
BW		 387 if (uart->port.x_char) {
388 UART_PUT_CHAR(uart, uart->port.x_char);
389 uart->port.icount.tx++;
390 uart->port.x_char = 0;
194de561 391 }
1b73351c 392
194de561
BW		 393 uart->tx_count = CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE);
394 if (uart->tx_count > (UART_XMIT_SIZE - xmit->tail))
395 uart->tx_count = UART_XMIT_SIZE - xmit->tail;
396 blackfin_dcache_flush_range((unsigned long)(xmit->buf+xmit->tail),
397 (unsigned long)(xmit->buf+xmit->tail+uart->tx_count));
398 set_dma_config(uart->tx_dma_channel,
399 set_bfin_dma_config(DIR_READ, DMA_FLOW_STOP,
400 INTR_ON_BUF,
401 DIMENSION_LINEAR,
2047e40d
MH		 402 DATA_SIZE_8,
403 DMA_SYNC_RESTART));
194de561
BW		 404 set_dma_start_addr(uart->tx_dma_channel, (unsigned long)(xmit->buf+xmit->tail));
405 set_dma_x_count(uart->tx_dma_channel, uart->tx_count);
406 set_dma_x_modify(uart->tx_dma_channel, 1);
f9d36da9 407 SSYNC();
194de561 408 enable_dma(uart->tx_dma_channel);
99ee7b5f 409
f4d640c9 410 UART_SET_IER(uart, ETBEI);
194de561
BW		 411}
412
2ac5ee47 413static void bfin_serial_dma_rx_chars(struct bfin_serial_port *uart)
194de561 414{
194de561
BW		 415 int i, flg, status;
416
417 status = UART_GET_LSR(uart);
0bcfd70e
MF		 418 UART_CLEAR_LSR(uart);
419
56f5de8f
SZ		 420 uart->port.icount.rx +=
421 CIRC_CNT(uart->rx_dma_buf.head, uart->rx_dma_buf.tail,
422 UART_XMIT_SIZE);
194de561
BW		 423
424 if (status & BI) {
425 uart->port.icount.brk++;
426 if (uart_handle_break(&uart->port))
427 goto dma_ignore_char;
9808901b 428 status &= ~(PE | FE);
2ac5ee47
MF		 429 }
430 if (status & PE)
194de561 431 uart->port.icount.parity++;
2ac5ee47 432 if (status & OE)
194de561 433 uart->port.icount.overrun++;
2ac5ee47 434 if (status & FE)
194de561 435 uart->port.icount.frame++;
2ac5ee47
MF		 436
437 status &= uart->port.read_status_mask;
438
439 if (status & BI)
440 flg = TTY_BREAK;
441 else if (status & PE)
442 flg = TTY_PARITY;
443 else if (status & FE)
444 flg = TTY_FRAME;
445 else
194de561
BW		 446 flg = TTY_NORMAL;
447
8c4210e3 448 for (i = uart->rx_dma_buf.tail; ; i++) {
56f5de8f
SZ		 449 if (i >= UART_XMIT_SIZE)
450 i = 0;
8c4210e3
SZ		 451 if (i == uart->rx_dma_buf.head)
452 break;
56f5de8f
SZ		 453 if (!uart_handle_sysrq_char(&uart->port, uart->rx_dma_buf.buf[i]))
454 uart_insert_char(&uart->port, status, OE,
455 uart->rx_dma_buf.buf[i], flg);
194de561 456 }
2ac5ee47
MF		 457
458 dma_ignore_char:
2e124b4a 459 tty_flip_buffer_push(&uart->port.state->port);
194de561
BW		 460}
461
462void bfin_serial_rx_dma_timeout(struct bfin_serial_port *uart)
463{
59e4e3e6 464 int x_pos, pos;
9642dbe7 465 unsigned long flags;
68a784cb 466
9642dbe7 467 spin_lock_irqsave(&uart->rx_lock, flags);
194de561 468
8516c568
SZ		 469 /* 2D DMA RX buffer ring is used. Because curr_y_count and
470 * curr_x_count can't be read as an atomic operation,
471 * curr_y_count should be read before curr_x_count. When
472 * curr_x_count is read, curr_y_count may already indicate
473 * next buffer line. But, the position calculated here is
474 * still indicate the old line. The wrong position data may
475 * be smaller than current buffer tail, which cause garbages
476 * are received if it is not prohibit.
477 */
56f5de8f
SZ		 478 uart->rx_dma_nrows = get_dma_curr_ycount(uart->rx_dma_channel);
479 x_pos = get_dma_curr_xcount(uart->rx_dma_channel);
480 uart->rx_dma_nrows = DMA_RX_YCOUNT - uart->rx_dma_nrows;
35ff6935 481 if (uart->rx_dma_nrows == DMA_RX_YCOUNT || x_pos == 0)
56f5de8f
SZ		 482 uart->rx_dma_nrows = 0;
483 x_pos = DMA_RX_XCOUNT - x_pos;
194de561
BW		 484 if (x_pos == DMA_RX_XCOUNT)
485 x_pos = 0;
486
487 pos = uart->rx_dma_nrows * DMA_RX_XCOUNT + x_pos;
8516c568
SZ		 488 /* Ignore receiving data if new position is in the same line of
489 * current buffer tail and small.
490 */
491 if (pos > uart->rx_dma_buf.tail ||
492 uart->rx_dma_nrows < (uart->rx_dma_buf.tail/DMA_RX_XCOUNT)) {
56f5de8f 493 uart->rx_dma_buf.head = pos;
194de561 494 bfin_serial_dma_rx_chars(uart);
56f5de8f 495 uart->rx_dma_buf.tail = uart->rx_dma_buf.head;
194de561 496 }
0aef4564 497
9642dbe7 498 spin_unlock_irqrestore(&uart->rx_lock, flags);
68a784cb 499
0a278423 500 mod_timer(&(uart->rx_dma_timer), jiffies + DMA_RX_FLUSH_JIFFIES);
194de561
BW		 501}
502
503static irqreturn_t bfin_serial_dma_tx_int(int irq, void *dev_id)
504{
505 struct bfin_serial_port *uart = dev_id;
ebd2c8f6 506 struct circ_buf *xmit = &uart->port.state->xmit;
194de561
BW		 507
508 spin_lock(&uart->port.lock);
509 if (!(get_dma_curr_irqstat(uart->tx_dma_channel)&DMA_RUN)) {
194de561 510 disable_dma(uart->tx_dma_channel);
0711d857 511 clear_dma_irqstat(uart->tx_dma_channel);
0efa4f2c
SZ		 512 /* Anomaly notes:
513 * 05000215 - we always clear ETBEI within last UART TX
514 * interrupt to end a string. It is always set
515 * when start a new tx.
516 */
f4d640c9 517 UART_CLEAR_IER(uart, ETBEI);
0711d857 518 uart->port.icount.tx += uart->tx_count;
239c25b1 519 if (!(xmit->tail == 0 && xmit->head == 0)) {
60f4b002 520 xmit->tail = (xmit->tail + uart->tx_count) & (UART_XMIT_SIZE - 1);
1b73351c 521
60f4b002
SZ		 522 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
523 uart_write_wakeup(&uart->port);
524 }
56f5de8f 525
1b73351c 526 bfin_serial_dma_tx_chars(uart);
194de561
BW		 527 }
528
529 spin_unlock(&uart->port.lock);
530 return IRQ_HANDLED;
531}
532
533static irqreturn_t bfin_serial_dma_rx_int(int irq, void *dev_id)
534{
535 struct bfin_serial_port *uart = dev_id;
3c2d0ed2 536 unsigned int irqstat;
35ff6935 537 int x_pos, pos;
0711d857 538
0f66e50a 539 spin_lock(&uart->rx_lock);
194de561
BW		 540 irqstat = get_dma_curr_irqstat(uart->rx_dma_channel);
541 clear_dma_irqstat(uart->rx_dma_channel);
8516c568
SZ		 542
543 uart->rx_dma_nrows = get_dma_curr_ycount(uart->rx_dma_channel);
35ff6935 544 x_pos = get_dma_curr_xcount(uart->rx_dma_channel);
8516c568 545 uart->rx_dma_nrows = DMA_RX_YCOUNT - uart->rx_dma_nrows;
35ff6935 546 if (uart->rx_dma_nrows == DMA_RX_YCOUNT || x_pos == 0)
8516c568
SZ		 547 uart->rx_dma_nrows = 0;
548
549 pos = uart->rx_dma_nrows * DMA_RX_XCOUNT;
550 if (pos > uart->rx_dma_buf.tail ||
551 uart->rx_dma_nrows < (uart->rx_dma_buf.tail/DMA_RX_XCOUNT)) {
552 uart->rx_dma_buf.head = pos;
553 bfin_serial_dma_rx_chars(uart);
554 uart->rx_dma_buf.tail = uart->rx_dma_buf.head;
555 }
556
0f66e50a 557 spin_unlock(&uart->rx_lock);
0aef4564 558
194de561
BW		 559 return IRQ_HANDLED;
560}
561#endif
562
563/*
564 * Return TIOCSER_TEMT when transmitter is not busy.
565 */
566static unsigned int bfin_serial_tx_empty(struct uart_port *port)
567{
568 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
3c2d0ed2 569 unsigned int lsr;
194de561
BW		 570
571 lsr = UART_GET_LSR(uart);
572 if (lsr & TEMT)
573 return TIOCSER_TEMT;
574 else
575 return 0;
576}
577
194de561
BW		 578static void bfin_serial_break_ctl(struct uart_port *port, int break_state)
579{
cf686762 580 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
59bd234b 581 u32 lcr = UART_GET_LCR(uart);
cf686762
MF		 582 if (break_state)
583 lcr |= SB;
584 else
585 lcr &= ~SB;
586 UART_PUT_LCR(uart, lcr);
587 SSYNC();
194de561
BW		 588}
589
590static int bfin_serial_startup(struct uart_port *port)
591{
592 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
593
594#ifdef CONFIG_SERIAL_BFIN_DMA
595 dma_addr_t dma_handle;
596
597 if (request_dma(uart->rx_dma_channel, "BFIN_UART_RX") < 0) {
598 printk(KERN_NOTICE "Unable to attach Blackfin UART RX DMA channel\n");
599 return -EBUSY;
600 }
601
602 if (request_dma(uart->tx_dma_channel, "BFIN_UART_TX") < 0) {
603 printk(KERN_NOTICE "Unable to attach Blackfin UART TX DMA channel\n");
604 free_dma(uart->rx_dma_channel);
605 return -EBUSY;
606 }
607
608 set_dma_callback(uart->rx_dma_channel, bfin_serial_dma_rx_int, uart);
609 set_dma_callback(uart->tx_dma_channel, bfin_serial_dma_tx_int, uart);
610
611 uart->rx_dma_buf.buf = (unsigned char *)dma_alloc_coherent(NULL, PAGE_SIZE, &dma_handle, GFP_DMA);
612 uart->rx_dma_buf.head = 0;
613 uart->rx_dma_buf.tail = 0;
614 uart->rx_dma_nrows = 0;
615
616 set_dma_config(uart->rx_dma_channel,
617 set_bfin_dma_config(DIR_WRITE, DMA_FLOW_AUTO,
618 INTR_ON_ROW, DIMENSION_2D,
2047e40d
MH		 619 DATA_SIZE_8,
620 DMA_SYNC_RESTART));
194de561
BW		 621 set_dma_x_count(uart->rx_dma_channel, DMA_RX_XCOUNT);
622 set_dma_x_modify(uart->rx_dma_channel, 1);
623 set_dma_y_count(uart->rx_dma_channel, DMA_RX_YCOUNT);
624 set_dma_y_modify(uart->rx_dma_channel, 1);
625 set_dma_start_addr(uart->rx_dma_channel, (unsigned long)uart->rx_dma_buf.buf);
626 enable_dma(uart->rx_dma_channel);
627
628 uart->rx_dma_timer.data = (unsigned long)(uart);
629 uart->rx_dma_timer.function = (void *)bfin_serial_rx_dma_timeout;
630 uart->rx_dma_timer.expires = jiffies + DMA_RX_FLUSH_JIFFIES;
631 add_timer(&(uart->rx_dma_timer));
632#else
6f95570e 633# if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \
52e15f0e
SZ		 634 defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE)
635 if (kgdboc_port_line == uart->port.line && kgdboc_break_enabled)
636 kgdboc_break_enabled = 0;
637 else {
638# endif
9cfb5c05 639 if (request_irq(uart->rx_irq, bfin_serial_rx_int, 0,
a359cca7 640 "BFIN_UART_RX", uart)) {
194de561
BW		 641 printk(KERN_NOTICE "Unable to attach BlackFin UART RX interrupt\n");
642 return -EBUSY;
643 }
644
645 if (request_irq
9cfb5c05 646 (uart->tx_irq, bfin_serial_tx_int, 0,
194de561
BW		 647 "BFIN_UART_TX", uart)) {
648 printk(KERN_NOTICE "Unable to attach BlackFin UART TX interrupt\n");
47918f05 649 free_irq(uart->rx_irq, uart);
194de561
BW		 650 return -EBUSY;
651 }
ab2375f2
SZ		 652
653# ifdef CONFIG_BF54x
654 {
b6100992
SZ		 655 /*
656 * UART2 and UART3 on BF548 share interrupt PINs and DMA
657 * controllers with SPORT2 and SPORT3. UART rx and tx
658 * interrupts are generated in PIO mode only when configure
659 * their peripheral mapping registers properly, which means
660 * request corresponding DMA channels in PIO mode as well.
661 */
ab2375f2
SZ		 662 unsigned uart_dma_ch_rx, uart_dma_ch_tx;
663
47918f05 664 switch (uart->rx_irq) {
ab2375f2
SZ		 665 case IRQ_UART3_RX:
666 uart_dma_ch_rx = CH_UART3_RX;
667 uart_dma_ch_tx = CH_UART3_TX;
668 break;
669 case IRQ_UART2_RX:
670 uart_dma_ch_rx = CH_UART2_RX;
671 uart_dma_ch_tx = CH_UART2_TX;
672 break;
673 default:
674 uart_dma_ch_rx = uart_dma_ch_tx = 0;
675 break;
fc811472 676 }
ab2375f2
SZ		 677
678 if (uart_dma_ch_rx &&
679 request_dma(uart_dma_ch_rx, "BFIN_UART_RX") < 0) {
680 printk(KERN_NOTICE"Fail to attach UART interrupt\n");
47918f05
SZ		 681 free_irq(uart->rx_irq, uart);
682 free_irq(uart->tx_irq, uart);
ab2375f2
SZ		 683 return -EBUSY;
684 }
685 if (uart_dma_ch_tx &&
686 request_dma(uart_dma_ch_tx, "BFIN_UART_TX") < 0) {
687 printk(KERN_NOTICE "Fail to attach UART interrupt\n");
688 free_dma(uart_dma_ch_rx);
47918f05
SZ		 689 free_irq(uart->rx_irq, uart);
690 free_irq(uart->tx_irq, uart);
ab2375f2
SZ		 691 return -EBUSY;
692 }
693 }
694# endif
6f95570e 695# if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \
52e15f0e
SZ		 696 defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE)
697 }
698# endif
6f95570e
SZ		 699#endif
700
701#ifdef CONFIG_SERIAL_BFIN_CTSRTS
702 if (uart->cts_pin >= 0) {
703 if (request_irq(gpio_to_irq(uart->cts_pin),
704 bfin_serial_mctrl_cts_int,
705 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING |
9cfb5c05 706 0, "BFIN_UART_CTS", uart)) {
6f95570e 707 uart->cts_pin = -1;
a89f2466 708 pr_info("Unable to attach BlackFin UART CTS interrupt. So, disable it.\n");
6f95570e
SZ		 709 }
710 }
32b44568
SZ		 711 if (uart->rts_pin >= 0) {
712 if (gpio_request(uart->rts_pin, DRIVER_NAME)) {
713 pr_info("fail to request RTS PIN at GPIO_%d\n", uart->rts_pin);
714 uart->rts_pin = -1;
715 } else
716 gpio_direction_output(uart->rts_pin, 0);
717 }
194de561 718#endif
d307d36a 719#ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
b48dc711
SZ		 720 if (uart->cts_pin >= 0) {
721 if (request_irq(uart->status_irq, bfin_serial_mctrl_cts_int,
190c6cc3 722 0, "BFIN_UART_MODEM_STATUS", uart)) {
b48dc711
SZ		 723 uart->cts_pin = -1;
724 dev_info(port->dev, "Unable to attach BlackFin UART Modem Status interrupt.\n");
725 }
d307d36a 726
b48dc711 727 /* CTS RTS PINs are negative assertive. */
3c2d0ed2 728 UART_PUT_MCR(uart, UART_GET_MCR(uart) | ACTS);
b48dc711
SZ		 729 UART_SET_IER(uart, EDSSI);
730 }
d307d36a
SZ		 731#endif
732
f4d640c9 733 UART_SET_IER(uart, ERBFI);
194de561
BW		 734 return 0;
735}
736
737static void bfin_serial_shutdown(struct uart_port *port)
738{
739 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
740
741#ifdef CONFIG_SERIAL_BFIN_DMA
742 disable_dma(uart->tx_dma_channel);
743 free_dma(uart->tx_dma_channel);
744 disable_dma(uart->rx_dma_channel);
745 free_dma(uart->rx_dma_channel);
746 del_timer(&(uart->rx_dma_timer));
75b780bd 747 dma_free_coherent(NULL, PAGE_SIZE, uart->rx_dma_buf.buf, 0);
194de561 748#else
ab2375f2
SZ		 749#ifdef CONFIG_BF54x
750 switch (uart->port.irq) {
751 case IRQ_UART3_RX:
752 free_dma(CH_UART3_RX);
753 free_dma(CH_UART3_TX);
754 break;
755 case IRQ_UART2_RX:
756 free_dma(CH_UART2_RX);
757 free_dma(CH_UART2_TX);
758 break;
759 default:
760 break;
fc811472 761 }
474f1a66 762#endif
47918f05
SZ		 763 free_irq(uart->rx_irq, uart);
764 free_irq(uart->tx_irq, uart);
194de561 765#endif
6f95570e 766
d307d36a 767#ifdef CONFIG_SERIAL_BFIN_CTSRTS
6f95570e
SZ		 768 if (uart->cts_pin >= 0)
769 free_irq(gpio_to_irq(uart->cts_pin), uart);
32b44568
SZ		 770 if (uart->rts_pin >= 0)
771 gpio_free(uart->rts_pin);
d307d36a
SZ		 772#endif
773#ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
57afb399 774 if (uart->cts_pin >= 0)
d307d36a
SZ		 775 free_irq(uart->status_irq, uart);
776#endif
194de561
BW		 777}
778
779static void
780bfin_serial_set_termios(struct uart_port *port, struct ktermios *termios,
781 struct ktermios *old)
782{
783 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
784 unsigned long flags;
785 unsigned int baud, quot;
3c2d0ed2 786 unsigned int ier, lcr = 0;
1cd3f2d2 787 unsigned long timeout;
194de561 788
8bd67d7d
PH		 789#ifdef CONFIG_SERIAL_BFIN_CTSRTS
790 if (old == NULL && uart->cts_pin != -1)
791 termios->c_cflag |= CRTSCTS;
792 else if (uart->cts_pin == -1)
793 termios->c_cflag &= ~CRTSCTS;
794#endif
795
194de561
BW		 796 switch (termios->c_cflag & CSIZE) {
797 case CS8:
798 lcr = WLS(8);
799 break;
800 case CS7:
801 lcr = WLS(7);
802 break;
803 case CS6:
804 lcr = WLS(6);
805 break;
806 case CS5:
807 lcr = WLS(5);
808 break;
809 default:
46e99c4a 810 printk(KERN_ERR "%s: word length not supported\n",
71cc2c21 811 __func__);
194de561
BW		 812 }
813
84507794
SZ		 814 /* Anomaly notes:
815 * 05000231 - STOP bit is always set to 1 whatever the user is set.
816 */
817 if (termios->c_cflag & CSTOPB) {
818 if (ANOMALY_05000231)
819 printk(KERN_WARNING "STOP bits other than 1 is not "
820 "supported in case of anomaly 05000231.\n");
821 else
822 lcr |= STB;
823 }
19aa6382 824 if (termios->c_cflag & PARENB)
194de561 825 lcr |= PEN;
19aa6382
MF		 826 if (!(termios->c_cflag & PARODD))
827 lcr |= EPS;
828 if (termios->c_cflag & CMSPAR)
829 lcr |= STP;
194de561 830
5bb06b62
SZ		 831 spin_lock_irqsave(&uart->port.lock, flags);
832
2ac5ee47
MF		 833 port->read_status_mask = OE;
834 if (termios->c_iflag & INPCK)
835 port->read_status_mask |= (FE | PE);
ef8b9ddc 836 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
2ac5ee47 837 port->read_status_mask |= BI;
194de561 838
2ac5ee47
MF		 839 /*
840 * Characters to ignore
841 */
842 port->ignore_status_mask = 0;
843 if (termios->c_iflag & IGNPAR)
844 port->ignore_status_mask |= FE | PE;
845 if (termios->c_iflag & IGNBRK) {
846 port->ignore_status_mask |= BI;
847 /*
848 * If we're ignoring parity and break indicators,
849 * ignore overruns too (for real raw support).
850 */
851 if (termios->c_iflag & IGNPAR)
852 port->ignore_status_mask |= OE;
853 }
194de561
BW		 854
855 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
ca3e442e
GY		 856 quot = uart_get_divisor(port, baud);
857
858 /* If discipline is not IRDA, apply ANOMALY_05000230 */
859 if (termios->c_line != N_IRDA)
860 quot -= ANOMALY_05000230;
861
8851c71e
MF		 862 UART_SET_ANOMALY_THRESHOLD(uart, USEC_PER_SEC / baud * 15);
863
1cd3f2d2
SZ		 864 /* Wait till the transfer buffer is empty */
865 timeout = jiffies + msecs_to_jiffies(10);
866 while (UART_GET_GCTL(uart) & UCEN && !(UART_GET_LSR(uart) & TEMT))
867 if (time_after(jiffies, timeout)) {
868 dev_warn(port->dev, "timeout waiting for TX buffer empty\n");
869 break;
870 }
871
194de561
BW		 872 /* Disable UART */
873 ier = UART_GET_IER(uart);
3c2d0ed2 874 UART_PUT_GCTL(uart, UART_GET_GCTL(uart) & ~UCEN);
1feaa51d 875 UART_DISABLE_INTS(uart);
194de561 876
b06d2f20 877 /* Set DLAB in LCR to Access CLK */
45828b81 878 UART_SET_DLAB(uart);
194de561 879
b06d2f20 880 UART_PUT_CLK(uart, quot);
194de561
BW		 881 SSYNC();
882
883 /* Clear DLAB in LCR to Access THR RBR IER */
45828b81 884 UART_CLEAR_DLAB(uart);
194de561 885
3c2d0ed2 886 UART_PUT_LCR(uart, (UART_GET_LCR(uart) & ~LCR_MASK) | lcr);
194de561
BW		 887
888 /* Enable UART */
1feaa51d 889 UART_ENABLE_INTS(uart, ier);
3c2d0ed2 890 UART_PUT_GCTL(uart, UART_GET_GCTL(uart) | UCEN);
194de561 891
b3ef5aba
GY		 892 /* Port speed changed, update the per-port timeout. */
893 uart_update_timeout(port, termios->c_cflag, baud);
894
194de561
BW		 895 spin_unlock_irqrestore(&uart->port.lock, flags);
896}
897
898static const char *bfin_serial_type(struct uart_port *port)
899{
900 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
901
902 return uart->port.type == PORT_BFIN ? "BFIN-UART" : NULL;
903}
904
905/*
906 * Release the memory region(s) being used by 'port'.
907 */
908static void bfin_serial_release_port(struct uart_port *port)
909{
910}
911
912/*
913 * Request the memory region(s) being used by 'port'.
914 */
915static int bfin_serial_request_port(struct uart_port *port)
916{
917 return 0;
918}
919
920/*
921 * Configure/autoconfigure the port.
922 */
923static void bfin_serial_config_port(struct uart_port *port, int flags)
924{
925 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
926
927 if (flags & UART_CONFIG_TYPE &&
928 bfin_serial_request_port(&uart->port) == 0)
929 uart->port.type = PORT_BFIN;
930}
931
932/*
933 * Verify the new serial_struct (for TIOCSSERIAL).
934 * The only change we allow are to the flags and type, and
935 * even then only between PORT_BFIN and PORT_UNKNOWN
936 */
937static int
938bfin_serial_verify_port(struct uart_port *port, struct serial_struct *ser)
939{
940 return 0;
941}
942
7d01b475
GY		 943/*
944 * Enable the IrDA function if tty->ldisc.num is N_IRDA.
945 * In other cases, disable IrDA function.
946 */
d87d9b7d 947static void bfin_serial_set_ldisc(struct uart_port *port, int ld)
7d01b475 948{
57afb399 949 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
3c2d0ed2 950 unsigned int val;
7d01b475 951
d87d9b7d 952 switch (ld) {
7d01b475 953 case N_IRDA:
57afb399 954 val = UART_GET_GCTL(uart);
b06d2f20 955 val |= (UMOD_IRDA | RPOLC);
57afb399 956 UART_PUT_GCTL(uart, val);
7d01b475
GY		 957 break;
958 default:
57afb399 959 val = UART_GET_GCTL(uart);
b06d2f20 960 val &= ~(UMOD_MASK | RPOLC);
57afb399 961 UART_PUT_GCTL(uart, val);
7d01b475
GY		 962 }
963}
964
6f95570e
SZ		 965static void bfin_serial_reset_irda(struct uart_port *port)
966{
57afb399 967 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
3c2d0ed2 968 unsigned int val;
6f95570e 969
57afb399 970 val = UART_GET_GCTL(uart);
b06d2f20 971 val &= ~(UMOD_MASK | RPOLC);
57afb399 972 UART_PUT_GCTL(uart, val);
6f95570e 973 SSYNC();
b06d2f20 974 val |= (UMOD_IRDA | RPOLC);
57afb399 975 UART_PUT_GCTL(uart, val);
6f95570e
SZ		 976 SSYNC();
977}
978
52e15f0e 979#ifdef CONFIG_CONSOLE_POLL
0efa4f2c
SZ		 980/* Anomaly notes:
981 * 05000099 - Because we only use THRE in poll_put and DR in poll_get,
982 * losing other bits of UART_LSR is not a problem here.
983 */
52e15f0e
SZ		 984static void bfin_serial_poll_put_char(struct uart_port *port, unsigned char chr)
985{
986 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
987
988 while (!(UART_GET_LSR(uart) & THRE))
989 cpu_relax();
990
991 UART_CLEAR_DLAB(uart);
992 UART_PUT_CHAR(uart, (unsigned char)chr);
993}
994
995static int bfin_serial_poll_get_char(struct uart_port *port)
996{
997 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
998 unsigned char chr;
999
1000 while (!(UART_GET_LSR(uart) & DR))
1001 cpu_relax();
1002
1003 UART_CLEAR_DLAB(uart);
1004 chr = UART_GET_CHAR(uart);
1005
1006 return chr;
1007}
1008#endif
1009
194de561
BW		 1010static struct uart_ops bfin_serial_pops = {
1011 .tx_empty = bfin_serial_tx_empty,
1012 .set_mctrl = bfin_serial_set_mctrl,
1013 .get_mctrl = bfin_serial_get_mctrl,
1014 .stop_tx = bfin_serial_stop_tx,
1015 .start_tx = bfin_serial_start_tx,
1016 .stop_rx = bfin_serial_stop_rx,
194de561
BW		 1017 .break_ctl = bfin_serial_break_ctl,
1018 .startup = bfin_serial_startup,
1019 .shutdown = bfin_serial_shutdown,
1020 .set_termios = bfin_serial_set_termios,
3b8458a9 1021 .set_ldisc = bfin_serial_set_ldisc,
194de561
BW		 1022 .type = bfin_serial_type,
1023 .release_port = bfin_serial_release_port,
1024 .request_port = bfin_serial_request_port,
1025 .config_port = bfin_serial_config_port,
1026 .verify_port = bfin_serial_verify_port,
52e15f0e
SZ		 1027#ifdef CONFIG_CONSOLE_POLL
1028 .poll_put_char = bfin_serial_poll_put_char,
1029 .poll_get_char = bfin_serial_poll_get_char,
1030#endif
194de561
BW		 1031};
1032
b6efa1ea 1033#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
194de561
BW		 1034/*
1035 * If the port was already initialised (eg, by a boot loader),
1036 * try to determine the current setup.
1037 */
1038static void __init
1039bfin_serial_console_get_options(struct bfin_serial_port *uart, int *baud,
1040 int *parity, int *bits)
1041{
3c2d0ed2 1042 unsigned int status;
194de561
BW		 1043
1044 status = UART_GET_IER(uart) & (ERBFI | ETBEI);
1045 if (status == (ERBFI | ETBEI)) {
1046 /* ok, the port was enabled */
59bd234b 1047 u32 lcr, clk;
194de561
BW		 1048
1049 lcr = UART_GET_LCR(uart);
1050
1051 *parity = 'n';
1052 if (lcr & PEN) {
1053 if (lcr & EPS)
1054 *parity = 'e';
1055 else
1056 *parity = 'o';
1057 }
59bd234b
SZ		 1058 *bits = ((lcr & WLS_MASK) >> WLS_OFFSET) + 5;
1059
b06d2f20 1060 /* Set DLAB in LCR to Access CLK */
45828b81 1061 UART_SET_DLAB(uart);
194de561 1062
b06d2f20 1063 clk = UART_GET_CLK(uart);
194de561
BW		 1064
1065 /* Clear DLAB in LCR to Access THR RBR IER */
45828b81 1066 UART_CLEAR_DLAB(uart);
194de561 1067
b06d2f20 1068 *baud = get_sclk() / (16*clk);
194de561 1069 }
71cc2c21 1070 pr_debug("%s:baud = %d, parity = %c, bits= %d\n", __func__, *baud, *parity, *bits);
194de561 1071}
0ae53640 1072
0ae53640 1073static struct uart_driver bfin_serial_reg;
194de561 1074
57afb399
SZ		 1075static void bfin_serial_console_putchar(struct uart_port *port, int ch)
1076{
1077 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
1078 while (!(UART_GET_LSR(uart) & THRE))
1079 barrier();
1080 UART_PUT_CHAR(uart, ch);
1081}
1082
1083#endif /* defined (CONFIG_SERIAL_BFIN_CONSOLE) ||
1084 defined (CONFIG_EARLY_PRINTK) */
1085
1086#ifdef CONFIG_SERIAL_BFIN_CONSOLE
1087#define CLASS_BFIN_CONSOLE "bfin-console"
1088/*
1089 * Interrupts are disabled on entering
1090 */
1091static void
1092bfin_serial_console_write(struct console *co, const char *s, unsigned int count)
1093{
1094 struct bfin_serial_port *uart = bfin_serial_ports[co->index];
1095 unsigned long flags;
1096
1097 spin_lock_irqsave(&uart->port.lock, flags);
1098 uart_console_write(&uart->port, s, count, bfin_serial_console_putchar);
1099 spin_unlock_irqrestore(&uart->port.lock, flags);
1100
1101}
1102
194de561
BW		 1103static int __init
1104bfin_serial_console_setup(struct console *co, char *options)
1105{
1106 struct bfin_serial_port *uart;
1107 int baud = 57600;
1108 int bits = 8;
1109 int parity = 'n';
d307d36a
SZ		 1110# if defined(CONFIG_SERIAL_BFIN_CTSRTS) || \
1111 defined(CONFIG_SERIAL_BFIN_HARD_CTSRTS)
194de561 1112 int flow = 'r';
b6efa1ea 1113# else
194de561 1114 int flow = 'n';
0ae53640 1115# endif
194de561
BW		 1116
1117 /*
1118 * Check whether an invalid uart number has been specified, and
1119 * if so, search for the first available port that does have
1120 * console support.
1121 */
57afb399
SZ		 1122 if (co->index < 0 || co->index >= BFIN_UART_NR_PORTS)
1123 return -ENODEV;
1124
1125 uart = bfin_serial_ports[co->index];
1126 if (!uart)
1127 return -ENODEV;
194de561
BW		 1128
1129 if (options)
1130 uart_parse_options(options, &baud, &parity, &bits, &flow);
1131 else
1132 bfin_serial_console_get_options(uart, &baud, &parity, &bits);
1133
1134 return uart_set_options(&uart->port, co, baud, parity, bits, flow);
0ae53640 1135}
194de561 1136
194de561 1137static struct console bfin_serial_console = {
57afb399 1138 .name = BFIN_SERIAL_DEV_NAME,
194de561
BW		 1139 .write = bfin_serial_console_write,
1140 .device = uart_console_device,
1141 .setup = bfin_serial_console_setup,
1142 .flags = CON_PRINTBUFFER,
1143 .index = -1,
1144 .data = &bfin_serial_reg,
1145};
bb7e58f8 1146#define BFIN_SERIAL_CONSOLE (&bfin_serial_console)
194de561
BW		 1147#else
1148#define BFIN_SERIAL_CONSOLE NULL
0ae53640
RG		 1149#endif /* CONFIG_SERIAL_BFIN_CONSOLE */
1150
57afb399
SZ		 1151#ifdef CONFIG_EARLY_PRINTK
1152static struct bfin_serial_port bfin_earlyprintk_port;
1153#define CLASS_BFIN_EARLYPRINTK "bfin-earlyprintk"
0ae53640 1154
57afb399
SZ		 1155/*
1156 * Interrupts are disabled on entering
1157 */
1158static void
1159bfin_earlyprintk_console_write(struct console *co, const char *s, unsigned int count)
0ae53640 1160{
57afb399 1161 unsigned long flags;
0ae53640 1162
57afb399
SZ		 1163 if (bfin_earlyprintk_port.port.line != co->index)
1164 return;
0ae53640 1165
57afb399
SZ		 1166 spin_lock_irqsave(&bfin_earlyprintk_port.port.lock, flags);
1167 uart_console_write(&bfin_earlyprintk_port.port, s, count,
1168 bfin_serial_console_putchar);
1169 spin_unlock_irqrestore(&bfin_earlyprintk_port.port.lock, flags);
0ae53640
RG		 1170}
1171
7de7c55b
RG		 1172/*
1173 * This should have a .setup or .early_setup in it, but then things get called
1174 * without the command line options, and the baud rate gets messed up - so
1175 * don't let the common infrastructure play with things. (see calls to setup
1176 * & earlysetup in ./kernel/printk.c:register_console()
1177 */
6734a834 1178static struct console bfin_early_serial_console __initdata = {
0ae53640 1179 .name = "early_BFuart",
57afb399 1180 .write = bfin_earlyprintk_console_write,
0ae53640
RG		 1181 .device = uart_console_device,
1182 .flags = CON_PRINTBUFFER,
0ae53640
RG		 1183 .index = -1,
1184 .data = &bfin_serial_reg,
1185};
6d9e4498
SZ		 1186#endif
1187
194de561
BW		 1188static struct uart_driver bfin_serial_reg = {
1189 .owner = THIS_MODULE,
57afb399
SZ		 1190 .driver_name = DRIVER_NAME,
1191 .dev_name = BFIN_SERIAL_DEV_NAME,
194de561
BW		 1192 .major = BFIN_SERIAL_MAJOR,
1193 .minor = BFIN_SERIAL_MINOR,
2ade9729 1194 .nr = BFIN_UART_NR_PORTS,
194de561
BW		 1195 .cons = BFIN_SERIAL_CONSOLE,
1196};
1197
57afb399 1198static int bfin_serial_suspend(struct platform_device *pdev, pm_message_t state)
194de561 1199{
57afb399 1200 struct bfin_serial_port *uart = platform_get_drvdata(pdev);
194de561 1201
57afb399
SZ		 1202 return uart_suspend_port(&bfin_serial_reg, &uart->port);
1203}
194de561 1204
57afb399
SZ		 1205static int bfin_serial_resume(struct platform_device *pdev)
1206{
1207 struct bfin_serial_port *uart = platform_get_drvdata(pdev);
1208
1209 return uart_resume_port(&bfin_serial_reg, &uart->port);
194de561
BW		 1210}
1211
57afb399 1212static int bfin_serial_probe(struct platform_device *pdev)
194de561 1213{
57afb399
SZ		 1214 struct resource *res;
1215 struct bfin_serial_port *uart = NULL;
1216 int ret = 0;
194de561 1217
57afb399
SZ		 1218 if (pdev->id < 0 || pdev->id >= BFIN_UART_NR_PORTS) {
1219 dev_err(&pdev->dev, "Wrong bfin uart platform device id.\n");
1220 return -ENOENT;
ccfbc3e1 1221 }
194de561 1222
57afb399 1223 if (bfin_serial_ports[pdev->id] == NULL) {
194de561 1224
57afb399
SZ		 1225 uart = kzalloc(sizeof(*uart), GFP_KERNEL);
1226 if (!uart) {
1227 dev_err(&pdev->dev,
1228 "fail to malloc bfin_serial_port\n");
1229 return -ENOMEM;
1230 }
1231 bfin_serial_ports[pdev->id] = uart;
194de561 1232
57afb399
SZ		 1233#ifdef CONFIG_EARLY_PRINTK
1234 if (!(bfin_earlyprintk_port.port.membase
1235 && bfin_earlyprintk_port.port.line == pdev->id)) {
1236 /*
1237 * If the peripheral PINs of current port is allocated
1238 * in earlyprintk probe stage, don't do it again.
1239 */
1240#endif
1241 ret = peripheral_request_list(
0e03e3f8 1242 dev_get_platdata(&pdev->dev),
574de559 1243 DRIVER_NAME);
57afb399
SZ		 1244 if (ret) {
1245 dev_err(&pdev->dev,
1246 "fail to request bfin serial peripherals\n");
1247 goto out_error_free_mem;
1248 }
1249#ifdef CONFIG_EARLY_PRINTK
1250 }
1251#endif
1252
1253 spin_lock_init(&uart->port.lock);
1254 uart->port.uartclk = get_sclk();
1255 uart->port.fifosize = BFIN_UART_TX_FIFO_SIZE;
1256 uart->port.ops = &bfin_serial_pops;
1257 uart->port.line = pdev->id;
1258 uart->port.iotype = UPIO_MEM;
1259 uart->port.flags = UPF_BOOT_AUTOCONF;
1260
1261 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1262 if (res == NULL) {
1263 dev_err(&pdev->dev, "Cannot get IORESOURCE_MEM\n");
1264 ret = -ENOENT;
1265 goto out_error_free_peripherals;
1266 }
1267
28f65c11 1268 uart->port.membase = ioremap(res->start, resource_size(res));
57afb399
SZ		 1269 if (!uart->port.membase) {
1270 dev_err(&pdev->dev, "Cannot map uart IO\n");
1271 ret = -ENXIO;
1272 goto out_error_free_peripherals;
1273 }
1274 uart->port.mapbase = res->start;
194de561 1275
47918f05
SZ		 1276 uart->tx_irq = platform_get_irq(pdev, 0);
1277 if (uart->tx_irq < 0) {
1278 dev_err(&pdev->dev, "No uart TX IRQ specified\n");
57afb399
SZ		 1279 ret = -ENOENT;
1280 goto out_error_unmap;
194de561 1281 }
57afb399 1282
47918f05
SZ		 1283 uart->rx_irq = platform_get_irq(pdev, 1);
1284 if (uart->rx_irq < 0) {
1285 dev_err(&pdev->dev, "No uart RX IRQ specified\n");
1286 ret = -ENOENT;
1287 goto out_error_unmap;
1288 }
1289 uart->port.irq = uart->rx_irq;
1290
1291 uart->status_irq = platform_get_irq(pdev, 2);
57afb399
SZ		 1292 if (uart->status_irq < 0) {
1293 dev_err(&pdev->dev, "No uart status IRQ specified\n");
1294 ret = -ENOENT;
1295 goto out_error_unmap;
1296 }
1297
1298#ifdef CONFIG_SERIAL_BFIN_DMA
0f66e50a 1299 spin_lock_init(&uart->rx_lock);
57afb399
SZ		 1300 uart->tx_done = 1;
1301 uart->tx_count = 0;
1302
1303 res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1304 if (res == NULL) {
1305 dev_err(&pdev->dev, "No uart TX DMA channel specified\n");
1306 ret = -ENOENT;
1307 goto out_error_unmap;
1308 }
1309 uart->tx_dma_channel = res->start;
1310
1311 res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
1312 if (res == NULL) {
1313 dev_err(&pdev->dev, "No uart RX DMA channel specified\n");
1314 ret = -ENOENT;
1315 goto out_error_unmap;
1316 }
1317 uart->rx_dma_channel = res->start;
1318
1319 init_timer(&(uart->rx_dma_timer));
1320#endif
1321
1322#if defined(CONFIG_SERIAL_BFIN_CTSRTS) || \
1323 defined(CONFIG_SERIAL_BFIN_HARD_CTSRTS)
1324 res = platform_get_resource(pdev, IORESOURCE_IO, 0);
1325 if (res == NULL)
1326 uart->cts_pin = -1;
8bd67d7d 1327 else
57afb399
SZ		 1328 uart->cts_pin = res->start;
1329
1330 res = platform_get_resource(pdev, IORESOURCE_IO, 1);
1331 if (res == NULL)
1332 uart->rts_pin = -1;
1333 else
1334 uart->rts_pin = res->start;
57afb399 1335#endif
194de561
BW		 1336 }
1337
57afb399
SZ		 1338#ifdef CONFIG_SERIAL_BFIN_CONSOLE
1339 if (!is_early_platform_device(pdev)) {
1340#endif
1341 uart = bfin_serial_ports[pdev->id];
1342 uart->port.dev = &pdev->dev;
1343 dev_set_drvdata(&pdev->dev, uart);
1344 ret = uart_add_one_port(&bfin_serial_reg, &uart->port);
1345#ifdef CONFIG_SERIAL_BFIN_CONSOLE
1346 }
1347#endif
1348
1349 if (!ret)
1350 return 0;
1351
1352 if (uart) {
1353out_error_unmap:
1354 iounmap(uart->port.membase);
1355out_error_free_peripherals:
0e03e3f8 1356 peripheral_free_list(dev_get_platdata(&pdev->dev));
57afb399
SZ		 1357out_error_free_mem:
1358 kfree(uart);
1359 bfin_serial_ports[pdev->id] = NULL;
1360 }
1361
1362 return ret;
194de561
BW		 1363}
1364
ae8d8a14 1365static int bfin_serial_remove(struct platform_device *pdev)
194de561 1366{
57afb399
SZ		 1367 struct bfin_serial_port *uart = platform_get_drvdata(pdev);
1368
1369 dev_set_drvdata(&pdev->dev, NULL);
1370
1371 if (uart) {
1372 uart_remove_one_port(&bfin_serial_reg, &uart->port);
57afb399 1373 iounmap(uart->port.membase);
0e03e3f8 1374 peripheral_free_list(dev_get_platdata(&pdev->dev));
57afb399
SZ		 1375 kfree(uart);
1376 bfin_serial_ports[pdev->id] = NULL;
ccfbc3e1 1377 }
194de561
BW		 1378
1379 return 0;
1380}
1381
1382static struct platform_driver bfin_serial_driver = {
1383 .probe = bfin_serial_probe,
2d47b716 1384 .remove = bfin_serial_remove,
194de561
BW		 1385 .suspend = bfin_serial_suspend,
1386 .resume = bfin_serial_resume,
1387 .driver = {
57afb399 1388 .name = DRIVER_NAME,
e169c139 1389 .owner = THIS_MODULE,
194de561
BW		 1390 },
1391};
1392
57afb399 1393#if defined(CONFIG_SERIAL_BFIN_CONSOLE)
6734a834 1394static struct early_platform_driver early_bfin_serial_driver __initdata = {
57afb399
SZ		 1395 .class_str = CLASS_BFIN_CONSOLE,
1396 .pdrv = &bfin_serial_driver,
1397 .requested_id = EARLY_PLATFORM_ID_UNSET,
1398};
1399
1400static int __init bfin_serial_rs_console_init(void)
1401{
1402 early_platform_driver_register(&early_bfin_serial_driver, DRIVER_NAME);
1403
1404 early_platform_driver_probe(CLASS_BFIN_CONSOLE, BFIN_UART_NR_PORTS, 0);
1405
1406 register_console(&bfin_serial_console);
1407
1408 return 0;
1409}
1410console_initcall(bfin_serial_rs_console_init);
1411#endif
1412
1413#ifdef CONFIG_EARLY_PRINTK
1414/*
1415 * Memory can't be allocated dynamically during earlyprink init stage.
1416 * So, do individual probe for earlyprink with a static uart port variable.
1417 */
1418static int bfin_earlyprintk_probe(struct platform_device *pdev)
194de561 1419{
57afb399 1420 struct resource *res;
194de561
BW		 1421 int ret;
1422
57afb399
SZ		 1423 if (pdev->id < 0 || pdev->id >= BFIN_UART_NR_PORTS) {
1424 dev_err(&pdev->dev, "Wrong earlyprintk platform device id.\n");
1425 return -ENOENT;
1426 }
1427
0e03e3f8
JH		 1428 ret = peripheral_request_list(dev_get_platdata(&pdev->dev),
1429 DRIVER_NAME);
57afb399
SZ		 1430 if (ret) {
1431 dev_err(&pdev->dev,
1432 "fail to request bfin serial peripherals\n");
1433 return ret;
1434 }
1435
1436 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1437 if (res == NULL) {
1438 dev_err(&pdev->dev, "Cannot get IORESOURCE_MEM\n");
1439 ret = -ENOENT;
1440 goto out_error_free_peripherals;
1441 }
1442
1443 bfin_earlyprintk_port.port.membase = ioremap(res->start,
28f65c11 1444 resource_size(res));
57afb399
SZ		 1445 if (!bfin_earlyprintk_port.port.membase) {
1446 dev_err(&pdev->dev, "Cannot map uart IO\n");
1447 ret = -ENXIO;
1448 goto out_error_free_peripherals;
1449 }
1450 bfin_earlyprintk_port.port.mapbase = res->start;
1451 bfin_earlyprintk_port.port.line = pdev->id;
1452 bfin_earlyprintk_port.port.uartclk = get_sclk();
1453 bfin_earlyprintk_port.port.fifosize = BFIN_UART_TX_FIFO_SIZE;
1454 spin_lock_init(&bfin_earlyprintk_port.port.lock);
1455
1456 return 0;
1457
1458out_error_free_peripherals:
0e03e3f8 1459 peripheral_free_list(dev_get_platdata(&pdev->dev));
57afb399
SZ		 1460
1461 return ret;
1462}
1463
1464static struct platform_driver bfin_earlyprintk_driver = {
1465 .probe = bfin_earlyprintk_probe,
1466 .driver = {
1467 .name = DRIVER_NAME,
1468 .owner = THIS_MODULE,
1469 },
1470};
1471
6734a834 1472static struct early_platform_driver early_bfin_earlyprintk_driver __initdata = {
57afb399
SZ		 1473 .class_str = CLASS_BFIN_EARLYPRINTK,
1474 .pdrv = &bfin_earlyprintk_driver,
1475 .requested_id = EARLY_PLATFORM_ID_UNSET,
1476};
1477
1478struct console __init *bfin_earlyserial_init(unsigned int port,
1479 unsigned int cflag)
1480{
1481 struct ktermios t;
1482 char port_name[20];
194de561 1483
57afb399
SZ		 1484 if (port < 0 || port >= BFIN_UART_NR_PORTS)
1485 return NULL;
1486
1487 /*
1488 * Only probe resource of the given port in earlyprintk boot arg.
1489 * The expected port id should be indicated in port name string.
1490 */
1491 snprintf(port_name, 20, DRIVER_NAME ".%d", port);
1492 early_platform_driver_register(&early_bfin_earlyprintk_driver,
1493 port_name);
1494 early_platform_driver_probe(CLASS_BFIN_EARLYPRINTK, 1, 0);
1495
1496 if (!bfin_earlyprintk_port.port.membase)
1497 return NULL;
1498
1499#ifdef CONFIG_SERIAL_BFIN_CONSOLE
1500 /*
1501 * If we are using early serial, don't let the normal console rewind
1502 * log buffer, since that causes things to be printed multiple times
1503 */
1504 bfin_serial_console.flags &= ~CON_PRINTBUFFER;
1505#endif
1506
1507 bfin_early_serial_console.index = port;
1508 t.c_cflag = cflag;
1509 t.c_iflag = 0;
1510 t.c_oflag = 0;
1511 t.c_lflag = ICANON;
1512 t.c_line = port;
1513 bfin_serial_set_termios(&bfin_earlyprintk_port.port, &t, &t);
1514
1515 return &bfin_early_serial_console;
1516}
1517#endif /* CONFIG_EARLY_PRINTK */
1518
1519static int __init bfin_serial_init(void)
1520{
1521 int ret;
1522
1523 pr_info("Blackfin serial driver\n");
194de561
BW		 1524
1525 ret = uart_register_driver(&bfin_serial_reg);
57afb399
SZ		 1526 if (ret) {
1527 pr_err("failed to register %s:%d\n",
1528 bfin_serial_reg.driver_name, ret);
1529 }
1530
1531 ret = platform_driver_register(&bfin_serial_driver);
1532 if (ret) {
1533 pr_err("fail to register bfin uart\n");
1534 uart_unregister_driver(&bfin_serial_reg);
194de561 1535 }
57afb399 1536
194de561
BW		 1537 return ret;
1538}
1539
1540static void __exit bfin_serial_exit(void)
1541{
1542 platform_driver_unregister(&bfin_serial_driver);
1543 uart_unregister_driver(&bfin_serial_reg);
1544}
1545
52e15f0e 1546
194de561
BW		 1547module_init(bfin_serial_init);
1548module_exit(bfin_serial_exit);
1549
57afb399 1550MODULE_AUTHOR("Sonic Zhang, Aubrey Li");
194de561
BW		 1551MODULE_DESCRIPTION("Blackfin generic serial port driver");
1552MODULE_LICENSE("GPL");
1553MODULE_ALIAS_CHARDEV_MAJOR(BFIN_SERIAL_MAJOR);
e169c139 1554MODULE_ALIAS("platform:bfin-uart");
Linux 6.x block layer and io_uring tree(s)