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tty: serial: Fix termios/port flags mismatch
[linux-2.6-block.git] / drivers / tty / serial / bfin_sport_uart.c
CommitLineData
2f351741 1/*
ccf68e59 2 * Blackfin On-Chip Sport Emulated UART Driver
2f351741 3 *
ccf68e59 4 * Copyright 2006-2009 Analog Devices Inc.
2f351741 5 *
ccf68e59 6 * Enter bugs at http://blackfin.uclinux.org/
2f351741 7 *
ccf68e59 8 * Licensed under the GPL-2 or later.
2f351741
BW		 9 */
10
11/*
12 * This driver and the hardware supported are in term of EE-191 of ADI.
631dd1a8 13 * http://www.analog.com/static/imported-files/application_notes/EE191.pdf
2f351741
BW		 14 * This application note describe how to implement a UART on a Sharc DSP,
15 * but this driver is implemented on Blackfin Processor.
ccf68e59 16 * Transmit Frame Sync is not used by this driver to transfer data out.
2f351741
BW		 17 */
18
ccf68e59 19/* #define DEBUG */
2f351741 20
ccf68e59 21#define DRV_NAME "bfin-sport-uart"
22#define DEVICE_NAME "ttySS"
23#define pr_fmt(fmt) DRV_NAME ": " fmt
2f351741
BW		 24
25#include <linux/module.h>
26#include <linux/ioport.h>
ccf68e59 27#include <linux/io.h>
2f351741
BW		 28#include <linux/init.h>
29#include <linux/console.h>
30#include <linux/sysrq.h>
5a0e3ad6 31#include <linux/slab.h>
2f351741
BW		 32#include <linux/platform_device.h>
33#include <linux/tty.h>
34#include <linux/tty_flip.h>
35#include <linux/serial_core.h>
36
2ce1efc9 37#include <asm/bfin_sport.h>
2f351741
BW		 38#include <asm/delay.h>
39#include <asm/portmux.h>
40
41#include "bfin_sport_uart.h"
42
2f351741
BW		 43struct sport_uart_port {
44 struct uart_port port;
2f351741 45 int err_irq;
ccf68e59 46 unsigned short csize;
47 unsigned short rxmask;
48 unsigned short txmask1;
49 unsigned short txmask2;
50 unsigned char stopb;
51/* unsigned char parib; */
1f7d1c85
SZ		 52#ifdef CONFIG_SERIAL_BFIN_SPORT_CTSRTS
53 int cts_pin;
54 int rts_pin;
55#endif
2f351741
BW		 56};
57
9356c461 58static int sport_uart_tx_chars(struct sport_uart_port *up);
2f351741
BW		 59static void sport_stop_tx(struct uart_port *port);
60
61static inline void tx_one_byte(struct sport_uart_port *up, unsigned int value)
62{
ccf68e59 63 pr_debug("%s value:%x, mask1=0x%x, mask2=0x%x\n", __func__, value,
64 up->txmask1, up->txmask2);
65
66 /* Place Start and Stop bits */
4328e3e5 67 __asm__ __volatile__ (
ccf68e59 68 "%[val] <<= 1;"
69 "%[val] = %[val] & %[mask1];"
70 "%[val] = %[val] | %[mask2];"
71 : [val]"+d"(value)
72 : [mask1]"d"(up->txmask1), [mask2]"d"(up->txmask2)
73 : "ASTAT"
4328e3e5 74 );
6ef53066 75 pr_debug("%s value:%x\n", __func__, value);
2f351741
BW		 76
77 SPORT_PUT_TX(up, value);
78}
79
ccf68e59 80static inline unsigned char rx_one_byte(struct sport_uart_port *up)
2f351741 81{
ccf68e59 82 unsigned int value;
83 unsigned char extract;
4328e3e5 84 u32 tmp_mask1, tmp_mask2, tmp_shift, tmp;
2f351741 85
ccf68e59 86 if ((up->csize + up->stopb) > 7)
87 value = SPORT_GET_RX32(up);
88 else
89 value = SPORT_GET_RX(up);
90
91 pr_debug("%s value:%x, cs=%d, mask=0x%x\n", __func__, value,
92 up->csize, up->rxmask);
2f351741 93
ccf68e59 94 /* Extract data */
4328e3e5
MF		 95 __asm__ __volatile__ (
96 "%[extr] = 0;"
ccf68e59 97 "%[mask1] = %[rxmask];"
98 "%[mask2] = 0x0200(Z);"
4328e3e5
MF		 99 "%[shift] = 0;"
100 "LSETUP(.Lloop_s, .Lloop_e) LC0 = %[lc];"
101 ".Lloop_s:"
102 "%[tmp] = extract(%[val], %[mask1].L)(Z);"
103 "%[tmp] <<= %[shift];"
104 "%[extr] = %[extr] | %[tmp];"
105 "%[mask1] = %[mask1] - %[mask2];"
106 ".Lloop_e:"
107 "%[shift] += 1;"
ccf68e59 108 : [extr]"=&d"(extract), [shift]"=&d"(tmp_shift), [tmp]"=&d"(tmp),
109 [mask1]"=&d"(tmp_mask1), [mask2]"=&d"(tmp_mask2)
110 : [val]"d"(value), [rxmask]"d"(up->rxmask), [lc]"a"(up->csize)
4328e3e5
MF		 111 : "ASTAT", "LB0", "LC0", "LT0"
112 );
2f351741
BW		 113
114 pr_debug(" extract:%x\n", extract);
115 return extract;
116}
117
ccf68e59 118static int sport_uart_setup(struct sport_uart_port *up, int size, int baud_rate)
2f351741 119{
ccf68e59 120 int tclkdiv, rclkdiv;
121 unsigned int sclk = get_sclk();
2f351741 122
ccf68e59 123 /* Set TCR1 and TCR2, TFSR is not enabled for uart */
33674691 124 SPORT_PUT_TCR1(up, (LATFS | ITFS | TFSR | TLSBIT | ITCLK));
ccf68e59 125 SPORT_PUT_TCR2(up, size + 1);
6ef53066 126 pr_debug("%s TCR1:%x, TCR2:%x\n", __func__, SPORT_GET_TCR1(up), SPORT_GET_TCR2(up));
2f351741
BW		 127
128 /* Set RCR1 and RCR2 */
129 SPORT_PUT_RCR1(up, (RCKFE | LARFS | LRFS | RFSR | IRCLK));
ccf68e59 130 SPORT_PUT_RCR2(up, (size + 1) * 2 - 1);
6ef53066 131 pr_debug("%s RCR1:%x, RCR2:%x\n", __func__, SPORT_GET_RCR1(up), SPORT_GET_RCR2(up));
2f351741 132
ccf68e59 133 tclkdiv = sclk / (2 * baud_rate) - 1;
0dd25df1
SZ		 134 /* The actual uart baud rate of devices vary between +/-2%. The sport
135 * RX sample rate should be faster than the double of the worst case,
136 * otherwise, wrong data are received. So, set sport RX clock to be
137 * 3% faster.
138 */
139 rclkdiv = sclk / (2 * baud_rate * 2 * 97 / 100) - 1;
2f351741 140 SPORT_PUT_TCLKDIV(up, tclkdiv);
2f351741
BW		 141 SPORT_PUT_RCLKDIV(up, rclkdiv);
142 SSYNC();
ccf68e59 143 pr_debug("%s sclk:%d, baud_rate:%d, tclkdiv:%d, rclkdiv:%d\n",
144 __func__, sclk, baud_rate, tclkdiv, rclkdiv);
2f351741
BW		 145
146 return 0;
147}
148
149static irqreturn_t sport_uart_rx_irq(int irq, void *dev_id)
150{
151 struct sport_uart_port *up = dev_id;
92a19f9c 152 struct tty_port *port = &up->port.state->port;
2f351741
BW		 153 unsigned int ch;
154
ccf68e59 155 spin_lock(&up->port.lock);
156
157 while (SPORT_GET_STAT(up) & RXNE) {
2f351741
BW		 158 ch = rx_one_byte(up);
159 up->port.icount.rx++;
160
ccf68e59 161 if (!uart_handle_sysrq_char(&up->port, ch))
92a19f9c 162 tty_insert_flip_char(port, ch, TTY_NORMAL);
ccf68e59 163 }
2f351741 164
ccf68e59 165 spin_unlock(&up->port.lock);
166
88c54a68
VK		 167 /* XXX this won't deadlock with lowlat? */
168 tty_flip_buffer_push(port);
169
2f351741
BW		 170 return IRQ_HANDLED;
171}
172
173static irqreturn_t sport_uart_tx_irq(int irq, void *dev_id)
174{
ccf68e59 175 struct sport_uart_port *up = dev_id;
176
177 spin_lock(&up->port.lock);
178 sport_uart_tx_chars(up);
179 spin_unlock(&up->port.lock);
2f351741
BW		 180
181 return IRQ_HANDLED;
182}
183
184static irqreturn_t sport_uart_err_irq(int irq, void *dev_id)
185{
186 struct sport_uart_port *up = dev_id;
2f351741
BW		 187 unsigned int stat = SPORT_GET_STAT(up);
188
ccf68e59 189 spin_lock(&up->port.lock);
190
2f351741
BW		 191 /* Overflow in RX FIFO */
192 if (stat & ROVF) {
193 up->port.icount.overrun++;
92a19f9c 194 tty_insert_flip_char(&up->port.state->port, 0, TTY_OVERRUN);
2f351741
BW		 195 SPORT_PUT_STAT(up, ROVF); /* Clear ROVF bit */
196 }
197 /* These should not happen */
198 if (stat & (TOVF | TUVF | RUVF)) {
ccf68e59 199 pr_err("SPORT Error:%s %s %s\n",
200 (stat & TOVF) ? "TX overflow" : "",
201 (stat & TUVF) ? "TX underflow" : "",
202 (stat & RUVF) ? "RX underflow" : "");
2f351741
BW		 203 SPORT_PUT_TCR1(up, SPORT_GET_TCR1(up) & ~TSPEN);
204 SPORT_PUT_RCR1(up, SPORT_GET_RCR1(up) & ~RSPEN);
205 }
206 SSYNC();
207
ccf68e59 208 spin_unlock(&up->port.lock);
92a19f9c
JS		 209 /* XXX we don't push the overrun bit to TTY? */
210
2f351741
BW		 211 return IRQ_HANDLED;
212}
213
1f7d1c85
SZ		 214#ifdef CONFIG_SERIAL_BFIN_SPORT_CTSRTS
215static unsigned int sport_get_mctrl(struct uart_port *port)
216{
217 struct sport_uart_port *up = (struct sport_uart_port *)port;
218 if (up->cts_pin < 0)
219 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
220
221 /* CTS PIN is negative assertive. */
222 if (SPORT_UART_GET_CTS(up))
223 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
224 else
225 return TIOCM_DSR | TIOCM_CAR;
226}
227
228static void sport_set_mctrl(struct uart_port *port, unsigned int mctrl)
229{
230 struct sport_uart_port *up = (struct sport_uart_port *)port;
231 if (up->rts_pin < 0)
232 return;
233
234 /* RTS PIN is negative assertive. */
235 if (mctrl & TIOCM_RTS)
236 SPORT_UART_ENABLE_RTS(up);
237 else
238 SPORT_UART_DISABLE_RTS(up);
239}
240
241/*
242 * Handle any change of modem status signal.
243 */
244static irqreturn_t sport_mctrl_cts_int(int irq, void *dev_id)
245{
246 struct sport_uart_port *up = (struct sport_uart_port *)dev_id;
247 unsigned int status;
248
249 status = sport_get_mctrl(&up->port);
250 uart_handle_cts_change(&up->port, status & TIOCM_CTS);
251
252 return IRQ_HANDLED;
253}
254#else
255static unsigned int sport_get_mctrl(struct uart_port *port)
256{
257 pr_debug("%s enter\n", __func__);
258 return TIOCM_CTS | TIOCM_CD | TIOCM_DSR;
259}
260
261static void sport_set_mctrl(struct uart_port *port, unsigned int mctrl)
262{
263 pr_debug("%s enter\n", __func__);
264}
265#endif
266
2f351741
BW		 267/* Reqeust IRQ, Setup clock */
268static int sport_startup(struct uart_port *port)
269{
270 struct sport_uart_port *up = (struct sport_uart_port *)port;
ccf68e59 271 int ret;
2f351741 272
6ef53066 273 pr_debug("%s enter\n", __func__);
ccf68e59 274 ret = request_irq(up->port.irq, sport_uart_rx_irq, 0,
275 "SPORT_UART_RX", up);
276 if (ret) {
277 dev_err(port->dev, "unable to request SPORT RX interrupt\n");
278 return ret;
2f351741
BW		 279 }
280
ccf68e59 281 ret = request_irq(up->port.irq+1, sport_uart_tx_irq, 0,
282 "SPORT_UART_TX", up);
283 if (ret) {
284 dev_err(port->dev, "unable to request SPORT TX interrupt\n");
2f351741
BW		 285 goto fail1;
286 }
287
ccf68e59 288 ret = request_irq(up->err_irq, sport_uart_err_irq, 0,
289 "SPORT_UART_STATUS", up);
290 if (ret) {
291 dev_err(port->dev, "unable to request SPORT status interrupt\n");
2f351741
BW		 292 goto fail2;
293 }
294
1f7d1c85
SZ		 295#ifdef CONFIG_SERIAL_BFIN_SPORT_CTSRTS
296 if (up->cts_pin >= 0) {
297 if (request_irq(gpio_to_irq(up->cts_pin),
298 sport_mctrl_cts_int,
299 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING |
9cfb5c05 300 0, "BFIN_SPORT_UART_CTS", up)) {
1f7d1c85 301 up->cts_pin = -1;
85ee7a1d 302 dev_info(port->dev, "Unable to attach BlackFin UART over SPORT CTS interrupt. So, disable it.\n");
1f7d1c85
SZ		 303 }
304 }
dc8f3703
SZ		 305 if (up->rts_pin >= 0) {
306 if (gpio_request(up->rts_pin, DRV_NAME)) {
307 dev_info(port->dev, "fail to request RTS PIN at GPIO_%d\n", up->rts_pin);
308 up->rts_pin = -1;
309 } else
310 gpio_direction_output(up->rts_pin, 0);
311 }
1f7d1c85
SZ		 312#endif
313
2f351741 314 return 0;
ccf68e59 315 fail2:
316 free_irq(up->port.irq+1, up);
317 fail1:
318 free_irq(up->port.irq, up);
2f351741 319
ccf68e59 320 return ret;
2f351741
BW		 321}
322
9356c461
SZ		 323/*
324 * sport_uart_tx_chars
325 *
326 * ret 1 means need to enable sport.
327 * ret 0 means do nothing.
328 */
329static int sport_uart_tx_chars(struct sport_uart_port *up)
2f351741 330{
ebd2c8f6 331 struct circ_buf *xmit = &up->port.state->xmit;
2f351741
BW		 332
333 if (SPORT_GET_STAT(up) & TXF)
9356c461 334 return 0;
2f351741
BW		 335
336 if (up->port.x_char) {
337 tx_one_byte(up, up->port.x_char);
338 up->port.icount.tx++;
339 up->port.x_char = 0;
9356c461 340 return 1;
2f351741
BW		 341 }
342
343 if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
3f3a978b
SZ		 344 /* The waiting loop to stop SPORT TX from TX interrupt is
345 * too long. This may block SPORT RX interrupts and cause
346 * RX FIFO overflow. So, do stop sport TX only after the last
347 * char in TX FIFO is moved into the shift register.
348 */
349 if (SPORT_GET_STAT(up) & TXHRE)
350 sport_stop_tx(&up->port);
9356c461 351 return 0;
2f351741
BW		 352 }
353
354 while(!(SPORT_GET_STAT(up) & TXF) && !uart_circ_empty(xmit)) {
355 tx_one_byte(up, xmit->buf[xmit->tail]);
356 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE -1);
357 up->port.icount.tx++;
358 }
359
360 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
361 uart_write_wakeup(&up->port);
9356c461
SZ		 362
363 return 1;
2f351741
BW		 364}
365
366static unsigned int sport_tx_empty(struct uart_port *port)
367{
368 struct sport_uart_port *up = (struct sport_uart_port *)port;
369 unsigned int stat;
370
371 stat = SPORT_GET_STAT(up);
6ef53066 372 pr_debug("%s stat:%04x\n", __func__, stat);
2f351741
BW		 373 if (stat & TXHRE) {
374 return TIOCSER_TEMT;
375 } else
376 return 0;
377}
378
2f351741
BW		 379static void sport_stop_tx(struct uart_port *port)
380{
381 struct sport_uart_port *up = (struct sport_uart_port *)port;
2f351741 382
6ef53066 383 pr_debug("%s enter\n", __func__);
2f351741 384
9356c461
SZ		 385 if (!(SPORT_GET_TCR1(up) & TSPEN))
386 return;
387
2f351741 388 /* Although the hold register is empty, last byte is still in shift
ccf68e59 389 * register and not sent out yet. So, put a dummy data into TX FIFO.
390 * Then, sport tx stops when last byte is shift out and the dummy
391 * data is moved into the shift register.
392 */
393 SPORT_PUT_TX(up, 0xffff);
394 while (!(SPORT_GET_STAT(up) & TXHRE))
395 cpu_relax();
2f351741
BW		 396
397 SPORT_PUT_TCR1(up, (SPORT_GET_TCR1(up) & ~TSPEN));
398 SSYNC();
399
400 return;
401}
402
403static void sport_start_tx(struct uart_port *port)
404{
405 struct sport_uart_port *up = (struct sport_uart_port *)port;
406
6ef53066 407 pr_debug("%s enter\n", __func__);
ccf68e59 408
2f351741 409 /* Write data into SPORT FIFO before enable SPROT to transmit */
9356c461
SZ		 410 if (sport_uart_tx_chars(up)) {
411 /* Enable transmit, then an interrupt will generated */
412 SPORT_PUT_TCR1(up, (SPORT_GET_TCR1(up) | TSPEN));
413 SSYNC();
414 }
2f351741 415
6ef53066 416 pr_debug("%s exit\n", __func__);
2f351741
BW		 417}
418
419static void sport_stop_rx(struct uart_port *port)
420{
421 struct sport_uart_port *up = (struct sport_uart_port *)port;
422
6ef53066 423 pr_debug("%s enter\n", __func__);
2f351741
BW		 424 /* Disable sport to stop rx */
425 SPORT_PUT_RCR1(up, (SPORT_GET_RCR1(up) & ~RSPEN));
426 SSYNC();
427}
428
2f351741
BW		 429static void sport_break_ctl(struct uart_port *port, int break_state)
430{
6ef53066 431 pr_debug("%s enter\n", __func__);
2f351741
BW		 432}
433
434static void sport_shutdown(struct uart_port *port)
435{
436 struct sport_uart_port *up = (struct sport_uart_port *)port;
437
ccf68e59 438 dev_dbg(port->dev, "%s enter\n", __func__);
2f351741
BW		 439
440 /* Disable sport */
441 SPORT_PUT_TCR1(up, (SPORT_GET_TCR1(up) & ~TSPEN));
442 SPORT_PUT_RCR1(up, (SPORT_GET_RCR1(up) & ~RSPEN));
443 SSYNC();
444
ccf68e59 445 free_irq(up->port.irq, up);
446 free_irq(up->port.irq+1, up);
2f351741 447 free_irq(up->err_irq, up);
1f7d1c85
SZ		 448#ifdef CONFIG_SERIAL_BFIN_SPORT_CTSRTS
449 if (up->cts_pin >= 0)
450 free_irq(gpio_to_irq(up->cts_pin), up);
dc8f3703
SZ		 451 if (up->rts_pin >= 0)
452 gpio_free(up->rts_pin);
1f7d1c85 453#endif
2f351741
BW		 454}
455
2f351741
BW		 456static const char *sport_type(struct uart_port *port)
457{
458 struct sport_uart_port *up = (struct sport_uart_port *)port;
459
6ef53066 460 pr_debug("%s enter\n", __func__);
ccf68e59 461 return up->port.type == PORT_BFIN_SPORT ? "BFIN-SPORT-UART" : NULL;
2f351741
BW		 462}
463
464static void sport_release_port(struct uart_port *port)
465{
6ef53066 466 pr_debug("%s enter\n", __func__);
2f351741
BW		 467}
468
469static int sport_request_port(struct uart_port *port)
470{
6ef53066 471 pr_debug("%s enter\n", __func__);
2f351741
BW		 472 return 0;
473}
474
475static void sport_config_port(struct uart_port *port, int flags)
476{
477 struct sport_uart_port *up = (struct sport_uart_port *)port;
478
6ef53066 479 pr_debug("%s enter\n", __func__);
2f351741
BW		 480 up->port.type = PORT_BFIN_SPORT;
481}
482
483static int sport_verify_port(struct uart_port *port, struct serial_struct *ser)
484{
6ef53066 485 pr_debug("%s enter\n", __func__);
2f351741
BW		 486 return 0;
487}
488
ccf68e59 489static void sport_set_termios(struct uart_port *port,
490 struct ktermios *termios, struct ktermios *old)
491{
492 struct sport_uart_port *up = (struct sport_uart_port *)port;
493 unsigned long flags;
494 int i;
495
496 pr_debug("%s enter, c_cflag:%08x\n", __func__, termios->c_cflag);
497
498 switch (termios->c_cflag & CSIZE) {
499 case CS8:
500 up->csize = 8;
501 break;
502 case CS7:
503 up->csize = 7;
504 break;
505 case CS6:
506 up->csize = 6;
507 break;
508 case CS5:
509 up->csize = 5;
510 break;
511 default:
512 pr_warning("requested word length not supported\n");
513 }
514
515 if (termios->c_cflag & CSTOPB) {
516 up->stopb = 1;
517 }
518 if (termios->c_cflag & PARENB) {
519 pr_warning("PAREN bits is not supported yet\n");
520 /* up->parib = 1; */
521 }
522
9498dc95
SZ		 523 spin_lock_irqsave(&up->port.lock, flags);
524
60bd940f 525 port->read_status_mask = 0;
ccf68e59 526
527 /*
528 * Characters to ignore
529 */
530 port->ignore_status_mask = 0;
ccf68e59 531
532 /* RX extract mask */
533 up->rxmask = 0x01 | (((up->csize + up->stopb) * 2 - 1) << 0x8);
534 /* TX masks, 8 bit data and 1 bit stop for example:
535 * mask1 = b#0111111110
536 * mask2 = b#1000000000
537 */
538 for (i = 0, up->txmask1 = 0; i < up->csize; i++)
539 up->txmask1 |= (1<<i);
540 up->txmask2 = (1<<i);
541 if (up->stopb) {
542 ++i;
543 up->txmask2 |= (1<<i);
544 }
545 up->txmask1 <<= 1;
546 up->txmask2 <<= 1;
547 /* uart baud rate */
548 port->uartclk = uart_get_baud_rate(port, termios, old, 0, get_sclk()/16);
549
ccf68e59 550 /* Disable UART */
551 SPORT_PUT_TCR1(up, SPORT_GET_TCR1(up) & ~TSPEN);
552 SPORT_PUT_RCR1(up, SPORT_GET_RCR1(up) & ~RSPEN);
553
554 sport_uart_setup(up, up->csize + up->stopb, port->uartclk);
555
556 /* driver TX line high after config, one dummy data is
557 * necessary to stop sport after shift one byte
558 */
559 SPORT_PUT_TX(up, 0xffff);
560 SPORT_PUT_TX(up, 0xffff);
561 SPORT_PUT_TCR1(up, (SPORT_GET_TCR1(up) | TSPEN));
562 SSYNC();
563 while (!(SPORT_GET_STAT(up) & TXHRE))
564 cpu_relax();
565 SPORT_PUT_TCR1(up, SPORT_GET_TCR1(up) & ~TSPEN);
566 SSYNC();
567
568 /* Port speed changed, update the per-port timeout. */
569 uart_update_timeout(port, termios->c_cflag, port->uartclk);
570
571 /* Enable sport rx */
572 SPORT_PUT_RCR1(up, SPORT_GET_RCR1(up) | RSPEN);
573 SSYNC();
574
575 spin_unlock_irqrestore(&up->port.lock, flags);
576}
577
2f351741
BW		 578struct uart_ops sport_uart_ops = {
579 .tx_empty = sport_tx_empty,
580 .set_mctrl = sport_set_mctrl,
581 .get_mctrl = sport_get_mctrl,
582 .stop_tx = sport_stop_tx,
583 .start_tx = sport_start_tx,
584 .stop_rx = sport_stop_rx,
2f351741
BW		 585 .break_ctl = sport_break_ctl,
586 .startup = sport_startup,
587 .shutdown = sport_shutdown,
588 .set_termios = sport_set_termios,
589 .type = sport_type,
590 .release_port = sport_release_port,
591 .request_port = sport_request_port,
592 .config_port = sport_config_port,
593 .verify_port = sport_verify_port,
594};
595
ccf68e59 596#define BFIN_SPORT_UART_MAX_PORTS 4
597
598static struct sport_uart_port *bfin_sport_uart_ports[BFIN_SPORT_UART_MAX_PORTS];
599
600#ifdef CONFIG_SERIAL_BFIN_SPORT_CONSOLE
b59588aa
SZ		 601#define CLASS_BFIN_SPORT_CONSOLE "bfin-sport-console"
602
ccf68e59 603static int __init
604sport_uart_console_setup(struct console *co, char *options)
605{
606 struct sport_uart_port *up;
607 int baud = 57600;
608 int bits = 8;
609 int parity = 'n';
1f7d1c85
SZ		 610# ifdef CONFIG_SERIAL_BFIN_SPORT_CTSRTS
611 int flow = 'r';
612# else
ccf68e59 613 int flow = 'n';
1f7d1c85 614# endif
ccf68e59 615
616 /* Check whether an invalid uart number has been specified */
617 if (co->index < 0 || co->index >= BFIN_SPORT_UART_MAX_PORTS)
618 return -ENODEV;
619
620 up = bfin_sport_uart_ports[co->index];
621 if (!up)
622 return -ENODEV;
623
624 if (options)
625 uart_parse_options(options, &baud, &parity, &bits, &flow);
626
627 return uart_set_options(&up->port, co, baud, parity, bits, flow);
628}
629
630static void sport_uart_console_putchar(struct uart_port *port, int ch)
631{
632 struct sport_uart_port *up = (struct sport_uart_port *)port;
633
634 while (SPORT_GET_STAT(up) & TXF)
635 barrier();
636
637 tx_one_byte(up, ch);
638}
639
640/*
641 * Interrupts are disabled on entering
642 */
643static void
644sport_uart_console_write(struct console *co, const char *s, unsigned int count)
645{
646 struct sport_uart_port *up = bfin_sport_uart_ports[co->index];
647 unsigned long flags;
648
649 spin_lock_irqsave(&up->port.lock, flags);
650
651 if (SPORT_GET_TCR1(up) & TSPEN)
652 uart_console_write(&up->port, s, count, sport_uart_console_putchar);
653 else {
654 /* dummy data to start sport */
655 while (SPORT_GET_STAT(up) & TXF)
656 barrier();
657 SPORT_PUT_TX(up, 0xffff);
658 /* Enable transmit, then an interrupt will generated */
659 SPORT_PUT_TCR1(up, (SPORT_GET_TCR1(up) | TSPEN));
660 SSYNC();
661
662 uart_console_write(&up->port, s, count, sport_uart_console_putchar);
663
664 /* Although the hold register is empty, last byte is still in shift
665 * register and not sent out yet. So, put a dummy data into TX FIFO.
666 * Then, sport tx stops when last byte is shift out and the dummy
667 * data is moved into the shift register.
668 */
669 while (SPORT_GET_STAT(up) & TXF)
670 barrier();
671 SPORT_PUT_TX(up, 0xffff);
672 while (!(SPORT_GET_STAT(up) & TXHRE))
673 barrier();
674
675 /* Stop sport tx transfer */
676 SPORT_PUT_TCR1(up, (SPORT_GET_TCR1(up) & ~TSPEN));
677 SSYNC();
2f351741 678 }
ccf68e59 679
680 spin_unlock_irqrestore(&up->port.lock, flags);
681}
682
683static struct uart_driver sport_uart_reg;
684
685static struct console sport_uart_console = {
686 .name = DEVICE_NAME,
687 .write = sport_uart_console_write,
688 .device = uart_console_device,
689 .setup = sport_uart_console_setup,
690 .flags = CON_PRINTBUFFER,
691 .index = -1,
692 .data = &sport_uart_reg,
2f351741
BW		 693};
694
ccf68e59 695#define SPORT_UART_CONSOLE (&sport_uart_console)
696#else
697#define SPORT_UART_CONSOLE NULL
698#endif /* CONFIG_SERIAL_BFIN_SPORT_CONSOLE */
699
700
2f351741
BW		 701static struct uart_driver sport_uart_reg = {
702 .owner = THIS_MODULE,
ccf68e59 703 .driver_name = DRV_NAME,
704 .dev_name = DEVICE_NAME,
2f351741
BW		 705 .major = 204,
706 .minor = 84,
ccf68e59 707 .nr = BFIN_SPORT_UART_MAX_PORTS,
708 .cons = SPORT_UART_CONSOLE,
2f351741
BW		 709};
710
ccf68e59 711#ifdef CONFIG_PM
712static int sport_uart_suspend(struct device *dev)
2f351741 713{
ccf68e59 714 struct sport_uart_port *sport = dev_get_drvdata(dev);
2f351741 715
ccf68e59 716 dev_dbg(dev, "%s enter\n", __func__);
2f351741
BW		 717 if (sport)
718 uart_suspend_port(&sport_uart_reg, &sport->port);
719
720 return 0;
721}
722
ccf68e59 723static int sport_uart_resume(struct device *dev)
2f351741 724{
ccf68e59 725 struct sport_uart_port *sport = dev_get_drvdata(dev);
2f351741 726
ccf68e59 727 dev_dbg(dev, "%s enter\n", __func__);
2f351741
BW		 728 if (sport)
729 uart_resume_port(&sport_uart_reg, &sport->port);
730
731 return 0;
732}
733
ccf68e59 734static struct dev_pm_ops bfin_sport_uart_dev_pm_ops = {
735 .suspend = sport_uart_suspend,
736 .resume = sport_uart_resume,
737};
738#endif
739
9671f099 740static int sport_uart_probe(struct platform_device *pdev)
2f351741 741{
ccf68e59 742 struct resource *res;
743 struct sport_uart_port *sport;
744 int ret = 0;
2f351741 745
ccf68e59 746 dev_dbg(&pdev->dev, "%s enter\n", __func__);
747
748 if (pdev->id < 0 || pdev->id >= BFIN_SPORT_UART_MAX_PORTS) {
749 dev_err(&pdev->dev, "Wrong sport uart platform device id.\n");
750 return -ENOENT;
751 }
752
753 if (bfin_sport_uart_ports[pdev->id] == NULL) {
754 bfin_sport_uart_ports[pdev->id] =
f4d10ca8 755 kzalloc(sizeof(struct sport_uart_port), GFP_KERNEL);
ccf68e59 756 sport = bfin_sport_uart_ports[pdev->id];
757 if (!sport) {
758 dev_err(&pdev->dev,
f4d10ca8 759 "Fail to malloc sport_uart_port\n");
ccf68e59 760 return -ENOMEM;
761 }
762
aaba105e
JH		 763 ret = peripheral_request_list(dev_get_platdata(&pdev->dev),
764 DRV_NAME);
ccf68e59 765 if (ret) {
766 dev_err(&pdev->dev,
767 "Fail to request SPORT peripherals\n");
768 goto out_error_free_mem;
769 }
770
771 spin_lock_init(&sport->port.lock);
772 sport->port.fifosize = SPORT_TX_FIFO_SIZE,
773 sport->port.ops = &sport_uart_ops;
774 sport->port.line = pdev->id;
775 sport->port.iotype = UPIO_MEM;
776 sport->port.flags = UPF_BOOT_AUTOCONF;
777
778 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
779 if (res == NULL) {
780 dev_err(&pdev->dev, "Cannot get IORESOURCE_MEM\n");
781 ret = -ENOENT;
782 goto out_error_free_peripherals;
783 }
784
e114474c 785 sport->port.membase = ioremap(res->start, resource_size(res));
ccf68e59 786 if (!sport->port.membase) {
787 dev_err(&pdev->dev, "Cannot map sport IO\n");
788 ret = -ENXIO;
789 goto out_error_free_peripherals;
790 }
e8126b32 791 sport->port.mapbase = res->start;
ccf68e59 792
793 sport->port.irq = platform_get_irq(pdev, 0);
940f3be4 794 if ((int)sport->port.irq < 0) {
ccf68e59 795 dev_err(&pdev->dev, "No sport RX/TX IRQ specified\n");
796 ret = -ENOENT;
797 goto out_error_unmap;
798 }
799
800 sport->err_irq = platform_get_irq(pdev, 1);
801 if (sport->err_irq < 0) {
802 dev_err(&pdev->dev, "No sport status IRQ specified\n");
803 ret = -ENOENT;
804 goto out_error_unmap;
805 }
1f7d1c85
SZ		 806#ifdef CONFIG_SERIAL_BFIN_SPORT_CTSRTS
807 res = platform_get_resource(pdev, IORESOURCE_IO, 0);
808 if (res == NULL)
809 sport->cts_pin = -1;
cee3948d 810 else {
1f7d1c85 811 sport->cts_pin = res->start;
cee3948d
SZ		 812 sport->port.flags |= ASYNC_CTS_FLOW;
813 }
1f7d1c85
SZ		 814
815 res = platform_get_resource(pdev, IORESOURCE_IO, 1);
816 if (res == NULL)
817 sport->rts_pin = -1;
818 else
819 sport->rts_pin = res->start;
1f7d1c85 820#endif
ccf68e59 821 }
822
823#ifdef CONFIG_SERIAL_BFIN_SPORT_CONSOLE
824 if (!is_early_platform_device(pdev)) {
825#endif
826 sport = bfin_sport_uart_ports[pdev->id];
827 sport->port.dev = &pdev->dev;
828 dev_set_drvdata(&pdev->dev, sport);
829 ret = uart_add_one_port(&sport_uart_reg, &sport->port);
830#ifdef CONFIG_SERIAL_BFIN_SPORT_CONSOLE
831 }
832#endif
833 if (!ret)
834 return 0;
835
836 if (sport) {
837out_error_unmap:
838 iounmap(sport->port.membase);
839out_error_free_peripherals:
aaba105e 840 peripheral_free_list(dev_get_platdata(&pdev->dev));
ccf68e59 841out_error_free_mem:
842 kfree(sport);
843 bfin_sport_uart_ports[pdev->id] = NULL;
844 }
845
846 return ret;
2f351741
BW		 847}
848
ae8d8a14 849static int sport_uart_remove(struct platform_device *pdev)
2f351741 850{
ccf68e59 851 struct sport_uart_port *sport = platform_get_drvdata(pdev);
2f351741 852
ccf68e59 853 dev_dbg(&pdev->dev, "%s enter\n", __func__);
854 dev_set_drvdata(&pdev->dev, NULL);
2f351741 855
ccf68e59 856 if (sport) {
2f351741 857 uart_remove_one_port(&sport_uart_reg, &sport->port);
ccf68e59 858 iounmap(sport->port.membase);
aaba105e 859 peripheral_free_list(dev_get_platdata(&pdev->dev));
ccf68e59 860 kfree(sport);
861 bfin_sport_uart_ports[pdev->id] = NULL;
862 }
2f351741
BW		 863
864 return 0;
865}
866
867static struct platform_driver sport_uart_driver = {
868 .probe = sport_uart_probe,
2d47b716 869 .remove = sport_uart_remove,
2f351741
BW		 870 .driver = {
871 .name = DRV_NAME,
ccf68e59 872#ifdef CONFIG_PM
873 .pm = &bfin_sport_uart_dev_pm_ops,
874#endif
2f351741
BW		 875 },
876};
877
ccf68e59 878#ifdef CONFIG_SERIAL_BFIN_SPORT_CONSOLE
20246fdf 879static struct early_platform_driver early_sport_uart_driver __initdata = {
b59588aa 880 .class_str = CLASS_BFIN_SPORT_CONSOLE,
ccf68e59 881 .pdrv = &sport_uart_driver,
882 .requested_id = EARLY_PLATFORM_ID_UNSET,
883};
884
885static int __init sport_uart_rs_console_init(void)
886{
887 early_platform_driver_register(&early_sport_uart_driver, DRV_NAME);
888
b59588aa
SZ		 889 early_platform_driver_probe(CLASS_BFIN_SPORT_CONSOLE,
890 BFIN_SPORT_UART_MAX_PORTS, 0);
ccf68e59 891
892 register_console(&sport_uart_console);
893
894 return 0;
895}
896console_initcall(sport_uart_rs_console_init);
897#endif
898
2f351741
BW		 899static int __init sport_uart_init(void)
900{
901 int ret;
902
e8126b32 903 pr_info("Blackfin uart over sport driver\n");
ccf68e59 904
2f351741 905 ret = uart_register_driver(&sport_uart_reg);
ccf68e59 906 if (ret) {
907 pr_err("failed to register %s:%d\n",
2f351741
BW		 908 sport_uart_reg.driver_name, ret);
909 return ret;
910 }
911
912 ret = platform_driver_register(&sport_uart_driver);
ccf68e59 913 if (ret) {
914 pr_err("failed to register sport uart driver:%d\n", ret);
2f351741
BW		 915 uart_unregister_driver(&sport_uart_reg);
916 }
917
2f351741
BW		 918 return ret;
919}
ccf68e59 920module_init(sport_uart_init);
2f351741
BW		 921
922static void __exit sport_uart_exit(void)
923{
2f351741
BW		 924 platform_driver_unregister(&sport_uart_driver);
925 uart_unregister_driver(&sport_uart_reg);
926}
2f351741
BW		 927module_exit(sport_uart_exit);
928
ccf68e59 929MODULE_AUTHOR("Sonic Zhang, Roy Huang");
930MODULE_DESCRIPTION("Blackfin serial over SPORT driver");
2f351741 931MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)