Commit | Line | Data |
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2f351741 | 1 | /* |
ccf68e59 | 2 | * Blackfin On-Chip Sport Emulated UART Driver |
2f351741 | 3 | * |
ccf68e59 | 4 | * Copyright 2006-2009 Analog Devices Inc. |
2f351741 | 5 | * |
ccf68e59 | 6 | * Enter bugs at http://blackfin.uclinux.org/ |
2f351741 | 7 | * |
ccf68e59 | 8 | * Licensed under the GPL-2 or later. |
2f351741 BW |
9 | */ |
10 | ||
11 | /* | |
12 | * This driver and the hardware supported are in term of EE-191 of ADI. | |
631dd1a8 | 13 | * http://www.analog.com/static/imported-files/application_notes/EE191.pdf |
2f351741 BW |
14 | * This application note describe how to implement a UART on a Sharc DSP, |
15 | * but this driver is implemented on Blackfin Processor. | |
ccf68e59 | 16 | * Transmit Frame Sync is not used by this driver to transfer data out. |
2f351741 BW |
17 | */ |
18 | ||
ccf68e59 | 19 | /* #define DEBUG */ |
2f351741 | 20 | |
ccf68e59 | 21 | #define DRV_NAME "bfin-sport-uart" |
22 | #define DEVICE_NAME "ttySS" | |
23 | #define pr_fmt(fmt) DRV_NAME ": " fmt | |
2f351741 BW |
24 | |
25 | #include <linux/module.h> | |
26 | #include <linux/ioport.h> | |
ccf68e59 | 27 | #include <linux/io.h> |
2f351741 BW |
28 | #include <linux/init.h> |
29 | #include <linux/console.h> | |
30 | #include <linux/sysrq.h> | |
5a0e3ad6 | 31 | #include <linux/slab.h> |
2f351741 BW |
32 | #include <linux/platform_device.h> |
33 | #include <linux/tty.h> | |
34 | #include <linux/tty_flip.h> | |
35 | #include <linux/serial_core.h> | |
36 | ||
2ce1efc9 | 37 | #include <asm/bfin_sport.h> |
2f351741 BW |
38 | #include <asm/delay.h> |
39 | #include <asm/portmux.h> | |
40 | ||
41 | #include "bfin_sport_uart.h" | |
42 | ||
2f351741 BW |
43 | struct sport_uart_port { |
44 | struct uart_port port; | |
2f351741 | 45 | int err_irq; |
ccf68e59 | 46 | unsigned short csize; |
47 | unsigned short rxmask; | |
48 | unsigned short txmask1; | |
49 | unsigned short txmask2; | |
50 | unsigned char stopb; | |
51 | /* unsigned char parib; */ | |
1f7d1c85 SZ |
52 | #ifdef CONFIG_SERIAL_BFIN_SPORT_CTSRTS |
53 | int cts_pin; | |
54 | int rts_pin; | |
55 | #endif | |
2f351741 BW |
56 | }; |
57 | ||
9356c461 | 58 | static int sport_uart_tx_chars(struct sport_uart_port *up); |
2f351741 BW |
59 | static void sport_stop_tx(struct uart_port *port); |
60 | ||
61 | static inline void tx_one_byte(struct sport_uart_port *up, unsigned int value) | |
62 | { | |
ccf68e59 | 63 | pr_debug("%s value:%x, mask1=0x%x, mask2=0x%x\n", __func__, value, |
64 | up->txmask1, up->txmask2); | |
65 | ||
66 | /* Place Start and Stop bits */ | |
4328e3e5 | 67 | __asm__ __volatile__ ( |
ccf68e59 | 68 | "%[val] <<= 1;" |
69 | "%[val] = %[val] & %[mask1];" | |
70 | "%[val] = %[val] | %[mask2];" | |
71 | : [val]"+d"(value) | |
72 | : [mask1]"d"(up->txmask1), [mask2]"d"(up->txmask2) | |
73 | : "ASTAT" | |
4328e3e5 | 74 | ); |
6ef53066 | 75 | pr_debug("%s value:%x\n", __func__, value); |
2f351741 BW |
76 | |
77 | SPORT_PUT_TX(up, value); | |
78 | } | |
79 | ||
ccf68e59 | 80 | static inline unsigned char rx_one_byte(struct sport_uart_port *up) |
2f351741 | 81 | { |
ccf68e59 | 82 | unsigned int value; |
83 | unsigned char extract; | |
4328e3e5 | 84 | u32 tmp_mask1, tmp_mask2, tmp_shift, tmp; |
2f351741 | 85 | |
ccf68e59 | 86 | if ((up->csize + up->stopb) > 7) |
87 | value = SPORT_GET_RX32(up); | |
88 | else | |
89 | value = SPORT_GET_RX(up); | |
90 | ||
91 | pr_debug("%s value:%x, cs=%d, mask=0x%x\n", __func__, value, | |
92 | up->csize, up->rxmask); | |
2f351741 | 93 | |
ccf68e59 | 94 | /* Extract data */ |
4328e3e5 MF |
95 | __asm__ __volatile__ ( |
96 | "%[extr] = 0;" | |
ccf68e59 | 97 | "%[mask1] = %[rxmask];" |
98 | "%[mask2] = 0x0200(Z);" | |
4328e3e5 MF |
99 | "%[shift] = 0;" |
100 | "LSETUP(.Lloop_s, .Lloop_e) LC0 = %[lc];" | |
101 | ".Lloop_s:" | |
102 | "%[tmp] = extract(%[val], %[mask1].L)(Z);" | |
103 | "%[tmp] <<= %[shift];" | |
104 | "%[extr] = %[extr] | %[tmp];" | |
105 | "%[mask1] = %[mask1] - %[mask2];" | |
106 | ".Lloop_e:" | |
107 | "%[shift] += 1;" | |
ccf68e59 | 108 | : [extr]"=&d"(extract), [shift]"=&d"(tmp_shift), [tmp]"=&d"(tmp), |
109 | [mask1]"=&d"(tmp_mask1), [mask2]"=&d"(tmp_mask2) | |
110 | : [val]"d"(value), [rxmask]"d"(up->rxmask), [lc]"a"(up->csize) | |
4328e3e5 MF |
111 | : "ASTAT", "LB0", "LC0", "LT0" |
112 | ); | |
2f351741 BW |
113 | |
114 | pr_debug(" extract:%x\n", extract); | |
115 | return extract; | |
116 | } | |
117 | ||
ccf68e59 | 118 | static int sport_uart_setup(struct sport_uart_port *up, int size, int baud_rate) |
2f351741 | 119 | { |
ccf68e59 | 120 | int tclkdiv, rclkdiv; |
121 | unsigned int sclk = get_sclk(); | |
2f351741 | 122 | |
ccf68e59 | 123 | /* Set TCR1 and TCR2, TFSR is not enabled for uart */ |
33674691 | 124 | SPORT_PUT_TCR1(up, (LATFS | ITFS | TFSR | TLSBIT | ITCLK)); |
ccf68e59 | 125 | SPORT_PUT_TCR2(up, size + 1); |
6ef53066 | 126 | pr_debug("%s TCR1:%x, TCR2:%x\n", __func__, SPORT_GET_TCR1(up), SPORT_GET_TCR2(up)); |
2f351741 BW |
127 | |
128 | /* Set RCR1 and RCR2 */ | |
129 | SPORT_PUT_RCR1(up, (RCKFE | LARFS | LRFS | RFSR | IRCLK)); | |
ccf68e59 | 130 | SPORT_PUT_RCR2(up, (size + 1) * 2 - 1); |
6ef53066 | 131 | pr_debug("%s RCR1:%x, RCR2:%x\n", __func__, SPORT_GET_RCR1(up), SPORT_GET_RCR2(up)); |
2f351741 | 132 | |
ccf68e59 | 133 | tclkdiv = sclk / (2 * baud_rate) - 1; |
0dd25df1 SZ |
134 | /* The actual uart baud rate of devices vary between +/-2%. The sport |
135 | * RX sample rate should be faster than the double of the worst case, | |
136 | * otherwise, wrong data are received. So, set sport RX clock to be | |
137 | * 3% faster. | |
138 | */ | |
139 | rclkdiv = sclk / (2 * baud_rate * 2 * 97 / 100) - 1; | |
2f351741 | 140 | SPORT_PUT_TCLKDIV(up, tclkdiv); |
2f351741 BW |
141 | SPORT_PUT_RCLKDIV(up, rclkdiv); |
142 | SSYNC(); | |
ccf68e59 | 143 | pr_debug("%s sclk:%d, baud_rate:%d, tclkdiv:%d, rclkdiv:%d\n", |
144 | __func__, sclk, baud_rate, tclkdiv, rclkdiv); | |
2f351741 BW |
145 | |
146 | return 0; | |
147 | } | |
148 | ||
149 | static irqreturn_t sport_uart_rx_irq(int irq, void *dev_id) | |
150 | { | |
151 | struct sport_uart_port *up = dev_id; | |
ebd2c8f6 | 152 | struct tty_struct *tty = up->port.state->port.tty; |
2f351741 BW |
153 | unsigned int ch; |
154 | ||
ccf68e59 | 155 | spin_lock(&up->port.lock); |
156 | ||
157 | while (SPORT_GET_STAT(up) & RXNE) { | |
2f351741 BW |
158 | ch = rx_one_byte(up); |
159 | up->port.icount.rx++; | |
160 | ||
ccf68e59 | 161 | if (!uart_handle_sysrq_char(&up->port, ch)) |
2f351741 | 162 | tty_insert_flip_char(tty, ch, TTY_NORMAL); |
ccf68e59 | 163 | } |
2f351741 BW |
164 | tty_flip_buffer_push(tty); |
165 | ||
ccf68e59 | 166 | spin_unlock(&up->port.lock); |
167 | ||
2f351741 BW |
168 | return IRQ_HANDLED; |
169 | } | |
170 | ||
171 | static irqreturn_t sport_uart_tx_irq(int irq, void *dev_id) | |
172 | { | |
ccf68e59 | 173 | struct sport_uart_port *up = dev_id; |
174 | ||
175 | spin_lock(&up->port.lock); | |
176 | sport_uart_tx_chars(up); | |
177 | spin_unlock(&up->port.lock); | |
2f351741 BW |
178 | |
179 | return IRQ_HANDLED; | |
180 | } | |
181 | ||
182 | static irqreturn_t sport_uart_err_irq(int irq, void *dev_id) | |
183 | { | |
184 | struct sport_uart_port *up = dev_id; | |
ebd2c8f6 | 185 | struct tty_struct *tty = up->port.state->port.tty; |
2f351741 BW |
186 | unsigned int stat = SPORT_GET_STAT(up); |
187 | ||
ccf68e59 | 188 | spin_lock(&up->port.lock); |
189 | ||
2f351741 BW |
190 | /* Overflow in RX FIFO */ |
191 | if (stat & ROVF) { | |
192 | up->port.icount.overrun++; | |
193 | tty_insert_flip_char(tty, 0, TTY_OVERRUN); | |
194 | SPORT_PUT_STAT(up, ROVF); /* Clear ROVF bit */ | |
195 | } | |
196 | /* These should not happen */ | |
197 | if (stat & (TOVF | TUVF | RUVF)) { | |
ccf68e59 | 198 | pr_err("SPORT Error:%s %s %s\n", |
199 | (stat & TOVF) ? "TX overflow" : "", | |
200 | (stat & TUVF) ? "TX underflow" : "", | |
201 | (stat & RUVF) ? "RX underflow" : ""); | |
2f351741 BW |
202 | SPORT_PUT_TCR1(up, SPORT_GET_TCR1(up) & ~TSPEN); |
203 | SPORT_PUT_RCR1(up, SPORT_GET_RCR1(up) & ~RSPEN); | |
204 | } | |
205 | SSYNC(); | |
206 | ||
ccf68e59 | 207 | spin_unlock(&up->port.lock); |
2f351741 BW |
208 | return IRQ_HANDLED; |
209 | } | |
210 | ||
1f7d1c85 SZ |
211 | #ifdef CONFIG_SERIAL_BFIN_SPORT_CTSRTS |
212 | static unsigned int sport_get_mctrl(struct uart_port *port) | |
213 | { | |
214 | struct sport_uart_port *up = (struct sport_uart_port *)port; | |
215 | if (up->cts_pin < 0) | |
216 | return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR; | |
217 | ||
218 | /* CTS PIN is negative assertive. */ | |
219 | if (SPORT_UART_GET_CTS(up)) | |
220 | return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR; | |
221 | else | |
222 | return TIOCM_DSR | TIOCM_CAR; | |
223 | } | |
224 | ||
225 | static void sport_set_mctrl(struct uart_port *port, unsigned int mctrl) | |
226 | { | |
227 | struct sport_uart_port *up = (struct sport_uart_port *)port; | |
228 | if (up->rts_pin < 0) | |
229 | return; | |
230 | ||
231 | /* RTS PIN is negative assertive. */ | |
232 | if (mctrl & TIOCM_RTS) | |
233 | SPORT_UART_ENABLE_RTS(up); | |
234 | else | |
235 | SPORT_UART_DISABLE_RTS(up); | |
236 | } | |
237 | ||
238 | /* | |
239 | * Handle any change of modem status signal. | |
240 | */ | |
241 | static irqreturn_t sport_mctrl_cts_int(int irq, void *dev_id) | |
242 | { | |
243 | struct sport_uart_port *up = (struct sport_uart_port *)dev_id; | |
244 | unsigned int status; | |
245 | ||
246 | status = sport_get_mctrl(&up->port); | |
247 | uart_handle_cts_change(&up->port, status & TIOCM_CTS); | |
248 | ||
249 | return IRQ_HANDLED; | |
250 | } | |
251 | #else | |
252 | static unsigned int sport_get_mctrl(struct uart_port *port) | |
253 | { | |
254 | pr_debug("%s enter\n", __func__); | |
255 | return TIOCM_CTS | TIOCM_CD | TIOCM_DSR; | |
256 | } | |
257 | ||
258 | static void sport_set_mctrl(struct uart_port *port, unsigned int mctrl) | |
259 | { | |
260 | pr_debug("%s enter\n", __func__); | |
261 | } | |
262 | #endif | |
263 | ||
2f351741 BW |
264 | /* Reqeust IRQ, Setup clock */ |
265 | static int sport_startup(struct uart_port *port) | |
266 | { | |
267 | struct sport_uart_port *up = (struct sport_uart_port *)port; | |
ccf68e59 | 268 | int ret; |
2f351741 | 269 | |
6ef53066 | 270 | pr_debug("%s enter\n", __func__); |
ccf68e59 | 271 | ret = request_irq(up->port.irq, sport_uart_rx_irq, 0, |
272 | "SPORT_UART_RX", up); | |
273 | if (ret) { | |
274 | dev_err(port->dev, "unable to request SPORT RX interrupt\n"); | |
275 | return ret; | |
2f351741 BW |
276 | } |
277 | ||
ccf68e59 | 278 | ret = request_irq(up->port.irq+1, sport_uart_tx_irq, 0, |
279 | "SPORT_UART_TX", up); | |
280 | if (ret) { | |
281 | dev_err(port->dev, "unable to request SPORT TX interrupt\n"); | |
2f351741 BW |
282 | goto fail1; |
283 | } | |
284 | ||
ccf68e59 | 285 | ret = request_irq(up->err_irq, sport_uart_err_irq, 0, |
286 | "SPORT_UART_STATUS", up); | |
287 | if (ret) { | |
288 | dev_err(port->dev, "unable to request SPORT status interrupt\n"); | |
2f351741 BW |
289 | goto fail2; |
290 | } | |
291 | ||
1f7d1c85 SZ |
292 | #ifdef CONFIG_SERIAL_BFIN_SPORT_CTSRTS |
293 | if (up->cts_pin >= 0) { | |
294 | if (request_irq(gpio_to_irq(up->cts_pin), | |
295 | sport_mctrl_cts_int, | |
296 | IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING | | |
9cfb5c05 | 297 | 0, "BFIN_SPORT_UART_CTS", up)) { |
1f7d1c85 | 298 | up->cts_pin = -1; |
85ee7a1d | 299 | dev_info(port->dev, "Unable to attach BlackFin UART over SPORT CTS interrupt. So, disable it.\n"); |
1f7d1c85 SZ |
300 | } |
301 | } | |
dc8f3703 SZ |
302 | if (up->rts_pin >= 0) { |
303 | if (gpio_request(up->rts_pin, DRV_NAME)) { | |
304 | dev_info(port->dev, "fail to request RTS PIN at GPIO_%d\n", up->rts_pin); | |
305 | up->rts_pin = -1; | |
306 | } else | |
307 | gpio_direction_output(up->rts_pin, 0); | |
308 | } | |
1f7d1c85 SZ |
309 | #endif |
310 | ||
2f351741 | 311 | return 0; |
ccf68e59 | 312 | fail2: |
313 | free_irq(up->port.irq+1, up); | |
314 | fail1: | |
315 | free_irq(up->port.irq, up); | |
2f351741 | 316 | |
ccf68e59 | 317 | return ret; |
2f351741 BW |
318 | } |
319 | ||
9356c461 SZ |
320 | /* |
321 | * sport_uart_tx_chars | |
322 | * | |
323 | * ret 1 means need to enable sport. | |
324 | * ret 0 means do nothing. | |
325 | */ | |
326 | static int sport_uart_tx_chars(struct sport_uart_port *up) | |
2f351741 | 327 | { |
ebd2c8f6 | 328 | struct circ_buf *xmit = &up->port.state->xmit; |
2f351741 BW |
329 | |
330 | if (SPORT_GET_STAT(up) & TXF) | |
9356c461 | 331 | return 0; |
2f351741 BW |
332 | |
333 | if (up->port.x_char) { | |
334 | tx_one_byte(up, up->port.x_char); | |
335 | up->port.icount.tx++; | |
336 | up->port.x_char = 0; | |
9356c461 | 337 | return 1; |
2f351741 BW |
338 | } |
339 | ||
340 | if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) { | |
3f3a978b SZ |
341 | /* The waiting loop to stop SPORT TX from TX interrupt is |
342 | * too long. This may block SPORT RX interrupts and cause | |
343 | * RX FIFO overflow. So, do stop sport TX only after the last | |
344 | * char in TX FIFO is moved into the shift register. | |
345 | */ | |
346 | if (SPORT_GET_STAT(up) & TXHRE) | |
347 | sport_stop_tx(&up->port); | |
9356c461 | 348 | return 0; |
2f351741 BW |
349 | } |
350 | ||
351 | while(!(SPORT_GET_STAT(up) & TXF) && !uart_circ_empty(xmit)) { | |
352 | tx_one_byte(up, xmit->buf[xmit->tail]); | |
353 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE -1); | |
354 | up->port.icount.tx++; | |
355 | } | |
356 | ||
357 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
358 | uart_write_wakeup(&up->port); | |
9356c461 SZ |
359 | |
360 | return 1; | |
2f351741 BW |
361 | } |
362 | ||
363 | static unsigned int sport_tx_empty(struct uart_port *port) | |
364 | { | |
365 | struct sport_uart_port *up = (struct sport_uart_port *)port; | |
366 | unsigned int stat; | |
367 | ||
368 | stat = SPORT_GET_STAT(up); | |
6ef53066 | 369 | pr_debug("%s stat:%04x\n", __func__, stat); |
2f351741 BW |
370 | if (stat & TXHRE) { |
371 | return TIOCSER_TEMT; | |
372 | } else | |
373 | return 0; | |
374 | } | |
375 | ||
2f351741 BW |
376 | static void sport_stop_tx(struct uart_port *port) |
377 | { | |
378 | struct sport_uart_port *up = (struct sport_uart_port *)port; | |
2f351741 | 379 | |
6ef53066 | 380 | pr_debug("%s enter\n", __func__); |
2f351741 | 381 | |
9356c461 SZ |
382 | if (!(SPORT_GET_TCR1(up) & TSPEN)) |
383 | return; | |
384 | ||
2f351741 | 385 | /* Although the hold register is empty, last byte is still in shift |
ccf68e59 | 386 | * register and not sent out yet. So, put a dummy data into TX FIFO. |
387 | * Then, sport tx stops when last byte is shift out and the dummy | |
388 | * data is moved into the shift register. | |
389 | */ | |
390 | SPORT_PUT_TX(up, 0xffff); | |
391 | while (!(SPORT_GET_STAT(up) & TXHRE)) | |
392 | cpu_relax(); | |
2f351741 BW |
393 | |
394 | SPORT_PUT_TCR1(up, (SPORT_GET_TCR1(up) & ~TSPEN)); | |
395 | SSYNC(); | |
396 | ||
397 | return; | |
398 | } | |
399 | ||
400 | static void sport_start_tx(struct uart_port *port) | |
401 | { | |
402 | struct sport_uart_port *up = (struct sport_uart_port *)port; | |
403 | ||
6ef53066 | 404 | pr_debug("%s enter\n", __func__); |
ccf68e59 | 405 | |
2f351741 | 406 | /* Write data into SPORT FIFO before enable SPROT to transmit */ |
9356c461 SZ |
407 | if (sport_uart_tx_chars(up)) { |
408 | /* Enable transmit, then an interrupt will generated */ | |
409 | SPORT_PUT_TCR1(up, (SPORT_GET_TCR1(up) | TSPEN)); | |
410 | SSYNC(); | |
411 | } | |
2f351741 | 412 | |
6ef53066 | 413 | pr_debug("%s exit\n", __func__); |
2f351741 BW |
414 | } |
415 | ||
416 | static void sport_stop_rx(struct uart_port *port) | |
417 | { | |
418 | struct sport_uart_port *up = (struct sport_uart_port *)port; | |
419 | ||
6ef53066 | 420 | pr_debug("%s enter\n", __func__); |
2f351741 BW |
421 | /* Disable sport to stop rx */ |
422 | SPORT_PUT_RCR1(up, (SPORT_GET_RCR1(up) & ~RSPEN)); | |
423 | SSYNC(); | |
424 | } | |
425 | ||
426 | static void sport_enable_ms(struct uart_port *port) | |
427 | { | |
6ef53066 | 428 | pr_debug("%s enter\n", __func__); |
2f351741 BW |
429 | } |
430 | ||
431 | static void sport_break_ctl(struct uart_port *port, int break_state) | |
432 | { | |
6ef53066 | 433 | pr_debug("%s enter\n", __func__); |
2f351741 BW |
434 | } |
435 | ||
436 | static void sport_shutdown(struct uart_port *port) | |
437 | { | |
438 | struct sport_uart_port *up = (struct sport_uart_port *)port; | |
439 | ||
ccf68e59 | 440 | dev_dbg(port->dev, "%s enter\n", __func__); |
2f351741 BW |
441 | |
442 | /* Disable sport */ | |
443 | SPORT_PUT_TCR1(up, (SPORT_GET_TCR1(up) & ~TSPEN)); | |
444 | SPORT_PUT_RCR1(up, (SPORT_GET_RCR1(up) & ~RSPEN)); | |
445 | SSYNC(); | |
446 | ||
ccf68e59 | 447 | free_irq(up->port.irq, up); |
448 | free_irq(up->port.irq+1, up); | |
2f351741 | 449 | free_irq(up->err_irq, up); |
1f7d1c85 SZ |
450 | #ifdef CONFIG_SERIAL_BFIN_SPORT_CTSRTS |
451 | if (up->cts_pin >= 0) | |
452 | free_irq(gpio_to_irq(up->cts_pin), up); | |
dc8f3703 SZ |
453 | if (up->rts_pin >= 0) |
454 | gpio_free(up->rts_pin); | |
1f7d1c85 | 455 | #endif |
2f351741 BW |
456 | } |
457 | ||
2f351741 BW |
458 | static const char *sport_type(struct uart_port *port) |
459 | { | |
460 | struct sport_uart_port *up = (struct sport_uart_port *)port; | |
461 | ||
6ef53066 | 462 | pr_debug("%s enter\n", __func__); |
ccf68e59 | 463 | return up->port.type == PORT_BFIN_SPORT ? "BFIN-SPORT-UART" : NULL; |
2f351741 BW |
464 | } |
465 | ||
466 | static void sport_release_port(struct uart_port *port) | |
467 | { | |
6ef53066 | 468 | pr_debug("%s enter\n", __func__); |
2f351741 BW |
469 | } |
470 | ||
471 | static int sport_request_port(struct uart_port *port) | |
472 | { | |
6ef53066 | 473 | pr_debug("%s enter\n", __func__); |
2f351741 BW |
474 | return 0; |
475 | } | |
476 | ||
477 | static void sport_config_port(struct uart_port *port, int flags) | |
478 | { | |
479 | struct sport_uart_port *up = (struct sport_uart_port *)port; | |
480 | ||
6ef53066 | 481 | pr_debug("%s enter\n", __func__); |
2f351741 BW |
482 | up->port.type = PORT_BFIN_SPORT; |
483 | } | |
484 | ||
485 | static int sport_verify_port(struct uart_port *port, struct serial_struct *ser) | |
486 | { | |
6ef53066 | 487 | pr_debug("%s enter\n", __func__); |
2f351741 BW |
488 | return 0; |
489 | } | |
490 | ||
ccf68e59 | 491 | static void sport_set_termios(struct uart_port *port, |
492 | struct ktermios *termios, struct ktermios *old) | |
493 | { | |
494 | struct sport_uart_port *up = (struct sport_uart_port *)port; | |
495 | unsigned long flags; | |
496 | int i; | |
497 | ||
498 | pr_debug("%s enter, c_cflag:%08x\n", __func__, termios->c_cflag); | |
499 | ||
500 | switch (termios->c_cflag & CSIZE) { | |
501 | case CS8: | |
502 | up->csize = 8; | |
503 | break; | |
504 | case CS7: | |
505 | up->csize = 7; | |
506 | break; | |
507 | case CS6: | |
508 | up->csize = 6; | |
509 | break; | |
510 | case CS5: | |
511 | up->csize = 5; | |
512 | break; | |
513 | default: | |
514 | pr_warning("requested word length not supported\n"); | |
515 | } | |
516 | ||
517 | if (termios->c_cflag & CSTOPB) { | |
518 | up->stopb = 1; | |
519 | } | |
520 | if (termios->c_cflag & PARENB) { | |
521 | pr_warning("PAREN bits is not supported yet\n"); | |
522 | /* up->parib = 1; */ | |
523 | } | |
524 | ||
9498dc95 SZ |
525 | spin_lock_irqsave(&up->port.lock, flags); |
526 | ||
60bd940f | 527 | port->read_status_mask = 0; |
ccf68e59 | 528 | |
529 | /* | |
530 | * Characters to ignore | |
531 | */ | |
532 | port->ignore_status_mask = 0; | |
ccf68e59 | 533 | |
534 | /* RX extract mask */ | |
535 | up->rxmask = 0x01 | (((up->csize + up->stopb) * 2 - 1) << 0x8); | |
536 | /* TX masks, 8 bit data and 1 bit stop for example: | |
537 | * mask1 = b#0111111110 | |
538 | * mask2 = b#1000000000 | |
539 | */ | |
540 | for (i = 0, up->txmask1 = 0; i < up->csize; i++) | |
541 | up->txmask1 |= (1<<i); | |
542 | up->txmask2 = (1<<i); | |
543 | if (up->stopb) { | |
544 | ++i; | |
545 | up->txmask2 |= (1<<i); | |
546 | } | |
547 | up->txmask1 <<= 1; | |
548 | up->txmask2 <<= 1; | |
549 | /* uart baud rate */ | |
550 | port->uartclk = uart_get_baud_rate(port, termios, old, 0, get_sclk()/16); | |
551 | ||
ccf68e59 | 552 | /* Disable UART */ |
553 | SPORT_PUT_TCR1(up, SPORT_GET_TCR1(up) & ~TSPEN); | |
554 | SPORT_PUT_RCR1(up, SPORT_GET_RCR1(up) & ~RSPEN); | |
555 | ||
556 | sport_uart_setup(up, up->csize + up->stopb, port->uartclk); | |
557 | ||
558 | /* driver TX line high after config, one dummy data is | |
559 | * necessary to stop sport after shift one byte | |
560 | */ | |
561 | SPORT_PUT_TX(up, 0xffff); | |
562 | SPORT_PUT_TX(up, 0xffff); | |
563 | SPORT_PUT_TCR1(up, (SPORT_GET_TCR1(up) | TSPEN)); | |
564 | SSYNC(); | |
565 | while (!(SPORT_GET_STAT(up) & TXHRE)) | |
566 | cpu_relax(); | |
567 | SPORT_PUT_TCR1(up, SPORT_GET_TCR1(up) & ~TSPEN); | |
568 | SSYNC(); | |
569 | ||
570 | /* Port speed changed, update the per-port timeout. */ | |
571 | uart_update_timeout(port, termios->c_cflag, port->uartclk); | |
572 | ||
573 | /* Enable sport rx */ | |
574 | SPORT_PUT_RCR1(up, SPORT_GET_RCR1(up) | RSPEN); | |
575 | SSYNC(); | |
576 | ||
577 | spin_unlock_irqrestore(&up->port.lock, flags); | |
578 | } | |
579 | ||
2f351741 BW |
580 | struct uart_ops sport_uart_ops = { |
581 | .tx_empty = sport_tx_empty, | |
582 | .set_mctrl = sport_set_mctrl, | |
583 | .get_mctrl = sport_get_mctrl, | |
584 | .stop_tx = sport_stop_tx, | |
585 | .start_tx = sport_start_tx, | |
586 | .stop_rx = sport_stop_rx, | |
587 | .enable_ms = sport_enable_ms, | |
588 | .break_ctl = sport_break_ctl, | |
589 | .startup = sport_startup, | |
590 | .shutdown = sport_shutdown, | |
591 | .set_termios = sport_set_termios, | |
592 | .type = sport_type, | |
593 | .release_port = sport_release_port, | |
594 | .request_port = sport_request_port, | |
595 | .config_port = sport_config_port, | |
596 | .verify_port = sport_verify_port, | |
597 | }; | |
598 | ||
ccf68e59 | 599 | #define BFIN_SPORT_UART_MAX_PORTS 4 |
600 | ||
601 | static struct sport_uart_port *bfin_sport_uart_ports[BFIN_SPORT_UART_MAX_PORTS]; | |
602 | ||
603 | #ifdef CONFIG_SERIAL_BFIN_SPORT_CONSOLE | |
b59588aa SZ |
604 | #define CLASS_BFIN_SPORT_CONSOLE "bfin-sport-console" |
605 | ||
ccf68e59 | 606 | static int __init |
607 | sport_uart_console_setup(struct console *co, char *options) | |
608 | { | |
609 | struct sport_uart_port *up; | |
610 | int baud = 57600; | |
611 | int bits = 8; | |
612 | int parity = 'n'; | |
1f7d1c85 SZ |
613 | # ifdef CONFIG_SERIAL_BFIN_SPORT_CTSRTS |
614 | int flow = 'r'; | |
615 | # else | |
ccf68e59 | 616 | int flow = 'n'; |
1f7d1c85 | 617 | # endif |
ccf68e59 | 618 | |
619 | /* Check whether an invalid uart number has been specified */ | |
620 | if (co->index < 0 || co->index >= BFIN_SPORT_UART_MAX_PORTS) | |
621 | return -ENODEV; | |
622 | ||
623 | up = bfin_sport_uart_ports[co->index]; | |
624 | if (!up) | |
625 | return -ENODEV; | |
626 | ||
627 | if (options) | |
628 | uart_parse_options(options, &baud, &parity, &bits, &flow); | |
629 | ||
630 | return uart_set_options(&up->port, co, baud, parity, bits, flow); | |
631 | } | |
632 | ||
633 | static void sport_uart_console_putchar(struct uart_port *port, int ch) | |
634 | { | |
635 | struct sport_uart_port *up = (struct sport_uart_port *)port; | |
636 | ||
637 | while (SPORT_GET_STAT(up) & TXF) | |
638 | barrier(); | |
639 | ||
640 | tx_one_byte(up, ch); | |
641 | } | |
642 | ||
643 | /* | |
644 | * Interrupts are disabled on entering | |
645 | */ | |
646 | static void | |
647 | sport_uart_console_write(struct console *co, const char *s, unsigned int count) | |
648 | { | |
649 | struct sport_uart_port *up = bfin_sport_uart_ports[co->index]; | |
650 | unsigned long flags; | |
651 | ||
652 | spin_lock_irqsave(&up->port.lock, flags); | |
653 | ||
654 | if (SPORT_GET_TCR1(up) & TSPEN) | |
655 | uart_console_write(&up->port, s, count, sport_uart_console_putchar); | |
656 | else { | |
657 | /* dummy data to start sport */ | |
658 | while (SPORT_GET_STAT(up) & TXF) | |
659 | barrier(); | |
660 | SPORT_PUT_TX(up, 0xffff); | |
661 | /* Enable transmit, then an interrupt will generated */ | |
662 | SPORT_PUT_TCR1(up, (SPORT_GET_TCR1(up) | TSPEN)); | |
663 | SSYNC(); | |
664 | ||
665 | uart_console_write(&up->port, s, count, sport_uart_console_putchar); | |
666 | ||
667 | /* Although the hold register is empty, last byte is still in shift | |
668 | * register and not sent out yet. So, put a dummy data into TX FIFO. | |
669 | * Then, sport tx stops when last byte is shift out and the dummy | |
670 | * data is moved into the shift register. | |
671 | */ | |
672 | while (SPORT_GET_STAT(up) & TXF) | |
673 | barrier(); | |
674 | SPORT_PUT_TX(up, 0xffff); | |
675 | while (!(SPORT_GET_STAT(up) & TXHRE)) | |
676 | barrier(); | |
677 | ||
678 | /* Stop sport tx transfer */ | |
679 | SPORT_PUT_TCR1(up, (SPORT_GET_TCR1(up) & ~TSPEN)); | |
680 | SSYNC(); | |
2f351741 | 681 | } |
ccf68e59 | 682 | |
683 | spin_unlock_irqrestore(&up->port.lock, flags); | |
684 | } | |
685 | ||
686 | static struct uart_driver sport_uart_reg; | |
687 | ||
688 | static struct console sport_uart_console = { | |
689 | .name = DEVICE_NAME, | |
690 | .write = sport_uart_console_write, | |
691 | .device = uart_console_device, | |
692 | .setup = sport_uart_console_setup, | |
693 | .flags = CON_PRINTBUFFER, | |
694 | .index = -1, | |
695 | .data = &sport_uart_reg, | |
2f351741 BW |
696 | }; |
697 | ||
ccf68e59 | 698 | #define SPORT_UART_CONSOLE (&sport_uart_console) |
699 | #else | |
700 | #define SPORT_UART_CONSOLE NULL | |
701 | #endif /* CONFIG_SERIAL_BFIN_SPORT_CONSOLE */ | |
702 | ||
703 | ||
2f351741 BW |
704 | static struct uart_driver sport_uart_reg = { |
705 | .owner = THIS_MODULE, | |
ccf68e59 | 706 | .driver_name = DRV_NAME, |
707 | .dev_name = DEVICE_NAME, | |
2f351741 BW |
708 | .major = 204, |
709 | .minor = 84, | |
ccf68e59 | 710 | .nr = BFIN_SPORT_UART_MAX_PORTS, |
711 | .cons = SPORT_UART_CONSOLE, | |
2f351741 BW |
712 | }; |
713 | ||
ccf68e59 | 714 | #ifdef CONFIG_PM |
715 | static int sport_uart_suspend(struct device *dev) | |
2f351741 | 716 | { |
ccf68e59 | 717 | struct sport_uart_port *sport = dev_get_drvdata(dev); |
2f351741 | 718 | |
ccf68e59 | 719 | dev_dbg(dev, "%s enter\n", __func__); |
2f351741 BW |
720 | if (sport) |
721 | uart_suspend_port(&sport_uart_reg, &sport->port); | |
722 | ||
723 | return 0; | |
724 | } | |
725 | ||
ccf68e59 | 726 | static int sport_uart_resume(struct device *dev) |
2f351741 | 727 | { |
ccf68e59 | 728 | struct sport_uart_port *sport = dev_get_drvdata(dev); |
2f351741 | 729 | |
ccf68e59 | 730 | dev_dbg(dev, "%s enter\n", __func__); |
2f351741 BW |
731 | if (sport) |
732 | uart_resume_port(&sport_uart_reg, &sport->port); | |
733 | ||
734 | return 0; | |
735 | } | |
736 | ||
ccf68e59 | 737 | static struct dev_pm_ops bfin_sport_uart_dev_pm_ops = { |
738 | .suspend = sport_uart_suspend, | |
739 | .resume = sport_uart_resume, | |
740 | }; | |
741 | #endif | |
742 | ||
9671f099 | 743 | static int sport_uart_probe(struct platform_device *pdev) |
2f351741 | 744 | { |
ccf68e59 | 745 | struct resource *res; |
746 | struct sport_uart_port *sport; | |
747 | int ret = 0; | |
2f351741 | 748 | |
ccf68e59 | 749 | dev_dbg(&pdev->dev, "%s enter\n", __func__); |
750 | ||
751 | if (pdev->id < 0 || pdev->id >= BFIN_SPORT_UART_MAX_PORTS) { | |
752 | dev_err(&pdev->dev, "Wrong sport uart platform device id.\n"); | |
753 | return -ENOENT; | |
754 | } | |
755 | ||
756 | if (bfin_sport_uart_ports[pdev->id] == NULL) { | |
757 | bfin_sport_uart_ports[pdev->id] = | |
f4d10ca8 | 758 | kzalloc(sizeof(struct sport_uart_port), GFP_KERNEL); |
ccf68e59 | 759 | sport = bfin_sport_uart_ports[pdev->id]; |
760 | if (!sport) { | |
761 | dev_err(&pdev->dev, | |
f4d10ca8 | 762 | "Fail to malloc sport_uart_port\n"); |
ccf68e59 | 763 | return -ENOMEM; |
764 | } | |
765 | ||
766 | ret = peripheral_request_list( | |
767 | (unsigned short *)pdev->dev.platform_data, DRV_NAME); | |
768 | if (ret) { | |
769 | dev_err(&pdev->dev, | |
770 | "Fail to request SPORT peripherals\n"); | |
771 | goto out_error_free_mem; | |
772 | } | |
773 | ||
774 | spin_lock_init(&sport->port.lock); | |
775 | sport->port.fifosize = SPORT_TX_FIFO_SIZE, | |
776 | sport->port.ops = &sport_uart_ops; | |
777 | sport->port.line = pdev->id; | |
778 | sport->port.iotype = UPIO_MEM; | |
779 | sport->port.flags = UPF_BOOT_AUTOCONF; | |
780 | ||
781 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
782 | if (res == NULL) { | |
783 | dev_err(&pdev->dev, "Cannot get IORESOURCE_MEM\n"); | |
784 | ret = -ENOENT; | |
785 | goto out_error_free_peripherals; | |
786 | } | |
787 | ||
e114474c | 788 | sport->port.membase = ioremap(res->start, resource_size(res)); |
ccf68e59 | 789 | if (!sport->port.membase) { |
790 | dev_err(&pdev->dev, "Cannot map sport IO\n"); | |
791 | ret = -ENXIO; | |
792 | goto out_error_free_peripherals; | |
793 | } | |
e8126b32 | 794 | sport->port.mapbase = res->start; |
ccf68e59 | 795 | |
796 | sport->port.irq = platform_get_irq(pdev, 0); | |
940f3be4 | 797 | if ((int)sport->port.irq < 0) { |
ccf68e59 | 798 | dev_err(&pdev->dev, "No sport RX/TX IRQ specified\n"); |
799 | ret = -ENOENT; | |
800 | goto out_error_unmap; | |
801 | } | |
802 | ||
803 | sport->err_irq = platform_get_irq(pdev, 1); | |
804 | if (sport->err_irq < 0) { | |
805 | dev_err(&pdev->dev, "No sport status IRQ specified\n"); | |
806 | ret = -ENOENT; | |
807 | goto out_error_unmap; | |
808 | } | |
1f7d1c85 SZ |
809 | #ifdef CONFIG_SERIAL_BFIN_SPORT_CTSRTS |
810 | res = platform_get_resource(pdev, IORESOURCE_IO, 0); | |
811 | if (res == NULL) | |
812 | sport->cts_pin = -1; | |
cee3948d | 813 | else { |
1f7d1c85 | 814 | sport->cts_pin = res->start; |
cee3948d SZ |
815 | sport->port.flags |= ASYNC_CTS_FLOW; |
816 | } | |
1f7d1c85 SZ |
817 | |
818 | res = platform_get_resource(pdev, IORESOURCE_IO, 1); | |
819 | if (res == NULL) | |
820 | sport->rts_pin = -1; | |
821 | else | |
822 | sport->rts_pin = res->start; | |
1f7d1c85 | 823 | #endif |
ccf68e59 | 824 | } |
825 | ||
826 | #ifdef CONFIG_SERIAL_BFIN_SPORT_CONSOLE | |
827 | if (!is_early_platform_device(pdev)) { | |
828 | #endif | |
829 | sport = bfin_sport_uart_ports[pdev->id]; | |
830 | sport->port.dev = &pdev->dev; | |
831 | dev_set_drvdata(&pdev->dev, sport); | |
832 | ret = uart_add_one_port(&sport_uart_reg, &sport->port); | |
833 | #ifdef CONFIG_SERIAL_BFIN_SPORT_CONSOLE | |
834 | } | |
835 | #endif | |
836 | if (!ret) | |
837 | return 0; | |
838 | ||
839 | if (sport) { | |
840 | out_error_unmap: | |
841 | iounmap(sport->port.membase); | |
842 | out_error_free_peripherals: | |
843 | peripheral_free_list( | |
844 | (unsigned short *)pdev->dev.platform_data); | |
845 | out_error_free_mem: | |
846 | kfree(sport); | |
847 | bfin_sport_uart_ports[pdev->id] = NULL; | |
848 | } | |
849 | ||
850 | return ret; | |
2f351741 BW |
851 | } |
852 | ||
ccf68e59 | 853 | static int __devexit sport_uart_remove(struct platform_device *pdev) |
2f351741 | 854 | { |
ccf68e59 | 855 | struct sport_uart_port *sport = platform_get_drvdata(pdev); |
2f351741 | 856 | |
ccf68e59 | 857 | dev_dbg(&pdev->dev, "%s enter\n", __func__); |
858 | dev_set_drvdata(&pdev->dev, NULL); | |
2f351741 | 859 | |
ccf68e59 | 860 | if (sport) { |
2f351741 | 861 | uart_remove_one_port(&sport_uart_reg, &sport->port); |
ccf68e59 | 862 | iounmap(sport->port.membase); |
863 | peripheral_free_list( | |
864 | (unsigned short *)pdev->dev.platform_data); | |
865 | kfree(sport); | |
866 | bfin_sport_uart_ports[pdev->id] = NULL; | |
867 | } | |
2f351741 BW |
868 | |
869 | return 0; | |
870 | } | |
871 | ||
872 | static struct platform_driver sport_uart_driver = { | |
873 | .probe = sport_uart_probe, | |
2d47b716 | 874 | .remove = sport_uart_remove, |
2f351741 BW |
875 | .driver = { |
876 | .name = DRV_NAME, | |
ccf68e59 | 877 | #ifdef CONFIG_PM |
878 | .pm = &bfin_sport_uart_dev_pm_ops, | |
879 | #endif | |
2f351741 BW |
880 | }, |
881 | }; | |
882 | ||
ccf68e59 | 883 | #ifdef CONFIG_SERIAL_BFIN_SPORT_CONSOLE |
884 | static __initdata struct early_platform_driver early_sport_uart_driver = { | |
b59588aa | 885 | .class_str = CLASS_BFIN_SPORT_CONSOLE, |
ccf68e59 | 886 | .pdrv = &sport_uart_driver, |
887 | .requested_id = EARLY_PLATFORM_ID_UNSET, | |
888 | }; | |
889 | ||
890 | static int __init sport_uart_rs_console_init(void) | |
891 | { | |
892 | early_platform_driver_register(&early_sport_uart_driver, DRV_NAME); | |
893 | ||
b59588aa SZ |
894 | early_platform_driver_probe(CLASS_BFIN_SPORT_CONSOLE, |
895 | BFIN_SPORT_UART_MAX_PORTS, 0); | |
ccf68e59 | 896 | |
897 | register_console(&sport_uart_console); | |
898 | ||
899 | return 0; | |
900 | } | |
901 | console_initcall(sport_uart_rs_console_init); | |
902 | #endif | |
903 | ||
2f351741 BW |
904 | static int __init sport_uart_init(void) |
905 | { | |
906 | int ret; | |
907 | ||
e8126b32 | 908 | pr_info("Blackfin uart over sport driver\n"); |
ccf68e59 | 909 | |
2f351741 | 910 | ret = uart_register_driver(&sport_uart_reg); |
ccf68e59 | 911 | if (ret) { |
912 | pr_err("failed to register %s:%d\n", | |
2f351741 BW |
913 | sport_uart_reg.driver_name, ret); |
914 | return ret; | |
915 | } | |
916 | ||
917 | ret = platform_driver_register(&sport_uart_driver); | |
ccf68e59 | 918 | if (ret) { |
919 | pr_err("failed to register sport uart driver:%d\n", ret); | |
2f351741 BW |
920 | uart_unregister_driver(&sport_uart_reg); |
921 | } | |
922 | ||
2f351741 BW |
923 | return ret; |
924 | } | |
ccf68e59 | 925 | module_init(sport_uart_init); |
2f351741 BW |
926 | |
927 | static void __exit sport_uart_exit(void) | |
928 | { | |
2f351741 BW |
929 | platform_driver_unregister(&sport_uart_driver); |
930 | uart_unregister_driver(&sport_uart_reg); | |
931 | } | |
2f351741 BW |
932 | module_exit(sport_uart_exit); |
933 | ||
ccf68e59 | 934 | MODULE_AUTHOR("Sonic Zhang, Roy Huang"); |
935 | MODULE_DESCRIPTION("Blackfin serial over SPORT driver"); | |
2f351741 | 936 | MODULE_LICENSE("GPL"); |