Commit | Line | Data |
---|---|---|
194de561 | 1 | /* |
1ba7a3ee | 2 | * Blackfin On-Chip Serial Driver |
194de561 | 3 | * |
57afb399 | 4 | * Copyright 2006-2010 Analog Devices Inc. |
194de561 | 5 | * |
1ba7a3ee | 6 | * Enter bugs at http://blackfin.uclinux.org/ |
194de561 | 7 | * |
1ba7a3ee | 8 | * Licensed under the GPL-2 or later. |
194de561 BW |
9 | */ |
10 | ||
11 | #if defined(CONFIG_SERIAL_BFIN_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) | |
12 | #define SUPPORT_SYSRQ | |
13 | #endif | |
14 | ||
57afb399 SZ |
15 | #define DRIVER_NAME "bfin-uart" |
16 | #define pr_fmt(fmt) DRIVER_NAME ": " fmt | |
17 | ||
194de561 BW |
18 | #include <linux/module.h> |
19 | #include <linux/ioport.h> | |
5a0e3ad6 | 20 | #include <linux/gfp.h> |
599b714c | 21 | #include <linux/io.h> |
194de561 BW |
22 | #include <linux/init.h> |
23 | #include <linux/console.h> | |
24 | #include <linux/sysrq.h> | |
25 | #include <linux/platform_device.h> | |
26 | #include <linux/tty.h> | |
27 | #include <linux/tty_flip.h> | |
28 | #include <linux/serial_core.h> | |
57afb399 SZ |
29 | #include <linux/gpio.h> |
30 | #include <linux/irq.h> | |
474f1a66 | 31 | #include <linux/kgdb.h> |
57afb399 SZ |
32 | #include <linux/slab.h> |
33 | #include <linux/dma-mapping.h> | |
194de561 | 34 | |
57afb399 | 35 | #include <asm/portmux.h> |
194de561 | 36 | #include <asm/cacheflush.h> |
57afb399 SZ |
37 | #include <asm/dma.h> |
38 | ||
39 | #define port_membase(uart) (((struct bfin_serial_port *)(uart))->port.membase) | |
40 | #define get_lsr_cache(uart) (((struct bfin_serial_port *)(uart))->lsr) | |
41 | #define put_lsr_cache(uart, v) (((struct bfin_serial_port *)(uart))->lsr = (v)) | |
42 | #include <asm/bfin_serial.h> | |
194de561 | 43 | |
607c268e MF |
44 | #ifdef CONFIG_SERIAL_BFIN_MODULE |
45 | # undef CONFIG_EARLY_PRINTK | |
46 | #endif | |
47 | ||
0271edd4 MF |
48 | #ifdef CONFIG_SERIAL_BFIN_MODULE |
49 | # undef CONFIG_EARLY_PRINTK | |
50 | #endif | |
51 | ||
194de561 | 52 | /* UART name and device definitions */ |
57afb399 | 53 | #define BFIN_SERIAL_DEV_NAME "ttyBF" |
194de561 BW |
54 | #define BFIN_SERIAL_MAJOR 204 |
55 | #define BFIN_SERIAL_MINOR 64 | |
56 | ||
57afb399 | 57 | static struct bfin_serial_port *bfin_serial_ports[BFIN_UART_NR_PORTS]; |
c9607ecc | 58 | |
52e15f0e SZ |
59 | #if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \ |
60 | defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE) | |
61 | ||
62 | # ifndef CONFIG_SERIAL_BFIN_PIO | |
63 | # error KGDB only support UART in PIO mode. | |
64 | # endif | |
65 | ||
66 | static int kgdboc_port_line; | |
67 | static int kgdboc_break_enabled; | |
68 | #endif | |
194de561 BW |
69 | /* |
70 | * Setup for console. Argument comes from the menuconfig | |
71 | */ | |
72 | #define DMA_RX_XCOUNT 512 | |
73 | #define DMA_RX_YCOUNT (PAGE_SIZE / DMA_RX_XCOUNT) | |
74 | ||
0aef4564 | 75 | #define DMA_RX_FLUSH_JIFFIES (HZ / 50) |
194de561 BW |
76 | |
77 | #ifdef CONFIG_SERIAL_BFIN_DMA | |
78 | static void bfin_serial_dma_tx_chars(struct bfin_serial_port *uart); | |
79 | #else | |
194de561 | 80 | static void bfin_serial_tx_chars(struct bfin_serial_port *uart); |
194de561 BW |
81 | #endif |
82 | ||
80d5c474 GY |
83 | static void bfin_serial_reset_irda(struct uart_port *port); |
84 | ||
d307d36a SZ |
85 | #if defined(CONFIG_SERIAL_BFIN_CTSRTS) || \ |
86 | defined(CONFIG_SERIAL_BFIN_HARD_CTSRTS) | |
87 | static unsigned int bfin_serial_get_mctrl(struct uart_port *port) | |
88 | { | |
89 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
90 | if (uart->cts_pin < 0) | |
91 | return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR; | |
92 | ||
93 | /* CTS PIN is negative assertive. */ | |
94 | if (UART_GET_CTS(uart)) | |
95 | return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR; | |
96 | else | |
97 | return TIOCM_DSR | TIOCM_CAR; | |
98 | } | |
99 | ||
100 | static void bfin_serial_set_mctrl(struct uart_port *port, unsigned int mctrl) | |
101 | { | |
102 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
103 | if (uart->rts_pin < 0) | |
104 | return; | |
105 | ||
106 | /* RTS PIN is negative assertive. */ | |
107 | if (mctrl & TIOCM_RTS) | |
108 | UART_ENABLE_RTS(uart); | |
109 | else | |
110 | UART_DISABLE_RTS(uart); | |
111 | } | |
112 | ||
113 | /* | |
114 | * Handle any change of modem status signal. | |
115 | */ | |
116 | static irqreturn_t bfin_serial_mctrl_cts_int(int irq, void *dev_id) | |
117 | { | |
118 | struct bfin_serial_port *uart = dev_id; | |
119 | unsigned int status; | |
120 | ||
121 | status = bfin_serial_get_mctrl(&uart->port); | |
122 | uart_handle_cts_change(&uart->port, status & TIOCM_CTS); | |
123 | #ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS | |
124 | uart->scts = 1; | |
125 | UART_CLEAR_SCTS(uart); | |
126 | UART_CLEAR_IER(uart, EDSSI); | |
127 | #endif | |
128 | ||
129 | return IRQ_HANDLED; | |
130 | } | |
131 | #else | |
132 | static unsigned int bfin_serial_get_mctrl(struct uart_port *port) | |
133 | { | |
134 | return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR; | |
135 | } | |
136 | ||
137 | static void bfin_serial_set_mctrl(struct uart_port *port, unsigned int mctrl) | |
138 | { | |
139 | } | |
140 | #endif | |
141 | ||
194de561 BW |
142 | /* |
143 | * interrupts are disabled on entry | |
144 | */ | |
145 | static void bfin_serial_stop_tx(struct uart_port *port) | |
146 | { | |
147 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
68a784cb | 148 | #ifdef CONFIG_SERIAL_BFIN_DMA |
ebd2c8f6 | 149 | struct circ_buf *xmit = &uart->port.state->xmit; |
68a784cb | 150 | #endif |
194de561 | 151 | |
f4d640c9 | 152 | while (!(UART_GET_LSR(uart) & TEMT)) |
0711d857 | 153 | cpu_relax(); |
f4d640c9 | 154 | |
194de561 BW |
155 | #ifdef CONFIG_SERIAL_BFIN_DMA |
156 | disable_dma(uart->tx_dma_channel); | |
0711d857 SZ |
157 | xmit->tail = (xmit->tail + uart->tx_count) & (UART_XMIT_SIZE - 1); |
158 | uart->port.icount.tx += uart->tx_count; | |
159 | uart->tx_count = 0; | |
160 | uart->tx_done = 1; | |
f4d640c9 RH |
161 | #else |
162 | #ifdef CONFIG_BF54x | |
f4d640c9 RH |
163 | /* Clear TFI bit */ |
164 | UART_PUT_LSR(uart, TFI); | |
194de561 | 165 | #endif |
89bf6dc5 | 166 | UART_CLEAR_IER(uart, ETBEI); |
f4d640c9 | 167 | #endif |
194de561 BW |
168 | } |
169 | ||
170 | /* | |
171 | * port is locked and interrupts are disabled | |
172 | */ | |
173 | static void bfin_serial_start_tx(struct uart_port *port) | |
174 | { | |
175 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
ebd2c8f6 | 176 | struct tty_struct *tty = uart->port.state->port.tty; |
80d5c474 | 177 | |
d307d36a | 178 | #ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS |
daba0280 | 179 | if (uart->scts && !(bfin_serial_get_mctrl(&uart->port) & TIOCM_CTS)) { |
d307d36a SZ |
180 | uart->scts = 0; |
181 | uart_handle_cts_change(&uart->port, uart->scts); | |
182 | } | |
183 | #endif | |
184 | ||
80d5c474 GY |
185 | /* |
186 | * To avoid losting RX interrupt, we reset IR function | |
187 | * before sending data. | |
188 | */ | |
189 | if (tty->termios->c_line == N_IRDA) | |
190 | bfin_serial_reset_irda(port); | |
194de561 BW |
191 | |
192 | #ifdef CONFIG_SERIAL_BFIN_DMA | |
0711d857 SZ |
193 | if (uart->tx_done) |
194 | bfin_serial_dma_tx_chars(uart); | |
f4d640c9 | 195 | #else |
f4d640c9 | 196 | UART_SET_IER(uart, ETBEI); |
a359cca7 | 197 | bfin_serial_tx_chars(uart); |
f4d640c9 | 198 | #endif |
194de561 BW |
199 | } |
200 | ||
201 | /* | |
202 | * Interrupts are enabled | |
203 | */ | |
204 | static void bfin_serial_stop_rx(struct uart_port *port) | |
205 | { | |
206 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
52e15f0e | 207 | |
f4d640c9 | 208 | UART_CLEAR_IER(uart, ERBFI); |
194de561 BW |
209 | } |
210 | ||
211 | /* | |
212 | * Set the modem control timer to fire immediately. | |
213 | */ | |
214 | static void bfin_serial_enable_ms(struct uart_port *port) | |
215 | { | |
216 | } | |
217 | ||
474f1a66 | 218 | |
50e2e15a | 219 | #if ANOMALY_05000363 && defined(CONFIG_SERIAL_BFIN_PIO) |
8851c71e MF |
220 | # define UART_GET_ANOMALY_THRESHOLD(uart) ((uart)->anomaly_threshold) |
221 | # define UART_SET_ANOMALY_THRESHOLD(uart, v) ((uart)->anomaly_threshold = (v)) | |
222 | #else | |
223 | # define UART_GET_ANOMALY_THRESHOLD(uart) 0 | |
224 | # define UART_SET_ANOMALY_THRESHOLD(uart, v) | |
225 | #endif | |
226 | ||
194de561 | 227 | #ifdef CONFIG_SERIAL_BFIN_PIO |
194de561 BW |
228 | static void bfin_serial_rx_chars(struct bfin_serial_port *uart) |
229 | { | |
52e15f0e | 230 | struct tty_struct *tty = NULL; |
194de561 | 231 | unsigned int status, ch, flg; |
8851c71e | 232 | static struct timeval anomaly_start = { .tv_sec = 0 }; |
194de561 | 233 | |
759eb040 | 234 | status = UART_GET_LSR(uart); |
0bcfd70e MF |
235 | UART_CLEAR_LSR(uart); |
236 | ||
237 | ch = UART_GET_CHAR(uart); | |
194de561 BW |
238 | uart->port.icount.rx++; |
239 | ||
52e15f0e SZ |
240 | #if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \ |
241 | defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE) | |
cdc592d5 SZ |
242 | if (kgdb_connected && kgdboc_port_line == uart->port.line |
243 | && kgdboc_break_enabled) | |
52e15f0e SZ |
244 | if (ch == 0x3) {/* Ctrl + C */ |
245 | kgdb_breakpoint(); | |
474f1a66 | 246 | return; |
474f1a66 | 247 | } |
52e15f0e | 248 | |
ebd2c8f6 | 249 | if (!uart->port.state || !uart->port.state->port.tty) |
52e15f0e | 250 | return; |
474f1a66 | 251 | #endif |
ebd2c8f6 | 252 | tty = uart->port.state->port.tty; |
bbf275f0 | 253 | |
50e2e15a | 254 | if (ANOMALY_05000363) { |
8851c71e MF |
255 | /* The BF533 (and BF561) family of processors have a nice anomaly |
256 | * where they continuously generate characters for a "single" break. | |
bbf275f0 | 257 | * We have to basically ignore this flood until the "next" valid |
8851c71e MF |
258 | * character comes across. Due to the nature of the flood, it is |
259 | * not possible to reliably catch bytes that are sent too quickly | |
260 | * after this break. So application code talking to the Blackfin | |
261 | * which sends a break signal must allow at least 1.5 character | |
262 | * times after the end of the break for things to stabilize. This | |
263 | * timeout was picked as it must absolutely be larger than 1 | |
264 | * character time +/- some percent. So 1.5 sounds good. All other | |
265 | * Blackfin families operate properly. Woo. | |
bbf275f0 | 266 | */ |
8851c71e MF |
267 | if (anomaly_start.tv_sec) { |
268 | struct timeval curr; | |
269 | suseconds_t usecs; | |
270 | ||
271 | if ((~ch & (~ch + 1)) & 0xff) | |
272 | goto known_good_char; | |
273 | ||
274 | do_gettimeofday(&curr); | |
275 | if (curr.tv_sec - anomaly_start.tv_sec > 1) | |
276 | goto known_good_char; | |
277 | ||
278 | usecs = 0; | |
279 | if (curr.tv_sec != anomaly_start.tv_sec) | |
280 | usecs += USEC_PER_SEC; | |
281 | usecs += curr.tv_usec - anomaly_start.tv_usec; | |
282 | ||
283 | if (usecs > UART_GET_ANOMALY_THRESHOLD(uart)) | |
284 | goto known_good_char; | |
285 | ||
286 | if (ch) | |
287 | anomaly_start.tv_sec = 0; | |
288 | else | |
289 | anomaly_start = curr; | |
290 | ||
291 | return; | |
292 | ||
293 | known_good_char: | |
e482a237 | 294 | status &= ~BI; |
8851c71e | 295 | anomaly_start.tv_sec = 0; |
bbf275f0 | 296 | } |
194de561 | 297 | } |
194de561 BW |
298 | |
299 | if (status & BI) { | |
50e2e15a | 300 | if (ANOMALY_05000363) |
8851c71e MF |
301 | if (bfin_revid() < 5) |
302 | do_gettimeofday(&anomaly_start); | |
194de561 BW |
303 | uart->port.icount.brk++; |
304 | if (uart_handle_break(&uart->port)) | |
305 | goto ignore_char; | |
9808901b | 306 | status &= ~(PE | FE); |
2ac5ee47 MF |
307 | } |
308 | if (status & PE) | |
194de561 | 309 | uart->port.icount.parity++; |
2ac5ee47 | 310 | if (status & OE) |
194de561 | 311 | uart->port.icount.overrun++; |
2ac5ee47 | 312 | if (status & FE) |
194de561 | 313 | uart->port.icount.frame++; |
2ac5ee47 MF |
314 | |
315 | status &= uart->port.read_status_mask; | |
316 | ||
317 | if (status & BI) | |
318 | flg = TTY_BREAK; | |
319 | else if (status & PE) | |
320 | flg = TTY_PARITY; | |
321 | else if (status & FE) | |
322 | flg = TTY_FRAME; | |
323 | else | |
194de561 BW |
324 | flg = TTY_NORMAL; |
325 | ||
326 | if (uart_handle_sysrq_char(&uart->port, ch)) | |
327 | goto ignore_char; | |
194de561 | 328 | |
2ac5ee47 MF |
329 | uart_insert_char(&uart->port, status, OE, ch, flg); |
330 | ||
331 | ignore_char: | |
332 | tty_flip_buffer_push(tty); | |
194de561 BW |
333 | } |
334 | ||
335 | static void bfin_serial_tx_chars(struct bfin_serial_port *uart) | |
336 | { | |
ebd2c8f6 | 337 | struct circ_buf *xmit = &uart->port.state->xmit; |
194de561 | 338 | |
194de561 | 339 | if (uart_circ_empty(xmit) || uart_tx_stopped(&uart->port)) { |
5ffdeea2 SZ |
340 | #ifdef CONFIG_BF54x |
341 | /* Clear TFI bit */ | |
342 | UART_PUT_LSR(uart, TFI); | |
343 | #endif | |
0efa4f2c SZ |
344 | /* Anomaly notes: |
345 | * 05000215 - we always clear ETBEI within last UART TX | |
346 | * interrupt to end a string. It is always set | |
347 | * when start a new tx. | |
348 | */ | |
5ffdeea2 | 349 | UART_CLEAR_IER(uart, ETBEI); |
194de561 BW |
350 | return; |
351 | } | |
352 | ||
f30ac0ce SZ |
353 | if (uart->port.x_char) { |
354 | UART_PUT_CHAR(uart, uart->port.x_char); | |
355 | uart->port.icount.tx++; | |
356 | uart->port.x_char = 0; | |
357 | } | |
358 | ||
759eb040 SZ |
359 | while ((UART_GET_LSR(uart) & THRE) && xmit->tail != xmit->head) { |
360 | UART_PUT_CHAR(uart, xmit->buf[xmit->tail]); | |
361 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); | |
362 | uart->port.icount.tx++; | |
759eb040 | 363 | } |
194de561 BW |
364 | |
365 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
366 | uart_write_wakeup(&uart->port); | |
194de561 BW |
367 | } |
368 | ||
5c4e472b AL |
369 | static irqreturn_t bfin_serial_rx_int(int irq, void *dev_id) |
370 | { | |
371 | struct bfin_serial_port *uart = dev_id; | |
372 | ||
0bcfd70e | 373 | while (UART_GET_LSR(uart) & DR) |
f4d640c9 | 374 | bfin_serial_rx_chars(uart); |
759eb040 | 375 | |
5c4e472b AL |
376 | return IRQ_HANDLED; |
377 | } | |
378 | ||
379 | static irqreturn_t bfin_serial_tx_int(int irq, void *dev_id) | |
194de561 BW |
380 | { |
381 | struct bfin_serial_port *uart = dev_id; | |
194de561 | 382 | |
d307d36a | 383 | #ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS |
daba0280 | 384 | if (uart->scts && !(bfin_serial_get_mctrl(&uart->port) & TIOCM_CTS)) { |
d307d36a SZ |
385 | uart->scts = 0; |
386 | uart_handle_cts_change(&uart->port, uart->scts); | |
387 | } | |
388 | #endif | |
f4d640c9 | 389 | spin_lock(&uart->port.lock); |
0bcfd70e | 390 | if (UART_GET_LSR(uart) & THRE) |
f4d640c9 | 391 | bfin_serial_tx_chars(uart); |
f4d640c9 | 392 | spin_unlock(&uart->port.lock); |
759eb040 | 393 | |
194de561 BW |
394 | return IRQ_HANDLED; |
395 | } | |
4cb4f22b | 396 | #endif |
194de561 | 397 | |
194de561 BW |
398 | #ifdef CONFIG_SERIAL_BFIN_DMA |
399 | static void bfin_serial_dma_tx_chars(struct bfin_serial_port *uart) | |
400 | { | |
ebd2c8f6 | 401 | struct circ_buf *xmit = &uart->port.state->xmit; |
194de561 | 402 | |
194de561 BW |
403 | uart->tx_done = 0; |
404 | ||
1b73351c | 405 | if (uart_circ_empty(xmit) || uart_tx_stopped(&uart->port)) { |
0711d857 | 406 | uart->tx_count = 0; |
1b73351c SZ |
407 | uart->tx_done = 1; |
408 | return; | |
409 | } | |
410 | ||
194de561 BW |
411 | if (uart->port.x_char) { |
412 | UART_PUT_CHAR(uart, uart->port.x_char); | |
413 | uart->port.icount.tx++; | |
414 | uart->port.x_char = 0; | |
194de561 | 415 | } |
1b73351c | 416 | |
194de561 BW |
417 | uart->tx_count = CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE); |
418 | if (uart->tx_count > (UART_XMIT_SIZE - xmit->tail)) | |
419 | uart->tx_count = UART_XMIT_SIZE - xmit->tail; | |
420 | blackfin_dcache_flush_range((unsigned long)(xmit->buf+xmit->tail), | |
421 | (unsigned long)(xmit->buf+xmit->tail+uart->tx_count)); | |
422 | set_dma_config(uart->tx_dma_channel, | |
423 | set_bfin_dma_config(DIR_READ, DMA_FLOW_STOP, | |
424 | INTR_ON_BUF, | |
425 | DIMENSION_LINEAR, | |
2047e40d MH |
426 | DATA_SIZE_8, |
427 | DMA_SYNC_RESTART)); | |
194de561 BW |
428 | set_dma_start_addr(uart->tx_dma_channel, (unsigned long)(xmit->buf+xmit->tail)); |
429 | set_dma_x_count(uart->tx_dma_channel, uart->tx_count); | |
430 | set_dma_x_modify(uart->tx_dma_channel, 1); | |
f9d36da9 | 431 | SSYNC(); |
194de561 | 432 | enable_dma(uart->tx_dma_channel); |
99ee7b5f | 433 | |
f4d640c9 | 434 | UART_SET_IER(uart, ETBEI); |
194de561 BW |
435 | } |
436 | ||
2ac5ee47 | 437 | static void bfin_serial_dma_rx_chars(struct bfin_serial_port *uart) |
194de561 | 438 | { |
ebd2c8f6 | 439 | struct tty_struct *tty = uart->port.state->port.tty; |
194de561 BW |
440 | int i, flg, status; |
441 | ||
442 | status = UART_GET_LSR(uart); | |
0bcfd70e MF |
443 | UART_CLEAR_LSR(uart); |
444 | ||
56f5de8f SZ |
445 | uart->port.icount.rx += |
446 | CIRC_CNT(uart->rx_dma_buf.head, uart->rx_dma_buf.tail, | |
447 | UART_XMIT_SIZE); | |
194de561 BW |
448 | |
449 | if (status & BI) { | |
450 | uart->port.icount.brk++; | |
451 | if (uart_handle_break(&uart->port)) | |
452 | goto dma_ignore_char; | |
9808901b | 453 | status &= ~(PE | FE); |
2ac5ee47 MF |
454 | } |
455 | if (status & PE) | |
194de561 | 456 | uart->port.icount.parity++; |
2ac5ee47 | 457 | if (status & OE) |
194de561 | 458 | uart->port.icount.overrun++; |
2ac5ee47 | 459 | if (status & FE) |
194de561 | 460 | uart->port.icount.frame++; |
2ac5ee47 MF |
461 | |
462 | status &= uart->port.read_status_mask; | |
463 | ||
464 | if (status & BI) | |
465 | flg = TTY_BREAK; | |
466 | else if (status & PE) | |
467 | flg = TTY_PARITY; | |
468 | else if (status & FE) | |
469 | flg = TTY_FRAME; | |
470 | else | |
194de561 BW |
471 | flg = TTY_NORMAL; |
472 | ||
8c4210e3 | 473 | for (i = uart->rx_dma_buf.tail; ; i++) { |
56f5de8f SZ |
474 | if (i >= UART_XMIT_SIZE) |
475 | i = 0; | |
8c4210e3 SZ |
476 | if (i == uart->rx_dma_buf.head) |
477 | break; | |
56f5de8f SZ |
478 | if (!uart_handle_sysrq_char(&uart->port, uart->rx_dma_buf.buf[i])) |
479 | uart_insert_char(&uart->port, status, OE, | |
480 | uart->rx_dma_buf.buf[i], flg); | |
194de561 | 481 | } |
2ac5ee47 MF |
482 | |
483 | dma_ignore_char: | |
194de561 BW |
484 | tty_flip_buffer_push(tty); |
485 | } | |
486 | ||
487 | void bfin_serial_rx_dma_timeout(struct bfin_serial_port *uart) | |
488 | { | |
59e4e3e6 | 489 | int x_pos, pos; |
68a784cb | 490 | |
0f66e50a SZ |
491 | dma_disable_irq_nosync(uart->rx_dma_channel); |
492 | spin_lock_bh(&uart->rx_lock); | |
194de561 | 493 | |
8516c568 SZ |
494 | /* 2D DMA RX buffer ring is used. Because curr_y_count and |
495 | * curr_x_count can't be read as an atomic operation, | |
496 | * curr_y_count should be read before curr_x_count. When | |
497 | * curr_x_count is read, curr_y_count may already indicate | |
498 | * next buffer line. But, the position calculated here is | |
499 | * still indicate the old line. The wrong position data may | |
500 | * be smaller than current buffer tail, which cause garbages | |
501 | * are received if it is not prohibit. | |
502 | */ | |
56f5de8f SZ |
503 | uart->rx_dma_nrows = get_dma_curr_ycount(uart->rx_dma_channel); |
504 | x_pos = get_dma_curr_xcount(uart->rx_dma_channel); | |
505 | uart->rx_dma_nrows = DMA_RX_YCOUNT - uart->rx_dma_nrows; | |
35ff6935 | 506 | if (uart->rx_dma_nrows == DMA_RX_YCOUNT || x_pos == 0) |
56f5de8f SZ |
507 | uart->rx_dma_nrows = 0; |
508 | x_pos = DMA_RX_XCOUNT - x_pos; | |
194de561 BW |
509 | if (x_pos == DMA_RX_XCOUNT) |
510 | x_pos = 0; | |
511 | ||
512 | pos = uart->rx_dma_nrows * DMA_RX_XCOUNT + x_pos; | |
8516c568 SZ |
513 | /* Ignore receiving data if new position is in the same line of |
514 | * current buffer tail and small. | |
515 | */ | |
516 | if (pos > uart->rx_dma_buf.tail || | |
517 | uart->rx_dma_nrows < (uart->rx_dma_buf.tail/DMA_RX_XCOUNT)) { | |
56f5de8f | 518 | uart->rx_dma_buf.head = pos; |
194de561 | 519 | bfin_serial_dma_rx_chars(uart); |
56f5de8f | 520 | uart->rx_dma_buf.tail = uart->rx_dma_buf.head; |
194de561 | 521 | } |
0aef4564 | 522 | |
0f66e50a | 523 | spin_unlock_bh(&uart->rx_lock); |
2860b791 | 524 | dma_enable_irq(uart->rx_dma_channel); |
68a784cb | 525 | |
0a278423 | 526 | mod_timer(&(uart->rx_dma_timer), jiffies + DMA_RX_FLUSH_JIFFIES); |
194de561 BW |
527 | } |
528 | ||
529 | static irqreturn_t bfin_serial_dma_tx_int(int irq, void *dev_id) | |
530 | { | |
531 | struct bfin_serial_port *uart = dev_id; | |
ebd2c8f6 | 532 | struct circ_buf *xmit = &uart->port.state->xmit; |
194de561 | 533 | |
d307d36a | 534 | #ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS |
daba0280 | 535 | if (uart->scts && !(bfin_serial_get_mctrl(&uart->port)&TIOCM_CTS)) { |
d307d36a SZ |
536 | uart->scts = 0; |
537 | uart_handle_cts_change(&uart->port, uart->scts); | |
538 | } | |
539 | #endif | |
540 | ||
194de561 BW |
541 | spin_lock(&uart->port.lock); |
542 | if (!(get_dma_curr_irqstat(uart->tx_dma_channel)&DMA_RUN)) { | |
194de561 | 543 | disable_dma(uart->tx_dma_channel); |
0711d857 | 544 | clear_dma_irqstat(uart->tx_dma_channel); |
0efa4f2c SZ |
545 | /* Anomaly notes: |
546 | * 05000215 - we always clear ETBEI within last UART TX | |
547 | * interrupt to end a string. It is always set | |
548 | * when start a new tx. | |
549 | */ | |
f4d640c9 | 550 | UART_CLEAR_IER(uart, ETBEI); |
0711d857 SZ |
551 | xmit->tail = (xmit->tail + uart->tx_count) & (UART_XMIT_SIZE - 1); |
552 | uart->port.icount.tx += uart->tx_count; | |
1b73351c | 553 | |
56f5de8f SZ |
554 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) |
555 | uart_write_wakeup(&uart->port); | |
556 | ||
1b73351c | 557 | bfin_serial_dma_tx_chars(uart); |
194de561 BW |
558 | } |
559 | ||
560 | spin_unlock(&uart->port.lock); | |
561 | return IRQ_HANDLED; | |
562 | } | |
563 | ||
564 | static irqreturn_t bfin_serial_dma_rx_int(int irq, void *dev_id) | |
565 | { | |
566 | struct bfin_serial_port *uart = dev_id; | |
567 | unsigned short irqstat; | |
35ff6935 | 568 | int x_pos, pos; |
0711d857 | 569 | |
0f66e50a | 570 | spin_lock(&uart->rx_lock); |
194de561 BW |
571 | irqstat = get_dma_curr_irqstat(uart->rx_dma_channel); |
572 | clear_dma_irqstat(uart->rx_dma_channel); | |
8516c568 SZ |
573 | |
574 | uart->rx_dma_nrows = get_dma_curr_ycount(uart->rx_dma_channel); | |
35ff6935 | 575 | x_pos = get_dma_curr_xcount(uart->rx_dma_channel); |
8516c568 | 576 | uart->rx_dma_nrows = DMA_RX_YCOUNT - uart->rx_dma_nrows; |
35ff6935 | 577 | if (uart->rx_dma_nrows == DMA_RX_YCOUNT || x_pos == 0) |
8516c568 SZ |
578 | uart->rx_dma_nrows = 0; |
579 | ||
580 | pos = uart->rx_dma_nrows * DMA_RX_XCOUNT; | |
581 | if (pos > uart->rx_dma_buf.tail || | |
582 | uart->rx_dma_nrows < (uart->rx_dma_buf.tail/DMA_RX_XCOUNT)) { | |
583 | uart->rx_dma_buf.head = pos; | |
584 | bfin_serial_dma_rx_chars(uart); | |
585 | uart->rx_dma_buf.tail = uart->rx_dma_buf.head; | |
586 | } | |
587 | ||
0f66e50a | 588 | spin_unlock(&uart->rx_lock); |
0aef4564 | 589 | |
194de561 BW |
590 | return IRQ_HANDLED; |
591 | } | |
592 | #endif | |
593 | ||
594 | /* | |
595 | * Return TIOCSER_TEMT when transmitter is not busy. | |
596 | */ | |
597 | static unsigned int bfin_serial_tx_empty(struct uart_port *port) | |
598 | { | |
599 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
600 | unsigned short lsr; | |
601 | ||
602 | lsr = UART_GET_LSR(uart); | |
603 | if (lsr & TEMT) | |
604 | return TIOCSER_TEMT; | |
605 | else | |
606 | return 0; | |
607 | } | |
608 | ||
194de561 BW |
609 | static void bfin_serial_break_ctl(struct uart_port *port, int break_state) |
610 | { | |
cf686762 MF |
611 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; |
612 | u16 lcr = UART_GET_LCR(uart); | |
613 | if (break_state) | |
614 | lcr |= SB; | |
615 | else | |
616 | lcr &= ~SB; | |
617 | UART_PUT_LCR(uart, lcr); | |
618 | SSYNC(); | |
194de561 BW |
619 | } |
620 | ||
621 | static int bfin_serial_startup(struct uart_port *port) | |
622 | { | |
623 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
624 | ||
625 | #ifdef CONFIG_SERIAL_BFIN_DMA | |
626 | dma_addr_t dma_handle; | |
627 | ||
628 | if (request_dma(uart->rx_dma_channel, "BFIN_UART_RX") < 0) { | |
629 | printk(KERN_NOTICE "Unable to attach Blackfin UART RX DMA channel\n"); | |
630 | return -EBUSY; | |
631 | } | |
632 | ||
633 | if (request_dma(uart->tx_dma_channel, "BFIN_UART_TX") < 0) { | |
634 | printk(KERN_NOTICE "Unable to attach Blackfin UART TX DMA channel\n"); | |
635 | free_dma(uart->rx_dma_channel); | |
636 | return -EBUSY; | |
637 | } | |
638 | ||
639 | set_dma_callback(uart->rx_dma_channel, bfin_serial_dma_rx_int, uart); | |
640 | set_dma_callback(uart->tx_dma_channel, bfin_serial_dma_tx_int, uart); | |
641 | ||
642 | uart->rx_dma_buf.buf = (unsigned char *)dma_alloc_coherent(NULL, PAGE_SIZE, &dma_handle, GFP_DMA); | |
643 | uart->rx_dma_buf.head = 0; | |
644 | uart->rx_dma_buf.tail = 0; | |
645 | uart->rx_dma_nrows = 0; | |
646 | ||
647 | set_dma_config(uart->rx_dma_channel, | |
648 | set_bfin_dma_config(DIR_WRITE, DMA_FLOW_AUTO, | |
649 | INTR_ON_ROW, DIMENSION_2D, | |
2047e40d MH |
650 | DATA_SIZE_8, |
651 | DMA_SYNC_RESTART)); | |
194de561 BW |
652 | set_dma_x_count(uart->rx_dma_channel, DMA_RX_XCOUNT); |
653 | set_dma_x_modify(uart->rx_dma_channel, 1); | |
654 | set_dma_y_count(uart->rx_dma_channel, DMA_RX_YCOUNT); | |
655 | set_dma_y_modify(uart->rx_dma_channel, 1); | |
656 | set_dma_start_addr(uart->rx_dma_channel, (unsigned long)uart->rx_dma_buf.buf); | |
657 | enable_dma(uart->rx_dma_channel); | |
658 | ||
659 | uart->rx_dma_timer.data = (unsigned long)(uart); | |
660 | uart->rx_dma_timer.function = (void *)bfin_serial_rx_dma_timeout; | |
661 | uart->rx_dma_timer.expires = jiffies + DMA_RX_FLUSH_JIFFIES; | |
662 | add_timer(&(uart->rx_dma_timer)); | |
663 | #else | |
6f95570e | 664 | # if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \ |
52e15f0e SZ |
665 | defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE) |
666 | if (kgdboc_port_line == uart->port.line && kgdboc_break_enabled) | |
667 | kgdboc_break_enabled = 0; | |
668 | else { | |
669 | # endif | |
a359cca7 SZ |
670 | if (request_irq(uart->port.irq, bfin_serial_rx_int, IRQF_DISABLED, |
671 | "BFIN_UART_RX", uart)) { | |
194de561 BW |
672 | printk(KERN_NOTICE "Unable to attach BlackFin UART RX interrupt\n"); |
673 | return -EBUSY; | |
674 | } | |
675 | ||
676 | if (request_irq | |
5c4e472b | 677 | (uart->port.irq+1, bfin_serial_tx_int, IRQF_DISABLED, |
194de561 BW |
678 | "BFIN_UART_TX", uart)) { |
679 | printk(KERN_NOTICE "Unable to attach BlackFin UART TX interrupt\n"); | |
680 | free_irq(uart->port.irq, uart); | |
681 | return -EBUSY; | |
682 | } | |
ab2375f2 SZ |
683 | |
684 | # ifdef CONFIG_BF54x | |
685 | { | |
b6100992 SZ |
686 | /* |
687 | * UART2 and UART3 on BF548 share interrupt PINs and DMA | |
688 | * controllers with SPORT2 and SPORT3. UART rx and tx | |
689 | * interrupts are generated in PIO mode only when configure | |
690 | * their peripheral mapping registers properly, which means | |
691 | * request corresponding DMA channels in PIO mode as well. | |
692 | */ | |
ab2375f2 SZ |
693 | unsigned uart_dma_ch_rx, uart_dma_ch_tx; |
694 | ||
695 | switch (uart->port.irq) { | |
696 | case IRQ_UART3_RX: | |
697 | uart_dma_ch_rx = CH_UART3_RX; | |
698 | uart_dma_ch_tx = CH_UART3_TX; | |
699 | break; | |
700 | case IRQ_UART2_RX: | |
701 | uart_dma_ch_rx = CH_UART2_RX; | |
702 | uart_dma_ch_tx = CH_UART2_TX; | |
703 | break; | |
704 | default: | |
705 | uart_dma_ch_rx = uart_dma_ch_tx = 0; | |
706 | break; | |
707 | }; | |
708 | ||
709 | if (uart_dma_ch_rx && | |
710 | request_dma(uart_dma_ch_rx, "BFIN_UART_RX") < 0) { | |
711 | printk(KERN_NOTICE"Fail to attach UART interrupt\n"); | |
712 | free_irq(uart->port.irq, uart); | |
713 | free_irq(uart->port.irq + 1, uart); | |
714 | return -EBUSY; | |
715 | } | |
716 | if (uart_dma_ch_tx && | |
717 | request_dma(uart_dma_ch_tx, "BFIN_UART_TX") < 0) { | |
718 | printk(KERN_NOTICE "Fail to attach UART interrupt\n"); | |
719 | free_dma(uart_dma_ch_rx); | |
720 | free_irq(uart->port.irq, uart); | |
721 | free_irq(uart->port.irq + 1, uart); | |
722 | return -EBUSY; | |
723 | } | |
724 | } | |
725 | # endif | |
6f95570e | 726 | # if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \ |
52e15f0e SZ |
727 | defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE) |
728 | } | |
729 | # endif | |
6f95570e SZ |
730 | #endif |
731 | ||
732 | #ifdef CONFIG_SERIAL_BFIN_CTSRTS | |
733 | if (uart->cts_pin >= 0) { | |
734 | if (request_irq(gpio_to_irq(uart->cts_pin), | |
735 | bfin_serial_mctrl_cts_int, | |
736 | IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING | | |
737 | IRQF_DISABLED, "BFIN_UART_CTS", uart)) { | |
738 | uart->cts_pin = -1; | |
a89f2466 | 739 | pr_info("Unable to attach BlackFin UART CTS interrupt. So, disable it.\n"); |
6f95570e SZ |
740 | } |
741 | } | |
742 | if (uart->rts_pin >= 0) { | |
6f95570e SZ |
743 | gpio_direction_output(uart->rts_pin, 0); |
744 | } | |
194de561 | 745 | #endif |
d307d36a | 746 | #ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS |
57afb399 | 747 | if (uart->cts_pin >= 0 && request_irq(uart->status_irq, |
d307d36a SZ |
748 | bfin_serial_mctrl_cts_int, |
749 | IRQF_DISABLED, "BFIN_UART_MODEM_STATUS", uart)) { | |
57afb399 | 750 | uart->cts_pin = -1; |
a89f2466 | 751 | pr_info("Unable to attach BlackFin UART Modem Status interrupt.\n"); |
d307d36a SZ |
752 | } |
753 | ||
d307d36a SZ |
754 | /* CTS RTS PINs are negative assertive. */ |
755 | UART_PUT_MCR(uart, ACTS); | |
756 | UART_SET_IER(uart, EDSSI); | |
757 | #endif | |
758 | ||
f4d640c9 | 759 | UART_SET_IER(uart, ERBFI); |
194de561 BW |
760 | return 0; |
761 | } | |
762 | ||
763 | static void bfin_serial_shutdown(struct uart_port *port) | |
764 | { | |
765 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
766 | ||
767 | #ifdef CONFIG_SERIAL_BFIN_DMA | |
768 | disable_dma(uart->tx_dma_channel); | |
769 | free_dma(uart->tx_dma_channel); | |
770 | disable_dma(uart->rx_dma_channel); | |
771 | free_dma(uart->rx_dma_channel); | |
772 | del_timer(&(uart->rx_dma_timer)); | |
75b780bd | 773 | dma_free_coherent(NULL, PAGE_SIZE, uart->rx_dma_buf.buf, 0); |
194de561 | 774 | #else |
ab2375f2 SZ |
775 | #ifdef CONFIG_BF54x |
776 | switch (uart->port.irq) { | |
777 | case IRQ_UART3_RX: | |
778 | free_dma(CH_UART3_RX); | |
779 | free_dma(CH_UART3_TX); | |
780 | break; | |
781 | case IRQ_UART2_RX: | |
782 | free_dma(CH_UART2_RX); | |
783 | free_dma(CH_UART2_TX); | |
784 | break; | |
785 | default: | |
786 | break; | |
787 | }; | |
474f1a66 | 788 | #endif |
194de561 BW |
789 | free_irq(uart->port.irq, uart); |
790 | free_irq(uart->port.irq+1, uart); | |
791 | #endif | |
6f95570e | 792 | |
d307d36a | 793 | #ifdef CONFIG_SERIAL_BFIN_CTSRTS |
6f95570e SZ |
794 | if (uart->cts_pin >= 0) |
795 | free_irq(gpio_to_irq(uart->cts_pin), uart); | |
d307d36a SZ |
796 | #endif |
797 | #ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS | |
57afb399 | 798 | if (uart->cts_pin >= 0) |
d307d36a SZ |
799 | free_irq(uart->status_irq, uart); |
800 | #endif | |
194de561 BW |
801 | } |
802 | ||
803 | static void | |
804 | bfin_serial_set_termios(struct uart_port *port, struct ktermios *termios, | |
805 | struct ktermios *old) | |
806 | { | |
807 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
808 | unsigned long flags; | |
809 | unsigned int baud, quot; | |
0c44a86d | 810 | unsigned short val, ier, lcr = 0; |
194de561 BW |
811 | |
812 | switch (termios->c_cflag & CSIZE) { | |
813 | case CS8: | |
814 | lcr = WLS(8); | |
815 | break; | |
816 | case CS7: | |
817 | lcr = WLS(7); | |
818 | break; | |
819 | case CS6: | |
820 | lcr = WLS(6); | |
821 | break; | |
822 | case CS5: | |
823 | lcr = WLS(5); | |
824 | break; | |
825 | default: | |
826 | printk(KERN_ERR "%s: word lengh not supported\n", | |
71cc2c21 | 827 | __func__); |
194de561 BW |
828 | } |
829 | ||
84507794 SZ |
830 | /* Anomaly notes: |
831 | * 05000231 - STOP bit is always set to 1 whatever the user is set. | |
832 | */ | |
833 | if (termios->c_cflag & CSTOPB) { | |
834 | if (ANOMALY_05000231) | |
835 | printk(KERN_WARNING "STOP bits other than 1 is not " | |
836 | "supported in case of anomaly 05000231.\n"); | |
837 | else | |
838 | lcr |= STB; | |
839 | } | |
19aa6382 | 840 | if (termios->c_cflag & PARENB) |
194de561 | 841 | lcr |= PEN; |
19aa6382 MF |
842 | if (!(termios->c_cflag & PARODD)) |
843 | lcr |= EPS; | |
844 | if (termios->c_cflag & CMSPAR) | |
845 | lcr |= STP; | |
194de561 | 846 | |
5bb06b62 SZ |
847 | spin_lock_irqsave(&uart->port.lock, flags); |
848 | ||
2ac5ee47 MF |
849 | port->read_status_mask = OE; |
850 | if (termios->c_iflag & INPCK) | |
851 | port->read_status_mask |= (FE | PE); | |
852 | if (termios->c_iflag & (BRKINT | PARMRK)) | |
853 | port->read_status_mask |= BI; | |
194de561 | 854 | |
2ac5ee47 MF |
855 | /* |
856 | * Characters to ignore | |
857 | */ | |
858 | port->ignore_status_mask = 0; | |
859 | if (termios->c_iflag & IGNPAR) | |
860 | port->ignore_status_mask |= FE | PE; | |
861 | if (termios->c_iflag & IGNBRK) { | |
862 | port->ignore_status_mask |= BI; | |
863 | /* | |
864 | * If we're ignoring parity and break indicators, | |
865 | * ignore overruns too (for real raw support). | |
866 | */ | |
867 | if (termios->c_iflag & IGNPAR) | |
868 | port->ignore_status_mask |= OE; | |
869 | } | |
194de561 BW |
870 | |
871 | baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16); | |
ca3e442e GY |
872 | quot = uart_get_divisor(port, baud); |
873 | ||
874 | /* If discipline is not IRDA, apply ANOMALY_05000230 */ | |
875 | if (termios->c_line != N_IRDA) | |
876 | quot -= ANOMALY_05000230; | |
877 | ||
8851c71e MF |
878 | UART_SET_ANOMALY_THRESHOLD(uart, USEC_PER_SEC / baud * 15); |
879 | ||
194de561 BW |
880 | /* Disable UART */ |
881 | ier = UART_GET_IER(uart); | |
1feaa51d | 882 | UART_DISABLE_INTS(uart); |
194de561 BW |
883 | |
884 | /* Set DLAB in LCR to Access DLL and DLH */ | |
45828b81 | 885 | UART_SET_DLAB(uart); |
194de561 BW |
886 | |
887 | UART_PUT_DLL(uart, quot & 0xFF); | |
194de561 BW |
888 | UART_PUT_DLH(uart, (quot >> 8) & 0xFF); |
889 | SSYNC(); | |
890 | ||
891 | /* Clear DLAB in LCR to Access THR RBR IER */ | |
45828b81 | 892 | UART_CLEAR_DLAB(uart); |
194de561 BW |
893 | |
894 | UART_PUT_LCR(uart, lcr); | |
895 | ||
896 | /* Enable UART */ | |
1feaa51d | 897 | UART_ENABLE_INTS(uart, ier); |
194de561 BW |
898 | |
899 | val = UART_GET_GCTL(uart); | |
900 | val |= UCEN; | |
901 | UART_PUT_GCTL(uart, val); | |
902 | ||
b3ef5aba GY |
903 | /* Port speed changed, update the per-port timeout. */ |
904 | uart_update_timeout(port, termios->c_cflag, baud); | |
905 | ||
194de561 BW |
906 | spin_unlock_irqrestore(&uart->port.lock, flags); |
907 | } | |
908 | ||
909 | static const char *bfin_serial_type(struct uart_port *port) | |
910 | { | |
911 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
912 | ||
913 | return uart->port.type == PORT_BFIN ? "BFIN-UART" : NULL; | |
914 | } | |
915 | ||
916 | /* | |
917 | * Release the memory region(s) being used by 'port'. | |
918 | */ | |
919 | static void bfin_serial_release_port(struct uart_port *port) | |
920 | { | |
921 | } | |
922 | ||
923 | /* | |
924 | * Request the memory region(s) being used by 'port'. | |
925 | */ | |
926 | static int bfin_serial_request_port(struct uart_port *port) | |
927 | { | |
928 | return 0; | |
929 | } | |
930 | ||
931 | /* | |
932 | * Configure/autoconfigure the port. | |
933 | */ | |
934 | static void bfin_serial_config_port(struct uart_port *port, int flags) | |
935 | { | |
936 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
937 | ||
938 | if (flags & UART_CONFIG_TYPE && | |
939 | bfin_serial_request_port(&uart->port) == 0) | |
940 | uart->port.type = PORT_BFIN; | |
941 | } | |
942 | ||
943 | /* | |
944 | * Verify the new serial_struct (for TIOCSSERIAL). | |
945 | * The only change we allow are to the flags and type, and | |
946 | * even then only between PORT_BFIN and PORT_UNKNOWN | |
947 | */ | |
948 | static int | |
949 | bfin_serial_verify_port(struct uart_port *port, struct serial_struct *ser) | |
950 | { | |
951 | return 0; | |
952 | } | |
953 | ||
7d01b475 GY |
954 | /* |
955 | * Enable the IrDA function if tty->ldisc.num is N_IRDA. | |
956 | * In other cases, disable IrDA function. | |
957 | */ | |
d87d9b7d | 958 | static void bfin_serial_set_ldisc(struct uart_port *port, int ld) |
7d01b475 | 959 | { |
57afb399 | 960 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; |
7d01b475 GY |
961 | unsigned short val; |
962 | ||
d87d9b7d | 963 | switch (ld) { |
7d01b475 | 964 | case N_IRDA: |
57afb399 | 965 | val = UART_GET_GCTL(uart); |
7d01b475 | 966 | val |= (IREN | RPOLC); |
57afb399 | 967 | UART_PUT_GCTL(uart, val); |
7d01b475 GY |
968 | break; |
969 | default: | |
57afb399 | 970 | val = UART_GET_GCTL(uart); |
7d01b475 | 971 | val &= ~(IREN | RPOLC); |
57afb399 | 972 | UART_PUT_GCTL(uart, val); |
7d01b475 GY |
973 | } |
974 | } | |
975 | ||
6f95570e SZ |
976 | static void bfin_serial_reset_irda(struct uart_port *port) |
977 | { | |
57afb399 | 978 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; |
6f95570e SZ |
979 | unsigned short val; |
980 | ||
57afb399 | 981 | val = UART_GET_GCTL(uart); |
6f95570e | 982 | val &= ~(IREN | RPOLC); |
57afb399 | 983 | UART_PUT_GCTL(uart, val); |
6f95570e SZ |
984 | SSYNC(); |
985 | val |= (IREN | RPOLC); | |
57afb399 | 986 | UART_PUT_GCTL(uart, val); |
6f95570e SZ |
987 | SSYNC(); |
988 | } | |
989 | ||
52e15f0e | 990 | #ifdef CONFIG_CONSOLE_POLL |
0efa4f2c SZ |
991 | /* Anomaly notes: |
992 | * 05000099 - Because we only use THRE in poll_put and DR in poll_get, | |
993 | * losing other bits of UART_LSR is not a problem here. | |
994 | */ | |
52e15f0e SZ |
995 | static void bfin_serial_poll_put_char(struct uart_port *port, unsigned char chr) |
996 | { | |
997 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
998 | ||
999 | while (!(UART_GET_LSR(uart) & THRE)) | |
1000 | cpu_relax(); | |
1001 | ||
1002 | UART_CLEAR_DLAB(uart); | |
1003 | UART_PUT_CHAR(uart, (unsigned char)chr); | |
1004 | } | |
1005 | ||
1006 | static int bfin_serial_poll_get_char(struct uart_port *port) | |
1007 | { | |
1008 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
1009 | unsigned char chr; | |
1010 | ||
1011 | while (!(UART_GET_LSR(uart) & DR)) | |
1012 | cpu_relax(); | |
1013 | ||
1014 | UART_CLEAR_DLAB(uart); | |
1015 | chr = UART_GET_CHAR(uart); | |
1016 | ||
1017 | return chr; | |
1018 | } | |
1019 | #endif | |
1020 | ||
1021 | #if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \ | |
1022 | defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE) | |
1023 | static void bfin_kgdboc_port_shutdown(struct uart_port *port) | |
1024 | { | |
1025 | if (kgdboc_break_enabled) { | |
1026 | kgdboc_break_enabled = 0; | |
1027 | bfin_serial_shutdown(port); | |
1028 | } | |
1029 | } | |
1030 | ||
1031 | static int bfin_kgdboc_port_startup(struct uart_port *port) | |
1032 | { | |
1033 | kgdboc_port_line = port->line; | |
1034 | kgdboc_break_enabled = !bfin_serial_startup(port); | |
1035 | return 0; | |
1036 | } | |
1037 | #endif | |
1038 | ||
194de561 BW |
1039 | static struct uart_ops bfin_serial_pops = { |
1040 | .tx_empty = bfin_serial_tx_empty, | |
1041 | .set_mctrl = bfin_serial_set_mctrl, | |
1042 | .get_mctrl = bfin_serial_get_mctrl, | |
1043 | .stop_tx = bfin_serial_stop_tx, | |
1044 | .start_tx = bfin_serial_start_tx, | |
1045 | .stop_rx = bfin_serial_stop_rx, | |
1046 | .enable_ms = bfin_serial_enable_ms, | |
1047 | .break_ctl = bfin_serial_break_ctl, | |
1048 | .startup = bfin_serial_startup, | |
1049 | .shutdown = bfin_serial_shutdown, | |
1050 | .set_termios = bfin_serial_set_termios, | |
3b8458a9 | 1051 | .set_ldisc = bfin_serial_set_ldisc, |
194de561 BW |
1052 | .type = bfin_serial_type, |
1053 | .release_port = bfin_serial_release_port, | |
1054 | .request_port = bfin_serial_request_port, | |
1055 | .config_port = bfin_serial_config_port, | |
1056 | .verify_port = bfin_serial_verify_port, | |
52e15f0e SZ |
1057 | #if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \ |
1058 | defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE) | |
1059 | .kgdboc_port_startup = bfin_kgdboc_port_startup, | |
1060 | .kgdboc_port_shutdown = bfin_kgdboc_port_shutdown, | |
1061 | #endif | |
1062 | #ifdef CONFIG_CONSOLE_POLL | |
1063 | .poll_put_char = bfin_serial_poll_put_char, | |
1064 | .poll_get_char = bfin_serial_poll_get_char, | |
1065 | #endif | |
194de561 BW |
1066 | }; |
1067 | ||
b6efa1ea | 1068 | #if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK) |
194de561 BW |
1069 | /* |
1070 | * If the port was already initialised (eg, by a boot loader), | |
1071 | * try to determine the current setup. | |
1072 | */ | |
1073 | static void __init | |
1074 | bfin_serial_console_get_options(struct bfin_serial_port *uart, int *baud, | |
1075 | int *parity, int *bits) | |
1076 | { | |
1077 | unsigned short status; | |
1078 | ||
1079 | status = UART_GET_IER(uart) & (ERBFI | ETBEI); | |
1080 | if (status == (ERBFI | ETBEI)) { | |
1081 | /* ok, the port was enabled */ | |
45828b81 | 1082 | u16 lcr, dlh, dll; |
194de561 BW |
1083 | |
1084 | lcr = UART_GET_LCR(uart); | |
1085 | ||
1086 | *parity = 'n'; | |
1087 | if (lcr & PEN) { | |
1088 | if (lcr & EPS) | |
1089 | *parity = 'e'; | |
1090 | else | |
1091 | *parity = 'o'; | |
1092 | } | |
1093 | switch (lcr & 0x03) { | |
1094 | case 0: *bits = 5; break; | |
1095 | case 1: *bits = 6; break; | |
1096 | case 2: *bits = 7; break; | |
1097 | case 3: *bits = 8; break; | |
1098 | } | |
1099 | /* Set DLAB in LCR to Access DLL and DLH */ | |
45828b81 | 1100 | UART_SET_DLAB(uart); |
194de561 BW |
1101 | |
1102 | dll = UART_GET_DLL(uart); | |
1103 | dlh = UART_GET_DLH(uart); | |
1104 | ||
1105 | /* Clear DLAB in LCR to Access THR RBR IER */ | |
45828b81 | 1106 | UART_CLEAR_DLAB(uart); |
194de561 BW |
1107 | |
1108 | *baud = get_sclk() / (16*(dll | dlh << 8)); | |
1109 | } | |
71cc2c21 | 1110 | pr_debug("%s:baud = %d, parity = %c, bits= %d\n", __func__, *baud, *parity, *bits); |
194de561 | 1111 | } |
0ae53640 | 1112 | |
0ae53640 | 1113 | static struct uart_driver bfin_serial_reg; |
194de561 | 1114 | |
57afb399 SZ |
1115 | static void bfin_serial_console_putchar(struct uart_port *port, int ch) |
1116 | { | |
1117 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
1118 | while (!(UART_GET_LSR(uart) & THRE)) | |
1119 | barrier(); | |
1120 | UART_PUT_CHAR(uart, ch); | |
1121 | } | |
1122 | ||
1123 | #endif /* defined (CONFIG_SERIAL_BFIN_CONSOLE) || | |
1124 | defined (CONFIG_EARLY_PRINTK) */ | |
1125 | ||
1126 | #ifdef CONFIG_SERIAL_BFIN_CONSOLE | |
1127 | #define CLASS_BFIN_CONSOLE "bfin-console" | |
1128 | /* | |
1129 | * Interrupts are disabled on entering | |
1130 | */ | |
1131 | static void | |
1132 | bfin_serial_console_write(struct console *co, const char *s, unsigned int count) | |
1133 | { | |
1134 | struct bfin_serial_port *uart = bfin_serial_ports[co->index]; | |
1135 | unsigned long flags; | |
1136 | ||
1137 | spin_lock_irqsave(&uart->port.lock, flags); | |
1138 | uart_console_write(&uart->port, s, count, bfin_serial_console_putchar); | |
1139 | spin_unlock_irqrestore(&uart->port.lock, flags); | |
1140 | ||
1141 | } | |
1142 | ||
194de561 BW |
1143 | static int __init |
1144 | bfin_serial_console_setup(struct console *co, char *options) | |
1145 | { | |
1146 | struct bfin_serial_port *uart; | |
1147 | int baud = 57600; | |
1148 | int bits = 8; | |
1149 | int parity = 'n'; | |
d307d36a SZ |
1150 | # if defined(CONFIG_SERIAL_BFIN_CTSRTS) || \ |
1151 | defined(CONFIG_SERIAL_BFIN_HARD_CTSRTS) | |
194de561 | 1152 | int flow = 'r'; |
b6efa1ea | 1153 | # else |
194de561 | 1154 | int flow = 'n'; |
0ae53640 | 1155 | # endif |
194de561 BW |
1156 | |
1157 | /* | |
1158 | * Check whether an invalid uart number has been specified, and | |
1159 | * if so, search for the first available port that does have | |
1160 | * console support. | |
1161 | */ | |
57afb399 SZ |
1162 | if (co->index < 0 || co->index >= BFIN_UART_NR_PORTS) |
1163 | return -ENODEV; | |
1164 | ||
1165 | uart = bfin_serial_ports[co->index]; | |
1166 | if (!uart) | |
1167 | return -ENODEV; | |
194de561 BW |
1168 | |
1169 | if (options) | |
1170 | uart_parse_options(options, &baud, &parity, &bits, &flow); | |
1171 | else | |
1172 | bfin_serial_console_get_options(uart, &baud, &parity, &bits); | |
1173 | ||
1174 | return uart_set_options(&uart->port, co, baud, parity, bits, flow); | |
0ae53640 | 1175 | } |
194de561 | 1176 | |
194de561 | 1177 | static struct console bfin_serial_console = { |
57afb399 | 1178 | .name = BFIN_SERIAL_DEV_NAME, |
194de561 BW |
1179 | .write = bfin_serial_console_write, |
1180 | .device = uart_console_device, | |
1181 | .setup = bfin_serial_console_setup, | |
1182 | .flags = CON_PRINTBUFFER, | |
1183 | .index = -1, | |
1184 | .data = &bfin_serial_reg, | |
1185 | }; | |
194de561 BW |
1186 | #define BFIN_SERIAL_CONSOLE &bfin_serial_console |
1187 | #else | |
1188 | #define BFIN_SERIAL_CONSOLE NULL | |
0ae53640 RG |
1189 | #endif /* CONFIG_SERIAL_BFIN_CONSOLE */ |
1190 | ||
57afb399 SZ |
1191 | #ifdef CONFIG_EARLY_PRINTK |
1192 | static struct bfin_serial_port bfin_earlyprintk_port; | |
1193 | #define CLASS_BFIN_EARLYPRINTK "bfin-earlyprintk" | |
0ae53640 | 1194 | |
57afb399 SZ |
1195 | /* |
1196 | * Interrupts are disabled on entering | |
1197 | */ | |
1198 | static void | |
1199 | bfin_earlyprintk_console_write(struct console *co, const char *s, unsigned int count) | |
0ae53640 | 1200 | { |
57afb399 | 1201 | unsigned long flags; |
0ae53640 | 1202 | |
57afb399 SZ |
1203 | if (bfin_earlyprintk_port.port.line != co->index) |
1204 | return; | |
0ae53640 | 1205 | |
57afb399 SZ |
1206 | spin_lock_irqsave(&bfin_earlyprintk_port.port.lock, flags); |
1207 | uart_console_write(&bfin_earlyprintk_port.port, s, count, | |
1208 | bfin_serial_console_putchar); | |
1209 | spin_unlock_irqrestore(&bfin_earlyprintk_port.port.lock, flags); | |
0ae53640 RG |
1210 | } |
1211 | ||
7de7c55b RG |
1212 | /* |
1213 | * This should have a .setup or .early_setup in it, but then things get called | |
1214 | * without the command line options, and the baud rate gets messed up - so | |
1215 | * don't let the common infrastructure play with things. (see calls to setup | |
1216 | * & earlysetup in ./kernel/printk.c:register_console() | |
1217 | */ | |
c1113400 | 1218 | static struct __initdata console bfin_early_serial_console = { |
0ae53640 | 1219 | .name = "early_BFuart", |
57afb399 | 1220 | .write = bfin_earlyprintk_console_write, |
0ae53640 RG |
1221 | .device = uart_console_device, |
1222 | .flags = CON_PRINTBUFFER, | |
0ae53640 RG |
1223 | .index = -1, |
1224 | .data = &bfin_serial_reg, | |
1225 | }; | |
6d9e4498 SZ |
1226 | #endif |
1227 | ||
194de561 BW |
1228 | static struct uart_driver bfin_serial_reg = { |
1229 | .owner = THIS_MODULE, | |
57afb399 SZ |
1230 | .driver_name = DRIVER_NAME, |
1231 | .dev_name = BFIN_SERIAL_DEV_NAME, | |
194de561 BW |
1232 | .major = BFIN_SERIAL_MAJOR, |
1233 | .minor = BFIN_SERIAL_MINOR, | |
2ade9729 | 1234 | .nr = BFIN_UART_NR_PORTS, |
194de561 BW |
1235 | .cons = BFIN_SERIAL_CONSOLE, |
1236 | }; | |
1237 | ||
57afb399 | 1238 | static int bfin_serial_suspend(struct platform_device *pdev, pm_message_t state) |
194de561 | 1239 | { |
57afb399 | 1240 | struct bfin_serial_port *uart = platform_get_drvdata(pdev); |
194de561 | 1241 | |
57afb399 SZ |
1242 | return uart_suspend_port(&bfin_serial_reg, &uart->port); |
1243 | } | |
194de561 | 1244 | |
57afb399 SZ |
1245 | static int bfin_serial_resume(struct platform_device *pdev) |
1246 | { | |
1247 | struct bfin_serial_port *uart = platform_get_drvdata(pdev); | |
1248 | ||
1249 | return uart_resume_port(&bfin_serial_reg, &uart->port); | |
194de561 BW |
1250 | } |
1251 | ||
57afb399 | 1252 | static int bfin_serial_probe(struct platform_device *pdev) |
194de561 | 1253 | { |
57afb399 SZ |
1254 | struct resource *res; |
1255 | struct bfin_serial_port *uart = NULL; | |
1256 | int ret = 0; | |
194de561 | 1257 | |
57afb399 SZ |
1258 | if (pdev->id < 0 || pdev->id >= BFIN_UART_NR_PORTS) { |
1259 | dev_err(&pdev->dev, "Wrong bfin uart platform device id.\n"); | |
1260 | return -ENOENT; | |
ccfbc3e1 | 1261 | } |
194de561 | 1262 | |
57afb399 | 1263 | if (bfin_serial_ports[pdev->id] == NULL) { |
194de561 | 1264 | |
57afb399 SZ |
1265 | uart = kzalloc(sizeof(*uart), GFP_KERNEL); |
1266 | if (!uart) { | |
1267 | dev_err(&pdev->dev, | |
1268 | "fail to malloc bfin_serial_port\n"); | |
1269 | return -ENOMEM; | |
1270 | } | |
1271 | bfin_serial_ports[pdev->id] = uart; | |
194de561 | 1272 | |
57afb399 SZ |
1273 | #ifdef CONFIG_EARLY_PRINTK |
1274 | if (!(bfin_earlyprintk_port.port.membase | |
1275 | && bfin_earlyprintk_port.port.line == pdev->id)) { | |
1276 | /* | |
1277 | * If the peripheral PINs of current port is allocated | |
1278 | * in earlyprintk probe stage, don't do it again. | |
1279 | */ | |
1280 | #endif | |
1281 | ret = peripheral_request_list( | |
1282 | (unsigned short *)pdev->dev.platform_data, DRIVER_NAME); | |
1283 | if (ret) { | |
1284 | dev_err(&pdev->dev, | |
1285 | "fail to request bfin serial peripherals\n"); | |
1286 | goto out_error_free_mem; | |
1287 | } | |
1288 | #ifdef CONFIG_EARLY_PRINTK | |
1289 | } | |
1290 | #endif | |
1291 | ||
1292 | spin_lock_init(&uart->port.lock); | |
1293 | uart->port.uartclk = get_sclk(); | |
1294 | uart->port.fifosize = BFIN_UART_TX_FIFO_SIZE; | |
1295 | uart->port.ops = &bfin_serial_pops; | |
1296 | uart->port.line = pdev->id; | |
1297 | uart->port.iotype = UPIO_MEM; | |
1298 | uart->port.flags = UPF_BOOT_AUTOCONF; | |
1299 | ||
1300 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1301 | if (res == NULL) { | |
1302 | dev_err(&pdev->dev, "Cannot get IORESOURCE_MEM\n"); | |
1303 | ret = -ENOENT; | |
1304 | goto out_error_free_peripherals; | |
1305 | } | |
1306 | ||
28f65c11 | 1307 | uart->port.membase = ioremap(res->start, resource_size(res)); |
57afb399 SZ |
1308 | if (!uart->port.membase) { |
1309 | dev_err(&pdev->dev, "Cannot map uart IO\n"); | |
1310 | ret = -ENXIO; | |
1311 | goto out_error_free_peripherals; | |
1312 | } | |
1313 | uart->port.mapbase = res->start; | |
194de561 | 1314 | |
57afb399 SZ |
1315 | uart->port.irq = platform_get_irq(pdev, 0); |
1316 | if (uart->port.irq < 0) { | |
1317 | dev_err(&pdev->dev, "No uart RX/TX IRQ specified\n"); | |
1318 | ret = -ENOENT; | |
1319 | goto out_error_unmap; | |
194de561 | 1320 | } |
57afb399 SZ |
1321 | |
1322 | uart->status_irq = platform_get_irq(pdev, 1); | |
1323 | if (uart->status_irq < 0) { | |
1324 | dev_err(&pdev->dev, "No uart status IRQ specified\n"); | |
1325 | ret = -ENOENT; | |
1326 | goto out_error_unmap; | |
1327 | } | |
1328 | ||
1329 | #ifdef CONFIG_SERIAL_BFIN_DMA | |
0f66e50a | 1330 | spin_lock_init(&uart->rx_lock); |
57afb399 SZ |
1331 | uart->tx_done = 1; |
1332 | uart->tx_count = 0; | |
1333 | ||
1334 | res = platform_get_resource(pdev, IORESOURCE_DMA, 0); | |
1335 | if (res == NULL) { | |
1336 | dev_err(&pdev->dev, "No uart TX DMA channel specified\n"); | |
1337 | ret = -ENOENT; | |
1338 | goto out_error_unmap; | |
1339 | } | |
1340 | uart->tx_dma_channel = res->start; | |
1341 | ||
1342 | res = platform_get_resource(pdev, IORESOURCE_DMA, 1); | |
1343 | if (res == NULL) { | |
1344 | dev_err(&pdev->dev, "No uart RX DMA channel specified\n"); | |
1345 | ret = -ENOENT; | |
1346 | goto out_error_unmap; | |
1347 | } | |
1348 | uart->rx_dma_channel = res->start; | |
1349 | ||
1350 | init_timer(&(uart->rx_dma_timer)); | |
1351 | #endif | |
1352 | ||
1353 | #if defined(CONFIG_SERIAL_BFIN_CTSRTS) || \ | |
1354 | defined(CONFIG_SERIAL_BFIN_HARD_CTSRTS) | |
1355 | res = platform_get_resource(pdev, IORESOURCE_IO, 0); | |
1356 | if (res == NULL) | |
1357 | uart->cts_pin = -1; | |
1358 | else | |
1359 | uart->cts_pin = res->start; | |
1360 | ||
1361 | res = platform_get_resource(pdev, IORESOURCE_IO, 1); | |
1362 | if (res == NULL) | |
1363 | uart->rts_pin = -1; | |
1364 | else | |
1365 | uart->rts_pin = res->start; | |
1366 | # if defined(CONFIG_SERIAL_BFIN_CTSRTS) | |
1367 | if (uart->rts_pin >= 0) | |
1368 | gpio_request(uart->rts_pin, DRIVER_NAME); | |
1369 | # endif | |
1370 | #endif | |
194de561 BW |
1371 | } |
1372 | ||
57afb399 SZ |
1373 | #ifdef CONFIG_SERIAL_BFIN_CONSOLE |
1374 | if (!is_early_platform_device(pdev)) { | |
1375 | #endif | |
1376 | uart = bfin_serial_ports[pdev->id]; | |
1377 | uart->port.dev = &pdev->dev; | |
1378 | dev_set_drvdata(&pdev->dev, uart); | |
1379 | ret = uart_add_one_port(&bfin_serial_reg, &uart->port); | |
1380 | #ifdef CONFIG_SERIAL_BFIN_CONSOLE | |
1381 | } | |
1382 | #endif | |
1383 | ||
1384 | if (!ret) | |
1385 | return 0; | |
1386 | ||
1387 | if (uart) { | |
1388 | out_error_unmap: | |
1389 | iounmap(uart->port.membase); | |
1390 | out_error_free_peripherals: | |
1391 | peripheral_free_list( | |
1392 | (unsigned short *)pdev->dev.platform_data); | |
1393 | out_error_free_mem: | |
1394 | kfree(uart); | |
1395 | bfin_serial_ports[pdev->id] = NULL; | |
1396 | } | |
1397 | ||
1398 | return ret; | |
194de561 BW |
1399 | } |
1400 | ||
57afb399 | 1401 | static int __devexit bfin_serial_remove(struct platform_device *pdev) |
194de561 | 1402 | { |
57afb399 SZ |
1403 | struct bfin_serial_port *uart = platform_get_drvdata(pdev); |
1404 | ||
1405 | dev_set_drvdata(&pdev->dev, NULL); | |
1406 | ||
1407 | if (uart) { | |
1408 | uart_remove_one_port(&bfin_serial_reg, &uart->port); | |
1409 | #ifdef CONFIG_SERIAL_BFIN_CTSRTS | |
1410 | if (uart->rts_pin >= 0) | |
1411 | gpio_free(uart->rts_pin); | |
194de561 | 1412 | #endif |
57afb399 SZ |
1413 | iounmap(uart->port.membase); |
1414 | peripheral_free_list( | |
1415 | (unsigned short *)pdev->dev.platform_data); | |
1416 | kfree(uart); | |
1417 | bfin_serial_ports[pdev->id] = NULL; | |
ccfbc3e1 | 1418 | } |
194de561 BW |
1419 | |
1420 | return 0; | |
1421 | } | |
1422 | ||
1423 | static struct platform_driver bfin_serial_driver = { | |
1424 | .probe = bfin_serial_probe, | |
57afb399 | 1425 | .remove = __devexit_p(bfin_serial_remove), |
194de561 BW |
1426 | .suspend = bfin_serial_suspend, |
1427 | .resume = bfin_serial_resume, | |
1428 | .driver = { | |
57afb399 | 1429 | .name = DRIVER_NAME, |
e169c139 | 1430 | .owner = THIS_MODULE, |
194de561 BW |
1431 | }, |
1432 | }; | |
1433 | ||
57afb399 SZ |
1434 | #if defined(CONFIG_SERIAL_BFIN_CONSOLE) |
1435 | static __initdata struct early_platform_driver early_bfin_serial_driver = { | |
1436 | .class_str = CLASS_BFIN_CONSOLE, | |
1437 | .pdrv = &bfin_serial_driver, | |
1438 | .requested_id = EARLY_PLATFORM_ID_UNSET, | |
1439 | }; | |
1440 | ||
1441 | static int __init bfin_serial_rs_console_init(void) | |
1442 | { | |
1443 | early_platform_driver_register(&early_bfin_serial_driver, DRIVER_NAME); | |
1444 | ||
1445 | early_platform_driver_probe(CLASS_BFIN_CONSOLE, BFIN_UART_NR_PORTS, 0); | |
1446 | ||
1447 | register_console(&bfin_serial_console); | |
1448 | ||
1449 | return 0; | |
1450 | } | |
1451 | console_initcall(bfin_serial_rs_console_init); | |
1452 | #endif | |
1453 | ||
1454 | #ifdef CONFIG_EARLY_PRINTK | |
1455 | /* | |
1456 | * Memory can't be allocated dynamically during earlyprink init stage. | |
1457 | * So, do individual probe for earlyprink with a static uart port variable. | |
1458 | */ | |
1459 | static int bfin_earlyprintk_probe(struct platform_device *pdev) | |
194de561 | 1460 | { |
57afb399 | 1461 | struct resource *res; |
194de561 BW |
1462 | int ret; |
1463 | ||
57afb399 SZ |
1464 | if (pdev->id < 0 || pdev->id >= BFIN_UART_NR_PORTS) { |
1465 | dev_err(&pdev->dev, "Wrong earlyprintk platform device id.\n"); | |
1466 | return -ENOENT; | |
1467 | } | |
1468 | ||
1469 | ret = peripheral_request_list( | |
1470 | (unsigned short *)pdev->dev.platform_data, DRIVER_NAME); | |
1471 | if (ret) { | |
1472 | dev_err(&pdev->dev, | |
1473 | "fail to request bfin serial peripherals\n"); | |
1474 | return ret; | |
1475 | } | |
1476 | ||
1477 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1478 | if (res == NULL) { | |
1479 | dev_err(&pdev->dev, "Cannot get IORESOURCE_MEM\n"); | |
1480 | ret = -ENOENT; | |
1481 | goto out_error_free_peripherals; | |
1482 | } | |
1483 | ||
1484 | bfin_earlyprintk_port.port.membase = ioremap(res->start, | |
28f65c11 | 1485 | resource_size(res)); |
57afb399 SZ |
1486 | if (!bfin_earlyprintk_port.port.membase) { |
1487 | dev_err(&pdev->dev, "Cannot map uart IO\n"); | |
1488 | ret = -ENXIO; | |
1489 | goto out_error_free_peripherals; | |
1490 | } | |
1491 | bfin_earlyprintk_port.port.mapbase = res->start; | |
1492 | bfin_earlyprintk_port.port.line = pdev->id; | |
1493 | bfin_earlyprintk_port.port.uartclk = get_sclk(); | |
1494 | bfin_earlyprintk_port.port.fifosize = BFIN_UART_TX_FIFO_SIZE; | |
1495 | spin_lock_init(&bfin_earlyprintk_port.port.lock); | |
1496 | ||
1497 | return 0; | |
1498 | ||
1499 | out_error_free_peripherals: | |
1500 | peripheral_free_list( | |
1501 | (unsigned short *)pdev->dev.platform_data); | |
1502 | ||
1503 | return ret; | |
1504 | } | |
1505 | ||
1506 | static struct platform_driver bfin_earlyprintk_driver = { | |
1507 | .probe = bfin_earlyprintk_probe, | |
1508 | .driver = { | |
1509 | .name = DRIVER_NAME, | |
1510 | .owner = THIS_MODULE, | |
1511 | }, | |
1512 | }; | |
1513 | ||
1514 | static __initdata struct early_platform_driver early_bfin_earlyprintk_driver = { | |
1515 | .class_str = CLASS_BFIN_EARLYPRINTK, | |
1516 | .pdrv = &bfin_earlyprintk_driver, | |
1517 | .requested_id = EARLY_PLATFORM_ID_UNSET, | |
1518 | }; | |
1519 | ||
1520 | struct console __init *bfin_earlyserial_init(unsigned int port, | |
1521 | unsigned int cflag) | |
1522 | { | |
1523 | struct ktermios t; | |
1524 | char port_name[20]; | |
194de561 | 1525 | |
57afb399 SZ |
1526 | if (port < 0 || port >= BFIN_UART_NR_PORTS) |
1527 | return NULL; | |
1528 | ||
1529 | /* | |
1530 | * Only probe resource of the given port in earlyprintk boot arg. | |
1531 | * The expected port id should be indicated in port name string. | |
1532 | */ | |
1533 | snprintf(port_name, 20, DRIVER_NAME ".%d", port); | |
1534 | early_platform_driver_register(&early_bfin_earlyprintk_driver, | |
1535 | port_name); | |
1536 | early_platform_driver_probe(CLASS_BFIN_EARLYPRINTK, 1, 0); | |
1537 | ||
1538 | if (!bfin_earlyprintk_port.port.membase) | |
1539 | return NULL; | |
1540 | ||
1541 | #ifdef CONFIG_SERIAL_BFIN_CONSOLE | |
1542 | /* | |
1543 | * If we are using early serial, don't let the normal console rewind | |
1544 | * log buffer, since that causes things to be printed multiple times | |
1545 | */ | |
1546 | bfin_serial_console.flags &= ~CON_PRINTBUFFER; | |
1547 | #endif | |
1548 | ||
1549 | bfin_early_serial_console.index = port; | |
1550 | t.c_cflag = cflag; | |
1551 | t.c_iflag = 0; | |
1552 | t.c_oflag = 0; | |
1553 | t.c_lflag = ICANON; | |
1554 | t.c_line = port; | |
1555 | bfin_serial_set_termios(&bfin_earlyprintk_port.port, &t, &t); | |
1556 | ||
1557 | return &bfin_early_serial_console; | |
1558 | } | |
1559 | #endif /* CONFIG_EARLY_PRINTK */ | |
1560 | ||
1561 | static int __init bfin_serial_init(void) | |
1562 | { | |
1563 | int ret; | |
1564 | ||
1565 | pr_info("Blackfin serial driver\n"); | |
194de561 BW |
1566 | |
1567 | ret = uart_register_driver(&bfin_serial_reg); | |
57afb399 SZ |
1568 | if (ret) { |
1569 | pr_err("failed to register %s:%d\n", | |
1570 | bfin_serial_reg.driver_name, ret); | |
1571 | } | |
1572 | ||
1573 | ret = platform_driver_register(&bfin_serial_driver); | |
1574 | if (ret) { | |
1575 | pr_err("fail to register bfin uart\n"); | |
1576 | uart_unregister_driver(&bfin_serial_reg); | |
194de561 | 1577 | } |
57afb399 | 1578 | |
194de561 BW |
1579 | return ret; |
1580 | } | |
1581 | ||
1582 | static void __exit bfin_serial_exit(void) | |
1583 | { | |
1584 | platform_driver_unregister(&bfin_serial_driver); | |
1585 | uart_unregister_driver(&bfin_serial_reg); | |
1586 | } | |
1587 | ||
52e15f0e | 1588 | |
194de561 BW |
1589 | module_init(bfin_serial_init); |
1590 | module_exit(bfin_serial_exit); | |
1591 | ||
57afb399 | 1592 | MODULE_AUTHOR("Sonic Zhang, Aubrey Li"); |
194de561 BW |
1593 | MODULE_DESCRIPTION("Blackfin generic serial port driver"); |
1594 | MODULE_LICENSE("GPL"); | |
1595 | MODULE_ALIAS_CHARDEV_MAJOR(BFIN_SERIAL_MAJOR); | |
e169c139 | 1596 | MODULE_ALIAS("platform:bfin-uart"); |