Commit | Line | Data |
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1e6c9c28 | 1 | /* |
7192f92c | 2 | * Driver for Atmel AT91 / AT32 Serial ports |
1e6c9c28 AV |
3 | * Copyright (C) 2003 Rick Bronson |
4 | * | |
5 | * Based on drivers/char/serial_sa1100.c, by Deep Blue Solutions Ltd. | |
6 | * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. | |
7 | * | |
a6670615 CC |
8 | * DMA support added by Chip Coldwell. |
9 | * | |
1e6c9c28 AV |
10 | * This program is free software; you can redistribute it and/or modify |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; either version 2 of the License, or | |
13 | * (at your option) any later version. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | * GNU General Public License for more details. | |
19 | * | |
20 | * You should have received a copy of the GNU General Public License | |
21 | * along with this program; if not, write to the Free Software | |
22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
23 | * | |
24 | */ | |
1e6c9c28 AV |
25 | #include <linux/module.h> |
26 | #include <linux/tty.h> | |
27 | #include <linux/ioport.h> | |
28 | #include <linux/slab.h> | |
29 | #include <linux/init.h> | |
30 | #include <linux/serial.h> | |
afefc415 | 31 | #include <linux/clk.h> |
1e6c9c28 AV |
32 | #include <linux/console.h> |
33 | #include <linux/sysrq.h> | |
34 | #include <linux/tty_flip.h> | |
afefc415 | 35 | #include <linux/platform_device.h> |
5fbe46b6 NF |
36 | #include <linux/of.h> |
37 | #include <linux/of_device.h> | |
354e57f3 | 38 | #include <linux/of_gpio.h> |
a6670615 | 39 | #include <linux/dma-mapping.h> |
93a3ddc2 | 40 | #include <linux/atmel_pdc.h> |
fa3218d8 | 41 | #include <linux/atmel_serial.h> |
e8faff73 | 42 | #include <linux/uaccess.h> |
bcd2360c | 43 | #include <linux/platform_data/atmel.h> |
2e68c22f | 44 | #include <linux/timer.h> |
354e57f3 | 45 | #include <linux/gpio.h> |
e0b0baad RG |
46 | #include <linux/gpio/consumer.h> |
47 | #include <linux/err.h> | |
ab5e4e41 | 48 | #include <linux/irq.h> |
1e6c9c28 AV |
49 | |
50 | #include <asm/io.h> | |
f7512e7c | 51 | #include <asm/ioctls.h> |
1e6c9c28 | 52 | |
a6670615 CC |
53 | #define PDC_BUFFER_SIZE 512 |
54 | /* Revisit: We should calculate this based on the actual port settings */ | |
55 | #define PDC_RX_TIMEOUT (3 * 10) /* 3 bytes */ | |
56 | ||
749c4e60 | 57 | #if defined(CONFIG_SERIAL_ATMEL_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) |
1e6c9c28 AV |
58 | #define SUPPORT_SYSRQ |
59 | #endif | |
60 | ||
61 | #include <linux/serial_core.h> | |
62 | ||
e0b0baad RG |
63 | #include "serial_mctrl_gpio.h" |
64 | ||
e8faff73 CS |
65 | static void atmel_start_rx(struct uart_port *port); |
66 | static void atmel_stop_rx(struct uart_port *port); | |
67 | ||
749c4e60 | 68 | #ifdef CONFIG_SERIAL_ATMEL_TTYAT |
1e6c9c28 AV |
69 | |
70 | /* Use device name ttyAT, major 204 and minor 154-169. This is necessary if we | |
71 | * should coexist with the 8250 driver, such as if we have an external 16C550 | |
72 | * UART. */ | |
7192f92c | 73 | #define SERIAL_ATMEL_MAJOR 204 |
1e6c9c28 | 74 | #define MINOR_START 154 |
7192f92c | 75 | #define ATMEL_DEVICENAME "ttyAT" |
1e6c9c28 AV |
76 | |
77 | #else | |
78 | ||
79 | /* Use device name ttyS, major 4, minor 64-68. This is the usual serial port | |
80 | * name, but it is legally reserved for the 8250 driver. */ | |
7192f92c | 81 | #define SERIAL_ATMEL_MAJOR TTY_MAJOR |
1e6c9c28 | 82 | #define MINOR_START 64 |
7192f92c | 83 | #define ATMEL_DEVICENAME "ttyS" |
1e6c9c28 AV |
84 | |
85 | #endif | |
86 | ||
7192f92c | 87 | #define ATMEL_ISR_PASS_LIMIT 256 |
1e6c9c28 | 88 | |
b843aa21 | 89 | /* UART registers. CR is write-only, hence no GET macro */ |
544fc728 HS |
90 | #define UART_PUT_CR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_CR) |
91 | #define UART_GET_MR(port) __raw_readl((port)->membase + ATMEL_US_MR) | |
92 | #define UART_PUT_MR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_MR) | |
93 | #define UART_PUT_IER(port,v) __raw_writel(v, (port)->membase + ATMEL_US_IER) | |
94 | #define UART_PUT_IDR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_IDR) | |
95 | #define UART_GET_IMR(port) __raw_readl((port)->membase + ATMEL_US_IMR) | |
96 | #define UART_GET_CSR(port) __raw_readl((port)->membase + ATMEL_US_CSR) | |
97 | #define UART_GET_CHAR(port) __raw_readl((port)->membase + ATMEL_US_RHR) | |
98 | #define UART_PUT_CHAR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_THR) | |
99 | #define UART_GET_BRGR(port) __raw_readl((port)->membase + ATMEL_US_BRGR) | |
100 | #define UART_PUT_BRGR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_BRGR) | |
101 | #define UART_PUT_RTOR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_RTOR) | |
e8faff73 | 102 | #define UART_PUT_TTGR(port, v) __raw_writel(v, (port)->membase + ATMEL_US_TTGR) |
055560b0 | 103 | #define UART_GET_IP_NAME(port) __raw_readl((port)->membase + ATMEL_US_NAME) |
731d9cae | 104 | #define UART_GET_IP_VERSION(port) __raw_readl((port)->membase + ATMEL_US_VERSION) |
544fc728 | 105 | |
1e6c9c28 | 106 | /* PDC registers */ |
544fc728 HS |
107 | #define UART_PUT_PTCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_PTCR) |
108 | #define UART_GET_PTSR(port) __raw_readl((port)->membase + ATMEL_PDC_PTSR) | |
109 | ||
110 | #define UART_PUT_RPR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RPR) | |
111 | #define UART_GET_RPR(port) __raw_readl((port)->membase + ATMEL_PDC_RPR) | |
112 | #define UART_PUT_RCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RCR) | |
113 | #define UART_PUT_RNPR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RNPR) | |
114 | #define UART_PUT_RNCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RNCR) | |
115 | ||
116 | #define UART_PUT_TPR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_TPR) | |
117 | #define UART_PUT_TCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_TCR) | |
39d4c922 | 118 | #define UART_GET_TCR(port) __raw_readl((port)->membase + ATMEL_PDC_TCR) |
1e6c9c28 | 119 | |
a6670615 CC |
120 | struct atmel_dma_buffer { |
121 | unsigned char *buf; | |
122 | dma_addr_t dma_addr; | |
123 | unsigned int dma_size; | |
124 | unsigned int ofs; | |
125 | }; | |
126 | ||
1ecc26bd RB |
127 | struct atmel_uart_char { |
128 | u16 status; | |
129 | u16 ch; | |
130 | }; | |
131 | ||
132 | #define ATMEL_SERIAL_RINGSIZE 1024 | |
133 | ||
afefc415 AV |
134 | /* |
135 | * We wrap our port structure around the generic uart_port. | |
136 | */ | |
7192f92c | 137 | struct atmel_uart_port { |
afefc415 AV |
138 | struct uart_port uart; /* uart */ |
139 | struct clk *clk; /* uart clock */ | |
f05596db AS |
140 | int may_wakeup; /* cached value of device_may_wakeup for times we need to disable it */ |
141 | u32 backup_imr; /* IMR saved during suspend */ | |
9e6077bd | 142 | int break_active; /* break being received */ |
1ecc26bd | 143 | |
34df42f5 | 144 | bool use_dma_rx; /* enable DMA receiver */ |
64e22ebe | 145 | bool use_pdc_rx; /* enable PDC receiver */ |
a6670615 CC |
146 | short pdc_rx_idx; /* current PDC RX buffer */ |
147 | struct atmel_dma_buffer pdc_rx[2]; /* PDC receier */ | |
148 | ||
08f738be | 149 | bool use_dma_tx; /* enable DMA transmitter */ |
64e22ebe | 150 | bool use_pdc_tx; /* enable PDC transmitter */ |
a6670615 CC |
151 | struct atmel_dma_buffer pdc_tx; /* PDC transmitter */ |
152 | ||
08f738be | 153 | spinlock_t lock_tx; /* port lock */ |
34df42f5 | 154 | spinlock_t lock_rx; /* port lock */ |
08f738be | 155 | struct dma_chan *chan_tx; |
34df42f5 | 156 | struct dma_chan *chan_rx; |
08f738be | 157 | struct dma_async_tx_descriptor *desc_tx; |
34df42f5 | 158 | struct dma_async_tx_descriptor *desc_rx; |
08f738be | 159 | dma_cookie_t cookie_tx; |
34df42f5 | 160 | dma_cookie_t cookie_rx; |
08f738be | 161 | struct scatterlist sg_tx; |
34df42f5 | 162 | struct scatterlist sg_rx; |
1ecc26bd RB |
163 | struct tasklet_struct tasklet; |
164 | unsigned int irq_status; | |
165 | unsigned int irq_status_prev; | |
166 | ||
167 | struct circ_buf rx_ring; | |
e8faff73 CS |
168 | |
169 | struct serial_rs485 rs485; /* rs485 settings */ | |
e0b0baad | 170 | struct mctrl_gpios *gpios; |
ab5e4e41 | 171 | int gpio_irq[UART_GPIO_MAX]; |
e8faff73 | 172 | unsigned int tx_done_mask; |
ab5e4e41 | 173 | bool ms_irq_enabled; |
055560b0 | 174 | bool is_usart; /* usart or uart */ |
2e68c22f | 175 | struct timer_list uart_timer; /* uart timer */ |
a930e528 ES |
176 | int (*prepare_rx)(struct uart_port *port); |
177 | int (*prepare_tx)(struct uart_port *port); | |
178 | void (*schedule_rx)(struct uart_port *port); | |
179 | void (*schedule_tx)(struct uart_port *port); | |
180 | void (*release_rx)(struct uart_port *port); | |
181 | void (*release_tx)(struct uart_port *port); | |
afefc415 AV |
182 | }; |
183 | ||
7192f92c | 184 | static struct atmel_uart_port atmel_ports[ATMEL_MAX_UART]; |
503bded9 | 185 | static DECLARE_BITMAP(atmel_ports_in_use, ATMEL_MAX_UART); |
afefc415 | 186 | |
1e6c9c28 | 187 | #ifdef SUPPORT_SYSRQ |
7192f92c | 188 | static struct console atmel_console; |
1e6c9c28 AV |
189 | #endif |
190 | ||
5fbe46b6 NF |
191 | #if defined(CONFIG_OF) |
192 | static const struct of_device_id atmel_serial_dt_ids[] = { | |
193 | { .compatible = "atmel,at91rm9200-usart" }, | |
194 | { .compatible = "atmel,at91sam9260-usart" }, | |
195 | { /* sentinel */ } | |
196 | }; | |
197 | ||
198 | MODULE_DEVICE_TABLE(of, atmel_serial_dt_ids); | |
199 | #endif | |
200 | ||
c811ab8c HS |
201 | static inline struct atmel_uart_port * |
202 | to_atmel_uart_port(struct uart_port *uart) | |
203 | { | |
204 | return container_of(uart, struct atmel_uart_port, uart); | |
205 | } | |
206 | ||
a6670615 | 207 | #ifdef CONFIG_SERIAL_ATMEL_PDC |
64e22ebe | 208 | static bool atmel_use_pdc_rx(struct uart_port *port) |
a6670615 | 209 | { |
c811ab8c | 210 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
a6670615 | 211 | |
64e22ebe | 212 | return atmel_port->use_pdc_rx; |
a6670615 CC |
213 | } |
214 | ||
64e22ebe | 215 | static bool atmel_use_pdc_tx(struct uart_port *port) |
a6670615 | 216 | { |
c811ab8c | 217 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
a6670615 | 218 | |
64e22ebe | 219 | return atmel_port->use_pdc_tx; |
a6670615 CC |
220 | } |
221 | #else | |
64e22ebe | 222 | static bool atmel_use_pdc_rx(struct uart_port *port) |
a6670615 CC |
223 | { |
224 | return false; | |
225 | } | |
226 | ||
64e22ebe | 227 | static bool atmel_use_pdc_tx(struct uart_port *port) |
a6670615 CC |
228 | { |
229 | return false; | |
230 | } | |
231 | #endif | |
232 | ||
08f738be ES |
233 | static bool atmel_use_dma_tx(struct uart_port *port) |
234 | { | |
235 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); | |
236 | ||
237 | return atmel_port->use_dma_tx; | |
238 | } | |
239 | ||
34df42f5 ES |
240 | static bool atmel_use_dma_rx(struct uart_port *port) |
241 | { | |
242 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); | |
243 | ||
244 | return atmel_port->use_dma_rx; | |
245 | } | |
246 | ||
e0b0baad RG |
247 | static unsigned int atmel_get_lines_status(struct uart_port *port) |
248 | { | |
249 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); | |
250 | unsigned int status, ret = 0; | |
251 | ||
252 | status = UART_GET_CSR(port); | |
253 | ||
254 | mctrl_gpio_get(atmel_port->gpios, &ret); | |
255 | ||
256 | if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios, | |
257 | UART_GPIO_CTS))) { | |
258 | if (ret & TIOCM_CTS) | |
259 | status &= ~ATMEL_US_CTS; | |
260 | else | |
261 | status |= ATMEL_US_CTS; | |
262 | } | |
263 | ||
264 | if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios, | |
265 | UART_GPIO_DSR))) { | |
266 | if (ret & TIOCM_DSR) | |
267 | status &= ~ATMEL_US_DSR; | |
268 | else | |
269 | status |= ATMEL_US_DSR; | |
270 | } | |
271 | ||
272 | if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios, | |
273 | UART_GPIO_RI))) { | |
274 | if (ret & TIOCM_RI) | |
275 | status &= ~ATMEL_US_RI; | |
276 | else | |
277 | status |= ATMEL_US_RI; | |
278 | } | |
279 | ||
280 | if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios, | |
281 | UART_GPIO_DCD))) { | |
282 | if (ret & TIOCM_CD) | |
283 | status &= ~ATMEL_US_DCD; | |
284 | else | |
285 | status |= ATMEL_US_DCD; | |
286 | } | |
287 | ||
288 | return status; | |
289 | } | |
290 | ||
e8faff73 CS |
291 | /* Enable or disable the rs485 support */ |
292 | void atmel_config_rs485(struct uart_port *port, struct serial_rs485 *rs485conf) | |
293 | { | |
294 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); | |
295 | unsigned int mode; | |
dbf1115d | 296 | unsigned long flags; |
e8faff73 | 297 | |
dbf1115d | 298 | spin_lock_irqsave(&port->lock, flags); |
e8faff73 CS |
299 | |
300 | /* Disable interrupts */ | |
301 | UART_PUT_IDR(port, atmel_port->tx_done_mask); | |
302 | ||
303 | mode = UART_GET_MR(port); | |
304 | ||
305 | /* Resetting serial mode to RS232 (0x0) */ | |
306 | mode &= ~ATMEL_US_USMODE; | |
307 | ||
308 | atmel_port->rs485 = *rs485conf; | |
309 | ||
310 | if (rs485conf->flags & SER_RS485_ENABLED) { | |
311 | dev_dbg(port->dev, "Setting UART to RS485\n"); | |
312 | atmel_port->tx_done_mask = ATMEL_US_TXEMPTY; | |
93f3350c | 313 | if ((rs485conf->delay_rts_after_send) > 0) |
1b633184 | 314 | UART_PUT_TTGR(port, rs485conf->delay_rts_after_send); |
e8faff73 CS |
315 | mode |= ATMEL_US_USMODE_RS485; |
316 | } else { | |
317 | dev_dbg(port->dev, "Setting UART to RS232\n"); | |
64e22ebe | 318 | if (atmel_use_pdc_tx(port)) |
e8faff73 CS |
319 | atmel_port->tx_done_mask = ATMEL_US_ENDTX | |
320 | ATMEL_US_TXBUFE; | |
321 | else | |
322 | atmel_port->tx_done_mask = ATMEL_US_TXRDY; | |
323 | } | |
324 | UART_PUT_MR(port, mode); | |
325 | ||
326 | /* Enable interrupts */ | |
327 | UART_PUT_IER(port, atmel_port->tx_done_mask); | |
328 | ||
dbf1115d | 329 | spin_unlock_irqrestore(&port->lock, flags); |
e8faff73 CS |
330 | |
331 | } | |
332 | ||
1e6c9c28 AV |
333 | /* |
334 | * Return TIOCSER_TEMT when transmitter FIFO and Shift register is empty. | |
335 | */ | |
7192f92c | 336 | static u_int atmel_tx_empty(struct uart_port *port) |
1e6c9c28 | 337 | { |
7192f92c | 338 | return (UART_GET_CSR(port) & ATMEL_US_TXEMPTY) ? TIOCSER_TEMT : 0; |
1e6c9c28 AV |
339 | } |
340 | ||
341 | /* | |
342 | * Set state of the modem control output lines | |
343 | */ | |
7192f92c | 344 | static void atmel_set_mctrl(struct uart_port *port, u_int mctrl) |
1e6c9c28 AV |
345 | { |
346 | unsigned int control = 0; | |
afefc415 | 347 | unsigned int mode; |
e8faff73 | 348 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
1e6c9c28 | 349 | |
1e6c9c28 | 350 | if (mctrl & TIOCM_RTS) |
7192f92c | 351 | control |= ATMEL_US_RTSEN; |
1e6c9c28 | 352 | else |
7192f92c | 353 | control |= ATMEL_US_RTSDIS; |
1e6c9c28 AV |
354 | |
355 | if (mctrl & TIOCM_DTR) | |
7192f92c | 356 | control |= ATMEL_US_DTREN; |
1e6c9c28 | 357 | else |
7192f92c | 358 | control |= ATMEL_US_DTRDIS; |
1e6c9c28 | 359 | |
afefc415 AV |
360 | UART_PUT_CR(port, control); |
361 | ||
e0b0baad RG |
362 | mctrl_gpio_set(atmel_port->gpios, mctrl); |
363 | ||
afefc415 | 364 | /* Local loopback mode? */ |
7192f92c | 365 | mode = UART_GET_MR(port) & ~ATMEL_US_CHMODE; |
afefc415 | 366 | if (mctrl & TIOCM_LOOP) |
7192f92c | 367 | mode |= ATMEL_US_CHMODE_LOC_LOOP; |
afefc415 | 368 | else |
7192f92c | 369 | mode |= ATMEL_US_CHMODE_NORMAL; |
e8faff73 CS |
370 | |
371 | /* Resetting serial mode to RS232 (0x0) */ | |
372 | mode &= ~ATMEL_US_USMODE; | |
373 | ||
374 | if (atmel_port->rs485.flags & SER_RS485_ENABLED) { | |
375 | dev_dbg(port->dev, "Setting UART to RS485\n"); | |
93f3350c | 376 | if ((atmel_port->rs485.delay_rts_after_send) > 0) |
1b633184 CS |
377 | UART_PUT_TTGR(port, |
378 | atmel_port->rs485.delay_rts_after_send); | |
e8faff73 CS |
379 | mode |= ATMEL_US_USMODE_RS485; |
380 | } else { | |
381 | dev_dbg(port->dev, "Setting UART to RS232\n"); | |
382 | } | |
afefc415 | 383 | UART_PUT_MR(port, mode); |
1e6c9c28 AV |
384 | } |
385 | ||
386 | /* | |
387 | * Get state of the modem control input lines | |
388 | */ | |
7192f92c | 389 | static u_int atmel_get_mctrl(struct uart_port *port) |
1e6c9c28 | 390 | { |
e0b0baad RG |
391 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
392 | unsigned int ret = 0, status; | |
1e6c9c28 AV |
393 | |
394 | status = UART_GET_CSR(port); | |
395 | ||
396 | /* | |
397 | * The control signals are active low. | |
398 | */ | |
7192f92c | 399 | if (!(status & ATMEL_US_DCD)) |
1e6c9c28 | 400 | ret |= TIOCM_CD; |
7192f92c | 401 | if (!(status & ATMEL_US_CTS)) |
1e6c9c28 | 402 | ret |= TIOCM_CTS; |
7192f92c | 403 | if (!(status & ATMEL_US_DSR)) |
1e6c9c28 | 404 | ret |= TIOCM_DSR; |
7192f92c | 405 | if (!(status & ATMEL_US_RI)) |
1e6c9c28 AV |
406 | ret |= TIOCM_RI; |
407 | ||
e0b0baad | 408 | return mctrl_gpio_get(atmel_port->gpios, &ret); |
1e6c9c28 AV |
409 | } |
410 | ||
411 | /* | |
412 | * Stop transmitting. | |
413 | */ | |
7192f92c | 414 | static void atmel_stop_tx(struct uart_port *port) |
1e6c9c28 | 415 | { |
e8faff73 CS |
416 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
417 | ||
64e22ebe | 418 | if (atmel_use_pdc_tx(port)) { |
a6670615 CC |
419 | /* disable PDC transmit */ |
420 | UART_PUT_PTCR(port, ATMEL_PDC_TXTDIS); | |
e8faff73 CS |
421 | } |
422 | /* Disable interrupts */ | |
423 | UART_PUT_IDR(port, atmel_port->tx_done_mask); | |
424 | ||
83cac9f3 BR |
425 | if ((atmel_port->rs485.flags & SER_RS485_ENABLED) && |
426 | !(atmel_port->rs485.flags & SER_RS485_RX_DURING_TX)) | |
e8faff73 | 427 | atmel_start_rx(port); |
1e6c9c28 AV |
428 | } |
429 | ||
430 | /* | |
431 | * Start transmitting. | |
432 | */ | |
7192f92c | 433 | static void atmel_start_tx(struct uart_port *port) |
1e6c9c28 | 434 | { |
e8faff73 CS |
435 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
436 | ||
64e22ebe | 437 | if (atmel_use_pdc_tx(port)) { |
a6670615 CC |
438 | if (UART_GET_PTSR(port) & ATMEL_PDC_TXTEN) |
439 | /* The transmitter is already running. Yes, we | |
440 | really need this.*/ | |
441 | return; | |
442 | ||
83cac9f3 BR |
443 | if ((atmel_port->rs485.flags & SER_RS485_ENABLED) && |
444 | !(atmel_port->rs485.flags & SER_RS485_RX_DURING_TX)) | |
e8faff73 CS |
445 | atmel_stop_rx(port); |
446 | ||
a6670615 CC |
447 | /* re-enable PDC transmit */ |
448 | UART_PUT_PTCR(port, ATMEL_PDC_TXTEN); | |
e8faff73 CS |
449 | } |
450 | /* Enable interrupts */ | |
451 | UART_PUT_IER(port, atmel_port->tx_done_mask); | |
452 | } | |
453 | ||
454 | /* | |
455 | * start receiving - port is in process of being opened. | |
456 | */ | |
457 | static void atmel_start_rx(struct uart_port *port) | |
458 | { | |
459 | UART_PUT_CR(port, ATMEL_US_RSTSTA); /* reset status and receiver */ | |
460 | ||
57c36868 SG |
461 | UART_PUT_CR(port, ATMEL_US_RXEN); |
462 | ||
64e22ebe | 463 | if (atmel_use_pdc_rx(port)) { |
e8faff73 CS |
464 | /* enable PDC controller */ |
465 | UART_PUT_IER(port, ATMEL_US_ENDRX | ATMEL_US_TIMEOUT | | |
466 | port->read_status_mask); | |
467 | UART_PUT_PTCR(port, ATMEL_PDC_RXTEN); | |
468 | } else { | |
469 | UART_PUT_IER(port, ATMEL_US_RXRDY); | |
470 | } | |
1e6c9c28 AV |
471 | } |
472 | ||
473 | /* | |
474 | * Stop receiving - port is in process of being closed. | |
475 | */ | |
7192f92c | 476 | static void atmel_stop_rx(struct uart_port *port) |
1e6c9c28 | 477 | { |
57c36868 SG |
478 | UART_PUT_CR(port, ATMEL_US_RXDIS); |
479 | ||
64e22ebe | 480 | if (atmel_use_pdc_rx(port)) { |
a6670615 CC |
481 | /* disable PDC receive */ |
482 | UART_PUT_PTCR(port, ATMEL_PDC_RXTDIS); | |
e8faff73 CS |
483 | UART_PUT_IDR(port, ATMEL_US_ENDRX | ATMEL_US_TIMEOUT | |
484 | port->read_status_mask); | |
485 | } else { | |
a6670615 | 486 | UART_PUT_IDR(port, ATMEL_US_RXRDY); |
e8faff73 | 487 | } |
1e6c9c28 AV |
488 | } |
489 | ||
490 | /* | |
491 | * Enable modem status interrupts | |
492 | */ | |
7192f92c | 493 | static void atmel_enable_ms(struct uart_port *port) |
1e6c9c28 | 494 | { |
ab5e4e41 RG |
495 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
496 | uint32_t ier = 0; | |
497 | ||
498 | /* | |
499 | * Interrupt should not be enabled twice | |
500 | */ | |
501 | if (atmel_port->ms_irq_enabled) | |
502 | return; | |
503 | ||
504 | atmel_port->ms_irq_enabled = true; | |
505 | ||
506 | if (atmel_port->gpio_irq[UART_GPIO_CTS] >= 0) | |
507 | enable_irq(atmel_port->gpio_irq[UART_GPIO_CTS]); | |
508 | else | |
509 | ier |= ATMEL_US_CTSIC; | |
510 | ||
511 | if (atmel_port->gpio_irq[UART_GPIO_DSR] >= 0) | |
512 | enable_irq(atmel_port->gpio_irq[UART_GPIO_DSR]); | |
513 | else | |
514 | ier |= ATMEL_US_DSRIC; | |
515 | ||
516 | if (atmel_port->gpio_irq[UART_GPIO_RI] >= 0) | |
517 | enable_irq(atmel_port->gpio_irq[UART_GPIO_RI]); | |
518 | else | |
519 | ier |= ATMEL_US_RIIC; | |
520 | ||
521 | if (atmel_port->gpio_irq[UART_GPIO_DCD] >= 0) | |
522 | enable_irq(atmel_port->gpio_irq[UART_GPIO_DCD]); | |
523 | else | |
524 | ier |= ATMEL_US_DCDIC; | |
525 | ||
526 | UART_PUT_IER(port, ier); | |
1e6c9c28 AV |
527 | } |
528 | ||
529 | /* | |
530 | * Control the transmission of a break signal | |
531 | */ | |
7192f92c | 532 | static void atmel_break_ctl(struct uart_port *port, int break_state) |
1e6c9c28 AV |
533 | { |
534 | if (break_state != 0) | |
7192f92c | 535 | UART_PUT_CR(port, ATMEL_US_STTBRK); /* start break */ |
1e6c9c28 | 536 | else |
7192f92c | 537 | UART_PUT_CR(port, ATMEL_US_STPBRK); /* stop break */ |
1e6c9c28 AV |
538 | } |
539 | ||
1ecc26bd RB |
540 | /* |
541 | * Stores the incoming character in the ring buffer | |
542 | */ | |
543 | static void | |
544 | atmel_buffer_rx_char(struct uart_port *port, unsigned int status, | |
545 | unsigned int ch) | |
546 | { | |
c811ab8c | 547 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
1ecc26bd RB |
548 | struct circ_buf *ring = &atmel_port->rx_ring; |
549 | struct atmel_uart_char *c; | |
550 | ||
551 | if (!CIRC_SPACE(ring->head, ring->tail, ATMEL_SERIAL_RINGSIZE)) | |
552 | /* Buffer overflow, ignore char */ | |
553 | return; | |
554 | ||
555 | c = &((struct atmel_uart_char *)ring->buf)[ring->head]; | |
556 | c->status = status; | |
557 | c->ch = ch; | |
558 | ||
559 | /* Make sure the character is stored before we update head. */ | |
560 | smp_wmb(); | |
561 | ||
562 | ring->head = (ring->head + 1) & (ATMEL_SERIAL_RINGSIZE - 1); | |
563 | } | |
564 | ||
a6670615 CC |
565 | /* |
566 | * Deal with parity, framing and overrun errors. | |
567 | */ | |
568 | static void atmel_pdc_rxerr(struct uart_port *port, unsigned int status) | |
569 | { | |
570 | /* clear error */ | |
571 | UART_PUT_CR(port, ATMEL_US_RSTSTA); | |
572 | ||
573 | if (status & ATMEL_US_RXBRK) { | |
574 | /* ignore side-effect */ | |
575 | status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME); | |
576 | port->icount.brk++; | |
577 | } | |
578 | if (status & ATMEL_US_PARE) | |
579 | port->icount.parity++; | |
580 | if (status & ATMEL_US_FRAME) | |
581 | port->icount.frame++; | |
582 | if (status & ATMEL_US_OVRE) | |
583 | port->icount.overrun++; | |
584 | } | |
585 | ||
1e6c9c28 AV |
586 | /* |
587 | * Characters received (called from interrupt handler) | |
588 | */ | |
7d12e780 | 589 | static void atmel_rx_chars(struct uart_port *port) |
1e6c9c28 | 590 | { |
c811ab8c | 591 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
1ecc26bd | 592 | unsigned int status, ch; |
1e6c9c28 | 593 | |
afefc415 | 594 | status = UART_GET_CSR(port); |
7192f92c | 595 | while (status & ATMEL_US_RXRDY) { |
1e6c9c28 AV |
596 | ch = UART_GET_CHAR(port); |
597 | ||
1e6c9c28 AV |
598 | /* |
599 | * note that the error handling code is | |
600 | * out of the main execution path | |
601 | */ | |
9e6077bd HS |
602 | if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME |
603 | | ATMEL_US_OVRE | ATMEL_US_RXBRK) | |
604 | || atmel_port->break_active)) { | |
1ecc26bd | 605 | |
b843aa21 RB |
606 | /* clear error */ |
607 | UART_PUT_CR(port, ATMEL_US_RSTSTA); | |
1ecc26bd | 608 | |
9e6077bd HS |
609 | if (status & ATMEL_US_RXBRK |
610 | && !atmel_port->break_active) { | |
9e6077bd HS |
611 | atmel_port->break_active = 1; |
612 | UART_PUT_IER(port, ATMEL_US_RXBRK); | |
9e6077bd HS |
613 | } else { |
614 | /* | |
615 | * This is either the end-of-break | |
616 | * condition or we've received at | |
617 | * least one character without RXBRK | |
618 | * being set. In both cases, the next | |
619 | * RXBRK will indicate start-of-break. | |
620 | */ | |
621 | UART_PUT_IDR(port, ATMEL_US_RXBRK); | |
622 | status &= ~ATMEL_US_RXBRK; | |
623 | atmel_port->break_active = 0; | |
afefc415 | 624 | } |
1e6c9c28 AV |
625 | } |
626 | ||
1ecc26bd | 627 | atmel_buffer_rx_char(port, status, ch); |
afefc415 | 628 | status = UART_GET_CSR(port); |
1e6c9c28 AV |
629 | } |
630 | ||
1ecc26bd | 631 | tasklet_schedule(&atmel_port->tasklet); |
1e6c9c28 AV |
632 | } |
633 | ||
634 | /* | |
1ecc26bd RB |
635 | * Transmit characters (called from tasklet with TXRDY interrupt |
636 | * disabled) | |
1e6c9c28 | 637 | */ |
7192f92c | 638 | static void atmel_tx_chars(struct uart_port *port) |
1e6c9c28 | 639 | { |
ebd2c8f6 | 640 | struct circ_buf *xmit = &port->state->xmit; |
e8faff73 | 641 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
1e6c9c28 | 642 | |
e8faff73 | 643 | if (port->x_char && UART_GET_CSR(port) & atmel_port->tx_done_mask) { |
1e6c9c28 AV |
644 | UART_PUT_CHAR(port, port->x_char); |
645 | port->icount.tx++; | |
646 | port->x_char = 0; | |
1e6c9c28 | 647 | } |
1ecc26bd | 648 | if (uart_circ_empty(xmit) || uart_tx_stopped(port)) |
1e6c9c28 | 649 | return; |
1e6c9c28 | 650 | |
e8faff73 | 651 | while (UART_GET_CSR(port) & atmel_port->tx_done_mask) { |
1e6c9c28 AV |
652 | UART_PUT_CHAR(port, xmit->buf[xmit->tail]); |
653 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); | |
654 | port->icount.tx++; | |
655 | if (uart_circ_empty(xmit)) | |
656 | break; | |
657 | } | |
658 | ||
659 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
660 | uart_write_wakeup(port); | |
661 | ||
1ecc26bd | 662 | if (!uart_circ_empty(xmit)) |
e8faff73 CS |
663 | /* Enable interrupts */ |
664 | UART_PUT_IER(port, atmel_port->tx_done_mask); | |
1e6c9c28 AV |
665 | } |
666 | ||
08f738be ES |
667 | static void atmel_complete_tx_dma(void *arg) |
668 | { | |
669 | struct atmel_uart_port *atmel_port = arg; | |
670 | struct uart_port *port = &atmel_port->uart; | |
671 | struct circ_buf *xmit = &port->state->xmit; | |
672 | struct dma_chan *chan = atmel_port->chan_tx; | |
673 | unsigned long flags; | |
674 | ||
675 | spin_lock_irqsave(&port->lock, flags); | |
676 | ||
677 | if (chan) | |
678 | dmaengine_terminate_all(chan); | |
679 | xmit->tail += sg_dma_len(&atmel_port->sg_tx); | |
680 | xmit->tail &= UART_XMIT_SIZE - 1; | |
681 | ||
682 | port->icount.tx += sg_dma_len(&atmel_port->sg_tx); | |
683 | ||
684 | spin_lock_irq(&atmel_port->lock_tx); | |
685 | async_tx_ack(atmel_port->desc_tx); | |
686 | atmel_port->cookie_tx = -EINVAL; | |
687 | atmel_port->desc_tx = NULL; | |
688 | spin_unlock_irq(&atmel_port->lock_tx); | |
689 | ||
690 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
691 | uart_write_wakeup(port); | |
692 | ||
693 | /* Do we really need this? */ | |
694 | if (!uart_circ_empty(xmit)) | |
695 | tasklet_schedule(&atmel_port->tasklet); | |
696 | ||
697 | spin_unlock_irqrestore(&port->lock, flags); | |
698 | } | |
699 | ||
700 | static void atmel_release_tx_dma(struct uart_port *port) | |
701 | { | |
702 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); | |
703 | struct dma_chan *chan = atmel_port->chan_tx; | |
704 | ||
705 | if (chan) { | |
706 | dmaengine_terminate_all(chan); | |
707 | dma_release_channel(chan); | |
708 | dma_unmap_sg(port->dev, &atmel_port->sg_tx, 1, | |
48479148 | 709 | DMA_TO_DEVICE); |
08f738be ES |
710 | } |
711 | ||
712 | atmel_port->desc_tx = NULL; | |
713 | atmel_port->chan_tx = NULL; | |
714 | atmel_port->cookie_tx = -EINVAL; | |
715 | } | |
716 | ||
717 | /* | |
718 | * Called from tasklet with TXRDY interrupt is disabled. | |
719 | */ | |
720 | static void atmel_tx_dma(struct uart_port *port) | |
721 | { | |
722 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); | |
723 | struct circ_buf *xmit = &port->state->xmit; | |
724 | struct dma_chan *chan = atmel_port->chan_tx; | |
725 | struct dma_async_tx_descriptor *desc; | |
726 | struct scatterlist *sg = &atmel_port->sg_tx; | |
727 | ||
728 | /* Make sure we have an idle channel */ | |
729 | if (atmel_port->desc_tx != NULL) | |
730 | return; | |
731 | ||
732 | if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) { | |
733 | /* | |
734 | * DMA is idle now. | |
735 | * Port xmit buffer is already mapped, | |
736 | * and it is one page... Just adjust | |
737 | * offsets and lengths. Since it is a circular buffer, | |
738 | * we have to transmit till the end, and then the rest. | |
739 | * Take the port lock to get a | |
740 | * consistent xmit buffer state. | |
741 | */ | |
742 | sg->offset = xmit->tail & (UART_XMIT_SIZE - 1); | |
743 | sg_dma_address(sg) = (sg_dma_address(sg) & | |
744 | ~(UART_XMIT_SIZE - 1)) | |
745 | + sg->offset; | |
746 | sg_dma_len(sg) = CIRC_CNT_TO_END(xmit->head, | |
747 | xmit->tail, | |
748 | UART_XMIT_SIZE); | |
749 | BUG_ON(!sg_dma_len(sg)); | |
750 | ||
751 | desc = dmaengine_prep_slave_sg(chan, | |
752 | sg, | |
753 | 1, | |
754 | DMA_MEM_TO_DEV, | |
755 | DMA_PREP_INTERRUPT | | |
756 | DMA_CTRL_ACK); | |
757 | if (!desc) { | |
758 | dev_err(port->dev, "Failed to send via dma!\n"); | |
759 | return; | |
760 | } | |
761 | ||
762 | dma_sync_sg_for_device(port->dev, sg, 1, DMA_MEM_TO_DEV); | |
763 | ||
764 | atmel_port->desc_tx = desc; | |
765 | desc->callback = atmel_complete_tx_dma; | |
766 | desc->callback_param = atmel_port; | |
767 | atmel_port->cookie_tx = dmaengine_submit(desc); | |
768 | ||
769 | } else { | |
770 | if (atmel_port->rs485.flags & SER_RS485_ENABLED) { | |
771 | /* DMA done, stop TX, start RX for RS485 */ | |
772 | atmel_start_rx(port); | |
773 | } | |
774 | } | |
775 | ||
776 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
777 | uart_write_wakeup(port); | |
778 | } | |
779 | ||
780 | static int atmel_prepare_tx_dma(struct uart_port *port) | |
781 | { | |
782 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); | |
783 | dma_cap_mask_t mask; | |
784 | struct dma_slave_config config; | |
785 | int ret, nent; | |
786 | ||
787 | dma_cap_zero(mask); | |
788 | dma_cap_set(DMA_SLAVE, mask); | |
789 | ||
790 | atmel_port->chan_tx = dma_request_slave_channel(port->dev, "tx"); | |
791 | if (atmel_port->chan_tx == NULL) | |
792 | goto chan_err; | |
793 | dev_info(port->dev, "using %s for tx DMA transfers\n", | |
794 | dma_chan_name(atmel_port->chan_tx)); | |
795 | ||
796 | spin_lock_init(&atmel_port->lock_tx); | |
797 | sg_init_table(&atmel_port->sg_tx, 1); | |
798 | /* UART circular tx buffer is an aligned page. */ | |
799 | BUG_ON((int)port->state->xmit.buf & ~PAGE_MASK); | |
800 | sg_set_page(&atmel_port->sg_tx, | |
801 | virt_to_page(port->state->xmit.buf), | |
802 | UART_XMIT_SIZE, | |
803 | (int)port->state->xmit.buf & ~PAGE_MASK); | |
804 | nent = dma_map_sg(port->dev, | |
805 | &atmel_port->sg_tx, | |
806 | 1, | |
48479148 | 807 | DMA_TO_DEVICE); |
08f738be ES |
808 | |
809 | if (!nent) { | |
810 | dev_dbg(port->dev, "need to release resource of dma\n"); | |
811 | goto chan_err; | |
812 | } else { | |
813 | dev_dbg(port->dev, "%s: mapped %d@%p to %x\n", __func__, | |
814 | sg_dma_len(&atmel_port->sg_tx), | |
815 | port->state->xmit.buf, | |
816 | sg_dma_address(&atmel_port->sg_tx)); | |
817 | } | |
818 | ||
819 | /* Configure the slave DMA */ | |
820 | memset(&config, 0, sizeof(config)); | |
821 | config.direction = DMA_MEM_TO_DEV; | |
822 | config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; | |
823 | config.dst_addr = port->mapbase + ATMEL_US_THR; | |
824 | ||
825 | ret = dmaengine_device_control(atmel_port->chan_tx, | |
826 | DMA_SLAVE_CONFIG, | |
827 | (unsigned long)&config); | |
828 | if (ret) { | |
829 | dev_err(port->dev, "DMA tx slave configuration failed\n"); | |
830 | goto chan_err; | |
831 | } | |
832 | ||
833 | return 0; | |
834 | ||
835 | chan_err: | |
836 | dev_err(port->dev, "TX channel not available, switch to pio\n"); | |
837 | atmel_port->use_dma_tx = 0; | |
838 | if (atmel_port->chan_tx) | |
839 | atmel_release_tx_dma(port); | |
840 | return -EINVAL; | |
841 | } | |
842 | ||
34df42f5 ES |
843 | static void atmel_flip_buffer_rx_dma(struct uart_port *port, |
844 | char *buf, size_t count) | |
845 | { | |
846 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); | |
847 | struct tty_port *tport = &port->state->port; | |
848 | ||
849 | dma_sync_sg_for_cpu(port->dev, | |
850 | &atmel_port->sg_rx, | |
851 | 1, | |
852 | DMA_DEV_TO_MEM); | |
853 | ||
854 | tty_insert_flip_string(tport, buf, count); | |
855 | ||
856 | dma_sync_sg_for_device(port->dev, | |
857 | &atmel_port->sg_rx, | |
858 | 1, | |
859 | DMA_DEV_TO_MEM); | |
860 | /* | |
861 | * Drop the lock here since it might end up calling | |
862 | * uart_start(), which takes the lock. | |
863 | */ | |
864 | spin_unlock(&port->lock); | |
865 | tty_flip_buffer_push(tport); | |
866 | spin_lock(&port->lock); | |
867 | } | |
868 | ||
869 | static void atmel_complete_rx_dma(void *arg) | |
870 | { | |
871 | struct uart_port *port = arg; | |
872 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); | |
873 | ||
874 | tasklet_schedule(&atmel_port->tasklet); | |
875 | } | |
876 | ||
877 | static void atmel_release_rx_dma(struct uart_port *port) | |
878 | { | |
879 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); | |
880 | struct dma_chan *chan = atmel_port->chan_rx; | |
881 | ||
882 | if (chan) { | |
883 | dmaengine_terminate_all(chan); | |
884 | dma_release_channel(chan); | |
885 | dma_unmap_sg(port->dev, &atmel_port->sg_rx, 1, | |
48479148 | 886 | DMA_FROM_DEVICE); |
34df42f5 ES |
887 | } |
888 | ||
889 | atmel_port->desc_rx = NULL; | |
890 | atmel_port->chan_rx = NULL; | |
891 | atmel_port->cookie_rx = -EINVAL; | |
892 | } | |
893 | ||
894 | static void atmel_rx_from_dma(struct uart_port *port) | |
895 | { | |
896 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); | |
897 | struct circ_buf *ring = &atmel_port->rx_ring; | |
898 | struct dma_chan *chan = atmel_port->chan_rx; | |
899 | struct dma_tx_state state; | |
900 | enum dma_status dmastat; | |
901 | size_t pending, count; | |
902 | ||
903 | ||
904 | /* Reset the UART timeout early so that we don't miss one */ | |
905 | UART_PUT_CR(port, ATMEL_US_STTTO); | |
906 | dmastat = dmaengine_tx_status(chan, | |
907 | atmel_port->cookie_rx, | |
908 | &state); | |
909 | /* Restart a new tasklet if DMA status is error */ | |
910 | if (dmastat == DMA_ERROR) { | |
911 | dev_dbg(port->dev, "Get residue error, restart tasklet\n"); | |
912 | UART_PUT_IER(port, ATMEL_US_TIMEOUT); | |
913 | tasklet_schedule(&atmel_port->tasklet); | |
914 | return; | |
915 | } | |
916 | /* current transfer size should no larger than dma buffer */ | |
917 | pending = sg_dma_len(&atmel_port->sg_rx) - state.residue; | |
918 | BUG_ON(pending > sg_dma_len(&atmel_port->sg_rx)); | |
919 | ||
920 | /* | |
921 | * This will take the chars we have so far, | |
922 | * ring->head will record the transfer size, only new bytes come | |
923 | * will insert into the framework. | |
924 | */ | |
925 | if (pending > ring->head) { | |
926 | count = pending - ring->head; | |
927 | ||
928 | atmel_flip_buffer_rx_dma(port, ring->buf + ring->head, count); | |
929 | ||
930 | ring->head += count; | |
931 | if (ring->head == sg_dma_len(&atmel_port->sg_rx)) | |
932 | ring->head = 0; | |
933 | ||
934 | port->icount.rx += count; | |
935 | } | |
936 | ||
937 | UART_PUT_IER(port, ATMEL_US_TIMEOUT); | |
938 | } | |
939 | ||
940 | static int atmel_prepare_rx_dma(struct uart_port *port) | |
941 | { | |
942 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); | |
943 | struct dma_async_tx_descriptor *desc; | |
944 | dma_cap_mask_t mask; | |
945 | struct dma_slave_config config; | |
946 | struct circ_buf *ring; | |
947 | int ret, nent; | |
948 | ||
949 | ring = &atmel_port->rx_ring; | |
950 | ||
951 | dma_cap_zero(mask); | |
952 | dma_cap_set(DMA_CYCLIC, mask); | |
953 | ||
954 | atmel_port->chan_rx = dma_request_slave_channel(port->dev, "rx"); | |
955 | if (atmel_port->chan_rx == NULL) | |
956 | goto chan_err; | |
957 | dev_info(port->dev, "using %s for rx DMA transfers\n", | |
958 | dma_chan_name(atmel_port->chan_rx)); | |
959 | ||
960 | spin_lock_init(&atmel_port->lock_rx); | |
961 | sg_init_table(&atmel_port->sg_rx, 1); | |
962 | /* UART circular rx buffer is an aligned page. */ | |
963 | BUG_ON((int)port->state->xmit.buf & ~PAGE_MASK); | |
964 | sg_set_page(&atmel_port->sg_rx, | |
965 | virt_to_page(ring->buf), | |
966 | ATMEL_SERIAL_RINGSIZE, | |
967 | (int)ring->buf & ~PAGE_MASK); | |
968 | nent = dma_map_sg(port->dev, | |
969 | &atmel_port->sg_rx, | |
970 | 1, | |
48479148 | 971 | DMA_FROM_DEVICE); |
34df42f5 ES |
972 | |
973 | if (!nent) { | |
974 | dev_dbg(port->dev, "need to release resource of dma\n"); | |
975 | goto chan_err; | |
976 | } else { | |
977 | dev_dbg(port->dev, "%s: mapped %d@%p to %x\n", __func__, | |
978 | sg_dma_len(&atmel_port->sg_rx), | |
979 | ring->buf, | |
980 | sg_dma_address(&atmel_port->sg_rx)); | |
981 | } | |
982 | ||
983 | /* Configure the slave DMA */ | |
984 | memset(&config, 0, sizeof(config)); | |
985 | config.direction = DMA_DEV_TO_MEM; | |
986 | config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; | |
987 | config.src_addr = port->mapbase + ATMEL_US_RHR; | |
988 | ||
989 | ret = dmaengine_device_control(atmel_port->chan_rx, | |
990 | DMA_SLAVE_CONFIG, | |
991 | (unsigned long)&config); | |
992 | if (ret) { | |
993 | dev_err(port->dev, "DMA rx slave configuration failed\n"); | |
994 | goto chan_err; | |
995 | } | |
996 | /* | |
997 | * Prepare a cyclic dma transfer, assign 2 descriptors, | |
998 | * each one is half ring buffer size | |
999 | */ | |
1000 | desc = dmaengine_prep_dma_cyclic(atmel_port->chan_rx, | |
1001 | sg_dma_address(&atmel_port->sg_rx), | |
1002 | sg_dma_len(&atmel_port->sg_rx), | |
1003 | sg_dma_len(&atmel_port->sg_rx)/2, | |
1004 | DMA_DEV_TO_MEM, | |
1005 | DMA_PREP_INTERRUPT); | |
1006 | desc->callback = atmel_complete_rx_dma; | |
1007 | desc->callback_param = port; | |
1008 | atmel_port->desc_rx = desc; | |
1009 | atmel_port->cookie_rx = dmaengine_submit(desc); | |
1010 | ||
1011 | return 0; | |
1012 | ||
1013 | chan_err: | |
1014 | dev_err(port->dev, "RX channel not available, switch to pio\n"); | |
1015 | atmel_port->use_dma_rx = 0; | |
1016 | if (atmel_port->chan_rx) | |
1017 | atmel_release_rx_dma(port); | |
1018 | return -EINVAL; | |
1019 | } | |
1020 | ||
2e68c22f ES |
1021 | static void atmel_uart_timer_callback(unsigned long data) |
1022 | { | |
1023 | struct uart_port *port = (void *)data; | |
1024 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); | |
1025 | ||
1026 | tasklet_schedule(&atmel_port->tasklet); | |
1027 | mod_timer(&atmel_port->uart_timer, jiffies + uart_poll_timeout(port)); | |
1028 | } | |
1029 | ||
b843aa21 RB |
1030 | /* |
1031 | * receive interrupt handler. | |
1032 | */ | |
1033 | static void | |
1034 | atmel_handle_receive(struct uart_port *port, unsigned int pending) | |
1035 | { | |
c811ab8c | 1036 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
b843aa21 | 1037 | |
64e22ebe | 1038 | if (atmel_use_pdc_rx(port)) { |
a6670615 CC |
1039 | /* |
1040 | * PDC receive. Just schedule the tasklet and let it | |
1041 | * figure out the details. | |
1042 | * | |
1043 | * TODO: We're not handling error flags correctly at | |
1044 | * the moment. | |
1045 | */ | |
1046 | if (pending & (ATMEL_US_ENDRX | ATMEL_US_TIMEOUT)) { | |
1047 | UART_PUT_IDR(port, (ATMEL_US_ENDRX | |
1048 | | ATMEL_US_TIMEOUT)); | |
1049 | tasklet_schedule(&atmel_port->tasklet); | |
1050 | } | |
1051 | ||
1052 | if (pending & (ATMEL_US_RXBRK | ATMEL_US_OVRE | | |
1053 | ATMEL_US_FRAME | ATMEL_US_PARE)) | |
1054 | atmel_pdc_rxerr(port, pending); | |
1055 | } | |
1056 | ||
34df42f5 ES |
1057 | if (atmel_use_dma_rx(port)) { |
1058 | if (pending & ATMEL_US_TIMEOUT) { | |
1059 | UART_PUT_IDR(port, ATMEL_US_TIMEOUT); | |
1060 | tasklet_schedule(&atmel_port->tasklet); | |
1061 | } | |
1062 | } | |
1063 | ||
b843aa21 RB |
1064 | /* Interrupt receive */ |
1065 | if (pending & ATMEL_US_RXRDY) | |
1066 | atmel_rx_chars(port); | |
1067 | else if (pending & ATMEL_US_RXBRK) { | |
1068 | /* | |
1069 | * End of break detected. If it came along with a | |
1070 | * character, atmel_rx_chars will handle it. | |
1071 | */ | |
1072 | UART_PUT_CR(port, ATMEL_US_RSTSTA); | |
1073 | UART_PUT_IDR(port, ATMEL_US_RXBRK); | |
1074 | atmel_port->break_active = 0; | |
1075 | } | |
1076 | } | |
1077 | ||
1078 | /* | |
1ecc26bd | 1079 | * transmit interrupt handler. (Transmit is IRQF_NODELAY safe) |
b843aa21 RB |
1080 | */ |
1081 | static void | |
1082 | atmel_handle_transmit(struct uart_port *port, unsigned int pending) | |
1083 | { | |
c811ab8c | 1084 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
1ecc26bd | 1085 | |
e8faff73 CS |
1086 | if (pending & atmel_port->tx_done_mask) { |
1087 | /* Either PDC or interrupt transmission */ | |
1088 | UART_PUT_IDR(port, atmel_port->tx_done_mask); | |
1089 | tasklet_schedule(&atmel_port->tasklet); | |
1ecc26bd | 1090 | } |
b843aa21 RB |
1091 | } |
1092 | ||
1093 | /* | |
1094 | * status flags interrupt handler. | |
1095 | */ | |
1096 | static void | |
1097 | atmel_handle_status(struct uart_port *port, unsigned int pending, | |
1098 | unsigned int status) | |
1099 | { | |
c811ab8c | 1100 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
1ecc26bd | 1101 | |
b843aa21 | 1102 | if (pending & (ATMEL_US_RIIC | ATMEL_US_DSRIC | ATMEL_US_DCDIC |
1ecc26bd RB |
1103 | | ATMEL_US_CTSIC)) { |
1104 | atmel_port->irq_status = status; | |
1105 | tasklet_schedule(&atmel_port->tasklet); | |
1106 | } | |
b843aa21 RB |
1107 | } |
1108 | ||
1e6c9c28 AV |
1109 | /* |
1110 | * Interrupt handler | |
1111 | */ | |
7d12e780 | 1112 | static irqreturn_t atmel_interrupt(int irq, void *dev_id) |
1e6c9c28 AV |
1113 | { |
1114 | struct uart_port *port = dev_id; | |
ab5e4e41 | 1115 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
1e6c9c28 | 1116 | unsigned int status, pending, pass_counter = 0; |
ab5e4e41 | 1117 | bool gpio_handled = false; |
1e6c9c28 | 1118 | |
a6670615 | 1119 | do { |
e0b0baad | 1120 | status = atmel_get_lines_status(port); |
a6670615 | 1121 | pending = status & UART_GET_IMR(port); |
ab5e4e41 RG |
1122 | if (!gpio_handled) { |
1123 | /* | |
1124 | * Dealing with GPIO interrupt | |
1125 | */ | |
1126 | if (irq == atmel_port->gpio_irq[UART_GPIO_CTS]) | |
1127 | pending |= ATMEL_US_CTSIC; | |
1128 | ||
1129 | if (irq == atmel_port->gpio_irq[UART_GPIO_DSR]) | |
1130 | pending |= ATMEL_US_DSRIC; | |
1131 | ||
1132 | if (irq == atmel_port->gpio_irq[UART_GPIO_RI]) | |
1133 | pending |= ATMEL_US_RIIC; | |
1134 | ||
1135 | if (irq == atmel_port->gpio_irq[UART_GPIO_DCD]) | |
1136 | pending |= ATMEL_US_DCDIC; | |
1137 | ||
1138 | gpio_handled = true; | |
1139 | } | |
a6670615 CC |
1140 | if (!pending) |
1141 | break; | |
1142 | ||
b843aa21 RB |
1143 | atmel_handle_receive(port, pending); |
1144 | atmel_handle_status(port, pending, status); | |
1145 | atmel_handle_transmit(port, pending); | |
a6670615 | 1146 | } while (pass_counter++ < ATMEL_ISR_PASS_LIMIT); |
afefc415 | 1147 | |
0400b697 | 1148 | return pass_counter ? IRQ_HANDLED : IRQ_NONE; |
a6670615 | 1149 | } |
1e6c9c28 | 1150 | |
a930e528 ES |
1151 | static void atmel_release_tx_pdc(struct uart_port *port) |
1152 | { | |
1153 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); | |
1154 | struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx; | |
1155 | ||
1156 | dma_unmap_single(port->dev, | |
1157 | pdc->dma_addr, | |
1158 | pdc->dma_size, | |
1159 | DMA_TO_DEVICE); | |
1160 | } | |
1161 | ||
a6670615 CC |
1162 | /* |
1163 | * Called from tasklet with ENDTX and TXBUFE interrupts disabled. | |
1164 | */ | |
64e22ebe | 1165 | static void atmel_tx_pdc(struct uart_port *port) |
a6670615 | 1166 | { |
c811ab8c | 1167 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
ebd2c8f6 | 1168 | struct circ_buf *xmit = &port->state->xmit; |
a6670615 CC |
1169 | struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx; |
1170 | int count; | |
1171 | ||
ba0657ff MT |
1172 | /* nothing left to transmit? */ |
1173 | if (UART_GET_TCR(port)) | |
1174 | return; | |
1175 | ||
a6670615 CC |
1176 | xmit->tail += pdc->ofs; |
1177 | xmit->tail &= UART_XMIT_SIZE - 1; | |
1178 | ||
1179 | port->icount.tx += pdc->ofs; | |
1180 | pdc->ofs = 0; | |
1181 | ||
ba0657ff | 1182 | /* more to transmit - setup next transfer */ |
a6670615 | 1183 | |
ba0657ff MT |
1184 | /* disable PDC transmit */ |
1185 | UART_PUT_PTCR(port, ATMEL_PDC_TXTDIS); | |
1186 | ||
1f14081d | 1187 | if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) { |
a6670615 CC |
1188 | dma_sync_single_for_device(port->dev, |
1189 | pdc->dma_addr, | |
1190 | pdc->dma_size, | |
1191 | DMA_TO_DEVICE); | |
1192 | ||
1193 | count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE); | |
1194 | pdc->ofs = count; | |
1195 | ||
1196 | UART_PUT_TPR(port, pdc->dma_addr + xmit->tail); | |
1197 | UART_PUT_TCR(port, count); | |
e8faff73 | 1198 | /* re-enable PDC transmit */ |
a6670615 | 1199 | UART_PUT_PTCR(port, ATMEL_PDC_TXTEN); |
e8faff73 CS |
1200 | /* Enable interrupts */ |
1201 | UART_PUT_IER(port, atmel_port->tx_done_mask); | |
1202 | } else { | |
83cac9f3 BR |
1203 | if ((atmel_port->rs485.flags & SER_RS485_ENABLED) && |
1204 | !(atmel_port->rs485.flags & SER_RS485_RX_DURING_TX)) { | |
e8faff73 CS |
1205 | /* DMA done, stop TX, start RX for RS485 */ |
1206 | atmel_start_rx(port); | |
1207 | } | |
1e6c9c28 | 1208 | } |
a6670615 CC |
1209 | |
1210 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
1211 | uart_write_wakeup(port); | |
1e6c9c28 AV |
1212 | } |
1213 | ||
a930e528 ES |
1214 | static int atmel_prepare_tx_pdc(struct uart_port *port) |
1215 | { | |
1216 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); | |
1217 | struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx; | |
1218 | struct circ_buf *xmit = &port->state->xmit; | |
1219 | ||
1220 | pdc->buf = xmit->buf; | |
1221 | pdc->dma_addr = dma_map_single(port->dev, | |
1222 | pdc->buf, | |
1223 | UART_XMIT_SIZE, | |
1224 | DMA_TO_DEVICE); | |
1225 | pdc->dma_size = UART_XMIT_SIZE; | |
1226 | pdc->ofs = 0; | |
1227 | ||
1228 | return 0; | |
1229 | } | |
1230 | ||
1ecc26bd RB |
1231 | static void atmel_rx_from_ring(struct uart_port *port) |
1232 | { | |
c811ab8c | 1233 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
1ecc26bd RB |
1234 | struct circ_buf *ring = &atmel_port->rx_ring; |
1235 | unsigned int flg; | |
1236 | unsigned int status; | |
1237 | ||
1238 | while (ring->head != ring->tail) { | |
1239 | struct atmel_uart_char c; | |
1240 | ||
1241 | /* Make sure c is loaded after head. */ | |
1242 | smp_rmb(); | |
1243 | ||
1244 | c = ((struct atmel_uart_char *)ring->buf)[ring->tail]; | |
1245 | ||
1246 | ring->tail = (ring->tail + 1) & (ATMEL_SERIAL_RINGSIZE - 1); | |
1247 | ||
1248 | port->icount.rx++; | |
1249 | status = c.status; | |
1250 | flg = TTY_NORMAL; | |
1251 | ||
1252 | /* | |
1253 | * note that the error handling code is | |
1254 | * out of the main execution path | |
1255 | */ | |
1256 | if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME | |
1257 | | ATMEL_US_OVRE | ATMEL_US_RXBRK))) { | |
1258 | if (status & ATMEL_US_RXBRK) { | |
1259 | /* ignore side-effect */ | |
1260 | status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME); | |
1261 | ||
1262 | port->icount.brk++; | |
1263 | if (uart_handle_break(port)) | |
1264 | continue; | |
1265 | } | |
1266 | if (status & ATMEL_US_PARE) | |
1267 | port->icount.parity++; | |
1268 | if (status & ATMEL_US_FRAME) | |
1269 | port->icount.frame++; | |
1270 | if (status & ATMEL_US_OVRE) | |
1271 | port->icount.overrun++; | |
1272 | ||
1273 | status &= port->read_status_mask; | |
1274 | ||
1275 | if (status & ATMEL_US_RXBRK) | |
1276 | flg = TTY_BREAK; | |
1277 | else if (status & ATMEL_US_PARE) | |
1278 | flg = TTY_PARITY; | |
1279 | else if (status & ATMEL_US_FRAME) | |
1280 | flg = TTY_FRAME; | |
1281 | } | |
1282 | ||
1283 | ||
1284 | if (uart_handle_sysrq_char(port, c.ch)) | |
1285 | continue; | |
1286 | ||
1287 | uart_insert_char(port, status, ATMEL_US_OVRE, c.ch, flg); | |
1288 | } | |
1289 | ||
1290 | /* | |
1291 | * Drop the lock here since it might end up calling | |
1292 | * uart_start(), which takes the lock. | |
1293 | */ | |
1294 | spin_unlock(&port->lock); | |
2e124b4a | 1295 | tty_flip_buffer_push(&port->state->port); |
1ecc26bd RB |
1296 | spin_lock(&port->lock); |
1297 | } | |
1298 | ||
a930e528 ES |
1299 | static void atmel_release_rx_pdc(struct uart_port *port) |
1300 | { | |
1301 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); | |
1302 | int i; | |
1303 | ||
1304 | for (i = 0; i < 2; i++) { | |
1305 | struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i]; | |
1306 | ||
1307 | dma_unmap_single(port->dev, | |
1308 | pdc->dma_addr, | |
1309 | pdc->dma_size, | |
1310 | DMA_FROM_DEVICE); | |
1311 | kfree(pdc->buf); | |
1312 | } | |
1313 | } | |
1314 | ||
64e22ebe | 1315 | static void atmel_rx_from_pdc(struct uart_port *port) |
a6670615 | 1316 | { |
c811ab8c | 1317 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
05c7cd39 | 1318 | struct tty_port *tport = &port->state->port; |
a6670615 CC |
1319 | struct atmel_dma_buffer *pdc; |
1320 | int rx_idx = atmel_port->pdc_rx_idx; | |
1321 | unsigned int head; | |
1322 | unsigned int tail; | |
1323 | unsigned int count; | |
1324 | ||
1325 | do { | |
1326 | /* Reset the UART timeout early so that we don't miss one */ | |
1327 | UART_PUT_CR(port, ATMEL_US_STTTO); | |
1328 | ||
1329 | pdc = &atmel_port->pdc_rx[rx_idx]; | |
1330 | head = UART_GET_RPR(port) - pdc->dma_addr; | |
1331 | tail = pdc->ofs; | |
1332 | ||
1333 | /* If the PDC has switched buffers, RPR won't contain | |
1334 | * any address within the current buffer. Since head | |
1335 | * is unsigned, we just need a one-way comparison to | |
1336 | * find out. | |
1337 | * | |
1338 | * In this case, we just need to consume the entire | |
1339 | * buffer and resubmit it for DMA. This will clear the | |
1340 | * ENDRX bit as well, so that we can safely re-enable | |
1341 | * all interrupts below. | |
1342 | */ | |
1343 | head = min(head, pdc->dma_size); | |
1344 | ||
1345 | if (likely(head != tail)) { | |
1346 | dma_sync_single_for_cpu(port->dev, pdc->dma_addr, | |
1347 | pdc->dma_size, DMA_FROM_DEVICE); | |
1348 | ||
1349 | /* | |
1350 | * head will only wrap around when we recycle | |
1351 | * the DMA buffer, and when that happens, we | |
1352 | * explicitly set tail to 0. So head will | |
1353 | * always be greater than tail. | |
1354 | */ | |
1355 | count = head - tail; | |
1356 | ||
05c7cd39 JS |
1357 | tty_insert_flip_string(tport, pdc->buf + pdc->ofs, |
1358 | count); | |
a6670615 CC |
1359 | |
1360 | dma_sync_single_for_device(port->dev, pdc->dma_addr, | |
1361 | pdc->dma_size, DMA_FROM_DEVICE); | |
1362 | ||
1363 | port->icount.rx += count; | |
1364 | pdc->ofs = head; | |
1365 | } | |
1366 | ||
1367 | /* | |
1368 | * If the current buffer is full, we need to check if | |
1369 | * the next one contains any additional data. | |
1370 | */ | |
1371 | if (head >= pdc->dma_size) { | |
1372 | pdc->ofs = 0; | |
1373 | UART_PUT_RNPR(port, pdc->dma_addr); | |
1374 | UART_PUT_RNCR(port, pdc->dma_size); | |
1375 | ||
1376 | rx_idx = !rx_idx; | |
1377 | atmel_port->pdc_rx_idx = rx_idx; | |
1378 | } | |
1379 | } while (head >= pdc->dma_size); | |
1380 | ||
1381 | /* | |
1382 | * Drop the lock here since it might end up calling | |
1383 | * uart_start(), which takes the lock. | |
1384 | */ | |
1385 | spin_unlock(&port->lock); | |
2e124b4a | 1386 | tty_flip_buffer_push(tport); |
a6670615 CC |
1387 | spin_lock(&port->lock); |
1388 | ||
1389 | UART_PUT_IER(port, ATMEL_US_ENDRX | ATMEL_US_TIMEOUT); | |
1390 | } | |
1391 | ||
a930e528 ES |
1392 | static int atmel_prepare_rx_pdc(struct uart_port *port) |
1393 | { | |
1394 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); | |
1395 | int i; | |
1396 | ||
1397 | for (i = 0; i < 2; i++) { | |
1398 | struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i]; | |
1399 | ||
1400 | pdc->buf = kmalloc(PDC_BUFFER_SIZE, GFP_KERNEL); | |
1401 | if (pdc->buf == NULL) { | |
1402 | if (i != 0) { | |
1403 | dma_unmap_single(port->dev, | |
1404 | atmel_port->pdc_rx[0].dma_addr, | |
1405 | PDC_BUFFER_SIZE, | |
1406 | DMA_FROM_DEVICE); | |
1407 | kfree(atmel_port->pdc_rx[0].buf); | |
1408 | } | |
1409 | atmel_port->use_pdc_rx = 0; | |
1410 | return -ENOMEM; | |
1411 | } | |
1412 | pdc->dma_addr = dma_map_single(port->dev, | |
1413 | pdc->buf, | |
1414 | PDC_BUFFER_SIZE, | |
1415 | DMA_FROM_DEVICE); | |
1416 | pdc->dma_size = PDC_BUFFER_SIZE; | |
1417 | pdc->ofs = 0; | |
1418 | } | |
1419 | ||
1420 | atmel_port->pdc_rx_idx = 0; | |
1421 | ||
1422 | UART_PUT_RPR(port, atmel_port->pdc_rx[0].dma_addr); | |
1423 | UART_PUT_RCR(port, PDC_BUFFER_SIZE); | |
1424 | ||
1425 | UART_PUT_RNPR(port, atmel_port->pdc_rx[1].dma_addr); | |
1426 | UART_PUT_RNCR(port, PDC_BUFFER_SIZE); | |
1427 | ||
1428 | return 0; | |
1429 | } | |
1430 | ||
1ecc26bd RB |
1431 | /* |
1432 | * tasklet handling tty stuff outside the interrupt handler. | |
1433 | */ | |
1434 | static void atmel_tasklet_func(unsigned long data) | |
1435 | { | |
1436 | struct uart_port *port = (struct uart_port *)data; | |
c811ab8c | 1437 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
1ecc26bd RB |
1438 | unsigned int status; |
1439 | unsigned int status_change; | |
1440 | ||
1441 | /* The interrupt handler does not take the lock */ | |
1442 | spin_lock(&port->lock); | |
1443 | ||
a930e528 | 1444 | atmel_port->schedule_tx(port); |
1ecc26bd RB |
1445 | |
1446 | status = atmel_port->irq_status; | |
1447 | status_change = status ^ atmel_port->irq_status_prev; | |
1448 | ||
1449 | if (status_change & (ATMEL_US_RI | ATMEL_US_DSR | |
1450 | | ATMEL_US_DCD | ATMEL_US_CTS)) { | |
1451 | /* TODO: All reads to CSR will clear these interrupts! */ | |
1452 | if (status_change & ATMEL_US_RI) | |
1453 | port->icount.rng++; | |
1454 | if (status_change & ATMEL_US_DSR) | |
1455 | port->icount.dsr++; | |
1456 | if (status_change & ATMEL_US_DCD) | |
1457 | uart_handle_dcd_change(port, !(status & ATMEL_US_DCD)); | |
1458 | if (status_change & ATMEL_US_CTS) | |
1459 | uart_handle_cts_change(port, !(status & ATMEL_US_CTS)); | |
1460 | ||
bdc04e31 | 1461 | wake_up_interruptible(&port->state->port.delta_msr_wait); |
1ecc26bd RB |
1462 | |
1463 | atmel_port->irq_status_prev = status; | |
1464 | } | |
1465 | ||
a930e528 | 1466 | atmel_port->schedule_rx(port); |
1ecc26bd RB |
1467 | |
1468 | spin_unlock(&port->lock); | |
1469 | } | |
1470 | ||
33d64c4f ES |
1471 | static int atmel_init_property(struct atmel_uart_port *atmel_port, |
1472 | struct platform_device *pdev) | |
1473 | { | |
1474 | struct device_node *np = pdev->dev.of_node; | |
574de559 | 1475 | struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev); |
33d64c4f ES |
1476 | |
1477 | if (np) { | |
1478 | /* DMA/PDC usage specification */ | |
1479 | if (of_get_property(np, "atmel,use-dma-rx", NULL)) { | |
1480 | if (of_get_property(np, "dmas", NULL)) { | |
1481 | atmel_port->use_dma_rx = true; | |
1482 | atmel_port->use_pdc_rx = false; | |
1483 | } else { | |
1484 | atmel_port->use_dma_rx = false; | |
1485 | atmel_port->use_pdc_rx = true; | |
1486 | } | |
1487 | } else { | |
1488 | atmel_port->use_dma_rx = false; | |
1489 | atmel_port->use_pdc_rx = false; | |
1490 | } | |
1491 | ||
1492 | if (of_get_property(np, "atmel,use-dma-tx", NULL)) { | |
1493 | if (of_get_property(np, "dmas", NULL)) { | |
1494 | atmel_port->use_dma_tx = true; | |
1495 | atmel_port->use_pdc_tx = false; | |
1496 | } else { | |
1497 | atmel_port->use_dma_tx = false; | |
1498 | atmel_port->use_pdc_tx = true; | |
1499 | } | |
1500 | } else { | |
1501 | atmel_port->use_dma_tx = false; | |
1502 | atmel_port->use_pdc_tx = false; | |
1503 | } | |
1504 | ||
1505 | } else { | |
1506 | atmel_port->use_pdc_rx = pdata->use_dma_rx; | |
1507 | atmel_port->use_pdc_tx = pdata->use_dma_tx; | |
1508 | atmel_port->use_dma_rx = false; | |
1509 | atmel_port->use_dma_tx = false; | |
1510 | } | |
1511 | ||
1512 | return 0; | |
1513 | } | |
1514 | ||
1515 | static void atmel_init_rs485(struct atmel_uart_port *atmel_port, | |
1516 | struct platform_device *pdev) | |
1517 | { | |
1518 | struct device_node *np = pdev->dev.of_node; | |
574de559 | 1519 | struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev); |
33d64c4f ES |
1520 | |
1521 | if (np) { | |
1522 | u32 rs485_delay[2]; | |
1523 | /* rs485 properties */ | |
1524 | if (of_property_read_u32_array(np, "rs485-rts-delay", | |
1525 | rs485_delay, 2) == 0) { | |
1526 | struct serial_rs485 *rs485conf = &atmel_port->rs485; | |
1527 | ||
1528 | rs485conf->delay_rts_before_send = rs485_delay[0]; | |
1529 | rs485conf->delay_rts_after_send = rs485_delay[1]; | |
1530 | rs485conf->flags = 0; | |
1531 | ||
1532 | if (of_get_property(np, "rs485-rx-during-tx", NULL)) | |
1533 | rs485conf->flags |= SER_RS485_RX_DURING_TX; | |
1534 | ||
1535 | if (of_get_property(np, "linux,rs485-enabled-at-boot-time", | |
1536 | NULL)) | |
1537 | rs485conf->flags |= SER_RS485_ENABLED; | |
1538 | } | |
1539 | } else { | |
1540 | atmel_port->rs485 = pdata->rs485; | |
1541 | } | |
1542 | ||
1543 | } | |
1544 | ||
a930e528 ES |
1545 | static void atmel_set_ops(struct uart_port *port) |
1546 | { | |
1547 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); | |
1548 | ||
34df42f5 ES |
1549 | if (atmel_use_dma_rx(port)) { |
1550 | atmel_port->prepare_rx = &atmel_prepare_rx_dma; | |
1551 | atmel_port->schedule_rx = &atmel_rx_from_dma; | |
1552 | atmel_port->release_rx = &atmel_release_rx_dma; | |
1553 | } else if (atmel_use_pdc_rx(port)) { | |
a930e528 ES |
1554 | atmel_port->prepare_rx = &atmel_prepare_rx_pdc; |
1555 | atmel_port->schedule_rx = &atmel_rx_from_pdc; | |
1556 | atmel_port->release_rx = &atmel_release_rx_pdc; | |
1557 | } else { | |
1558 | atmel_port->prepare_rx = NULL; | |
1559 | atmel_port->schedule_rx = &atmel_rx_from_ring; | |
1560 | atmel_port->release_rx = NULL; | |
1561 | } | |
1562 | ||
08f738be ES |
1563 | if (atmel_use_dma_tx(port)) { |
1564 | atmel_port->prepare_tx = &atmel_prepare_tx_dma; | |
1565 | atmel_port->schedule_tx = &atmel_tx_dma; | |
1566 | atmel_port->release_tx = &atmel_release_tx_dma; | |
1567 | } else if (atmel_use_pdc_tx(port)) { | |
a930e528 ES |
1568 | atmel_port->prepare_tx = &atmel_prepare_tx_pdc; |
1569 | atmel_port->schedule_tx = &atmel_tx_pdc; | |
1570 | atmel_port->release_tx = &atmel_release_tx_pdc; | |
1571 | } else { | |
1572 | atmel_port->prepare_tx = NULL; | |
1573 | atmel_port->schedule_tx = &atmel_tx_chars; | |
1574 | atmel_port->release_tx = NULL; | |
1575 | } | |
1576 | } | |
1577 | ||
055560b0 ES |
1578 | /* |
1579 | * Get ip name usart or uart | |
1580 | */ | |
892db58b | 1581 | static void atmel_get_ip_name(struct uart_port *port) |
055560b0 ES |
1582 | { |
1583 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); | |
1584 | int name = UART_GET_IP_NAME(port); | |
731d9cae | 1585 | u32 version; |
055560b0 ES |
1586 | int usart, uart; |
1587 | /* usart and uart ascii */ | |
1588 | usart = 0x55534152; | |
1589 | uart = 0x44424755; | |
1590 | ||
1591 | atmel_port->is_usart = false; | |
1592 | ||
1593 | if (name == usart) { | |
1594 | dev_dbg(port->dev, "This is usart\n"); | |
1595 | atmel_port->is_usart = true; | |
1596 | } else if (name == uart) { | |
1597 | dev_dbg(port->dev, "This is uart\n"); | |
1598 | atmel_port->is_usart = false; | |
1599 | } else { | |
731d9cae NF |
1600 | /* fallback for older SoCs: use version field */ |
1601 | version = UART_GET_IP_VERSION(port); | |
1602 | switch (version) { | |
1603 | case 0x302: | |
1604 | case 0x10213: | |
1605 | dev_dbg(port->dev, "This version is usart\n"); | |
1606 | atmel_port->is_usart = true; | |
1607 | break; | |
1608 | case 0x203: | |
1609 | case 0x10202: | |
1610 | dev_dbg(port->dev, "This version is uart\n"); | |
1611 | atmel_port->is_usart = false; | |
1612 | break; | |
1613 | default: | |
1614 | dev_err(port->dev, "Not supported ip name nor version, set to uart\n"); | |
1615 | } | |
055560b0 | 1616 | } |
055560b0 ES |
1617 | } |
1618 | ||
ab5e4e41 RG |
1619 | static void atmel_free_gpio_irq(struct uart_port *port) |
1620 | { | |
1621 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); | |
1622 | enum mctrl_gpio_idx i; | |
1623 | ||
1624 | for (i = 0; i < UART_GPIO_MAX; i++) | |
1625 | if (atmel_port->gpio_irq[i] >= 0) | |
1626 | free_irq(atmel_port->gpio_irq[i], port); | |
1627 | } | |
1628 | ||
1629 | static int atmel_request_gpio_irq(struct uart_port *port) | |
1630 | { | |
1631 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); | |
1632 | int *irq = atmel_port->gpio_irq; | |
1633 | enum mctrl_gpio_idx i; | |
1634 | int err = 0; | |
1635 | ||
1636 | for (i = 0; (i < UART_GPIO_MAX) && !err; i++) { | |
1637 | if (irq[i] < 0) | |
1638 | continue; | |
1639 | ||
1640 | irq_set_status_flags(irq[i], IRQ_NOAUTOEN); | |
1641 | err = request_irq(irq[i], atmel_interrupt, IRQ_TYPE_EDGE_BOTH, | |
1642 | "atmel_serial", port); | |
1643 | if (err) | |
1644 | dev_err(port->dev, "atmel_startup - Can't get %d irq\n", | |
1645 | irq[i]); | |
1646 | } | |
1647 | ||
1648 | /* | |
1649 | * If something went wrong, rollback. | |
1650 | */ | |
1651 | while (err && (--i >= 0)) | |
1652 | if (irq[i] >= 0) | |
1653 | free_irq(irq[i], port); | |
1654 | ||
1655 | return err; | |
1656 | } | |
1657 | ||
1e6c9c28 AV |
1658 | /* |
1659 | * Perform initialization and enable port for reception | |
1660 | */ | |
7192f92c | 1661 | static int atmel_startup(struct uart_port *port) |
1e6c9c28 | 1662 | { |
33d64c4f | 1663 | struct platform_device *pdev = to_platform_device(port->dev); |
c811ab8c | 1664 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
ebd2c8f6 | 1665 | struct tty_struct *tty = port->state->port.tty; |
1e6c9c28 AV |
1666 | int retval; |
1667 | ||
1668 | /* | |
1669 | * Ensure that no interrupts are enabled otherwise when | |
1670 | * request_irq() is called we could get stuck trying to | |
1671 | * handle an unexpected interrupt | |
1672 | */ | |
1673 | UART_PUT_IDR(port, -1); | |
ab5e4e41 | 1674 | atmel_port->ms_irq_enabled = false; |
1e6c9c28 AV |
1675 | |
1676 | /* | |
1677 | * Allocate the IRQ | |
1678 | */ | |
b843aa21 | 1679 | retval = request_irq(port->irq, atmel_interrupt, IRQF_SHARED, |
ae161068 | 1680 | tty ? tty->name : "atmel_serial", port); |
1e6c9c28 | 1681 | if (retval) { |
ddaa6037 | 1682 | dev_err(port->dev, "atmel_startup - Can't get irq\n"); |
1e6c9c28 AV |
1683 | return retval; |
1684 | } | |
1685 | ||
ab5e4e41 RG |
1686 | /* |
1687 | * Get the GPIO lines IRQ | |
1688 | */ | |
1689 | retval = atmel_request_gpio_irq(port); | |
1690 | if (retval) | |
1691 | goto free_irq; | |
1692 | ||
a6670615 CC |
1693 | /* |
1694 | * Initialize DMA (if necessary) | |
1695 | */ | |
33d64c4f ES |
1696 | atmel_init_property(atmel_port, pdev); |
1697 | ||
a930e528 ES |
1698 | if (atmel_port->prepare_rx) { |
1699 | retval = atmel_port->prepare_rx(port); | |
1700 | if (retval < 0) | |
1701 | atmel_set_ops(port); | |
a6670615 | 1702 | } |
a6670615 | 1703 | |
a930e528 ES |
1704 | if (atmel_port->prepare_tx) { |
1705 | retval = atmel_port->prepare_tx(port); | |
1706 | if (retval < 0) | |
1707 | atmel_set_ops(port); | |
a6670615 | 1708 | } |
1e6c9c28 | 1709 | |
27c0c8e5 | 1710 | /* Save current CSR for comparison in atmel_tasklet_func() */ |
e0b0baad | 1711 | atmel_port->irq_status_prev = atmel_get_lines_status(port); |
27c0c8e5 AN |
1712 | atmel_port->irq_status = atmel_port->irq_status_prev; |
1713 | ||
1e6c9c28 AV |
1714 | /* |
1715 | * Finally, enable the serial port | |
1716 | */ | |
7192f92c | 1717 | UART_PUT_CR(port, ATMEL_US_RSTSTA | ATMEL_US_RSTRX); |
b843aa21 RB |
1718 | /* enable xmit & rcvr */ |
1719 | UART_PUT_CR(port, ATMEL_US_TXEN | ATMEL_US_RXEN); | |
afefc415 | 1720 | |
8bc661bf MR |
1721 | setup_timer(&atmel_port->uart_timer, |
1722 | atmel_uart_timer_callback, | |
1723 | (unsigned long)port); | |
1724 | ||
64e22ebe | 1725 | if (atmel_use_pdc_rx(port)) { |
a6670615 | 1726 | /* set UART timeout */ |
2e68c22f | 1727 | if (!atmel_port->is_usart) { |
2e68c22f ES |
1728 | mod_timer(&atmel_port->uart_timer, |
1729 | jiffies + uart_poll_timeout(port)); | |
1730 | /* set USART timeout */ | |
1731 | } else { | |
1732 | UART_PUT_RTOR(port, PDC_RX_TIMEOUT); | |
1733 | UART_PUT_CR(port, ATMEL_US_STTTO); | |
a6670615 | 1734 | |
2e68c22f ES |
1735 | UART_PUT_IER(port, ATMEL_US_ENDRX | ATMEL_US_TIMEOUT); |
1736 | } | |
a6670615 CC |
1737 | /* enable PDC controller */ |
1738 | UART_PUT_PTCR(port, ATMEL_PDC_RXTEN); | |
34df42f5 | 1739 | } else if (atmel_use_dma_rx(port)) { |
2e68c22f ES |
1740 | /* set UART timeout */ |
1741 | if (!atmel_port->is_usart) { | |
2e68c22f ES |
1742 | mod_timer(&atmel_port->uart_timer, |
1743 | jiffies + uart_poll_timeout(port)); | |
1744 | /* set USART timeout */ | |
1745 | } else { | |
1746 | UART_PUT_RTOR(port, PDC_RX_TIMEOUT); | |
1747 | UART_PUT_CR(port, ATMEL_US_STTTO); | |
34df42f5 | 1748 | |
2e68c22f ES |
1749 | UART_PUT_IER(port, ATMEL_US_TIMEOUT); |
1750 | } | |
a6670615 CC |
1751 | } else { |
1752 | /* enable receive only */ | |
1753 | UART_PUT_IER(port, ATMEL_US_RXRDY); | |
1754 | } | |
afefc415 | 1755 | |
1e6c9c28 | 1756 | return 0; |
ab5e4e41 RG |
1757 | |
1758 | free_irq: | |
1759 | free_irq(port->irq, port); | |
1760 | ||
1761 | return retval; | |
1e6c9c28 AV |
1762 | } |
1763 | ||
1764 | /* | |
1765 | * Disable the port | |
1766 | */ | |
7192f92c | 1767 | static void atmel_shutdown(struct uart_port *port) |
1e6c9c28 | 1768 | { |
c811ab8c | 1769 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
0cc7c6c7 | 1770 | |
8bc661bf MR |
1771 | /* |
1772 | * Prevent any tasklets being scheduled during | |
1773 | * cleanup | |
1774 | */ | |
1775 | del_timer_sync(&atmel_port->uart_timer); | |
1776 | ||
0cc7c6c7 MR |
1777 | /* |
1778 | * Clear out any scheduled tasklets before | |
1779 | * we destroy the buffers | |
1780 | */ | |
1781 | tasklet_kill(&atmel_port->tasklet); | |
1782 | ||
a6670615 | 1783 | /* |
0cc7c6c7 MR |
1784 | * Ensure everything is stopped and |
1785 | * disable all interrupts, port and break condition. | |
a6670615 CC |
1786 | */ |
1787 | atmel_stop_rx(port); | |
1788 | atmel_stop_tx(port); | |
1789 | ||
0cc7c6c7 MR |
1790 | UART_PUT_CR(port, ATMEL_US_RSTSTA); |
1791 | UART_PUT_IDR(port, -1); | |
1792 | ||
1793 | ||
a6670615 CC |
1794 | /* |
1795 | * Shut-down the DMA. | |
1796 | */ | |
a930e528 ES |
1797 | if (atmel_port->release_rx) |
1798 | atmel_port->release_rx(port); | |
1799 | if (atmel_port->release_tx) | |
1800 | atmel_port->release_tx(port); | |
a6670615 | 1801 | |
bb7e73c5 MD |
1802 | /* |
1803 | * Reset ring buffer pointers | |
1804 | */ | |
1805 | atmel_port->rx_ring.head = 0; | |
1806 | atmel_port->rx_ring.tail = 0; | |
1807 | ||
1e6c9c28 | 1808 | /* |
ab5e4e41 | 1809 | * Free the interrupts |
1e6c9c28 AV |
1810 | */ |
1811 | free_irq(port->irq, port); | |
ab5e4e41 RG |
1812 | atmel_free_gpio_irq(port); |
1813 | ||
1814 | atmel_port->ms_irq_enabled = false; | |
1e6c9c28 AV |
1815 | } |
1816 | ||
9afd561a HS |
1817 | /* |
1818 | * Flush any TX data submitted for DMA. Called when the TX circular | |
1819 | * buffer is reset. | |
1820 | */ | |
1821 | static void atmel_flush_buffer(struct uart_port *port) | |
1822 | { | |
1823 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); | |
1824 | ||
64e22ebe | 1825 | if (atmel_use_pdc_tx(port)) { |
9afd561a HS |
1826 | UART_PUT_TCR(port, 0); |
1827 | atmel_port->pdc_tx.ofs = 0; | |
1828 | } | |
1829 | } | |
1830 | ||
1e6c9c28 AV |
1831 | /* |
1832 | * Power / Clock management. | |
1833 | */ | |
b843aa21 RB |
1834 | static void atmel_serial_pm(struct uart_port *port, unsigned int state, |
1835 | unsigned int oldstate) | |
1e6c9c28 | 1836 | { |
c811ab8c | 1837 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
afefc415 | 1838 | |
1e6c9c28 | 1839 | switch (state) { |
b843aa21 RB |
1840 | case 0: |
1841 | /* | |
1842 | * Enable the peripheral clock for this serial port. | |
1843 | * This is called on uart_open() or a resume event. | |
1844 | */ | |
91f8c2d8 | 1845 | clk_prepare_enable(atmel_port->clk); |
f05596db AS |
1846 | |
1847 | /* re-enable interrupts if we disabled some on suspend */ | |
1848 | UART_PUT_IER(port, atmel_port->backup_imr); | |
b843aa21 RB |
1849 | break; |
1850 | case 3: | |
f05596db AS |
1851 | /* Back up the interrupt mask and disable all interrupts */ |
1852 | atmel_port->backup_imr = UART_GET_IMR(port); | |
1853 | UART_PUT_IDR(port, -1); | |
1854 | ||
b843aa21 RB |
1855 | /* |
1856 | * Disable the peripheral clock for this serial port. | |
1857 | * This is called on uart_close() or a suspend event. | |
1858 | */ | |
91f8c2d8 | 1859 | clk_disable_unprepare(atmel_port->clk); |
b843aa21 RB |
1860 | break; |
1861 | default: | |
ddaa6037 | 1862 | dev_err(port->dev, "atmel_serial: unknown pm %d\n", state); |
1e6c9c28 AV |
1863 | } |
1864 | } | |
1865 | ||
1866 | /* | |
1867 | * Change the port parameters | |
1868 | */ | |
b843aa21 RB |
1869 | static void atmel_set_termios(struct uart_port *port, struct ktermios *termios, |
1870 | struct ktermios *old) | |
1e6c9c28 AV |
1871 | { |
1872 | unsigned long flags; | |
1873 | unsigned int mode, imr, quot, baud; | |
e8faff73 | 1874 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
1e6c9c28 | 1875 | |
03abeac0 | 1876 | /* Get current mode register */ |
b843aa21 | 1877 | mode = UART_GET_MR(port) & ~(ATMEL_US_USCLKS | ATMEL_US_CHRL |
8e706c4d PM |
1878 | | ATMEL_US_NBSTOP | ATMEL_US_PAR |
1879 | | ATMEL_US_USMODE); | |
03abeac0 | 1880 | |
b843aa21 | 1881 | baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16); |
1e6c9c28 AV |
1882 | quot = uart_get_divisor(port, baud); |
1883 | ||
b843aa21 | 1884 | if (quot > 65535) { /* BRGR is 16-bit, so switch to slower clock */ |
03abeac0 AV |
1885 | quot /= 8; |
1886 | mode |= ATMEL_US_USCLKS_MCK_DIV8; | |
1887 | } | |
1e6c9c28 AV |
1888 | |
1889 | /* byte size */ | |
1890 | switch (termios->c_cflag & CSIZE) { | |
1891 | case CS5: | |
7192f92c | 1892 | mode |= ATMEL_US_CHRL_5; |
1e6c9c28 AV |
1893 | break; |
1894 | case CS6: | |
7192f92c | 1895 | mode |= ATMEL_US_CHRL_6; |
1e6c9c28 AV |
1896 | break; |
1897 | case CS7: | |
7192f92c | 1898 | mode |= ATMEL_US_CHRL_7; |
1e6c9c28 AV |
1899 | break; |
1900 | default: | |
7192f92c | 1901 | mode |= ATMEL_US_CHRL_8; |
1e6c9c28 AV |
1902 | break; |
1903 | } | |
1904 | ||
1905 | /* stop bits */ | |
1906 | if (termios->c_cflag & CSTOPB) | |
7192f92c | 1907 | mode |= ATMEL_US_NBSTOP_2; |
1e6c9c28 AV |
1908 | |
1909 | /* parity */ | |
1910 | if (termios->c_cflag & PARENB) { | |
b843aa21 RB |
1911 | /* Mark or Space parity */ |
1912 | if (termios->c_cflag & CMSPAR) { | |
1e6c9c28 | 1913 | if (termios->c_cflag & PARODD) |
7192f92c | 1914 | mode |= ATMEL_US_PAR_MARK; |
1e6c9c28 | 1915 | else |
7192f92c | 1916 | mode |= ATMEL_US_PAR_SPACE; |
b843aa21 | 1917 | } else if (termios->c_cflag & PARODD) |
7192f92c | 1918 | mode |= ATMEL_US_PAR_ODD; |
1e6c9c28 | 1919 | else |
7192f92c | 1920 | mode |= ATMEL_US_PAR_EVEN; |
b843aa21 | 1921 | } else |
7192f92c | 1922 | mode |= ATMEL_US_PAR_NONE; |
1e6c9c28 | 1923 | |
8e706c4d PM |
1924 | /* hardware handshake (RTS/CTS) */ |
1925 | if (termios->c_cflag & CRTSCTS) | |
1926 | mode |= ATMEL_US_USMODE_HWHS; | |
1927 | else | |
1928 | mode |= ATMEL_US_USMODE_NORMAL; | |
1929 | ||
1e6c9c28 AV |
1930 | spin_lock_irqsave(&port->lock, flags); |
1931 | ||
7192f92c | 1932 | port->read_status_mask = ATMEL_US_OVRE; |
1e6c9c28 | 1933 | if (termios->c_iflag & INPCK) |
7192f92c | 1934 | port->read_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE); |
ef8b9ddc | 1935 | if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) |
7192f92c | 1936 | port->read_status_mask |= ATMEL_US_RXBRK; |
1e6c9c28 | 1937 | |
64e22ebe | 1938 | if (atmel_use_pdc_rx(port)) |
a6670615 CC |
1939 | /* need to enable error interrupts */ |
1940 | UART_PUT_IER(port, port->read_status_mask); | |
1941 | ||
1e6c9c28 AV |
1942 | /* |
1943 | * Characters to ignore | |
1944 | */ | |
1945 | port->ignore_status_mask = 0; | |
1946 | if (termios->c_iflag & IGNPAR) | |
7192f92c | 1947 | port->ignore_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE); |
1e6c9c28 | 1948 | if (termios->c_iflag & IGNBRK) { |
7192f92c | 1949 | port->ignore_status_mask |= ATMEL_US_RXBRK; |
1e6c9c28 AV |
1950 | /* |
1951 | * If we're ignoring parity and break indicators, | |
1952 | * ignore overruns too (for real raw support). | |
1953 | */ | |
1954 | if (termios->c_iflag & IGNPAR) | |
7192f92c | 1955 | port->ignore_status_mask |= ATMEL_US_OVRE; |
1e6c9c28 | 1956 | } |
b843aa21 | 1957 | /* TODO: Ignore all characters if CREAD is set.*/ |
1e6c9c28 AV |
1958 | |
1959 | /* update the per-port timeout */ | |
1960 | uart_update_timeout(port, termios->c_cflag, baud); | |
1961 | ||
0ccad870 HS |
1962 | /* |
1963 | * save/disable interrupts. The tty layer will ensure that the | |
1964 | * transmitter is empty if requested by the caller, so there's | |
1965 | * no need to wait for it here. | |
1966 | */ | |
b843aa21 RB |
1967 | imr = UART_GET_IMR(port); |
1968 | UART_PUT_IDR(port, -1); | |
1e6c9c28 AV |
1969 | |
1970 | /* disable receiver and transmitter */ | |
7192f92c | 1971 | UART_PUT_CR(port, ATMEL_US_TXDIS | ATMEL_US_RXDIS); |
1e6c9c28 | 1972 | |
e8faff73 CS |
1973 | /* Resetting serial mode to RS232 (0x0) */ |
1974 | mode &= ~ATMEL_US_USMODE; | |
1975 | ||
1976 | if (atmel_port->rs485.flags & SER_RS485_ENABLED) { | |
93f3350c | 1977 | if ((atmel_port->rs485.delay_rts_after_send) > 0) |
1b633184 CS |
1978 | UART_PUT_TTGR(port, |
1979 | atmel_port->rs485.delay_rts_after_send); | |
e8faff73 | 1980 | mode |= ATMEL_US_USMODE_RS485; |
e8faff73 CS |
1981 | } |
1982 | ||
1e6c9c28 AV |
1983 | /* set the parity, stop bits and data size */ |
1984 | UART_PUT_MR(port, mode); | |
1985 | ||
1986 | /* set the baud rate */ | |
1987 | UART_PUT_BRGR(port, quot); | |
7192f92c HS |
1988 | UART_PUT_CR(port, ATMEL_US_RSTSTA | ATMEL_US_RSTRX); |
1989 | UART_PUT_CR(port, ATMEL_US_TXEN | ATMEL_US_RXEN); | |
1e6c9c28 AV |
1990 | |
1991 | /* restore interrupts */ | |
1992 | UART_PUT_IER(port, imr); | |
1993 | ||
1994 | /* CTS flow-control and modem-status interrupts */ | |
1995 | if (UART_ENABLE_MS(port, termios->c_cflag)) | |
1996 | port->ops->enable_ms(port); | |
1997 | ||
1998 | spin_unlock_irqrestore(&port->lock, flags); | |
1999 | } | |
2000 | ||
42bd7a4f VP |
2001 | static void atmel_set_ldisc(struct uart_port *port, int new) |
2002 | { | |
b54bf3b2 | 2003 | if (new == N_PPS) { |
42bd7a4f VP |
2004 | port->flags |= UPF_HARDPPS_CD; |
2005 | atmel_enable_ms(port); | |
2006 | } else { | |
2007 | port->flags &= ~UPF_HARDPPS_CD; | |
2008 | } | |
2009 | } | |
2010 | ||
1e6c9c28 AV |
2011 | /* |
2012 | * Return string describing the specified port | |
2013 | */ | |
7192f92c | 2014 | static const char *atmel_type(struct uart_port *port) |
1e6c9c28 | 2015 | { |
9ab4f88b | 2016 | return (port->type == PORT_ATMEL) ? "ATMEL_SERIAL" : NULL; |
1e6c9c28 AV |
2017 | } |
2018 | ||
2019 | /* | |
2020 | * Release the memory region(s) being used by 'port'. | |
2021 | */ | |
7192f92c | 2022 | static void atmel_release_port(struct uart_port *port) |
1e6c9c28 | 2023 | { |
afefc415 AV |
2024 | struct platform_device *pdev = to_platform_device(port->dev); |
2025 | int size = pdev->resource[0].end - pdev->resource[0].start + 1; | |
2026 | ||
2027 | release_mem_region(port->mapbase, size); | |
2028 | ||
2029 | if (port->flags & UPF_IOREMAP) { | |
2030 | iounmap(port->membase); | |
2031 | port->membase = NULL; | |
2032 | } | |
1e6c9c28 AV |
2033 | } |
2034 | ||
2035 | /* | |
2036 | * Request the memory region(s) being used by 'port'. | |
2037 | */ | |
7192f92c | 2038 | static int atmel_request_port(struct uart_port *port) |
1e6c9c28 | 2039 | { |
afefc415 AV |
2040 | struct platform_device *pdev = to_platform_device(port->dev); |
2041 | int size = pdev->resource[0].end - pdev->resource[0].start + 1; | |
2042 | ||
7192f92c | 2043 | if (!request_mem_region(port->mapbase, size, "atmel_serial")) |
afefc415 AV |
2044 | return -EBUSY; |
2045 | ||
2046 | if (port->flags & UPF_IOREMAP) { | |
2047 | port->membase = ioremap(port->mapbase, size); | |
2048 | if (port->membase == NULL) { | |
2049 | release_mem_region(port->mapbase, size); | |
2050 | return -ENOMEM; | |
2051 | } | |
2052 | } | |
1e6c9c28 | 2053 | |
afefc415 | 2054 | return 0; |
1e6c9c28 AV |
2055 | } |
2056 | ||
2057 | /* | |
2058 | * Configure/autoconfigure the port. | |
2059 | */ | |
7192f92c | 2060 | static void atmel_config_port(struct uart_port *port, int flags) |
1e6c9c28 AV |
2061 | { |
2062 | if (flags & UART_CONFIG_TYPE) { | |
9ab4f88b | 2063 | port->type = PORT_ATMEL; |
7192f92c | 2064 | atmel_request_port(port); |
1e6c9c28 AV |
2065 | } |
2066 | } | |
2067 | ||
2068 | /* | |
2069 | * Verify the new serial_struct (for TIOCSSERIAL). | |
2070 | */ | |
7192f92c | 2071 | static int atmel_verify_port(struct uart_port *port, struct serial_struct *ser) |
1e6c9c28 AV |
2072 | { |
2073 | int ret = 0; | |
9ab4f88b | 2074 | if (ser->type != PORT_UNKNOWN && ser->type != PORT_ATMEL) |
1e6c9c28 AV |
2075 | ret = -EINVAL; |
2076 | if (port->irq != ser->irq) | |
2077 | ret = -EINVAL; | |
2078 | if (ser->io_type != SERIAL_IO_MEM) | |
2079 | ret = -EINVAL; | |
2080 | if (port->uartclk / 16 != ser->baud_base) | |
2081 | ret = -EINVAL; | |
2082 | if ((void *)port->mapbase != ser->iomem_base) | |
2083 | ret = -EINVAL; | |
2084 | if (port->iobase != ser->port) | |
2085 | ret = -EINVAL; | |
2086 | if (ser->hub6 != 0) | |
2087 | ret = -EINVAL; | |
2088 | return ret; | |
2089 | } | |
2090 | ||
8fe2d541 AT |
2091 | #ifdef CONFIG_CONSOLE_POLL |
2092 | static int atmel_poll_get_char(struct uart_port *port) | |
2093 | { | |
2094 | while (!(UART_GET_CSR(port) & ATMEL_US_RXRDY)) | |
2095 | cpu_relax(); | |
2096 | ||
2097 | return UART_GET_CHAR(port); | |
2098 | } | |
2099 | ||
2100 | static void atmel_poll_put_char(struct uart_port *port, unsigned char ch) | |
2101 | { | |
2102 | while (!(UART_GET_CSR(port) & ATMEL_US_TXRDY)) | |
2103 | cpu_relax(); | |
2104 | ||
2105 | UART_PUT_CHAR(port, ch); | |
2106 | } | |
2107 | #endif | |
2108 | ||
e8faff73 CS |
2109 | static int |
2110 | atmel_ioctl(struct uart_port *port, unsigned int cmd, unsigned long arg) | |
2111 | { | |
2112 | struct serial_rs485 rs485conf; | |
2113 | ||
2114 | switch (cmd) { | |
2115 | case TIOCSRS485: | |
2116 | if (copy_from_user(&rs485conf, (struct serial_rs485 *) arg, | |
2117 | sizeof(rs485conf))) | |
2118 | return -EFAULT; | |
2119 | ||
2120 | atmel_config_rs485(port, &rs485conf); | |
2121 | break; | |
2122 | ||
2123 | case TIOCGRS485: | |
2124 | if (copy_to_user((struct serial_rs485 *) arg, | |
2125 | &(to_atmel_uart_port(port)->rs485), | |
2126 | sizeof(rs485conf))) | |
2127 | return -EFAULT; | |
2128 | break; | |
2129 | ||
2130 | default: | |
2131 | return -ENOIOCTLCMD; | |
2132 | } | |
2133 | return 0; | |
2134 | } | |
2135 | ||
2136 | ||
2137 | ||
7192f92c HS |
2138 | static struct uart_ops atmel_pops = { |
2139 | .tx_empty = atmel_tx_empty, | |
2140 | .set_mctrl = atmel_set_mctrl, | |
2141 | .get_mctrl = atmel_get_mctrl, | |
2142 | .stop_tx = atmel_stop_tx, | |
2143 | .start_tx = atmel_start_tx, | |
2144 | .stop_rx = atmel_stop_rx, | |
2145 | .enable_ms = atmel_enable_ms, | |
2146 | .break_ctl = atmel_break_ctl, | |
2147 | .startup = atmel_startup, | |
2148 | .shutdown = atmel_shutdown, | |
9afd561a | 2149 | .flush_buffer = atmel_flush_buffer, |
7192f92c | 2150 | .set_termios = atmel_set_termios, |
42bd7a4f | 2151 | .set_ldisc = atmel_set_ldisc, |
7192f92c HS |
2152 | .type = atmel_type, |
2153 | .release_port = atmel_release_port, | |
2154 | .request_port = atmel_request_port, | |
2155 | .config_port = atmel_config_port, | |
2156 | .verify_port = atmel_verify_port, | |
2157 | .pm = atmel_serial_pm, | |
e8faff73 | 2158 | .ioctl = atmel_ioctl, |
8fe2d541 AT |
2159 | #ifdef CONFIG_CONSOLE_POLL |
2160 | .poll_get_char = atmel_poll_get_char, | |
2161 | .poll_put_char = atmel_poll_put_char, | |
2162 | #endif | |
1e6c9c28 AV |
2163 | }; |
2164 | ||
afefc415 AV |
2165 | /* |
2166 | * Configure the port from the platform device resource info. | |
2167 | */ | |
91f8c2d8 | 2168 | static int atmel_init_port(struct atmel_uart_port *atmel_port, |
b843aa21 | 2169 | struct platform_device *pdev) |
1e6c9c28 | 2170 | { |
91f8c2d8 | 2171 | int ret; |
7192f92c | 2172 | struct uart_port *port = &atmel_port->uart; |
574de559 | 2173 | struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev); |
afefc415 | 2174 | |
33d64c4f ES |
2175 | if (!atmel_init_property(atmel_port, pdev)) |
2176 | atmel_set_ops(port); | |
afefc415 | 2177 | |
33d64c4f | 2178 | atmel_init_rs485(atmel_port, pdev); |
a930e528 | 2179 | |
e8faff73 CS |
2180 | port->iotype = UPIO_MEM; |
2181 | port->flags = UPF_BOOT_AUTOCONF; | |
2182 | port->ops = &atmel_pops; | |
2183 | port->fifosize = 1; | |
e8faff73 | 2184 | port->dev = &pdev->dev; |
afefc415 AV |
2185 | port->mapbase = pdev->resource[0].start; |
2186 | port->irq = pdev->resource[1].start; | |
2187 | ||
1ecc26bd RB |
2188 | tasklet_init(&atmel_port->tasklet, atmel_tasklet_func, |
2189 | (unsigned long)port); | |
2190 | ||
2191 | memset(&atmel_port->rx_ring, 0, sizeof(atmel_port->rx_ring)); | |
2192 | ||
5fbe46b6 | 2193 | if (pdata && pdata->regs) { |
75d35213 | 2194 | /* Already mapped by setup code */ |
1acfc7ec | 2195 | port->membase = pdata->regs; |
588edbf3 | 2196 | } else { |
afefc415 AV |
2197 | port->flags |= UPF_IOREMAP; |
2198 | port->membase = NULL; | |
2199 | } | |
1e6c9c28 | 2200 | |
b843aa21 RB |
2201 | /* for console, the clock could already be configured */ |
2202 | if (!atmel_port->clk) { | |
7192f92c | 2203 | atmel_port->clk = clk_get(&pdev->dev, "usart"); |
91f8c2d8 BB |
2204 | if (IS_ERR(atmel_port->clk)) { |
2205 | ret = PTR_ERR(atmel_port->clk); | |
2206 | atmel_port->clk = NULL; | |
2207 | return ret; | |
2208 | } | |
2209 | ret = clk_prepare_enable(atmel_port->clk); | |
2210 | if (ret) { | |
2211 | clk_put(atmel_port->clk); | |
2212 | atmel_port->clk = NULL; | |
2213 | return ret; | |
2214 | } | |
7192f92c | 2215 | port->uartclk = clk_get_rate(atmel_port->clk); |
91f8c2d8 | 2216 | clk_disable_unprepare(atmel_port->clk); |
06a7f058 | 2217 | /* only enable clock when USART is in use */ |
afefc415 | 2218 | } |
a6670615 | 2219 | |
e8faff73 CS |
2220 | /* Use TXEMPTY for interrupt when rs485 else TXRDY or ENDTX|TXBUFE */ |
2221 | if (atmel_port->rs485.flags & SER_RS485_ENABLED) | |
2222 | atmel_port->tx_done_mask = ATMEL_US_TXEMPTY; | |
64e22ebe | 2223 | else if (atmel_use_pdc_tx(port)) { |
a6670615 | 2224 | port->fifosize = PDC_BUFFER_SIZE; |
e8faff73 CS |
2225 | atmel_port->tx_done_mask = ATMEL_US_ENDTX | ATMEL_US_TXBUFE; |
2226 | } else { | |
2227 | atmel_port->tx_done_mask = ATMEL_US_TXRDY; | |
2228 | } | |
91f8c2d8 BB |
2229 | |
2230 | return 0; | |
1e6c9c28 AV |
2231 | } |
2232 | ||
69f6a27b JCPV |
2233 | struct platform_device *atmel_default_console_device; /* the serial console device */ |
2234 | ||
749c4e60 | 2235 | #ifdef CONFIG_SERIAL_ATMEL_CONSOLE |
7192f92c | 2236 | static void atmel_console_putchar(struct uart_port *port, int ch) |
d358788f | 2237 | { |
7192f92c | 2238 | while (!(UART_GET_CSR(port) & ATMEL_US_TXRDY)) |
829dd811 | 2239 | cpu_relax(); |
d358788f RK |
2240 | UART_PUT_CHAR(port, ch); |
2241 | } | |
1e6c9c28 AV |
2242 | |
2243 | /* | |
2244 | * Interrupts are disabled on entering | |
2245 | */ | |
7192f92c | 2246 | static void atmel_console_write(struct console *co, const char *s, u_int count) |
1e6c9c28 | 2247 | { |
7192f92c | 2248 | struct uart_port *port = &atmel_ports[co->index].uart; |
e8faff73 | 2249 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
d358788f | 2250 | unsigned int status, imr; |
39d4c922 | 2251 | unsigned int pdc_tx; |
1e6c9c28 AV |
2252 | |
2253 | /* | |
b843aa21 | 2254 | * First, save IMR and then disable interrupts |
1e6c9c28 | 2255 | */ |
b843aa21 | 2256 | imr = UART_GET_IMR(port); |
e8faff73 | 2257 | UART_PUT_IDR(port, ATMEL_US_RXRDY | atmel_port->tx_done_mask); |
1e6c9c28 | 2258 | |
39d4c922 MP |
2259 | /* Store PDC transmit status and disable it */ |
2260 | pdc_tx = UART_GET_PTSR(port) & ATMEL_PDC_TXTEN; | |
2261 | UART_PUT_PTCR(port, ATMEL_PDC_TXTDIS); | |
2262 | ||
7192f92c | 2263 | uart_console_write(port, s, count, atmel_console_putchar); |
1e6c9c28 AV |
2264 | |
2265 | /* | |
b843aa21 RB |
2266 | * Finally, wait for transmitter to become empty |
2267 | * and restore IMR | |
1e6c9c28 AV |
2268 | */ |
2269 | do { | |
2270 | status = UART_GET_CSR(port); | |
7192f92c | 2271 | } while (!(status & ATMEL_US_TXRDY)); |
39d4c922 MP |
2272 | |
2273 | /* Restore PDC transmit status */ | |
2274 | if (pdc_tx) | |
2275 | UART_PUT_PTCR(port, ATMEL_PDC_TXTEN); | |
2276 | ||
b843aa21 RB |
2277 | /* set interrupts back the way they were */ |
2278 | UART_PUT_IER(port, imr); | |
1e6c9c28 AV |
2279 | } |
2280 | ||
2281 | /* | |
b843aa21 RB |
2282 | * If the port was already initialised (eg, by a boot loader), |
2283 | * try to determine the current setup. | |
1e6c9c28 | 2284 | */ |
b843aa21 RB |
2285 | static void __init atmel_console_get_options(struct uart_port *port, int *baud, |
2286 | int *parity, int *bits) | |
1e6c9c28 AV |
2287 | { |
2288 | unsigned int mr, quot; | |
2289 | ||
1c0fd82f HS |
2290 | /* |
2291 | * If the baud rate generator isn't running, the port wasn't | |
2292 | * initialized by the boot loader. | |
2293 | */ | |
9c81c5c9 | 2294 | quot = UART_GET_BRGR(port) & ATMEL_US_CD; |
1c0fd82f HS |
2295 | if (!quot) |
2296 | return; | |
1e6c9c28 | 2297 | |
7192f92c HS |
2298 | mr = UART_GET_MR(port) & ATMEL_US_CHRL; |
2299 | if (mr == ATMEL_US_CHRL_8) | |
1e6c9c28 AV |
2300 | *bits = 8; |
2301 | else | |
2302 | *bits = 7; | |
2303 | ||
7192f92c HS |
2304 | mr = UART_GET_MR(port) & ATMEL_US_PAR; |
2305 | if (mr == ATMEL_US_PAR_EVEN) | |
1e6c9c28 | 2306 | *parity = 'e'; |
7192f92c | 2307 | else if (mr == ATMEL_US_PAR_ODD) |
1e6c9c28 AV |
2308 | *parity = 'o'; |
2309 | ||
4d5e392c HS |
2310 | /* |
2311 | * The serial core only rounds down when matching this to a | |
2312 | * supported baud rate. Make sure we don't end up slightly | |
2313 | * lower than one of those, as it would make us fall through | |
2314 | * to a much lower baud rate than we really want. | |
2315 | */ | |
4d5e392c | 2316 | *baud = port->uartclk / (16 * (quot - 1)); |
1e6c9c28 AV |
2317 | } |
2318 | ||
7192f92c | 2319 | static int __init atmel_console_setup(struct console *co, char *options) |
1e6c9c28 | 2320 | { |
91f8c2d8 | 2321 | int ret; |
7192f92c | 2322 | struct uart_port *port = &atmel_ports[co->index].uart; |
1e6c9c28 AV |
2323 | int baud = 115200; |
2324 | int bits = 8; | |
2325 | int parity = 'n'; | |
2326 | int flow = 'n'; | |
2327 | ||
b843aa21 RB |
2328 | if (port->membase == NULL) { |
2329 | /* Port not initialized yet - delay setup */ | |
afefc415 | 2330 | return -ENODEV; |
b843aa21 | 2331 | } |
1e6c9c28 | 2332 | |
91f8c2d8 BB |
2333 | ret = clk_prepare_enable(atmel_ports[co->index].clk); |
2334 | if (ret) | |
2335 | return ret; | |
06a7f058 | 2336 | |
b843aa21 | 2337 | UART_PUT_IDR(port, -1); |
7192f92c HS |
2338 | UART_PUT_CR(port, ATMEL_US_RSTSTA | ATMEL_US_RSTRX); |
2339 | UART_PUT_CR(port, ATMEL_US_TXEN | ATMEL_US_RXEN); | |
1e6c9c28 AV |
2340 | |
2341 | if (options) | |
2342 | uart_parse_options(options, &baud, &parity, &bits, &flow); | |
2343 | else | |
7192f92c | 2344 | atmel_console_get_options(port, &baud, &parity, &bits); |
1e6c9c28 AV |
2345 | |
2346 | return uart_set_options(port, co, baud, parity, bits, flow); | |
2347 | } | |
2348 | ||
7192f92c | 2349 | static struct uart_driver atmel_uart; |
1e6c9c28 | 2350 | |
7192f92c HS |
2351 | static struct console atmel_console = { |
2352 | .name = ATMEL_DEVICENAME, | |
2353 | .write = atmel_console_write, | |
1e6c9c28 | 2354 | .device = uart_console_device, |
7192f92c | 2355 | .setup = atmel_console_setup, |
1e6c9c28 AV |
2356 | .flags = CON_PRINTBUFFER, |
2357 | .index = -1, | |
7192f92c | 2358 | .data = &atmel_uart, |
1e6c9c28 AV |
2359 | }; |
2360 | ||
06a7f058 | 2361 | #define ATMEL_CONSOLE_DEVICE (&atmel_console) |
1e6c9c28 | 2362 | |
afefc415 AV |
2363 | /* |
2364 | * Early console initialization (before VM subsystem initialized). | |
2365 | */ | |
7192f92c | 2366 | static int __init atmel_console_init(void) |
1e6c9c28 | 2367 | { |
91f8c2d8 | 2368 | int ret; |
73e2798b | 2369 | if (atmel_default_console_device) { |
0d0a3cc1 | 2370 | struct atmel_uart_data *pdata = |
574de559 | 2371 | dev_get_platdata(&atmel_default_console_device->dev); |
efb8d21b | 2372 | int id = pdata->num; |
4cbf9f48 NF |
2373 | struct atmel_uart_port *port = &atmel_ports[id]; |
2374 | ||
4cbf9f48 NF |
2375 | port->backup_imr = 0; |
2376 | port->uart.line = id; | |
0d0a3cc1 | 2377 | |
4cbf9f48 | 2378 | add_preferred_console(ATMEL_DEVICENAME, id, NULL); |
91f8c2d8 BB |
2379 | ret = atmel_init_port(port, atmel_default_console_device); |
2380 | if (ret) | |
2381 | return ret; | |
7192f92c | 2382 | register_console(&atmel_console); |
afefc415 | 2383 | } |
1e6c9c28 | 2384 | |
1e6c9c28 AV |
2385 | return 0; |
2386 | } | |
b843aa21 | 2387 | |
7192f92c | 2388 | console_initcall(atmel_console_init); |
1e6c9c28 | 2389 | |
afefc415 AV |
2390 | /* |
2391 | * Late console initialization. | |
2392 | */ | |
7192f92c | 2393 | static int __init atmel_late_console_init(void) |
afefc415 | 2394 | { |
b843aa21 RB |
2395 | if (atmel_default_console_device |
2396 | && !(atmel_console.flags & CON_ENABLED)) | |
7192f92c | 2397 | register_console(&atmel_console); |
afefc415 AV |
2398 | |
2399 | return 0; | |
2400 | } | |
b843aa21 | 2401 | |
7192f92c | 2402 | core_initcall(atmel_late_console_init); |
afefc415 | 2403 | |
dfa7f343 HS |
2404 | static inline bool atmel_is_console_port(struct uart_port *port) |
2405 | { | |
2406 | return port->cons && port->cons->index == port->line; | |
2407 | } | |
2408 | ||
1e6c9c28 | 2409 | #else |
7192f92c | 2410 | #define ATMEL_CONSOLE_DEVICE NULL |
dfa7f343 HS |
2411 | |
2412 | static inline bool atmel_is_console_port(struct uart_port *port) | |
2413 | { | |
2414 | return false; | |
2415 | } | |
1e6c9c28 AV |
2416 | #endif |
2417 | ||
7192f92c | 2418 | static struct uart_driver atmel_uart = { |
b843aa21 RB |
2419 | .owner = THIS_MODULE, |
2420 | .driver_name = "atmel_serial", | |
2421 | .dev_name = ATMEL_DEVICENAME, | |
2422 | .major = SERIAL_ATMEL_MAJOR, | |
2423 | .minor = MINOR_START, | |
2424 | .nr = ATMEL_MAX_UART, | |
2425 | .cons = ATMEL_CONSOLE_DEVICE, | |
1e6c9c28 AV |
2426 | }; |
2427 | ||
afefc415 | 2428 | #ifdef CONFIG_PM |
f826caa4 HS |
2429 | static bool atmel_serial_clk_will_stop(void) |
2430 | { | |
2431 | #ifdef CONFIG_ARCH_AT91 | |
2432 | return at91_suspend_entering_slow_clock(); | |
2433 | #else | |
2434 | return false; | |
2435 | #endif | |
2436 | } | |
2437 | ||
b843aa21 RB |
2438 | static int atmel_serial_suspend(struct platform_device *pdev, |
2439 | pm_message_t state) | |
1e6c9c28 | 2440 | { |
afefc415 | 2441 | struct uart_port *port = platform_get_drvdata(pdev); |
c811ab8c | 2442 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
afefc415 | 2443 | |
e1c609ef HS |
2444 | if (atmel_is_console_port(port) && console_suspend_enabled) { |
2445 | /* Drain the TX shifter */ | |
2446 | while (!(UART_GET_CSR(port) & ATMEL_US_TXEMPTY)) | |
2447 | cpu_relax(); | |
2448 | } | |
2449 | ||
f05596db AS |
2450 | /* we can not wake up if we're running on slow clock */ |
2451 | atmel_port->may_wakeup = device_may_wakeup(&pdev->dev); | |
2452 | if (atmel_serial_clk_will_stop()) | |
2453 | device_set_wakeup_enable(&pdev->dev, 0); | |
2454 | ||
2455 | uart_suspend_port(&atmel_uart, port); | |
1e6c9c28 | 2456 | |
afefc415 AV |
2457 | return 0; |
2458 | } | |
1e6c9c28 | 2459 | |
7192f92c | 2460 | static int atmel_serial_resume(struct platform_device *pdev) |
afefc415 AV |
2461 | { |
2462 | struct uart_port *port = platform_get_drvdata(pdev); | |
c811ab8c | 2463 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
1e6c9c28 | 2464 | |
f05596db AS |
2465 | uart_resume_port(&atmel_uart, port); |
2466 | device_set_wakeup_enable(&pdev->dev, atmel_port->may_wakeup); | |
1e6c9c28 AV |
2467 | |
2468 | return 0; | |
2469 | } | |
afefc415 | 2470 | #else |
7192f92c HS |
2471 | #define atmel_serial_suspend NULL |
2472 | #define atmel_serial_resume NULL | |
afefc415 | 2473 | #endif |
1e6c9c28 | 2474 | |
e0b0baad RG |
2475 | static int atmel_init_gpios(struct atmel_uart_port *p, struct device *dev) |
2476 | { | |
ab5e4e41 RG |
2477 | enum mctrl_gpio_idx i; |
2478 | struct gpio_desc *gpiod; | |
2479 | ||
e0b0baad RG |
2480 | p->gpios = mctrl_gpio_init(dev, 0); |
2481 | if (IS_ERR_OR_NULL(p->gpios)) | |
2482 | return -1; | |
2483 | ||
ab5e4e41 RG |
2484 | for (i = 0; i < UART_GPIO_MAX; i++) { |
2485 | gpiod = mctrl_gpio_to_gpiod(p->gpios, i); | |
2486 | if (gpiod && (gpiod_get_direction(gpiod) == GPIOF_DIR_IN)) | |
2487 | p->gpio_irq[i] = gpiod_to_irq(gpiod); | |
2488 | else | |
2489 | p->gpio_irq[i] = -EINVAL; | |
2490 | } | |
2491 | ||
e0b0baad RG |
2492 | return 0; |
2493 | } | |
2494 | ||
9671f099 | 2495 | static int atmel_serial_probe(struct platform_device *pdev) |
1e6c9c28 | 2496 | { |
7192f92c | 2497 | struct atmel_uart_port *port; |
5fbe46b6 | 2498 | struct device_node *np = pdev->dev.of_node; |
574de559 | 2499 | struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev); |
1ecc26bd | 2500 | void *data; |
4cbf9f48 | 2501 | int ret = -ENODEV; |
1e6c9c28 | 2502 | |
9d09daf8 | 2503 | BUILD_BUG_ON(ATMEL_SERIAL_RINGSIZE & (ATMEL_SERIAL_RINGSIZE - 1)); |
1ecc26bd | 2504 | |
5fbe46b6 NF |
2505 | if (np) |
2506 | ret = of_alias_get_id(np, "serial"); | |
2507 | else | |
2508 | if (pdata) | |
2509 | ret = pdata->num; | |
4cbf9f48 NF |
2510 | |
2511 | if (ret < 0) | |
5fbe46b6 | 2512 | /* port id not found in platform data nor device-tree aliases: |
4cbf9f48 | 2513 | * auto-enumerate it */ |
503bded9 | 2514 | ret = find_first_zero_bit(atmel_ports_in_use, ATMEL_MAX_UART); |
4cbf9f48 | 2515 | |
503bded9 | 2516 | if (ret >= ATMEL_MAX_UART) { |
4cbf9f48 NF |
2517 | ret = -ENODEV; |
2518 | goto err; | |
2519 | } | |
2520 | ||
503bded9 | 2521 | if (test_and_set_bit(ret, atmel_ports_in_use)) { |
4cbf9f48 NF |
2522 | /* port already in use */ |
2523 | ret = -EBUSY; | |
2524 | goto err; | |
2525 | } | |
2526 | ||
2527 | port = &atmel_ports[ret]; | |
f05596db | 2528 | port->backup_imr = 0; |
4cbf9f48 | 2529 | port->uart.line = ret; |
e0b0baad RG |
2530 | |
2531 | ret = atmel_init_gpios(port, &pdev->dev); | |
2532 | if (ret < 0) | |
2533 | dev_err(&pdev->dev, "%s", | |
2534 | "Failed to initialize GPIOs. The serial port may not work as expected"); | |
f05596db | 2535 | |
91f8c2d8 BB |
2536 | ret = atmel_init_port(port, pdev); |
2537 | if (ret) | |
2538 | goto err; | |
1e6c9c28 | 2539 | |
64e22ebe | 2540 | if (!atmel_use_pdc_rx(&port->uart)) { |
a6670615 | 2541 | ret = -ENOMEM; |
6433471d HS |
2542 | data = kmalloc(sizeof(struct atmel_uart_char) |
2543 | * ATMEL_SERIAL_RINGSIZE, GFP_KERNEL); | |
a6670615 CC |
2544 | if (!data) |
2545 | goto err_alloc_ring; | |
2546 | port->rx_ring.buf = data; | |
2547 | } | |
1ecc26bd | 2548 | |
7192f92c | 2549 | ret = uart_add_one_port(&atmel_uart, &port->uart); |
dfa7f343 HS |
2550 | if (ret) |
2551 | goto err_add_port; | |
2552 | ||
8da14b5f | 2553 | #ifdef CONFIG_SERIAL_ATMEL_CONSOLE |
06a7f058 DB |
2554 | if (atmel_is_console_port(&port->uart) |
2555 | && ATMEL_CONSOLE_DEVICE->flags & CON_ENABLED) { | |
2556 | /* | |
2557 | * The serial core enabled the clock for us, so undo | |
91f8c2d8 | 2558 | * the clk_prepare_enable() in atmel_console_setup() |
06a7f058 | 2559 | */ |
91f8c2d8 | 2560 | clk_disable_unprepare(port->clk); |
06a7f058 | 2561 | } |
8da14b5f | 2562 | #endif |
06a7f058 | 2563 | |
dfa7f343 HS |
2564 | device_init_wakeup(&pdev->dev, 1); |
2565 | platform_set_drvdata(pdev, port); | |
2566 | ||
5dfbd1d7 CS |
2567 | if (port->rs485.flags & SER_RS485_ENABLED) { |
2568 | UART_PUT_MR(&port->uart, ATMEL_US_USMODE_NORMAL); | |
2569 | UART_PUT_CR(&port->uart, ATMEL_US_RTSEN); | |
2570 | } | |
2571 | ||
055560b0 ES |
2572 | /* |
2573 | * Get port name of usart or uart | |
2574 | */ | |
892db58b | 2575 | atmel_get_ip_name(&port->uart); |
055560b0 | 2576 | |
dfa7f343 HS |
2577 | return 0; |
2578 | ||
2579 | err_add_port: | |
1ecc26bd RB |
2580 | kfree(port->rx_ring.buf); |
2581 | port->rx_ring.buf = NULL; | |
2582 | err_alloc_ring: | |
dfa7f343 | 2583 | if (!atmel_is_console_port(&port->uart)) { |
dfa7f343 HS |
2584 | clk_put(port->clk); |
2585 | port->clk = NULL; | |
afefc415 | 2586 | } |
4cbf9f48 | 2587 | err: |
afefc415 AV |
2588 | return ret; |
2589 | } | |
2590 | ||
ae8d8a14 | 2591 | static int atmel_serial_remove(struct platform_device *pdev) |
afefc415 AV |
2592 | { |
2593 | struct uart_port *port = platform_get_drvdata(pdev); | |
c811ab8c | 2594 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
afefc415 AV |
2595 | int ret = 0; |
2596 | ||
f50c995f MR |
2597 | tasklet_kill(&atmel_port->tasklet); |
2598 | ||
afefc415 | 2599 | device_init_wakeup(&pdev->dev, 0); |
afefc415 | 2600 | |
dfa7f343 HS |
2601 | ret = uart_remove_one_port(&atmel_uart, port); |
2602 | ||
1ecc26bd RB |
2603 | kfree(atmel_port->rx_ring.buf); |
2604 | ||
dfa7f343 HS |
2605 | /* "port" is allocated statically, so we shouldn't free it */ |
2606 | ||
503bded9 | 2607 | clear_bit(port->line, atmel_ports_in_use); |
4cbf9f48 | 2608 | |
dfa7f343 | 2609 | clk_put(atmel_port->clk); |
afefc415 AV |
2610 | |
2611 | return ret; | |
2612 | } | |
2613 | ||
7192f92c HS |
2614 | static struct platform_driver atmel_serial_driver = { |
2615 | .probe = atmel_serial_probe, | |
2d47b716 | 2616 | .remove = atmel_serial_remove, |
7192f92c HS |
2617 | .suspend = atmel_serial_suspend, |
2618 | .resume = atmel_serial_resume, | |
afefc415 | 2619 | .driver = { |
1e8ea802 | 2620 | .name = "atmel_usart", |
afefc415 | 2621 | .owner = THIS_MODULE, |
5fbe46b6 | 2622 | .of_match_table = of_match_ptr(atmel_serial_dt_ids), |
afefc415 AV |
2623 | }, |
2624 | }; | |
2625 | ||
7192f92c | 2626 | static int __init atmel_serial_init(void) |
afefc415 AV |
2627 | { |
2628 | int ret; | |
2629 | ||
7192f92c | 2630 | ret = uart_register_driver(&atmel_uart); |
afefc415 AV |
2631 | if (ret) |
2632 | return ret; | |
2633 | ||
7192f92c | 2634 | ret = platform_driver_register(&atmel_serial_driver); |
afefc415 | 2635 | if (ret) |
7192f92c | 2636 | uart_unregister_driver(&atmel_uart); |
afefc415 AV |
2637 | |
2638 | return ret; | |
2639 | } | |
2640 | ||
7192f92c | 2641 | static void __exit atmel_serial_exit(void) |
afefc415 | 2642 | { |
7192f92c HS |
2643 | platform_driver_unregister(&atmel_serial_driver); |
2644 | uart_unregister_driver(&atmel_uart); | |
1e6c9c28 AV |
2645 | } |
2646 | ||
7192f92c HS |
2647 | module_init(atmel_serial_init); |
2648 | module_exit(atmel_serial_exit); | |
1e6c9c28 AV |
2649 | |
2650 | MODULE_AUTHOR("Rick Bronson"); | |
7192f92c | 2651 | MODULE_DESCRIPTION("Atmel AT91 / AT32 serial port driver"); |
1e6c9c28 | 2652 | MODULE_LICENSE("GPL"); |
e169c139 | 2653 | MODULE_ALIAS("platform:atmel_usart"); |