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serial: core: Claim port mutex for set_ldisc()
[linux-block.git] / drivers / tty / serial / atmel_serial.c
CommitLineData
1e6c9c28 1/*
7192f92c 2 * Driver for Atmel AT91 / AT32 Serial ports
1e6c9c28
AV		 3 * Copyright (C) 2003 Rick Bronson
4 *
5 * Based on drivers/char/serial_sa1100.c, by Deep Blue Solutions Ltd.
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
7 *
a6670615
CC		 8 * DMA support added by Chip Coldwell.
9 *
1e6c9c28
AV		 10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 *
24 */
1e6c9c28
AV		 25#include <linux/module.h>
26#include <linux/tty.h>
27#include <linux/ioport.h>
28#include <linux/slab.h>
29#include <linux/init.h>
30#include <linux/serial.h>
afefc415 31#include <linux/clk.h>
1e6c9c28
AV		 32#include <linux/console.h>
33#include <linux/sysrq.h>
34#include <linux/tty_flip.h>
afefc415 35#include <linux/platform_device.h>
5fbe46b6
NF		 36#include <linux/of.h>
37#include <linux/of_device.h>
354e57f3 38#include <linux/of_gpio.h>
a6670615 39#include <linux/dma-mapping.h>
6b997bab 40#include <linux/dmaengine.h>
93a3ddc2 41#include <linux/atmel_pdc.h>
fa3218d8 42#include <linux/atmel_serial.h>
e8faff73 43#include <linux/uaccess.h>
bcd2360c 44#include <linux/platform_data/atmel.h>
2e68c22f 45#include <linux/timer.h>
354e57f3 46#include <linux/gpio.h>
e0b0baad
RG		 47#include <linux/gpio/consumer.h>
48#include <linux/err.h>
ab5e4e41 49#include <linux/irq.h>
1e6c9c28
AV		 50
51#include <asm/io.h>
f7512e7c 52#include <asm/ioctls.h>
1e6c9c28 53
a6670615
CC		 54#define PDC_BUFFER_SIZE 512
55/* Revisit: We should calculate this based on the actual port settings */
56#define PDC_RX_TIMEOUT (3 * 10) /* 3 bytes */
57
749c4e60 58#if defined(CONFIG_SERIAL_ATMEL_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
1e6c9c28
AV		 59#define SUPPORT_SYSRQ
60#endif
61
62#include <linux/serial_core.h>
63
e0b0baad
RG		 64#include "serial_mctrl_gpio.h"
65
e8faff73
CS		 66static void atmel_start_rx(struct uart_port *port);
67static void atmel_stop_rx(struct uart_port *port);
68
749c4e60 69#ifdef CONFIG_SERIAL_ATMEL_TTYAT
1e6c9c28
AV		 70
71/* Use device name ttyAT, major 204 and minor 154-169. This is necessary if we
72 * should coexist with the 8250 driver, such as if we have an external 16C550
73 * UART. */
7192f92c 74#define SERIAL_ATMEL_MAJOR 204
1e6c9c28 75#define MINOR_START 154
7192f92c 76#define ATMEL_DEVICENAME "ttyAT"
1e6c9c28
AV		 77
78#else
79
80/* Use device name ttyS, major 4, minor 64-68. This is the usual serial port
81 * name, but it is legally reserved for the 8250 driver. */
7192f92c 82#define SERIAL_ATMEL_MAJOR TTY_MAJOR
1e6c9c28 83#define MINOR_START 64
7192f92c 84#define ATMEL_DEVICENAME "ttyS"
1e6c9c28
AV		 85
86#endif
87
7192f92c 88#define ATMEL_ISR_PASS_LIMIT 256
1e6c9c28 89
b843aa21 90/* UART registers. CR is write-only, hence no GET macro */
544fc728
HS		 91#define UART_PUT_CR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_CR)
92#define UART_GET_MR(port) __raw_readl((port)->membase + ATMEL_US_MR)
93#define UART_PUT_MR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_MR)
94#define UART_PUT_IER(port,v) __raw_writel(v, (port)->membase + ATMEL_US_IER)
95#define UART_PUT_IDR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_IDR)
96#define UART_GET_IMR(port) __raw_readl((port)->membase + ATMEL_US_IMR)
97#define UART_GET_CSR(port) __raw_readl((port)->membase + ATMEL_US_CSR)
98#define UART_GET_CHAR(port) __raw_readl((port)->membase + ATMEL_US_RHR)
99#define UART_PUT_CHAR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_THR)
100#define UART_GET_BRGR(port) __raw_readl((port)->membase + ATMEL_US_BRGR)
101#define UART_PUT_BRGR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_BRGR)
102#define UART_PUT_RTOR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_RTOR)
e8faff73 103#define UART_PUT_TTGR(port, v) __raw_writel(v, (port)->membase + ATMEL_US_TTGR)
055560b0 104#define UART_GET_IP_NAME(port) __raw_readl((port)->membase + ATMEL_US_NAME)
731d9cae 105#define UART_GET_IP_VERSION(port) __raw_readl((port)->membase + ATMEL_US_VERSION)
544fc728 106
1e6c9c28 107 /* PDC registers */
544fc728
HS		 108#define UART_PUT_PTCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_PTCR)
109#define UART_GET_PTSR(port) __raw_readl((port)->membase + ATMEL_PDC_PTSR)
110
111#define UART_PUT_RPR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RPR)
112#define UART_GET_RPR(port) __raw_readl((port)->membase + ATMEL_PDC_RPR)
113#define UART_PUT_RCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RCR)
114#define UART_PUT_RNPR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RNPR)
115#define UART_PUT_RNCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RNCR)
116
117#define UART_PUT_TPR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_TPR)
118#define UART_PUT_TCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_TCR)
39d4c922 119#define UART_GET_TCR(port) __raw_readl((port)->membase + ATMEL_PDC_TCR)
1e6c9c28 120
a6670615
CC		 121struct atmel_dma_buffer {
122 unsigned char *buf;
123 dma_addr_t dma_addr;
124 unsigned int dma_size;
125 unsigned int ofs;
126};
127
1ecc26bd
RB		 128struct atmel_uart_char {
129 u16 status;
130 u16 ch;
131};
132
133#define ATMEL_SERIAL_RINGSIZE 1024
134
afefc415
AV		 135/*
136 * We wrap our port structure around the generic uart_port.
137 */
7192f92c 138struct atmel_uart_port {
afefc415
AV		 139 struct uart_port uart; /* uart */
140 struct clk *clk; /* uart clock */
f05596db
AS		 141 int may_wakeup; /* cached value of device_may_wakeup for times we need to disable it */
142 u32 backup_imr; /* IMR saved during suspend */
9e6077bd 143 int break_active; /* break being received */
1ecc26bd 144
34df42f5 145 bool use_dma_rx; /* enable DMA receiver */
64e22ebe 146 bool use_pdc_rx; /* enable PDC receiver */
a6670615
CC		 147 short pdc_rx_idx; /* current PDC RX buffer */
148 struct atmel_dma_buffer pdc_rx[2]; /* PDC receier */
149
08f738be 150 bool use_dma_tx; /* enable DMA transmitter */
64e22ebe 151 bool use_pdc_tx; /* enable PDC transmitter */
a6670615
CC		 152 struct atmel_dma_buffer pdc_tx; /* PDC transmitter */
153
08f738be 154 spinlock_t lock_tx; /* port lock */
34df42f5 155 spinlock_t lock_rx; /* port lock */
08f738be 156 struct dma_chan *chan_tx;
34df42f5 157 struct dma_chan *chan_rx;
08f738be 158 struct dma_async_tx_descriptor *desc_tx;
34df42f5 159 struct dma_async_tx_descriptor *desc_rx;
08f738be 160 dma_cookie_t cookie_tx;
34df42f5 161 dma_cookie_t cookie_rx;
08f738be 162 struct scatterlist sg_tx;
34df42f5 163 struct scatterlist sg_rx;
1ecc26bd
RB		 164 struct tasklet_struct tasklet;
165 unsigned int irq_status;
166 unsigned int irq_status_prev;
167
168 struct circ_buf rx_ring;
e8faff73
CS		 169
170 struct serial_rs485 rs485; /* rs485 settings */
e0b0baad 171 struct mctrl_gpios *gpios;
ab5e4e41 172 int gpio_irq[UART_GPIO_MAX];
e8faff73 173 unsigned int tx_done_mask;
ab5e4e41 174 bool ms_irq_enabled;
055560b0 175 bool is_usart; /* usart or uart */
2e68c22f 176 struct timer_list uart_timer; /* uart timer */
a930e528
ES		 177 int (*prepare_rx)(struct uart_port *port);
178 int (*prepare_tx)(struct uart_port *port);
179 void (*schedule_rx)(struct uart_port *port);
180 void (*schedule_tx)(struct uart_port *port);
181 void (*release_rx)(struct uart_port *port);
182 void (*release_tx)(struct uart_port *port);
afefc415
AV		 183};
184
7192f92c 185static struct atmel_uart_port atmel_ports[ATMEL_MAX_UART];
503bded9 186static DECLARE_BITMAP(atmel_ports_in_use, ATMEL_MAX_UART);
afefc415 187
1e6c9c28 188#ifdef SUPPORT_SYSRQ
7192f92c 189static struct console atmel_console;
1e6c9c28
AV		 190#endif
191
5fbe46b6
NF		 192#if defined(CONFIG_OF)
193static const struct of_device_id atmel_serial_dt_ids[] = {
194 { .compatible = "atmel,at91rm9200-usart" },
195 { .compatible = "atmel,at91sam9260-usart" },
196 { /* sentinel */ }
197};
198
199MODULE_DEVICE_TABLE(of, atmel_serial_dt_ids);
200#endif
201
c811ab8c
HS		 202static inline struct atmel_uart_port *
203to_atmel_uart_port(struct uart_port *uart)
204{
205 return container_of(uart, struct atmel_uart_port, uart);
206}
207
a6670615 208#ifdef CONFIG_SERIAL_ATMEL_PDC
64e22ebe 209static bool atmel_use_pdc_rx(struct uart_port *port)
a6670615 210{
c811ab8c 211 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
a6670615 212
64e22ebe 213 return atmel_port->use_pdc_rx;
a6670615
CC		 214}
215
64e22ebe 216static bool atmel_use_pdc_tx(struct uart_port *port)
a6670615 217{
c811ab8c 218 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
a6670615 219
64e22ebe 220 return atmel_port->use_pdc_tx;
a6670615
CC		 221}
222#else
64e22ebe 223static bool atmel_use_pdc_rx(struct uart_port *port)
a6670615
CC		 224{
225 return false;
226}
227
64e22ebe 228static bool atmel_use_pdc_tx(struct uart_port *port)
a6670615
CC		 229{
230 return false;
231}
232#endif
233
08f738be
ES		 234static bool atmel_use_dma_tx(struct uart_port *port)
235{
236 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
237
238 return atmel_port->use_dma_tx;
239}
240
34df42f5
ES		 241static bool atmel_use_dma_rx(struct uart_port *port)
242{
243 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
244
245 return atmel_port->use_dma_rx;
246}
247
e0b0baad
RG		 248static unsigned int atmel_get_lines_status(struct uart_port *port)
249{
250 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
251 unsigned int status, ret = 0;
252
253 status = UART_GET_CSR(port);
254
255 mctrl_gpio_get(atmel_port->gpios, &ret);
256
257 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios,
258 UART_GPIO_CTS))) {
259 if (ret & TIOCM_CTS)
260 status &= ~ATMEL_US_CTS;
261 else
262 status |= ATMEL_US_CTS;
263 }
264
265 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios,
266 UART_GPIO_DSR))) {
267 if (ret & TIOCM_DSR)
268 status &= ~ATMEL_US_DSR;
269 else
270 status |= ATMEL_US_DSR;
271 }
272
273 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios,
274 UART_GPIO_RI))) {
275 if (ret & TIOCM_RI)
276 status &= ~ATMEL_US_RI;
277 else
278 status |= ATMEL_US_RI;
279 }
280
281 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios,
282 UART_GPIO_DCD))) {
283 if (ret & TIOCM_CD)
284 status &= ~ATMEL_US_DCD;
285 else
286 status |= ATMEL_US_DCD;
287 }
288
289 return status;
290}
291
e8faff73
CS		 292/* Enable or disable the rs485 support */
293void atmel_config_rs485(struct uart_port *port, struct serial_rs485 *rs485conf)
294{
295 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
296 unsigned int mode;
dbf1115d 297 unsigned long flags;
e8faff73 298
dbf1115d 299 spin_lock_irqsave(&port->lock, flags);
e8faff73
CS		 300
301 /* Disable interrupts */
302 UART_PUT_IDR(port, atmel_port->tx_done_mask);
303
304 mode = UART_GET_MR(port);
305
306 /* Resetting serial mode to RS232 (0x0) */
307 mode &= ~ATMEL_US_USMODE;
308
309 atmel_port->rs485 = *rs485conf;
310
311 if (rs485conf->flags & SER_RS485_ENABLED) {
312 dev_dbg(port->dev, "Setting UART to RS485\n");
313 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY;
93f3350c 314 if ((rs485conf->delay_rts_after_send) > 0)
1b633184 315 UART_PUT_TTGR(port, rs485conf->delay_rts_after_send);
e8faff73
CS		 316 mode |= ATMEL_US_USMODE_RS485;
317 } else {
318 dev_dbg(port->dev, "Setting UART to RS232\n");
64e22ebe 319 if (atmel_use_pdc_tx(port))
e8faff73
CS		 320 atmel_port->tx_done_mask = ATMEL_US_ENDTX |
321 ATMEL_US_TXBUFE;
322 else
323 atmel_port->tx_done_mask = ATMEL_US_TXRDY;
324 }
325 UART_PUT_MR(port, mode);
326
327 /* Enable interrupts */
328 UART_PUT_IER(port, atmel_port->tx_done_mask);
329
dbf1115d 330 spin_unlock_irqrestore(&port->lock, flags);
e8faff73
CS		 331
332}
333
1e6c9c28
AV		 334/*
335 * Return TIOCSER_TEMT when transmitter FIFO and Shift register is empty.
336 */
7192f92c 337static u_int atmel_tx_empty(struct uart_port *port)
1e6c9c28 338{
7192f92c 339 return (UART_GET_CSR(port) & ATMEL_US_TXEMPTY) ? TIOCSER_TEMT : 0;
1e6c9c28
AV		 340}
341
342/*
343 * Set state of the modem control output lines
344 */
7192f92c 345static void atmel_set_mctrl(struct uart_port *port, u_int mctrl)
1e6c9c28
AV		 346{
347 unsigned int control = 0;
afefc415 348 unsigned int mode;
e8faff73 349 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1e6c9c28 350
1e6c9c28 351 if (mctrl & TIOCM_RTS)
7192f92c 352 control |= ATMEL_US_RTSEN;
1e6c9c28 353 else
7192f92c 354 control |= ATMEL_US_RTSDIS;
1e6c9c28
AV		 355
356 if (mctrl & TIOCM_DTR)
7192f92c 357 control |= ATMEL_US_DTREN;
1e6c9c28 358 else
7192f92c 359 control |= ATMEL_US_DTRDIS;
1e6c9c28 360
afefc415
AV		 361 UART_PUT_CR(port, control);
362
e0b0baad
RG		 363 mctrl_gpio_set(atmel_port->gpios, mctrl);
364
afefc415 365 /* Local loopback mode? */
7192f92c 366 mode = UART_GET_MR(port) & ~ATMEL_US_CHMODE;
afefc415 367 if (mctrl & TIOCM_LOOP)
7192f92c 368 mode |= ATMEL_US_CHMODE_LOC_LOOP;
afefc415 369 else
7192f92c 370 mode |= ATMEL_US_CHMODE_NORMAL;
e8faff73
CS		 371
372 /* Resetting serial mode to RS232 (0x0) */
373 mode &= ~ATMEL_US_USMODE;
374
375 if (atmel_port->rs485.flags & SER_RS485_ENABLED) {
376 dev_dbg(port->dev, "Setting UART to RS485\n");
93f3350c 377 if ((atmel_port->rs485.delay_rts_after_send) > 0)
1b633184
CS		 378 UART_PUT_TTGR(port,
379 atmel_port->rs485.delay_rts_after_send);
e8faff73
CS		 380 mode |= ATMEL_US_USMODE_RS485;
381 } else {
382 dev_dbg(port->dev, "Setting UART to RS232\n");
383 }
afefc415 384 UART_PUT_MR(port, mode);
1e6c9c28
AV		 385}
386
387/*
388 * Get state of the modem control input lines
389 */
7192f92c 390static u_int atmel_get_mctrl(struct uart_port *port)
1e6c9c28 391{
e0b0baad
RG		 392 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
393 unsigned int ret = 0, status;
1e6c9c28
AV		 394
395 status = UART_GET_CSR(port);
396
397 /*
398 * The control signals are active low.
399 */
7192f92c 400 if (!(status & ATMEL_US_DCD))
1e6c9c28 401 ret |= TIOCM_CD;
7192f92c 402 if (!(status & ATMEL_US_CTS))
1e6c9c28 403 ret |= TIOCM_CTS;
7192f92c 404 if (!(status & ATMEL_US_DSR))
1e6c9c28 405 ret |= TIOCM_DSR;
7192f92c 406 if (!(status & ATMEL_US_RI))
1e6c9c28
AV		 407 ret |= TIOCM_RI;
408
e0b0baad 409 return mctrl_gpio_get(atmel_port->gpios, &ret);
1e6c9c28
AV		 410}
411
412/*
413 * Stop transmitting.
414 */
7192f92c 415static void atmel_stop_tx(struct uart_port *port)
1e6c9c28 416{
e8faff73
CS		 417 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
418
64e22ebe 419 if (atmel_use_pdc_tx(port)) {
a6670615
CC		 420 /* disable PDC transmit */
421 UART_PUT_PTCR(port, ATMEL_PDC_TXTDIS);
e8faff73
CS		 422 }
423 /* Disable interrupts */
424 UART_PUT_IDR(port, atmel_port->tx_done_mask);
425
83cac9f3
BR		 426 if ((atmel_port->rs485.flags & SER_RS485_ENABLED) &&
427 !(atmel_port->rs485.flags & SER_RS485_RX_DURING_TX))
e8faff73 428 atmel_start_rx(port);
1e6c9c28
AV		 429}
430
431/*
432 * Start transmitting.
433 */
7192f92c 434static void atmel_start_tx(struct uart_port *port)
1e6c9c28 435{
e8faff73
CS		 436 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
437
64e22ebe 438 if (atmel_use_pdc_tx(port)) {
a6670615
CC		 439 if (UART_GET_PTSR(port) & ATMEL_PDC_TXTEN)
440 /* The transmitter is already running. Yes, we
441 really need this.*/
442 return;
443
83cac9f3
BR		 444 if ((atmel_port->rs485.flags & SER_RS485_ENABLED) &&
445 !(atmel_port->rs485.flags & SER_RS485_RX_DURING_TX))
e8faff73
CS		 446 atmel_stop_rx(port);
447
a6670615
CC		 448 /* re-enable PDC transmit */
449 UART_PUT_PTCR(port, ATMEL_PDC_TXTEN);
e8faff73
CS		 450 }
451 /* Enable interrupts */
452 UART_PUT_IER(port, atmel_port->tx_done_mask);
453}
454
455/*
456 * start receiving - port is in process of being opened.
457 */
458static void atmel_start_rx(struct uart_port *port)
459{
460 UART_PUT_CR(port, ATMEL_US_RSTSTA); /* reset status and receiver */
461
57c36868
SG		 462 UART_PUT_CR(port, ATMEL_US_RXEN);
463
64e22ebe 464 if (atmel_use_pdc_rx(port)) {
e8faff73
CS		 465 /* enable PDC controller */
466 UART_PUT_IER(port, ATMEL_US_ENDRX | ATMEL_US_TIMEOUT |
467 port->read_status_mask);
468 UART_PUT_PTCR(port, ATMEL_PDC_RXTEN);
469 } else {
470 UART_PUT_IER(port, ATMEL_US_RXRDY);
471 }
1e6c9c28
AV		 472}
473
474/*
475 * Stop receiving - port is in process of being closed.
476 */
7192f92c 477static void atmel_stop_rx(struct uart_port *port)
1e6c9c28 478{
57c36868
SG		 479 UART_PUT_CR(port, ATMEL_US_RXDIS);
480
64e22ebe 481 if (atmel_use_pdc_rx(port)) {
a6670615
CC		 482 /* disable PDC receive */
483 UART_PUT_PTCR(port, ATMEL_PDC_RXTDIS);
e8faff73
CS		 484 UART_PUT_IDR(port, ATMEL_US_ENDRX | ATMEL_US_TIMEOUT |
485 port->read_status_mask);
486 } else {
a6670615 487 UART_PUT_IDR(port, ATMEL_US_RXRDY);
e8faff73 488 }
1e6c9c28
AV		 489}
490
491/*
492 * Enable modem status interrupts
493 */
7192f92c 494static void atmel_enable_ms(struct uart_port *port)
1e6c9c28 495{
ab5e4e41
RG		 496 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
497 uint32_t ier = 0;
498
499 /*
500 * Interrupt should not be enabled twice
501 */
502 if (atmel_port->ms_irq_enabled)
503 return;
504
505 atmel_port->ms_irq_enabled = true;
506
507 if (atmel_port->gpio_irq[UART_GPIO_CTS] >= 0)
508 enable_irq(atmel_port->gpio_irq[UART_GPIO_CTS]);
509 else
510 ier |= ATMEL_US_CTSIC;
511
512 if (atmel_port->gpio_irq[UART_GPIO_DSR] >= 0)
513 enable_irq(atmel_port->gpio_irq[UART_GPIO_DSR]);
514 else
515 ier |= ATMEL_US_DSRIC;
516
517 if (atmel_port->gpio_irq[UART_GPIO_RI] >= 0)
518 enable_irq(atmel_port->gpio_irq[UART_GPIO_RI]);
519 else
520 ier |= ATMEL_US_RIIC;
521
522 if (atmel_port->gpio_irq[UART_GPIO_DCD] >= 0)
523 enable_irq(atmel_port->gpio_irq[UART_GPIO_DCD]);
524 else
525 ier |= ATMEL_US_DCDIC;
526
527 UART_PUT_IER(port, ier);
1e6c9c28
AV		 528}
529
35b675b9
RG		 530/*
531 * Disable modem status interrupts
532 */
533static void atmel_disable_ms(struct uart_port *port)
534{
535 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
536 uint32_t idr = 0;
537
538 /*
539 * Interrupt should not be disabled twice
540 */
541 if (!atmel_port->ms_irq_enabled)
542 return;
543
544 atmel_port->ms_irq_enabled = false;
545
546 if (atmel_port->gpio_irq[UART_GPIO_CTS] >= 0)
547 disable_irq(atmel_port->gpio_irq[UART_GPIO_CTS]);
548 else
549 idr |= ATMEL_US_CTSIC;
550
551 if (atmel_port->gpio_irq[UART_GPIO_DSR] >= 0)
552 disable_irq(atmel_port->gpio_irq[UART_GPIO_DSR]);
553 else
554 idr |= ATMEL_US_DSRIC;
555
556 if (atmel_port->gpio_irq[UART_GPIO_RI] >= 0)
557 disable_irq(atmel_port->gpio_irq[UART_GPIO_RI]);
558 else
559 idr |= ATMEL_US_RIIC;
560
561 if (atmel_port->gpio_irq[UART_GPIO_DCD] >= 0)
562 disable_irq(atmel_port->gpio_irq[UART_GPIO_DCD]);
563 else
564 idr |= ATMEL_US_DCDIC;
565
566 UART_PUT_IDR(port, idr);
567}
568
1e6c9c28
AV		 569/*
570 * Control the transmission of a break signal
571 */
7192f92c 572static void atmel_break_ctl(struct uart_port *port, int break_state)
1e6c9c28
AV		 573{
574 if (break_state != 0)
7192f92c 575 UART_PUT_CR(port, ATMEL_US_STTBRK); /* start break */
1e6c9c28 576 else
7192f92c 577 UART_PUT_CR(port, ATMEL_US_STPBRK); /* stop break */
1e6c9c28
AV		 578}
579
1ecc26bd
RB		 580/*
581 * Stores the incoming character in the ring buffer
582 */
583static void
584atmel_buffer_rx_char(struct uart_port *port, unsigned int status,
585 unsigned int ch)
586{
c811ab8c 587 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1ecc26bd
RB		 588 struct circ_buf *ring = &atmel_port->rx_ring;
589 struct atmel_uart_char *c;
590
591 if (!CIRC_SPACE(ring->head, ring->tail, ATMEL_SERIAL_RINGSIZE))
592 /* Buffer overflow, ignore char */
593 return;
594
595 c = &((struct atmel_uart_char *)ring->buf)[ring->head];
596 c->status = status;
597 c->ch = ch;
598
599 /* Make sure the character is stored before we update head. */
600 smp_wmb();
601
602 ring->head = (ring->head + 1) & (ATMEL_SERIAL_RINGSIZE - 1);
603}
604
a6670615
CC		 605/*
606 * Deal with parity, framing and overrun errors.
607 */
608static void atmel_pdc_rxerr(struct uart_port *port, unsigned int status)
609{
610 /* clear error */
611 UART_PUT_CR(port, ATMEL_US_RSTSTA);
612
613 if (status & ATMEL_US_RXBRK) {
614 /* ignore side-effect */
615 status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME);
616 port->icount.brk++;
617 }
618 if (status & ATMEL_US_PARE)
619 port->icount.parity++;
620 if (status & ATMEL_US_FRAME)
621 port->icount.frame++;
622 if (status & ATMEL_US_OVRE)
623 port->icount.overrun++;
624}
625
1e6c9c28
AV		 626/*
627 * Characters received (called from interrupt handler)
628 */
7d12e780 629static void atmel_rx_chars(struct uart_port *port)
1e6c9c28 630{
c811ab8c 631 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1ecc26bd 632 unsigned int status, ch;
1e6c9c28 633
afefc415 634 status = UART_GET_CSR(port);
7192f92c 635 while (status & ATMEL_US_RXRDY) {
1e6c9c28
AV		 636 ch = UART_GET_CHAR(port);
637
1e6c9c28
AV		 638 /*
639 * note that the error handling code is
640 * out of the main execution path
641 */
9e6077bd
HS		 642 if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME
643 | ATMEL_US_OVRE | ATMEL_US_RXBRK)
644 || atmel_port->break_active)) {
1ecc26bd 645
b843aa21
RB		 646 /* clear error */
647 UART_PUT_CR(port, ATMEL_US_RSTSTA);
1ecc26bd 648
9e6077bd
HS		 649 if (status & ATMEL_US_RXBRK
650 && !atmel_port->break_active) {
9e6077bd
HS		 651 atmel_port->break_active = 1;
652 UART_PUT_IER(port, ATMEL_US_RXBRK);
9e6077bd
HS		 653 } else {
654 /*
655 * This is either the end-of-break
656 * condition or we've received at
657 * least one character without RXBRK
658 * being set. In both cases, the next
659 * RXBRK will indicate start-of-break.
660 */
661 UART_PUT_IDR(port, ATMEL_US_RXBRK);
662 status &= ~ATMEL_US_RXBRK;
663 atmel_port->break_active = 0;
afefc415 664 }
1e6c9c28
AV		 665 }
666
1ecc26bd 667 atmel_buffer_rx_char(port, status, ch);
afefc415 668 status = UART_GET_CSR(port);
1e6c9c28
AV		 669 }
670
1ecc26bd 671 tasklet_schedule(&atmel_port->tasklet);
1e6c9c28
AV		 672}
673
674/*
1ecc26bd
RB		 675 * Transmit characters (called from tasklet with TXRDY interrupt
676 * disabled)
1e6c9c28 677 */
7192f92c 678static void atmel_tx_chars(struct uart_port *port)
1e6c9c28 679{
ebd2c8f6 680 struct circ_buf *xmit = &port->state->xmit;
e8faff73 681 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1e6c9c28 682
e8faff73 683 if (port->x_char && UART_GET_CSR(port) & atmel_port->tx_done_mask) {
1e6c9c28
AV		 684 UART_PUT_CHAR(port, port->x_char);
685 port->icount.tx++;
686 port->x_char = 0;
1e6c9c28 687 }
1ecc26bd 688 if (uart_circ_empty(xmit) || uart_tx_stopped(port))
1e6c9c28 689 return;
1e6c9c28 690
e8faff73 691 while (UART_GET_CSR(port) & atmel_port->tx_done_mask) {
1e6c9c28
AV		 692 UART_PUT_CHAR(port, xmit->buf[xmit->tail]);
693 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
694 port->icount.tx++;
695 if (uart_circ_empty(xmit))
696 break;
697 }
698
699 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
700 uart_write_wakeup(port);
701
1ecc26bd 702 if (!uart_circ_empty(xmit))
e8faff73
CS		 703 /* Enable interrupts */
704 UART_PUT_IER(port, atmel_port->tx_done_mask);
1e6c9c28
AV		 705}
706
08f738be
ES		 707static void atmel_complete_tx_dma(void *arg)
708{
709 struct atmel_uart_port *atmel_port = arg;
710 struct uart_port *port = &atmel_port->uart;
711 struct circ_buf *xmit = &port->state->xmit;
712 struct dma_chan *chan = atmel_port->chan_tx;
713 unsigned long flags;
714
715 spin_lock_irqsave(&port->lock, flags);
716
717 if (chan)
718 dmaengine_terminate_all(chan);
719 xmit->tail += sg_dma_len(&atmel_port->sg_tx);
720 xmit->tail &= UART_XMIT_SIZE - 1;
721
722 port->icount.tx += sg_dma_len(&atmel_port->sg_tx);
723
724 spin_lock_irq(&atmel_port->lock_tx);
725 async_tx_ack(atmel_port->desc_tx);
726 atmel_port->cookie_tx = -EINVAL;
727 atmel_port->desc_tx = NULL;
728 spin_unlock_irq(&atmel_port->lock_tx);
729
730 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
731 uart_write_wakeup(port);
732
733 /* Do we really need this? */
734 if (!uart_circ_empty(xmit))
735 tasklet_schedule(&atmel_port->tasklet);
736
737 spin_unlock_irqrestore(&port->lock, flags);
738}
739
740static void atmel_release_tx_dma(struct uart_port *port)
741{
742 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
743 struct dma_chan *chan = atmel_port->chan_tx;
744
745 if (chan) {
746 dmaengine_terminate_all(chan);
747 dma_release_channel(chan);
748 dma_unmap_sg(port->dev, &atmel_port->sg_tx, 1,
48479148 749 DMA_TO_DEVICE);
08f738be
ES		 750 }
751
752 atmel_port->desc_tx = NULL;
753 atmel_port->chan_tx = NULL;
754 atmel_port->cookie_tx = -EINVAL;
755}
756
757/*
758 * Called from tasklet with TXRDY interrupt is disabled.
759 */
760static void atmel_tx_dma(struct uart_port *port)
761{
762 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
763 struct circ_buf *xmit = &port->state->xmit;
764 struct dma_chan *chan = atmel_port->chan_tx;
765 struct dma_async_tx_descriptor *desc;
766 struct scatterlist *sg = &atmel_port->sg_tx;
767
768 /* Make sure we have an idle channel */
769 if (atmel_port->desc_tx != NULL)
770 return;
771
772 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) {
773 /*
774 * DMA is idle now.
775 * Port xmit buffer is already mapped,
776 * and it is one page... Just adjust
777 * offsets and lengths. Since it is a circular buffer,
778 * we have to transmit till the end, and then the rest.
779 * Take the port lock to get a
780 * consistent xmit buffer state.
781 */
782 sg->offset = xmit->tail & (UART_XMIT_SIZE - 1);
783 sg_dma_address(sg) = (sg_dma_address(sg) &
784 ~(UART_XMIT_SIZE - 1))
785 + sg->offset;
786 sg_dma_len(sg) = CIRC_CNT_TO_END(xmit->head,
787 xmit->tail,
788 UART_XMIT_SIZE);
789 BUG_ON(!sg_dma_len(sg));
790
791 desc = dmaengine_prep_slave_sg(chan,
792 sg,
793 1,
794 DMA_MEM_TO_DEV,
795 DMA_PREP_INTERRUPT |
796 DMA_CTRL_ACK);
797 if (!desc) {
798 dev_err(port->dev, "Failed to send via dma!\n");
799 return;
800 }
801
802 dma_sync_sg_for_device(port->dev, sg, 1, DMA_MEM_TO_DEV);
803
804 atmel_port->desc_tx = desc;
805 desc->callback = atmel_complete_tx_dma;
806 desc->callback_param = atmel_port;
807 atmel_port->cookie_tx = dmaengine_submit(desc);
808
809 } else {
810 if (atmel_port->rs485.flags & SER_RS485_ENABLED) {
811 /* DMA done, stop TX, start RX for RS485 */
812 atmel_start_rx(port);
813 }
814 }
815
816 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
817 uart_write_wakeup(port);
818}
819
820static int atmel_prepare_tx_dma(struct uart_port *port)
821{
822 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
823 dma_cap_mask_t mask;
824 struct dma_slave_config config;
825 int ret, nent;
826
827 dma_cap_zero(mask);
828 dma_cap_set(DMA_SLAVE, mask);
829
830 atmel_port->chan_tx = dma_request_slave_channel(port->dev, "tx");
831 if (atmel_port->chan_tx == NULL)
832 goto chan_err;
833 dev_info(port->dev, "using %s for tx DMA transfers\n",
834 dma_chan_name(atmel_port->chan_tx));
835
836 spin_lock_init(&atmel_port->lock_tx);
837 sg_init_table(&atmel_port->sg_tx, 1);
838 /* UART circular tx buffer is an aligned page. */
839 BUG_ON((int)port->state->xmit.buf & ~PAGE_MASK);
840 sg_set_page(&atmel_port->sg_tx,
841 virt_to_page(port->state->xmit.buf),
842 UART_XMIT_SIZE,
843 (int)port->state->xmit.buf & ~PAGE_MASK);
844 nent = dma_map_sg(port->dev,
845 &atmel_port->sg_tx,
846 1,
48479148 847 DMA_TO_DEVICE);
08f738be
ES		 848
849 if (!nent) {
850 dev_dbg(port->dev, "need to release resource of dma\n");
851 goto chan_err;
852 } else {
853 dev_dbg(port->dev, "%s: mapped %d@%p to %x\n", __func__,
854 sg_dma_len(&atmel_port->sg_tx),
855 port->state->xmit.buf,
856 sg_dma_address(&atmel_port->sg_tx));
857 }
858
859 /* Configure the slave DMA */
860 memset(&config, 0, sizeof(config));
861 config.direction = DMA_MEM_TO_DEV;
862 config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
863 config.dst_addr = port->mapbase + ATMEL_US_THR;
864
5483c10e
MR		 865 ret = dmaengine_slave_config(atmel_port->chan_tx,
866 &config);
08f738be
ES		 867 if (ret) {
868 dev_err(port->dev, "DMA tx slave configuration failed\n");
869 goto chan_err;
870 }
871
872 return 0;
873
874chan_err:
875 dev_err(port->dev, "TX channel not available, switch to pio\n");
876 atmel_port->use_dma_tx = 0;
877 if (atmel_port->chan_tx)
878 atmel_release_tx_dma(port);
879 return -EINVAL;
880}
881
34df42f5
ES		 882static void atmel_complete_rx_dma(void *arg)
883{
884 struct uart_port *port = arg;
885 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
886
887 tasklet_schedule(&atmel_port->tasklet);
888}
889
890static void atmel_release_rx_dma(struct uart_port *port)
891{
892 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
893 struct dma_chan *chan = atmel_port->chan_rx;
894
895 if (chan) {
896 dmaengine_terminate_all(chan);
897 dma_release_channel(chan);
898 dma_unmap_sg(port->dev, &atmel_port->sg_rx, 1,
48479148 899 DMA_FROM_DEVICE);
34df42f5
ES		 900 }
901
902 atmel_port->desc_rx = NULL;
903 atmel_port->chan_rx = NULL;
904 atmel_port->cookie_rx = -EINVAL;
905}
906
907static void atmel_rx_from_dma(struct uart_port *port)
908{
909 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
66f37aaf 910 struct tty_port *tport = &port->state->port;
34df42f5
ES		 911 struct circ_buf *ring = &atmel_port->rx_ring;
912 struct dma_chan *chan = atmel_port->chan_rx;
913 struct dma_tx_state state;
914 enum dma_status dmastat;
66f37aaf 915 size_t count;
34df42f5
ES		 916
917
918 /* Reset the UART timeout early so that we don't miss one */
919 UART_PUT_CR(port, ATMEL_US_STTTO);
920 dmastat = dmaengine_tx_status(chan,
921 atmel_port->cookie_rx,
922 &state);
923 /* Restart a new tasklet if DMA status is error */
924 if (dmastat == DMA_ERROR) {
925 dev_dbg(port->dev, "Get residue error, restart tasklet\n");
926 UART_PUT_IER(port, ATMEL_US_TIMEOUT);
927 tasklet_schedule(&atmel_port->tasklet);
928 return;
929 }
34df42f5 930
66f37aaf
CP		 931 /* CPU claims ownership of RX DMA buffer */
932 dma_sync_sg_for_cpu(port->dev,
933 &atmel_port->sg_rx,
934 1,
935 DMA_DEV_TO_MEM);
936
937 /*
938 * ring->head points to the end of data already written by the DMA.
939 * ring->tail points to the beginning of data to be read by the
940 * framework.
941 * The current transfer size should not be larger than the dma buffer
942 * length.
943 */
944 ring->head = sg_dma_len(&atmel_port->sg_rx) - state.residue;
945 BUG_ON(ring->head > sg_dma_len(&atmel_port->sg_rx));
34df42f5 946 /*
66f37aaf
CP		 947 * At this point ring->head may point to the first byte right after the
948 * last byte of the dma buffer:
949 * 0 <= ring->head <= sg_dma_len(&atmel_port->sg_rx)
950 *
951 * However ring->tail must always points inside the dma buffer:
952 * 0 <= ring->tail <= sg_dma_len(&atmel_port->sg_rx) - 1
953 *
954 * Since we use a ring buffer, we have to handle the case
955 * where head is lower than tail. In such a case, we first read from
956 * tail to the end of the buffer then reset tail.
34df42f5 957 */
66f37aaf
CP		 958 if (ring->head < ring->tail) {
959 count = sg_dma_len(&atmel_port->sg_rx) - ring->tail;
34df42f5 960
66f37aaf
CP		 961 tty_insert_flip_string(tport, ring->buf + ring->tail, count);
962 ring->tail = 0;
963 port->icount.rx += count;
964 }
34df42f5 965
66f37aaf
CP		 966 /* Finally we read data from tail to head */
967 if (ring->tail < ring->head) {
968 count = ring->head - ring->tail;
34df42f5 969
66f37aaf
CP		 970 tty_insert_flip_string(tport, ring->buf + ring->tail, count);
971 /* Wrap ring->head if needed */
972 if (ring->head >= sg_dma_len(&atmel_port->sg_rx))
973 ring->head = 0;
974 ring->tail = ring->head;
34df42f5
ES		 975 port->icount.rx += count;
976 }
977
66f37aaf
CP		 978 /* USART retreives ownership of RX DMA buffer */
979 dma_sync_sg_for_device(port->dev,
980 &atmel_port->sg_rx,
981 1,
982 DMA_DEV_TO_MEM);
983
984 /*
985 * Drop the lock here since it might end up calling
986 * uart_start(), which takes the lock.
987 */
988 spin_unlock(&port->lock);
989 tty_flip_buffer_push(tport);
990 spin_lock(&port->lock);
991
34df42f5
ES		 992 UART_PUT_IER(port, ATMEL_US_TIMEOUT);
993}
994
995static int atmel_prepare_rx_dma(struct uart_port *port)
996{
997 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
998 struct dma_async_tx_descriptor *desc;
999 dma_cap_mask_t mask;
1000 struct dma_slave_config config;
1001 struct circ_buf *ring;
1002 int ret, nent;
1003
1004 ring = &atmel_port->rx_ring;
1005
1006 dma_cap_zero(mask);
1007 dma_cap_set(DMA_CYCLIC, mask);
1008
1009 atmel_port->chan_rx = dma_request_slave_channel(port->dev, "rx");
1010 if (atmel_port->chan_rx == NULL)
1011 goto chan_err;
1012 dev_info(port->dev, "using %s for rx DMA transfers\n",
1013 dma_chan_name(atmel_port->chan_rx));
1014
1015 spin_lock_init(&atmel_port->lock_rx);
1016 sg_init_table(&atmel_port->sg_rx, 1);
1017 /* UART circular rx buffer is an aligned page. */
1018 BUG_ON((int)port->state->xmit.buf & ~PAGE_MASK);
1019 sg_set_page(&atmel_port->sg_rx,
1020 virt_to_page(ring->buf),
1021 ATMEL_SERIAL_RINGSIZE,
1022 (int)ring->buf & ~PAGE_MASK);
1023 nent = dma_map_sg(port->dev,
1024 &atmel_port->sg_rx,
1025 1,
48479148 1026 DMA_FROM_DEVICE);
34df42f5
ES		 1027
1028 if (!nent) {
1029 dev_dbg(port->dev, "need to release resource of dma\n");
1030 goto chan_err;
1031 } else {
1032 dev_dbg(port->dev, "%s: mapped %d@%p to %x\n", __func__,
1033 sg_dma_len(&atmel_port->sg_rx),
1034 ring->buf,
1035 sg_dma_address(&atmel_port->sg_rx));
1036 }
1037
1038 /* Configure the slave DMA */
1039 memset(&config, 0, sizeof(config));
1040 config.direction = DMA_DEV_TO_MEM;
1041 config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1042 config.src_addr = port->mapbase + ATMEL_US_RHR;
1043
5483c10e
MR		 1044 ret = dmaengine_slave_config(atmel_port->chan_rx,
1045 &config);
34df42f5
ES		 1046 if (ret) {
1047 dev_err(port->dev, "DMA rx slave configuration failed\n");
1048 goto chan_err;
1049 }
1050 /*
1051 * Prepare a cyclic dma transfer, assign 2 descriptors,
1052 * each one is half ring buffer size
1053 */
1054 desc = dmaengine_prep_dma_cyclic(atmel_port->chan_rx,
1055 sg_dma_address(&atmel_port->sg_rx),
1056 sg_dma_len(&atmel_port->sg_rx),
1057 sg_dma_len(&atmel_port->sg_rx)/2,
1058 DMA_DEV_TO_MEM,
1059 DMA_PREP_INTERRUPT);
1060 desc->callback = atmel_complete_rx_dma;
1061 desc->callback_param = port;
1062 atmel_port->desc_rx = desc;
1063 atmel_port->cookie_rx = dmaengine_submit(desc);
1064
1065 return 0;
1066
1067chan_err:
1068 dev_err(port->dev, "RX channel not available, switch to pio\n");
1069 atmel_port->use_dma_rx = 0;
1070 if (atmel_port->chan_rx)
1071 atmel_release_rx_dma(port);
1072 return -EINVAL;
1073}
1074
2e68c22f
ES		 1075static void atmel_uart_timer_callback(unsigned long data)
1076{
1077 struct uart_port *port = (void *)data;
1078 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1079
1080 tasklet_schedule(&atmel_port->tasklet);
1081 mod_timer(&atmel_port->uart_timer, jiffies + uart_poll_timeout(port));
1082}
1083
b843aa21
RB		 1084/*
1085 * receive interrupt handler.
1086 */
1087static void
1088atmel_handle_receive(struct uart_port *port, unsigned int pending)
1089{
c811ab8c 1090 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
b843aa21 1091
64e22ebe 1092 if (atmel_use_pdc_rx(port)) {
a6670615
CC		 1093 /*
1094 * PDC receive. Just schedule the tasklet and let it
1095 * figure out the details.
1096 *
1097 * TODO: We're not handling error flags correctly at
1098 * the moment.
1099 */
1100 if (pending & (ATMEL_US_ENDRX | ATMEL_US_TIMEOUT)) {
1101 UART_PUT_IDR(port, (ATMEL_US_ENDRX
1102 | ATMEL_US_TIMEOUT));
1103 tasklet_schedule(&atmel_port->tasklet);
1104 }
1105
1106 if (pending & (ATMEL_US_RXBRK | ATMEL_US_OVRE |
1107 ATMEL_US_FRAME | ATMEL_US_PARE))
1108 atmel_pdc_rxerr(port, pending);
1109 }
1110
34df42f5
ES		 1111 if (atmel_use_dma_rx(port)) {
1112 if (pending & ATMEL_US_TIMEOUT) {
1113 UART_PUT_IDR(port, ATMEL_US_TIMEOUT);
1114 tasklet_schedule(&atmel_port->tasklet);
1115 }
1116 }
1117
b843aa21
RB		 1118 /* Interrupt receive */
1119 if (pending & ATMEL_US_RXRDY)
1120 atmel_rx_chars(port);
1121 else if (pending & ATMEL_US_RXBRK) {
1122 /*
1123 * End of break detected. If it came along with a
1124 * character, atmel_rx_chars will handle it.
1125 */
1126 UART_PUT_CR(port, ATMEL_US_RSTSTA);
1127 UART_PUT_IDR(port, ATMEL_US_RXBRK);
1128 atmel_port->break_active = 0;
1129 }
1130}
1131
1132/*
1ecc26bd 1133 * transmit interrupt handler. (Transmit is IRQF_NODELAY safe)
b843aa21
RB		 1134 */
1135static void
1136atmel_handle_transmit(struct uart_port *port, unsigned int pending)
1137{
c811ab8c 1138 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1ecc26bd 1139
e8faff73
CS		 1140 if (pending & atmel_port->tx_done_mask) {
1141 /* Either PDC or interrupt transmission */
1142 UART_PUT_IDR(port, atmel_port->tx_done_mask);
1143 tasklet_schedule(&atmel_port->tasklet);
1ecc26bd 1144 }
b843aa21
RB		 1145}
1146
1147/*
1148 * status flags interrupt handler.
1149 */
1150static void
1151atmel_handle_status(struct uart_port *port, unsigned int pending,
1152 unsigned int status)
1153{
c811ab8c 1154 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1ecc26bd 1155
b843aa21 1156 if (pending & (ATMEL_US_RIIC | ATMEL_US_DSRIC | ATMEL_US_DCDIC
1ecc26bd
RB		 1157 | ATMEL_US_CTSIC)) {
1158 atmel_port->irq_status = status;
1159 tasklet_schedule(&atmel_port->tasklet);
1160 }
b843aa21
RB		 1161}
1162
1e6c9c28
AV		 1163/*
1164 * Interrupt handler
1165 */
7d12e780 1166static irqreturn_t atmel_interrupt(int irq, void *dev_id)
1e6c9c28
AV		 1167{
1168 struct uart_port *port = dev_id;
ab5e4e41 1169 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1e6c9c28 1170 unsigned int status, pending, pass_counter = 0;
ab5e4e41 1171 bool gpio_handled = false;
1e6c9c28 1172
a6670615 1173 do {
e0b0baad 1174 status = atmel_get_lines_status(port);
a6670615 1175 pending = status & UART_GET_IMR(port);
ab5e4e41
RG		 1176 if (!gpio_handled) {
1177 /*
1178 * Dealing with GPIO interrupt
1179 */
1180 if (irq == atmel_port->gpio_irq[UART_GPIO_CTS])
1181 pending |= ATMEL_US_CTSIC;
1182
1183 if (irq == atmel_port->gpio_irq[UART_GPIO_DSR])
1184 pending |= ATMEL_US_DSRIC;
1185
1186 if (irq == atmel_port->gpio_irq[UART_GPIO_RI])
1187 pending |= ATMEL_US_RIIC;
1188
1189 if (irq == atmel_port->gpio_irq[UART_GPIO_DCD])
1190 pending |= ATMEL_US_DCDIC;
1191
1192 gpio_handled = true;
1193 }
a6670615
CC		 1194 if (!pending)
1195 break;
1196
b843aa21
RB		 1197 atmel_handle_receive(port, pending);
1198 atmel_handle_status(port, pending, status);
1199 atmel_handle_transmit(port, pending);
a6670615 1200 } while (pass_counter++ < ATMEL_ISR_PASS_LIMIT);
afefc415 1201
0400b697 1202 return pass_counter ? IRQ_HANDLED : IRQ_NONE;
a6670615 1203}
1e6c9c28 1204
a930e528
ES		 1205static void atmel_release_tx_pdc(struct uart_port *port)
1206{
1207 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1208 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1209
1210 dma_unmap_single(port->dev,
1211 pdc->dma_addr,
1212 pdc->dma_size,
1213 DMA_TO_DEVICE);
1214}
1215
a6670615
CC		 1216/*
1217 * Called from tasklet with ENDTX and TXBUFE interrupts disabled.
1218 */
64e22ebe 1219static void atmel_tx_pdc(struct uart_port *port)
a6670615 1220{
c811ab8c 1221 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
ebd2c8f6 1222 struct circ_buf *xmit = &port->state->xmit;
a6670615
CC		 1223 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1224 int count;
1225
ba0657ff
MT		 1226 /* nothing left to transmit? */
1227 if (UART_GET_TCR(port))
1228 return;
1229
a6670615
CC		 1230 xmit->tail += pdc->ofs;
1231 xmit->tail &= UART_XMIT_SIZE - 1;
1232
1233 port->icount.tx += pdc->ofs;
1234 pdc->ofs = 0;
1235
ba0657ff 1236 /* more to transmit - setup next transfer */
a6670615 1237
ba0657ff
MT		 1238 /* disable PDC transmit */
1239 UART_PUT_PTCR(port, ATMEL_PDC_TXTDIS);
1240
1f14081d 1241 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) {
a6670615
CC		 1242 dma_sync_single_for_device(port->dev,
1243 pdc->dma_addr,
1244 pdc->dma_size,
1245 DMA_TO_DEVICE);
1246
1247 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
1248 pdc->ofs = count;
1249
1250 UART_PUT_TPR(port, pdc->dma_addr + xmit->tail);
1251 UART_PUT_TCR(port, count);
e8faff73 1252 /* re-enable PDC transmit */
a6670615 1253 UART_PUT_PTCR(port, ATMEL_PDC_TXTEN);
e8faff73
CS		 1254 /* Enable interrupts */
1255 UART_PUT_IER(port, atmel_port->tx_done_mask);
1256 } else {
83cac9f3
BR		 1257 if ((atmel_port->rs485.flags & SER_RS485_ENABLED) &&
1258 !(atmel_port->rs485.flags & SER_RS485_RX_DURING_TX)) {
e8faff73
CS		 1259 /* DMA done, stop TX, start RX for RS485 */
1260 atmel_start_rx(port);
1261 }
1e6c9c28 1262 }
a6670615
CC		 1263
1264 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1265 uart_write_wakeup(port);
1e6c9c28
AV		 1266}
1267
a930e528
ES		 1268static int atmel_prepare_tx_pdc(struct uart_port *port)
1269{
1270 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1271 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1272 struct circ_buf *xmit = &port->state->xmit;
1273
1274 pdc->buf = xmit->buf;
1275 pdc->dma_addr = dma_map_single(port->dev,
1276 pdc->buf,
1277 UART_XMIT_SIZE,
1278 DMA_TO_DEVICE);
1279 pdc->dma_size = UART_XMIT_SIZE;
1280 pdc->ofs = 0;
1281
1282 return 0;
1283}
1284
1ecc26bd
RB		 1285static void atmel_rx_from_ring(struct uart_port *port)
1286{
c811ab8c 1287 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1ecc26bd
RB		 1288 struct circ_buf *ring = &atmel_port->rx_ring;
1289 unsigned int flg;
1290 unsigned int status;
1291
1292 while (ring->head != ring->tail) {
1293 struct atmel_uart_char c;
1294
1295 /* Make sure c is loaded after head. */
1296 smp_rmb();
1297
1298 c = ((struct atmel_uart_char *)ring->buf)[ring->tail];
1299
1300 ring->tail = (ring->tail + 1) & (ATMEL_SERIAL_RINGSIZE - 1);
1301
1302 port->icount.rx++;
1303 status = c.status;
1304 flg = TTY_NORMAL;
1305
1306 /*
1307 * note that the error handling code is
1308 * out of the main execution path
1309 */
1310 if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME
1311 | ATMEL_US_OVRE | ATMEL_US_RXBRK))) {
1312 if (status & ATMEL_US_RXBRK) {
1313 /* ignore side-effect */
1314 status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME);
1315
1316 port->icount.brk++;
1317 if (uart_handle_break(port))
1318 continue;
1319 }
1320 if (status & ATMEL_US_PARE)
1321 port->icount.parity++;
1322 if (status & ATMEL_US_FRAME)
1323 port->icount.frame++;
1324 if (status & ATMEL_US_OVRE)
1325 port->icount.overrun++;
1326
1327 status &= port->read_status_mask;
1328
1329 if (status & ATMEL_US_RXBRK)
1330 flg = TTY_BREAK;
1331 else if (status & ATMEL_US_PARE)
1332 flg = TTY_PARITY;
1333 else if (status & ATMEL_US_FRAME)
1334 flg = TTY_FRAME;
1335 }
1336
1337
1338 if (uart_handle_sysrq_char(port, c.ch))
1339 continue;
1340
1341 uart_insert_char(port, status, ATMEL_US_OVRE, c.ch, flg);
1342 }
1343
1344 /*
1345 * Drop the lock here since it might end up calling
1346 * uart_start(), which takes the lock.
1347 */
1348 spin_unlock(&port->lock);
2e124b4a 1349 tty_flip_buffer_push(&port->state->port);
1ecc26bd
RB		 1350 spin_lock(&port->lock);
1351}
1352
a930e528
ES		 1353static void atmel_release_rx_pdc(struct uart_port *port)
1354{
1355 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1356 int i;
1357
1358 for (i = 0; i < 2; i++) {
1359 struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i];
1360
1361 dma_unmap_single(port->dev,
1362 pdc->dma_addr,
1363 pdc->dma_size,
1364 DMA_FROM_DEVICE);
1365 kfree(pdc->buf);
1366 }
1367}
1368
64e22ebe 1369static void atmel_rx_from_pdc(struct uart_port *port)
a6670615 1370{
c811ab8c 1371 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
05c7cd39 1372 struct tty_port *tport = &port->state->port;
a6670615
CC		 1373 struct atmel_dma_buffer *pdc;
1374 int rx_idx = atmel_port->pdc_rx_idx;
1375 unsigned int head;
1376 unsigned int tail;
1377 unsigned int count;
1378
1379 do {
1380 /* Reset the UART timeout early so that we don't miss one */
1381 UART_PUT_CR(port, ATMEL_US_STTTO);
1382
1383 pdc = &atmel_port->pdc_rx[rx_idx];
1384 head = UART_GET_RPR(port) - pdc->dma_addr;
1385 tail = pdc->ofs;
1386
1387 /* If the PDC has switched buffers, RPR won't contain
1388 * any address within the current buffer. Since head
1389 * is unsigned, we just need a one-way comparison to
1390 * find out.
1391 *
1392 * In this case, we just need to consume the entire
1393 * buffer and resubmit it for DMA. This will clear the
1394 * ENDRX bit as well, so that we can safely re-enable
1395 * all interrupts below.
1396 */
1397 head = min(head, pdc->dma_size);
1398
1399 if (likely(head != tail)) {
1400 dma_sync_single_for_cpu(port->dev, pdc->dma_addr,
1401 pdc->dma_size, DMA_FROM_DEVICE);
1402
1403 /*
1404 * head will only wrap around when we recycle
1405 * the DMA buffer, and when that happens, we
1406 * explicitly set tail to 0. So head will
1407 * always be greater than tail.
1408 */
1409 count = head - tail;
1410
05c7cd39
JS		 1411 tty_insert_flip_string(tport, pdc->buf + pdc->ofs,
1412 count);
a6670615
CC		 1413
1414 dma_sync_single_for_device(port->dev, pdc->dma_addr,
1415 pdc->dma_size, DMA_FROM_DEVICE);
1416
1417 port->icount.rx += count;
1418 pdc->ofs = head;
1419 }
1420
1421 /*
1422 * If the current buffer is full, we need to check if
1423 * the next one contains any additional data.
1424 */
1425 if (head >= pdc->dma_size) {
1426 pdc->ofs = 0;
1427 UART_PUT_RNPR(port, pdc->dma_addr);
1428 UART_PUT_RNCR(port, pdc->dma_size);
1429
1430 rx_idx = !rx_idx;
1431 atmel_port->pdc_rx_idx = rx_idx;
1432 }
1433 } while (head >= pdc->dma_size);
1434
1435 /*
1436 * Drop the lock here since it might end up calling
1437 * uart_start(), which takes the lock.
1438 */
1439 spin_unlock(&port->lock);
2e124b4a 1440 tty_flip_buffer_push(tport);
a6670615
CC		 1441 spin_lock(&port->lock);
1442
1443 UART_PUT_IER(port, ATMEL_US_ENDRX | ATMEL_US_TIMEOUT);
1444}
1445
a930e528
ES		 1446static int atmel_prepare_rx_pdc(struct uart_port *port)
1447{
1448 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1449 int i;
1450
1451 for (i = 0; i < 2; i++) {
1452 struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i];
1453
1454 pdc->buf = kmalloc(PDC_BUFFER_SIZE, GFP_KERNEL);
1455 if (pdc->buf == NULL) {
1456 if (i != 0) {
1457 dma_unmap_single(port->dev,
1458 atmel_port->pdc_rx[0].dma_addr,
1459 PDC_BUFFER_SIZE,
1460 DMA_FROM_DEVICE);
1461 kfree(atmel_port->pdc_rx[0].buf);
1462 }
1463 atmel_port->use_pdc_rx = 0;
1464 return -ENOMEM;
1465 }
1466 pdc->dma_addr = dma_map_single(port->dev,
1467 pdc->buf,
1468 PDC_BUFFER_SIZE,
1469 DMA_FROM_DEVICE);
1470 pdc->dma_size = PDC_BUFFER_SIZE;
1471 pdc->ofs = 0;
1472 }
1473
1474 atmel_port->pdc_rx_idx = 0;
1475
1476 UART_PUT_RPR(port, atmel_port->pdc_rx[0].dma_addr);
1477 UART_PUT_RCR(port, PDC_BUFFER_SIZE);
1478
1479 UART_PUT_RNPR(port, atmel_port->pdc_rx[1].dma_addr);
1480 UART_PUT_RNCR(port, PDC_BUFFER_SIZE);
1481
1482 return 0;
1483}
1484
1ecc26bd
RB		 1485/*
1486 * tasklet handling tty stuff outside the interrupt handler.
1487 */
1488static void atmel_tasklet_func(unsigned long data)
1489{
1490 struct uart_port *port = (struct uart_port *)data;
c811ab8c 1491 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1ecc26bd
RB		 1492 unsigned int status;
1493 unsigned int status_change;
1494
1495 /* The interrupt handler does not take the lock */
1496 spin_lock(&port->lock);
1497
a930e528 1498 atmel_port->schedule_tx(port);
1ecc26bd
RB		 1499
1500 status = atmel_port->irq_status;
1501 status_change = status ^ atmel_port->irq_status_prev;
1502
1503 if (status_change & (ATMEL_US_RI | ATMEL_US_DSR
1504 | ATMEL_US_DCD | ATMEL_US_CTS)) {
1505 /* TODO: All reads to CSR will clear these interrupts! */
1506 if (status_change & ATMEL_US_RI)
1507 port->icount.rng++;
1508 if (status_change & ATMEL_US_DSR)
1509 port->icount.dsr++;
1510 if (status_change & ATMEL_US_DCD)
1511 uart_handle_dcd_change(port, !(status & ATMEL_US_DCD));
1512 if (status_change & ATMEL_US_CTS)
1513 uart_handle_cts_change(port, !(status & ATMEL_US_CTS));
1514
bdc04e31 1515 wake_up_interruptible(&port->state->port.delta_msr_wait);
1ecc26bd
RB		 1516
1517 atmel_port->irq_status_prev = status;
1518 }
1519
a930e528 1520 atmel_port->schedule_rx(port);
1ecc26bd
RB		 1521
1522 spin_unlock(&port->lock);
1523}
1524
33d64c4f
ES		 1525static int atmel_init_property(struct atmel_uart_port *atmel_port,
1526 struct platform_device *pdev)
1527{
1528 struct device_node *np = pdev->dev.of_node;
574de559 1529 struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev);
33d64c4f
ES		 1530
1531 if (np) {
1532 /* DMA/PDC usage specification */
1533 if (of_get_property(np, "atmel,use-dma-rx", NULL)) {
1534 if (of_get_property(np, "dmas", NULL)) {
1535 atmel_port->use_dma_rx = true;
1536 atmel_port->use_pdc_rx = false;
1537 } else {
1538 atmel_port->use_dma_rx = false;
1539 atmel_port->use_pdc_rx = true;
1540 }
1541 } else {
1542 atmel_port->use_dma_rx = false;
1543 atmel_port->use_pdc_rx = false;
1544 }
1545
1546 if (of_get_property(np, "atmel,use-dma-tx", NULL)) {
1547 if (of_get_property(np, "dmas", NULL)) {
1548 atmel_port->use_dma_tx = true;
1549 atmel_port->use_pdc_tx = false;
1550 } else {
1551 atmel_port->use_dma_tx = false;
1552 atmel_port->use_pdc_tx = true;
1553 }
1554 } else {
1555 atmel_port->use_dma_tx = false;
1556 atmel_port->use_pdc_tx = false;
1557 }
1558
1559 } else {
1560 atmel_port->use_pdc_rx = pdata->use_dma_rx;
1561 atmel_port->use_pdc_tx = pdata->use_dma_tx;
1562 atmel_port->use_dma_rx = false;
1563 atmel_port->use_dma_tx = false;
1564 }
1565
1566 return 0;
1567}
1568
1569static void atmel_init_rs485(struct atmel_uart_port *atmel_port,
1570 struct platform_device *pdev)
1571{
1572 struct device_node *np = pdev->dev.of_node;
574de559 1573 struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev);
33d64c4f
ES		 1574
1575 if (np) {
1576 u32 rs485_delay[2];
1577 /* rs485 properties */
1578 if (of_property_read_u32_array(np, "rs485-rts-delay",
1579 rs485_delay, 2) == 0) {
1580 struct serial_rs485 *rs485conf = &atmel_port->rs485;
1581
1582 rs485conf->delay_rts_before_send = rs485_delay[0];
1583 rs485conf->delay_rts_after_send = rs485_delay[1];
1584 rs485conf->flags = 0;
1585
1586 if (of_get_property(np, "rs485-rx-during-tx", NULL))
1587 rs485conf->flags |= SER_RS485_RX_DURING_TX;
1588
1589 if (of_get_property(np, "linux,rs485-enabled-at-boot-time",
1590 NULL))
1591 rs485conf->flags |= SER_RS485_ENABLED;
1592 }
1593 } else {
1594 atmel_port->rs485 = pdata->rs485;
1595 }
1596
1597}
1598
a930e528
ES		 1599static void atmel_set_ops(struct uart_port *port)
1600{
1601 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1602
34df42f5
ES		 1603 if (atmel_use_dma_rx(port)) {
1604 atmel_port->prepare_rx = &atmel_prepare_rx_dma;
1605 atmel_port->schedule_rx = &atmel_rx_from_dma;
1606 atmel_port->release_rx = &atmel_release_rx_dma;
1607 } else if (atmel_use_pdc_rx(port)) {
a930e528
ES		 1608 atmel_port->prepare_rx = &atmel_prepare_rx_pdc;
1609 atmel_port->schedule_rx = &atmel_rx_from_pdc;
1610 atmel_port->release_rx = &atmel_release_rx_pdc;
1611 } else {
1612 atmel_port->prepare_rx = NULL;
1613 atmel_port->schedule_rx = &atmel_rx_from_ring;
1614 atmel_port->release_rx = NULL;
1615 }
1616
08f738be
ES		 1617 if (atmel_use_dma_tx(port)) {
1618 atmel_port->prepare_tx = &atmel_prepare_tx_dma;
1619 atmel_port->schedule_tx = &atmel_tx_dma;
1620 atmel_port->release_tx = &atmel_release_tx_dma;
1621 } else if (atmel_use_pdc_tx(port)) {
a930e528
ES		 1622 atmel_port->prepare_tx = &atmel_prepare_tx_pdc;
1623 atmel_port->schedule_tx = &atmel_tx_pdc;
1624 atmel_port->release_tx = &atmel_release_tx_pdc;
1625 } else {
1626 atmel_port->prepare_tx = NULL;
1627 atmel_port->schedule_tx = &atmel_tx_chars;
1628 atmel_port->release_tx = NULL;
1629 }
1630}
1631
055560b0
ES		 1632/*
1633 * Get ip name usart or uart
1634 */
892db58b 1635static void atmel_get_ip_name(struct uart_port *port)
055560b0
ES		 1636{
1637 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1638 int name = UART_GET_IP_NAME(port);
731d9cae 1639 u32 version;
055560b0
ES		 1640 int usart, uart;
1641 /* usart and uart ascii */
1642 usart = 0x55534152;
1643 uart = 0x44424755;
1644
1645 atmel_port->is_usart = false;
1646
1647 if (name == usart) {
1648 dev_dbg(port->dev, "This is usart\n");
1649 atmel_port->is_usart = true;
1650 } else if (name == uart) {
1651 dev_dbg(port->dev, "This is uart\n");
1652 atmel_port->is_usart = false;
1653 } else {
731d9cae
NF		 1654 /* fallback for older SoCs: use version field */
1655 version = UART_GET_IP_VERSION(port);
1656 switch (version) {
1657 case 0x302:
1658 case 0x10213:
1659 dev_dbg(port->dev, "This version is usart\n");
1660 atmel_port->is_usart = true;
1661 break;
1662 case 0x203:
1663 case 0x10202:
1664 dev_dbg(port->dev, "This version is uart\n");
1665 atmel_port->is_usart = false;
1666 break;
1667 default:
1668 dev_err(port->dev, "Not supported ip name nor version, set to uart\n");
1669 }
055560b0 1670 }
055560b0
ES		 1671}
1672
ab5e4e41
RG		 1673static void atmel_free_gpio_irq(struct uart_port *port)
1674{
1675 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1676 enum mctrl_gpio_idx i;
1677
1678 for (i = 0; i < UART_GPIO_MAX; i++)
1679 if (atmel_port->gpio_irq[i] >= 0)
1680 free_irq(atmel_port->gpio_irq[i], port);
1681}
1682
1683static int atmel_request_gpio_irq(struct uart_port *port)
1684{
1685 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1686 int *irq = atmel_port->gpio_irq;
1687 enum mctrl_gpio_idx i;
1688 int err = 0;
1689
1690 for (i = 0; (i < UART_GPIO_MAX) && !err; i++) {
1691 if (irq[i] < 0)
1692 continue;
1693
1694 irq_set_status_flags(irq[i], IRQ_NOAUTOEN);
1695 err = request_irq(irq[i], atmel_interrupt, IRQ_TYPE_EDGE_BOTH,
1696 "atmel_serial", port);
1697 if (err)
1698 dev_err(port->dev, "atmel_startup - Can't get %d irq\n",
1699 irq[i]);
1700 }
1701
1702 /*
1703 * If something went wrong, rollback.
1704 */
1705 while (err && (--i >= 0))
1706 if (irq[i] >= 0)
1707 free_irq(irq[i], port);
1708
1709 return err;
1710}
1711
1e6c9c28
AV		 1712/*
1713 * Perform initialization and enable port for reception
1714 */
7192f92c 1715static int atmel_startup(struct uart_port *port)
1e6c9c28 1716{
33d64c4f 1717 struct platform_device *pdev = to_platform_device(port->dev);
c811ab8c 1718 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
ebd2c8f6 1719 struct tty_struct *tty = port->state->port.tty;
1e6c9c28
AV		 1720 int retval;
1721
1722 /*
1723 * Ensure that no interrupts are enabled otherwise when
1724 * request_irq() is called we could get stuck trying to
1725 * handle an unexpected interrupt
1726 */
1727 UART_PUT_IDR(port, -1);
ab5e4e41 1728 atmel_port->ms_irq_enabled = false;
1e6c9c28
AV		 1729
1730 /*
1731 * Allocate the IRQ
1732 */
b843aa21 1733 retval = request_irq(port->irq, atmel_interrupt, IRQF_SHARED,
ae161068 1734 tty ? tty->name : "atmel_serial", port);
1e6c9c28 1735 if (retval) {
ddaa6037 1736 dev_err(port->dev, "atmel_startup - Can't get irq\n");
1e6c9c28
AV		 1737 return retval;
1738 }
1739
ab5e4e41
RG		 1740 /*
1741 * Get the GPIO lines IRQ
1742 */
1743 retval = atmel_request_gpio_irq(port);
1744 if (retval)
1745 goto free_irq;
1746
a6670615
CC		 1747 /*
1748 * Initialize DMA (if necessary)
1749 */
33d64c4f
ES		 1750 atmel_init_property(atmel_port, pdev);
1751
a930e528
ES		 1752 if (atmel_port->prepare_rx) {
1753 retval = atmel_port->prepare_rx(port);
1754 if (retval < 0)
1755 atmel_set_ops(port);
a6670615 1756 }
a6670615 1757
a930e528
ES		 1758 if (atmel_port->prepare_tx) {
1759 retval = atmel_port->prepare_tx(port);
1760 if (retval < 0)
1761 atmel_set_ops(port);
a6670615 1762 }
1e6c9c28 1763
27c0c8e5 1764 /* Save current CSR for comparison in atmel_tasklet_func() */
e0b0baad 1765 atmel_port->irq_status_prev = atmel_get_lines_status(port);
27c0c8e5
AN		 1766 atmel_port->irq_status = atmel_port->irq_status_prev;
1767
1e6c9c28
AV		 1768 /*
1769 * Finally, enable the serial port
1770 */
7192f92c 1771 UART_PUT_CR(port, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
b843aa21
RB		 1772 /* enable xmit & rcvr */
1773 UART_PUT_CR(port, ATMEL_US_TXEN | ATMEL_US_RXEN);
afefc415 1774
8bc661bf
MR		 1775 setup_timer(&atmel_port->uart_timer,
1776 atmel_uart_timer_callback,
1777 (unsigned long)port);
1778
64e22ebe 1779 if (atmel_use_pdc_rx(port)) {
a6670615 1780 /* set UART timeout */
2e68c22f 1781 if (!atmel_port->is_usart) {
2e68c22f
ES		 1782 mod_timer(&atmel_port->uart_timer,
1783 jiffies + uart_poll_timeout(port));
1784 /* set USART timeout */
1785 } else {
1786 UART_PUT_RTOR(port, PDC_RX_TIMEOUT);
1787 UART_PUT_CR(port, ATMEL_US_STTTO);
a6670615 1788
2e68c22f
ES		 1789 UART_PUT_IER(port, ATMEL_US_ENDRX | ATMEL_US_TIMEOUT);
1790 }
a6670615
CC		 1791 /* enable PDC controller */
1792 UART_PUT_PTCR(port, ATMEL_PDC_RXTEN);
34df42f5 1793 } else if (atmel_use_dma_rx(port)) {
2e68c22f
ES		 1794 /* set UART timeout */
1795 if (!atmel_port->is_usart) {
2e68c22f
ES		 1796 mod_timer(&atmel_port->uart_timer,
1797 jiffies + uart_poll_timeout(port));
1798 /* set USART timeout */
1799 } else {
1800 UART_PUT_RTOR(port, PDC_RX_TIMEOUT);
1801 UART_PUT_CR(port, ATMEL_US_STTTO);
34df42f5 1802
2e68c22f
ES		 1803 UART_PUT_IER(port, ATMEL_US_TIMEOUT);
1804 }
a6670615
CC		 1805 } else {
1806 /* enable receive only */
1807 UART_PUT_IER(port, ATMEL_US_RXRDY);
1808 }
afefc415 1809
1e6c9c28 1810 return 0;
ab5e4e41
RG		 1811
1812free_irq:
1813 free_irq(port->irq, port);
1814
1815 return retval;
1e6c9c28
AV		 1816}
1817
479e9b94
PH		 1818/*
1819 * Flush any TX data submitted for DMA. Called when the TX circular
1820 * buffer is reset.
1821 */
1822static void atmel_flush_buffer(struct uart_port *port)
1823{
1824 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1825
1826 if (atmel_use_pdc_tx(port)) {
1827 UART_PUT_TCR(port, 0);
1828 atmel_port->pdc_tx.ofs = 0;
1829 }
1830}
1831
1e6c9c28
AV		 1832/*
1833 * Disable the port
1834 */
7192f92c 1835static void atmel_shutdown(struct uart_port *port)
1e6c9c28 1836{
c811ab8c 1837 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
0cc7c6c7 1838
8bc661bf
MR		 1839 /*
1840 * Prevent any tasklets being scheduled during
1841 * cleanup
1842 */
1843 del_timer_sync(&atmel_port->uart_timer);
1844
0cc7c6c7
MR		 1845 /*
1846 * Clear out any scheduled tasklets before
1847 * we destroy the buffers
1848 */
1849 tasklet_kill(&atmel_port->tasklet);
1850
a6670615 1851 /*
0cc7c6c7
MR		 1852 * Ensure everything is stopped and
1853 * disable all interrupts, port and break condition.
a6670615
CC		 1854 */
1855 atmel_stop_rx(port);
1856 atmel_stop_tx(port);
1857
0cc7c6c7
MR		 1858 UART_PUT_CR(port, ATMEL_US_RSTSTA);
1859 UART_PUT_IDR(port, -1);
1860
1861
a6670615
CC		 1862 /*
1863 * Shut-down the DMA.
1864 */
a930e528
ES		 1865 if (atmel_port->release_rx)
1866 atmel_port->release_rx(port);
1867 if (atmel_port->release_tx)
1868 atmel_port->release_tx(port);
a6670615 1869
bb7e73c5
MD		 1870 /*
1871 * Reset ring buffer pointers
1872 */
1873 atmel_port->rx_ring.head = 0;
1874 atmel_port->rx_ring.tail = 0;
1875
1e6c9c28 1876 /*
ab5e4e41 1877 * Free the interrupts
1e6c9c28
AV		 1878 */
1879 free_irq(port->irq, port);
ab5e4e41
RG		 1880 atmel_free_gpio_irq(port);
1881
1882 atmel_port->ms_irq_enabled = false;
1e6c9c28 1883
479e9b94 1884 atmel_flush_buffer(port);
9afd561a
HS		 1885}
1886
1e6c9c28
AV		 1887/*
1888 * Power / Clock management.
1889 */
b843aa21
RB		 1890static void atmel_serial_pm(struct uart_port *port, unsigned int state,
1891 unsigned int oldstate)
1e6c9c28 1892{
c811ab8c 1893 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
afefc415 1894
1e6c9c28 1895 switch (state) {
b843aa21
RB		 1896 case 0:
1897 /*
1898 * Enable the peripheral clock for this serial port.
1899 * This is called on uart_open() or a resume event.
1900 */
91f8c2d8 1901 clk_prepare_enable(atmel_port->clk);
f05596db
AS		 1902
1903 /* re-enable interrupts if we disabled some on suspend */
1904 UART_PUT_IER(port, atmel_port->backup_imr);
b843aa21
RB		 1905 break;
1906 case 3:
f05596db
AS		 1907 /* Back up the interrupt mask and disable all interrupts */
1908 atmel_port->backup_imr = UART_GET_IMR(port);
1909 UART_PUT_IDR(port, -1);
1910
b843aa21
RB		 1911 /*
1912 * Disable the peripheral clock for this serial port.
1913 * This is called on uart_close() or a suspend event.
1914 */
91f8c2d8 1915 clk_disable_unprepare(atmel_port->clk);
b843aa21
RB		 1916 break;
1917 default:
ddaa6037 1918 dev_err(port->dev, "atmel_serial: unknown pm %d\n", state);
1e6c9c28
AV		 1919 }
1920}
1921
1922/*
1923 * Change the port parameters
1924 */
b843aa21
RB		 1925static void atmel_set_termios(struct uart_port *port, struct ktermios *termios,
1926 struct ktermios *old)
1e6c9c28
AV		 1927{
1928 unsigned long flags;
1929 unsigned int mode, imr, quot, baud;
e8faff73 1930 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1e6c9c28 1931
03abeac0 1932 /* Get current mode register */
b843aa21 1933 mode = UART_GET_MR(port) & ~(ATMEL_US_USCLKS | ATMEL_US_CHRL
8e706c4d
PM		 1934 | ATMEL_US_NBSTOP | ATMEL_US_PAR
1935 | ATMEL_US_USMODE);
03abeac0 1936
b843aa21 1937 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
1e6c9c28
AV		 1938 quot = uart_get_divisor(port, baud);
1939
b843aa21 1940 if (quot > 65535) { /* BRGR is 16-bit, so switch to slower clock */
03abeac0
AV		 1941 quot /= 8;
1942 mode |= ATMEL_US_USCLKS_MCK_DIV8;
1943 }
1e6c9c28
AV		 1944
1945 /* byte size */
1946 switch (termios->c_cflag & CSIZE) {
1947 case CS5:
7192f92c 1948 mode |= ATMEL_US_CHRL_5;
1e6c9c28
AV		 1949 break;
1950 case CS6:
7192f92c 1951 mode |= ATMEL_US_CHRL_6;
1e6c9c28
AV		 1952 break;
1953 case CS7:
7192f92c 1954 mode |= ATMEL_US_CHRL_7;
1e6c9c28
AV		 1955 break;
1956 default:
7192f92c 1957 mode |= ATMEL_US_CHRL_8;
1e6c9c28
AV		 1958 break;
1959 }
1960
1961 /* stop bits */
1962 if (termios->c_cflag & CSTOPB)
7192f92c 1963 mode |= ATMEL_US_NBSTOP_2;
1e6c9c28
AV		 1964
1965 /* parity */
1966 if (termios->c_cflag & PARENB) {
b843aa21
RB		 1967 /* Mark or Space parity */
1968 if (termios->c_cflag & CMSPAR) {
1e6c9c28 1969 if (termios->c_cflag & PARODD)
7192f92c 1970 mode |= ATMEL_US_PAR_MARK;
1e6c9c28 1971 else
7192f92c 1972 mode |= ATMEL_US_PAR_SPACE;
b843aa21 1973 } else if (termios->c_cflag & PARODD)
7192f92c 1974 mode |= ATMEL_US_PAR_ODD;
1e6c9c28 1975 else
7192f92c 1976 mode |= ATMEL_US_PAR_EVEN;
b843aa21 1977 } else
7192f92c 1978 mode |= ATMEL_US_PAR_NONE;
1e6c9c28 1979
8e706c4d
PM		 1980 /* hardware handshake (RTS/CTS) */
1981 if (termios->c_cflag & CRTSCTS)
1982 mode |= ATMEL_US_USMODE_HWHS;
1983 else
1984 mode |= ATMEL_US_USMODE_NORMAL;
1985
1e6c9c28
AV		 1986 spin_lock_irqsave(&port->lock, flags);
1987
7192f92c 1988 port->read_status_mask = ATMEL_US_OVRE;
1e6c9c28 1989 if (termios->c_iflag & INPCK)
7192f92c 1990 port->read_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE);
ef8b9ddc 1991 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
7192f92c 1992 port->read_status_mask |= ATMEL_US_RXBRK;
1e6c9c28 1993
64e22ebe 1994 if (atmel_use_pdc_rx(port))
a6670615
CC		 1995 /* need to enable error interrupts */
1996 UART_PUT_IER(port, port->read_status_mask);
1997
1e6c9c28
AV		 1998 /*
1999 * Characters to ignore
2000 */
2001 port->ignore_status_mask = 0;
2002 if (termios->c_iflag & IGNPAR)
7192f92c 2003 port->ignore_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE);
1e6c9c28 2004 if (termios->c_iflag & IGNBRK) {
7192f92c 2005 port->ignore_status_mask |= ATMEL_US_RXBRK;
1e6c9c28
AV		 2006 /*
2007 * If we're ignoring parity and break indicators,
2008 * ignore overruns too (for real raw support).
2009 */
2010 if (termios->c_iflag & IGNPAR)
7192f92c 2011 port->ignore_status_mask |= ATMEL_US_OVRE;
1e6c9c28 2012 }
b843aa21 2013 /* TODO: Ignore all characters if CREAD is set.*/
1e6c9c28
AV		 2014
2015 /* update the per-port timeout */
2016 uart_update_timeout(port, termios->c_cflag, baud);
2017
0ccad870
HS		 2018 /*
2019 * save/disable interrupts. The tty layer will ensure that the
2020 * transmitter is empty if requested by the caller, so there's
2021 * no need to wait for it here.
2022 */
b843aa21
RB		 2023 imr = UART_GET_IMR(port);
2024 UART_PUT_IDR(port, -1);
1e6c9c28
AV		 2025
2026 /* disable receiver and transmitter */
7192f92c 2027 UART_PUT_CR(port, ATMEL_US_TXDIS | ATMEL_US_RXDIS);
1e6c9c28 2028
e8faff73
CS		 2029 /* Resetting serial mode to RS232 (0x0) */
2030 mode &= ~ATMEL_US_USMODE;
2031
2032 if (atmel_port->rs485.flags & SER_RS485_ENABLED) {
93f3350c 2033 if ((atmel_port->rs485.delay_rts_after_send) > 0)
1b633184
CS		 2034 UART_PUT_TTGR(port,
2035 atmel_port->rs485.delay_rts_after_send);
e8faff73 2036 mode |= ATMEL_US_USMODE_RS485;
e8faff73
CS		 2037 }
2038
1e6c9c28
AV		 2039 /* set the parity, stop bits and data size */
2040 UART_PUT_MR(port, mode);
2041
2042 /* set the baud rate */
2043 UART_PUT_BRGR(port, quot);
7192f92c
HS		 2044 UART_PUT_CR(port, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
2045 UART_PUT_CR(port, ATMEL_US_TXEN | ATMEL_US_RXEN);
1e6c9c28
AV		 2046
2047 /* restore interrupts */
2048 UART_PUT_IER(port, imr);
2049
2050 /* CTS flow-control and modem-status interrupts */
2051 if (UART_ENABLE_MS(port, termios->c_cflag))
35b675b9
RG		 2052 atmel_enable_ms(port);
2053 else
2054 atmel_disable_ms(port);
1e6c9c28
AV		 2055
2056 spin_unlock_irqrestore(&port->lock, flags);
2057}
2058
42bd7a4f
VP		 2059static void atmel_set_ldisc(struct uart_port *port, int new)
2060{
b54bf3b2 2061 if (new == N_PPS) {
42bd7a4f
VP		 2062 port->flags |= UPF_HARDPPS_CD;
2063 atmel_enable_ms(port);
2064 } else {
2065 port->flags &= ~UPF_HARDPPS_CD;
2066 }
2067}
2068
1e6c9c28
AV		 2069/*
2070 * Return string describing the specified port
2071 */
7192f92c 2072static const char *atmel_type(struct uart_port *port)
1e6c9c28 2073{
9ab4f88b 2074 return (port->type == PORT_ATMEL) ? "ATMEL_SERIAL" : NULL;
1e6c9c28
AV		 2075}
2076
2077/*
2078 * Release the memory region(s) being used by 'port'.
2079 */
7192f92c 2080static void atmel_release_port(struct uart_port *port)
1e6c9c28 2081{
afefc415
AV		 2082 struct platform_device *pdev = to_platform_device(port->dev);
2083 int size = pdev->resource[0].end - pdev->resource[0].start + 1;
2084
2085 release_mem_region(port->mapbase, size);
2086
2087 if (port->flags & UPF_IOREMAP) {
2088 iounmap(port->membase);
2089 port->membase = NULL;
2090 }
1e6c9c28
AV		 2091}
2092
2093/*
2094 * Request the memory region(s) being used by 'port'.
2095 */
7192f92c 2096static int atmel_request_port(struct uart_port *port)
1e6c9c28 2097{
afefc415
AV		 2098 struct platform_device *pdev = to_platform_device(port->dev);
2099 int size = pdev->resource[0].end - pdev->resource[0].start + 1;
2100
7192f92c 2101 if (!request_mem_region(port->mapbase, size, "atmel_serial"))
afefc415
AV		 2102 return -EBUSY;
2103
2104 if (port->flags & UPF_IOREMAP) {
2105 port->membase = ioremap(port->mapbase, size);
2106 if (port->membase == NULL) {
2107 release_mem_region(port->mapbase, size);
2108 return -ENOMEM;
2109 }
2110 }
1e6c9c28 2111
afefc415 2112 return 0;
1e6c9c28
AV		 2113}
2114
2115/*
2116 * Configure/autoconfigure the port.
2117 */
7192f92c 2118static void atmel_config_port(struct uart_port *port, int flags)
1e6c9c28
AV		 2119{
2120 if (flags & UART_CONFIG_TYPE) {
9ab4f88b 2121 port->type = PORT_ATMEL;
7192f92c 2122 atmel_request_port(port);
1e6c9c28
AV		 2123 }
2124}
2125
2126/*
2127 * Verify the new serial_struct (for TIOCSSERIAL).
2128 */
7192f92c 2129static int atmel_verify_port(struct uart_port *port, struct serial_struct *ser)
1e6c9c28
AV		 2130{
2131 int ret = 0;
9ab4f88b 2132 if (ser->type != PORT_UNKNOWN && ser->type != PORT_ATMEL)
1e6c9c28
AV		 2133 ret = -EINVAL;
2134 if (port->irq != ser->irq)
2135 ret = -EINVAL;
2136 if (ser->io_type != SERIAL_IO_MEM)
2137 ret = -EINVAL;
2138 if (port->uartclk / 16 != ser->baud_base)
2139 ret = -EINVAL;
2140 if ((void *)port->mapbase != ser->iomem_base)
2141 ret = -EINVAL;
2142 if (port->iobase != ser->port)
2143 ret = -EINVAL;
2144 if (ser->hub6 != 0)
2145 ret = -EINVAL;
2146 return ret;
2147}
2148
8fe2d541
AT		 2149#ifdef CONFIG_CONSOLE_POLL
2150static int atmel_poll_get_char(struct uart_port *port)
2151{
2152 while (!(UART_GET_CSR(port) & ATMEL_US_RXRDY))
2153 cpu_relax();
2154
2155 return UART_GET_CHAR(port);
2156}
2157
2158static void atmel_poll_put_char(struct uart_port *port, unsigned char ch)
2159{
2160 while (!(UART_GET_CSR(port) & ATMEL_US_TXRDY))
2161 cpu_relax();
2162
2163 UART_PUT_CHAR(port, ch);
2164}
2165#endif
2166
e8faff73
CS		 2167static int
2168atmel_ioctl(struct uart_port *port, unsigned int cmd, unsigned long arg)
2169{
2170 struct serial_rs485 rs485conf;
2171
2172 switch (cmd) {
2173 case TIOCSRS485:
2174 if (copy_from_user(&rs485conf, (struct serial_rs485 *) arg,
2175 sizeof(rs485conf)))
2176 return -EFAULT;
2177
2178 atmel_config_rs485(port, &rs485conf);
2179 break;
2180
2181 case TIOCGRS485:
2182 if (copy_to_user((struct serial_rs485 *) arg,
2183 &(to_atmel_uart_port(port)->rs485),
2184 sizeof(rs485conf)))
2185 return -EFAULT;
2186 break;
2187
2188 default:
2189 return -ENOIOCTLCMD;
2190 }
2191 return 0;
2192}
2193
2194
2195
7192f92c
HS		 2196static struct uart_ops atmel_pops = {
2197 .tx_empty = atmel_tx_empty,
2198 .set_mctrl = atmel_set_mctrl,
2199 .get_mctrl = atmel_get_mctrl,
2200 .stop_tx = atmel_stop_tx,
2201 .start_tx = atmel_start_tx,
2202 .stop_rx = atmel_stop_rx,
2203 .enable_ms = atmel_enable_ms,
2204 .break_ctl = atmel_break_ctl,
2205 .startup = atmel_startup,
2206 .shutdown = atmel_shutdown,
9afd561a 2207 .flush_buffer = atmel_flush_buffer,
7192f92c 2208 .set_termios = atmel_set_termios,
42bd7a4f 2209 .set_ldisc = atmel_set_ldisc,
7192f92c
HS		 2210 .type = atmel_type,
2211 .release_port = atmel_release_port,
2212 .request_port = atmel_request_port,
2213 .config_port = atmel_config_port,
2214 .verify_port = atmel_verify_port,
2215 .pm = atmel_serial_pm,
e8faff73 2216 .ioctl = atmel_ioctl,
8fe2d541
AT		 2217#ifdef CONFIG_CONSOLE_POLL
2218 .poll_get_char = atmel_poll_get_char,
2219 .poll_put_char = atmel_poll_put_char,
2220#endif
1e6c9c28
AV		 2221};
2222
afefc415
AV		 2223/*
2224 * Configure the port from the platform device resource info.
2225 */
91f8c2d8 2226static int atmel_init_port(struct atmel_uart_port *atmel_port,
b843aa21 2227 struct platform_device *pdev)
1e6c9c28 2228{
91f8c2d8 2229 int ret;
7192f92c 2230 struct uart_port *port = &atmel_port->uart;
574de559 2231 struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev);
afefc415 2232
33d64c4f
ES		 2233 if (!atmel_init_property(atmel_port, pdev))
2234 atmel_set_ops(port);
afefc415 2235
33d64c4f 2236 atmel_init_rs485(atmel_port, pdev);
a930e528 2237
e8faff73
CS		 2238 port->iotype = UPIO_MEM;
2239 port->flags = UPF_BOOT_AUTOCONF;
2240 port->ops = &atmel_pops;
2241 port->fifosize = 1;
e8faff73 2242 port->dev = &pdev->dev;
afefc415
AV		 2243 port->mapbase = pdev->resource[0].start;
2244 port->irq = pdev->resource[1].start;
2245
1ecc26bd
RB		 2246 tasklet_init(&atmel_port->tasklet, atmel_tasklet_func,
2247 (unsigned long)port);
2248
2249 memset(&atmel_port->rx_ring, 0, sizeof(atmel_port->rx_ring));
2250
5fbe46b6 2251 if (pdata && pdata->regs) {
75d35213 2252 /* Already mapped by setup code */
1acfc7ec 2253 port->membase = pdata->regs;
588edbf3 2254 } else {
afefc415
AV		 2255 port->flags |= UPF_IOREMAP;
2256 port->membase = NULL;
2257 }
1e6c9c28 2258
b843aa21
RB		 2259 /* for console, the clock could already be configured */
2260 if (!atmel_port->clk) {
7192f92c 2261 atmel_port->clk = clk_get(&pdev->dev, "usart");
91f8c2d8
BB		 2262 if (IS_ERR(atmel_port->clk)) {
2263 ret = PTR_ERR(atmel_port->clk);
2264 atmel_port->clk = NULL;
2265 return ret;
2266 }
2267 ret = clk_prepare_enable(atmel_port->clk);
2268 if (ret) {
2269 clk_put(atmel_port->clk);
2270 atmel_port->clk = NULL;
2271 return ret;
2272 }
7192f92c 2273 port->uartclk = clk_get_rate(atmel_port->clk);
91f8c2d8 2274 clk_disable_unprepare(atmel_port->clk);
06a7f058 2275 /* only enable clock when USART is in use */
afefc415 2276 }
a6670615 2277
e8faff73
CS		 2278 /* Use TXEMPTY for interrupt when rs485 else TXRDY or ENDTX|TXBUFE */
2279 if (atmel_port->rs485.flags & SER_RS485_ENABLED)
2280 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY;
64e22ebe 2281 else if (atmel_use_pdc_tx(port)) {
a6670615 2282 port->fifosize = PDC_BUFFER_SIZE;
e8faff73
CS		 2283 atmel_port->tx_done_mask = ATMEL_US_ENDTX | ATMEL_US_TXBUFE;
2284 } else {
2285 atmel_port->tx_done_mask = ATMEL_US_TXRDY;
2286 }
91f8c2d8
BB		 2287
2288 return 0;
1e6c9c28
AV		 2289}
2290
69f6a27b
JCPV		 2291struct platform_device *atmel_default_console_device; /* the serial console device */
2292
749c4e60 2293#ifdef CONFIG_SERIAL_ATMEL_CONSOLE
7192f92c 2294static void atmel_console_putchar(struct uart_port *port, int ch)
d358788f 2295{
7192f92c 2296 while (!(UART_GET_CSR(port) & ATMEL_US_TXRDY))
829dd811 2297 cpu_relax();
d358788f
RK		 2298 UART_PUT_CHAR(port, ch);
2299}
1e6c9c28
AV		 2300
2301/*
2302 * Interrupts are disabled on entering
2303 */
7192f92c 2304static void atmel_console_write(struct console *co, const char *s, u_int count)
1e6c9c28 2305{
7192f92c 2306 struct uart_port *port = &atmel_ports[co->index].uart;
e8faff73 2307 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
d358788f 2308 unsigned int status, imr;
39d4c922 2309 unsigned int pdc_tx;
1e6c9c28
AV		 2310
2311 /*
b843aa21 2312 * First, save IMR and then disable interrupts
1e6c9c28 2313 */
b843aa21 2314 imr = UART_GET_IMR(port);
e8faff73 2315 UART_PUT_IDR(port, ATMEL_US_RXRDY | atmel_port->tx_done_mask);
1e6c9c28 2316
39d4c922
MP		 2317 /* Store PDC transmit status and disable it */
2318 pdc_tx = UART_GET_PTSR(port) & ATMEL_PDC_TXTEN;
2319 UART_PUT_PTCR(port, ATMEL_PDC_TXTDIS);
2320
7192f92c 2321 uart_console_write(port, s, count, atmel_console_putchar);
1e6c9c28
AV		 2322
2323 /*
b843aa21
RB		 2324 * Finally, wait for transmitter to become empty
2325 * and restore IMR
1e6c9c28
AV		 2326 */
2327 do {
2328 status = UART_GET_CSR(port);
7192f92c 2329 } while (!(status & ATMEL_US_TXRDY));
39d4c922
MP		 2330
2331 /* Restore PDC transmit status */
2332 if (pdc_tx)
2333 UART_PUT_PTCR(port, ATMEL_PDC_TXTEN);
2334
b843aa21
RB		 2335 /* set interrupts back the way they were */
2336 UART_PUT_IER(port, imr);
1e6c9c28
AV		 2337}
2338
2339/*
b843aa21
RB		 2340 * If the port was already initialised (eg, by a boot loader),
2341 * try to determine the current setup.
1e6c9c28 2342 */
b843aa21
RB		 2343static void __init atmel_console_get_options(struct uart_port *port, int *baud,
2344 int *parity, int *bits)
1e6c9c28
AV		 2345{
2346 unsigned int mr, quot;
2347
1c0fd82f
HS		 2348 /*
2349 * If the baud rate generator isn't running, the port wasn't
2350 * initialized by the boot loader.
2351 */
9c81c5c9 2352 quot = UART_GET_BRGR(port) & ATMEL_US_CD;
1c0fd82f
HS		 2353 if (!quot)
2354 return;
1e6c9c28 2355
7192f92c
HS		 2356 mr = UART_GET_MR(port) & ATMEL_US_CHRL;
2357 if (mr == ATMEL_US_CHRL_8)
1e6c9c28
AV		 2358 *bits = 8;
2359 else
2360 *bits = 7;
2361
7192f92c
HS		 2362 mr = UART_GET_MR(port) & ATMEL_US_PAR;
2363 if (mr == ATMEL_US_PAR_EVEN)
1e6c9c28 2364 *parity = 'e';
7192f92c 2365 else if (mr == ATMEL_US_PAR_ODD)
1e6c9c28
AV		 2366 *parity = 'o';
2367
4d5e392c
HS		 2368 /*
2369 * The serial core only rounds down when matching this to a
2370 * supported baud rate. Make sure we don't end up slightly
2371 * lower than one of those, as it would make us fall through
2372 * to a much lower baud rate than we really want.
2373 */
4d5e392c 2374 *baud = port->uartclk / (16 * (quot - 1));
1e6c9c28
AV		 2375}
2376
7192f92c 2377static int __init atmel_console_setup(struct console *co, char *options)
1e6c9c28 2378{
91f8c2d8 2379 int ret;
7192f92c 2380 struct uart_port *port = &atmel_ports[co->index].uart;
1e6c9c28
AV		 2381 int baud = 115200;
2382 int bits = 8;
2383 int parity = 'n';
2384 int flow = 'n';
2385
b843aa21
RB		 2386 if (port->membase == NULL) {
2387 /* Port not initialized yet - delay setup */
afefc415 2388 return -ENODEV;
b843aa21 2389 }
1e6c9c28 2390
91f8c2d8
BB		 2391 ret = clk_prepare_enable(atmel_ports[co->index].clk);
2392 if (ret)
2393 return ret;
06a7f058 2394
b843aa21 2395 UART_PUT_IDR(port, -1);
7192f92c
HS		 2396 UART_PUT_CR(port, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
2397 UART_PUT_CR(port, ATMEL_US_TXEN | ATMEL_US_RXEN);
1e6c9c28
AV		 2398
2399 if (options)
2400 uart_parse_options(options, &baud, &parity, &bits, &flow);
2401 else
7192f92c 2402 atmel_console_get_options(port, &baud, &parity, &bits);
1e6c9c28
AV		 2403
2404 return uart_set_options(port, co, baud, parity, bits, flow);
2405}
2406
7192f92c 2407static struct uart_driver atmel_uart;
1e6c9c28 2408
7192f92c
HS		 2409static struct console atmel_console = {
2410 .name = ATMEL_DEVICENAME,
2411 .write = atmel_console_write,
1e6c9c28 2412 .device = uart_console_device,
7192f92c 2413 .setup = atmel_console_setup,
1e6c9c28
AV		 2414 .flags = CON_PRINTBUFFER,
2415 .index = -1,
7192f92c 2416 .data = &atmel_uart,
1e6c9c28
AV		 2417};
2418
06a7f058 2419#define ATMEL_CONSOLE_DEVICE (&atmel_console)
1e6c9c28 2420
afefc415
AV		 2421/*
2422 * Early console initialization (before VM subsystem initialized).
2423 */
7192f92c 2424static int __init atmel_console_init(void)
1e6c9c28 2425{
91f8c2d8 2426 int ret;
73e2798b 2427 if (atmel_default_console_device) {
0d0a3cc1 2428 struct atmel_uart_data *pdata =
574de559 2429 dev_get_platdata(&atmel_default_console_device->dev);
efb8d21b 2430 int id = pdata->num;
4cbf9f48
NF		 2431 struct atmel_uart_port *port = &atmel_ports[id];
2432
4cbf9f48
NF		 2433 port->backup_imr = 0;
2434 port->uart.line = id;
0d0a3cc1 2435
4cbf9f48 2436 add_preferred_console(ATMEL_DEVICENAME, id, NULL);
91f8c2d8
BB		 2437 ret = atmel_init_port(port, atmel_default_console_device);
2438 if (ret)
2439 return ret;
7192f92c 2440 register_console(&atmel_console);
afefc415 2441 }
1e6c9c28 2442
1e6c9c28
AV		 2443 return 0;
2444}
b843aa21 2445
7192f92c 2446console_initcall(atmel_console_init);
1e6c9c28 2447
afefc415
AV		 2448/*
2449 * Late console initialization.
2450 */
7192f92c 2451static int __init atmel_late_console_init(void)
afefc415 2452{
b843aa21
RB		 2453 if (atmel_default_console_device
2454 && !(atmel_console.flags & CON_ENABLED))
7192f92c 2455 register_console(&atmel_console);
afefc415
AV		 2456
2457 return 0;
2458}
b843aa21 2459
7192f92c 2460core_initcall(atmel_late_console_init);
afefc415 2461
dfa7f343
HS		 2462static inline bool atmel_is_console_port(struct uart_port *port)
2463{
2464 return port->cons && port->cons->index == port->line;
2465}
2466
1e6c9c28 2467#else
7192f92c 2468#define ATMEL_CONSOLE_DEVICE NULL
dfa7f343
HS		 2469
2470static inline bool atmel_is_console_port(struct uart_port *port)
2471{
2472 return false;
2473}
1e6c9c28
AV		 2474#endif
2475
7192f92c 2476static struct uart_driver atmel_uart = {
b843aa21
RB		 2477 .owner = THIS_MODULE,
2478 .driver_name = "atmel_serial",
2479 .dev_name = ATMEL_DEVICENAME,
2480 .major = SERIAL_ATMEL_MAJOR,
2481 .minor = MINOR_START,
2482 .nr = ATMEL_MAX_UART,
2483 .cons = ATMEL_CONSOLE_DEVICE,
1e6c9c28
AV		 2484};
2485
afefc415 2486#ifdef CONFIG_PM
f826caa4
HS		 2487static bool atmel_serial_clk_will_stop(void)
2488{
2489#ifdef CONFIG_ARCH_AT91
2490 return at91_suspend_entering_slow_clock();
2491#else
2492 return false;
2493#endif
2494}
2495
b843aa21
RB		 2496static int atmel_serial_suspend(struct platform_device *pdev,
2497 pm_message_t state)
1e6c9c28 2498{
afefc415 2499 struct uart_port *port = platform_get_drvdata(pdev);
c811ab8c 2500 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
afefc415 2501
e1c609ef
HS		 2502 if (atmel_is_console_port(port) && console_suspend_enabled) {
2503 /* Drain the TX shifter */
2504 while (!(UART_GET_CSR(port) & ATMEL_US_TXEMPTY))
2505 cpu_relax();
2506 }
2507
f05596db
AS		 2508 /* we can not wake up if we're running on slow clock */
2509 atmel_port->may_wakeup = device_may_wakeup(&pdev->dev);
2510 if (atmel_serial_clk_will_stop())
2511 device_set_wakeup_enable(&pdev->dev, 0);
2512
2513 uart_suspend_port(&atmel_uart, port);
1e6c9c28 2514
afefc415
AV		 2515 return 0;
2516}
1e6c9c28 2517
7192f92c 2518static int atmel_serial_resume(struct platform_device *pdev)
afefc415
AV		 2519{
2520 struct uart_port *port = platform_get_drvdata(pdev);
c811ab8c 2521 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1e6c9c28 2522
f05596db
AS		 2523 uart_resume_port(&atmel_uart, port);
2524 device_set_wakeup_enable(&pdev->dev, atmel_port->may_wakeup);
1e6c9c28
AV		 2525
2526 return 0;
2527}
afefc415 2528#else
7192f92c
HS		 2529#define atmel_serial_suspend NULL
2530#define atmel_serial_resume NULL
afefc415 2531#endif
1e6c9c28 2532
e0b0baad
RG		 2533static int atmel_init_gpios(struct atmel_uart_port *p, struct device *dev)
2534{
ab5e4e41
RG		 2535 enum mctrl_gpio_idx i;
2536 struct gpio_desc *gpiod;
2537
e0b0baad
RG		 2538 p->gpios = mctrl_gpio_init(dev, 0);
2539 if (IS_ERR_OR_NULL(p->gpios))
2540 return -1;
2541
ab5e4e41
RG		 2542 for (i = 0; i < UART_GPIO_MAX; i++) {
2543 gpiod = mctrl_gpio_to_gpiod(p->gpios, i);
2544 if (gpiod && (gpiod_get_direction(gpiod) == GPIOF_DIR_IN))
2545 p->gpio_irq[i] = gpiod_to_irq(gpiod);
2546 else
2547 p->gpio_irq[i] = -EINVAL;
2548 }
2549
e0b0baad
RG		 2550 return 0;
2551}
2552
9671f099 2553static int atmel_serial_probe(struct platform_device *pdev)
1e6c9c28 2554{
7192f92c 2555 struct atmel_uart_port *port;
5fbe46b6 2556 struct device_node *np = pdev->dev.of_node;
574de559 2557 struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev);
1ecc26bd 2558 void *data;
4cbf9f48 2559 int ret = -ENODEV;
1e6c9c28 2560
9d09daf8 2561 BUILD_BUG_ON(ATMEL_SERIAL_RINGSIZE & (ATMEL_SERIAL_RINGSIZE - 1));
1ecc26bd 2562
5fbe46b6
NF		 2563 if (np)
2564 ret = of_alias_get_id(np, "serial");
2565 else
2566 if (pdata)
2567 ret = pdata->num;
4cbf9f48
NF		 2568
2569 if (ret < 0)
5fbe46b6 2570 /* port id not found in platform data nor device-tree aliases:
4cbf9f48 2571 * auto-enumerate it */
503bded9 2572 ret = find_first_zero_bit(atmel_ports_in_use, ATMEL_MAX_UART);
4cbf9f48 2573
503bded9 2574 if (ret >= ATMEL_MAX_UART) {
4cbf9f48
NF		 2575 ret = -ENODEV;
2576 goto err;
2577 }
2578
503bded9 2579 if (test_and_set_bit(ret, atmel_ports_in_use)) {
4cbf9f48
NF		 2580 /* port already in use */
2581 ret = -EBUSY;
2582 goto err;
2583 }
2584
2585 port = &atmel_ports[ret];
f05596db 2586 port->backup_imr = 0;
4cbf9f48 2587 port->uart.line = ret;
e0b0baad
RG		 2588
2589 ret = atmel_init_gpios(port, &pdev->dev);
2590 if (ret < 0)
2591 dev_err(&pdev->dev, "%s",
2592 "Failed to initialize GPIOs. The serial port may not work as expected");
f05596db 2593
91f8c2d8
BB		 2594 ret = atmel_init_port(port, pdev);
2595 if (ret)
2596 goto err;
1e6c9c28 2597
64e22ebe 2598 if (!atmel_use_pdc_rx(&port->uart)) {
a6670615 2599 ret = -ENOMEM;
6433471d
HS		 2600 data = kmalloc(sizeof(struct atmel_uart_char)
2601 * ATMEL_SERIAL_RINGSIZE, GFP_KERNEL);
a6670615
CC		 2602 if (!data)
2603 goto err_alloc_ring;
2604 port->rx_ring.buf = data;
2605 }
1ecc26bd 2606
7192f92c 2607 ret = uart_add_one_port(&atmel_uart, &port->uart);
dfa7f343
HS		 2608 if (ret)
2609 goto err_add_port;
2610
8da14b5f 2611#ifdef CONFIG_SERIAL_ATMEL_CONSOLE
06a7f058
DB		 2612 if (atmel_is_console_port(&port->uart)
2613 && ATMEL_CONSOLE_DEVICE->flags & CON_ENABLED) {
2614 /*
2615 * The serial core enabled the clock for us, so undo
91f8c2d8 2616 * the clk_prepare_enable() in atmel_console_setup()
06a7f058 2617 */
91f8c2d8 2618 clk_disable_unprepare(port->clk);
06a7f058 2619 }
8da14b5f 2620#endif
06a7f058 2621
dfa7f343
HS		 2622 device_init_wakeup(&pdev->dev, 1);
2623 platform_set_drvdata(pdev, port);
2624
5dfbd1d7
CS		 2625 if (port->rs485.flags & SER_RS485_ENABLED) {
2626 UART_PUT_MR(&port->uart, ATMEL_US_USMODE_NORMAL);
2627 UART_PUT_CR(&port->uart, ATMEL_US_RTSEN);
2628 }
2629
055560b0
ES		 2630 /*
2631 * Get port name of usart or uart
2632 */
892db58b 2633 atmel_get_ip_name(&port->uart);
055560b0 2634
dfa7f343
HS		 2635 return 0;
2636
2637err_add_port:
1ecc26bd
RB		 2638 kfree(port->rx_ring.buf);
2639 port->rx_ring.buf = NULL;
2640err_alloc_ring:
dfa7f343 2641 if (!atmel_is_console_port(&port->uart)) {
dfa7f343
HS		 2642 clk_put(port->clk);
2643 port->clk = NULL;
afefc415 2644 }
4cbf9f48 2645err:
afefc415
AV		 2646 return ret;
2647}
2648
ae8d8a14 2649static int atmel_serial_remove(struct platform_device *pdev)
afefc415
AV		 2650{
2651 struct uart_port *port = platform_get_drvdata(pdev);
c811ab8c 2652 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
afefc415
AV		 2653 int ret = 0;
2654
f50c995f
MR		 2655 tasklet_kill(&atmel_port->tasklet);
2656
afefc415 2657 device_init_wakeup(&pdev->dev, 0);
afefc415 2658
dfa7f343
HS		 2659 ret = uart_remove_one_port(&atmel_uart, port);
2660
1ecc26bd
RB		 2661 kfree(atmel_port->rx_ring.buf);
2662
dfa7f343
HS		 2663 /* "port" is allocated statically, so we shouldn't free it */
2664
503bded9 2665 clear_bit(port->line, atmel_ports_in_use);
4cbf9f48 2666
dfa7f343 2667 clk_put(atmel_port->clk);
afefc415
AV		 2668
2669 return ret;
2670}
2671
7192f92c
HS		 2672static struct platform_driver atmel_serial_driver = {
2673 .probe = atmel_serial_probe,
2d47b716 2674 .remove = atmel_serial_remove,
7192f92c
HS		 2675 .suspend = atmel_serial_suspend,
2676 .resume = atmel_serial_resume,
afefc415 2677 .driver = {
1e8ea802 2678 .name = "atmel_usart",
afefc415 2679 .owner = THIS_MODULE,
5fbe46b6 2680 .of_match_table = of_match_ptr(atmel_serial_dt_ids),
afefc415
AV		 2681 },
2682};
2683
7192f92c 2684static int __init atmel_serial_init(void)
afefc415
AV		 2685{
2686 int ret;
2687
7192f92c 2688 ret = uart_register_driver(&atmel_uart);
afefc415
AV		 2689 if (ret)
2690 return ret;
2691
7192f92c 2692 ret = platform_driver_register(&atmel_serial_driver);
afefc415 2693 if (ret)
7192f92c 2694 uart_unregister_driver(&atmel_uart);
afefc415
AV		 2695
2696 return ret;
2697}
2698
7192f92c 2699static void __exit atmel_serial_exit(void)
afefc415 2700{
7192f92c
HS		 2701 platform_driver_unregister(&atmel_serial_driver);
2702 uart_unregister_driver(&atmel_uart);
1e6c9c28
AV		 2703}
2704
7192f92c
HS		 2705module_init(atmel_serial_init);
2706module_exit(atmel_serial_exit);
1e6c9c28
AV		 2707
2708MODULE_AUTHOR("Rick Bronson");
7192f92c 2709MODULE_DESCRIPTION("Atmel AT91 / AT32 serial port driver");
1e6c9c28 2710MODULE_LICENSE("GPL");
e169c139 2711MODULE_ALIAS("platform:atmel_usart");
Linux 6.x block layer and io_uring tree(s)