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1e6c9c28 | 1 | /* |
7192f92c | 2 | * Driver for Atmel AT91 / AT32 Serial ports |
1e6c9c28 AV |
3 | * Copyright (C) 2003 Rick Bronson |
4 | * | |
5 | * Based on drivers/char/serial_sa1100.c, by Deep Blue Solutions Ltd. | |
6 | * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. | |
7 | * | |
a6670615 CC |
8 | * DMA support added by Chip Coldwell. |
9 | * | |
1e6c9c28 AV |
10 | * This program is free software; you can redistribute it and/or modify |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; either version 2 of the License, or | |
13 | * (at your option) any later version. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | * GNU General Public License for more details. | |
19 | * | |
20 | * You should have received a copy of the GNU General Public License | |
21 | * along with this program; if not, write to the Free Software | |
22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
23 | * | |
24 | */ | |
1e6c9c28 AV |
25 | #include <linux/module.h> |
26 | #include <linux/tty.h> | |
27 | #include <linux/ioport.h> | |
28 | #include <linux/slab.h> | |
29 | #include <linux/init.h> | |
30 | #include <linux/serial.h> | |
afefc415 | 31 | #include <linux/clk.h> |
1e6c9c28 AV |
32 | #include <linux/console.h> |
33 | #include <linux/sysrq.h> | |
34 | #include <linux/tty_flip.h> | |
afefc415 | 35 | #include <linux/platform_device.h> |
5fbe46b6 NF |
36 | #include <linux/of.h> |
37 | #include <linux/of_device.h> | |
354e57f3 | 38 | #include <linux/of_gpio.h> |
a6670615 | 39 | #include <linux/dma-mapping.h> |
6b997bab | 40 | #include <linux/dmaengine.h> |
93a3ddc2 | 41 | #include <linux/atmel_pdc.h> |
fa3218d8 | 42 | #include <linux/atmel_serial.h> |
e8faff73 | 43 | #include <linux/uaccess.h> |
bcd2360c | 44 | #include <linux/platform_data/atmel.h> |
2e68c22f | 45 | #include <linux/timer.h> |
354e57f3 | 46 | #include <linux/gpio.h> |
e0b0baad RG |
47 | #include <linux/gpio/consumer.h> |
48 | #include <linux/err.h> | |
ab5e4e41 | 49 | #include <linux/irq.h> |
1e6c9c28 AV |
50 | |
51 | #include <asm/io.h> | |
f7512e7c | 52 | #include <asm/ioctls.h> |
1e6c9c28 | 53 | |
a6670615 CC |
54 | #define PDC_BUFFER_SIZE 512 |
55 | /* Revisit: We should calculate this based on the actual port settings */ | |
56 | #define PDC_RX_TIMEOUT (3 * 10) /* 3 bytes */ | |
57 | ||
749c4e60 | 58 | #if defined(CONFIG_SERIAL_ATMEL_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) |
1e6c9c28 AV |
59 | #define SUPPORT_SYSRQ |
60 | #endif | |
61 | ||
62 | #include <linux/serial_core.h> | |
63 | ||
e0b0baad RG |
64 | #include "serial_mctrl_gpio.h" |
65 | ||
e8faff73 CS |
66 | static void atmel_start_rx(struct uart_port *port); |
67 | static void atmel_stop_rx(struct uart_port *port); | |
68 | ||
749c4e60 | 69 | #ifdef CONFIG_SERIAL_ATMEL_TTYAT |
1e6c9c28 AV |
70 | |
71 | /* Use device name ttyAT, major 204 and minor 154-169. This is necessary if we | |
72 | * should coexist with the 8250 driver, such as if we have an external 16C550 | |
73 | * UART. */ | |
7192f92c | 74 | #define SERIAL_ATMEL_MAJOR 204 |
1e6c9c28 | 75 | #define MINOR_START 154 |
7192f92c | 76 | #define ATMEL_DEVICENAME "ttyAT" |
1e6c9c28 AV |
77 | |
78 | #else | |
79 | ||
80 | /* Use device name ttyS, major 4, minor 64-68. This is the usual serial port | |
81 | * name, but it is legally reserved for the 8250 driver. */ | |
7192f92c | 82 | #define SERIAL_ATMEL_MAJOR TTY_MAJOR |
1e6c9c28 | 83 | #define MINOR_START 64 |
7192f92c | 84 | #define ATMEL_DEVICENAME "ttyS" |
1e6c9c28 AV |
85 | |
86 | #endif | |
87 | ||
7192f92c | 88 | #define ATMEL_ISR_PASS_LIMIT 256 |
1e6c9c28 | 89 | |
b843aa21 | 90 | /* UART registers. CR is write-only, hence no GET macro */ |
544fc728 HS |
91 | #define UART_PUT_CR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_CR) |
92 | #define UART_GET_MR(port) __raw_readl((port)->membase + ATMEL_US_MR) | |
93 | #define UART_PUT_MR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_MR) | |
94 | #define UART_PUT_IER(port,v) __raw_writel(v, (port)->membase + ATMEL_US_IER) | |
95 | #define UART_PUT_IDR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_IDR) | |
96 | #define UART_GET_IMR(port) __raw_readl((port)->membase + ATMEL_US_IMR) | |
97 | #define UART_GET_CSR(port) __raw_readl((port)->membase + ATMEL_US_CSR) | |
98 | #define UART_GET_CHAR(port) __raw_readl((port)->membase + ATMEL_US_RHR) | |
99 | #define UART_PUT_CHAR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_THR) | |
100 | #define UART_GET_BRGR(port) __raw_readl((port)->membase + ATMEL_US_BRGR) | |
101 | #define UART_PUT_BRGR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_BRGR) | |
102 | #define UART_PUT_RTOR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_RTOR) | |
e8faff73 | 103 | #define UART_PUT_TTGR(port, v) __raw_writel(v, (port)->membase + ATMEL_US_TTGR) |
055560b0 | 104 | #define UART_GET_IP_NAME(port) __raw_readl((port)->membase + ATMEL_US_NAME) |
731d9cae | 105 | #define UART_GET_IP_VERSION(port) __raw_readl((port)->membase + ATMEL_US_VERSION) |
544fc728 | 106 | |
1e6c9c28 | 107 | /* PDC registers */ |
544fc728 HS |
108 | #define UART_PUT_PTCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_PTCR) |
109 | #define UART_GET_PTSR(port) __raw_readl((port)->membase + ATMEL_PDC_PTSR) | |
110 | ||
111 | #define UART_PUT_RPR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RPR) | |
112 | #define UART_GET_RPR(port) __raw_readl((port)->membase + ATMEL_PDC_RPR) | |
113 | #define UART_PUT_RCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RCR) | |
114 | #define UART_PUT_RNPR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RNPR) | |
115 | #define UART_PUT_RNCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RNCR) | |
116 | ||
117 | #define UART_PUT_TPR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_TPR) | |
118 | #define UART_PUT_TCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_TCR) | |
39d4c922 | 119 | #define UART_GET_TCR(port) __raw_readl((port)->membase + ATMEL_PDC_TCR) |
1e6c9c28 | 120 | |
a6670615 CC |
121 | struct atmel_dma_buffer { |
122 | unsigned char *buf; | |
123 | dma_addr_t dma_addr; | |
124 | unsigned int dma_size; | |
125 | unsigned int ofs; | |
126 | }; | |
127 | ||
1ecc26bd RB |
128 | struct atmel_uart_char { |
129 | u16 status; | |
130 | u16 ch; | |
131 | }; | |
132 | ||
133 | #define ATMEL_SERIAL_RINGSIZE 1024 | |
134 | ||
afefc415 AV |
135 | /* |
136 | * We wrap our port structure around the generic uart_port. | |
137 | */ | |
7192f92c | 138 | struct atmel_uart_port { |
afefc415 AV |
139 | struct uart_port uart; /* uart */ |
140 | struct clk *clk; /* uart clock */ | |
f05596db AS |
141 | int may_wakeup; /* cached value of device_may_wakeup for times we need to disable it */ |
142 | u32 backup_imr; /* IMR saved during suspend */ | |
9e6077bd | 143 | int break_active; /* break being received */ |
1ecc26bd | 144 | |
34df42f5 | 145 | bool use_dma_rx; /* enable DMA receiver */ |
64e22ebe | 146 | bool use_pdc_rx; /* enable PDC receiver */ |
a6670615 CC |
147 | short pdc_rx_idx; /* current PDC RX buffer */ |
148 | struct atmel_dma_buffer pdc_rx[2]; /* PDC receier */ | |
149 | ||
08f738be | 150 | bool use_dma_tx; /* enable DMA transmitter */ |
64e22ebe | 151 | bool use_pdc_tx; /* enable PDC transmitter */ |
a6670615 CC |
152 | struct atmel_dma_buffer pdc_tx; /* PDC transmitter */ |
153 | ||
08f738be | 154 | spinlock_t lock_tx; /* port lock */ |
34df42f5 | 155 | spinlock_t lock_rx; /* port lock */ |
08f738be | 156 | struct dma_chan *chan_tx; |
34df42f5 | 157 | struct dma_chan *chan_rx; |
08f738be | 158 | struct dma_async_tx_descriptor *desc_tx; |
34df42f5 | 159 | struct dma_async_tx_descriptor *desc_rx; |
08f738be | 160 | dma_cookie_t cookie_tx; |
34df42f5 | 161 | dma_cookie_t cookie_rx; |
08f738be | 162 | struct scatterlist sg_tx; |
34df42f5 | 163 | struct scatterlist sg_rx; |
1ecc26bd RB |
164 | struct tasklet_struct tasklet; |
165 | unsigned int irq_status; | |
166 | unsigned int irq_status_prev; | |
167 | ||
168 | struct circ_buf rx_ring; | |
e8faff73 | 169 | |
e0b0baad | 170 | struct mctrl_gpios *gpios; |
ab5e4e41 | 171 | int gpio_irq[UART_GPIO_MAX]; |
e8faff73 | 172 | unsigned int tx_done_mask; |
ab5e4e41 | 173 | bool ms_irq_enabled; |
055560b0 | 174 | bool is_usart; /* usart or uart */ |
2e68c22f | 175 | struct timer_list uart_timer; /* uart timer */ |
a930e528 ES |
176 | int (*prepare_rx)(struct uart_port *port); |
177 | int (*prepare_tx)(struct uart_port *port); | |
178 | void (*schedule_rx)(struct uart_port *port); | |
179 | void (*schedule_tx)(struct uart_port *port); | |
180 | void (*release_rx)(struct uart_port *port); | |
181 | void (*release_tx)(struct uart_port *port); | |
afefc415 AV |
182 | }; |
183 | ||
7192f92c | 184 | static struct atmel_uart_port atmel_ports[ATMEL_MAX_UART]; |
503bded9 | 185 | static DECLARE_BITMAP(atmel_ports_in_use, ATMEL_MAX_UART); |
afefc415 | 186 | |
1e6c9c28 | 187 | #ifdef SUPPORT_SYSRQ |
7192f92c | 188 | static struct console atmel_console; |
1e6c9c28 AV |
189 | #endif |
190 | ||
5fbe46b6 NF |
191 | #if defined(CONFIG_OF) |
192 | static const struct of_device_id atmel_serial_dt_ids[] = { | |
193 | { .compatible = "atmel,at91rm9200-usart" }, | |
194 | { .compatible = "atmel,at91sam9260-usart" }, | |
195 | { /* sentinel */ } | |
196 | }; | |
197 | ||
198 | MODULE_DEVICE_TABLE(of, atmel_serial_dt_ids); | |
199 | #endif | |
200 | ||
c811ab8c HS |
201 | static inline struct atmel_uart_port * |
202 | to_atmel_uart_port(struct uart_port *uart) | |
203 | { | |
204 | return container_of(uart, struct atmel_uart_port, uart); | |
205 | } | |
206 | ||
a6670615 | 207 | #ifdef CONFIG_SERIAL_ATMEL_PDC |
64e22ebe | 208 | static bool atmel_use_pdc_rx(struct uart_port *port) |
a6670615 | 209 | { |
c811ab8c | 210 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
a6670615 | 211 | |
64e22ebe | 212 | return atmel_port->use_pdc_rx; |
a6670615 CC |
213 | } |
214 | ||
64e22ebe | 215 | static bool atmel_use_pdc_tx(struct uart_port *port) |
a6670615 | 216 | { |
c811ab8c | 217 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
a6670615 | 218 | |
64e22ebe | 219 | return atmel_port->use_pdc_tx; |
a6670615 CC |
220 | } |
221 | #else | |
64e22ebe | 222 | static bool atmel_use_pdc_rx(struct uart_port *port) |
a6670615 CC |
223 | { |
224 | return false; | |
225 | } | |
226 | ||
64e22ebe | 227 | static bool atmel_use_pdc_tx(struct uart_port *port) |
a6670615 CC |
228 | { |
229 | return false; | |
230 | } | |
231 | #endif | |
232 | ||
08f738be ES |
233 | static bool atmel_use_dma_tx(struct uart_port *port) |
234 | { | |
235 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); | |
236 | ||
237 | return atmel_port->use_dma_tx; | |
238 | } | |
239 | ||
34df42f5 ES |
240 | static bool atmel_use_dma_rx(struct uart_port *port) |
241 | { | |
242 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); | |
243 | ||
244 | return atmel_port->use_dma_rx; | |
245 | } | |
246 | ||
e0b0baad RG |
247 | static unsigned int atmel_get_lines_status(struct uart_port *port) |
248 | { | |
249 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); | |
250 | unsigned int status, ret = 0; | |
251 | ||
252 | status = UART_GET_CSR(port); | |
253 | ||
254 | mctrl_gpio_get(atmel_port->gpios, &ret); | |
255 | ||
256 | if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios, | |
257 | UART_GPIO_CTS))) { | |
258 | if (ret & TIOCM_CTS) | |
259 | status &= ~ATMEL_US_CTS; | |
260 | else | |
261 | status |= ATMEL_US_CTS; | |
262 | } | |
263 | ||
264 | if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios, | |
265 | UART_GPIO_DSR))) { | |
266 | if (ret & TIOCM_DSR) | |
267 | status &= ~ATMEL_US_DSR; | |
268 | else | |
269 | status |= ATMEL_US_DSR; | |
270 | } | |
271 | ||
272 | if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios, | |
273 | UART_GPIO_RI))) { | |
274 | if (ret & TIOCM_RI) | |
275 | status &= ~ATMEL_US_RI; | |
276 | else | |
277 | status |= ATMEL_US_RI; | |
278 | } | |
279 | ||
280 | if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios, | |
281 | UART_GPIO_DCD))) { | |
282 | if (ret & TIOCM_CD) | |
283 | status &= ~ATMEL_US_DCD; | |
284 | else | |
285 | status |= ATMEL_US_DCD; | |
286 | } | |
287 | ||
288 | return status; | |
289 | } | |
290 | ||
e8faff73 | 291 | /* Enable or disable the rs485 support */ |
13bd3e6f RRD |
292 | static int atmel_config_rs485(struct uart_port *port, |
293 | struct serial_rs485 *rs485conf) | |
e8faff73 CS |
294 | { |
295 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); | |
296 | unsigned int mode; | |
e8faff73 CS |
297 | |
298 | /* Disable interrupts */ | |
299 | UART_PUT_IDR(port, atmel_port->tx_done_mask); | |
300 | ||
301 | mode = UART_GET_MR(port); | |
302 | ||
303 | /* Resetting serial mode to RS232 (0x0) */ | |
304 | mode &= ~ATMEL_US_USMODE; | |
305 | ||
13bd3e6f | 306 | port->rs485 = *rs485conf; |
e8faff73 CS |
307 | |
308 | if (rs485conf->flags & SER_RS485_ENABLED) { | |
309 | dev_dbg(port->dev, "Setting UART to RS485\n"); | |
310 | atmel_port->tx_done_mask = ATMEL_US_TXEMPTY; | |
93f3350c | 311 | if ((rs485conf->delay_rts_after_send) > 0) |
1b633184 | 312 | UART_PUT_TTGR(port, rs485conf->delay_rts_after_send); |
e8faff73 CS |
313 | mode |= ATMEL_US_USMODE_RS485; |
314 | } else { | |
315 | dev_dbg(port->dev, "Setting UART to RS232\n"); | |
64e22ebe | 316 | if (atmel_use_pdc_tx(port)) |
e8faff73 CS |
317 | atmel_port->tx_done_mask = ATMEL_US_ENDTX | |
318 | ATMEL_US_TXBUFE; | |
319 | else | |
320 | atmel_port->tx_done_mask = ATMEL_US_TXRDY; | |
321 | } | |
322 | UART_PUT_MR(port, mode); | |
323 | ||
324 | /* Enable interrupts */ | |
325 | UART_PUT_IER(port, atmel_port->tx_done_mask); | |
326 | ||
13bd3e6f | 327 | return 0; |
e8faff73 CS |
328 | } |
329 | ||
1e6c9c28 AV |
330 | /* |
331 | * Return TIOCSER_TEMT when transmitter FIFO and Shift register is empty. | |
332 | */ | |
7192f92c | 333 | static u_int atmel_tx_empty(struct uart_port *port) |
1e6c9c28 | 334 | { |
7192f92c | 335 | return (UART_GET_CSR(port) & ATMEL_US_TXEMPTY) ? TIOCSER_TEMT : 0; |
1e6c9c28 AV |
336 | } |
337 | ||
338 | /* | |
339 | * Set state of the modem control output lines | |
340 | */ | |
7192f92c | 341 | static void atmel_set_mctrl(struct uart_port *port, u_int mctrl) |
1e6c9c28 AV |
342 | { |
343 | unsigned int control = 0; | |
1cf6e8fc CP |
344 | unsigned int mode = UART_GET_MR(port); |
345 | unsigned int rts_paused, rts_ready; | |
e8faff73 | 346 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
1e6c9c28 | 347 | |
1cf6e8fc CP |
348 | /* override mode to RS485 if needed, otherwise keep the current mode */ |
349 | if (port->rs485.flags & SER_RS485_ENABLED) { | |
350 | if ((port->rs485.delay_rts_after_send) > 0) | |
351 | UART_PUT_TTGR(port, port->rs485.delay_rts_after_send); | |
352 | mode &= ~ATMEL_US_USMODE; | |
353 | mode |= ATMEL_US_USMODE_RS485; | |
354 | } | |
355 | ||
356 | /* set the RTS line state according to the mode */ | |
357 | if ((mode & ATMEL_US_USMODE) == ATMEL_US_USMODE_HWHS) { | |
358 | /* force RTS line to high level */ | |
359 | rts_paused = ATMEL_US_RTSEN; | |
360 | ||
361 | /* give the control of the RTS line back to the hardware */ | |
362 | rts_ready = ATMEL_US_RTSDIS; | |
363 | } else { | |
364 | /* force RTS line to high level */ | |
365 | rts_paused = ATMEL_US_RTSDIS; | |
366 | ||
367 | /* force RTS line to low level */ | |
368 | rts_ready = ATMEL_US_RTSEN; | |
369 | } | |
370 | ||
1e6c9c28 | 371 | if (mctrl & TIOCM_RTS) |
1cf6e8fc | 372 | control |= rts_ready; |
1e6c9c28 | 373 | else |
1cf6e8fc | 374 | control |= rts_paused; |
1e6c9c28 AV |
375 | |
376 | if (mctrl & TIOCM_DTR) | |
7192f92c | 377 | control |= ATMEL_US_DTREN; |
1e6c9c28 | 378 | else |
7192f92c | 379 | control |= ATMEL_US_DTRDIS; |
1e6c9c28 | 380 | |
afefc415 AV |
381 | UART_PUT_CR(port, control); |
382 | ||
e0b0baad RG |
383 | mctrl_gpio_set(atmel_port->gpios, mctrl); |
384 | ||
afefc415 | 385 | /* Local loopback mode? */ |
1cf6e8fc | 386 | mode &= ~ATMEL_US_CHMODE; |
afefc415 | 387 | if (mctrl & TIOCM_LOOP) |
7192f92c | 388 | mode |= ATMEL_US_CHMODE_LOC_LOOP; |
afefc415 | 389 | else |
7192f92c | 390 | mode |= ATMEL_US_CHMODE_NORMAL; |
e8faff73 | 391 | |
afefc415 | 392 | UART_PUT_MR(port, mode); |
1e6c9c28 AV |
393 | } |
394 | ||
395 | /* | |
396 | * Get state of the modem control input lines | |
397 | */ | |
7192f92c | 398 | static u_int atmel_get_mctrl(struct uart_port *port) |
1e6c9c28 | 399 | { |
e0b0baad RG |
400 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
401 | unsigned int ret = 0, status; | |
1e6c9c28 AV |
402 | |
403 | status = UART_GET_CSR(port); | |
404 | ||
405 | /* | |
406 | * The control signals are active low. | |
407 | */ | |
7192f92c | 408 | if (!(status & ATMEL_US_DCD)) |
1e6c9c28 | 409 | ret |= TIOCM_CD; |
7192f92c | 410 | if (!(status & ATMEL_US_CTS)) |
1e6c9c28 | 411 | ret |= TIOCM_CTS; |
7192f92c | 412 | if (!(status & ATMEL_US_DSR)) |
1e6c9c28 | 413 | ret |= TIOCM_DSR; |
7192f92c | 414 | if (!(status & ATMEL_US_RI)) |
1e6c9c28 AV |
415 | ret |= TIOCM_RI; |
416 | ||
e0b0baad | 417 | return mctrl_gpio_get(atmel_port->gpios, &ret); |
1e6c9c28 AV |
418 | } |
419 | ||
420 | /* | |
421 | * Stop transmitting. | |
422 | */ | |
7192f92c | 423 | static void atmel_stop_tx(struct uart_port *port) |
1e6c9c28 | 424 | { |
e8faff73 CS |
425 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
426 | ||
64e22ebe | 427 | if (atmel_use_pdc_tx(port)) { |
a6670615 CC |
428 | /* disable PDC transmit */ |
429 | UART_PUT_PTCR(port, ATMEL_PDC_TXTDIS); | |
e8faff73 CS |
430 | } |
431 | /* Disable interrupts */ | |
432 | UART_PUT_IDR(port, atmel_port->tx_done_mask); | |
433 | ||
13bd3e6f RRD |
434 | if ((port->rs485.flags & SER_RS485_ENABLED) && |
435 | !(port->rs485.flags & SER_RS485_RX_DURING_TX)) | |
e8faff73 | 436 | atmel_start_rx(port); |
1e6c9c28 AV |
437 | } |
438 | ||
439 | /* | |
440 | * Start transmitting. | |
441 | */ | |
7192f92c | 442 | static void atmel_start_tx(struct uart_port *port) |
1e6c9c28 | 443 | { |
e8faff73 CS |
444 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
445 | ||
64e22ebe | 446 | if (atmel_use_pdc_tx(port)) { |
a6670615 CC |
447 | if (UART_GET_PTSR(port) & ATMEL_PDC_TXTEN) |
448 | /* The transmitter is already running. Yes, we | |
449 | really need this.*/ | |
450 | return; | |
451 | ||
13bd3e6f RRD |
452 | if ((port->rs485.flags & SER_RS485_ENABLED) && |
453 | !(port->rs485.flags & SER_RS485_RX_DURING_TX)) | |
e8faff73 CS |
454 | atmel_stop_rx(port); |
455 | ||
a6670615 CC |
456 | /* re-enable PDC transmit */ |
457 | UART_PUT_PTCR(port, ATMEL_PDC_TXTEN); | |
e8faff73 CS |
458 | } |
459 | /* Enable interrupts */ | |
460 | UART_PUT_IER(port, atmel_port->tx_done_mask); | |
461 | } | |
462 | ||
463 | /* | |
464 | * start receiving - port is in process of being opened. | |
465 | */ | |
466 | static void atmel_start_rx(struct uart_port *port) | |
467 | { | |
468 | UART_PUT_CR(port, ATMEL_US_RSTSTA); /* reset status and receiver */ | |
469 | ||
57c36868 SG |
470 | UART_PUT_CR(port, ATMEL_US_RXEN); |
471 | ||
64e22ebe | 472 | if (atmel_use_pdc_rx(port)) { |
e8faff73 CS |
473 | /* enable PDC controller */ |
474 | UART_PUT_IER(port, ATMEL_US_ENDRX | ATMEL_US_TIMEOUT | | |
475 | port->read_status_mask); | |
476 | UART_PUT_PTCR(port, ATMEL_PDC_RXTEN); | |
477 | } else { | |
478 | UART_PUT_IER(port, ATMEL_US_RXRDY); | |
479 | } | |
1e6c9c28 AV |
480 | } |
481 | ||
482 | /* | |
483 | * Stop receiving - port is in process of being closed. | |
484 | */ | |
7192f92c | 485 | static void atmel_stop_rx(struct uart_port *port) |
1e6c9c28 | 486 | { |
57c36868 SG |
487 | UART_PUT_CR(port, ATMEL_US_RXDIS); |
488 | ||
64e22ebe | 489 | if (atmel_use_pdc_rx(port)) { |
a6670615 CC |
490 | /* disable PDC receive */ |
491 | UART_PUT_PTCR(port, ATMEL_PDC_RXTDIS); | |
e8faff73 CS |
492 | UART_PUT_IDR(port, ATMEL_US_ENDRX | ATMEL_US_TIMEOUT | |
493 | port->read_status_mask); | |
494 | } else { | |
a6670615 | 495 | UART_PUT_IDR(port, ATMEL_US_RXRDY); |
e8faff73 | 496 | } |
1e6c9c28 AV |
497 | } |
498 | ||
499 | /* | |
500 | * Enable modem status interrupts | |
501 | */ | |
7192f92c | 502 | static void atmel_enable_ms(struct uart_port *port) |
1e6c9c28 | 503 | { |
ab5e4e41 RG |
504 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
505 | uint32_t ier = 0; | |
506 | ||
507 | /* | |
508 | * Interrupt should not be enabled twice | |
509 | */ | |
510 | if (atmel_port->ms_irq_enabled) | |
511 | return; | |
512 | ||
513 | atmel_port->ms_irq_enabled = true; | |
514 | ||
515 | if (atmel_port->gpio_irq[UART_GPIO_CTS] >= 0) | |
516 | enable_irq(atmel_port->gpio_irq[UART_GPIO_CTS]); | |
517 | else | |
518 | ier |= ATMEL_US_CTSIC; | |
519 | ||
520 | if (atmel_port->gpio_irq[UART_GPIO_DSR] >= 0) | |
521 | enable_irq(atmel_port->gpio_irq[UART_GPIO_DSR]); | |
522 | else | |
523 | ier |= ATMEL_US_DSRIC; | |
524 | ||
525 | if (atmel_port->gpio_irq[UART_GPIO_RI] >= 0) | |
526 | enable_irq(atmel_port->gpio_irq[UART_GPIO_RI]); | |
527 | else | |
528 | ier |= ATMEL_US_RIIC; | |
529 | ||
530 | if (atmel_port->gpio_irq[UART_GPIO_DCD] >= 0) | |
531 | enable_irq(atmel_port->gpio_irq[UART_GPIO_DCD]); | |
532 | else | |
533 | ier |= ATMEL_US_DCDIC; | |
534 | ||
535 | UART_PUT_IER(port, ier); | |
1e6c9c28 AV |
536 | } |
537 | ||
35b675b9 RG |
538 | /* |
539 | * Disable modem status interrupts | |
540 | */ | |
541 | static void atmel_disable_ms(struct uart_port *port) | |
542 | { | |
543 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); | |
544 | uint32_t idr = 0; | |
545 | ||
546 | /* | |
547 | * Interrupt should not be disabled twice | |
548 | */ | |
549 | if (!atmel_port->ms_irq_enabled) | |
550 | return; | |
551 | ||
552 | atmel_port->ms_irq_enabled = false; | |
553 | ||
554 | if (atmel_port->gpio_irq[UART_GPIO_CTS] >= 0) | |
555 | disable_irq(atmel_port->gpio_irq[UART_GPIO_CTS]); | |
556 | else | |
557 | idr |= ATMEL_US_CTSIC; | |
558 | ||
559 | if (atmel_port->gpio_irq[UART_GPIO_DSR] >= 0) | |
560 | disable_irq(atmel_port->gpio_irq[UART_GPIO_DSR]); | |
561 | else | |
562 | idr |= ATMEL_US_DSRIC; | |
563 | ||
564 | if (atmel_port->gpio_irq[UART_GPIO_RI] >= 0) | |
565 | disable_irq(atmel_port->gpio_irq[UART_GPIO_RI]); | |
566 | else | |
567 | idr |= ATMEL_US_RIIC; | |
568 | ||
569 | if (atmel_port->gpio_irq[UART_GPIO_DCD] >= 0) | |
570 | disable_irq(atmel_port->gpio_irq[UART_GPIO_DCD]); | |
571 | else | |
572 | idr |= ATMEL_US_DCDIC; | |
573 | ||
574 | UART_PUT_IDR(port, idr); | |
575 | } | |
576 | ||
1e6c9c28 AV |
577 | /* |
578 | * Control the transmission of a break signal | |
579 | */ | |
7192f92c | 580 | static void atmel_break_ctl(struct uart_port *port, int break_state) |
1e6c9c28 AV |
581 | { |
582 | if (break_state != 0) | |
7192f92c | 583 | UART_PUT_CR(port, ATMEL_US_STTBRK); /* start break */ |
1e6c9c28 | 584 | else |
7192f92c | 585 | UART_PUT_CR(port, ATMEL_US_STPBRK); /* stop break */ |
1e6c9c28 AV |
586 | } |
587 | ||
1ecc26bd RB |
588 | /* |
589 | * Stores the incoming character in the ring buffer | |
590 | */ | |
591 | static void | |
592 | atmel_buffer_rx_char(struct uart_port *port, unsigned int status, | |
593 | unsigned int ch) | |
594 | { | |
c811ab8c | 595 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
1ecc26bd RB |
596 | struct circ_buf *ring = &atmel_port->rx_ring; |
597 | struct atmel_uart_char *c; | |
598 | ||
599 | if (!CIRC_SPACE(ring->head, ring->tail, ATMEL_SERIAL_RINGSIZE)) | |
600 | /* Buffer overflow, ignore char */ | |
601 | return; | |
602 | ||
603 | c = &((struct atmel_uart_char *)ring->buf)[ring->head]; | |
604 | c->status = status; | |
605 | c->ch = ch; | |
606 | ||
607 | /* Make sure the character is stored before we update head. */ | |
608 | smp_wmb(); | |
609 | ||
610 | ring->head = (ring->head + 1) & (ATMEL_SERIAL_RINGSIZE - 1); | |
611 | } | |
612 | ||
a6670615 CC |
613 | /* |
614 | * Deal with parity, framing and overrun errors. | |
615 | */ | |
616 | static void atmel_pdc_rxerr(struct uart_port *port, unsigned int status) | |
617 | { | |
618 | /* clear error */ | |
619 | UART_PUT_CR(port, ATMEL_US_RSTSTA); | |
620 | ||
621 | if (status & ATMEL_US_RXBRK) { | |
622 | /* ignore side-effect */ | |
623 | status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME); | |
624 | port->icount.brk++; | |
625 | } | |
626 | if (status & ATMEL_US_PARE) | |
627 | port->icount.parity++; | |
628 | if (status & ATMEL_US_FRAME) | |
629 | port->icount.frame++; | |
630 | if (status & ATMEL_US_OVRE) | |
631 | port->icount.overrun++; | |
632 | } | |
633 | ||
1e6c9c28 AV |
634 | /* |
635 | * Characters received (called from interrupt handler) | |
636 | */ | |
7d12e780 | 637 | static void atmel_rx_chars(struct uart_port *port) |
1e6c9c28 | 638 | { |
c811ab8c | 639 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
1ecc26bd | 640 | unsigned int status, ch; |
1e6c9c28 | 641 | |
afefc415 | 642 | status = UART_GET_CSR(port); |
7192f92c | 643 | while (status & ATMEL_US_RXRDY) { |
1e6c9c28 AV |
644 | ch = UART_GET_CHAR(port); |
645 | ||
1e6c9c28 AV |
646 | /* |
647 | * note that the error handling code is | |
648 | * out of the main execution path | |
649 | */ | |
9e6077bd HS |
650 | if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME |
651 | | ATMEL_US_OVRE | ATMEL_US_RXBRK) | |
652 | || atmel_port->break_active)) { | |
1ecc26bd | 653 | |
b843aa21 RB |
654 | /* clear error */ |
655 | UART_PUT_CR(port, ATMEL_US_RSTSTA); | |
1ecc26bd | 656 | |
9e6077bd HS |
657 | if (status & ATMEL_US_RXBRK |
658 | && !atmel_port->break_active) { | |
9e6077bd HS |
659 | atmel_port->break_active = 1; |
660 | UART_PUT_IER(port, ATMEL_US_RXBRK); | |
9e6077bd HS |
661 | } else { |
662 | /* | |
663 | * This is either the end-of-break | |
664 | * condition or we've received at | |
665 | * least one character without RXBRK | |
666 | * being set. In both cases, the next | |
667 | * RXBRK will indicate start-of-break. | |
668 | */ | |
669 | UART_PUT_IDR(port, ATMEL_US_RXBRK); | |
670 | status &= ~ATMEL_US_RXBRK; | |
671 | atmel_port->break_active = 0; | |
afefc415 | 672 | } |
1e6c9c28 AV |
673 | } |
674 | ||
1ecc26bd | 675 | atmel_buffer_rx_char(port, status, ch); |
afefc415 | 676 | status = UART_GET_CSR(port); |
1e6c9c28 AV |
677 | } |
678 | ||
1ecc26bd | 679 | tasklet_schedule(&atmel_port->tasklet); |
1e6c9c28 AV |
680 | } |
681 | ||
682 | /* | |
1ecc26bd RB |
683 | * Transmit characters (called from tasklet with TXRDY interrupt |
684 | * disabled) | |
1e6c9c28 | 685 | */ |
7192f92c | 686 | static void atmel_tx_chars(struct uart_port *port) |
1e6c9c28 | 687 | { |
ebd2c8f6 | 688 | struct circ_buf *xmit = &port->state->xmit; |
e8faff73 | 689 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
1e6c9c28 | 690 | |
e8faff73 | 691 | if (port->x_char && UART_GET_CSR(port) & atmel_port->tx_done_mask) { |
1e6c9c28 AV |
692 | UART_PUT_CHAR(port, port->x_char); |
693 | port->icount.tx++; | |
694 | port->x_char = 0; | |
1e6c9c28 | 695 | } |
1ecc26bd | 696 | if (uart_circ_empty(xmit) || uart_tx_stopped(port)) |
1e6c9c28 | 697 | return; |
1e6c9c28 | 698 | |
e8faff73 | 699 | while (UART_GET_CSR(port) & atmel_port->tx_done_mask) { |
1e6c9c28 AV |
700 | UART_PUT_CHAR(port, xmit->buf[xmit->tail]); |
701 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); | |
702 | port->icount.tx++; | |
703 | if (uart_circ_empty(xmit)) | |
704 | break; | |
705 | } | |
706 | ||
707 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
708 | uart_write_wakeup(port); | |
709 | ||
1ecc26bd | 710 | if (!uart_circ_empty(xmit)) |
e8faff73 CS |
711 | /* Enable interrupts */ |
712 | UART_PUT_IER(port, atmel_port->tx_done_mask); | |
1e6c9c28 AV |
713 | } |
714 | ||
08f738be ES |
715 | static void atmel_complete_tx_dma(void *arg) |
716 | { | |
717 | struct atmel_uart_port *atmel_port = arg; | |
718 | struct uart_port *port = &atmel_port->uart; | |
719 | struct circ_buf *xmit = &port->state->xmit; | |
720 | struct dma_chan *chan = atmel_port->chan_tx; | |
721 | unsigned long flags; | |
722 | ||
723 | spin_lock_irqsave(&port->lock, flags); | |
724 | ||
725 | if (chan) | |
726 | dmaengine_terminate_all(chan); | |
727 | xmit->tail += sg_dma_len(&atmel_port->sg_tx); | |
728 | xmit->tail &= UART_XMIT_SIZE - 1; | |
729 | ||
730 | port->icount.tx += sg_dma_len(&atmel_port->sg_tx); | |
731 | ||
732 | spin_lock_irq(&atmel_port->lock_tx); | |
733 | async_tx_ack(atmel_port->desc_tx); | |
734 | atmel_port->cookie_tx = -EINVAL; | |
735 | atmel_port->desc_tx = NULL; | |
736 | spin_unlock_irq(&atmel_port->lock_tx); | |
737 | ||
738 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
739 | uart_write_wakeup(port); | |
740 | ||
1842dc2e CP |
741 | /* |
742 | * xmit is a circular buffer so, if we have just send data from | |
743 | * xmit->tail to the end of xmit->buf, now we have to transmit the | |
744 | * remaining data from the beginning of xmit->buf to xmit->head. | |
745 | */ | |
08f738be ES |
746 | if (!uart_circ_empty(xmit)) |
747 | tasklet_schedule(&atmel_port->tasklet); | |
748 | ||
749 | spin_unlock_irqrestore(&port->lock, flags); | |
750 | } | |
751 | ||
752 | static void atmel_release_tx_dma(struct uart_port *port) | |
753 | { | |
754 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); | |
755 | struct dma_chan *chan = atmel_port->chan_tx; | |
756 | ||
757 | if (chan) { | |
758 | dmaengine_terminate_all(chan); | |
759 | dma_release_channel(chan); | |
760 | dma_unmap_sg(port->dev, &atmel_port->sg_tx, 1, | |
48479148 | 761 | DMA_TO_DEVICE); |
08f738be ES |
762 | } |
763 | ||
764 | atmel_port->desc_tx = NULL; | |
765 | atmel_port->chan_tx = NULL; | |
766 | atmel_port->cookie_tx = -EINVAL; | |
767 | } | |
768 | ||
769 | /* | |
770 | * Called from tasklet with TXRDY interrupt is disabled. | |
771 | */ | |
772 | static void atmel_tx_dma(struct uart_port *port) | |
773 | { | |
774 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); | |
775 | struct circ_buf *xmit = &port->state->xmit; | |
776 | struct dma_chan *chan = atmel_port->chan_tx; | |
777 | struct dma_async_tx_descriptor *desc; | |
778 | struct scatterlist *sg = &atmel_port->sg_tx; | |
779 | ||
780 | /* Make sure we have an idle channel */ | |
781 | if (atmel_port->desc_tx != NULL) | |
782 | return; | |
783 | ||
784 | if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) { | |
785 | /* | |
786 | * DMA is idle now. | |
787 | * Port xmit buffer is already mapped, | |
788 | * and it is one page... Just adjust | |
789 | * offsets and lengths. Since it is a circular buffer, | |
790 | * we have to transmit till the end, and then the rest. | |
791 | * Take the port lock to get a | |
792 | * consistent xmit buffer state. | |
793 | */ | |
794 | sg->offset = xmit->tail & (UART_XMIT_SIZE - 1); | |
795 | sg_dma_address(sg) = (sg_dma_address(sg) & | |
796 | ~(UART_XMIT_SIZE - 1)) | |
797 | + sg->offset; | |
798 | sg_dma_len(sg) = CIRC_CNT_TO_END(xmit->head, | |
799 | xmit->tail, | |
800 | UART_XMIT_SIZE); | |
801 | BUG_ON(!sg_dma_len(sg)); | |
802 | ||
803 | desc = dmaengine_prep_slave_sg(chan, | |
1842dc2e CP |
804 | sg, |
805 | 1, | |
806 | DMA_MEM_TO_DEV, | |
807 | DMA_PREP_INTERRUPT | | |
808 | DMA_CTRL_ACK); | |
08f738be ES |
809 | if (!desc) { |
810 | dev_err(port->dev, "Failed to send via dma!\n"); | |
811 | return; | |
812 | } | |
813 | ||
485819b5 | 814 | dma_sync_sg_for_device(port->dev, sg, 1, DMA_TO_DEVICE); |
08f738be ES |
815 | |
816 | atmel_port->desc_tx = desc; | |
817 | desc->callback = atmel_complete_tx_dma; | |
818 | desc->callback_param = atmel_port; | |
819 | atmel_port->cookie_tx = dmaengine_submit(desc); | |
820 | ||
821 | } else { | |
13bd3e6f | 822 | if (port->rs485.flags & SER_RS485_ENABLED) { |
08f738be ES |
823 | /* DMA done, stop TX, start RX for RS485 */ |
824 | atmel_start_rx(port); | |
825 | } | |
826 | } | |
827 | ||
828 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
829 | uart_write_wakeup(port); | |
830 | } | |
831 | ||
832 | static int atmel_prepare_tx_dma(struct uart_port *port) | |
833 | { | |
834 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); | |
835 | dma_cap_mask_t mask; | |
836 | struct dma_slave_config config; | |
837 | int ret, nent; | |
838 | ||
839 | dma_cap_zero(mask); | |
840 | dma_cap_set(DMA_SLAVE, mask); | |
841 | ||
842 | atmel_port->chan_tx = dma_request_slave_channel(port->dev, "tx"); | |
843 | if (atmel_port->chan_tx == NULL) | |
844 | goto chan_err; | |
845 | dev_info(port->dev, "using %s for tx DMA transfers\n", | |
846 | dma_chan_name(atmel_port->chan_tx)); | |
847 | ||
848 | spin_lock_init(&atmel_port->lock_tx); | |
849 | sg_init_table(&atmel_port->sg_tx, 1); | |
850 | /* UART circular tx buffer is an aligned page. */ | |
851 | BUG_ON((int)port->state->xmit.buf & ~PAGE_MASK); | |
852 | sg_set_page(&atmel_port->sg_tx, | |
853 | virt_to_page(port->state->xmit.buf), | |
854 | UART_XMIT_SIZE, | |
855 | (int)port->state->xmit.buf & ~PAGE_MASK); | |
856 | nent = dma_map_sg(port->dev, | |
857 | &atmel_port->sg_tx, | |
858 | 1, | |
48479148 | 859 | DMA_TO_DEVICE); |
08f738be ES |
860 | |
861 | if (!nent) { | |
862 | dev_dbg(port->dev, "need to release resource of dma\n"); | |
863 | goto chan_err; | |
864 | } else { | |
865 | dev_dbg(port->dev, "%s: mapped %d@%p to %x\n", __func__, | |
866 | sg_dma_len(&atmel_port->sg_tx), | |
867 | port->state->xmit.buf, | |
868 | sg_dma_address(&atmel_port->sg_tx)); | |
869 | } | |
870 | ||
871 | /* Configure the slave DMA */ | |
872 | memset(&config, 0, sizeof(config)); | |
873 | config.direction = DMA_MEM_TO_DEV; | |
874 | config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; | |
875 | config.dst_addr = port->mapbase + ATMEL_US_THR; | |
876 | ||
5483c10e MR |
877 | ret = dmaengine_slave_config(atmel_port->chan_tx, |
878 | &config); | |
08f738be ES |
879 | if (ret) { |
880 | dev_err(port->dev, "DMA tx slave configuration failed\n"); | |
881 | goto chan_err; | |
882 | } | |
883 | ||
884 | return 0; | |
885 | ||
886 | chan_err: | |
887 | dev_err(port->dev, "TX channel not available, switch to pio\n"); | |
888 | atmel_port->use_dma_tx = 0; | |
889 | if (atmel_port->chan_tx) | |
890 | atmel_release_tx_dma(port); | |
891 | return -EINVAL; | |
892 | } | |
893 | ||
34df42f5 ES |
894 | static void atmel_complete_rx_dma(void *arg) |
895 | { | |
896 | struct uart_port *port = arg; | |
897 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); | |
898 | ||
899 | tasklet_schedule(&atmel_port->tasklet); | |
900 | } | |
901 | ||
902 | static void atmel_release_rx_dma(struct uart_port *port) | |
903 | { | |
904 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); | |
905 | struct dma_chan *chan = atmel_port->chan_rx; | |
906 | ||
907 | if (chan) { | |
908 | dmaengine_terminate_all(chan); | |
909 | dma_release_channel(chan); | |
910 | dma_unmap_sg(port->dev, &atmel_port->sg_rx, 1, | |
48479148 | 911 | DMA_FROM_DEVICE); |
34df42f5 ES |
912 | } |
913 | ||
914 | atmel_port->desc_rx = NULL; | |
915 | atmel_port->chan_rx = NULL; | |
916 | atmel_port->cookie_rx = -EINVAL; | |
917 | } | |
918 | ||
919 | static void atmel_rx_from_dma(struct uart_port *port) | |
920 | { | |
921 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); | |
66f37aaf | 922 | struct tty_port *tport = &port->state->port; |
34df42f5 ES |
923 | struct circ_buf *ring = &atmel_port->rx_ring; |
924 | struct dma_chan *chan = atmel_port->chan_rx; | |
925 | struct dma_tx_state state; | |
926 | enum dma_status dmastat; | |
66f37aaf | 927 | size_t count; |
34df42f5 ES |
928 | |
929 | ||
930 | /* Reset the UART timeout early so that we don't miss one */ | |
931 | UART_PUT_CR(port, ATMEL_US_STTTO); | |
932 | dmastat = dmaengine_tx_status(chan, | |
933 | atmel_port->cookie_rx, | |
934 | &state); | |
935 | /* Restart a new tasklet if DMA status is error */ | |
936 | if (dmastat == DMA_ERROR) { | |
937 | dev_dbg(port->dev, "Get residue error, restart tasklet\n"); | |
938 | UART_PUT_IER(port, ATMEL_US_TIMEOUT); | |
939 | tasklet_schedule(&atmel_port->tasklet); | |
940 | return; | |
941 | } | |
34df42f5 | 942 | |
66f37aaf CP |
943 | /* CPU claims ownership of RX DMA buffer */ |
944 | dma_sync_sg_for_cpu(port->dev, | |
945 | &atmel_port->sg_rx, | |
946 | 1, | |
485819b5 | 947 | DMA_FROM_DEVICE); |
66f37aaf CP |
948 | |
949 | /* | |
950 | * ring->head points to the end of data already written by the DMA. | |
951 | * ring->tail points to the beginning of data to be read by the | |
952 | * framework. | |
953 | * The current transfer size should not be larger than the dma buffer | |
954 | * length. | |
955 | */ | |
956 | ring->head = sg_dma_len(&atmel_port->sg_rx) - state.residue; | |
957 | BUG_ON(ring->head > sg_dma_len(&atmel_port->sg_rx)); | |
34df42f5 | 958 | /* |
66f37aaf CP |
959 | * At this point ring->head may point to the first byte right after the |
960 | * last byte of the dma buffer: | |
961 | * 0 <= ring->head <= sg_dma_len(&atmel_port->sg_rx) | |
962 | * | |
963 | * However ring->tail must always points inside the dma buffer: | |
964 | * 0 <= ring->tail <= sg_dma_len(&atmel_port->sg_rx) - 1 | |
965 | * | |
966 | * Since we use a ring buffer, we have to handle the case | |
967 | * where head is lower than tail. In such a case, we first read from | |
968 | * tail to the end of the buffer then reset tail. | |
34df42f5 | 969 | */ |
66f37aaf CP |
970 | if (ring->head < ring->tail) { |
971 | count = sg_dma_len(&atmel_port->sg_rx) - ring->tail; | |
34df42f5 | 972 | |
66f37aaf CP |
973 | tty_insert_flip_string(tport, ring->buf + ring->tail, count); |
974 | ring->tail = 0; | |
975 | port->icount.rx += count; | |
976 | } | |
34df42f5 | 977 | |
66f37aaf CP |
978 | /* Finally we read data from tail to head */ |
979 | if (ring->tail < ring->head) { | |
980 | count = ring->head - ring->tail; | |
34df42f5 | 981 | |
66f37aaf CP |
982 | tty_insert_flip_string(tport, ring->buf + ring->tail, count); |
983 | /* Wrap ring->head if needed */ | |
984 | if (ring->head >= sg_dma_len(&atmel_port->sg_rx)) | |
985 | ring->head = 0; | |
986 | ring->tail = ring->head; | |
34df42f5 ES |
987 | port->icount.rx += count; |
988 | } | |
989 | ||
66f37aaf CP |
990 | /* USART retreives ownership of RX DMA buffer */ |
991 | dma_sync_sg_for_device(port->dev, | |
992 | &atmel_port->sg_rx, | |
993 | 1, | |
485819b5 | 994 | DMA_FROM_DEVICE); |
66f37aaf CP |
995 | |
996 | /* | |
997 | * Drop the lock here since it might end up calling | |
998 | * uart_start(), which takes the lock. | |
999 | */ | |
1000 | spin_unlock(&port->lock); | |
1001 | tty_flip_buffer_push(tport); | |
1002 | spin_lock(&port->lock); | |
1003 | ||
34df42f5 ES |
1004 | UART_PUT_IER(port, ATMEL_US_TIMEOUT); |
1005 | } | |
1006 | ||
1007 | static int atmel_prepare_rx_dma(struct uart_port *port) | |
1008 | { | |
1009 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); | |
1010 | struct dma_async_tx_descriptor *desc; | |
1011 | dma_cap_mask_t mask; | |
1012 | struct dma_slave_config config; | |
1013 | struct circ_buf *ring; | |
1014 | int ret, nent; | |
1015 | ||
1016 | ring = &atmel_port->rx_ring; | |
1017 | ||
1018 | dma_cap_zero(mask); | |
1019 | dma_cap_set(DMA_CYCLIC, mask); | |
1020 | ||
1021 | atmel_port->chan_rx = dma_request_slave_channel(port->dev, "rx"); | |
1022 | if (atmel_port->chan_rx == NULL) | |
1023 | goto chan_err; | |
1024 | dev_info(port->dev, "using %s for rx DMA transfers\n", | |
1025 | dma_chan_name(atmel_port->chan_rx)); | |
1026 | ||
1027 | spin_lock_init(&atmel_port->lock_rx); | |
1028 | sg_init_table(&atmel_port->sg_rx, 1); | |
1029 | /* UART circular rx buffer is an aligned page. */ | |
1030 | BUG_ON((int)port->state->xmit.buf & ~PAGE_MASK); | |
1031 | sg_set_page(&atmel_port->sg_rx, | |
1842dc2e CP |
1032 | virt_to_page(ring->buf), |
1033 | ATMEL_SERIAL_RINGSIZE, | |
1034 | (int)ring->buf & ~PAGE_MASK); | |
1035 | nent = dma_map_sg(port->dev, | |
1036 | &atmel_port->sg_rx, | |
1037 | 1, | |
1038 | DMA_FROM_DEVICE); | |
34df42f5 ES |
1039 | |
1040 | if (!nent) { | |
1041 | dev_dbg(port->dev, "need to release resource of dma\n"); | |
1042 | goto chan_err; | |
1043 | } else { | |
1044 | dev_dbg(port->dev, "%s: mapped %d@%p to %x\n", __func__, | |
1045 | sg_dma_len(&atmel_port->sg_rx), | |
1046 | ring->buf, | |
1047 | sg_dma_address(&atmel_port->sg_rx)); | |
1048 | } | |
1049 | ||
1050 | /* Configure the slave DMA */ | |
1051 | memset(&config, 0, sizeof(config)); | |
1052 | config.direction = DMA_DEV_TO_MEM; | |
1053 | config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; | |
1054 | config.src_addr = port->mapbase + ATMEL_US_RHR; | |
1055 | ||
5483c10e MR |
1056 | ret = dmaengine_slave_config(atmel_port->chan_rx, |
1057 | &config); | |
34df42f5 ES |
1058 | if (ret) { |
1059 | dev_err(port->dev, "DMA rx slave configuration failed\n"); | |
1060 | goto chan_err; | |
1061 | } | |
1062 | /* | |
1063 | * Prepare a cyclic dma transfer, assign 2 descriptors, | |
1064 | * each one is half ring buffer size | |
1065 | */ | |
1066 | desc = dmaengine_prep_dma_cyclic(atmel_port->chan_rx, | |
1842dc2e CP |
1067 | sg_dma_address(&atmel_port->sg_rx), |
1068 | sg_dma_len(&atmel_port->sg_rx), | |
1069 | sg_dma_len(&atmel_port->sg_rx)/2, | |
1070 | DMA_DEV_TO_MEM, | |
1071 | DMA_PREP_INTERRUPT); | |
34df42f5 ES |
1072 | desc->callback = atmel_complete_rx_dma; |
1073 | desc->callback_param = port; | |
1074 | atmel_port->desc_rx = desc; | |
1075 | atmel_port->cookie_rx = dmaengine_submit(desc); | |
1076 | ||
1077 | return 0; | |
1078 | ||
1079 | chan_err: | |
1080 | dev_err(port->dev, "RX channel not available, switch to pio\n"); | |
1081 | atmel_port->use_dma_rx = 0; | |
1082 | if (atmel_port->chan_rx) | |
1083 | atmel_release_rx_dma(port); | |
1084 | return -EINVAL; | |
1085 | } | |
1086 | ||
2e68c22f ES |
1087 | static void atmel_uart_timer_callback(unsigned long data) |
1088 | { | |
1089 | struct uart_port *port = (void *)data; | |
1090 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); | |
1091 | ||
1092 | tasklet_schedule(&atmel_port->tasklet); | |
1093 | mod_timer(&atmel_port->uart_timer, jiffies + uart_poll_timeout(port)); | |
1094 | } | |
1095 | ||
b843aa21 RB |
1096 | /* |
1097 | * receive interrupt handler. | |
1098 | */ | |
1099 | static void | |
1100 | atmel_handle_receive(struct uart_port *port, unsigned int pending) | |
1101 | { | |
c811ab8c | 1102 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
b843aa21 | 1103 | |
64e22ebe | 1104 | if (atmel_use_pdc_rx(port)) { |
a6670615 CC |
1105 | /* |
1106 | * PDC receive. Just schedule the tasklet and let it | |
1107 | * figure out the details. | |
1108 | * | |
1109 | * TODO: We're not handling error flags correctly at | |
1110 | * the moment. | |
1111 | */ | |
1112 | if (pending & (ATMEL_US_ENDRX | ATMEL_US_TIMEOUT)) { | |
1113 | UART_PUT_IDR(port, (ATMEL_US_ENDRX | |
1114 | | ATMEL_US_TIMEOUT)); | |
1115 | tasklet_schedule(&atmel_port->tasklet); | |
1116 | } | |
1117 | ||
1118 | if (pending & (ATMEL_US_RXBRK | ATMEL_US_OVRE | | |
1119 | ATMEL_US_FRAME | ATMEL_US_PARE)) | |
1120 | atmel_pdc_rxerr(port, pending); | |
1121 | } | |
1122 | ||
34df42f5 ES |
1123 | if (atmel_use_dma_rx(port)) { |
1124 | if (pending & ATMEL_US_TIMEOUT) { | |
1125 | UART_PUT_IDR(port, ATMEL_US_TIMEOUT); | |
1126 | tasklet_schedule(&atmel_port->tasklet); | |
1127 | } | |
1128 | } | |
1129 | ||
b843aa21 RB |
1130 | /* Interrupt receive */ |
1131 | if (pending & ATMEL_US_RXRDY) | |
1132 | atmel_rx_chars(port); | |
1133 | else if (pending & ATMEL_US_RXBRK) { | |
1134 | /* | |
1135 | * End of break detected. If it came along with a | |
1136 | * character, atmel_rx_chars will handle it. | |
1137 | */ | |
1138 | UART_PUT_CR(port, ATMEL_US_RSTSTA); | |
1139 | UART_PUT_IDR(port, ATMEL_US_RXBRK); | |
1140 | atmel_port->break_active = 0; | |
1141 | } | |
1142 | } | |
1143 | ||
1144 | /* | |
1ecc26bd | 1145 | * transmit interrupt handler. (Transmit is IRQF_NODELAY safe) |
b843aa21 RB |
1146 | */ |
1147 | static void | |
1148 | atmel_handle_transmit(struct uart_port *port, unsigned int pending) | |
1149 | { | |
c811ab8c | 1150 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
1ecc26bd | 1151 | |
e8faff73 CS |
1152 | if (pending & atmel_port->tx_done_mask) { |
1153 | /* Either PDC or interrupt transmission */ | |
1154 | UART_PUT_IDR(port, atmel_port->tx_done_mask); | |
1155 | tasklet_schedule(&atmel_port->tasklet); | |
1ecc26bd | 1156 | } |
b843aa21 RB |
1157 | } |
1158 | ||
1159 | /* | |
1160 | * status flags interrupt handler. | |
1161 | */ | |
1162 | static void | |
1163 | atmel_handle_status(struct uart_port *port, unsigned int pending, | |
1164 | unsigned int status) | |
1165 | { | |
c811ab8c | 1166 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
1ecc26bd | 1167 | |
b843aa21 | 1168 | if (pending & (ATMEL_US_RIIC | ATMEL_US_DSRIC | ATMEL_US_DCDIC |
1ecc26bd RB |
1169 | | ATMEL_US_CTSIC)) { |
1170 | atmel_port->irq_status = status; | |
1171 | tasklet_schedule(&atmel_port->tasklet); | |
1172 | } | |
b843aa21 RB |
1173 | } |
1174 | ||
1e6c9c28 AV |
1175 | /* |
1176 | * Interrupt handler | |
1177 | */ | |
7d12e780 | 1178 | static irqreturn_t atmel_interrupt(int irq, void *dev_id) |
1e6c9c28 AV |
1179 | { |
1180 | struct uart_port *port = dev_id; | |
ab5e4e41 | 1181 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
1e6c9c28 | 1182 | unsigned int status, pending, pass_counter = 0; |
ab5e4e41 | 1183 | bool gpio_handled = false; |
1e6c9c28 | 1184 | |
a6670615 | 1185 | do { |
e0b0baad | 1186 | status = atmel_get_lines_status(port); |
a6670615 | 1187 | pending = status & UART_GET_IMR(port); |
ab5e4e41 RG |
1188 | if (!gpio_handled) { |
1189 | /* | |
1190 | * Dealing with GPIO interrupt | |
1191 | */ | |
1192 | if (irq == atmel_port->gpio_irq[UART_GPIO_CTS]) | |
1193 | pending |= ATMEL_US_CTSIC; | |
1194 | ||
1195 | if (irq == atmel_port->gpio_irq[UART_GPIO_DSR]) | |
1196 | pending |= ATMEL_US_DSRIC; | |
1197 | ||
1198 | if (irq == atmel_port->gpio_irq[UART_GPIO_RI]) | |
1199 | pending |= ATMEL_US_RIIC; | |
1200 | ||
1201 | if (irq == atmel_port->gpio_irq[UART_GPIO_DCD]) | |
1202 | pending |= ATMEL_US_DCDIC; | |
1203 | ||
1204 | gpio_handled = true; | |
1205 | } | |
a6670615 CC |
1206 | if (!pending) |
1207 | break; | |
1208 | ||
b843aa21 RB |
1209 | atmel_handle_receive(port, pending); |
1210 | atmel_handle_status(port, pending, status); | |
1211 | atmel_handle_transmit(port, pending); | |
a6670615 | 1212 | } while (pass_counter++ < ATMEL_ISR_PASS_LIMIT); |
afefc415 | 1213 | |
0400b697 | 1214 | return pass_counter ? IRQ_HANDLED : IRQ_NONE; |
a6670615 | 1215 | } |
1e6c9c28 | 1216 | |
a930e528 ES |
1217 | static void atmel_release_tx_pdc(struct uart_port *port) |
1218 | { | |
1219 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); | |
1220 | struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx; | |
1221 | ||
1222 | dma_unmap_single(port->dev, | |
1223 | pdc->dma_addr, | |
1224 | pdc->dma_size, | |
1225 | DMA_TO_DEVICE); | |
1226 | } | |
1227 | ||
a6670615 CC |
1228 | /* |
1229 | * Called from tasklet with ENDTX and TXBUFE interrupts disabled. | |
1230 | */ | |
64e22ebe | 1231 | static void atmel_tx_pdc(struct uart_port *port) |
a6670615 | 1232 | { |
c811ab8c | 1233 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
ebd2c8f6 | 1234 | struct circ_buf *xmit = &port->state->xmit; |
a6670615 CC |
1235 | struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx; |
1236 | int count; | |
1237 | ||
ba0657ff MT |
1238 | /* nothing left to transmit? */ |
1239 | if (UART_GET_TCR(port)) | |
1240 | return; | |
1241 | ||
a6670615 CC |
1242 | xmit->tail += pdc->ofs; |
1243 | xmit->tail &= UART_XMIT_SIZE - 1; | |
1244 | ||
1245 | port->icount.tx += pdc->ofs; | |
1246 | pdc->ofs = 0; | |
1247 | ||
ba0657ff | 1248 | /* more to transmit - setup next transfer */ |
a6670615 | 1249 | |
ba0657ff MT |
1250 | /* disable PDC transmit */ |
1251 | UART_PUT_PTCR(port, ATMEL_PDC_TXTDIS); | |
1252 | ||
1f14081d | 1253 | if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) { |
a6670615 CC |
1254 | dma_sync_single_for_device(port->dev, |
1255 | pdc->dma_addr, | |
1256 | pdc->dma_size, | |
1257 | DMA_TO_DEVICE); | |
1258 | ||
1259 | count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE); | |
1260 | pdc->ofs = count; | |
1261 | ||
1262 | UART_PUT_TPR(port, pdc->dma_addr + xmit->tail); | |
1263 | UART_PUT_TCR(port, count); | |
e8faff73 | 1264 | /* re-enable PDC transmit */ |
a6670615 | 1265 | UART_PUT_PTCR(port, ATMEL_PDC_TXTEN); |
e8faff73 CS |
1266 | /* Enable interrupts */ |
1267 | UART_PUT_IER(port, atmel_port->tx_done_mask); | |
1268 | } else { | |
13bd3e6f RRD |
1269 | if ((port->rs485.flags & SER_RS485_ENABLED) && |
1270 | !(port->rs485.flags & SER_RS485_RX_DURING_TX)) { | |
e8faff73 CS |
1271 | /* DMA done, stop TX, start RX for RS485 */ |
1272 | atmel_start_rx(port); | |
1273 | } | |
1e6c9c28 | 1274 | } |
a6670615 CC |
1275 | |
1276 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
1277 | uart_write_wakeup(port); | |
1e6c9c28 AV |
1278 | } |
1279 | ||
a930e528 ES |
1280 | static int atmel_prepare_tx_pdc(struct uart_port *port) |
1281 | { | |
1282 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); | |
1283 | struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx; | |
1284 | struct circ_buf *xmit = &port->state->xmit; | |
1285 | ||
1286 | pdc->buf = xmit->buf; | |
1287 | pdc->dma_addr = dma_map_single(port->dev, | |
1288 | pdc->buf, | |
1289 | UART_XMIT_SIZE, | |
1290 | DMA_TO_DEVICE); | |
1291 | pdc->dma_size = UART_XMIT_SIZE; | |
1292 | pdc->ofs = 0; | |
1293 | ||
1294 | return 0; | |
1295 | } | |
1296 | ||
1ecc26bd RB |
1297 | static void atmel_rx_from_ring(struct uart_port *port) |
1298 | { | |
c811ab8c | 1299 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
1ecc26bd RB |
1300 | struct circ_buf *ring = &atmel_port->rx_ring; |
1301 | unsigned int flg; | |
1302 | unsigned int status; | |
1303 | ||
1304 | while (ring->head != ring->tail) { | |
1305 | struct atmel_uart_char c; | |
1306 | ||
1307 | /* Make sure c is loaded after head. */ | |
1308 | smp_rmb(); | |
1309 | ||
1310 | c = ((struct atmel_uart_char *)ring->buf)[ring->tail]; | |
1311 | ||
1312 | ring->tail = (ring->tail + 1) & (ATMEL_SERIAL_RINGSIZE - 1); | |
1313 | ||
1314 | port->icount.rx++; | |
1315 | status = c.status; | |
1316 | flg = TTY_NORMAL; | |
1317 | ||
1318 | /* | |
1319 | * note that the error handling code is | |
1320 | * out of the main execution path | |
1321 | */ | |
1322 | if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME | |
1323 | | ATMEL_US_OVRE | ATMEL_US_RXBRK))) { | |
1324 | if (status & ATMEL_US_RXBRK) { | |
1325 | /* ignore side-effect */ | |
1326 | status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME); | |
1327 | ||
1328 | port->icount.brk++; | |
1329 | if (uart_handle_break(port)) | |
1330 | continue; | |
1331 | } | |
1332 | if (status & ATMEL_US_PARE) | |
1333 | port->icount.parity++; | |
1334 | if (status & ATMEL_US_FRAME) | |
1335 | port->icount.frame++; | |
1336 | if (status & ATMEL_US_OVRE) | |
1337 | port->icount.overrun++; | |
1338 | ||
1339 | status &= port->read_status_mask; | |
1340 | ||
1341 | if (status & ATMEL_US_RXBRK) | |
1342 | flg = TTY_BREAK; | |
1343 | else if (status & ATMEL_US_PARE) | |
1344 | flg = TTY_PARITY; | |
1345 | else if (status & ATMEL_US_FRAME) | |
1346 | flg = TTY_FRAME; | |
1347 | } | |
1348 | ||
1349 | ||
1350 | if (uart_handle_sysrq_char(port, c.ch)) | |
1351 | continue; | |
1352 | ||
1353 | uart_insert_char(port, status, ATMEL_US_OVRE, c.ch, flg); | |
1354 | } | |
1355 | ||
1356 | /* | |
1357 | * Drop the lock here since it might end up calling | |
1358 | * uart_start(), which takes the lock. | |
1359 | */ | |
1360 | spin_unlock(&port->lock); | |
2e124b4a | 1361 | tty_flip_buffer_push(&port->state->port); |
1ecc26bd RB |
1362 | spin_lock(&port->lock); |
1363 | } | |
1364 | ||
a930e528 ES |
1365 | static void atmel_release_rx_pdc(struct uart_port *port) |
1366 | { | |
1367 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); | |
1368 | int i; | |
1369 | ||
1370 | for (i = 0; i < 2; i++) { | |
1371 | struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i]; | |
1372 | ||
1373 | dma_unmap_single(port->dev, | |
1374 | pdc->dma_addr, | |
1375 | pdc->dma_size, | |
1376 | DMA_FROM_DEVICE); | |
1377 | kfree(pdc->buf); | |
1378 | } | |
1379 | } | |
1380 | ||
64e22ebe | 1381 | static void atmel_rx_from_pdc(struct uart_port *port) |
a6670615 | 1382 | { |
c811ab8c | 1383 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
05c7cd39 | 1384 | struct tty_port *tport = &port->state->port; |
a6670615 CC |
1385 | struct atmel_dma_buffer *pdc; |
1386 | int rx_idx = atmel_port->pdc_rx_idx; | |
1387 | unsigned int head; | |
1388 | unsigned int tail; | |
1389 | unsigned int count; | |
1390 | ||
1391 | do { | |
1392 | /* Reset the UART timeout early so that we don't miss one */ | |
1393 | UART_PUT_CR(port, ATMEL_US_STTTO); | |
1394 | ||
1395 | pdc = &atmel_port->pdc_rx[rx_idx]; | |
1396 | head = UART_GET_RPR(port) - pdc->dma_addr; | |
1397 | tail = pdc->ofs; | |
1398 | ||
1399 | /* If the PDC has switched buffers, RPR won't contain | |
1400 | * any address within the current buffer. Since head | |
1401 | * is unsigned, we just need a one-way comparison to | |
1402 | * find out. | |
1403 | * | |
1404 | * In this case, we just need to consume the entire | |
1405 | * buffer and resubmit it for DMA. This will clear the | |
1406 | * ENDRX bit as well, so that we can safely re-enable | |
1407 | * all interrupts below. | |
1408 | */ | |
1409 | head = min(head, pdc->dma_size); | |
1410 | ||
1411 | if (likely(head != tail)) { | |
1412 | dma_sync_single_for_cpu(port->dev, pdc->dma_addr, | |
1413 | pdc->dma_size, DMA_FROM_DEVICE); | |
1414 | ||
1415 | /* | |
1416 | * head will only wrap around when we recycle | |
1417 | * the DMA buffer, and when that happens, we | |
1418 | * explicitly set tail to 0. So head will | |
1419 | * always be greater than tail. | |
1420 | */ | |
1421 | count = head - tail; | |
1422 | ||
05c7cd39 JS |
1423 | tty_insert_flip_string(tport, pdc->buf + pdc->ofs, |
1424 | count); | |
a6670615 CC |
1425 | |
1426 | dma_sync_single_for_device(port->dev, pdc->dma_addr, | |
1427 | pdc->dma_size, DMA_FROM_DEVICE); | |
1428 | ||
1429 | port->icount.rx += count; | |
1430 | pdc->ofs = head; | |
1431 | } | |
1432 | ||
1433 | /* | |
1434 | * If the current buffer is full, we need to check if | |
1435 | * the next one contains any additional data. | |
1436 | */ | |
1437 | if (head >= pdc->dma_size) { | |
1438 | pdc->ofs = 0; | |
1439 | UART_PUT_RNPR(port, pdc->dma_addr); | |
1440 | UART_PUT_RNCR(port, pdc->dma_size); | |
1441 | ||
1442 | rx_idx = !rx_idx; | |
1443 | atmel_port->pdc_rx_idx = rx_idx; | |
1444 | } | |
1445 | } while (head >= pdc->dma_size); | |
1446 | ||
1447 | /* | |
1448 | * Drop the lock here since it might end up calling | |
1449 | * uart_start(), which takes the lock. | |
1450 | */ | |
1451 | spin_unlock(&port->lock); | |
2e124b4a | 1452 | tty_flip_buffer_push(tport); |
a6670615 CC |
1453 | spin_lock(&port->lock); |
1454 | ||
1455 | UART_PUT_IER(port, ATMEL_US_ENDRX | ATMEL_US_TIMEOUT); | |
1456 | } | |
1457 | ||
a930e528 ES |
1458 | static int atmel_prepare_rx_pdc(struct uart_port *port) |
1459 | { | |
1460 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); | |
1461 | int i; | |
1462 | ||
1463 | for (i = 0; i < 2; i++) { | |
1464 | struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i]; | |
1465 | ||
1466 | pdc->buf = kmalloc(PDC_BUFFER_SIZE, GFP_KERNEL); | |
1467 | if (pdc->buf == NULL) { | |
1468 | if (i != 0) { | |
1469 | dma_unmap_single(port->dev, | |
1470 | atmel_port->pdc_rx[0].dma_addr, | |
1471 | PDC_BUFFER_SIZE, | |
1472 | DMA_FROM_DEVICE); | |
1473 | kfree(atmel_port->pdc_rx[0].buf); | |
1474 | } | |
1475 | atmel_port->use_pdc_rx = 0; | |
1476 | return -ENOMEM; | |
1477 | } | |
1478 | pdc->dma_addr = dma_map_single(port->dev, | |
1479 | pdc->buf, | |
1480 | PDC_BUFFER_SIZE, | |
1481 | DMA_FROM_DEVICE); | |
1482 | pdc->dma_size = PDC_BUFFER_SIZE; | |
1483 | pdc->ofs = 0; | |
1484 | } | |
1485 | ||
1486 | atmel_port->pdc_rx_idx = 0; | |
1487 | ||
1488 | UART_PUT_RPR(port, atmel_port->pdc_rx[0].dma_addr); | |
1489 | UART_PUT_RCR(port, PDC_BUFFER_SIZE); | |
1490 | ||
1491 | UART_PUT_RNPR(port, atmel_port->pdc_rx[1].dma_addr); | |
1492 | UART_PUT_RNCR(port, PDC_BUFFER_SIZE); | |
1493 | ||
1494 | return 0; | |
1495 | } | |
1496 | ||
1ecc26bd RB |
1497 | /* |
1498 | * tasklet handling tty stuff outside the interrupt handler. | |
1499 | */ | |
1500 | static void atmel_tasklet_func(unsigned long data) | |
1501 | { | |
1502 | struct uart_port *port = (struct uart_port *)data; | |
c811ab8c | 1503 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
1ecc26bd RB |
1504 | unsigned int status; |
1505 | unsigned int status_change; | |
1506 | ||
1507 | /* The interrupt handler does not take the lock */ | |
1508 | spin_lock(&port->lock); | |
1509 | ||
a930e528 | 1510 | atmel_port->schedule_tx(port); |
1ecc26bd RB |
1511 | |
1512 | status = atmel_port->irq_status; | |
1513 | status_change = status ^ atmel_port->irq_status_prev; | |
1514 | ||
1515 | if (status_change & (ATMEL_US_RI | ATMEL_US_DSR | |
1516 | | ATMEL_US_DCD | ATMEL_US_CTS)) { | |
1517 | /* TODO: All reads to CSR will clear these interrupts! */ | |
1518 | if (status_change & ATMEL_US_RI) | |
1519 | port->icount.rng++; | |
1520 | if (status_change & ATMEL_US_DSR) | |
1521 | port->icount.dsr++; | |
1522 | if (status_change & ATMEL_US_DCD) | |
1523 | uart_handle_dcd_change(port, !(status & ATMEL_US_DCD)); | |
1524 | if (status_change & ATMEL_US_CTS) | |
1525 | uart_handle_cts_change(port, !(status & ATMEL_US_CTS)); | |
1526 | ||
bdc04e31 | 1527 | wake_up_interruptible(&port->state->port.delta_msr_wait); |
1ecc26bd RB |
1528 | |
1529 | atmel_port->irq_status_prev = status; | |
1530 | } | |
1531 | ||
a930e528 | 1532 | atmel_port->schedule_rx(port); |
1ecc26bd RB |
1533 | |
1534 | spin_unlock(&port->lock); | |
1535 | } | |
1536 | ||
33d64c4f ES |
1537 | static int atmel_init_property(struct atmel_uart_port *atmel_port, |
1538 | struct platform_device *pdev) | |
1539 | { | |
1540 | struct device_node *np = pdev->dev.of_node; | |
574de559 | 1541 | struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev); |
33d64c4f ES |
1542 | |
1543 | if (np) { | |
1544 | /* DMA/PDC usage specification */ | |
1545 | if (of_get_property(np, "atmel,use-dma-rx", NULL)) { | |
1546 | if (of_get_property(np, "dmas", NULL)) { | |
1547 | atmel_port->use_dma_rx = true; | |
1548 | atmel_port->use_pdc_rx = false; | |
1549 | } else { | |
1550 | atmel_port->use_dma_rx = false; | |
1551 | atmel_port->use_pdc_rx = true; | |
1552 | } | |
1553 | } else { | |
1554 | atmel_port->use_dma_rx = false; | |
1555 | atmel_port->use_pdc_rx = false; | |
1556 | } | |
1557 | ||
1558 | if (of_get_property(np, "atmel,use-dma-tx", NULL)) { | |
1559 | if (of_get_property(np, "dmas", NULL)) { | |
1560 | atmel_port->use_dma_tx = true; | |
1561 | atmel_port->use_pdc_tx = false; | |
1562 | } else { | |
1563 | atmel_port->use_dma_tx = false; | |
1564 | atmel_port->use_pdc_tx = true; | |
1565 | } | |
1566 | } else { | |
1567 | atmel_port->use_dma_tx = false; | |
1568 | atmel_port->use_pdc_tx = false; | |
1569 | } | |
1570 | ||
1571 | } else { | |
1572 | atmel_port->use_pdc_rx = pdata->use_dma_rx; | |
1573 | atmel_port->use_pdc_tx = pdata->use_dma_tx; | |
1574 | atmel_port->use_dma_rx = false; | |
1575 | atmel_port->use_dma_tx = false; | |
1576 | } | |
1577 | ||
1578 | return 0; | |
1579 | } | |
1580 | ||
13bd3e6f | 1581 | static void atmel_init_rs485(struct uart_port *port, |
33d64c4f ES |
1582 | struct platform_device *pdev) |
1583 | { | |
1584 | struct device_node *np = pdev->dev.of_node; | |
574de559 | 1585 | struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev); |
33d64c4f ES |
1586 | |
1587 | if (np) { | |
1588 | u32 rs485_delay[2]; | |
1589 | /* rs485 properties */ | |
1590 | if (of_property_read_u32_array(np, "rs485-rts-delay", | |
1591 | rs485_delay, 2) == 0) { | |
13bd3e6f | 1592 | struct serial_rs485 *rs485conf = &port->rs485; |
33d64c4f ES |
1593 | |
1594 | rs485conf->delay_rts_before_send = rs485_delay[0]; | |
1595 | rs485conf->delay_rts_after_send = rs485_delay[1]; | |
1596 | rs485conf->flags = 0; | |
1597 | ||
1598 | if (of_get_property(np, "rs485-rx-during-tx", NULL)) | |
1599 | rs485conf->flags |= SER_RS485_RX_DURING_TX; | |
1600 | ||
1601 | if (of_get_property(np, "linux,rs485-enabled-at-boot-time", | |
1602 | NULL)) | |
1603 | rs485conf->flags |= SER_RS485_ENABLED; | |
1604 | } | |
1605 | } else { | |
13bd3e6f | 1606 | port->rs485 = pdata->rs485; |
33d64c4f ES |
1607 | } |
1608 | ||
1609 | } | |
1610 | ||
a930e528 ES |
1611 | static void atmel_set_ops(struct uart_port *port) |
1612 | { | |
1613 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); | |
1614 | ||
34df42f5 ES |
1615 | if (atmel_use_dma_rx(port)) { |
1616 | atmel_port->prepare_rx = &atmel_prepare_rx_dma; | |
1617 | atmel_port->schedule_rx = &atmel_rx_from_dma; | |
1618 | atmel_port->release_rx = &atmel_release_rx_dma; | |
1619 | } else if (atmel_use_pdc_rx(port)) { | |
a930e528 ES |
1620 | atmel_port->prepare_rx = &atmel_prepare_rx_pdc; |
1621 | atmel_port->schedule_rx = &atmel_rx_from_pdc; | |
1622 | atmel_port->release_rx = &atmel_release_rx_pdc; | |
1623 | } else { | |
1624 | atmel_port->prepare_rx = NULL; | |
1625 | atmel_port->schedule_rx = &atmel_rx_from_ring; | |
1626 | atmel_port->release_rx = NULL; | |
1627 | } | |
1628 | ||
08f738be ES |
1629 | if (atmel_use_dma_tx(port)) { |
1630 | atmel_port->prepare_tx = &atmel_prepare_tx_dma; | |
1631 | atmel_port->schedule_tx = &atmel_tx_dma; | |
1632 | atmel_port->release_tx = &atmel_release_tx_dma; | |
1633 | } else if (atmel_use_pdc_tx(port)) { | |
a930e528 ES |
1634 | atmel_port->prepare_tx = &atmel_prepare_tx_pdc; |
1635 | atmel_port->schedule_tx = &atmel_tx_pdc; | |
1636 | atmel_port->release_tx = &atmel_release_tx_pdc; | |
1637 | } else { | |
1638 | atmel_port->prepare_tx = NULL; | |
1639 | atmel_port->schedule_tx = &atmel_tx_chars; | |
1640 | atmel_port->release_tx = NULL; | |
1641 | } | |
1642 | } | |
1643 | ||
055560b0 ES |
1644 | /* |
1645 | * Get ip name usart or uart | |
1646 | */ | |
892db58b | 1647 | static void atmel_get_ip_name(struct uart_port *port) |
055560b0 ES |
1648 | { |
1649 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); | |
1650 | int name = UART_GET_IP_NAME(port); | |
731d9cae | 1651 | u32 version; |
055560b0 ES |
1652 | int usart, uart; |
1653 | /* usart and uart ascii */ | |
1654 | usart = 0x55534152; | |
1655 | uart = 0x44424755; | |
1656 | ||
1657 | atmel_port->is_usart = false; | |
1658 | ||
1659 | if (name == usart) { | |
1660 | dev_dbg(port->dev, "This is usart\n"); | |
1661 | atmel_port->is_usart = true; | |
1662 | } else if (name == uart) { | |
1663 | dev_dbg(port->dev, "This is uart\n"); | |
1664 | atmel_port->is_usart = false; | |
1665 | } else { | |
731d9cae NF |
1666 | /* fallback for older SoCs: use version field */ |
1667 | version = UART_GET_IP_VERSION(port); | |
1668 | switch (version) { | |
1669 | case 0x302: | |
1670 | case 0x10213: | |
1671 | dev_dbg(port->dev, "This version is usart\n"); | |
1672 | atmel_port->is_usart = true; | |
1673 | break; | |
1674 | case 0x203: | |
1675 | case 0x10202: | |
1676 | dev_dbg(port->dev, "This version is uart\n"); | |
1677 | atmel_port->is_usart = false; | |
1678 | break; | |
1679 | default: | |
1680 | dev_err(port->dev, "Not supported ip name nor version, set to uart\n"); | |
1681 | } | |
055560b0 | 1682 | } |
055560b0 ES |
1683 | } |
1684 | ||
ab5e4e41 RG |
1685 | static void atmel_free_gpio_irq(struct uart_port *port) |
1686 | { | |
1687 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); | |
1688 | enum mctrl_gpio_idx i; | |
1689 | ||
1690 | for (i = 0; i < UART_GPIO_MAX; i++) | |
1691 | if (atmel_port->gpio_irq[i] >= 0) | |
1692 | free_irq(atmel_port->gpio_irq[i], port); | |
1693 | } | |
1694 | ||
1695 | static int atmel_request_gpio_irq(struct uart_port *port) | |
1696 | { | |
1697 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); | |
1698 | int *irq = atmel_port->gpio_irq; | |
1699 | enum mctrl_gpio_idx i; | |
1700 | int err = 0; | |
1701 | ||
1702 | for (i = 0; (i < UART_GPIO_MAX) && !err; i++) { | |
1703 | if (irq[i] < 0) | |
1704 | continue; | |
1705 | ||
1706 | irq_set_status_flags(irq[i], IRQ_NOAUTOEN); | |
1707 | err = request_irq(irq[i], atmel_interrupt, IRQ_TYPE_EDGE_BOTH, | |
1708 | "atmel_serial", port); | |
1709 | if (err) | |
1710 | dev_err(port->dev, "atmel_startup - Can't get %d irq\n", | |
1711 | irq[i]); | |
1712 | } | |
1713 | ||
1714 | /* | |
1715 | * If something went wrong, rollback. | |
1716 | */ | |
1717 | while (err && (--i >= 0)) | |
1718 | if (irq[i] >= 0) | |
1719 | free_irq(irq[i], port); | |
1720 | ||
1721 | return err; | |
1722 | } | |
1723 | ||
1e6c9c28 AV |
1724 | /* |
1725 | * Perform initialization and enable port for reception | |
1726 | */ | |
7192f92c | 1727 | static int atmel_startup(struct uart_port *port) |
1e6c9c28 | 1728 | { |
33d64c4f | 1729 | struct platform_device *pdev = to_platform_device(port->dev); |
c811ab8c | 1730 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
ebd2c8f6 | 1731 | struct tty_struct *tty = port->state->port.tty; |
1e6c9c28 AV |
1732 | int retval; |
1733 | ||
1734 | /* | |
1735 | * Ensure that no interrupts are enabled otherwise when | |
1736 | * request_irq() is called we could get stuck trying to | |
1737 | * handle an unexpected interrupt | |
1738 | */ | |
1739 | UART_PUT_IDR(port, -1); | |
ab5e4e41 | 1740 | atmel_port->ms_irq_enabled = false; |
1e6c9c28 AV |
1741 | |
1742 | /* | |
1743 | * Allocate the IRQ | |
1744 | */ | |
b843aa21 | 1745 | retval = request_irq(port->irq, atmel_interrupt, IRQF_SHARED, |
ae161068 | 1746 | tty ? tty->name : "atmel_serial", port); |
1e6c9c28 | 1747 | if (retval) { |
ddaa6037 | 1748 | dev_err(port->dev, "atmel_startup - Can't get irq\n"); |
1e6c9c28 AV |
1749 | return retval; |
1750 | } | |
1751 | ||
ab5e4e41 RG |
1752 | /* |
1753 | * Get the GPIO lines IRQ | |
1754 | */ | |
1755 | retval = atmel_request_gpio_irq(port); | |
1756 | if (retval) | |
1757 | goto free_irq; | |
1758 | ||
a6670615 CC |
1759 | /* |
1760 | * Initialize DMA (if necessary) | |
1761 | */ | |
33d64c4f ES |
1762 | atmel_init_property(atmel_port, pdev); |
1763 | ||
a930e528 ES |
1764 | if (atmel_port->prepare_rx) { |
1765 | retval = atmel_port->prepare_rx(port); | |
1766 | if (retval < 0) | |
1767 | atmel_set_ops(port); | |
a6670615 | 1768 | } |
a6670615 | 1769 | |
a930e528 ES |
1770 | if (atmel_port->prepare_tx) { |
1771 | retval = atmel_port->prepare_tx(port); | |
1772 | if (retval < 0) | |
1773 | atmel_set_ops(port); | |
a6670615 | 1774 | } |
1e6c9c28 | 1775 | |
27c0c8e5 | 1776 | /* Save current CSR for comparison in atmel_tasklet_func() */ |
e0b0baad | 1777 | atmel_port->irq_status_prev = atmel_get_lines_status(port); |
27c0c8e5 AN |
1778 | atmel_port->irq_status = atmel_port->irq_status_prev; |
1779 | ||
1e6c9c28 AV |
1780 | /* |
1781 | * Finally, enable the serial port | |
1782 | */ | |
7192f92c | 1783 | UART_PUT_CR(port, ATMEL_US_RSTSTA | ATMEL_US_RSTRX); |
b843aa21 RB |
1784 | /* enable xmit & rcvr */ |
1785 | UART_PUT_CR(port, ATMEL_US_TXEN | ATMEL_US_RXEN); | |
afefc415 | 1786 | |
8bc661bf MR |
1787 | setup_timer(&atmel_port->uart_timer, |
1788 | atmel_uart_timer_callback, | |
1789 | (unsigned long)port); | |
1790 | ||
64e22ebe | 1791 | if (atmel_use_pdc_rx(port)) { |
a6670615 | 1792 | /* set UART timeout */ |
2e68c22f | 1793 | if (!atmel_port->is_usart) { |
2e68c22f ES |
1794 | mod_timer(&atmel_port->uart_timer, |
1795 | jiffies + uart_poll_timeout(port)); | |
1796 | /* set USART timeout */ | |
1797 | } else { | |
1798 | UART_PUT_RTOR(port, PDC_RX_TIMEOUT); | |
1799 | UART_PUT_CR(port, ATMEL_US_STTTO); | |
a6670615 | 1800 | |
2e68c22f ES |
1801 | UART_PUT_IER(port, ATMEL_US_ENDRX | ATMEL_US_TIMEOUT); |
1802 | } | |
a6670615 CC |
1803 | /* enable PDC controller */ |
1804 | UART_PUT_PTCR(port, ATMEL_PDC_RXTEN); | |
34df42f5 | 1805 | } else if (atmel_use_dma_rx(port)) { |
2e68c22f ES |
1806 | /* set UART timeout */ |
1807 | if (!atmel_port->is_usart) { | |
2e68c22f ES |
1808 | mod_timer(&atmel_port->uart_timer, |
1809 | jiffies + uart_poll_timeout(port)); | |
1810 | /* set USART timeout */ | |
1811 | } else { | |
1812 | UART_PUT_RTOR(port, PDC_RX_TIMEOUT); | |
1813 | UART_PUT_CR(port, ATMEL_US_STTTO); | |
34df42f5 | 1814 | |
2e68c22f ES |
1815 | UART_PUT_IER(port, ATMEL_US_TIMEOUT); |
1816 | } | |
a6670615 CC |
1817 | } else { |
1818 | /* enable receive only */ | |
1819 | UART_PUT_IER(port, ATMEL_US_RXRDY); | |
1820 | } | |
afefc415 | 1821 | |
1e6c9c28 | 1822 | return 0; |
ab5e4e41 RG |
1823 | |
1824 | free_irq: | |
1825 | free_irq(port->irq, port); | |
1826 | ||
1827 | return retval; | |
1e6c9c28 AV |
1828 | } |
1829 | ||
479e9b94 PH |
1830 | /* |
1831 | * Flush any TX data submitted for DMA. Called when the TX circular | |
1832 | * buffer is reset. | |
1833 | */ | |
1834 | static void atmel_flush_buffer(struct uart_port *port) | |
1835 | { | |
1836 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); | |
1837 | ||
1838 | if (atmel_use_pdc_tx(port)) { | |
1839 | UART_PUT_TCR(port, 0); | |
1840 | atmel_port->pdc_tx.ofs = 0; | |
1841 | } | |
1842 | } | |
1843 | ||
1e6c9c28 AV |
1844 | /* |
1845 | * Disable the port | |
1846 | */ | |
7192f92c | 1847 | static void atmel_shutdown(struct uart_port *port) |
1e6c9c28 | 1848 | { |
c811ab8c | 1849 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
0cc7c6c7 | 1850 | |
8bc661bf MR |
1851 | /* |
1852 | * Prevent any tasklets being scheduled during | |
1853 | * cleanup | |
1854 | */ | |
1855 | del_timer_sync(&atmel_port->uart_timer); | |
1856 | ||
0cc7c6c7 MR |
1857 | /* |
1858 | * Clear out any scheduled tasklets before | |
1859 | * we destroy the buffers | |
1860 | */ | |
1861 | tasklet_kill(&atmel_port->tasklet); | |
1862 | ||
a6670615 | 1863 | /* |
0cc7c6c7 MR |
1864 | * Ensure everything is stopped and |
1865 | * disable all interrupts, port and break condition. | |
a6670615 CC |
1866 | */ |
1867 | atmel_stop_rx(port); | |
1868 | atmel_stop_tx(port); | |
1869 | ||
0cc7c6c7 MR |
1870 | UART_PUT_CR(port, ATMEL_US_RSTSTA); |
1871 | UART_PUT_IDR(port, -1); | |
1872 | ||
1873 | ||
a6670615 CC |
1874 | /* |
1875 | * Shut-down the DMA. | |
1876 | */ | |
a930e528 ES |
1877 | if (atmel_port->release_rx) |
1878 | atmel_port->release_rx(port); | |
1879 | if (atmel_port->release_tx) | |
1880 | atmel_port->release_tx(port); | |
a6670615 | 1881 | |
bb7e73c5 MD |
1882 | /* |
1883 | * Reset ring buffer pointers | |
1884 | */ | |
1885 | atmel_port->rx_ring.head = 0; | |
1886 | atmel_port->rx_ring.tail = 0; | |
1887 | ||
1e6c9c28 | 1888 | /* |
ab5e4e41 | 1889 | * Free the interrupts |
1e6c9c28 AV |
1890 | */ |
1891 | free_irq(port->irq, port); | |
ab5e4e41 RG |
1892 | atmel_free_gpio_irq(port); |
1893 | ||
1894 | atmel_port->ms_irq_enabled = false; | |
1e6c9c28 | 1895 | |
479e9b94 | 1896 | atmel_flush_buffer(port); |
9afd561a HS |
1897 | } |
1898 | ||
1e6c9c28 AV |
1899 | /* |
1900 | * Power / Clock management. | |
1901 | */ | |
b843aa21 RB |
1902 | static void atmel_serial_pm(struct uart_port *port, unsigned int state, |
1903 | unsigned int oldstate) | |
1e6c9c28 | 1904 | { |
c811ab8c | 1905 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
afefc415 | 1906 | |
1e6c9c28 | 1907 | switch (state) { |
b843aa21 RB |
1908 | case 0: |
1909 | /* | |
1910 | * Enable the peripheral clock for this serial port. | |
1911 | * This is called on uart_open() or a resume event. | |
1912 | */ | |
91f8c2d8 | 1913 | clk_prepare_enable(atmel_port->clk); |
f05596db AS |
1914 | |
1915 | /* re-enable interrupts if we disabled some on suspend */ | |
1916 | UART_PUT_IER(port, atmel_port->backup_imr); | |
b843aa21 RB |
1917 | break; |
1918 | case 3: | |
f05596db AS |
1919 | /* Back up the interrupt mask and disable all interrupts */ |
1920 | atmel_port->backup_imr = UART_GET_IMR(port); | |
1921 | UART_PUT_IDR(port, -1); | |
1922 | ||
b843aa21 RB |
1923 | /* |
1924 | * Disable the peripheral clock for this serial port. | |
1925 | * This is called on uart_close() or a suspend event. | |
1926 | */ | |
91f8c2d8 | 1927 | clk_disable_unprepare(atmel_port->clk); |
b843aa21 RB |
1928 | break; |
1929 | default: | |
ddaa6037 | 1930 | dev_err(port->dev, "atmel_serial: unknown pm %d\n", state); |
1e6c9c28 AV |
1931 | } |
1932 | } | |
1933 | ||
1934 | /* | |
1935 | * Change the port parameters | |
1936 | */ | |
b843aa21 RB |
1937 | static void atmel_set_termios(struct uart_port *port, struct ktermios *termios, |
1938 | struct ktermios *old) | |
1e6c9c28 AV |
1939 | { |
1940 | unsigned long flags; | |
1cf6e8fc CP |
1941 | unsigned int old_mode, mode, imr, quot, baud; |
1942 | ||
1943 | /* save the current mode register */ | |
1944 | mode = old_mode = UART_GET_MR(port); | |
1e6c9c28 | 1945 | |
1cf6e8fc CP |
1946 | /* reset the mode, clock divisor, parity, stop bits and data size */ |
1947 | mode &= ~(ATMEL_US_USCLKS | ATMEL_US_CHRL | ATMEL_US_NBSTOP | | |
1948 | ATMEL_US_PAR | ATMEL_US_USMODE); | |
03abeac0 | 1949 | |
b843aa21 | 1950 | baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16); |
1e6c9c28 AV |
1951 | quot = uart_get_divisor(port, baud); |
1952 | ||
b843aa21 | 1953 | if (quot > 65535) { /* BRGR is 16-bit, so switch to slower clock */ |
03abeac0 AV |
1954 | quot /= 8; |
1955 | mode |= ATMEL_US_USCLKS_MCK_DIV8; | |
1956 | } | |
1e6c9c28 AV |
1957 | |
1958 | /* byte size */ | |
1959 | switch (termios->c_cflag & CSIZE) { | |
1960 | case CS5: | |
7192f92c | 1961 | mode |= ATMEL_US_CHRL_5; |
1e6c9c28 AV |
1962 | break; |
1963 | case CS6: | |
7192f92c | 1964 | mode |= ATMEL_US_CHRL_6; |
1e6c9c28 AV |
1965 | break; |
1966 | case CS7: | |
7192f92c | 1967 | mode |= ATMEL_US_CHRL_7; |
1e6c9c28 AV |
1968 | break; |
1969 | default: | |
7192f92c | 1970 | mode |= ATMEL_US_CHRL_8; |
1e6c9c28 AV |
1971 | break; |
1972 | } | |
1973 | ||
1974 | /* stop bits */ | |
1975 | if (termios->c_cflag & CSTOPB) | |
7192f92c | 1976 | mode |= ATMEL_US_NBSTOP_2; |
1e6c9c28 AV |
1977 | |
1978 | /* parity */ | |
1979 | if (termios->c_cflag & PARENB) { | |
b843aa21 RB |
1980 | /* Mark or Space parity */ |
1981 | if (termios->c_cflag & CMSPAR) { | |
1e6c9c28 | 1982 | if (termios->c_cflag & PARODD) |
7192f92c | 1983 | mode |= ATMEL_US_PAR_MARK; |
1e6c9c28 | 1984 | else |
7192f92c | 1985 | mode |= ATMEL_US_PAR_SPACE; |
b843aa21 | 1986 | } else if (termios->c_cflag & PARODD) |
7192f92c | 1987 | mode |= ATMEL_US_PAR_ODD; |
1e6c9c28 | 1988 | else |
7192f92c | 1989 | mode |= ATMEL_US_PAR_EVEN; |
b843aa21 | 1990 | } else |
7192f92c | 1991 | mode |= ATMEL_US_PAR_NONE; |
1e6c9c28 AV |
1992 | |
1993 | spin_lock_irqsave(&port->lock, flags); | |
1994 | ||
7192f92c | 1995 | port->read_status_mask = ATMEL_US_OVRE; |
1e6c9c28 | 1996 | if (termios->c_iflag & INPCK) |
7192f92c | 1997 | port->read_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE); |
ef8b9ddc | 1998 | if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) |
7192f92c | 1999 | port->read_status_mask |= ATMEL_US_RXBRK; |
1e6c9c28 | 2000 | |
64e22ebe | 2001 | if (atmel_use_pdc_rx(port)) |
a6670615 CC |
2002 | /* need to enable error interrupts */ |
2003 | UART_PUT_IER(port, port->read_status_mask); | |
2004 | ||
1e6c9c28 AV |
2005 | /* |
2006 | * Characters to ignore | |
2007 | */ | |
2008 | port->ignore_status_mask = 0; | |
2009 | if (termios->c_iflag & IGNPAR) | |
7192f92c | 2010 | port->ignore_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE); |
1e6c9c28 | 2011 | if (termios->c_iflag & IGNBRK) { |
7192f92c | 2012 | port->ignore_status_mask |= ATMEL_US_RXBRK; |
1e6c9c28 AV |
2013 | /* |
2014 | * If we're ignoring parity and break indicators, | |
2015 | * ignore overruns too (for real raw support). | |
2016 | */ | |
2017 | if (termios->c_iflag & IGNPAR) | |
7192f92c | 2018 | port->ignore_status_mask |= ATMEL_US_OVRE; |
1e6c9c28 | 2019 | } |
b843aa21 | 2020 | /* TODO: Ignore all characters if CREAD is set.*/ |
1e6c9c28 AV |
2021 | |
2022 | /* update the per-port timeout */ | |
2023 | uart_update_timeout(port, termios->c_cflag, baud); | |
2024 | ||
0ccad870 HS |
2025 | /* |
2026 | * save/disable interrupts. The tty layer will ensure that the | |
2027 | * transmitter is empty if requested by the caller, so there's | |
2028 | * no need to wait for it here. | |
2029 | */ | |
b843aa21 RB |
2030 | imr = UART_GET_IMR(port); |
2031 | UART_PUT_IDR(port, -1); | |
1e6c9c28 AV |
2032 | |
2033 | /* disable receiver and transmitter */ | |
7192f92c | 2034 | UART_PUT_CR(port, ATMEL_US_TXDIS | ATMEL_US_RXDIS); |
1e6c9c28 | 2035 | |
1cf6e8fc | 2036 | /* mode */ |
13bd3e6f RRD |
2037 | if (port->rs485.flags & SER_RS485_ENABLED) { |
2038 | if ((port->rs485.delay_rts_after_send) > 0) | |
2039 | UART_PUT_TTGR(port, port->rs485.delay_rts_after_send); | |
e8faff73 | 2040 | mode |= ATMEL_US_USMODE_RS485; |
1cf6e8fc CP |
2041 | } else if (termios->c_cflag & CRTSCTS) { |
2042 | /* RS232 with hardware handshake (RTS/CTS) */ | |
2043 | mode |= ATMEL_US_USMODE_HWHS; | |
2044 | } else { | |
2045 | /* RS232 without hadware handshake */ | |
2046 | mode |= ATMEL_US_USMODE_NORMAL; | |
e8faff73 CS |
2047 | } |
2048 | ||
1cf6e8fc | 2049 | /* set the mode, clock divisor, parity, stop bits and data size */ |
1e6c9c28 AV |
2050 | UART_PUT_MR(port, mode); |
2051 | ||
1cf6e8fc CP |
2052 | /* |
2053 | * when switching the mode, set the RTS line state according to the | |
2054 | * new mode, otherwise keep the former state | |
2055 | */ | |
2056 | if ((old_mode & ATMEL_US_USMODE) != (mode & ATMEL_US_USMODE)) { | |
2057 | unsigned int rts_state; | |
2058 | ||
2059 | if ((mode & ATMEL_US_USMODE) == ATMEL_US_USMODE_HWHS) { | |
2060 | /* let the hardware control the RTS line */ | |
2061 | rts_state = ATMEL_US_RTSDIS; | |
2062 | } else { | |
2063 | /* force RTS line to low level */ | |
2064 | rts_state = ATMEL_US_RTSEN; | |
2065 | } | |
2066 | ||
2067 | UART_PUT_CR(port, rts_state); | |
2068 | } | |
2069 | ||
1e6c9c28 AV |
2070 | /* set the baud rate */ |
2071 | UART_PUT_BRGR(port, quot); | |
7192f92c HS |
2072 | UART_PUT_CR(port, ATMEL_US_RSTSTA | ATMEL_US_RSTRX); |
2073 | UART_PUT_CR(port, ATMEL_US_TXEN | ATMEL_US_RXEN); | |
1e6c9c28 AV |
2074 | |
2075 | /* restore interrupts */ | |
2076 | UART_PUT_IER(port, imr); | |
2077 | ||
2078 | /* CTS flow-control and modem-status interrupts */ | |
2079 | if (UART_ENABLE_MS(port, termios->c_cflag)) | |
35b675b9 RG |
2080 | atmel_enable_ms(port); |
2081 | else | |
2082 | atmel_disable_ms(port); | |
1e6c9c28 AV |
2083 | |
2084 | spin_unlock_irqrestore(&port->lock, flags); | |
2085 | } | |
2086 | ||
732a84a0 | 2087 | static void atmel_set_ldisc(struct uart_port *port, struct ktermios *termios) |
42bd7a4f | 2088 | { |
732a84a0 | 2089 | if (termios->c_line == N_PPS) { |
42bd7a4f | 2090 | port->flags |= UPF_HARDPPS_CD; |
d41510ce | 2091 | spin_lock_irq(&port->lock); |
42bd7a4f | 2092 | atmel_enable_ms(port); |
d41510ce | 2093 | spin_unlock_irq(&port->lock); |
42bd7a4f VP |
2094 | } else { |
2095 | port->flags &= ~UPF_HARDPPS_CD; | |
cab68f89 PH |
2096 | if (!UART_ENABLE_MS(port, termios->c_cflag)) { |
2097 | spin_lock_irq(&port->lock); | |
2098 | atmel_disable_ms(port); | |
2099 | spin_unlock_irq(&port->lock); | |
2100 | } | |
42bd7a4f VP |
2101 | } |
2102 | } | |
2103 | ||
1e6c9c28 AV |
2104 | /* |
2105 | * Return string describing the specified port | |
2106 | */ | |
7192f92c | 2107 | static const char *atmel_type(struct uart_port *port) |
1e6c9c28 | 2108 | { |
9ab4f88b | 2109 | return (port->type == PORT_ATMEL) ? "ATMEL_SERIAL" : NULL; |
1e6c9c28 AV |
2110 | } |
2111 | ||
2112 | /* | |
2113 | * Release the memory region(s) being used by 'port'. | |
2114 | */ | |
7192f92c | 2115 | static void atmel_release_port(struct uart_port *port) |
1e6c9c28 | 2116 | { |
afefc415 AV |
2117 | struct platform_device *pdev = to_platform_device(port->dev); |
2118 | int size = pdev->resource[0].end - pdev->resource[0].start + 1; | |
2119 | ||
2120 | release_mem_region(port->mapbase, size); | |
2121 | ||
2122 | if (port->flags & UPF_IOREMAP) { | |
2123 | iounmap(port->membase); | |
2124 | port->membase = NULL; | |
2125 | } | |
1e6c9c28 AV |
2126 | } |
2127 | ||
2128 | /* | |
2129 | * Request the memory region(s) being used by 'port'. | |
2130 | */ | |
7192f92c | 2131 | static int atmel_request_port(struct uart_port *port) |
1e6c9c28 | 2132 | { |
afefc415 AV |
2133 | struct platform_device *pdev = to_platform_device(port->dev); |
2134 | int size = pdev->resource[0].end - pdev->resource[0].start + 1; | |
2135 | ||
7192f92c | 2136 | if (!request_mem_region(port->mapbase, size, "atmel_serial")) |
afefc415 AV |
2137 | return -EBUSY; |
2138 | ||
2139 | if (port->flags & UPF_IOREMAP) { | |
2140 | port->membase = ioremap(port->mapbase, size); | |
2141 | if (port->membase == NULL) { | |
2142 | release_mem_region(port->mapbase, size); | |
2143 | return -ENOMEM; | |
2144 | } | |
2145 | } | |
1e6c9c28 | 2146 | |
afefc415 | 2147 | return 0; |
1e6c9c28 AV |
2148 | } |
2149 | ||
2150 | /* | |
2151 | * Configure/autoconfigure the port. | |
2152 | */ | |
7192f92c | 2153 | static void atmel_config_port(struct uart_port *port, int flags) |
1e6c9c28 AV |
2154 | { |
2155 | if (flags & UART_CONFIG_TYPE) { | |
9ab4f88b | 2156 | port->type = PORT_ATMEL; |
7192f92c | 2157 | atmel_request_port(port); |
1e6c9c28 AV |
2158 | } |
2159 | } | |
2160 | ||
2161 | /* | |
2162 | * Verify the new serial_struct (for TIOCSSERIAL). | |
2163 | */ | |
7192f92c | 2164 | static int atmel_verify_port(struct uart_port *port, struct serial_struct *ser) |
1e6c9c28 AV |
2165 | { |
2166 | int ret = 0; | |
9ab4f88b | 2167 | if (ser->type != PORT_UNKNOWN && ser->type != PORT_ATMEL) |
1e6c9c28 AV |
2168 | ret = -EINVAL; |
2169 | if (port->irq != ser->irq) | |
2170 | ret = -EINVAL; | |
2171 | if (ser->io_type != SERIAL_IO_MEM) | |
2172 | ret = -EINVAL; | |
2173 | if (port->uartclk / 16 != ser->baud_base) | |
2174 | ret = -EINVAL; | |
2175 | if ((void *)port->mapbase != ser->iomem_base) | |
2176 | ret = -EINVAL; | |
2177 | if (port->iobase != ser->port) | |
2178 | ret = -EINVAL; | |
2179 | if (ser->hub6 != 0) | |
2180 | ret = -EINVAL; | |
2181 | return ret; | |
2182 | } | |
2183 | ||
8fe2d541 AT |
2184 | #ifdef CONFIG_CONSOLE_POLL |
2185 | static int atmel_poll_get_char(struct uart_port *port) | |
2186 | { | |
2187 | while (!(UART_GET_CSR(port) & ATMEL_US_RXRDY)) | |
2188 | cpu_relax(); | |
2189 | ||
2190 | return UART_GET_CHAR(port); | |
2191 | } | |
2192 | ||
2193 | static void atmel_poll_put_char(struct uart_port *port, unsigned char ch) | |
2194 | { | |
2195 | while (!(UART_GET_CSR(port) & ATMEL_US_TXRDY)) | |
2196 | cpu_relax(); | |
2197 | ||
2198 | UART_PUT_CHAR(port, ch); | |
2199 | } | |
2200 | #endif | |
2201 | ||
7192f92c HS |
2202 | static struct uart_ops atmel_pops = { |
2203 | .tx_empty = atmel_tx_empty, | |
2204 | .set_mctrl = atmel_set_mctrl, | |
2205 | .get_mctrl = atmel_get_mctrl, | |
2206 | .stop_tx = atmel_stop_tx, | |
2207 | .start_tx = atmel_start_tx, | |
2208 | .stop_rx = atmel_stop_rx, | |
2209 | .enable_ms = atmel_enable_ms, | |
2210 | .break_ctl = atmel_break_ctl, | |
2211 | .startup = atmel_startup, | |
2212 | .shutdown = atmel_shutdown, | |
9afd561a | 2213 | .flush_buffer = atmel_flush_buffer, |
7192f92c | 2214 | .set_termios = atmel_set_termios, |
42bd7a4f | 2215 | .set_ldisc = atmel_set_ldisc, |
7192f92c HS |
2216 | .type = atmel_type, |
2217 | .release_port = atmel_release_port, | |
2218 | .request_port = atmel_request_port, | |
2219 | .config_port = atmel_config_port, | |
2220 | .verify_port = atmel_verify_port, | |
2221 | .pm = atmel_serial_pm, | |
8fe2d541 AT |
2222 | #ifdef CONFIG_CONSOLE_POLL |
2223 | .poll_get_char = atmel_poll_get_char, | |
2224 | .poll_put_char = atmel_poll_put_char, | |
2225 | #endif | |
1e6c9c28 AV |
2226 | }; |
2227 | ||
afefc415 AV |
2228 | /* |
2229 | * Configure the port from the platform device resource info. | |
2230 | */ | |
91f8c2d8 | 2231 | static int atmel_init_port(struct atmel_uart_port *atmel_port, |
b843aa21 | 2232 | struct platform_device *pdev) |
1e6c9c28 | 2233 | { |
91f8c2d8 | 2234 | int ret; |
7192f92c | 2235 | struct uart_port *port = &atmel_port->uart; |
574de559 | 2236 | struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev); |
afefc415 | 2237 | |
33d64c4f ES |
2238 | if (!atmel_init_property(atmel_port, pdev)) |
2239 | atmel_set_ops(port); | |
afefc415 | 2240 | |
13bd3e6f | 2241 | atmel_init_rs485(port, pdev); |
a930e528 | 2242 | |
e8faff73 CS |
2243 | port->iotype = UPIO_MEM; |
2244 | port->flags = UPF_BOOT_AUTOCONF; | |
2245 | port->ops = &atmel_pops; | |
2246 | port->fifosize = 1; | |
e8faff73 | 2247 | port->dev = &pdev->dev; |
afefc415 AV |
2248 | port->mapbase = pdev->resource[0].start; |
2249 | port->irq = pdev->resource[1].start; | |
13bd3e6f | 2250 | port->rs485_config = atmel_config_rs485; |
afefc415 | 2251 | |
1ecc26bd RB |
2252 | tasklet_init(&atmel_port->tasklet, atmel_tasklet_func, |
2253 | (unsigned long)port); | |
2254 | ||
2255 | memset(&atmel_port->rx_ring, 0, sizeof(atmel_port->rx_ring)); | |
2256 | ||
5fbe46b6 | 2257 | if (pdata && pdata->regs) { |
75d35213 | 2258 | /* Already mapped by setup code */ |
1acfc7ec | 2259 | port->membase = pdata->regs; |
588edbf3 | 2260 | } else { |
afefc415 AV |
2261 | port->flags |= UPF_IOREMAP; |
2262 | port->membase = NULL; | |
2263 | } | |
1e6c9c28 | 2264 | |
b843aa21 RB |
2265 | /* for console, the clock could already be configured */ |
2266 | if (!atmel_port->clk) { | |
7192f92c | 2267 | atmel_port->clk = clk_get(&pdev->dev, "usart"); |
91f8c2d8 BB |
2268 | if (IS_ERR(atmel_port->clk)) { |
2269 | ret = PTR_ERR(atmel_port->clk); | |
2270 | atmel_port->clk = NULL; | |
2271 | return ret; | |
2272 | } | |
2273 | ret = clk_prepare_enable(atmel_port->clk); | |
2274 | if (ret) { | |
2275 | clk_put(atmel_port->clk); | |
2276 | atmel_port->clk = NULL; | |
2277 | return ret; | |
2278 | } | |
7192f92c | 2279 | port->uartclk = clk_get_rate(atmel_port->clk); |
91f8c2d8 | 2280 | clk_disable_unprepare(atmel_port->clk); |
06a7f058 | 2281 | /* only enable clock when USART is in use */ |
afefc415 | 2282 | } |
a6670615 | 2283 | |
e8faff73 | 2284 | /* Use TXEMPTY for interrupt when rs485 else TXRDY or ENDTX|TXBUFE */ |
13bd3e6f | 2285 | if (port->rs485.flags & SER_RS485_ENABLED) |
e8faff73 | 2286 | atmel_port->tx_done_mask = ATMEL_US_TXEMPTY; |
64e22ebe | 2287 | else if (atmel_use_pdc_tx(port)) { |
a6670615 | 2288 | port->fifosize = PDC_BUFFER_SIZE; |
e8faff73 CS |
2289 | atmel_port->tx_done_mask = ATMEL_US_ENDTX | ATMEL_US_TXBUFE; |
2290 | } else { | |
2291 | atmel_port->tx_done_mask = ATMEL_US_TXRDY; | |
2292 | } | |
91f8c2d8 BB |
2293 | |
2294 | return 0; | |
1e6c9c28 AV |
2295 | } |
2296 | ||
69f6a27b JCPV |
2297 | struct platform_device *atmel_default_console_device; /* the serial console device */ |
2298 | ||
749c4e60 | 2299 | #ifdef CONFIG_SERIAL_ATMEL_CONSOLE |
7192f92c | 2300 | static void atmel_console_putchar(struct uart_port *port, int ch) |
d358788f | 2301 | { |
7192f92c | 2302 | while (!(UART_GET_CSR(port) & ATMEL_US_TXRDY)) |
829dd811 | 2303 | cpu_relax(); |
d358788f RK |
2304 | UART_PUT_CHAR(port, ch); |
2305 | } | |
1e6c9c28 AV |
2306 | |
2307 | /* | |
2308 | * Interrupts are disabled on entering | |
2309 | */ | |
7192f92c | 2310 | static void atmel_console_write(struct console *co, const char *s, u_int count) |
1e6c9c28 | 2311 | { |
7192f92c | 2312 | struct uart_port *port = &atmel_ports[co->index].uart; |
e8faff73 | 2313 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
d358788f | 2314 | unsigned int status, imr; |
39d4c922 | 2315 | unsigned int pdc_tx; |
1e6c9c28 AV |
2316 | |
2317 | /* | |
b843aa21 | 2318 | * First, save IMR and then disable interrupts |
1e6c9c28 | 2319 | */ |
b843aa21 | 2320 | imr = UART_GET_IMR(port); |
e8faff73 | 2321 | UART_PUT_IDR(port, ATMEL_US_RXRDY | atmel_port->tx_done_mask); |
1e6c9c28 | 2322 | |
39d4c922 MP |
2323 | /* Store PDC transmit status and disable it */ |
2324 | pdc_tx = UART_GET_PTSR(port) & ATMEL_PDC_TXTEN; | |
2325 | UART_PUT_PTCR(port, ATMEL_PDC_TXTDIS); | |
2326 | ||
7192f92c | 2327 | uart_console_write(port, s, count, atmel_console_putchar); |
1e6c9c28 AV |
2328 | |
2329 | /* | |
b843aa21 RB |
2330 | * Finally, wait for transmitter to become empty |
2331 | * and restore IMR | |
1e6c9c28 AV |
2332 | */ |
2333 | do { | |
2334 | status = UART_GET_CSR(port); | |
7192f92c | 2335 | } while (!(status & ATMEL_US_TXRDY)); |
39d4c922 MP |
2336 | |
2337 | /* Restore PDC transmit status */ | |
2338 | if (pdc_tx) | |
2339 | UART_PUT_PTCR(port, ATMEL_PDC_TXTEN); | |
2340 | ||
b843aa21 RB |
2341 | /* set interrupts back the way they were */ |
2342 | UART_PUT_IER(port, imr); | |
1e6c9c28 AV |
2343 | } |
2344 | ||
2345 | /* | |
b843aa21 RB |
2346 | * If the port was already initialised (eg, by a boot loader), |
2347 | * try to determine the current setup. | |
1e6c9c28 | 2348 | */ |
b843aa21 RB |
2349 | static void __init atmel_console_get_options(struct uart_port *port, int *baud, |
2350 | int *parity, int *bits) | |
1e6c9c28 AV |
2351 | { |
2352 | unsigned int mr, quot; | |
2353 | ||
1c0fd82f HS |
2354 | /* |
2355 | * If the baud rate generator isn't running, the port wasn't | |
2356 | * initialized by the boot loader. | |
2357 | */ | |
9c81c5c9 | 2358 | quot = UART_GET_BRGR(port) & ATMEL_US_CD; |
1c0fd82f HS |
2359 | if (!quot) |
2360 | return; | |
1e6c9c28 | 2361 | |
7192f92c HS |
2362 | mr = UART_GET_MR(port) & ATMEL_US_CHRL; |
2363 | if (mr == ATMEL_US_CHRL_8) | |
1e6c9c28 AV |
2364 | *bits = 8; |
2365 | else | |
2366 | *bits = 7; | |
2367 | ||
7192f92c HS |
2368 | mr = UART_GET_MR(port) & ATMEL_US_PAR; |
2369 | if (mr == ATMEL_US_PAR_EVEN) | |
1e6c9c28 | 2370 | *parity = 'e'; |
7192f92c | 2371 | else if (mr == ATMEL_US_PAR_ODD) |
1e6c9c28 AV |
2372 | *parity = 'o'; |
2373 | ||
4d5e392c HS |
2374 | /* |
2375 | * The serial core only rounds down when matching this to a | |
2376 | * supported baud rate. Make sure we don't end up slightly | |
2377 | * lower than one of those, as it would make us fall through | |
2378 | * to a much lower baud rate than we really want. | |
2379 | */ | |
4d5e392c | 2380 | *baud = port->uartclk / (16 * (quot - 1)); |
1e6c9c28 AV |
2381 | } |
2382 | ||
7192f92c | 2383 | static int __init atmel_console_setup(struct console *co, char *options) |
1e6c9c28 | 2384 | { |
91f8c2d8 | 2385 | int ret; |
7192f92c | 2386 | struct uart_port *port = &atmel_ports[co->index].uart; |
1e6c9c28 AV |
2387 | int baud = 115200; |
2388 | int bits = 8; | |
2389 | int parity = 'n'; | |
2390 | int flow = 'n'; | |
2391 | ||
b843aa21 RB |
2392 | if (port->membase == NULL) { |
2393 | /* Port not initialized yet - delay setup */ | |
afefc415 | 2394 | return -ENODEV; |
b843aa21 | 2395 | } |
1e6c9c28 | 2396 | |
91f8c2d8 BB |
2397 | ret = clk_prepare_enable(atmel_ports[co->index].clk); |
2398 | if (ret) | |
2399 | return ret; | |
06a7f058 | 2400 | |
b843aa21 | 2401 | UART_PUT_IDR(port, -1); |
7192f92c HS |
2402 | UART_PUT_CR(port, ATMEL_US_RSTSTA | ATMEL_US_RSTRX); |
2403 | UART_PUT_CR(port, ATMEL_US_TXEN | ATMEL_US_RXEN); | |
1e6c9c28 AV |
2404 | |
2405 | if (options) | |
2406 | uart_parse_options(options, &baud, &parity, &bits, &flow); | |
2407 | else | |
7192f92c | 2408 | atmel_console_get_options(port, &baud, &parity, &bits); |
1e6c9c28 AV |
2409 | |
2410 | return uart_set_options(port, co, baud, parity, bits, flow); | |
2411 | } | |
2412 | ||
7192f92c | 2413 | static struct uart_driver atmel_uart; |
1e6c9c28 | 2414 | |
7192f92c HS |
2415 | static struct console atmel_console = { |
2416 | .name = ATMEL_DEVICENAME, | |
2417 | .write = atmel_console_write, | |
1e6c9c28 | 2418 | .device = uart_console_device, |
7192f92c | 2419 | .setup = atmel_console_setup, |
1e6c9c28 AV |
2420 | .flags = CON_PRINTBUFFER, |
2421 | .index = -1, | |
7192f92c | 2422 | .data = &atmel_uart, |
1e6c9c28 AV |
2423 | }; |
2424 | ||
06a7f058 | 2425 | #define ATMEL_CONSOLE_DEVICE (&atmel_console) |
1e6c9c28 | 2426 | |
afefc415 AV |
2427 | /* |
2428 | * Early console initialization (before VM subsystem initialized). | |
2429 | */ | |
7192f92c | 2430 | static int __init atmel_console_init(void) |
1e6c9c28 | 2431 | { |
91f8c2d8 | 2432 | int ret; |
73e2798b | 2433 | if (atmel_default_console_device) { |
0d0a3cc1 | 2434 | struct atmel_uart_data *pdata = |
574de559 | 2435 | dev_get_platdata(&atmel_default_console_device->dev); |
efb8d21b | 2436 | int id = pdata->num; |
4cbf9f48 NF |
2437 | struct atmel_uart_port *port = &atmel_ports[id]; |
2438 | ||
4cbf9f48 NF |
2439 | port->backup_imr = 0; |
2440 | port->uart.line = id; | |
0d0a3cc1 | 2441 | |
4cbf9f48 | 2442 | add_preferred_console(ATMEL_DEVICENAME, id, NULL); |
91f8c2d8 BB |
2443 | ret = atmel_init_port(port, atmel_default_console_device); |
2444 | if (ret) | |
2445 | return ret; | |
7192f92c | 2446 | register_console(&atmel_console); |
afefc415 | 2447 | } |
1e6c9c28 | 2448 | |
1e6c9c28 AV |
2449 | return 0; |
2450 | } | |
b843aa21 | 2451 | |
7192f92c | 2452 | console_initcall(atmel_console_init); |
1e6c9c28 | 2453 | |
afefc415 AV |
2454 | /* |
2455 | * Late console initialization. | |
2456 | */ | |
7192f92c | 2457 | static int __init atmel_late_console_init(void) |
afefc415 | 2458 | { |
b843aa21 RB |
2459 | if (atmel_default_console_device |
2460 | && !(atmel_console.flags & CON_ENABLED)) | |
7192f92c | 2461 | register_console(&atmel_console); |
afefc415 AV |
2462 | |
2463 | return 0; | |
2464 | } | |
b843aa21 | 2465 | |
7192f92c | 2466 | core_initcall(atmel_late_console_init); |
afefc415 | 2467 | |
dfa7f343 HS |
2468 | static inline bool atmel_is_console_port(struct uart_port *port) |
2469 | { | |
2470 | return port->cons && port->cons->index == port->line; | |
2471 | } | |
2472 | ||
1e6c9c28 | 2473 | #else |
7192f92c | 2474 | #define ATMEL_CONSOLE_DEVICE NULL |
dfa7f343 HS |
2475 | |
2476 | static inline bool atmel_is_console_port(struct uart_port *port) | |
2477 | { | |
2478 | return false; | |
2479 | } | |
1e6c9c28 AV |
2480 | #endif |
2481 | ||
7192f92c | 2482 | static struct uart_driver atmel_uart = { |
b843aa21 RB |
2483 | .owner = THIS_MODULE, |
2484 | .driver_name = "atmel_serial", | |
2485 | .dev_name = ATMEL_DEVICENAME, | |
2486 | .major = SERIAL_ATMEL_MAJOR, | |
2487 | .minor = MINOR_START, | |
2488 | .nr = ATMEL_MAX_UART, | |
2489 | .cons = ATMEL_CONSOLE_DEVICE, | |
1e6c9c28 AV |
2490 | }; |
2491 | ||
afefc415 | 2492 | #ifdef CONFIG_PM |
f826caa4 HS |
2493 | static bool atmel_serial_clk_will_stop(void) |
2494 | { | |
2495 | #ifdef CONFIG_ARCH_AT91 | |
2496 | return at91_suspend_entering_slow_clock(); | |
2497 | #else | |
2498 | return false; | |
2499 | #endif | |
2500 | } | |
2501 | ||
b843aa21 RB |
2502 | static int atmel_serial_suspend(struct platform_device *pdev, |
2503 | pm_message_t state) | |
1e6c9c28 | 2504 | { |
afefc415 | 2505 | struct uart_port *port = platform_get_drvdata(pdev); |
c811ab8c | 2506 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
afefc415 | 2507 | |
e1c609ef HS |
2508 | if (atmel_is_console_port(port) && console_suspend_enabled) { |
2509 | /* Drain the TX shifter */ | |
2510 | while (!(UART_GET_CSR(port) & ATMEL_US_TXEMPTY)) | |
2511 | cpu_relax(); | |
2512 | } | |
2513 | ||
f05596db AS |
2514 | /* we can not wake up if we're running on slow clock */ |
2515 | atmel_port->may_wakeup = device_may_wakeup(&pdev->dev); | |
2516 | if (atmel_serial_clk_will_stop()) | |
2517 | device_set_wakeup_enable(&pdev->dev, 0); | |
2518 | ||
2519 | uart_suspend_port(&atmel_uart, port); | |
1e6c9c28 | 2520 | |
afefc415 AV |
2521 | return 0; |
2522 | } | |
1e6c9c28 | 2523 | |
7192f92c | 2524 | static int atmel_serial_resume(struct platform_device *pdev) |
afefc415 AV |
2525 | { |
2526 | struct uart_port *port = platform_get_drvdata(pdev); | |
c811ab8c | 2527 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
1e6c9c28 | 2528 | |
f05596db AS |
2529 | uart_resume_port(&atmel_uart, port); |
2530 | device_set_wakeup_enable(&pdev->dev, atmel_port->may_wakeup); | |
1e6c9c28 AV |
2531 | |
2532 | return 0; | |
2533 | } | |
afefc415 | 2534 | #else |
7192f92c HS |
2535 | #define atmel_serial_suspend NULL |
2536 | #define atmel_serial_resume NULL | |
afefc415 | 2537 | #endif |
1e6c9c28 | 2538 | |
e0b0baad RG |
2539 | static int atmel_init_gpios(struct atmel_uart_port *p, struct device *dev) |
2540 | { | |
ab5e4e41 RG |
2541 | enum mctrl_gpio_idx i; |
2542 | struct gpio_desc *gpiod; | |
2543 | ||
e0b0baad RG |
2544 | p->gpios = mctrl_gpio_init(dev, 0); |
2545 | if (IS_ERR_OR_NULL(p->gpios)) | |
2546 | return -1; | |
2547 | ||
ab5e4e41 RG |
2548 | for (i = 0; i < UART_GPIO_MAX; i++) { |
2549 | gpiod = mctrl_gpio_to_gpiod(p->gpios, i); | |
2550 | if (gpiod && (gpiod_get_direction(gpiod) == GPIOF_DIR_IN)) | |
2551 | p->gpio_irq[i] = gpiod_to_irq(gpiod); | |
2552 | else | |
2553 | p->gpio_irq[i] = -EINVAL; | |
2554 | } | |
2555 | ||
e0b0baad RG |
2556 | return 0; |
2557 | } | |
2558 | ||
9671f099 | 2559 | static int atmel_serial_probe(struct platform_device *pdev) |
1e6c9c28 | 2560 | { |
7192f92c | 2561 | struct atmel_uart_port *port; |
5fbe46b6 | 2562 | struct device_node *np = pdev->dev.of_node; |
574de559 | 2563 | struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev); |
1ecc26bd | 2564 | void *data; |
4cbf9f48 | 2565 | int ret = -ENODEV; |
bd737f87 | 2566 | bool rs485_enabled; |
1e6c9c28 | 2567 | |
9d09daf8 | 2568 | BUILD_BUG_ON(ATMEL_SERIAL_RINGSIZE & (ATMEL_SERIAL_RINGSIZE - 1)); |
1ecc26bd | 2569 | |
5fbe46b6 NF |
2570 | if (np) |
2571 | ret = of_alias_get_id(np, "serial"); | |
2572 | else | |
2573 | if (pdata) | |
2574 | ret = pdata->num; | |
4cbf9f48 NF |
2575 | |
2576 | if (ret < 0) | |
5fbe46b6 | 2577 | /* port id not found in platform data nor device-tree aliases: |
4cbf9f48 | 2578 | * auto-enumerate it */ |
503bded9 | 2579 | ret = find_first_zero_bit(atmel_ports_in_use, ATMEL_MAX_UART); |
4cbf9f48 | 2580 | |
503bded9 | 2581 | if (ret >= ATMEL_MAX_UART) { |
4cbf9f48 NF |
2582 | ret = -ENODEV; |
2583 | goto err; | |
2584 | } | |
2585 | ||
503bded9 | 2586 | if (test_and_set_bit(ret, atmel_ports_in_use)) { |
4cbf9f48 NF |
2587 | /* port already in use */ |
2588 | ret = -EBUSY; | |
2589 | goto err; | |
2590 | } | |
2591 | ||
2592 | port = &atmel_ports[ret]; | |
f05596db | 2593 | port->backup_imr = 0; |
4cbf9f48 | 2594 | port->uart.line = ret; |
e0b0baad RG |
2595 | |
2596 | ret = atmel_init_gpios(port, &pdev->dev); | |
2597 | if (ret < 0) | |
2598 | dev_err(&pdev->dev, "%s", | |
2599 | "Failed to initialize GPIOs. The serial port may not work as expected"); | |
f05596db | 2600 | |
91f8c2d8 BB |
2601 | ret = atmel_init_port(port, pdev); |
2602 | if (ret) | |
6fbb9bdf | 2603 | goto err_clear_bit; |
1e6c9c28 | 2604 | |
64e22ebe | 2605 | if (!atmel_use_pdc_rx(&port->uart)) { |
a6670615 | 2606 | ret = -ENOMEM; |
6433471d HS |
2607 | data = kmalloc(sizeof(struct atmel_uart_char) |
2608 | * ATMEL_SERIAL_RINGSIZE, GFP_KERNEL); | |
a6670615 CC |
2609 | if (!data) |
2610 | goto err_alloc_ring; | |
2611 | port->rx_ring.buf = data; | |
2612 | } | |
1ecc26bd | 2613 | |
bd737f87 RRD |
2614 | rs485_enabled = port->uart.rs485.flags & SER_RS485_ENABLED; |
2615 | ||
7192f92c | 2616 | ret = uart_add_one_port(&atmel_uart, &port->uart); |
dfa7f343 HS |
2617 | if (ret) |
2618 | goto err_add_port; | |
2619 | ||
8da14b5f | 2620 | #ifdef CONFIG_SERIAL_ATMEL_CONSOLE |
06a7f058 DB |
2621 | if (atmel_is_console_port(&port->uart) |
2622 | && ATMEL_CONSOLE_DEVICE->flags & CON_ENABLED) { | |
2623 | /* | |
2624 | * The serial core enabled the clock for us, so undo | |
91f8c2d8 | 2625 | * the clk_prepare_enable() in atmel_console_setup() |
06a7f058 | 2626 | */ |
91f8c2d8 | 2627 | clk_disable_unprepare(port->clk); |
06a7f058 | 2628 | } |
8da14b5f | 2629 | #endif |
06a7f058 | 2630 | |
dfa7f343 HS |
2631 | device_init_wakeup(&pdev->dev, 1); |
2632 | platform_set_drvdata(pdev, port); | |
2633 | ||
d4f64187 CP |
2634 | /* |
2635 | * The peripheral clock has been disabled by atmel_init_port(): | |
2636 | * enable it before accessing I/O registers | |
2637 | */ | |
2638 | clk_prepare_enable(port->clk); | |
2639 | ||
bd737f87 | 2640 | if (rs485_enabled) { |
5dfbd1d7 CS |
2641 | UART_PUT_MR(&port->uart, ATMEL_US_USMODE_NORMAL); |
2642 | UART_PUT_CR(&port->uart, ATMEL_US_RTSEN); | |
2643 | } | |
2644 | ||
055560b0 ES |
2645 | /* |
2646 | * Get port name of usart or uart | |
2647 | */ | |
892db58b | 2648 | atmel_get_ip_name(&port->uart); |
055560b0 | 2649 | |
d4f64187 CP |
2650 | /* |
2651 | * The peripheral clock can now safely be disabled till the port | |
2652 | * is used | |
2653 | */ | |
2654 | clk_disable_unprepare(port->clk); | |
2655 | ||
dfa7f343 HS |
2656 | return 0; |
2657 | ||
2658 | err_add_port: | |
1ecc26bd RB |
2659 | kfree(port->rx_ring.buf); |
2660 | port->rx_ring.buf = NULL; | |
2661 | err_alloc_ring: | |
dfa7f343 | 2662 | if (!atmel_is_console_port(&port->uart)) { |
dfa7f343 HS |
2663 | clk_put(port->clk); |
2664 | port->clk = NULL; | |
afefc415 | 2665 | } |
6fbb9bdf CP |
2666 | err_clear_bit: |
2667 | clear_bit(port->uart.line, atmel_ports_in_use); | |
4cbf9f48 | 2668 | err: |
afefc415 AV |
2669 | return ret; |
2670 | } | |
2671 | ||
ae8d8a14 | 2672 | static int atmel_serial_remove(struct platform_device *pdev) |
afefc415 AV |
2673 | { |
2674 | struct uart_port *port = platform_get_drvdata(pdev); | |
c811ab8c | 2675 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
afefc415 AV |
2676 | int ret = 0; |
2677 | ||
f50c995f MR |
2678 | tasklet_kill(&atmel_port->tasklet); |
2679 | ||
afefc415 | 2680 | device_init_wakeup(&pdev->dev, 0); |
afefc415 | 2681 | |
dfa7f343 HS |
2682 | ret = uart_remove_one_port(&atmel_uart, port); |
2683 | ||
1ecc26bd RB |
2684 | kfree(atmel_port->rx_ring.buf); |
2685 | ||
dfa7f343 HS |
2686 | /* "port" is allocated statically, so we shouldn't free it */ |
2687 | ||
503bded9 | 2688 | clear_bit(port->line, atmel_ports_in_use); |
4cbf9f48 | 2689 | |
dfa7f343 | 2690 | clk_put(atmel_port->clk); |
afefc415 AV |
2691 | |
2692 | return ret; | |
2693 | } | |
2694 | ||
7192f92c HS |
2695 | static struct platform_driver atmel_serial_driver = { |
2696 | .probe = atmel_serial_probe, | |
2d47b716 | 2697 | .remove = atmel_serial_remove, |
7192f92c HS |
2698 | .suspend = atmel_serial_suspend, |
2699 | .resume = atmel_serial_resume, | |
afefc415 | 2700 | .driver = { |
1e8ea802 | 2701 | .name = "atmel_usart", |
5fbe46b6 | 2702 | .of_match_table = of_match_ptr(atmel_serial_dt_ids), |
afefc415 AV |
2703 | }, |
2704 | }; | |
2705 | ||
7192f92c | 2706 | static int __init atmel_serial_init(void) |
afefc415 AV |
2707 | { |
2708 | int ret; | |
2709 | ||
7192f92c | 2710 | ret = uart_register_driver(&atmel_uart); |
afefc415 AV |
2711 | if (ret) |
2712 | return ret; | |
2713 | ||
7192f92c | 2714 | ret = platform_driver_register(&atmel_serial_driver); |
afefc415 | 2715 | if (ret) |
7192f92c | 2716 | uart_unregister_driver(&atmel_uart); |
afefc415 AV |
2717 | |
2718 | return ret; | |
2719 | } | |
2720 | ||
7192f92c | 2721 | static void __exit atmel_serial_exit(void) |
afefc415 | 2722 | { |
7192f92c HS |
2723 | platform_driver_unregister(&atmel_serial_driver); |
2724 | uart_unregister_driver(&atmel_uart); | |
1e6c9c28 AV |
2725 | } |
2726 | ||
7192f92c HS |
2727 | module_init(atmel_serial_init); |
2728 | module_exit(atmel_serial_exit); | |
1e6c9c28 AV |
2729 | |
2730 | MODULE_AUTHOR("Rick Bronson"); | |
7192f92c | 2731 | MODULE_DESCRIPTION("Atmel AT91 / AT32 serial port driver"); |
1e6c9c28 | 2732 | MODULE_LICENSE("GPL"); |
e169c139 | 2733 | MODULE_ALIAS("platform:atmel_usart"); |