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serial: imx: use Tx ready rather than Tx empty irq
[linux-block.git] / drivers / tty / serial / atmel_serial.c
CommitLineData
e3b3d0f5 1// SPDX-License-Identifier: GPL-2.0+
1e6c9c28 2/*
72ce5732 3 * Driver for Atmel AT91 Serial ports
1e6c9c28
AV		 4 * Copyright (C) 2003 Rick Bronson
5 *
6 * Based on drivers/char/serial_sa1100.c, by Deep Blue Solutions Ltd.
7 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
8 *
a6670615 9 * DMA support added by Chip Coldwell.
1e6c9c28 10 */
1e6c9c28
AV		 11#include <linux/tty.h>
12#include <linux/ioport.h>
13#include <linux/slab.h>
14#include <linux/init.h>
15#include <linux/serial.h>
afefc415 16#include <linux/clk.h>
1e6c9c28
AV		 17#include <linux/console.h>
18#include <linux/sysrq.h>
19#include <linux/tty_flip.h>
afefc415 20#include <linux/platform_device.h>
5fbe46b6
NF		 21#include <linux/of.h>
22#include <linux/of_device.h>
354e57f3 23#include <linux/of_gpio.h>
a6670615 24#include <linux/dma-mapping.h>
6b997bab 25#include <linux/dmaengine.h>
93a3ddc2 26#include <linux/atmel_pdc.h>
e8faff73 27#include <linux/uaccess.h>
bcd2360c 28#include <linux/platform_data/atmel.h>
2e68c22f 29#include <linux/timer.h>
354e57f3 30#include <linux/gpio.h>
e0b0baad
RG		 31#include <linux/gpio/consumer.h>
32#include <linux/err.h>
ab5e4e41 33#include <linux/irq.h>
2c7af5ba 34#include <linux/suspend.h>
2b5cf14b 35#include <linux/mm.h>
1e6c9c28 36
377fedd1 37#include <asm/div64.h>
1e6c9c28 38#include <asm/io.h>
f7512e7c 39#include <asm/ioctls.h>
1e6c9c28 40
a6670615
CC		 41#define PDC_BUFFER_SIZE 512
42/* Revisit: We should calculate this based on the actual port settings */
43#define PDC_RX_TIMEOUT (3 * 10) /* 3 bytes */
44
b5199d46
CP		 45/* The minium number of data FIFOs should be able to contain */
46#define ATMEL_MIN_FIFO_SIZE 8
47/*
48 * These two offsets are substracted from the RX FIFO size to define the RTS
49 * high and low thresholds
50 */
51#define ATMEL_RTS_HIGH_OFFSET 16
52#define ATMEL_RTS_LOW_OFFSET 20
53
749c4e60 54#if defined(CONFIG_SERIAL_ATMEL_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
1e6c9c28
AV		 55#define SUPPORT_SYSRQ
56#endif
57
58#include <linux/serial_core.h>
59
e0b0baad 60#include "serial_mctrl_gpio.h"
8961df89 61#include "atmel_serial.h"
e0b0baad 62
e8faff73
CS		 63static void atmel_start_rx(struct uart_port *port);
64static void atmel_stop_rx(struct uart_port *port);
65
749c4e60 66#ifdef CONFIG_SERIAL_ATMEL_TTYAT
1e6c9c28
AV		 67
68/* Use device name ttyAT, major 204 and minor 154-169. This is necessary if we
69 * should coexist with the 8250 driver, such as if we have an external 16C550
70 * UART. */
7192f92c 71#define SERIAL_ATMEL_MAJOR 204
1e6c9c28 72#define MINOR_START 154
7192f92c 73#define ATMEL_DEVICENAME "ttyAT"
1e6c9c28
AV		 74
75#else
76
77/* Use device name ttyS, major 4, minor 64-68. This is the usual serial port
78 * name, but it is legally reserved for the 8250 driver. */
7192f92c 79#define SERIAL_ATMEL_MAJOR TTY_MAJOR
1e6c9c28 80#define MINOR_START 64
7192f92c 81#define ATMEL_DEVICENAME "ttyS"
1e6c9c28
AV		 82
83#endif
84
7192f92c 85#define ATMEL_ISR_PASS_LIMIT 256
1e6c9c28 86
a6670615
CC		 87struct atmel_dma_buffer {
88 unsigned char *buf;
89 dma_addr_t dma_addr;
90 unsigned int dma_size;
91 unsigned int ofs;
92};
93
1ecc26bd
RB		 94struct atmel_uart_char {
95 u16 status;
96 u16 ch;
97};
98
637ba54f
LD		 99/*
100 * Be careful, the real size of the ring buffer is
101 * sizeof(atmel_uart_char) * ATMEL_SERIAL_RINGSIZE. It means that ring buffer
102 * can contain up to 1024 characters in PIO mode and up to 4096 characters in
103 * DMA mode.
104 */
1ecc26bd
RB		 105#define ATMEL_SERIAL_RINGSIZE 1024
106
9af92fbf
AB		 107/*
108 * at91: 6 USARTs and one DBGU port (SAM9260)
432f9748 109 * samx7: 3 USARTs and 5 UARTs
9af92fbf 110 */
432f9748 111#define ATMEL_MAX_UART 8
9af92fbf 112
afefc415
AV		 113/*
114 * We wrap our port structure around the generic uart_port.
115 */
7192f92c 116struct atmel_uart_port {
afefc415
AV		 117 struct uart_port uart; /* uart */
118 struct clk *clk; /* uart clock */
f05596db
AS		 119 int may_wakeup; /* cached value of device_may_wakeup for times we need to disable it */
120 u32 backup_imr; /* IMR saved during suspend */
9e6077bd 121 int break_active; /* break being received */
1ecc26bd 122
34df42f5 123 bool use_dma_rx; /* enable DMA receiver */
64e22ebe 124 bool use_pdc_rx; /* enable PDC receiver */
a6670615
CC		 125 short pdc_rx_idx; /* current PDC RX buffer */
126 struct atmel_dma_buffer pdc_rx[2]; /* PDC receier */
127
08f738be 128 bool use_dma_tx; /* enable DMA transmitter */
64e22ebe 129 bool use_pdc_tx; /* enable PDC transmitter */
a6670615
CC		 130 struct atmel_dma_buffer pdc_tx; /* PDC transmitter */
131
08f738be 132 spinlock_t lock_tx; /* port lock */
34df42f5 133 spinlock_t lock_rx; /* port lock */
08f738be 134 struct dma_chan *chan_tx;
34df42f5 135 struct dma_chan *chan_rx;
08f738be 136 struct dma_async_tx_descriptor *desc_tx;
34df42f5 137 struct dma_async_tx_descriptor *desc_rx;
08f738be 138 dma_cookie_t cookie_tx;
34df42f5 139 dma_cookie_t cookie_rx;
08f738be 140 struct scatterlist sg_tx;
34df42f5 141 struct scatterlist sg_rx;
00e8e658
NF		 142 struct tasklet_struct tasklet_rx;
143 struct tasklet_struct tasklet_tx;
98f2082c 144 atomic_t tasklet_shutdown;
1ecc26bd 145 unsigned int irq_status_prev;
5f258b3e 146 unsigned int tx_len;
1ecc26bd
RB		 147
148 struct circ_buf rx_ring;
e8faff73 149
e0b0baad 150 struct mctrl_gpios *gpios;
377fedd1
NF		 151 u32 backup_mode; /* MR saved during iso7816 operations */
152 u32 backup_brgr; /* BRGR saved during iso7816 operations */
e8faff73 153 unsigned int tx_done_mask;
b5199d46
CP		 154 u32 fifo_size;
155 u32 rts_high;
156 u32 rts_low;
ab5e4e41 157 bool ms_irq_enabled;
2958ccee 158 u32 rtor; /* address of receiver timeout register if it exists */
5bf5635a 159 bool has_frac_baudrate;
4b769371
NF		 160 bool has_hw_timer;
161 struct timer_list uart_timer;
2c7af5ba 162
ea04f82a 163 bool tx_stopped;
2c7af5ba
BB		 164 bool suspended;
165 unsigned int pending;
166 unsigned int pending_status;
167 spinlock_t lock_suspended;
168
69646d7a
RS		 169 bool hd_start_rx; /* can start RX during half-duplex operation */
170
377fedd1
NF		 171 /* ISO7816 */
172 unsigned int fidi_min;
173 unsigned int fidi_max;
174
488ae82d 175#ifdef CONFIG_PM
6a5f0e2f
AB		 176 struct {
177 u32 cr;
178 u32 mr;
179 u32 imr;
180 u32 brgr;
181 u32 rtor;
182 u32 ttgr;
183 u32 fmr;
184 u32 fimr;
185 } cache;
488ae82d 186#endif
6a5f0e2f 187
a930e528
ES		 188 int (*prepare_rx)(struct uart_port *port);
189 int (*prepare_tx)(struct uart_port *port);
190 void (*schedule_rx)(struct uart_port *port);
191 void (*schedule_tx)(struct uart_port *port);
192 void (*release_rx)(struct uart_port *port);
193 void (*release_tx)(struct uart_port *port);
afefc415
AV		 194};
195
7192f92c 196static struct atmel_uart_port atmel_ports[ATMEL_MAX_UART];
503bded9 197static DECLARE_BITMAP(atmel_ports_in_use, ATMEL_MAX_UART);
afefc415 198
1e6c9c28 199#ifdef SUPPORT_SYSRQ
7192f92c 200static struct console atmel_console;
1e6c9c28
AV		 201#endif
202
5fbe46b6
NF		 203#if defined(CONFIG_OF)
204static const struct of_device_id atmel_serial_dt_ids[] = {
c24d2531 205 { .compatible = "atmel,at91rm9200-usart-serial" },
5fbe46b6
NF		 206 { /* sentinel */ }
207};
5fbe46b6
NF		 208#endif
209
c811ab8c
HS		 210static inline struct atmel_uart_port *
211to_atmel_uart_port(struct uart_port *uart)
212{
213 return container_of(uart, struct atmel_uart_port, uart);
214}
215
4e7decda
CP		 216static inline u32 atmel_uart_readl(struct uart_port *port, u32 reg)
217{
218 return __raw_readl(port->membase + reg);
219}
220
221static inline void atmel_uart_writel(struct uart_port *port, u32 reg, u32 value)
222{
223 __raw_writel(value, port->membase + reg);
224}
225
a6499435 226static inline u8 atmel_uart_read_char(struct uart_port *port)
b5199d46 227{
a6499435 228 return __raw_readb(port->membase + ATMEL_US_RHR);
b5199d46
CP		 229}
230
a6499435
CP		 231static inline void atmel_uart_write_char(struct uart_port *port, u8 value)
232{
233 __raw_writeb(value, port->membase + ATMEL_US_THR);
234}
235
f3040983
RS		 236static inline int atmel_uart_is_half_duplex(struct uart_port *port)
237{
238 return ((port->rs485.flags & SER_RS485_ENABLED) &&
239 !(port->rs485.flags & SER_RS485_RX_DURING_TX)) ||
240 (port->iso7816.flags & SER_ISO7816_ENABLED);
241}
242
a6670615 243#ifdef CONFIG_SERIAL_ATMEL_PDC
64e22ebe 244static bool atmel_use_pdc_rx(struct uart_port *port)
a6670615 245{
c811ab8c 246 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
a6670615 247
64e22ebe 248 return atmel_port->use_pdc_rx;
a6670615
CC		 249}
250
64e22ebe 251static bool atmel_use_pdc_tx(struct uart_port *port)
a6670615 252{
c811ab8c 253 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
a6670615 254
64e22ebe 255 return atmel_port->use_pdc_tx;
a6670615
CC		 256}
257#else
64e22ebe 258static bool atmel_use_pdc_rx(struct uart_port *port)
a6670615
CC		 259{
260 return false;
261}
262
64e22ebe 263static bool atmel_use_pdc_tx(struct uart_port *port)
a6670615
CC		 264{
265 return false;
266}
267#endif
268
08f738be
ES		 269static bool atmel_use_dma_tx(struct uart_port *port)
270{
271 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
272
273 return atmel_port->use_dma_tx;
274}
275
34df42f5
ES		 276static bool atmel_use_dma_rx(struct uart_port *port)
277{
278 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
279
280 return atmel_port->use_dma_rx;
281}
282
5be605ac
AB		 283static bool atmel_use_fifo(struct uart_port *port)
284{
285 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
286
287 return atmel_port->fifo_size;
288}
289
98f2082c
NF		 290static void atmel_tasklet_schedule(struct atmel_uart_port *atmel_port,
291 struct tasklet_struct *t)
292{
293 if (!atomic_read(&atmel_port->tasklet_shutdown))
294 tasklet_schedule(t);
295}
296
e0b0baad
RG		 297static unsigned int atmel_get_lines_status(struct uart_port *port)
298{
299 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
300 unsigned int status, ret = 0;
301
4e7decda 302 status = atmel_uart_readl(port, ATMEL_US_CSR);
e0b0baad
RG		 303
304 mctrl_gpio_get(atmel_port->gpios, &ret);
305
306 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios,
307 UART_GPIO_CTS))) {
308 if (ret & TIOCM_CTS)
309 status &= ~ATMEL_US_CTS;
310 else
311 status |= ATMEL_US_CTS;
312 }
313
314 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios,
315 UART_GPIO_DSR))) {
316 if (ret & TIOCM_DSR)
317 status &= ~ATMEL_US_DSR;
318 else
319 status |= ATMEL_US_DSR;
320 }
321
322 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios,
323 UART_GPIO_RI))) {
324 if (ret & TIOCM_RI)
325 status &= ~ATMEL_US_RI;
326 else
327 status |= ATMEL_US_RI;
328 }
329
330 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios,
331 UART_GPIO_DCD))) {
332 if (ret & TIOCM_CD)
333 status &= ~ATMEL_US_DCD;
334 else
335 status |= ATMEL_US_DCD;
336 }
337
338 return status;
339}
340
e8faff73 341/* Enable or disable the rs485 support */
13bd3e6f
RRD		 342static int atmel_config_rs485(struct uart_port *port,
343 struct serial_rs485 *rs485conf)
e8faff73
CS		 344{
345 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
346 unsigned int mode;
e8faff73
CS		 347
348 /* Disable interrupts */
4e7decda 349 atmel_uart_writel(port, ATMEL_US_IDR, atmel_port->tx_done_mask);
e8faff73 350
4e7decda 351 mode = atmel_uart_readl(port, ATMEL_US_MR);
e8faff73
CS		 352
353 /* Resetting serial mode to RS232 (0x0) */
354 mode &= ~ATMEL_US_USMODE;
355
13bd3e6f 356 port->rs485 = *rs485conf;
e8faff73
CS		 357
358 if (rs485conf->flags & SER_RS485_ENABLED) {
359 dev_dbg(port->dev, "Setting UART to RS485\n");
360 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY;
4e7decda
CP		 361 atmel_uart_writel(port, ATMEL_US_TTGR,
362 rs485conf->delay_rts_after_send);
e8faff73
CS		 363 mode |= ATMEL_US_USMODE_RS485;
364 } else {
365 dev_dbg(port->dev, "Setting UART to RS232\n");
64e22ebe 366 if (atmel_use_pdc_tx(port))
e8faff73
CS		 367 atmel_port->tx_done_mask = ATMEL_US_ENDTX |
368 ATMEL_US_TXBUFE;
369 else
370 atmel_port->tx_done_mask = ATMEL_US_TXRDY;
371 }
4e7decda 372 atmel_uart_writel(port, ATMEL_US_MR, mode);
e8faff73
CS		 373
374 /* Enable interrupts */
4e7decda 375 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->tx_done_mask);
e8faff73 376
13bd3e6f 377 return 0;
e8faff73
CS		 378}
379
377fedd1
NF		 380static unsigned int atmel_calc_cd(struct uart_port *port,
381 struct serial_iso7816 *iso7816conf)
382{
383 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
384 unsigned int cd;
385 u64 mck_rate;
386
387 mck_rate = (u64)clk_get_rate(atmel_port->clk);
388 do_div(mck_rate, iso7816conf->clk);
389 cd = mck_rate;
390 return cd;
391}
392
393static unsigned int atmel_calc_fidi(struct uart_port *port,
394 struct serial_iso7816 *iso7816conf)
395{
396 u64 fidi = 0;
397
398 if (iso7816conf->sc_fi && iso7816conf->sc_di) {
399 fidi = (u64)iso7816conf->sc_fi;
400 do_div(fidi, iso7816conf->sc_di);
401 }
402 return (u32)fidi;
403}
404
405/* Enable or disable the iso7816 support */
406/* Called with interrupts disabled */
407static int atmel_config_iso7816(struct uart_port *port,
408 struct serial_iso7816 *iso7816conf)
409{
410 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
411 unsigned int mode;
412 unsigned int cd, fidi;
413 int ret = 0;
414
415 /* Disable interrupts */
416 atmel_uart_writel(port, ATMEL_US_IDR, atmel_port->tx_done_mask);
417
418 mode = atmel_uart_readl(port, ATMEL_US_MR);
419
420 if (iso7816conf->flags & SER_ISO7816_ENABLED) {
421 mode &= ~ATMEL_US_USMODE;
422
423 if (iso7816conf->tg > 255) {
424 dev_err(port->dev, "ISO7816: Timeguard exceeding 255\n");
425 memset(iso7816conf, 0, sizeof(struct serial_iso7816));
426 ret = -EINVAL;
427 goto err_out;
428 }
429
430 if ((iso7816conf->flags & SER_ISO7816_T_PARAM)
431 == SER_ISO7816_T(0)) {
432 mode |= ATMEL_US_USMODE_ISO7816_T0 | ATMEL_US_DSNACK;
433 } else if ((iso7816conf->flags & SER_ISO7816_T_PARAM)
434 == SER_ISO7816_T(1)) {
435 mode |= ATMEL_US_USMODE_ISO7816_T1 | ATMEL_US_INACK;
436 } else {
437 dev_err(port->dev, "ISO7816: Type not supported\n");
438 memset(iso7816conf, 0, sizeof(struct serial_iso7816));
439 ret = -EINVAL;
440 goto err_out;
441 }
442
443 mode &= ~(ATMEL_US_USCLKS | ATMEL_US_NBSTOP | ATMEL_US_PAR);
444
445 /* select mck clock, and output */
446 mode |= ATMEL_US_USCLKS_MCK | ATMEL_US_CLKO;
447 /* set parity for normal/inverse mode + max iterations */
448 mode |= ATMEL_US_PAR_EVEN | ATMEL_US_NBSTOP_1 | ATMEL_US_MAX_ITER(3);
449
450 cd = atmel_calc_cd(port, iso7816conf);
451 fidi = atmel_calc_fidi(port, iso7816conf);
452 if (fidi == 0) {
453 dev_warn(port->dev, "ISO7816 fidi = 0, Generator generates no signal\n");
454 } else if (fidi < atmel_port->fidi_min
455 || fidi > atmel_port->fidi_max) {
456 dev_err(port->dev, "ISO7816 fidi = %u, value not supported\n", fidi);
457 memset(iso7816conf, 0, sizeof(struct serial_iso7816));
458 ret = -EINVAL;
459 goto err_out;
460 }
461
462 if (!(port->iso7816.flags & SER_ISO7816_ENABLED)) {
463 /* port not yet in iso7816 mode: store configuration */
464 atmel_port->backup_mode = atmel_uart_readl(port, ATMEL_US_MR);
465 atmel_port->backup_brgr = atmel_uart_readl(port, ATMEL_US_BRGR);
466 }
467
468 atmel_uart_writel(port, ATMEL_US_TTGR, iso7816conf->tg);
469 atmel_uart_writel(port, ATMEL_US_BRGR, cd);
470 atmel_uart_writel(port, ATMEL_US_FIDI, fidi);
471
472 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXDIS | ATMEL_US_RXEN);
473 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY | ATMEL_US_NACK | ATMEL_US_ITERATION;
474 } else {
475 dev_dbg(port->dev, "Setting UART back to RS232\n");
476 /* back to last RS232 settings */
477 mode = atmel_port->backup_mode;
478 memset(iso7816conf, 0, sizeof(struct serial_iso7816));
479 atmel_uart_writel(port, ATMEL_US_TTGR, 0);
480 atmel_uart_writel(port, ATMEL_US_BRGR, atmel_port->backup_brgr);
481 atmel_uart_writel(port, ATMEL_US_FIDI, 0x174);
482
483 if (atmel_use_pdc_tx(port))
484 atmel_port->tx_done_mask = ATMEL_US_ENDTX |
485 ATMEL_US_TXBUFE;
486 else
487 atmel_port->tx_done_mask = ATMEL_US_TXRDY;
488 }
489
490 port->iso7816 = *iso7816conf;
491
492 atmel_uart_writel(port, ATMEL_US_MR, mode);
493
494err_out:
495 /* Enable interrupts */
496 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->tx_done_mask);
497
498 return ret;
499}
500
1e6c9c28
AV		 501/*
502 * Return TIOCSER_TEMT when transmitter FIFO and Shift register is empty.
503 */
7192f92c 504static u_int atmel_tx_empty(struct uart_port *port)
1e6c9c28 505{
ea04f82a
RI		 506 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
507
508 if (atmel_port->tx_stopped)
509 return TIOCSER_TEMT;
4e7decda
CP		 510 return (atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXEMPTY) ?
511 TIOCSER_TEMT :
512 0;
1e6c9c28
AV		 513}
514
515/*
516 * Set state of the modem control output lines
517 */
7192f92c 518static void atmel_set_mctrl(struct uart_port *port, u_int mctrl)
1e6c9c28
AV		 519{
520 unsigned int control = 0;
4e7decda 521 unsigned int mode = atmel_uart_readl(port, ATMEL_US_MR);
1cf6e8fc 522 unsigned int rts_paused, rts_ready;
e8faff73 523 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1e6c9c28 524
1cf6e8fc
CP		 525 /* override mode to RS485 if needed, otherwise keep the current mode */
526 if (port->rs485.flags & SER_RS485_ENABLED) {
4e7decda
CP		 527 atmel_uart_writel(port, ATMEL_US_TTGR,
528 port->rs485.delay_rts_after_send);
1cf6e8fc
CP		 529 mode &= ~ATMEL_US_USMODE;
530 mode |= ATMEL_US_USMODE_RS485;
531 }
532
533 /* set the RTS line state according to the mode */
534 if ((mode & ATMEL_US_USMODE) == ATMEL_US_USMODE_HWHS) {
535 /* force RTS line to high level */
536 rts_paused = ATMEL_US_RTSEN;
537
538 /* give the control of the RTS line back to the hardware */
539 rts_ready = ATMEL_US_RTSDIS;
540 } else {
541 /* force RTS line to high level */
542 rts_paused = ATMEL_US_RTSDIS;
543
544 /* force RTS line to low level */
545 rts_ready = ATMEL_US_RTSEN;
546 }
547
1e6c9c28 548 if (mctrl & TIOCM_RTS)
1cf6e8fc 549 control |= rts_ready;
1e6c9c28 550 else
1cf6e8fc 551 control |= rts_paused;
1e6c9c28
AV		 552
553 if (mctrl & TIOCM_DTR)
7192f92c 554 control |= ATMEL_US_DTREN;
1e6c9c28 555 else
7192f92c 556 control |= ATMEL_US_DTRDIS;
1e6c9c28 557
4e7decda 558 atmel_uart_writel(port, ATMEL_US_CR, control);
afefc415 559
e0b0baad
RG		 560 mctrl_gpio_set(atmel_port->gpios, mctrl);
561
afefc415 562 /* Local loopback mode? */
1cf6e8fc 563 mode &= ~ATMEL_US_CHMODE;
afefc415 564 if (mctrl & TIOCM_LOOP)
7192f92c 565 mode |= ATMEL_US_CHMODE_LOC_LOOP;
afefc415 566 else
7192f92c 567 mode |= ATMEL_US_CHMODE_NORMAL;
e8faff73 568
4e7decda 569 atmel_uart_writel(port, ATMEL_US_MR, mode);
1e6c9c28
AV		 570}
571
572/*
573 * Get state of the modem control input lines
574 */
7192f92c 575static u_int atmel_get_mctrl(struct uart_port *port)
1e6c9c28 576{
e0b0baad
RG		 577 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
578 unsigned int ret = 0, status;
1e6c9c28 579
4e7decda 580 status = atmel_uart_readl(port, ATMEL_US_CSR);
1e6c9c28
AV		 581
582 /*
583 * The control signals are active low.
584 */
7192f92c 585 if (!(status & ATMEL_US_DCD))
1e6c9c28 586 ret |= TIOCM_CD;
7192f92c 587 if (!(status & ATMEL_US_CTS))
1e6c9c28 588 ret |= TIOCM_CTS;
7192f92c 589 if (!(status & ATMEL_US_DSR))
1e6c9c28 590 ret |= TIOCM_DSR;
7192f92c 591 if (!(status & ATMEL_US_RI))
1e6c9c28
AV		 592 ret |= TIOCM_RI;
593
e0b0baad 594 return mctrl_gpio_get(atmel_port->gpios, &ret);
1e6c9c28
AV		 595}
596
597/*
598 * Stop transmitting.
599 */
7192f92c 600static void atmel_stop_tx(struct uart_port *port)
1e6c9c28 601{
e8faff73
CS		 602 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
603
64e22ebe 604 if (atmel_use_pdc_tx(port)) {
a6670615 605 /* disable PDC transmit */
4e7decda 606 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS);
e8faff73 607 }
89d82324
RG		 608
609 /*
610 * Disable the transmitter.
611 * This is mandatory when DMA is used, otherwise the DMA buffer
612 * is fully transmitted.
613 */
614 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXDIS);
ea04f82a 615 atmel_port->tx_stopped = true;
89d82324 616
e8faff73 617 /* Disable interrupts */
4e7decda 618 atmel_uart_writel(port, ATMEL_US_IDR, atmel_port->tx_done_mask);
e8faff73 619
f3040983 620 if (atmel_uart_is_half_duplex(port))
e8faff73 621 atmel_start_rx(port);
f3040983 622
1e6c9c28
AV		 623}
624
625/*
626 * Start transmitting.
627 */
7192f92c 628static void atmel_start_tx(struct uart_port *port)
1e6c9c28 629{
e8faff73
CS		 630 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
631
0058f087
AB		 632 if (atmel_use_pdc_tx(port) && (atmel_uart_readl(port, ATMEL_PDC_PTSR)
633 & ATMEL_PDC_TXTEN))
634 /* The transmitter is already running. Yes, we
635 really need this.*/
636 return;
a6670615 637
0058f087 638 if (atmel_use_pdc_tx(port) || atmel_use_dma_tx(port))
f3040983 639 if (atmel_uart_is_half_duplex(port))
e8faff73
CS		 640 atmel_stop_rx(port);
641
0058f087 642 if (atmel_use_pdc_tx(port))
a6670615 643 /* re-enable PDC transmit */
4e7decda 644 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
0058f087 645
e8faff73 646 /* Enable interrupts */
4e7decda 647 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->tx_done_mask);
89d82324
RG		 648
649 /* re-enable the transmitter */
650 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN);
ea04f82a 651 atmel_port->tx_stopped = false;
e8faff73
CS		 652}
653
654/*
655 * start receiving - port is in process of being opened.
656 */
657static void atmel_start_rx(struct uart_port *port)
658{
4e7decda
CP		 659 /* reset status and receiver */
660 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
e8faff73 661
4e7decda 662 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RXEN);
57c36868 663
64e22ebe 664 if (atmel_use_pdc_rx(port)) {
e8faff73 665 /* enable PDC controller */
4e7decda
CP		 666 atmel_uart_writel(port, ATMEL_US_IER,
667 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT |
668 port->read_status_mask);
669 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN);
e8faff73 670 } else {
4e7decda 671 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_RXRDY);
e8faff73 672 }
1e6c9c28
AV		 673}
674
675/*
676 * Stop receiving - port is in process of being closed.
677 */
7192f92c 678static void atmel_stop_rx(struct uart_port *port)
1e6c9c28 679{
4e7decda 680 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RXDIS);
57c36868 681
64e22ebe 682 if (atmel_use_pdc_rx(port)) {
a6670615 683 /* disable PDC receive */
4e7decda
CP		 684 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS);
685 atmel_uart_writel(port, ATMEL_US_IDR,
686 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT |
687 port->read_status_mask);
e8faff73 688 } else {
4e7decda 689 atmel_uart_writel(port, ATMEL_US_IDR, ATMEL_US_RXRDY);
e8faff73 690 }
1e6c9c28
AV		 691}
692
693/*
694 * Enable modem status interrupts
695 */
7192f92c 696static void atmel_enable_ms(struct uart_port *port)
1e6c9c28 697{
ab5e4e41
RG		 698 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
699 uint32_t ier = 0;
700
701 /*
702 * Interrupt should not be enabled twice
703 */
704 if (atmel_port->ms_irq_enabled)
705 return;
706
707 atmel_port->ms_irq_enabled = true;
708
18dfef9c 709 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_CTS))
ab5e4e41
RG		 710 ier |= ATMEL_US_CTSIC;
711
18dfef9c 712 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DSR))
ab5e4e41
RG		 713 ier |= ATMEL_US_DSRIC;
714
18dfef9c 715 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_RI))
ab5e4e41
RG		 716 ier |= ATMEL_US_RIIC;
717
18dfef9c 718 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DCD))
ab5e4e41
RG		 719 ier |= ATMEL_US_DCDIC;
720
4e7decda 721 atmel_uart_writel(port, ATMEL_US_IER, ier);
18dfef9c
UKK		 722
723 mctrl_gpio_enable_ms(atmel_port->gpios);
1e6c9c28
AV		 724}
725
35b675b9
RG		 726/*
727 * Disable modem status interrupts
728 */
729static void atmel_disable_ms(struct uart_port *port)
730{
731 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
732 uint32_t idr = 0;
733
734 /*
735 * Interrupt should not be disabled twice
736 */
737 if (!atmel_port->ms_irq_enabled)
738 return;
739
740 atmel_port->ms_irq_enabled = false;
741
18dfef9c
UKK		 742 mctrl_gpio_disable_ms(atmel_port->gpios);
743
744 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_CTS))
35b675b9
RG		 745 idr |= ATMEL_US_CTSIC;
746
18dfef9c 747 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DSR))
35b675b9
RG		 748 idr |= ATMEL_US_DSRIC;
749
18dfef9c 750 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_RI))
35b675b9
RG		 751 idr |= ATMEL_US_RIIC;
752
18dfef9c 753 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DCD))
35b675b9
RG		 754 idr |= ATMEL_US_DCDIC;
755
4e7decda 756 atmel_uart_writel(port, ATMEL_US_IDR, idr);
35b675b9
RG		 757}
758
1e6c9c28
AV		 759/*
760 * Control the transmission of a break signal
761 */
7192f92c 762static void atmel_break_ctl(struct uart_port *port, int break_state)
1e6c9c28
AV		 763{
764 if (break_state != 0)
4e7decda
CP		 765 /* start break */
766 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTBRK);
1e6c9c28 767 else
4e7decda
CP		 768 /* stop break */
769 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STPBRK);
1e6c9c28
AV		 770}
771
1ecc26bd
RB		 772/*
773 * Stores the incoming character in the ring buffer
774 */
775static void
776atmel_buffer_rx_char(struct uart_port *port, unsigned int status,
777 unsigned int ch)
778{
c811ab8c 779 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1ecc26bd
RB		 780 struct circ_buf *ring = &atmel_port->rx_ring;
781 struct atmel_uart_char *c;
782
783 if (!CIRC_SPACE(ring->head, ring->tail, ATMEL_SERIAL_RINGSIZE))
784 /* Buffer overflow, ignore char */
785 return;
786
787 c = &((struct atmel_uart_char *)ring->buf)[ring->head];
788 c->status = status;
789 c->ch = ch;
790
791 /* Make sure the character is stored before we update head. */
792 smp_wmb();
793
794 ring->head = (ring->head + 1) & (ATMEL_SERIAL_RINGSIZE - 1);
795}
796
a6670615
CC		 797/*
798 * Deal with parity, framing and overrun errors.
799 */
800static void atmel_pdc_rxerr(struct uart_port *port, unsigned int status)
801{
802 /* clear error */
4e7decda 803 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
a6670615
CC		 804
805 if (status & ATMEL_US_RXBRK) {
806 /* ignore side-effect */
807 status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME);
808 port->icount.brk++;
809 }
810 if (status & ATMEL_US_PARE)
811 port->icount.parity++;
812 if (status & ATMEL_US_FRAME)
813 port->icount.frame++;
814 if (status & ATMEL_US_OVRE)
815 port->icount.overrun++;
816}
817
1e6c9c28
AV		 818/*
819 * Characters received (called from interrupt handler)
820 */
7d12e780 821static void atmel_rx_chars(struct uart_port *port)
1e6c9c28 822{
c811ab8c 823 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1ecc26bd 824 unsigned int status, ch;
1e6c9c28 825
4e7decda 826 status = atmel_uart_readl(port, ATMEL_US_CSR);
7192f92c 827 while (status & ATMEL_US_RXRDY) {
a6499435 828 ch = atmel_uart_read_char(port);
1e6c9c28 829
1e6c9c28
AV		 830 /*
831 * note that the error handling code is
832 * out of the main execution path
833 */
9e6077bd
HS		 834 if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME
835 | ATMEL_US_OVRE | ATMEL_US_RXBRK)
836 || atmel_port->break_active)) {
1ecc26bd 837
b843aa21 838 /* clear error */
4e7decda 839 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
1ecc26bd 840
9e6077bd
HS		 841 if (status & ATMEL_US_RXBRK
842 && !atmel_port->break_active) {
9e6077bd 843 atmel_port->break_active = 1;
4e7decda
CP		 844 atmel_uart_writel(port, ATMEL_US_IER,
845 ATMEL_US_RXBRK);
9e6077bd
HS		 846 } else {
847 /*
848 * This is either the end-of-break
849 * condition or we've received at
850 * least one character without RXBRK
851 * being set. In both cases, the next
852 * RXBRK will indicate start-of-break.
853 */
4e7decda
CP		 854 atmel_uart_writel(port, ATMEL_US_IDR,
855 ATMEL_US_RXBRK);
9e6077bd
HS		 856 status &= ~ATMEL_US_RXBRK;
857 atmel_port->break_active = 0;
afefc415 858 }
1e6c9c28
AV		 859 }
860
1ecc26bd 861 atmel_buffer_rx_char(port, status, ch);
4e7decda 862 status = atmel_uart_readl(port, ATMEL_US_CSR);
1e6c9c28
AV		 863 }
864
98f2082c 865 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_rx);
1e6c9c28
AV		 866}
867
868/*
1ecc26bd
RB		 869 * Transmit characters (called from tasklet with TXRDY interrupt
870 * disabled)
1e6c9c28 871 */
7192f92c 872static void atmel_tx_chars(struct uart_port *port)
1e6c9c28 873{
ebd2c8f6 874 struct circ_buf *xmit = &port->state->xmit;
e8faff73 875 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1e6c9c28 876
4e7decda
CP		 877 if (port->x_char &&
878 (atmel_uart_readl(port, ATMEL_US_CSR) & atmel_port->tx_done_mask)) {
a6499435 879 atmel_uart_write_char(port, port->x_char);
1e6c9c28
AV		 880 port->icount.tx++;
881 port->x_char = 0;
1e6c9c28 882 }
1ecc26bd 883 if (uart_circ_empty(xmit) || uart_tx_stopped(port))
1e6c9c28 884 return;
1e6c9c28 885
4e7decda
CP		 886 while (atmel_uart_readl(port, ATMEL_US_CSR) &
887 atmel_port->tx_done_mask) {
a6499435 888 atmel_uart_write_char(port, xmit->buf[xmit->tail]);
1e6c9c28
AV		 889 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
890 port->icount.tx++;
891 if (uart_circ_empty(xmit))
892 break;
893 }
894
895 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
896 uart_write_wakeup(port);
897
1ecc26bd 898 if (!uart_circ_empty(xmit))
e8faff73 899 /* Enable interrupts */
4e7decda
CP		 900 atmel_uart_writel(port, ATMEL_US_IER,
901 atmel_port->tx_done_mask);
1e6c9c28
AV		 902}
903
08f738be
ES		 904static void atmel_complete_tx_dma(void *arg)
905{
906 struct atmel_uart_port *atmel_port = arg;
907 struct uart_port *port = &atmel_port->uart;
908 struct circ_buf *xmit = &port->state->xmit;
909 struct dma_chan *chan = atmel_port->chan_tx;
910 unsigned long flags;
911
912 spin_lock_irqsave(&port->lock, flags);
913
914 if (chan)
915 dmaengine_terminate_all(chan);
5f258b3e 916 xmit->tail += atmel_port->tx_len;
08f738be
ES		 917 xmit->tail &= UART_XMIT_SIZE - 1;
918
5f258b3e 919 port->icount.tx += atmel_port->tx_len;
08f738be
ES		 920
921 spin_lock_irq(&atmel_port->lock_tx);
922 async_tx_ack(atmel_port->desc_tx);
923 atmel_port->cookie_tx = -EINVAL;
924 atmel_port->desc_tx = NULL;
925 spin_unlock_irq(&atmel_port->lock_tx);
926
927 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
928 uart_write_wakeup(port);
929
1842dc2e
CP		 930 /*
931 * xmit is a circular buffer so, if we have just send data from
932 * xmit->tail to the end of xmit->buf, now we have to transmit the
933 * remaining data from the beginning of xmit->buf to xmit->head.
934 */
08f738be 935 if (!uart_circ_empty(xmit))
98f2082c 936 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_tx);
f3040983 937 else if (atmel_uart_is_half_duplex(port)) {
69646d7a
RS		 938 /*
939 * DMA done, re-enable TXEMPTY and signal that we can stop
940 * TX and start RX for RS485
941 */
942 atmel_port->hd_start_rx = true;
943 atmel_uart_writel(port, ATMEL_US_IER,
944 atmel_port->tx_done_mask);
b389f173 945 }
08f738be
ES		 946
947 spin_unlock_irqrestore(&port->lock, flags);
948}
949
950static void atmel_release_tx_dma(struct uart_port *port)
951{
952 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
953 struct dma_chan *chan = atmel_port->chan_tx;
954
955 if (chan) {
956 dmaengine_terminate_all(chan);
957 dma_release_channel(chan);
958 dma_unmap_sg(port->dev, &atmel_port->sg_tx, 1,
48479148 959 DMA_TO_DEVICE);
08f738be
ES		 960 }
961
962 atmel_port->desc_tx = NULL;
963 atmel_port->chan_tx = NULL;
964 atmel_port->cookie_tx = -EINVAL;
965}
966
967/*
968 * Called from tasklet with TXRDY interrupt is disabled.
969 */
970static void atmel_tx_dma(struct uart_port *port)
971{
972 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
973 struct circ_buf *xmit = &port->state->xmit;
974 struct dma_chan *chan = atmel_port->chan_tx;
975 struct dma_async_tx_descriptor *desc;
5f258b3e
CP		 976 struct scatterlist sgl[2], *sg, *sg_tx = &atmel_port->sg_tx;
977 unsigned int tx_len, part1_len, part2_len, sg_len;
978 dma_addr_t phys_addr;
08f738be
ES		 979
980 /* Make sure we have an idle channel */
981 if (atmel_port->desc_tx != NULL)
982 return;
983
984 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) {
985 /*
986 * DMA is idle now.
987 * Port xmit buffer is already mapped,
988 * and it is one page... Just adjust
989 * offsets and lengths. Since it is a circular buffer,
990 * we have to transmit till the end, and then the rest.
991 * Take the port lock to get a
992 * consistent xmit buffer state.
993 */
5f258b3e
CP		 994 tx_len = CIRC_CNT_TO_END(xmit->head,
995 xmit->tail,
996 UART_XMIT_SIZE);
997
998 if (atmel_port->fifo_size) {
999 /* multi data mode */
1000 part1_len = (tx_len & ~0x3); /* DWORD access */
1001 part2_len = (tx_len & 0x3); /* BYTE access */
1002 } else {
1003 /* single data (legacy) mode */
1004 part1_len = 0;
1005 part2_len = tx_len; /* BYTE access only */
1006 }
1007
1008 sg_init_table(sgl, 2);
1009 sg_len = 0;
1010 phys_addr = sg_dma_address(sg_tx) + xmit->tail;
1011 if (part1_len) {
1012 sg = &sgl[sg_len++];
1013 sg_dma_address(sg) = phys_addr;
1014 sg_dma_len(sg) = part1_len;
1015
1016 phys_addr += part1_len;
1017 }
1018
1019 if (part2_len) {
1020 sg = &sgl[sg_len++];
1021 sg_dma_address(sg) = phys_addr;
1022 sg_dma_len(sg) = part2_len;
1023 }
1024
1025 /*
1026 * save tx_len so atmel_complete_tx_dma() will increase
1027 * xmit->tail correctly
1028 */
1029 atmel_port->tx_len = tx_len;
08f738be
ES		 1030
1031 desc = dmaengine_prep_slave_sg(chan,
5f258b3e
CP		 1032 sgl,
1033 sg_len,
1842dc2e
CP		 1034 DMA_MEM_TO_DEV,
1035 DMA_PREP_INTERRUPT |
1036 DMA_CTRL_ACK);
08f738be
ES		 1037 if (!desc) {
1038 dev_err(port->dev, "Failed to send via dma!\n");
1039 return;
1040 }
1041
5f258b3e 1042 dma_sync_sg_for_device(port->dev, sg_tx, 1, DMA_TO_DEVICE);
08f738be
ES		 1043
1044 atmel_port->desc_tx = desc;
1045 desc->callback = atmel_complete_tx_dma;
1046 desc->callback_param = atmel_port;
1047 atmel_port->cookie_tx = dmaengine_submit(desc);
08f738be
ES		 1048 }
1049
1050 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1051 uart_write_wakeup(port);
1052}
1053
1054static int atmel_prepare_tx_dma(struct uart_port *port)
1055{
1056 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
c24d2531 1057 struct device *mfd_dev = port->dev->parent;
08f738be
ES		 1058 dma_cap_mask_t mask;
1059 struct dma_slave_config config;
1060 int ret, nent;
1061
1062 dma_cap_zero(mask);
1063 dma_cap_set(DMA_SLAVE, mask);
1064
c24d2531 1065 atmel_port->chan_tx = dma_request_slave_channel(mfd_dev, "tx");
08f738be
ES		 1066 if (atmel_port->chan_tx == NULL)
1067 goto chan_err;
1068 dev_info(port->dev, "using %s for tx DMA transfers\n",
1069 dma_chan_name(atmel_port->chan_tx));
1070
1071 spin_lock_init(&atmel_port->lock_tx);
1072 sg_init_table(&atmel_port->sg_tx, 1);
1073 /* UART circular tx buffer is an aligned page. */
2c277054 1074 BUG_ON(!PAGE_ALIGNED(port->state->xmit.buf));
08f738be
ES		 1075 sg_set_page(&atmel_port->sg_tx,
1076 virt_to_page(port->state->xmit.buf),
1077 UART_XMIT_SIZE,
2b5cf14b 1078 offset_in_page(port->state->xmit.buf));
08f738be
ES		 1079 nent = dma_map_sg(port->dev,
1080 &atmel_port->sg_tx,
1081 1,
48479148 1082 DMA_TO_DEVICE);
08f738be
ES		 1083
1084 if (!nent) {
1085 dev_dbg(port->dev, "need to release resource of dma\n");
1086 goto chan_err;
1087 } else {
c8d1f022 1088 dev_dbg(port->dev, "%s: mapped %d@%p to %pad\n", __func__,
08f738be
ES		 1089 sg_dma_len(&atmel_port->sg_tx),
1090 port->state->xmit.buf,
c8d1f022 1091 &sg_dma_address(&atmel_port->sg_tx));
08f738be
ES		 1092 }
1093
1094 /* Configure the slave DMA */
1095 memset(&config, 0, sizeof(config));
1096 config.direction = DMA_MEM_TO_DEV;
5f258b3e
CP		 1097 config.dst_addr_width = (atmel_port->fifo_size) ?
1098 DMA_SLAVE_BUSWIDTH_4_BYTES :
1099 DMA_SLAVE_BUSWIDTH_1_BYTE;
08f738be 1100 config.dst_addr = port->mapbase + ATMEL_US_THR;
a8d4e016 1101 config.dst_maxburst = 1;
08f738be 1102
5483c10e
MR		 1103 ret = dmaengine_slave_config(atmel_port->chan_tx,
1104 &config);
08f738be
ES		 1105 if (ret) {
1106 dev_err(port->dev, "DMA tx slave configuration failed\n");
1107 goto chan_err;
1108 }
1109
1110 return 0;
1111
1112chan_err:
1113 dev_err(port->dev, "TX channel not available, switch to pio\n");
1114 atmel_port->use_dma_tx = 0;
1115 if (atmel_port->chan_tx)
1116 atmel_release_tx_dma(port);
1117 return -EINVAL;
1118}
1119
34df42f5
ES		 1120static void atmel_complete_rx_dma(void *arg)
1121{
1122 struct uart_port *port = arg;
1123 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1124
98f2082c 1125 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_rx);
34df42f5
ES		 1126}
1127
1128static void atmel_release_rx_dma(struct uart_port *port)
1129{
1130 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1131 struct dma_chan *chan = atmel_port->chan_rx;
1132
1133 if (chan) {
1134 dmaengine_terminate_all(chan);
1135 dma_release_channel(chan);
1136 dma_unmap_sg(port->dev, &atmel_port->sg_rx, 1,
48479148 1137 DMA_FROM_DEVICE);
34df42f5
ES		 1138 }
1139
1140 atmel_port->desc_rx = NULL;
1141 atmel_port->chan_rx = NULL;
1142 atmel_port->cookie_rx = -EINVAL;
1143}
1144
1145static void atmel_rx_from_dma(struct uart_port *port)
1146{
1147 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
66f37aaf 1148 struct tty_port *tport = &port->state->port;
34df42f5
ES		 1149 struct circ_buf *ring = &atmel_port->rx_ring;
1150 struct dma_chan *chan = atmel_port->chan_rx;
1151 struct dma_tx_state state;
1152 enum dma_status dmastat;
66f37aaf 1153 size_t count;
34df42f5
ES		 1154
1155
1156 /* Reset the UART timeout early so that we don't miss one */
4e7decda 1157 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
34df42f5
ES		 1158 dmastat = dmaengine_tx_status(chan,
1159 atmel_port->cookie_rx,
1160 &state);
1161 /* Restart a new tasklet if DMA status is error */
1162 if (dmastat == DMA_ERROR) {
1163 dev_dbg(port->dev, "Get residue error, restart tasklet\n");
4e7decda 1164 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_TIMEOUT);
98f2082c 1165 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_rx);
34df42f5
ES		 1166 return;
1167 }
34df42f5 1168
66f37aaf
CP		 1169 /* CPU claims ownership of RX DMA buffer */
1170 dma_sync_sg_for_cpu(port->dev,
1171 &atmel_port->sg_rx,
1172 1,
485819b5 1173 DMA_FROM_DEVICE);
66f37aaf
CP		 1174
1175 /*
1176 * ring->head points to the end of data already written by the DMA.
1177 * ring->tail points to the beginning of data to be read by the
1178 * framework.
1179 * The current transfer size should not be larger than the dma buffer
1180 * length.
1181 */
1182 ring->head = sg_dma_len(&atmel_port->sg_rx) - state.residue;
1183 BUG_ON(ring->head > sg_dma_len(&atmel_port->sg_rx));
34df42f5 1184 /*
66f37aaf
CP		 1185 * At this point ring->head may point to the first byte right after the
1186 * last byte of the dma buffer:
1187 * 0 <= ring->head <= sg_dma_len(&atmel_port->sg_rx)
1188 *
1189 * However ring->tail must always points inside the dma buffer:
1190 * 0 <= ring->tail <= sg_dma_len(&atmel_port->sg_rx) - 1
1191 *
1192 * Since we use a ring buffer, we have to handle the case
1193 * where head is lower than tail. In such a case, we first read from
1194 * tail to the end of the buffer then reset tail.
34df42f5 1195 */
66f37aaf
CP		 1196 if (ring->head < ring->tail) {
1197 count = sg_dma_len(&atmel_port->sg_rx) - ring->tail;
34df42f5 1198
66f37aaf
CP		 1199 tty_insert_flip_string(tport, ring->buf + ring->tail, count);
1200 ring->tail = 0;
1201 port->icount.rx += count;
1202 }
34df42f5 1203
66f37aaf
CP		 1204 /* Finally we read data from tail to head */
1205 if (ring->tail < ring->head) {
1206 count = ring->head - ring->tail;
34df42f5 1207
66f37aaf
CP		 1208 tty_insert_flip_string(tport, ring->buf + ring->tail, count);
1209 /* Wrap ring->head if needed */
1210 if (ring->head >= sg_dma_len(&atmel_port->sg_rx))
1211 ring->head = 0;
1212 ring->tail = ring->head;
34df42f5
ES		 1213 port->icount.rx += count;
1214 }
1215
66f37aaf
CP		 1216 /* USART retreives ownership of RX DMA buffer */
1217 dma_sync_sg_for_device(port->dev,
1218 &atmel_port->sg_rx,
1219 1,
485819b5 1220 DMA_FROM_DEVICE);
66f37aaf
CP		 1221
1222 /*
1223 * Drop the lock here since it might end up calling
1224 * uart_start(), which takes the lock.
1225 */
1226 spin_unlock(&port->lock);
1227 tty_flip_buffer_push(tport);
1228 spin_lock(&port->lock);
1229
4e7decda 1230 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_TIMEOUT);
34df42f5
ES		 1231}
1232
1233static int atmel_prepare_rx_dma(struct uart_port *port)
1234{
1235 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
c24d2531 1236 struct device *mfd_dev = port->dev->parent;
34df42f5
ES		 1237 struct dma_async_tx_descriptor *desc;
1238 dma_cap_mask_t mask;
1239 struct dma_slave_config config;
1240 struct circ_buf *ring;
1241 int ret, nent;
1242
1243 ring = &atmel_port->rx_ring;
1244
1245 dma_cap_zero(mask);
1246 dma_cap_set(DMA_CYCLIC, mask);
1247
c24d2531 1248 atmel_port->chan_rx = dma_request_slave_channel(mfd_dev, "rx");
34df42f5
ES		 1249 if (atmel_port->chan_rx == NULL)
1250 goto chan_err;
1251 dev_info(port->dev, "using %s for rx DMA transfers\n",
1252 dma_chan_name(atmel_port->chan_rx));
1253
1254 spin_lock_init(&atmel_port->lock_rx);
1255 sg_init_table(&atmel_port->sg_rx, 1);
1256 /* UART circular rx buffer is an aligned page. */
2c277054 1257 BUG_ON(!PAGE_ALIGNED(ring->buf));
34df42f5 1258 sg_set_page(&atmel_port->sg_rx,
1842dc2e 1259 virt_to_page(ring->buf),
a510880f 1260 sizeof(struct atmel_uart_char) * ATMEL_SERIAL_RINGSIZE,
2b5cf14b 1261 offset_in_page(ring->buf));
1842dc2e
CP		 1262 nent = dma_map_sg(port->dev,
1263 &atmel_port->sg_rx,
1264 1,
1265 DMA_FROM_DEVICE);
34df42f5
ES		 1266
1267 if (!nent) {
1268 dev_dbg(port->dev, "need to release resource of dma\n");
1269 goto chan_err;
1270 } else {
c8d1f022 1271 dev_dbg(port->dev, "%s: mapped %d@%p to %pad\n", __func__,
34df42f5
ES		 1272 sg_dma_len(&atmel_port->sg_rx),
1273 ring->buf,
c8d1f022 1274 &sg_dma_address(&atmel_port->sg_rx));
34df42f5
ES		 1275 }
1276
1277 /* Configure the slave DMA */
1278 memset(&config, 0, sizeof(config));
1279 config.direction = DMA_DEV_TO_MEM;
1280 config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1281 config.src_addr = port->mapbase + ATMEL_US_RHR;
a8d4e016 1282 config.src_maxburst = 1;
34df42f5 1283
5483c10e
MR		 1284 ret = dmaengine_slave_config(atmel_port->chan_rx,
1285 &config);
34df42f5
ES		 1286 if (ret) {
1287 dev_err(port->dev, "DMA rx slave configuration failed\n");
1288 goto chan_err;
1289 }
1290 /*
1291 * Prepare a cyclic dma transfer, assign 2 descriptors,
1292 * each one is half ring buffer size
1293 */
1294 desc = dmaengine_prep_dma_cyclic(atmel_port->chan_rx,
1842dc2e
CP		 1295 sg_dma_address(&atmel_port->sg_rx),
1296 sg_dma_len(&atmel_port->sg_rx),
1297 sg_dma_len(&atmel_port->sg_rx)/2,
1298 DMA_DEV_TO_MEM,
1299 DMA_PREP_INTERRUPT);
c85be041
KL		 1300 if (!desc) {
1301 dev_err(port->dev, "Preparing DMA cyclic failed\n");
1302 goto chan_err;
1303 }
34df42f5
ES		 1304 desc->callback = atmel_complete_rx_dma;
1305 desc->callback_param = port;
1306 atmel_port->desc_rx = desc;
1307 atmel_port->cookie_rx = dmaengine_submit(desc);
1308
1309 return 0;
1310
1311chan_err:
1312 dev_err(port->dev, "RX channel not available, switch to pio\n");
1313 atmel_port->use_dma_rx = 0;
1314 if (atmel_port->chan_rx)
1315 atmel_release_rx_dma(port);
1316 return -EINVAL;
1317}
1318
026cb432 1319static void atmel_uart_timer_callback(struct timer_list *t)
2e68c22f 1320{
026cb432
KC		 1321 struct atmel_uart_port *atmel_port = from_timer(atmel_port, t,
1322 uart_timer);
1323 struct uart_port *port = &atmel_port->uart;
2e68c22f 1324
98f2082c
NF		 1325 if (!atomic_read(&atmel_port->tasklet_shutdown)) {
1326 tasklet_schedule(&atmel_port->tasklet_rx);
1327 mod_timer(&atmel_port->uart_timer,
1328 jiffies + uart_poll_timeout(port));
1329 }
2e68c22f
ES		 1330}
1331
b843aa21
RB		 1332/*
1333 * receive interrupt handler.
1334 */
1335static void
1336atmel_handle_receive(struct uart_port *port, unsigned int pending)
1337{
c811ab8c 1338 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
b843aa21 1339
64e22ebe 1340 if (atmel_use_pdc_rx(port)) {
a6670615
CC		 1341 /*
1342 * PDC receive. Just schedule the tasklet and let it
1343 * figure out the details.
1344 *
1345 * TODO: We're not handling error flags correctly at
1346 * the moment.
1347 */
1348 if (pending & (ATMEL_US_ENDRX | ATMEL_US_TIMEOUT)) {
4e7decda
CP		 1349 atmel_uart_writel(port, ATMEL_US_IDR,
1350 (ATMEL_US_ENDRX | ATMEL_US_TIMEOUT));
98f2082c
NF		 1351 atmel_tasklet_schedule(atmel_port,
1352 &atmel_port->tasklet_rx);
a6670615
CC		 1353 }
1354
1355 if (pending & (ATMEL_US_RXBRK | ATMEL_US_OVRE |
1356 ATMEL_US_FRAME | ATMEL_US_PARE))
1357 atmel_pdc_rxerr(port, pending);
1358 }
1359
34df42f5
ES		 1360 if (atmel_use_dma_rx(port)) {
1361 if (pending & ATMEL_US_TIMEOUT) {
4e7decda
CP		 1362 atmel_uart_writel(port, ATMEL_US_IDR,
1363 ATMEL_US_TIMEOUT);
98f2082c
NF		 1364 atmel_tasklet_schedule(atmel_port,
1365 &atmel_port->tasklet_rx);
34df42f5
ES		 1366 }
1367 }
1368
b843aa21
RB		 1369 /* Interrupt receive */
1370 if (pending & ATMEL_US_RXRDY)
1371 atmel_rx_chars(port);
1372 else if (pending & ATMEL_US_RXBRK) {
1373 /*
1374 * End of break detected. If it came along with a
1375 * character, atmel_rx_chars will handle it.
1376 */
4e7decda
CP		 1377 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
1378 atmel_uart_writel(port, ATMEL_US_IDR, ATMEL_US_RXBRK);
b843aa21
RB		 1379 atmel_port->break_active = 0;
1380 }
1381}
1382
1383/*
1ecc26bd 1384 * transmit interrupt handler. (Transmit is IRQF_NODELAY safe)
b843aa21
RB		 1385 */
1386static void
1387atmel_handle_transmit(struct uart_port *port, unsigned int pending)
1388{
c811ab8c 1389 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1ecc26bd 1390
e8faff73 1391 if (pending & atmel_port->tx_done_mask) {
4e7decda
CP		 1392 atmel_uart_writel(port, ATMEL_US_IDR,
1393 atmel_port->tx_done_mask);
69646d7a
RS		 1394
1395 /* Start RX if flag was set and FIFO is empty */
1396 if (atmel_port->hd_start_rx) {
1397 if (!(atmel_uart_readl(port, ATMEL_US_CSR)
1398 & ATMEL_US_TXEMPTY))
1399 dev_warn(port->dev, "Should start RX, but TX fifo is not empty\n");
1400
1401 atmel_port->hd_start_rx = false;
1402 atmel_start_rx(port);
69646d7a
RS		 1403 }
1404
98f2082c 1405 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_tx);
1ecc26bd 1406 }
b843aa21
RB		 1407}
1408
1409/*
1410 * status flags interrupt handler.
1411 */
1412static void
1413atmel_handle_status(struct uart_port *port, unsigned int pending,
1414 unsigned int status)
1415{
c811ab8c 1416 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
9205218e 1417 unsigned int status_change;
1ecc26bd 1418
b843aa21 1419 if (pending & (ATMEL_US_RIIC | ATMEL_US_DSRIC | ATMEL_US_DCDIC
1ecc26bd 1420 | ATMEL_US_CTSIC)) {
9205218e 1421 status_change = status ^ atmel_port->irq_status_prev;
d033e82d 1422 atmel_port->irq_status_prev = status;
9205218e
NF		 1423
1424 if (status_change & (ATMEL_US_RI | ATMEL_US_DSR
1425 | ATMEL_US_DCD | ATMEL_US_CTS)) {
1426 /* TODO: All reads to CSR will clear these interrupts! */
1427 if (status_change & ATMEL_US_RI)
1428 port->icount.rng++;
1429 if (status_change & ATMEL_US_DSR)
1430 port->icount.dsr++;
1431 if (status_change & ATMEL_US_DCD)
1432 uart_handle_dcd_change(port, !(status & ATMEL_US_DCD));
1433 if (status_change & ATMEL_US_CTS)
1434 uart_handle_cts_change(port, !(status & ATMEL_US_CTS));
1435
1436 wake_up_interruptible(&port->state->port.delta_msr_wait);
1437 }
1ecc26bd 1438 }
377fedd1
NF		 1439
1440 if (pending & (ATMEL_US_NACK | ATMEL_US_ITERATION))
1441 dev_dbg(port->dev, "ISO7816 ERROR (0x%08x)\n", pending);
b843aa21
RB		 1442}
1443
1e6c9c28
AV		 1444/*
1445 * Interrupt handler
1446 */
7d12e780 1447static irqreturn_t atmel_interrupt(int irq, void *dev_id)
1e6c9c28
AV		 1448{
1449 struct uart_port *port = dev_id;
ab5e4e41 1450 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2c7af5ba 1451 unsigned int status, pending, mask, pass_counter = 0;
1e6c9c28 1452
2c7af5ba
BB		 1453 spin_lock(&atmel_port->lock_suspended);
1454
a6670615 1455 do {
e0b0baad 1456 status = atmel_get_lines_status(port);
4e7decda 1457 mask = atmel_uart_readl(port, ATMEL_US_IMR);
2c7af5ba 1458 pending = status & mask;
a6670615
CC		 1459 if (!pending)
1460 break;
1461
2c7af5ba
BB		 1462 if (atmel_port->suspended) {
1463 atmel_port->pending |= pending;
1464 atmel_port->pending_status = status;
4e7decda 1465 atmel_uart_writel(port, ATMEL_US_IDR, mask);
2c7af5ba
BB		 1466 pm_system_wakeup();
1467 break;
1468 }
1469
b843aa21
RB		 1470 atmel_handle_receive(port, pending);
1471 atmel_handle_status(port, pending, status);
1472 atmel_handle_transmit(port, pending);
a6670615 1473 } while (pass_counter++ < ATMEL_ISR_PASS_LIMIT);
afefc415 1474
2c7af5ba
BB		 1475 spin_unlock(&atmel_port->lock_suspended);
1476
0400b697 1477 return pass_counter ? IRQ_HANDLED : IRQ_NONE;
a6670615 1478}
1e6c9c28 1479
a930e528
ES		 1480static void atmel_release_tx_pdc(struct uart_port *port)
1481{
1482 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1483 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1484
1485 dma_unmap_single(port->dev,
1486 pdc->dma_addr,
1487 pdc->dma_size,
1488 DMA_TO_DEVICE);
1489}
1490
a6670615
CC		 1491/*
1492 * Called from tasklet with ENDTX and TXBUFE interrupts disabled.
1493 */
64e22ebe 1494static void atmel_tx_pdc(struct uart_port *port)
a6670615 1495{
c811ab8c 1496 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
ebd2c8f6 1497 struct circ_buf *xmit = &port->state->xmit;
a6670615
CC		 1498 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1499 int count;
1500
ba0657ff 1501 /* nothing left to transmit? */
4e7decda 1502 if (atmel_uart_readl(port, ATMEL_PDC_TCR))
ba0657ff
MT		 1503 return;
1504
a6670615
CC		 1505 xmit->tail += pdc->ofs;
1506 xmit->tail &= UART_XMIT_SIZE - 1;
1507
1508 port->icount.tx += pdc->ofs;
1509 pdc->ofs = 0;
1510
ba0657ff 1511 /* more to transmit - setup next transfer */
a6670615 1512
ba0657ff 1513 /* disable PDC transmit */
4e7decda 1514 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS);
ba0657ff 1515
1f14081d 1516 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) {
a6670615
CC		 1517 dma_sync_single_for_device(port->dev,
1518 pdc->dma_addr,
1519 pdc->dma_size,
1520 DMA_TO_DEVICE);
1521
1522 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
1523 pdc->ofs = count;
1524
4e7decda
CP		 1525 atmel_uart_writel(port, ATMEL_PDC_TPR,
1526 pdc->dma_addr + xmit->tail);
1527 atmel_uart_writel(port, ATMEL_PDC_TCR, count);
e8faff73 1528 /* re-enable PDC transmit */
4e7decda 1529 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
e8faff73 1530 /* Enable interrupts */
4e7decda
CP		 1531 atmel_uart_writel(port, ATMEL_US_IER,
1532 atmel_port->tx_done_mask);
e8faff73 1533 } else {
f3040983 1534 if (atmel_uart_is_half_duplex(port)) {
e8faff73
CS		 1535 /* DMA done, stop TX, start RX for RS485 */
1536 atmel_start_rx(port);
1537 }
1e6c9c28 1538 }
a6670615
CC		 1539
1540 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1541 uart_write_wakeup(port);
1e6c9c28
AV		 1542}
1543
a930e528
ES		 1544static int atmel_prepare_tx_pdc(struct uart_port *port)
1545{
1546 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1547 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1548 struct circ_buf *xmit = &port->state->xmit;
1549
1550 pdc->buf = xmit->buf;
1551 pdc->dma_addr = dma_map_single(port->dev,
1552 pdc->buf,
1553 UART_XMIT_SIZE,
1554 DMA_TO_DEVICE);
1555 pdc->dma_size = UART_XMIT_SIZE;
1556 pdc->ofs = 0;
1557
1558 return 0;
1559}
1560
1ecc26bd
RB		 1561static void atmel_rx_from_ring(struct uart_port *port)
1562{
c811ab8c 1563 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1ecc26bd
RB		 1564 struct circ_buf *ring = &atmel_port->rx_ring;
1565 unsigned int flg;
1566 unsigned int status;
1567
1568 while (ring->head != ring->tail) {
1569 struct atmel_uart_char c;
1570
1571 /* Make sure c is loaded after head. */
1572 smp_rmb();
1573
1574 c = ((struct atmel_uart_char *)ring->buf)[ring->tail];
1575
1576 ring->tail = (ring->tail + 1) & (ATMEL_SERIAL_RINGSIZE - 1);
1577
1578 port->icount.rx++;
1579 status = c.status;
1580 flg = TTY_NORMAL;
1581
1582 /*
1583 * note that the error handling code is
1584 * out of the main execution path
1585 */
1586 if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME
1587 | ATMEL_US_OVRE | ATMEL_US_RXBRK))) {
1588 if (status & ATMEL_US_RXBRK) {
1589 /* ignore side-effect */
1590 status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME);
1591
1592 port->icount.brk++;
1593 if (uart_handle_break(port))
1594 continue;
1595 }
1596 if (status & ATMEL_US_PARE)
1597 port->icount.parity++;
1598 if (status & ATMEL_US_FRAME)
1599 port->icount.frame++;
1600 if (status & ATMEL_US_OVRE)
1601 port->icount.overrun++;
1602
1603 status &= port->read_status_mask;
1604
1605 if (status & ATMEL_US_RXBRK)
1606 flg = TTY_BREAK;
1607 else if (status & ATMEL_US_PARE)
1608 flg = TTY_PARITY;
1609 else if (status & ATMEL_US_FRAME)
1610 flg = TTY_FRAME;
1611 }
1612
1613
1614 if (uart_handle_sysrq_char(port, c.ch))
1615 continue;
1616
1617 uart_insert_char(port, status, ATMEL_US_OVRE, c.ch, flg);
1618 }
1619
1620 /*
1621 * Drop the lock here since it might end up calling
1622 * uart_start(), which takes the lock.
1623 */
1624 spin_unlock(&port->lock);
2e124b4a 1625 tty_flip_buffer_push(&port->state->port);
1ecc26bd
RB		 1626 spin_lock(&port->lock);
1627}
1628
a930e528
ES		 1629static void atmel_release_rx_pdc(struct uart_port *port)
1630{
1631 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1632 int i;
1633
1634 for (i = 0; i < 2; i++) {
1635 struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i];
1636
1637 dma_unmap_single(port->dev,
1638 pdc->dma_addr,
1639 pdc->dma_size,
1640 DMA_FROM_DEVICE);
1641 kfree(pdc->buf);
1642 }
1643}
1644
64e22ebe 1645static void atmel_rx_from_pdc(struct uart_port *port)
a6670615 1646{
c811ab8c 1647 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
05c7cd39 1648 struct tty_port *tport = &port->state->port;
a6670615
CC		 1649 struct atmel_dma_buffer *pdc;
1650 int rx_idx = atmel_port->pdc_rx_idx;
1651 unsigned int head;
1652 unsigned int tail;
1653 unsigned int count;
1654
1655 do {
1656 /* Reset the UART timeout early so that we don't miss one */
4e7decda 1657 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
a6670615
CC		 1658
1659 pdc = &atmel_port->pdc_rx[rx_idx];
4e7decda 1660 head = atmel_uart_readl(port, ATMEL_PDC_RPR) - pdc->dma_addr;
a6670615
CC		 1661 tail = pdc->ofs;
1662
1663 /* If the PDC has switched buffers, RPR won't contain
1664 * any address within the current buffer. Since head
1665 * is unsigned, we just need a one-way comparison to
1666 * find out.
1667 *
1668 * In this case, we just need to consume the entire
1669 * buffer and resubmit it for DMA. This will clear the
1670 * ENDRX bit as well, so that we can safely re-enable
1671 * all interrupts below.
1672 */
1673 head = min(head, pdc->dma_size);
1674
1675 if (likely(head != tail)) {
1676 dma_sync_single_for_cpu(port->dev, pdc->dma_addr,
1677 pdc->dma_size, DMA_FROM_DEVICE);
1678
1679 /*
1680 * head will only wrap around when we recycle
1681 * the DMA buffer, and when that happens, we
1682 * explicitly set tail to 0. So head will
1683 * always be greater than tail.
1684 */
1685 count = head - tail;
1686
05c7cd39
JS		 1687 tty_insert_flip_string(tport, pdc->buf + pdc->ofs,
1688 count);
a6670615
CC		 1689
1690 dma_sync_single_for_device(port->dev, pdc->dma_addr,
1691 pdc->dma_size, DMA_FROM_DEVICE);
1692
1693 port->icount.rx += count;
1694 pdc->ofs = head;
1695 }
1696
1697 /*
1698 * If the current buffer is full, we need to check if
1699 * the next one contains any additional data.
1700 */
1701 if (head >= pdc->dma_size) {
1702 pdc->ofs = 0;
4e7decda
CP		 1703 atmel_uart_writel(port, ATMEL_PDC_RNPR, pdc->dma_addr);
1704 atmel_uart_writel(port, ATMEL_PDC_RNCR, pdc->dma_size);
a6670615
CC		 1705
1706 rx_idx = !rx_idx;
1707 atmel_port->pdc_rx_idx = rx_idx;
1708 }
1709 } while (head >= pdc->dma_size);
1710
1711 /*
1712 * Drop the lock here since it might end up calling
1713 * uart_start(), which takes the lock.
1714 */
1715 spin_unlock(&port->lock);
2e124b4a 1716 tty_flip_buffer_push(tport);
a6670615
CC		 1717 spin_lock(&port->lock);
1718
4e7decda
CP		 1719 atmel_uart_writel(port, ATMEL_US_IER,
1720 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT);
a6670615
CC		 1721}
1722
a930e528
ES		 1723static int atmel_prepare_rx_pdc(struct uart_port *port)
1724{
1725 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1726 int i;
1727
1728 for (i = 0; i < 2; i++) {
1729 struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i];
1730
1731 pdc->buf = kmalloc(PDC_BUFFER_SIZE, GFP_KERNEL);
1732 if (pdc->buf == NULL) {
1733 if (i != 0) {
1734 dma_unmap_single(port->dev,
1735 atmel_port->pdc_rx[0].dma_addr,
1736 PDC_BUFFER_SIZE,
1737 DMA_FROM_DEVICE);
1738 kfree(atmel_port->pdc_rx[0].buf);
1739 }
1740 atmel_port->use_pdc_rx = 0;
1741 return -ENOMEM;
1742 }
1743 pdc->dma_addr = dma_map_single(port->dev,
1744 pdc->buf,
1745 PDC_BUFFER_SIZE,
1746 DMA_FROM_DEVICE);
1747 pdc->dma_size = PDC_BUFFER_SIZE;
1748 pdc->ofs = 0;
1749 }
1750
1751 atmel_port->pdc_rx_idx = 0;
1752
4e7decda
CP		 1753 atmel_uart_writel(port, ATMEL_PDC_RPR, atmel_port->pdc_rx[0].dma_addr);
1754 atmel_uart_writel(port, ATMEL_PDC_RCR, PDC_BUFFER_SIZE);
a930e528 1755
4e7decda
CP		 1756 atmel_uart_writel(port, ATMEL_PDC_RNPR,
1757 atmel_port->pdc_rx[1].dma_addr);
1758 atmel_uart_writel(port, ATMEL_PDC_RNCR, PDC_BUFFER_SIZE);
a930e528
ES		 1759
1760 return 0;
1761}
1762
1ecc26bd
RB		 1763/*
1764 * tasklet handling tty stuff outside the interrupt handler.
1765 */
00e8e658 1766static void atmel_tasklet_rx_func(unsigned long data)
1ecc26bd
RB		 1767{
1768 struct uart_port *port = (struct uart_port *)data;
c811ab8c 1769 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1ecc26bd
RB		 1770
1771 /* The interrupt handler does not take the lock */
1772 spin_lock(&port->lock);
a930e528 1773 atmel_port->schedule_rx(port);
00e8e658
NF		 1774 spin_unlock(&port->lock);
1775}
1ecc26bd 1776
00e8e658
NF		 1777static void atmel_tasklet_tx_func(unsigned long data)
1778{
1779 struct uart_port *port = (struct uart_port *)data;
1780 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1781
1782 /* The interrupt handler does not take the lock */
1783 spin_lock(&port->lock);
1784 atmel_port->schedule_tx(port);
1ecc26bd
RB		 1785 spin_unlock(&port->lock);
1786}
1787
4a1e8888 1788static void atmel_init_property(struct atmel_uart_port *atmel_port,
33d64c4f
ES		 1789 struct platform_device *pdev)
1790{
1791 struct device_node *np = pdev->dev.of_node;
92c8f7c0
AB		 1792
1793 /* DMA/PDC usage specification */
1794 if (of_property_read_bool(np, "atmel,use-dma-rx")) {
1795 if (of_property_read_bool(np, "dmas")) {
1796 atmel_port->use_dma_rx = true;
1797 atmel_port->use_pdc_rx = false;
33d64c4f
ES		 1798 } else {
1799 atmel_port->use_dma_rx = false;
92c8f7c0 1800 atmel_port->use_pdc_rx = true;
33d64c4f 1801 }
92c8f7c0
AB		 1802 } else {
1803 atmel_port->use_dma_rx = false;
1804 atmel_port->use_pdc_rx = false;
1805 }
33d64c4f 1806
92c8f7c0
AB		 1807 if (of_property_read_bool(np, "atmel,use-dma-tx")) {
1808 if (of_property_read_bool(np, "dmas")) {
1809 atmel_port->use_dma_tx = true;
1810 atmel_port->use_pdc_tx = false;
33d64c4f
ES		 1811 } else {
1812 atmel_port->use_dma_tx = false;
92c8f7c0 1813 atmel_port->use_pdc_tx = true;
33d64c4f 1814 }
33d64c4f 1815 } else {
33d64c4f 1816 atmel_port->use_dma_tx = false;
92c8f7c0 1817 atmel_port->use_pdc_tx = false;
33d64c4f 1818 }
33d64c4f
ES		 1819}
1820
a930e528
ES		 1821static void atmel_set_ops(struct uart_port *port)
1822{
1823 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1824
34df42f5
ES		 1825 if (atmel_use_dma_rx(port)) {
1826 atmel_port->prepare_rx = &atmel_prepare_rx_dma;
1827 atmel_port->schedule_rx = &atmel_rx_from_dma;
1828 atmel_port->release_rx = &atmel_release_rx_dma;
1829 } else if (atmel_use_pdc_rx(port)) {
a930e528
ES		 1830 atmel_port->prepare_rx = &atmel_prepare_rx_pdc;
1831 atmel_port->schedule_rx = &atmel_rx_from_pdc;
1832 atmel_port->release_rx = &atmel_release_rx_pdc;
1833 } else {
1834 atmel_port->prepare_rx = NULL;
1835 atmel_port->schedule_rx = &atmel_rx_from_ring;
1836 atmel_port->release_rx = NULL;
1837 }
1838
08f738be
ES		 1839 if (atmel_use_dma_tx(port)) {
1840 atmel_port->prepare_tx = &atmel_prepare_tx_dma;
1841 atmel_port->schedule_tx = &atmel_tx_dma;
1842 atmel_port->release_tx = &atmel_release_tx_dma;
1843 } else if (atmel_use_pdc_tx(port)) {
a930e528
ES		 1844 atmel_port->prepare_tx = &atmel_prepare_tx_pdc;
1845 atmel_port->schedule_tx = &atmel_tx_pdc;
1846 atmel_port->release_tx = &atmel_release_tx_pdc;
1847 } else {
1848 atmel_port->prepare_tx = NULL;
1849 atmel_port->schedule_tx = &atmel_tx_chars;
1850 atmel_port->release_tx = NULL;
1851 }
1852}
1853
055560b0
ES		 1854/*
1855 * Get ip name usart or uart
1856 */
892db58b 1857static void atmel_get_ip_name(struct uart_port *port)
055560b0
ES		 1858{
1859 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
4e7decda 1860 int name = atmel_uart_readl(port, ATMEL_US_NAME);
731d9cae 1861 u32 version;
1d673fb9 1862 u32 usart, dbgu_uart, new_uart;
4b769371
NF		 1863 /* ASCII decoding for IP version */
1864 usart = 0x55534152; /* USAR(T) */
1865 dbgu_uart = 0x44424755; /* DBGU */
1d673fb9 1866 new_uart = 0x55415254; /* UART */
055560b0 1867
5bf5635a
LD		 1868 /*
1869 * Only USART devices from at91sam9260 SOC implement fractional
2867af2d
RI		 1870 * baudrate. It is available for all asynchronous modes, with the
1871 * following restriction: the sampling clock's duty cycle is not
1872 * constant.
5bf5635a
LD		 1873 */
1874 atmel_port->has_frac_baudrate = false;
4b769371 1875 atmel_port->has_hw_timer = false;
055560b0 1876
2958ccee
LD		 1877 if (name == new_uart) {
1878 dev_dbg(port->dev, "Uart with hw timer");
4b769371 1879 atmel_port->has_hw_timer = true;
2958ccee
LD		 1880 atmel_port->rtor = ATMEL_UA_RTOR;
1881 } else if (name == usart) {
1882 dev_dbg(port->dev, "Usart\n");
5bf5635a 1883 atmel_port->has_frac_baudrate = true;
2958ccee
LD		 1884 atmel_port->has_hw_timer = true;
1885 atmel_port->rtor = ATMEL_US_RTOR;
377fedd1
NF		 1886 version = atmel_uart_readl(port, ATMEL_US_VERSION);
1887 switch (version) {
1888 case 0x814: /* sama5d2 */
1889 /* fall through */
1890 case 0x701: /* sama5d4 */
1891 atmel_port->fidi_min = 3;
1892 atmel_port->fidi_max = 65535;
1893 break;
1894 case 0x502: /* sam9x5, sama5d3 */
1895 atmel_port->fidi_min = 3;
1896 atmel_port->fidi_max = 2047;
1897 break;
1898 default:
1899 atmel_port->fidi_min = 1;
1900 atmel_port->fidi_max = 2047;
1901 }
4b769371
NF		 1902 } else if (name == dbgu_uart) {
1903 dev_dbg(port->dev, "Dbgu or uart without hw timer\n");
055560b0 1904 } else {
731d9cae 1905 /* fallback for older SoCs: use version field */
4e7decda 1906 version = atmel_uart_readl(port, ATMEL_US_VERSION);
731d9cae
NF		 1907 switch (version) {
1908 case 0x302:
1909 case 0x10213:
fd63a890 1910 case 0x10302:
731d9cae 1911 dev_dbg(port->dev, "This version is usart\n");
5bf5635a 1912 atmel_port->has_frac_baudrate = true;
4b769371 1913 atmel_port->has_hw_timer = true;
2958ccee 1914 atmel_port->rtor = ATMEL_US_RTOR;
731d9cae
NF		 1915 break;
1916 case 0x203:
1917 case 0x10202:
1918 dev_dbg(port->dev, "This version is uart\n");
731d9cae
NF		 1919 break;
1920 default:
1921 dev_err(port->dev, "Not supported ip name nor version, set to uart\n");
1922 }
055560b0 1923 }
055560b0
ES		 1924}
1925
1e6c9c28
AV		 1926/*
1927 * Perform initialization and enable port for reception
1928 */
7192f92c 1929static int atmel_startup(struct uart_port *port)
1e6c9c28 1930{
33d64c4f 1931 struct platform_device *pdev = to_platform_device(port->dev);
c811ab8c 1932 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1e6c9c28
AV		 1933 int retval;
1934
1935 /*
1936 * Ensure that no interrupts are enabled otherwise when
1937 * request_irq() is called we could get stuck trying to
1938 * handle an unexpected interrupt
1939 */
4e7decda 1940 atmel_uart_writel(port, ATMEL_US_IDR, -1);
ab5e4e41 1941 atmel_port->ms_irq_enabled = false;
1e6c9c28
AV		 1942
1943 /*
1944 * Allocate the IRQ
1945 */
2c7af5ba 1946 retval = request_irq(port->irq, atmel_interrupt,
9594b5be
SAS		 1947 IRQF_SHARED | IRQF_COND_SUSPEND,
1948 dev_name(&pdev->dev), port);
1e6c9c28 1949 if (retval) {
ddaa6037 1950 dev_err(port->dev, "atmel_startup - Can't get irq\n");
1e6c9c28
AV		 1951 return retval;
1952 }
1953
98f2082c
NF		 1954 atomic_set(&atmel_port->tasklet_shutdown, 0);
1955 tasklet_init(&atmel_port->tasklet_rx, atmel_tasklet_rx_func,
1956 (unsigned long)port);
1957 tasklet_init(&atmel_port->tasklet_tx, atmel_tasklet_tx_func,
1958 (unsigned long)port);
1e125786 1959
a6670615
CC		 1960 /*
1961 * Initialize DMA (if necessary)
1962 */
33d64c4f 1963 atmel_init_property(atmel_port, pdev);
4d9628a1 1964 atmel_set_ops(port);
33d64c4f 1965
a930e528
ES		 1966 if (atmel_port->prepare_rx) {
1967 retval = atmel_port->prepare_rx(port);
1968 if (retval < 0)
1969 atmel_set_ops(port);
a6670615 1970 }
a6670615 1971
a930e528
ES		 1972 if (atmel_port->prepare_tx) {
1973 retval = atmel_port->prepare_tx(port);
1974 if (retval < 0)
1975 atmel_set_ops(port);
a6670615 1976 }
1e6c9c28 1977
b5199d46
CP		 1978 /*
1979 * Enable FIFO when available
1980 */
1981 if (atmel_port->fifo_size) {
1982 unsigned int txrdym = ATMEL_US_ONE_DATA;
1983 unsigned int rxrdym = ATMEL_US_ONE_DATA;
1984 unsigned int fmr;
1985
1986 atmel_uart_writel(port, ATMEL_US_CR,
1987 ATMEL_US_FIFOEN |
1988 ATMEL_US_RXFCLR |
1989 ATMEL_US_TXFLCLR);
1990
5f258b3e
CP		 1991 if (atmel_use_dma_tx(port))
1992 txrdym = ATMEL_US_FOUR_DATA;
1993
b5199d46
CP		 1994 fmr = ATMEL_US_TXRDYM(txrdym) | ATMEL_US_RXRDYM(rxrdym);
1995 if (atmel_port->rts_high &&
1996 atmel_port->rts_low)
1997 fmr |= ATMEL_US_FRTSC |
1998 ATMEL_US_RXFTHRES(atmel_port->rts_high) |
1999 ATMEL_US_RXFTHRES2(atmel_port->rts_low);
2000
2001 atmel_uart_writel(port, ATMEL_US_FMR, fmr);
2002 }
2003
27c0c8e5 2004 /* Save current CSR for comparison in atmel_tasklet_func() */
e0b0baad 2005 atmel_port->irq_status_prev = atmel_get_lines_status(port);
27c0c8e5 2006
1e6c9c28
AV		 2007 /*
2008 * Finally, enable the serial port
2009 */
4e7decda 2010 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
b843aa21 2011 /* enable xmit & rcvr */
4e7decda 2012 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN);
ea04f82a 2013 atmel_port->tx_stopped = false;
afefc415 2014
026cb432 2015 timer_setup(&atmel_port->uart_timer, atmel_uart_timer_callback, 0);
8bc661bf 2016
64e22ebe 2017 if (atmel_use_pdc_rx(port)) {
a6670615 2018 /* set UART timeout */
4b769371 2019 if (!atmel_port->has_hw_timer) {
2e68c22f
ES		 2020 mod_timer(&atmel_port->uart_timer,
2021 jiffies + uart_poll_timeout(port));
2022 /* set USART timeout */
2023 } else {
2958ccee
LD		 2024 atmel_uart_writel(port, atmel_port->rtor,
2025 PDC_RX_TIMEOUT);
4e7decda 2026 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
a6670615 2027
4e7decda
CP		 2028 atmel_uart_writel(port, ATMEL_US_IER,
2029 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT);
2e68c22f 2030 }
a6670615 2031 /* enable PDC controller */
4e7decda 2032 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN);
34df42f5 2033 } else if (atmel_use_dma_rx(port)) {
2e68c22f 2034 /* set UART timeout */
4b769371 2035 if (!atmel_port->has_hw_timer) {
2e68c22f
ES		 2036 mod_timer(&atmel_port->uart_timer,
2037 jiffies + uart_poll_timeout(port));
2038 /* set USART timeout */
2039 } else {
2958ccee
LD		 2040 atmel_uart_writel(port, atmel_port->rtor,
2041 PDC_RX_TIMEOUT);
4e7decda 2042 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
34df42f5 2043
4e7decda
CP		 2044 atmel_uart_writel(port, ATMEL_US_IER,
2045 ATMEL_US_TIMEOUT);
2e68c22f 2046 }
a6670615
CC		 2047 } else {
2048 /* enable receive only */
4e7decda 2049 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_RXRDY);
a6670615 2050 }
afefc415 2051
1e6c9c28
AV		 2052 return 0;
2053}
2054
479e9b94
PH		 2055/*
2056 * Flush any TX data submitted for DMA. Called when the TX circular
2057 * buffer is reset.
2058 */
2059static void atmel_flush_buffer(struct uart_port *port)
2060{
2061 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2062
2063 if (atmel_use_pdc_tx(port)) {
4e7decda 2064 atmel_uart_writel(port, ATMEL_PDC_TCR, 0);
479e9b94
PH		 2065 atmel_port->pdc_tx.ofs = 0;
2066 }
31ca2c63
RG		 2067 /*
2068 * in uart_flush_buffer(), the xmit circular buffer has just
2069 * been cleared, so we have to reset tx_len accordingly.
2070 */
2071 atmel_port->tx_len = 0;
479e9b94
PH		 2072}
2073
1e6c9c28
AV		 2074/*
2075 * Disable the port
2076 */
7192f92c 2077static void atmel_shutdown(struct uart_port *port)
1e6c9c28 2078{
c811ab8c 2079 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
0cc7c6c7 2080
0ae9fdef
RG		 2081 /* Disable modem control lines interrupts */
2082 atmel_disable_ms(port);
2083
98f2082c
NF		 2084 /* Disable interrupts at device level */
2085 atmel_uart_writel(port, ATMEL_US_IDR, -1);
2086
2087 /* Prevent spurious interrupts from scheduling the tasklet */
2088 atomic_inc(&atmel_port->tasklet_shutdown);
2089
8bc661bf
MR		 2090 /*
2091 * Prevent any tasklets being scheduled during
2092 * cleanup
2093 */
2094 del_timer_sync(&atmel_port->uart_timer);
2095
98f2082c
NF		 2096 /* Make sure that no interrupt is on the fly */
2097 synchronize_irq(port->irq);
2098
0cc7c6c7
MR		 2099 /*
2100 * Clear out any scheduled tasklets before
2101 * we destroy the buffers
2102 */
00e8e658
NF		 2103 tasklet_kill(&atmel_port->tasklet_rx);
2104 tasklet_kill(&atmel_port->tasklet_tx);
0cc7c6c7 2105
a6670615 2106 /*
0cc7c6c7 2107 * Ensure everything is stopped and
98f2082c 2108 * disable port and break condition.
a6670615
CC		 2109 */
2110 atmel_stop_rx(port);
2111 atmel_stop_tx(port);
2112
4e7decda 2113 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
0cc7c6c7 2114
a6670615
CC		 2115 /*
2116 * Shut-down the DMA.
2117 */
a930e528
ES		 2118 if (atmel_port->release_rx)
2119 atmel_port->release_rx(port);
2120 if (atmel_port->release_tx)
2121 atmel_port->release_tx(port);
a6670615 2122
bb7e73c5
MD		 2123 /*
2124 * Reset ring buffer pointers
2125 */
2126 atmel_port->rx_ring.head = 0;
2127 atmel_port->rx_ring.tail = 0;
2128
1e6c9c28 2129 /*
ab5e4e41 2130 * Free the interrupts
1e6c9c28
AV		 2131 */
2132 free_irq(port->irq, port);
ab5e4e41 2133
479e9b94 2134 atmel_flush_buffer(port);
9afd561a
HS		 2135}
2136
1e6c9c28
AV		 2137/*
2138 * Power / Clock management.
2139 */
b843aa21
RB		 2140static void atmel_serial_pm(struct uart_port *port, unsigned int state,
2141 unsigned int oldstate)
1e6c9c28 2142{
c811ab8c 2143 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
afefc415 2144
1e6c9c28 2145 switch (state) {
b843aa21
RB		 2146 case 0:
2147 /*
2148 * Enable the peripheral clock for this serial port.
2149 * This is called on uart_open() or a resume event.
2150 */
91f8c2d8 2151 clk_prepare_enable(atmel_port->clk);
f05596db
AS		 2152
2153 /* re-enable interrupts if we disabled some on suspend */
4e7decda 2154 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->backup_imr);
b843aa21
RB		 2155 break;
2156 case 3:
f05596db 2157 /* Back up the interrupt mask and disable all interrupts */
4e7decda
CP		 2158 atmel_port->backup_imr = atmel_uart_readl(port, ATMEL_US_IMR);
2159 atmel_uart_writel(port, ATMEL_US_IDR, -1);
f05596db 2160
b843aa21
RB		 2161 /*
2162 * Disable the peripheral clock for this serial port.
2163 * This is called on uart_close() or a suspend event.
2164 */
91f8c2d8 2165 clk_disable_unprepare(atmel_port->clk);
b843aa21
RB		 2166 break;
2167 default:
ddaa6037 2168 dev_err(port->dev, "atmel_serial: unknown pm %d\n", state);
1e6c9c28
AV		 2169 }
2170}
2171
2172/*
2173 * Change the port parameters
2174 */
b843aa21
RB		 2175static void atmel_set_termios(struct uart_port *port, struct ktermios *termios,
2176 struct ktermios *old)
1e6c9c28 2177{
5bf5635a 2178 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1e6c9c28 2179 unsigned long flags;
5bf5635a 2180 unsigned int old_mode, mode, imr, quot, baud, div, cd, fp = 0;
1cf6e8fc
CP		 2181
2182 /* save the current mode register */
4e7decda 2183 mode = old_mode = atmel_uart_readl(port, ATMEL_US_MR);
1e6c9c28 2184
1cf6e8fc
CP		 2185 /* reset the mode, clock divisor, parity, stop bits and data size */
2186 mode &= ~(ATMEL_US_USCLKS | ATMEL_US_CHRL | ATMEL_US_NBSTOP |
2187 ATMEL_US_PAR | ATMEL_US_USMODE);
03abeac0 2188
b843aa21 2189 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
1e6c9c28
AV		 2190
2191 /* byte size */
2192 switch (termios->c_cflag & CSIZE) {
2193 case CS5:
7192f92c 2194 mode |= ATMEL_US_CHRL_5;
1e6c9c28
AV		 2195 break;
2196 case CS6:
7192f92c 2197 mode |= ATMEL_US_CHRL_6;
1e6c9c28
AV		 2198 break;
2199 case CS7:
7192f92c 2200 mode |= ATMEL_US_CHRL_7;
1e6c9c28
AV		 2201 break;
2202 default:
7192f92c 2203 mode |= ATMEL_US_CHRL_8;
1e6c9c28
AV		 2204 break;
2205 }
2206
2207 /* stop bits */
2208 if (termios->c_cflag & CSTOPB)
7192f92c 2209 mode |= ATMEL_US_NBSTOP_2;
1e6c9c28
AV		 2210
2211 /* parity */
2212 if (termios->c_cflag & PARENB) {
b843aa21
RB		 2213 /* Mark or Space parity */
2214 if (termios->c_cflag & CMSPAR) {
1e6c9c28 2215 if (termios->c_cflag & PARODD)
7192f92c 2216 mode |= ATMEL_US_PAR_MARK;
1e6c9c28 2217 else
7192f92c 2218 mode |= ATMEL_US_PAR_SPACE;
b843aa21 2219 } else if (termios->c_cflag & PARODD)
7192f92c 2220 mode |= ATMEL_US_PAR_ODD;
1e6c9c28 2221 else
7192f92c 2222 mode |= ATMEL_US_PAR_EVEN;
b843aa21 2223 } else
7192f92c 2224 mode |= ATMEL_US_PAR_NONE;
1e6c9c28
AV		 2225
2226 spin_lock_irqsave(&port->lock, flags);
2227
7192f92c 2228 port->read_status_mask = ATMEL_US_OVRE;
1e6c9c28 2229 if (termios->c_iflag & INPCK)
7192f92c 2230 port->read_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE);
ef8b9ddc 2231 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
7192f92c 2232 port->read_status_mask |= ATMEL_US_RXBRK;
1e6c9c28 2233
64e22ebe 2234 if (atmel_use_pdc_rx(port))
a6670615 2235 /* need to enable error interrupts */
4e7decda 2236 atmel_uart_writel(port, ATMEL_US_IER, port->read_status_mask);
a6670615 2237
1e6c9c28
AV		 2238 /*
2239 * Characters to ignore
2240 */
2241 port->ignore_status_mask = 0;
2242 if (termios->c_iflag & IGNPAR)
7192f92c 2243 port->ignore_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE);
1e6c9c28 2244 if (termios->c_iflag & IGNBRK) {
7192f92c 2245 port->ignore_status_mask |= ATMEL_US_RXBRK;
1e6c9c28
AV		 2246 /*
2247 * If we're ignoring parity and break indicators,
2248 * ignore overruns too (for real raw support).
2249 */
2250 if (termios->c_iflag & IGNPAR)
7192f92c 2251 port->ignore_status_mask |= ATMEL_US_OVRE;
1e6c9c28 2252 }
b843aa21 2253 /* TODO: Ignore all characters if CREAD is set.*/
1e6c9c28
AV		 2254
2255 /* update the per-port timeout */
2256 uart_update_timeout(port, termios->c_cflag, baud);
2257
0ccad870
HS		 2258 /*
2259 * save/disable interrupts. The tty layer will ensure that the
2260 * transmitter is empty if requested by the caller, so there's
2261 * no need to wait for it here.
2262 */
4e7decda
CP		 2263 imr = atmel_uart_readl(port, ATMEL_US_IMR);
2264 atmel_uart_writel(port, ATMEL_US_IDR, -1);
1e6c9c28
AV		 2265
2266 /* disable receiver and transmitter */
4e7decda 2267 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXDIS | ATMEL_US_RXDIS);
ea04f82a 2268 atmel_port->tx_stopped = true;
1e6c9c28 2269
1cf6e8fc 2270 /* mode */
13bd3e6f 2271 if (port->rs485.flags & SER_RS485_ENABLED) {
4e7decda
CP		 2272 atmel_uart_writel(port, ATMEL_US_TTGR,
2273 port->rs485.delay_rts_after_send);
e8faff73 2274 mode |= ATMEL_US_USMODE_RS485;
377fedd1
NF		 2275 } else if (port->iso7816.flags & SER_ISO7816_ENABLED) {
2276 atmel_uart_writel(port, ATMEL_US_TTGR, port->iso7816.tg);
2277 /* select mck clock, and output */
2278 mode |= ATMEL_US_USCLKS_MCK | ATMEL_US_CLKO;
2279 /* set max iterations */
2280 mode |= ATMEL_US_MAX_ITER(3);
2281 if ((port->iso7816.flags & SER_ISO7816_T_PARAM)
2282 == SER_ISO7816_T(0))
2283 mode |= ATMEL_US_USMODE_ISO7816_T0;
2284 else
2285 mode |= ATMEL_US_USMODE_ISO7816_T1;
1cf6e8fc
CP		 2286 } else if (termios->c_cflag & CRTSCTS) {
2287 /* RS232 with hardware handshake (RTS/CTS) */
9bcffe75
RG		 2288 if (atmel_use_fifo(port) &&
2289 !mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_CTS)) {
2290 /*
2291 * with ATMEL_US_USMODE_HWHS set, the controller will
2292 * be able to drive the RTS pin high/low when the RX
2293 * FIFO is above RXFTHRES/below RXFTHRES2.
2294 * It will also disable the transmitter when the CTS
2295 * pin is high.
2296 * This mode is not activated if CTS pin is a GPIO
2297 * because in this case, the transmitter is always
2298 * disabled (there must be an internal pull-up
2299 * responsible for this behaviour).
2300 * If the RTS pin is a GPIO, the controller won't be
2301 * able to drive it according to the FIFO thresholds,
2302 * but it will be handled by the driver.
2303 */
5be605ac 2304 mode |= ATMEL_US_USMODE_HWHS;
9bcffe75
RG		 2305 } else {
2306 /*
2307 * For platforms without FIFO, the flow control is
2308 * handled by the driver.
2309 */
2310 mode |= ATMEL_US_USMODE_NORMAL;
5be605ac 2311 }
1cf6e8fc
CP		 2312 } else {
2313 /* RS232 without hadware handshake */
2314 mode |= ATMEL_US_USMODE_NORMAL;
e8faff73
CS		 2315 }
2316
1cf6e8fc 2317 /* set the mode, clock divisor, parity, stop bits and data size */
4e7decda 2318 atmel_uart_writel(port, ATMEL_US_MR, mode);
1e6c9c28 2319
1cf6e8fc
CP		 2320 /*
2321 * when switching the mode, set the RTS line state according to the
2322 * new mode, otherwise keep the former state
2323 */
2324 if ((old_mode & ATMEL_US_USMODE) != (mode & ATMEL_US_USMODE)) {
2325 unsigned int rts_state;
2326
2327 if ((mode & ATMEL_US_USMODE) == ATMEL_US_USMODE_HWHS) {
2328 /* let the hardware control the RTS line */
2329 rts_state = ATMEL_US_RTSDIS;
2330 } else {
2331 /* force RTS line to low level */
2332 rts_state = ATMEL_US_RTSEN;
2333 }
2334
4e7decda 2335 atmel_uart_writel(port, ATMEL_US_CR, rts_state);
1cf6e8fc
CP		 2336 }
2337
5bf5635a
LD		 2338 /*
2339 * Set the baud rate:
2340 * Fractional baudrate allows to setup output frequency more
2341 * accurately. This feature is enabled only when using normal mode.
2342 * baudrate = selected clock / (8 * (2 - OVER) * (CD + FP / 8))
2343 * Currently, OVER is always set to 0 so we get
36131cdf
AS		 2344 * baudrate = selected clock / (16 * (CD + FP / 8))
2345 * then
2346 * 8 CD + FP = selected clock / (2 * baudrate)
5bf5635a 2347 */
2867af2d 2348 if (atmel_port->has_frac_baudrate) {
36131cdf
AS		 2349 div = DIV_ROUND_CLOSEST(port->uartclk, baud * 2);
2350 cd = div >> 3;
2351 fp = div & ATMEL_US_FP_MASK;
5bf5635a
LD		 2352 } else {
2353 cd = uart_get_divisor(port, baud);
2354 }
2355
2356 if (cd > 65535) { /* BRGR is 16-bit, so switch to slower clock */
2357 cd /= 8;
2358 mode |= ATMEL_US_USCLKS_MCK_DIV8;
2359 }
2360 quot = cd | fp << ATMEL_US_FP_OFFSET;
2361
377fedd1
NF		 2362 if (!(port->iso7816.flags & SER_ISO7816_ENABLED))
2363 atmel_uart_writel(port, ATMEL_US_BRGR, quot);
4e7decda
CP		 2364 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
2365 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN);
ea04f82a 2366 atmel_port->tx_stopped = false;
1e6c9c28
AV		 2367
2368 /* restore interrupts */
4e7decda 2369 atmel_uart_writel(port, ATMEL_US_IER, imr);
1e6c9c28
AV		 2370
2371 /* CTS flow-control and modem-status interrupts */
2372 if (UART_ENABLE_MS(port, termios->c_cflag))
35b675b9
RG		 2373 atmel_enable_ms(port);
2374 else
2375 atmel_disable_ms(port);
1e6c9c28
AV		 2376
2377 spin_unlock_irqrestore(&port->lock, flags);
2378}
2379
732a84a0 2380static void atmel_set_ldisc(struct uart_port *port, struct ktermios *termios)
42bd7a4f 2381{
732a84a0 2382 if (termios->c_line == N_PPS) {
42bd7a4f 2383 port->flags |= UPF_HARDPPS_CD;
d41510ce 2384 spin_lock_irq(&port->lock);
42bd7a4f 2385 atmel_enable_ms(port);
d41510ce 2386 spin_unlock_irq(&port->lock);
42bd7a4f
VP		 2387 } else {
2388 port->flags &= ~UPF_HARDPPS_CD;
cab68f89
PH		 2389 if (!UART_ENABLE_MS(port, termios->c_cflag)) {
2390 spin_lock_irq(&port->lock);
2391 atmel_disable_ms(port);
2392 spin_unlock_irq(&port->lock);
2393 }
42bd7a4f
VP		 2394 }
2395}
2396
1e6c9c28
AV		 2397/*
2398 * Return string describing the specified port
2399 */
7192f92c 2400static const char *atmel_type(struct uart_port *port)
1e6c9c28 2401{
9ab4f88b 2402 return (port->type == PORT_ATMEL) ? "ATMEL_SERIAL" : NULL;
1e6c9c28
AV		 2403}
2404
2405/*
2406 * Release the memory region(s) being used by 'port'.
2407 */
7192f92c 2408static void atmel_release_port(struct uart_port *port)
1e6c9c28 2409{
c24d2531
RP		 2410 struct platform_device *mpdev = to_platform_device(port->dev->parent);
2411 int size = resource_size(mpdev->resource);
afefc415
AV		 2412
2413 release_mem_region(port->mapbase, size);
2414
2415 if (port->flags & UPF_IOREMAP) {
2416 iounmap(port->membase);
2417 port->membase = NULL;
2418 }
1e6c9c28
AV		 2419}
2420
2421/*
2422 * Request the memory region(s) being used by 'port'.
2423 */
7192f92c 2424static int atmel_request_port(struct uart_port *port)
1e6c9c28 2425{
c24d2531
RP		 2426 struct platform_device *mpdev = to_platform_device(port->dev->parent);
2427 int size = resource_size(mpdev->resource);
afefc415 2428
7192f92c 2429 if (!request_mem_region(port->mapbase, size, "atmel_serial"))
afefc415
AV		 2430 return -EBUSY;
2431
2432 if (port->flags & UPF_IOREMAP) {
2433 port->membase = ioremap(port->mapbase, size);
2434 if (port->membase == NULL) {
2435 release_mem_region(port->mapbase, size);
2436 return -ENOMEM;
2437 }
2438 }
1e6c9c28 2439
afefc415 2440 return 0;
1e6c9c28
AV		 2441}
2442
2443/*
2444 * Configure/autoconfigure the port.
2445 */
7192f92c 2446static void atmel_config_port(struct uart_port *port, int flags)
1e6c9c28
AV		 2447{
2448 if (flags & UART_CONFIG_TYPE) {
9ab4f88b 2449 port->type = PORT_ATMEL;
7192f92c 2450 atmel_request_port(port);
1e6c9c28
AV		 2451 }
2452}
2453
2454/*
2455 * Verify the new serial_struct (for TIOCSSERIAL).
2456 */
7192f92c 2457static int atmel_verify_port(struct uart_port *port, struct serial_struct *ser)
1e6c9c28
AV		 2458{
2459 int ret = 0;
9ab4f88b 2460 if (ser->type != PORT_UNKNOWN && ser->type != PORT_ATMEL)
1e6c9c28
AV		 2461 ret = -EINVAL;
2462 if (port->irq != ser->irq)
2463 ret = -EINVAL;
2464 if (ser->io_type != SERIAL_IO_MEM)
2465 ret = -EINVAL;
2466 if (port->uartclk / 16 != ser->baud_base)
2467 ret = -EINVAL;
270c2ade 2468 if (port->mapbase != (unsigned long)ser->iomem_base)
1e6c9c28
AV		 2469 ret = -EINVAL;
2470 if (port->iobase != ser->port)
2471 ret = -EINVAL;
2472 if (ser->hub6 != 0)
2473 ret = -EINVAL;
2474 return ret;
2475}
2476
8fe2d541
AT		 2477#ifdef CONFIG_CONSOLE_POLL
2478static int atmel_poll_get_char(struct uart_port *port)
2479{
4e7decda 2480 while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_RXRDY))
8fe2d541
AT		 2481 cpu_relax();
2482
a6499435 2483 return atmel_uart_read_char(port);
8fe2d541
AT		 2484}
2485
2486static void atmel_poll_put_char(struct uart_port *port, unsigned char ch)
2487{
4e7decda 2488 while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXRDY))
8fe2d541
AT		 2489 cpu_relax();
2490
a6499435 2491 atmel_uart_write_char(port, ch);
8fe2d541
AT		 2492}
2493#endif
2494
5c7dcdb6 2495static const struct uart_ops atmel_pops = {
7192f92c
HS		 2496 .tx_empty = atmel_tx_empty,
2497 .set_mctrl = atmel_set_mctrl,
2498 .get_mctrl = atmel_get_mctrl,
2499 .stop_tx = atmel_stop_tx,
2500 .start_tx = atmel_start_tx,
2501 .stop_rx = atmel_stop_rx,
2502 .enable_ms = atmel_enable_ms,
2503 .break_ctl = atmel_break_ctl,
2504 .startup = atmel_startup,
2505 .shutdown = atmel_shutdown,
9afd561a 2506 .flush_buffer = atmel_flush_buffer,
7192f92c 2507 .set_termios = atmel_set_termios,
42bd7a4f 2508 .set_ldisc = atmel_set_ldisc,
7192f92c
HS		 2509 .type = atmel_type,
2510 .release_port = atmel_release_port,
2511 .request_port = atmel_request_port,
2512 .config_port = atmel_config_port,
2513 .verify_port = atmel_verify_port,
2514 .pm = atmel_serial_pm,
8fe2d541
AT		 2515#ifdef CONFIG_CONSOLE_POLL
2516 .poll_get_char = atmel_poll_get_char,
2517 .poll_put_char = atmel_poll_put_char,
2518#endif
1e6c9c28
AV		 2519};
2520
afefc415
AV		 2521/*
2522 * Configure the port from the platform device resource info.
2523 */
91f8c2d8 2524static int atmel_init_port(struct atmel_uart_port *atmel_port,
b843aa21 2525 struct platform_device *pdev)
1e6c9c28 2526{
91f8c2d8 2527 int ret;
7192f92c 2528 struct uart_port *port = &atmel_port->uart;
c24d2531 2529 struct platform_device *mpdev = to_platform_device(pdev->dev.parent);
afefc415 2530
4a1e8888
LZ		 2531 atmel_init_property(atmel_port, pdev);
2532 atmel_set_ops(port);
afefc415 2533
c24d2531 2534 uart_get_rs485_mode(&mpdev->dev, &port->rs485);
a930e528 2535
e8faff73 2536 port->iotype = UPIO_MEM;
92c8f7c0 2537 port->flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP;
e8faff73
CS		 2538 port->ops = &atmel_pops;
2539 port->fifosize = 1;
e8faff73 2540 port->dev = &pdev->dev;
c24d2531
RP		 2541 port->mapbase = mpdev->resource[0].start;
2542 port->irq = mpdev->resource[1].start;
13bd3e6f 2543 port->rs485_config = atmel_config_rs485;
377fedd1 2544 port->iso7816_config = atmel_config_iso7816;
c24d2531 2545 port->membase = NULL;
afefc415 2546
1ecc26bd
RB		 2547 memset(&atmel_port->rx_ring, 0, sizeof(atmel_port->rx_ring));
2548
b843aa21
RB		 2549 /* for console, the clock could already be configured */
2550 if (!atmel_port->clk) {
c24d2531 2551 atmel_port->clk = clk_get(&mpdev->dev, "usart");
91f8c2d8
BB		 2552 if (IS_ERR(atmel_port->clk)) {
2553 ret = PTR_ERR(atmel_port->clk);
2554 atmel_port->clk = NULL;
2555 return ret;
2556 }
2557 ret = clk_prepare_enable(atmel_port->clk);
2558 if (ret) {
2559 clk_put(atmel_port->clk);
2560 atmel_port->clk = NULL;
2561 return ret;
2562 }
7192f92c 2563 port->uartclk = clk_get_rate(atmel_port->clk);
91f8c2d8 2564 clk_disable_unprepare(atmel_port->clk);
06a7f058 2565 /* only enable clock when USART is in use */
afefc415 2566 }
a6670615 2567
377fedd1
NF		 2568 /*
2569 * Use TXEMPTY for interrupt when rs485 or ISO7816 else TXRDY or
2570 * ENDTX|TXBUFE
2571 */
2572 if (port->rs485.flags & SER_RS485_ENABLED ||
2573 port->iso7816.flags & SER_ISO7816_ENABLED)
e8faff73 2574 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY;
64e22ebe 2575 else if (atmel_use_pdc_tx(port)) {
a6670615 2576 port->fifosize = PDC_BUFFER_SIZE;
e8faff73
CS		 2577 atmel_port->tx_done_mask = ATMEL_US_ENDTX | ATMEL_US_TXBUFE;
2578 } else {
2579 atmel_port->tx_done_mask = ATMEL_US_TXRDY;
2580 }
91f8c2d8
BB		 2581
2582 return 0;
1e6c9c28
AV		 2583}
2584
749c4e60 2585#ifdef CONFIG_SERIAL_ATMEL_CONSOLE
7192f92c 2586static void atmel_console_putchar(struct uart_port *port, int ch)
d358788f 2587{
4e7decda 2588 while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXRDY))
829dd811 2589 cpu_relax();
a6499435 2590 atmel_uart_write_char(port, ch);
d358788f 2591}
1e6c9c28
AV		 2592
2593/*
2594 * Interrupts are disabled on entering
2595 */
7192f92c 2596static void atmel_console_write(struct console *co, const char *s, u_int count)
1e6c9c28 2597{
7192f92c 2598 struct uart_port *port = &atmel_ports[co->index].uart;
e8faff73 2599 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
d358788f 2600 unsigned int status, imr;
39d4c922 2601 unsigned int pdc_tx;
1e6c9c28
AV		 2602
2603 /*
b843aa21 2604 * First, save IMR and then disable interrupts
1e6c9c28 2605 */
4e7decda
CP		 2606 imr = atmel_uart_readl(port, ATMEL_US_IMR);
2607 atmel_uart_writel(port, ATMEL_US_IDR,
2608 ATMEL_US_RXRDY | atmel_port->tx_done_mask);
1e6c9c28 2609
39d4c922 2610 /* Store PDC transmit status and disable it */
4e7decda
CP		 2611 pdc_tx = atmel_uart_readl(port, ATMEL_PDC_PTSR) & ATMEL_PDC_TXTEN;
2612 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS);
39d4c922 2613
497e1e16
NF		 2614 /* Make sure that tx path is actually able to send characters */
2615 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN);
ea04f82a 2616 atmel_port->tx_stopped = false;
497e1e16 2617
7192f92c 2618 uart_console_write(port, s, count, atmel_console_putchar);
1e6c9c28
AV		 2619
2620 /*
b843aa21
RB		 2621 * Finally, wait for transmitter to become empty
2622 * and restore IMR
1e6c9c28
AV		 2623 */
2624 do {
4e7decda 2625 status = atmel_uart_readl(port, ATMEL_US_CSR);
7192f92c 2626 } while (!(status & ATMEL_US_TXRDY));
39d4c922
MP		 2627
2628 /* Restore PDC transmit status */
2629 if (pdc_tx)
4e7decda 2630 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
39d4c922 2631
b843aa21 2632 /* set interrupts back the way they were */
4e7decda 2633 atmel_uart_writel(port, ATMEL_US_IER, imr);
1e6c9c28
AV		 2634}
2635
2636/*
b843aa21
RB		 2637 * If the port was already initialised (eg, by a boot loader),
2638 * try to determine the current setup.
1e6c9c28 2639 */
b843aa21
RB		 2640static void __init atmel_console_get_options(struct uart_port *port, int *baud,
2641 int *parity, int *bits)
1e6c9c28
AV		 2642{
2643 unsigned int mr, quot;
2644
1c0fd82f
HS		 2645 /*
2646 * If the baud rate generator isn't running, the port wasn't
2647 * initialized by the boot loader.
2648 */
4e7decda 2649 quot = atmel_uart_readl(port, ATMEL_US_BRGR) & ATMEL_US_CD;
1c0fd82f
HS		 2650 if (!quot)
2651 return;
1e6c9c28 2652
4e7decda 2653 mr = atmel_uart_readl(port, ATMEL_US_MR) & ATMEL_US_CHRL;
7192f92c 2654 if (mr == ATMEL_US_CHRL_8)
1e6c9c28
AV		 2655 *bits = 8;
2656 else
2657 *bits = 7;
2658
4e7decda 2659 mr = atmel_uart_readl(port, ATMEL_US_MR) & ATMEL_US_PAR;
7192f92c 2660 if (mr == ATMEL_US_PAR_EVEN)
1e6c9c28 2661 *parity = 'e';
7192f92c 2662 else if (mr == ATMEL_US_PAR_ODD)
1e6c9c28
AV		 2663 *parity = 'o';
2664
4d5e392c
HS		 2665 /*
2666 * The serial core only rounds down when matching this to a
2667 * supported baud rate. Make sure we don't end up slightly
2668 * lower than one of those, as it would make us fall through
2669 * to a much lower baud rate than we really want.
2670 */
4d5e392c 2671 *baud = port->uartclk / (16 * (quot - 1));
1e6c9c28
AV		 2672}
2673
7192f92c 2674static int __init atmel_console_setup(struct console *co, char *options)
1e6c9c28 2675{
91f8c2d8 2676 int ret;
7192f92c 2677 struct uart_port *port = &atmel_ports[co->index].uart;
ea04f82a 2678 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1e6c9c28
AV		 2679 int baud = 115200;
2680 int bits = 8;
2681 int parity = 'n';
2682 int flow = 'n';
2683
b843aa21
RB		 2684 if (port->membase == NULL) {
2685 /* Port not initialized yet - delay setup */
afefc415 2686 return -ENODEV;
b843aa21 2687 }
1e6c9c28 2688
91f8c2d8
BB		 2689 ret = clk_prepare_enable(atmel_ports[co->index].clk);
2690 if (ret)
2691 return ret;
06a7f058 2692
4e7decda
CP		 2693 atmel_uart_writel(port, ATMEL_US_IDR, -1);
2694 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
2695 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN);
ea04f82a 2696 atmel_port->tx_stopped = false;
1e6c9c28
AV		 2697
2698 if (options)
2699 uart_parse_options(options, &baud, &parity, &bits, &flow);
2700 else
7192f92c 2701 atmel_console_get_options(port, &baud, &parity, &bits);
1e6c9c28
AV		 2702
2703 return uart_set_options(port, co, baud, parity, bits, flow);
2704}
2705
7192f92c 2706static struct uart_driver atmel_uart;
1e6c9c28 2707
7192f92c
HS		 2708static struct console atmel_console = {
2709 .name = ATMEL_DEVICENAME,
2710 .write = atmel_console_write,
1e6c9c28 2711 .device = uart_console_device,
7192f92c 2712 .setup = atmel_console_setup,
1e6c9c28
AV		 2713 .flags = CON_PRINTBUFFER,
2714 .index = -1,
7192f92c 2715 .data = &atmel_uart,
1e6c9c28
AV		 2716};
2717
06a7f058 2718#define ATMEL_CONSOLE_DEVICE (&atmel_console)
1e6c9c28 2719
dfa7f343
HS		 2720static inline bool atmel_is_console_port(struct uart_port *port)
2721{
2722 return port->cons && port->cons->index == port->line;
2723}
2724
1e6c9c28 2725#else
7192f92c 2726#define ATMEL_CONSOLE_DEVICE NULL
dfa7f343
HS		 2727
2728static inline bool atmel_is_console_port(struct uart_port *port)
2729{
2730 return false;
2731}
1e6c9c28
AV		 2732#endif
2733
7192f92c 2734static struct uart_driver atmel_uart = {
b843aa21
RB		 2735 .owner = THIS_MODULE,
2736 .driver_name = "atmel_serial",
2737 .dev_name = ATMEL_DEVICENAME,
2738 .major = SERIAL_ATMEL_MAJOR,
2739 .minor = MINOR_START,
2740 .nr = ATMEL_MAX_UART,
2741 .cons = ATMEL_CONSOLE_DEVICE,
1e6c9c28
AV		 2742};
2743
afefc415 2744#ifdef CONFIG_PM
f826caa4
HS		 2745static bool atmel_serial_clk_will_stop(void)
2746{
2747#ifdef CONFIG_ARCH_AT91
2748 return at91_suspend_entering_slow_clock();
2749#else
2750 return false;
2751#endif
2752}
2753
b843aa21
RB		 2754static int atmel_serial_suspend(struct platform_device *pdev,
2755 pm_message_t state)
1e6c9c28 2756{
afefc415 2757 struct uart_port *port = platform_get_drvdata(pdev);
c811ab8c 2758 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
afefc415 2759
e1c609ef
HS		 2760 if (atmel_is_console_port(port) && console_suspend_enabled) {
2761 /* Drain the TX shifter */
4e7decda
CP		 2762 while (!(atmel_uart_readl(port, ATMEL_US_CSR) &
2763 ATMEL_US_TXEMPTY))
e1c609ef
HS		 2764 cpu_relax();
2765 }
2766
6a5f0e2f
AB		 2767 if (atmel_is_console_port(port) && !console_suspend_enabled) {
2768 /* Cache register values as we won't get a full shutdown/startup
2769 * cycle
2770 */
2771 atmel_port->cache.mr = atmel_uart_readl(port, ATMEL_US_MR);
2772 atmel_port->cache.imr = atmel_uart_readl(port, ATMEL_US_IMR);
2773 atmel_port->cache.brgr = atmel_uart_readl(port, ATMEL_US_BRGR);
2774 atmel_port->cache.rtor = atmel_uart_readl(port,
2775 atmel_port->rtor);
2776 atmel_port->cache.ttgr = atmel_uart_readl(port, ATMEL_US_TTGR);
2777 atmel_port->cache.fmr = atmel_uart_readl(port, ATMEL_US_FMR);
2778 atmel_port->cache.fimr = atmel_uart_readl(port, ATMEL_US_FIMR);
2779 }
2780
f05596db
AS		 2781 /* we can not wake up if we're running on slow clock */
2782 atmel_port->may_wakeup = device_may_wakeup(&pdev->dev);
2c7af5ba
BB		 2783 if (atmel_serial_clk_will_stop()) {
2784 unsigned long flags;
2785
2786 spin_lock_irqsave(&atmel_port->lock_suspended, flags);
2787 atmel_port->suspended = true;
2788 spin_unlock_irqrestore(&atmel_port->lock_suspended, flags);
f05596db 2789 device_set_wakeup_enable(&pdev->dev, 0);
2c7af5ba 2790 }
f05596db
AS		 2791
2792 uart_suspend_port(&atmel_uart, port);
1e6c9c28 2793
afefc415
AV		 2794 return 0;
2795}
1e6c9c28 2796
7192f92c 2797static int atmel_serial_resume(struct platform_device *pdev)
afefc415
AV		 2798{
2799 struct uart_port *port = platform_get_drvdata(pdev);
c811ab8c 2800 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2c7af5ba
BB		 2801 unsigned long flags;
2802
6a5f0e2f
AB		 2803 if (atmel_is_console_port(port) && !console_suspend_enabled) {
2804 atmel_uart_writel(port, ATMEL_US_MR, atmel_port->cache.mr);
2805 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->cache.imr);
2806 atmel_uart_writel(port, ATMEL_US_BRGR, atmel_port->cache.brgr);
2807 atmel_uart_writel(port, atmel_port->rtor,
2808 atmel_port->cache.rtor);
2809 atmel_uart_writel(port, ATMEL_US_TTGR, atmel_port->cache.ttgr);
2810
2811 if (atmel_port->fifo_size) {
2812 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_FIFOEN |
2813 ATMEL_US_RXFCLR | ATMEL_US_TXFLCLR);
2814 atmel_uart_writel(port, ATMEL_US_FMR,
2815 atmel_port->cache.fmr);
2816 atmel_uart_writel(port, ATMEL_US_FIER,
2817 atmel_port->cache.fimr);
2818 }
2819 atmel_start_rx(port);
2820 }
2821
2c7af5ba
BB		 2822 spin_lock_irqsave(&atmel_port->lock_suspended, flags);
2823 if (atmel_port->pending) {
2824 atmel_handle_receive(port, atmel_port->pending);
2825 atmel_handle_status(port, atmel_port->pending,
2826 atmel_port->pending_status);
2827 atmel_handle_transmit(port, atmel_port->pending);
2828 atmel_port->pending = 0;
2829 }
2830 atmel_port->suspended = false;
2831 spin_unlock_irqrestore(&atmel_port->lock_suspended, flags);
1e6c9c28 2832
f05596db
AS		 2833 uart_resume_port(&atmel_uart, port);
2834 device_set_wakeup_enable(&pdev->dev, atmel_port->may_wakeup);
1e6c9c28
AV		 2835
2836 return 0;
2837}
afefc415 2838#else
7192f92c
HS		 2839#define atmel_serial_suspend NULL
2840#define atmel_serial_resume NULL
afefc415 2841#endif
1e6c9c28 2842
b78cd169 2843static void atmel_serial_probe_fifos(struct atmel_uart_port *atmel_port,
b5199d46
CP		 2844 struct platform_device *pdev)
2845{
b78cd169
JA		 2846 atmel_port->fifo_size = 0;
2847 atmel_port->rts_low = 0;
2848 atmel_port->rts_high = 0;
b5199d46
CP		 2849
2850 if (of_property_read_u32(pdev->dev.of_node,
2851 "atmel,fifo-size",
b78cd169 2852 &atmel_port->fifo_size))
b5199d46
CP		 2853 return;
2854
b78cd169 2855 if (!atmel_port->fifo_size)
b5199d46
CP		 2856 return;
2857
b78cd169
JA		 2858 if (atmel_port->fifo_size < ATMEL_MIN_FIFO_SIZE) {
2859 atmel_port->fifo_size = 0;
b5199d46
CP		 2860 dev_err(&pdev->dev, "Invalid FIFO size\n");
2861 return;
2862 }
2863
2864 /*
2865 * 0 <= rts_low <= rts_high <= fifo_size
2866 * Once their CTS line asserted by the remote peer, some x86 UARTs tend
2867 * to flush their internal TX FIFO, commonly up to 16 data, before
2868 * actually stopping to send new data. So we try to set the RTS High
2869 * Threshold to a reasonably high value respecting this 16 data
2870 * empirical rule when possible.
2871 */
b78cd169
JA		 2872 atmel_port->rts_high = max_t(int, atmel_port->fifo_size >> 1,
2873 atmel_port->fifo_size - ATMEL_RTS_HIGH_OFFSET);
2874 atmel_port->rts_low = max_t(int, atmel_port->fifo_size >> 2,
2875 atmel_port->fifo_size - ATMEL_RTS_LOW_OFFSET);
b5199d46
CP		 2876
2877 dev_info(&pdev->dev, "Using FIFO (%u data)\n",
b78cd169 2878 atmel_port->fifo_size);
b5199d46 2879 dev_dbg(&pdev->dev, "RTS High Threshold : %2u data\n",
b78cd169 2880 atmel_port->rts_high);
b5199d46 2881 dev_dbg(&pdev->dev, "RTS Low Threshold : %2u data\n",
b78cd169 2882 atmel_port->rts_low);
b5199d46
CP		 2883}
2884
9671f099 2885static int atmel_serial_probe(struct platform_device *pdev)
1e6c9c28 2886{
b78cd169 2887 struct atmel_uart_port *atmel_port;
c24d2531 2888 struct device_node *np = pdev->dev.parent->of_node;
1ecc26bd 2889 void *data;
8d41ab87 2890 int ret;
bd737f87 2891 bool rs485_enabled;
1e6c9c28 2892
9d09daf8 2893 BUILD_BUG_ON(ATMEL_SERIAL_RINGSIZE & (ATMEL_SERIAL_RINGSIZE - 1));
1ecc26bd 2894
c24d2531
RP		 2895 /*
2896 * In device tree there is no node with "atmel,at91rm9200-usart-serial"
2897 * as compatible string. This driver is probed by at91-usart mfd driver
2898 * which is just a wrapper over the atmel_serial driver and
2899 * spi-at91-usart driver. All attributes needed by this driver are
2900 * found in of_node of parent.
2901 */
2902 pdev->dev.of_node = np;
2903
92c8f7c0 2904 ret = of_alias_get_id(np, "serial");
4cbf9f48 2905 if (ret < 0)
5fbe46b6 2906 /* port id not found in platform data nor device-tree aliases:
4cbf9f48 2907 * auto-enumerate it */
503bded9 2908 ret = find_first_zero_bit(atmel_ports_in_use, ATMEL_MAX_UART);
4cbf9f48 2909
503bded9 2910 if (ret >= ATMEL_MAX_UART) {
4cbf9f48
NF		 2911 ret = -ENODEV;
2912 goto err;
2913 }
2914
503bded9 2915 if (test_and_set_bit(ret, atmel_ports_in_use)) {
4cbf9f48
NF		 2916 /* port already in use */
2917 ret = -EBUSY;
2918 goto err;
2919 }
2920
b78cd169
JA		 2921 atmel_port = &atmel_ports[ret];
2922 atmel_port->backup_imr = 0;
2923 atmel_port->uart.line = ret;
2924 atmel_serial_probe_fifos(atmel_port, pdev);
e0b0baad 2925
98f2082c 2926 atomic_set(&atmel_port->tasklet_shutdown, 0);
b78cd169 2927 spin_lock_init(&atmel_port->lock_suspended);
2c7af5ba 2928
b78cd169 2929 ret = atmel_init_port(atmel_port, pdev);
91f8c2d8 2930 if (ret)
6fbb9bdf 2931 goto err_clear_bit;
1e6c9c28 2932
b78cd169
JA		 2933 atmel_port->gpios = mctrl_gpio_init(&atmel_port->uart, 0);
2934 if (IS_ERR(atmel_port->gpios)) {
2935 ret = PTR_ERR(atmel_port->gpios);
18dfef9c
UKK		 2936 goto err_clear_bit;
2937 }
2938
b78cd169 2939 if (!atmel_use_pdc_rx(&atmel_port->uart)) {
a6670615 2940 ret = -ENOMEM;
6da2ec56
KC		 2941 data = kmalloc_array(ATMEL_SERIAL_RINGSIZE,
2942 sizeof(struct atmel_uart_char),
2943 GFP_KERNEL);
a6670615
CC		 2944 if (!data)
2945 goto err_alloc_ring;
b78cd169 2946 atmel_port->rx_ring.buf = data;
a6670615 2947 }
1ecc26bd 2948
b78cd169 2949 rs485_enabled = atmel_port->uart.rs485.flags & SER_RS485_ENABLED;
bd737f87 2950
b78cd169 2951 ret = uart_add_one_port(&atmel_uart, &atmel_port->uart);
dfa7f343
HS		 2952 if (ret)
2953 goto err_add_port;
2954
8da14b5f 2955#ifdef CONFIG_SERIAL_ATMEL_CONSOLE
b78cd169 2956 if (atmel_is_console_port(&atmel_port->uart)
06a7f058
DB		 2957 && ATMEL_CONSOLE_DEVICE->flags & CON_ENABLED) {
2958 /*
2959 * The serial core enabled the clock for us, so undo
91f8c2d8 2960 * the clk_prepare_enable() in atmel_console_setup()
06a7f058 2961 */
b78cd169 2962 clk_disable_unprepare(atmel_port->clk);
06a7f058 2963 }
8da14b5f 2964#endif
06a7f058 2965
dfa7f343 2966 device_init_wakeup(&pdev->dev, 1);
b78cd169 2967 platform_set_drvdata(pdev, atmel_port);
dfa7f343 2968
d4f64187
CP		 2969 /*
2970 * The peripheral clock has been disabled by atmel_init_port():
2971 * enable it before accessing I/O registers
2972 */
b78cd169 2973 clk_prepare_enable(atmel_port->clk);
d4f64187 2974
bd737f87 2975 if (rs485_enabled) {
b78cd169 2976 atmel_uart_writel(&atmel_port->uart, ATMEL_US_MR,
4e7decda 2977 ATMEL_US_USMODE_NORMAL);
b78cd169
JA		 2978 atmel_uart_writel(&atmel_port->uart, ATMEL_US_CR,
2979 ATMEL_US_RTSEN);
5dfbd1d7
CS		 2980 }
2981
055560b0
ES		 2982 /*
2983 * Get port name of usart or uart
2984 */
b78cd169 2985 atmel_get_ip_name(&atmel_port->uart);
055560b0 2986
d4f64187
CP		 2987 /*
2988 * The peripheral clock can now safely be disabled till the port
2989 * is used
2990 */
b78cd169 2991 clk_disable_unprepare(atmel_port->clk);
d4f64187 2992
dfa7f343
HS		 2993 return 0;
2994
2995err_add_port:
b78cd169
JA		 2996 kfree(atmel_port->rx_ring.buf);
2997 atmel_port->rx_ring.buf = NULL;
1ecc26bd 2998err_alloc_ring:
b78cd169
JA		 2999 if (!atmel_is_console_port(&atmel_port->uart)) {
3000 clk_put(atmel_port->clk);
3001 atmel_port->clk = NULL;
afefc415 3002 }
6fbb9bdf 3003err_clear_bit:
b78cd169 3004 clear_bit(atmel_port->uart.line, atmel_ports_in_use);
4cbf9f48 3005err:
afefc415
AV		 3006 return ret;
3007}
3008
f4a8ab04
RI		 3009/*
3010 * Even if the driver is not modular, it makes sense to be able to
3011 * unbind a device: there can be many bound devices, and there are
3012 * situations where dynamic binding and unbinding can be useful.
3013 *
3014 * For example, a connected device can require a specific firmware update
3015 * protocol that needs bitbanging on IO lines, but use the regular serial
3016 * port in the normal case.
3017 */
3018static int atmel_serial_remove(struct platform_device *pdev)
3019{
3020 struct uart_port *port = platform_get_drvdata(pdev);
3021 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
3022 int ret = 0;
3023
00e8e658
NF		 3024 tasklet_kill(&atmel_port->tasklet_rx);
3025 tasklet_kill(&atmel_port->tasklet_tx);
f4a8ab04
RI		 3026
3027 device_init_wakeup(&pdev->dev, 0);
3028
3029 ret = uart_remove_one_port(&atmel_uart, port);
3030
3031 kfree(atmel_port->rx_ring.buf);
3032
3033 /* "port" is allocated statically, so we shouldn't free it */
3034
3035 clear_bit(port->line, atmel_ports_in_use);
3036
3037 clk_put(atmel_port->clk);
3038 atmel_port->clk = NULL;
c24d2531 3039 pdev->dev.of_node = NULL;
f4a8ab04
RI		 3040
3041 return ret;
3042}
3043
7192f92c
HS		 3044static struct platform_driver atmel_serial_driver = {
3045 .probe = atmel_serial_probe,
f4a8ab04 3046 .remove = atmel_serial_remove,
7192f92c
HS		 3047 .suspend = atmel_serial_suspend,
3048 .resume = atmel_serial_resume,
afefc415 3049 .driver = {
c24d2531 3050 .name = "atmel_usart_serial",
c39dfebc 3051 .of_match_table = of_match_ptr(atmel_serial_dt_ids),
afefc415
AV		 3052 },
3053};
3054
7192f92c 3055static int __init atmel_serial_init(void)
afefc415
AV		 3056{
3057 int ret;
3058
7192f92c 3059 ret = uart_register_driver(&atmel_uart);
afefc415
AV		 3060 if (ret)
3061 return ret;
3062
7192f92c 3063 ret = platform_driver_register(&atmel_serial_driver);
afefc415 3064 if (ret)
7192f92c 3065 uart_unregister_driver(&atmel_uart);
afefc415
AV		 3066
3067 return ret;
3068}
c39dfebc 3069device_initcall(atmel_serial_init);
Linux 6.x block layer and io_uring tree(s)