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serial: 8250: Add hardware dependency to RT288X option
[linux-2.6-block.git] / drivers / tty / serial / atmel_serial.c
CommitLineData
1e6c9c28 1/*
7192f92c 2 * Driver for Atmel AT91 / AT32 Serial ports
1e6c9c28
AV		 3 * Copyright (C) 2003 Rick Bronson
4 *
5 * Based on drivers/char/serial_sa1100.c, by Deep Blue Solutions Ltd.
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
7 *
a6670615
CC		 8 * DMA support added by Chip Coldwell.
9 *
1e6c9c28
AV		 10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 *
24 */
1e6c9c28
AV		 25#include <linux/tty.h>
26#include <linux/ioport.h>
27#include <linux/slab.h>
28#include <linux/init.h>
29#include <linux/serial.h>
afefc415 30#include <linux/clk.h>
1e6c9c28
AV		 31#include <linux/console.h>
32#include <linux/sysrq.h>
33#include <linux/tty_flip.h>
afefc415 34#include <linux/platform_device.h>
5fbe46b6
NF		 35#include <linux/of.h>
36#include <linux/of_device.h>
354e57f3 37#include <linux/of_gpio.h>
a6670615 38#include <linux/dma-mapping.h>
6b997bab 39#include <linux/dmaengine.h>
93a3ddc2 40#include <linux/atmel_pdc.h>
fa3218d8 41#include <linux/atmel_serial.h>
e8faff73 42#include <linux/uaccess.h>
bcd2360c 43#include <linux/platform_data/atmel.h>
2e68c22f 44#include <linux/timer.h>
354e57f3 45#include <linux/gpio.h>
e0b0baad
RG		 46#include <linux/gpio/consumer.h>
47#include <linux/err.h>
ab5e4e41 48#include <linux/irq.h>
2c7af5ba 49#include <linux/suspend.h>
1e6c9c28
AV		 50
51#include <asm/io.h>
f7512e7c 52#include <asm/ioctls.h>
1e6c9c28 53
a6670615
CC		 54#define PDC_BUFFER_SIZE 512
55/* Revisit: We should calculate this based on the actual port settings */
56#define PDC_RX_TIMEOUT (3 * 10) /* 3 bytes */
57
b5199d46
CP		 58/* The minium number of data FIFOs should be able to contain */
59#define ATMEL_MIN_FIFO_SIZE 8
60/*
61 * These two offsets are substracted from the RX FIFO size to define the RTS
62 * high and low thresholds
63 */
64#define ATMEL_RTS_HIGH_OFFSET 16
65#define ATMEL_RTS_LOW_OFFSET 20
66
749c4e60 67#if defined(CONFIG_SERIAL_ATMEL_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
1e6c9c28
AV		 68#define SUPPORT_SYSRQ
69#endif
70
71#include <linux/serial_core.h>
72
e0b0baad
RG		 73#include "serial_mctrl_gpio.h"
74
e8faff73
CS		 75static void atmel_start_rx(struct uart_port *port);
76static void atmel_stop_rx(struct uart_port *port);
77
749c4e60 78#ifdef CONFIG_SERIAL_ATMEL_TTYAT
1e6c9c28
AV		 79
80/* Use device name ttyAT, major 204 and minor 154-169. This is necessary if we
81 * should coexist with the 8250 driver, such as if we have an external 16C550
82 * UART. */
7192f92c 83#define SERIAL_ATMEL_MAJOR 204
1e6c9c28 84#define MINOR_START 154
7192f92c 85#define ATMEL_DEVICENAME "ttyAT"
1e6c9c28
AV		 86
87#else
88
89/* Use device name ttyS, major 4, minor 64-68. This is the usual serial port
90 * name, but it is legally reserved for the 8250 driver. */
7192f92c 91#define SERIAL_ATMEL_MAJOR TTY_MAJOR
1e6c9c28 92#define MINOR_START 64
7192f92c 93#define ATMEL_DEVICENAME "ttyS"
1e6c9c28
AV		 94
95#endif
96
7192f92c 97#define ATMEL_ISR_PASS_LIMIT 256
1e6c9c28 98
a6670615
CC		 99struct atmel_dma_buffer {
100 unsigned char *buf;
101 dma_addr_t dma_addr;
102 unsigned int dma_size;
103 unsigned int ofs;
104};
105
1ecc26bd
RB		 106struct atmel_uart_char {
107 u16 status;
108 u16 ch;
109};
110
111#define ATMEL_SERIAL_RINGSIZE 1024
112
9af92fbf
AB		 113/*
114 * at91: 6 USARTs and one DBGU port (SAM9260)
115 * avr32: 4
116 */
117#define ATMEL_MAX_UART 7
118
afefc415
AV		 119/*
120 * We wrap our port structure around the generic uart_port.
121 */
7192f92c 122struct atmel_uart_port {
afefc415
AV		 123 struct uart_port uart; /* uart */
124 struct clk *clk; /* uart clock */
f05596db
AS		 125 int may_wakeup; /* cached value of device_may_wakeup for times we need to disable it */
126 u32 backup_imr; /* IMR saved during suspend */
9e6077bd 127 int break_active; /* break being received */
1ecc26bd 128
34df42f5 129 bool use_dma_rx; /* enable DMA receiver */
64e22ebe 130 bool use_pdc_rx; /* enable PDC receiver */
a6670615
CC		 131 short pdc_rx_idx; /* current PDC RX buffer */
132 struct atmel_dma_buffer pdc_rx[2]; /* PDC receier */
133
08f738be 134 bool use_dma_tx; /* enable DMA transmitter */
64e22ebe 135 bool use_pdc_tx; /* enable PDC transmitter */
a6670615
CC		 136 struct atmel_dma_buffer pdc_tx; /* PDC transmitter */
137
08f738be 138 spinlock_t lock_tx; /* port lock */
34df42f5 139 spinlock_t lock_rx; /* port lock */
08f738be 140 struct dma_chan *chan_tx;
34df42f5 141 struct dma_chan *chan_rx;
08f738be 142 struct dma_async_tx_descriptor *desc_tx;
34df42f5 143 struct dma_async_tx_descriptor *desc_rx;
08f738be 144 dma_cookie_t cookie_tx;
34df42f5 145 dma_cookie_t cookie_rx;
08f738be 146 struct scatterlist sg_tx;
34df42f5 147 struct scatterlist sg_rx;
1ecc26bd
RB		 148 struct tasklet_struct tasklet;
149 unsigned int irq_status;
150 unsigned int irq_status_prev;
d033e82d 151 unsigned int status_change;
5f258b3e 152 unsigned int tx_len;
1ecc26bd
RB		 153
154 struct circ_buf rx_ring;
e8faff73 155
e0b0baad 156 struct mctrl_gpios *gpios;
e8faff73 157 unsigned int tx_done_mask;
b5199d46
CP		 158 u32 fifo_size;
159 u32 rts_high;
160 u32 rts_low;
ab5e4e41 161 bool ms_irq_enabled;
4b769371
NF		 162 bool has_hw_timer;
163 struct timer_list uart_timer;
2c7af5ba
BB		 164
165 bool suspended;
166 unsigned int pending;
167 unsigned int pending_status;
168 spinlock_t lock_suspended;
169
a930e528
ES		 170 int (*prepare_rx)(struct uart_port *port);
171 int (*prepare_tx)(struct uart_port *port);
172 void (*schedule_rx)(struct uart_port *port);
173 void (*schedule_tx)(struct uart_port *port);
174 void (*release_rx)(struct uart_port *port);
175 void (*release_tx)(struct uart_port *port);
afefc415
AV		 176};
177
7192f92c 178static struct atmel_uart_port atmel_ports[ATMEL_MAX_UART];
503bded9 179static DECLARE_BITMAP(atmel_ports_in_use, ATMEL_MAX_UART);
afefc415 180
1e6c9c28 181#ifdef SUPPORT_SYSRQ
7192f92c 182static struct console atmel_console;
1e6c9c28
AV		 183#endif
184
5fbe46b6
NF		 185#if defined(CONFIG_OF)
186static const struct of_device_id atmel_serial_dt_ids[] = {
187 { .compatible = "atmel,at91rm9200-usart" },
188 { .compatible = "atmel,at91sam9260-usart" },
189 { /* sentinel */ }
190};
5fbe46b6
NF		 191#endif
192
c811ab8c
HS		 193static inline struct atmel_uart_port *
194to_atmel_uart_port(struct uart_port *uart)
195{
196 return container_of(uart, struct atmel_uart_port, uart);
197}
198
4e7decda
CP		 199static inline u32 atmel_uart_readl(struct uart_port *port, u32 reg)
200{
201 return __raw_readl(port->membase + reg);
202}
203
204static inline void atmel_uart_writel(struct uart_port *port, u32 reg, u32 value)
205{
206 __raw_writel(value, port->membase + reg);
207}
208
a6499435
CP		 209#ifdef CONFIG_AVR32
210
211/* AVR32 cannot handle 8 or 16bit I/O accesses but only 32bit I/O accesses */
212static inline u8 atmel_uart_read_char(struct uart_port *port)
213{
214 return __raw_readl(port->membase + ATMEL_US_RHR);
215}
216
217static inline void atmel_uart_write_char(struct uart_port *port, u8 value)
b5199d46 218{
a6499435 219 __raw_writel(value, port->membase + ATMEL_US_THR);
b5199d46
CP		 220}
221
a6499435
CP		 222#else
223
224static inline u8 atmel_uart_read_char(struct uart_port *port)
b5199d46 225{
a6499435 226 return __raw_readb(port->membase + ATMEL_US_RHR);
b5199d46
CP		 227}
228
a6499435
CP		 229static inline void atmel_uart_write_char(struct uart_port *port, u8 value)
230{
231 __raw_writeb(value, port->membase + ATMEL_US_THR);
232}
233
234#endif
235
a6670615 236#ifdef CONFIG_SERIAL_ATMEL_PDC
64e22ebe 237static bool atmel_use_pdc_rx(struct uart_port *port)
a6670615 238{
c811ab8c 239 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
a6670615 240
64e22ebe 241 return atmel_port->use_pdc_rx;
a6670615
CC		 242}
243
64e22ebe 244static bool atmel_use_pdc_tx(struct uart_port *port)
a6670615 245{
c811ab8c 246 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
a6670615 247
64e22ebe 248 return atmel_port->use_pdc_tx;
a6670615
CC		 249}
250#else
64e22ebe 251static bool atmel_use_pdc_rx(struct uart_port *port)
a6670615
CC		 252{
253 return false;
254}
255
64e22ebe 256static bool atmel_use_pdc_tx(struct uart_port *port)
a6670615
CC		 257{
258 return false;
259}
260#endif
261
08f738be
ES		 262static bool atmel_use_dma_tx(struct uart_port *port)
263{
264 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
265
266 return atmel_port->use_dma_tx;
267}
268
34df42f5
ES		 269static bool atmel_use_dma_rx(struct uart_port *port)
270{
271 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
272
273 return atmel_port->use_dma_rx;
274}
275
e0b0baad
RG		 276static unsigned int atmel_get_lines_status(struct uart_port *port)
277{
278 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
279 unsigned int status, ret = 0;
280
4e7decda 281 status = atmel_uart_readl(port, ATMEL_US_CSR);
e0b0baad
RG		 282
283 mctrl_gpio_get(atmel_port->gpios, &ret);
284
285 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios,
286 UART_GPIO_CTS))) {
287 if (ret & TIOCM_CTS)
288 status &= ~ATMEL_US_CTS;
289 else
290 status |= ATMEL_US_CTS;
291 }
292
293 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios,
294 UART_GPIO_DSR))) {
295 if (ret & TIOCM_DSR)
296 status &= ~ATMEL_US_DSR;
297 else
298 status |= ATMEL_US_DSR;
299 }
300
301 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios,
302 UART_GPIO_RI))) {
303 if (ret & TIOCM_RI)
304 status &= ~ATMEL_US_RI;
305 else
306 status |= ATMEL_US_RI;
307 }
308
309 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios,
310 UART_GPIO_DCD))) {
311 if (ret & TIOCM_CD)
312 status &= ~ATMEL_US_DCD;
313 else
314 status |= ATMEL_US_DCD;
315 }
316
317 return status;
318}
319
e8faff73 320/* Enable or disable the rs485 support */
13bd3e6f
RRD		 321static int atmel_config_rs485(struct uart_port *port,
322 struct serial_rs485 *rs485conf)
e8faff73
CS		 323{
324 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
325 unsigned int mode;
e8faff73
CS		 326
327 /* Disable interrupts */
4e7decda 328 atmel_uart_writel(port, ATMEL_US_IDR, atmel_port->tx_done_mask);
e8faff73 329
4e7decda 330 mode = atmel_uart_readl(port, ATMEL_US_MR);
e8faff73
CS		 331
332 /* Resetting serial mode to RS232 (0x0) */
333 mode &= ~ATMEL_US_USMODE;
334
13bd3e6f 335 port->rs485 = *rs485conf;
e8faff73
CS		 336
337 if (rs485conf->flags & SER_RS485_ENABLED) {
338 dev_dbg(port->dev, "Setting UART to RS485\n");
339 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY;
4e7decda
CP		 340 atmel_uart_writel(port, ATMEL_US_TTGR,
341 rs485conf->delay_rts_after_send);
e8faff73
CS		 342 mode |= ATMEL_US_USMODE_RS485;
343 } else {
344 dev_dbg(port->dev, "Setting UART to RS232\n");
64e22ebe 345 if (atmel_use_pdc_tx(port))
e8faff73
CS		 346 atmel_port->tx_done_mask = ATMEL_US_ENDTX |
347 ATMEL_US_TXBUFE;
348 else
349 atmel_port->tx_done_mask = ATMEL_US_TXRDY;
350 }
4e7decda 351 atmel_uart_writel(port, ATMEL_US_MR, mode);
e8faff73
CS		 352
353 /* Enable interrupts */
4e7decda 354 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->tx_done_mask);
e8faff73 355
13bd3e6f 356 return 0;
e8faff73
CS		 357}
358
1e6c9c28
AV		 359/*
360 * Return TIOCSER_TEMT when transmitter FIFO and Shift register is empty.
361 */
7192f92c 362static u_int atmel_tx_empty(struct uart_port *port)
1e6c9c28 363{
4e7decda
CP		 364 return (atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXEMPTY) ?
365 TIOCSER_TEMT :
366 0;
1e6c9c28
AV		 367}
368
369/*
370 * Set state of the modem control output lines
371 */
7192f92c 372static void atmel_set_mctrl(struct uart_port *port, u_int mctrl)
1e6c9c28
AV		 373{
374 unsigned int control = 0;
4e7decda 375 unsigned int mode = atmel_uart_readl(port, ATMEL_US_MR);
1cf6e8fc 376 unsigned int rts_paused, rts_ready;
e8faff73 377 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1e6c9c28 378
1cf6e8fc
CP		 379 /* override mode to RS485 if needed, otherwise keep the current mode */
380 if (port->rs485.flags & SER_RS485_ENABLED) {
4e7decda
CP		 381 atmel_uart_writel(port, ATMEL_US_TTGR,
382 port->rs485.delay_rts_after_send);
1cf6e8fc
CP		 383 mode &= ~ATMEL_US_USMODE;
384 mode |= ATMEL_US_USMODE_RS485;
385 }
386
387 /* set the RTS line state according to the mode */
388 if ((mode & ATMEL_US_USMODE) == ATMEL_US_USMODE_HWHS) {
389 /* force RTS line to high level */
390 rts_paused = ATMEL_US_RTSEN;
391
392 /* give the control of the RTS line back to the hardware */
393 rts_ready = ATMEL_US_RTSDIS;
394 } else {
395 /* force RTS line to high level */
396 rts_paused = ATMEL_US_RTSDIS;
397
398 /* force RTS line to low level */
399 rts_ready = ATMEL_US_RTSEN;
400 }
401
1e6c9c28 402 if (mctrl & TIOCM_RTS)
1cf6e8fc 403 control |= rts_ready;
1e6c9c28 404 else
1cf6e8fc 405 control |= rts_paused;
1e6c9c28
AV		 406
407 if (mctrl & TIOCM_DTR)
7192f92c 408 control |= ATMEL_US_DTREN;
1e6c9c28 409 else
7192f92c 410 control |= ATMEL_US_DTRDIS;
1e6c9c28 411
4e7decda 412 atmel_uart_writel(port, ATMEL_US_CR, control);
afefc415 413
e0b0baad
RG		 414 mctrl_gpio_set(atmel_port->gpios, mctrl);
415
afefc415 416 /* Local loopback mode? */
1cf6e8fc 417 mode &= ~ATMEL_US_CHMODE;
afefc415 418 if (mctrl & TIOCM_LOOP)
7192f92c 419 mode |= ATMEL_US_CHMODE_LOC_LOOP;
afefc415 420 else
7192f92c 421 mode |= ATMEL_US_CHMODE_NORMAL;
e8faff73 422
4e7decda 423 atmel_uart_writel(port, ATMEL_US_MR, mode);
1e6c9c28
AV		 424}
425
426/*
427 * Get state of the modem control input lines
428 */
7192f92c 429static u_int atmel_get_mctrl(struct uart_port *port)
1e6c9c28 430{
e0b0baad
RG		 431 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
432 unsigned int ret = 0, status;
1e6c9c28 433
4e7decda 434 status = atmel_uart_readl(port, ATMEL_US_CSR);
1e6c9c28
AV		 435
436 /*
437 * The control signals are active low.
438 */
7192f92c 439 if (!(status & ATMEL_US_DCD))
1e6c9c28 440 ret |= TIOCM_CD;
7192f92c 441 if (!(status & ATMEL_US_CTS))
1e6c9c28 442 ret |= TIOCM_CTS;
7192f92c 443 if (!(status & ATMEL_US_DSR))
1e6c9c28 444 ret |= TIOCM_DSR;
7192f92c 445 if (!(status & ATMEL_US_RI))
1e6c9c28
AV		 446 ret |= TIOCM_RI;
447
e0b0baad 448 return mctrl_gpio_get(atmel_port->gpios, &ret);
1e6c9c28
AV		 449}
450
451/*
452 * Stop transmitting.
453 */
7192f92c 454static void atmel_stop_tx(struct uart_port *port)
1e6c9c28 455{
e8faff73
CS		 456 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
457
64e22ebe 458 if (atmel_use_pdc_tx(port)) {
a6670615 459 /* disable PDC transmit */
4e7decda 460 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS);
e8faff73
CS		 461 }
462 /* Disable interrupts */
4e7decda 463 atmel_uart_writel(port, ATMEL_US_IDR, atmel_port->tx_done_mask);
e8faff73 464
13bd3e6f
RRD		 465 if ((port->rs485.flags & SER_RS485_ENABLED) &&
466 !(port->rs485.flags & SER_RS485_RX_DURING_TX))
e8faff73 467 atmel_start_rx(port);
1e6c9c28
AV		 468}
469
470/*
471 * Start transmitting.
472 */
7192f92c 473static void atmel_start_tx(struct uart_port *port)
1e6c9c28 474{
e8faff73
CS		 475 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
476
64e22ebe 477 if (atmel_use_pdc_tx(port)) {
4e7decda 478 if (atmel_uart_readl(port, ATMEL_PDC_PTSR) & ATMEL_PDC_TXTEN)
a6670615
CC		 479 /* The transmitter is already running. Yes, we
480 really need this.*/
481 return;
482
13bd3e6f
RRD		 483 if ((port->rs485.flags & SER_RS485_ENABLED) &&
484 !(port->rs485.flags & SER_RS485_RX_DURING_TX))
e8faff73
CS		 485 atmel_stop_rx(port);
486
a6670615 487 /* re-enable PDC transmit */
4e7decda 488 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
e8faff73
CS		 489 }
490 /* Enable interrupts */
4e7decda 491 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->tx_done_mask);
e8faff73
CS		 492}
493
494/*
495 * start receiving - port is in process of being opened.
496 */
497static void atmel_start_rx(struct uart_port *port)
498{
4e7decda
CP		 499 /* reset status and receiver */
500 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
e8faff73 501
4e7decda 502 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RXEN);
57c36868 503
64e22ebe 504 if (atmel_use_pdc_rx(port)) {
e8faff73 505 /* enable PDC controller */
4e7decda
CP		 506 atmel_uart_writel(port, ATMEL_US_IER,
507 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT |
508 port->read_status_mask);
509 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN);
e8faff73 510 } else {
4e7decda 511 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_RXRDY);
e8faff73 512 }
1e6c9c28
AV		 513}
514
515/*
516 * Stop receiving - port is in process of being closed.
517 */
7192f92c 518static void atmel_stop_rx(struct uart_port *port)
1e6c9c28 519{
4e7decda 520 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RXDIS);
57c36868 521
64e22ebe 522 if (atmel_use_pdc_rx(port)) {
a6670615 523 /* disable PDC receive */
4e7decda
CP		 524 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS);
525 atmel_uart_writel(port, ATMEL_US_IDR,
526 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT |
527 port->read_status_mask);
e8faff73 528 } else {
4e7decda 529 atmel_uart_writel(port, ATMEL_US_IDR, ATMEL_US_RXRDY);
e8faff73 530 }
1e6c9c28
AV		 531}
532
533/*
534 * Enable modem status interrupts
535 */
7192f92c 536static void atmel_enable_ms(struct uart_port *port)
1e6c9c28 537{
ab5e4e41
RG		 538 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
539 uint32_t ier = 0;
540
541 /*
542 * Interrupt should not be enabled twice
543 */
544 if (atmel_port->ms_irq_enabled)
545 return;
546
547 atmel_port->ms_irq_enabled = true;
548
18dfef9c 549 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_CTS))
ab5e4e41
RG		 550 ier |= ATMEL_US_CTSIC;
551
18dfef9c 552 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DSR))
ab5e4e41
RG		 553 ier |= ATMEL_US_DSRIC;
554
18dfef9c 555 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_RI))
ab5e4e41
RG		 556 ier |= ATMEL_US_RIIC;
557
18dfef9c 558 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DCD))
ab5e4e41
RG		 559 ier |= ATMEL_US_DCDIC;
560
4e7decda 561 atmel_uart_writel(port, ATMEL_US_IER, ier);
18dfef9c
UKK		 562
563 mctrl_gpio_enable_ms(atmel_port->gpios);
1e6c9c28
AV		 564}
565
35b675b9
RG		 566/*
567 * Disable modem status interrupts
568 */
569static void atmel_disable_ms(struct uart_port *port)
570{
571 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
572 uint32_t idr = 0;
573
574 /*
575 * Interrupt should not be disabled twice
576 */
577 if (!atmel_port->ms_irq_enabled)
578 return;
579
580 atmel_port->ms_irq_enabled = false;
581
18dfef9c
UKK		 582 mctrl_gpio_disable_ms(atmel_port->gpios);
583
584 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_CTS))
35b675b9
RG		 585 idr |= ATMEL_US_CTSIC;
586
18dfef9c 587 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DSR))
35b675b9
RG		 588 idr |= ATMEL_US_DSRIC;
589
18dfef9c 590 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_RI))
35b675b9
RG		 591 idr |= ATMEL_US_RIIC;
592
18dfef9c 593 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DCD))
35b675b9
RG		 594 idr |= ATMEL_US_DCDIC;
595
4e7decda 596 atmel_uart_writel(port, ATMEL_US_IDR, idr);
35b675b9
RG		 597}
598
1e6c9c28
AV		 599/*
600 * Control the transmission of a break signal
601 */
7192f92c 602static void atmel_break_ctl(struct uart_port *port, int break_state)
1e6c9c28
AV		 603{
604 if (break_state != 0)
4e7decda
CP		 605 /* start break */
606 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTBRK);
1e6c9c28 607 else
4e7decda
CP		 608 /* stop break */
609 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STPBRK);
1e6c9c28
AV		 610}
611
1ecc26bd
RB		 612/*
613 * Stores the incoming character in the ring buffer
614 */
615static void
616atmel_buffer_rx_char(struct uart_port *port, unsigned int status,
617 unsigned int ch)
618{
c811ab8c 619 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1ecc26bd
RB		 620 struct circ_buf *ring = &atmel_port->rx_ring;
621 struct atmel_uart_char *c;
622
623 if (!CIRC_SPACE(ring->head, ring->tail, ATMEL_SERIAL_RINGSIZE))
624 /* Buffer overflow, ignore char */
625 return;
626
627 c = &((struct atmel_uart_char *)ring->buf)[ring->head];
628 c->status = status;
629 c->ch = ch;
630
631 /* Make sure the character is stored before we update head. */
632 smp_wmb();
633
634 ring->head = (ring->head + 1) & (ATMEL_SERIAL_RINGSIZE - 1);
635}
636
a6670615
CC		 637/*
638 * Deal with parity, framing and overrun errors.
639 */
640static void atmel_pdc_rxerr(struct uart_port *port, unsigned int status)
641{
642 /* clear error */
4e7decda 643 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
a6670615
CC		 644
645 if (status & ATMEL_US_RXBRK) {
646 /* ignore side-effect */
647 status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME);
648 port->icount.brk++;
649 }
650 if (status & ATMEL_US_PARE)
651 port->icount.parity++;
652 if (status & ATMEL_US_FRAME)
653 port->icount.frame++;
654 if (status & ATMEL_US_OVRE)
655 port->icount.overrun++;
656}
657
1e6c9c28
AV		 658/*
659 * Characters received (called from interrupt handler)
660 */
7d12e780 661static void atmel_rx_chars(struct uart_port *port)
1e6c9c28 662{
c811ab8c 663 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1ecc26bd 664 unsigned int status, ch;
1e6c9c28 665
4e7decda 666 status = atmel_uart_readl(port, ATMEL_US_CSR);
7192f92c 667 while (status & ATMEL_US_RXRDY) {
a6499435 668 ch = atmel_uart_read_char(port);
1e6c9c28 669
1e6c9c28
AV		 670 /*
671 * note that the error handling code is
672 * out of the main execution path
673 */
9e6077bd
HS		 674 if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME
675 | ATMEL_US_OVRE | ATMEL_US_RXBRK)
676 || atmel_port->break_active)) {
1ecc26bd 677
b843aa21 678 /* clear error */
4e7decda 679 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
1ecc26bd 680
9e6077bd
HS		 681 if (status & ATMEL_US_RXBRK
682 && !atmel_port->break_active) {
9e6077bd 683 atmel_port->break_active = 1;
4e7decda
CP		 684 atmel_uart_writel(port, ATMEL_US_IER,
685 ATMEL_US_RXBRK);
9e6077bd
HS		 686 } else {
687 /*
688 * This is either the end-of-break
689 * condition or we've received at
690 * least one character without RXBRK
691 * being set. In both cases, the next
692 * RXBRK will indicate start-of-break.
693 */
4e7decda
CP		 694 atmel_uart_writel(port, ATMEL_US_IDR,
695 ATMEL_US_RXBRK);
9e6077bd
HS		 696 status &= ~ATMEL_US_RXBRK;
697 atmel_port->break_active = 0;
afefc415 698 }
1e6c9c28
AV		 699 }
700
1ecc26bd 701 atmel_buffer_rx_char(port, status, ch);
4e7decda 702 status = atmel_uart_readl(port, ATMEL_US_CSR);
1e6c9c28
AV		 703 }
704
1ecc26bd 705 tasklet_schedule(&atmel_port->tasklet);
1e6c9c28
AV		 706}
707
708/*
1ecc26bd
RB		 709 * Transmit characters (called from tasklet with TXRDY interrupt
710 * disabled)
1e6c9c28 711 */
7192f92c 712static void atmel_tx_chars(struct uart_port *port)
1e6c9c28 713{
ebd2c8f6 714 struct circ_buf *xmit = &port->state->xmit;
e8faff73 715 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1e6c9c28 716
4e7decda
CP		 717 if (port->x_char &&
718 (atmel_uart_readl(port, ATMEL_US_CSR) & atmel_port->tx_done_mask)) {
a6499435 719 atmel_uart_write_char(port, port->x_char);
1e6c9c28
AV		 720 port->icount.tx++;
721 port->x_char = 0;
1e6c9c28 722 }
1ecc26bd 723 if (uart_circ_empty(xmit) || uart_tx_stopped(port))
1e6c9c28 724 return;
1e6c9c28 725
4e7decda
CP		 726 while (atmel_uart_readl(port, ATMEL_US_CSR) &
727 atmel_port->tx_done_mask) {
a6499435 728 atmel_uart_write_char(port, xmit->buf[xmit->tail]);
1e6c9c28
AV		 729 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
730 port->icount.tx++;
731 if (uart_circ_empty(xmit))
732 break;
733 }
734
735 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
736 uart_write_wakeup(port);
737
1ecc26bd 738 if (!uart_circ_empty(xmit))
e8faff73 739 /* Enable interrupts */
4e7decda
CP		 740 atmel_uart_writel(port, ATMEL_US_IER,
741 atmel_port->tx_done_mask);
1e6c9c28
AV		 742}
743
08f738be
ES		 744static void atmel_complete_tx_dma(void *arg)
745{
746 struct atmel_uart_port *atmel_port = arg;
747 struct uart_port *port = &atmel_port->uart;
748 struct circ_buf *xmit = &port->state->xmit;
749 struct dma_chan *chan = atmel_port->chan_tx;
750 unsigned long flags;
751
752 spin_lock_irqsave(&port->lock, flags);
753
754 if (chan)
755 dmaengine_terminate_all(chan);
5f258b3e 756 xmit->tail += atmel_port->tx_len;
08f738be
ES		 757 xmit->tail &= UART_XMIT_SIZE - 1;
758
5f258b3e 759 port->icount.tx += atmel_port->tx_len;
08f738be
ES		 760
761 spin_lock_irq(&atmel_port->lock_tx);
762 async_tx_ack(atmel_port->desc_tx);
763 atmel_port->cookie_tx = -EINVAL;
764 atmel_port->desc_tx = NULL;
765 spin_unlock_irq(&atmel_port->lock_tx);
766
767 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
768 uart_write_wakeup(port);
769
1842dc2e
CP		 770 /*
771 * xmit is a circular buffer so, if we have just send data from
772 * xmit->tail to the end of xmit->buf, now we have to transmit the
773 * remaining data from the beginning of xmit->buf to xmit->head.
774 */
08f738be
ES		 775 if (!uart_circ_empty(xmit))
776 tasklet_schedule(&atmel_port->tasklet);
777
778 spin_unlock_irqrestore(&port->lock, flags);
779}
780
781static void atmel_release_tx_dma(struct uart_port *port)
782{
783 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
784 struct dma_chan *chan = atmel_port->chan_tx;
785
786 if (chan) {
787 dmaengine_terminate_all(chan);
788 dma_release_channel(chan);
789 dma_unmap_sg(port->dev, &atmel_port->sg_tx, 1,
48479148 790 DMA_TO_DEVICE);
08f738be
ES		 791 }
792
793 atmel_port->desc_tx = NULL;
794 atmel_port->chan_tx = NULL;
795 atmel_port->cookie_tx = -EINVAL;
796}
797
798/*
799 * Called from tasklet with TXRDY interrupt is disabled.
800 */
801static void atmel_tx_dma(struct uart_port *port)
802{
803 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
804 struct circ_buf *xmit = &port->state->xmit;
805 struct dma_chan *chan = atmel_port->chan_tx;
806 struct dma_async_tx_descriptor *desc;
5f258b3e
CP		 807 struct scatterlist sgl[2], *sg, *sg_tx = &atmel_port->sg_tx;
808 unsigned int tx_len, part1_len, part2_len, sg_len;
809 dma_addr_t phys_addr;
08f738be
ES		 810
811 /* Make sure we have an idle channel */
812 if (atmel_port->desc_tx != NULL)
813 return;
814
815 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) {
816 /*
817 * DMA is idle now.
818 * Port xmit buffer is already mapped,
819 * and it is one page... Just adjust
820 * offsets and lengths. Since it is a circular buffer,
821 * we have to transmit till the end, and then the rest.
822 * Take the port lock to get a
823 * consistent xmit buffer state.
824 */
5f258b3e
CP		 825 tx_len = CIRC_CNT_TO_END(xmit->head,
826 xmit->tail,
827 UART_XMIT_SIZE);
828
829 if (atmel_port->fifo_size) {
830 /* multi data mode */
831 part1_len = (tx_len & ~0x3); /* DWORD access */
832 part2_len = (tx_len & 0x3); /* BYTE access */
833 } else {
834 /* single data (legacy) mode */
835 part1_len = 0;
836 part2_len = tx_len; /* BYTE access only */
837 }
838
839 sg_init_table(sgl, 2);
840 sg_len = 0;
841 phys_addr = sg_dma_address(sg_tx) + xmit->tail;
842 if (part1_len) {
843 sg = &sgl[sg_len++];
844 sg_dma_address(sg) = phys_addr;
845 sg_dma_len(sg) = part1_len;
846
847 phys_addr += part1_len;
848 }
849
850 if (part2_len) {
851 sg = &sgl[sg_len++];
852 sg_dma_address(sg) = phys_addr;
853 sg_dma_len(sg) = part2_len;
854 }
855
856 /*
857 * save tx_len so atmel_complete_tx_dma() will increase
858 * xmit->tail correctly
859 */
860 atmel_port->tx_len = tx_len;
08f738be
ES		 861
862 desc = dmaengine_prep_slave_sg(chan,
5f258b3e
CP		 863 sgl,
864 sg_len,
1842dc2e
CP		 865 DMA_MEM_TO_DEV,
866 DMA_PREP_INTERRUPT |
867 DMA_CTRL_ACK);
08f738be
ES		 868 if (!desc) {
869 dev_err(port->dev, "Failed to send via dma!\n");
870 return;
871 }
872
5f258b3e 873 dma_sync_sg_for_device(port->dev, sg_tx, 1, DMA_TO_DEVICE);
08f738be
ES		 874
875 atmel_port->desc_tx = desc;
876 desc->callback = atmel_complete_tx_dma;
877 desc->callback_param = atmel_port;
878 atmel_port->cookie_tx = dmaengine_submit(desc);
879
880 } else {
13bd3e6f 881 if (port->rs485.flags & SER_RS485_ENABLED) {
08f738be
ES		 882 /* DMA done, stop TX, start RX for RS485 */
883 atmel_start_rx(port);
884 }
885 }
886
887 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
888 uart_write_wakeup(port);
889}
890
891static int atmel_prepare_tx_dma(struct uart_port *port)
892{
893 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
894 dma_cap_mask_t mask;
895 struct dma_slave_config config;
896 int ret, nent;
897
898 dma_cap_zero(mask);
899 dma_cap_set(DMA_SLAVE, mask);
900
901 atmel_port->chan_tx = dma_request_slave_channel(port->dev, "tx");
902 if (atmel_port->chan_tx == NULL)
903 goto chan_err;
904 dev_info(port->dev, "using %s for tx DMA transfers\n",
905 dma_chan_name(atmel_port->chan_tx));
906
907 spin_lock_init(&atmel_port->lock_tx);
908 sg_init_table(&atmel_port->sg_tx, 1);
909 /* UART circular tx buffer is an aligned page. */
2c277054 910 BUG_ON(!PAGE_ALIGNED(port->state->xmit.buf));
08f738be
ES		 911 sg_set_page(&atmel_port->sg_tx,
912 virt_to_page(port->state->xmit.buf),
913 UART_XMIT_SIZE,
c8d1f022 914 (unsigned long)port->state->xmit.buf & ~PAGE_MASK);
08f738be
ES		 915 nent = dma_map_sg(port->dev,
916 &atmel_port->sg_tx,
917 1,
48479148 918 DMA_TO_DEVICE);
08f738be
ES		 919
920 if (!nent) {
921 dev_dbg(port->dev, "need to release resource of dma\n");
922 goto chan_err;
923 } else {
c8d1f022 924 dev_dbg(port->dev, "%s: mapped %d@%p to %pad\n", __func__,
08f738be
ES		 925 sg_dma_len(&atmel_port->sg_tx),
926 port->state->xmit.buf,
c8d1f022 927 &sg_dma_address(&atmel_port->sg_tx));
08f738be
ES		 928 }
929
930 /* Configure the slave DMA */
931 memset(&config, 0, sizeof(config));
932 config.direction = DMA_MEM_TO_DEV;
5f258b3e
CP		 933 config.dst_addr_width = (atmel_port->fifo_size) ?
934 DMA_SLAVE_BUSWIDTH_4_BYTES :
935 DMA_SLAVE_BUSWIDTH_1_BYTE;
08f738be 936 config.dst_addr = port->mapbase + ATMEL_US_THR;
a8d4e016 937 config.dst_maxburst = 1;
08f738be 938
5483c10e
MR		 939 ret = dmaengine_slave_config(atmel_port->chan_tx,
940 &config);
08f738be
ES		 941 if (ret) {
942 dev_err(port->dev, "DMA tx slave configuration failed\n");
943 goto chan_err;
944 }
945
946 return 0;
947
948chan_err:
949 dev_err(port->dev, "TX channel not available, switch to pio\n");
950 atmel_port->use_dma_tx = 0;
951 if (atmel_port->chan_tx)
952 atmel_release_tx_dma(port);
953 return -EINVAL;
954}
955
34df42f5
ES		 956static void atmel_complete_rx_dma(void *arg)
957{
958 struct uart_port *port = arg;
959 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
960
961 tasklet_schedule(&atmel_port->tasklet);
962}
963
964static void atmel_release_rx_dma(struct uart_port *port)
965{
966 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
967 struct dma_chan *chan = atmel_port->chan_rx;
968
969 if (chan) {
970 dmaengine_terminate_all(chan);
971 dma_release_channel(chan);
972 dma_unmap_sg(port->dev, &atmel_port->sg_rx, 1,
48479148 973 DMA_FROM_DEVICE);
34df42f5
ES		 974 }
975
976 atmel_port->desc_rx = NULL;
977 atmel_port->chan_rx = NULL;
978 atmel_port->cookie_rx = -EINVAL;
979}
980
981static void atmel_rx_from_dma(struct uart_port *port)
982{
983 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
66f37aaf 984 struct tty_port *tport = &port->state->port;
34df42f5
ES		 985 struct circ_buf *ring = &atmel_port->rx_ring;
986 struct dma_chan *chan = atmel_port->chan_rx;
987 struct dma_tx_state state;
988 enum dma_status dmastat;
66f37aaf 989 size_t count;
34df42f5
ES		 990
991
992 /* Reset the UART timeout early so that we don't miss one */
4e7decda 993 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
34df42f5
ES		 994 dmastat = dmaengine_tx_status(chan,
995 atmel_port->cookie_rx,
996 &state);
997 /* Restart a new tasklet if DMA status is error */
998 if (dmastat == DMA_ERROR) {
999 dev_dbg(port->dev, "Get residue error, restart tasklet\n");
4e7decda 1000 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_TIMEOUT);
34df42f5
ES		 1001 tasklet_schedule(&atmel_port->tasklet);
1002 return;
1003 }
34df42f5 1004
66f37aaf
CP		 1005 /* CPU claims ownership of RX DMA buffer */
1006 dma_sync_sg_for_cpu(port->dev,
1007 &atmel_port->sg_rx,
1008 1,
485819b5 1009 DMA_FROM_DEVICE);
66f37aaf
CP		 1010
1011 /*
1012 * ring->head points to the end of data already written by the DMA.
1013 * ring->tail points to the beginning of data to be read by the
1014 * framework.
1015 * The current transfer size should not be larger than the dma buffer
1016 * length.
1017 */
1018 ring->head = sg_dma_len(&atmel_port->sg_rx) - state.residue;
1019 BUG_ON(ring->head > sg_dma_len(&atmel_port->sg_rx));
34df42f5 1020 /*
66f37aaf
CP		 1021 * At this point ring->head may point to the first byte right after the
1022 * last byte of the dma buffer:
1023 * 0 <= ring->head <= sg_dma_len(&atmel_port->sg_rx)
1024 *
1025 * However ring->tail must always points inside the dma buffer:
1026 * 0 <= ring->tail <= sg_dma_len(&atmel_port->sg_rx) - 1
1027 *
1028 * Since we use a ring buffer, we have to handle the case
1029 * where head is lower than tail. In such a case, we first read from
1030 * tail to the end of the buffer then reset tail.
34df42f5 1031 */
66f37aaf
CP		 1032 if (ring->head < ring->tail) {
1033 count = sg_dma_len(&atmel_port->sg_rx) - ring->tail;
34df42f5 1034
66f37aaf
CP		 1035 tty_insert_flip_string(tport, ring->buf + ring->tail, count);
1036 ring->tail = 0;
1037 port->icount.rx += count;
1038 }
34df42f5 1039
66f37aaf
CP		 1040 /* Finally we read data from tail to head */
1041 if (ring->tail < ring->head) {
1042 count = ring->head - ring->tail;
34df42f5 1043
66f37aaf
CP		 1044 tty_insert_flip_string(tport, ring->buf + ring->tail, count);
1045 /* Wrap ring->head if needed */
1046 if (ring->head >= sg_dma_len(&atmel_port->sg_rx))
1047 ring->head = 0;
1048 ring->tail = ring->head;
34df42f5
ES		 1049 port->icount.rx += count;
1050 }
1051
66f37aaf
CP		 1052 /* USART retreives ownership of RX DMA buffer */
1053 dma_sync_sg_for_device(port->dev,
1054 &atmel_port->sg_rx,
1055 1,
485819b5 1056 DMA_FROM_DEVICE);
66f37aaf
CP		 1057
1058 /*
1059 * Drop the lock here since it might end up calling
1060 * uart_start(), which takes the lock.
1061 */
1062 spin_unlock(&port->lock);
1063 tty_flip_buffer_push(tport);
1064 spin_lock(&port->lock);
1065
4e7decda 1066 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_TIMEOUT);
34df42f5
ES		 1067}
1068
1069static int atmel_prepare_rx_dma(struct uart_port *port)
1070{
1071 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1072 struct dma_async_tx_descriptor *desc;
1073 dma_cap_mask_t mask;
1074 struct dma_slave_config config;
1075 struct circ_buf *ring;
1076 int ret, nent;
1077
1078 ring = &atmel_port->rx_ring;
1079
1080 dma_cap_zero(mask);
1081 dma_cap_set(DMA_CYCLIC, mask);
1082
1083 atmel_port->chan_rx = dma_request_slave_channel(port->dev, "rx");
1084 if (atmel_port->chan_rx == NULL)
1085 goto chan_err;
1086 dev_info(port->dev, "using %s for rx DMA transfers\n",
1087 dma_chan_name(atmel_port->chan_rx));
1088
1089 spin_lock_init(&atmel_port->lock_rx);
1090 sg_init_table(&atmel_port->sg_rx, 1);
1091 /* UART circular rx buffer is an aligned page. */
2c277054 1092 BUG_ON(!PAGE_ALIGNED(ring->buf));
34df42f5 1093 sg_set_page(&atmel_port->sg_rx,
1842dc2e 1094 virt_to_page(ring->buf),
a510880f 1095 sizeof(struct atmel_uart_char) * ATMEL_SERIAL_RINGSIZE,
c8d1f022 1096 (unsigned long)ring->buf & ~PAGE_MASK);
1842dc2e
CP		 1097 nent = dma_map_sg(port->dev,
1098 &atmel_port->sg_rx,
1099 1,
1100 DMA_FROM_DEVICE);
34df42f5
ES		 1101
1102 if (!nent) {
1103 dev_dbg(port->dev, "need to release resource of dma\n");
1104 goto chan_err;
1105 } else {
c8d1f022 1106 dev_dbg(port->dev, "%s: mapped %d@%p to %pad\n", __func__,
34df42f5
ES		 1107 sg_dma_len(&atmel_port->sg_rx),
1108 ring->buf,
c8d1f022 1109 &sg_dma_address(&atmel_port->sg_rx));
34df42f5
ES		 1110 }
1111
1112 /* Configure the slave DMA */
1113 memset(&config, 0, sizeof(config));
1114 config.direction = DMA_DEV_TO_MEM;
1115 config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1116 config.src_addr = port->mapbase + ATMEL_US_RHR;
a8d4e016 1117 config.src_maxburst = 1;
34df42f5 1118
5483c10e
MR		 1119 ret = dmaengine_slave_config(atmel_port->chan_rx,
1120 &config);
34df42f5
ES		 1121 if (ret) {
1122 dev_err(port->dev, "DMA rx slave configuration failed\n");
1123 goto chan_err;
1124 }
1125 /*
1126 * Prepare a cyclic dma transfer, assign 2 descriptors,
1127 * each one is half ring buffer size
1128 */
1129 desc = dmaengine_prep_dma_cyclic(atmel_port->chan_rx,
1842dc2e
CP		 1130 sg_dma_address(&atmel_port->sg_rx),
1131 sg_dma_len(&atmel_port->sg_rx),
1132 sg_dma_len(&atmel_port->sg_rx)/2,
1133 DMA_DEV_TO_MEM,
1134 DMA_PREP_INTERRUPT);
34df42f5
ES		 1135 desc->callback = atmel_complete_rx_dma;
1136 desc->callback_param = port;
1137 atmel_port->desc_rx = desc;
1138 atmel_port->cookie_rx = dmaengine_submit(desc);
1139
1140 return 0;
1141
1142chan_err:
1143 dev_err(port->dev, "RX channel not available, switch to pio\n");
1144 atmel_port->use_dma_rx = 0;
1145 if (atmel_port->chan_rx)
1146 atmel_release_rx_dma(port);
1147 return -EINVAL;
1148}
1149
2e68c22f
ES		 1150static void atmel_uart_timer_callback(unsigned long data)
1151{
1152 struct uart_port *port = (void *)data;
1153 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1154
1155 tasklet_schedule(&atmel_port->tasklet);
1156 mod_timer(&atmel_port->uart_timer, jiffies + uart_poll_timeout(port));
1157}
1158
b843aa21
RB		 1159/*
1160 * receive interrupt handler.
1161 */
1162static void
1163atmel_handle_receive(struct uart_port *port, unsigned int pending)
1164{
c811ab8c 1165 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
b843aa21 1166
64e22ebe 1167 if (atmel_use_pdc_rx(port)) {
a6670615
CC		 1168 /*
1169 * PDC receive. Just schedule the tasklet and let it
1170 * figure out the details.
1171 *
1172 * TODO: We're not handling error flags correctly at
1173 * the moment.
1174 */
1175 if (pending & (ATMEL_US_ENDRX | ATMEL_US_TIMEOUT)) {
4e7decda
CP		 1176 atmel_uart_writel(port, ATMEL_US_IDR,
1177 (ATMEL_US_ENDRX | ATMEL_US_TIMEOUT));
a6670615
CC		 1178 tasklet_schedule(&atmel_port->tasklet);
1179 }
1180
1181 if (pending & (ATMEL_US_RXBRK | ATMEL_US_OVRE |
1182 ATMEL_US_FRAME | ATMEL_US_PARE))
1183 atmel_pdc_rxerr(port, pending);
1184 }
1185
34df42f5
ES		 1186 if (atmel_use_dma_rx(port)) {
1187 if (pending & ATMEL_US_TIMEOUT) {
4e7decda
CP		 1188 atmel_uart_writel(port, ATMEL_US_IDR,
1189 ATMEL_US_TIMEOUT);
34df42f5
ES		 1190 tasklet_schedule(&atmel_port->tasklet);
1191 }
1192 }
1193
b843aa21
RB		 1194 /* Interrupt receive */
1195 if (pending & ATMEL_US_RXRDY)
1196 atmel_rx_chars(port);
1197 else if (pending & ATMEL_US_RXBRK) {
1198 /*
1199 * End of break detected. If it came along with a
1200 * character, atmel_rx_chars will handle it.
1201 */
4e7decda
CP		 1202 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
1203 atmel_uart_writel(port, ATMEL_US_IDR, ATMEL_US_RXBRK);
b843aa21
RB		 1204 atmel_port->break_active = 0;
1205 }
1206}
1207
1208/*
1ecc26bd 1209 * transmit interrupt handler. (Transmit is IRQF_NODELAY safe)
b843aa21
RB		 1210 */
1211static void
1212atmel_handle_transmit(struct uart_port *port, unsigned int pending)
1213{
c811ab8c 1214 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1ecc26bd 1215
e8faff73
CS		 1216 if (pending & atmel_port->tx_done_mask) {
1217 /* Either PDC or interrupt transmission */
4e7decda
CP		 1218 atmel_uart_writel(port, ATMEL_US_IDR,
1219 atmel_port->tx_done_mask);
e8faff73 1220 tasklet_schedule(&atmel_port->tasklet);
1ecc26bd 1221 }
b843aa21
RB		 1222}
1223
1224/*
1225 * status flags interrupt handler.
1226 */
1227static void
1228atmel_handle_status(struct uart_port *port, unsigned int pending,
1229 unsigned int status)
1230{
c811ab8c 1231 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1ecc26bd 1232
b843aa21 1233 if (pending & (ATMEL_US_RIIC | ATMEL_US_DSRIC | ATMEL_US_DCDIC
1ecc26bd
RB		 1234 | ATMEL_US_CTSIC)) {
1235 atmel_port->irq_status = status;
d033e82d
LZ		 1236 atmel_port->status_change = atmel_port->irq_status ^
1237 atmel_port->irq_status_prev;
1238 atmel_port->irq_status_prev = status;
1ecc26bd
RB		 1239 tasklet_schedule(&atmel_port->tasklet);
1240 }
b843aa21
RB		 1241}
1242
1e6c9c28
AV		 1243/*
1244 * Interrupt handler
1245 */
7d12e780 1246static irqreturn_t atmel_interrupt(int irq, void *dev_id)
1e6c9c28
AV		 1247{
1248 struct uart_port *port = dev_id;
ab5e4e41 1249 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2c7af5ba 1250 unsigned int status, pending, mask, pass_counter = 0;
1e6c9c28 1251
2c7af5ba
BB		 1252 spin_lock(&atmel_port->lock_suspended);
1253
a6670615 1254 do {
e0b0baad 1255 status = atmel_get_lines_status(port);
4e7decda 1256 mask = atmel_uart_readl(port, ATMEL_US_IMR);
2c7af5ba 1257 pending = status & mask;
a6670615
CC		 1258 if (!pending)
1259 break;
1260
2c7af5ba
BB		 1261 if (atmel_port->suspended) {
1262 atmel_port->pending |= pending;
1263 atmel_port->pending_status = status;
4e7decda 1264 atmel_uart_writel(port, ATMEL_US_IDR, mask);
2c7af5ba
BB		 1265 pm_system_wakeup();
1266 break;
1267 }
1268
b843aa21
RB		 1269 atmel_handle_receive(port, pending);
1270 atmel_handle_status(port, pending, status);
1271 atmel_handle_transmit(port, pending);
a6670615 1272 } while (pass_counter++ < ATMEL_ISR_PASS_LIMIT);
afefc415 1273
2c7af5ba
BB		 1274 spin_unlock(&atmel_port->lock_suspended);
1275
0400b697 1276 return pass_counter ? IRQ_HANDLED : IRQ_NONE;
a6670615 1277}
1e6c9c28 1278
a930e528
ES		 1279static void atmel_release_tx_pdc(struct uart_port *port)
1280{
1281 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1282 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1283
1284 dma_unmap_single(port->dev,
1285 pdc->dma_addr,
1286 pdc->dma_size,
1287 DMA_TO_DEVICE);
1288}
1289
a6670615
CC		 1290/*
1291 * Called from tasklet with ENDTX and TXBUFE interrupts disabled.
1292 */
64e22ebe 1293static void atmel_tx_pdc(struct uart_port *port)
a6670615 1294{
c811ab8c 1295 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
ebd2c8f6 1296 struct circ_buf *xmit = &port->state->xmit;
a6670615
CC		 1297 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1298 int count;
1299
ba0657ff 1300 /* nothing left to transmit? */
4e7decda 1301 if (atmel_uart_readl(port, ATMEL_PDC_TCR))
ba0657ff
MT		 1302 return;
1303
a6670615
CC		 1304 xmit->tail += pdc->ofs;
1305 xmit->tail &= UART_XMIT_SIZE - 1;
1306
1307 port->icount.tx += pdc->ofs;
1308 pdc->ofs = 0;
1309
ba0657ff 1310 /* more to transmit - setup next transfer */
a6670615 1311
ba0657ff 1312 /* disable PDC transmit */
4e7decda 1313 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS);
ba0657ff 1314
1f14081d 1315 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) {
a6670615
CC		 1316 dma_sync_single_for_device(port->dev,
1317 pdc->dma_addr,
1318 pdc->dma_size,
1319 DMA_TO_DEVICE);
1320
1321 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
1322 pdc->ofs = count;
1323
4e7decda
CP		 1324 atmel_uart_writel(port, ATMEL_PDC_TPR,
1325 pdc->dma_addr + xmit->tail);
1326 atmel_uart_writel(port, ATMEL_PDC_TCR, count);
e8faff73 1327 /* re-enable PDC transmit */
4e7decda 1328 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
e8faff73 1329 /* Enable interrupts */
4e7decda
CP		 1330 atmel_uart_writel(port, ATMEL_US_IER,
1331 atmel_port->tx_done_mask);
e8faff73 1332 } else {
13bd3e6f
RRD		 1333 if ((port->rs485.flags & SER_RS485_ENABLED) &&
1334 !(port->rs485.flags & SER_RS485_RX_DURING_TX)) {
e8faff73
CS		 1335 /* DMA done, stop TX, start RX for RS485 */
1336 atmel_start_rx(port);
1337 }
1e6c9c28 1338 }
a6670615
CC		 1339
1340 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1341 uart_write_wakeup(port);
1e6c9c28
AV		 1342}
1343
a930e528
ES		 1344static int atmel_prepare_tx_pdc(struct uart_port *port)
1345{
1346 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1347 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1348 struct circ_buf *xmit = &port->state->xmit;
1349
1350 pdc->buf = xmit->buf;
1351 pdc->dma_addr = dma_map_single(port->dev,
1352 pdc->buf,
1353 UART_XMIT_SIZE,
1354 DMA_TO_DEVICE);
1355 pdc->dma_size = UART_XMIT_SIZE;
1356 pdc->ofs = 0;
1357
1358 return 0;
1359}
1360
1ecc26bd
RB		 1361static void atmel_rx_from_ring(struct uart_port *port)
1362{
c811ab8c 1363 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1ecc26bd
RB		 1364 struct circ_buf *ring = &atmel_port->rx_ring;
1365 unsigned int flg;
1366 unsigned int status;
1367
1368 while (ring->head != ring->tail) {
1369 struct atmel_uart_char c;
1370
1371 /* Make sure c is loaded after head. */
1372 smp_rmb();
1373
1374 c = ((struct atmel_uart_char *)ring->buf)[ring->tail];
1375
1376 ring->tail = (ring->tail + 1) & (ATMEL_SERIAL_RINGSIZE - 1);
1377
1378 port->icount.rx++;
1379 status = c.status;
1380 flg = TTY_NORMAL;
1381
1382 /*
1383 * note that the error handling code is
1384 * out of the main execution path
1385 */
1386 if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME
1387 | ATMEL_US_OVRE | ATMEL_US_RXBRK))) {
1388 if (status & ATMEL_US_RXBRK) {
1389 /* ignore side-effect */
1390 status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME);
1391
1392 port->icount.brk++;
1393 if (uart_handle_break(port))
1394 continue;
1395 }
1396 if (status & ATMEL_US_PARE)
1397 port->icount.parity++;
1398 if (status & ATMEL_US_FRAME)
1399 port->icount.frame++;
1400 if (status & ATMEL_US_OVRE)
1401 port->icount.overrun++;
1402
1403 status &= port->read_status_mask;
1404
1405 if (status & ATMEL_US_RXBRK)
1406 flg = TTY_BREAK;
1407 else if (status & ATMEL_US_PARE)
1408 flg = TTY_PARITY;
1409 else if (status & ATMEL_US_FRAME)
1410 flg = TTY_FRAME;
1411 }
1412
1413
1414 if (uart_handle_sysrq_char(port, c.ch))
1415 continue;
1416
1417 uart_insert_char(port, status, ATMEL_US_OVRE, c.ch, flg);
1418 }
1419
1420 /*
1421 * Drop the lock here since it might end up calling
1422 * uart_start(), which takes the lock.
1423 */
1424 spin_unlock(&port->lock);
2e124b4a 1425 tty_flip_buffer_push(&port->state->port);
1ecc26bd
RB		 1426 spin_lock(&port->lock);
1427}
1428
a930e528
ES		 1429static void atmel_release_rx_pdc(struct uart_port *port)
1430{
1431 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1432 int i;
1433
1434 for (i = 0; i < 2; i++) {
1435 struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i];
1436
1437 dma_unmap_single(port->dev,
1438 pdc->dma_addr,
1439 pdc->dma_size,
1440 DMA_FROM_DEVICE);
1441 kfree(pdc->buf);
1442 }
1443}
1444
64e22ebe 1445static void atmel_rx_from_pdc(struct uart_port *port)
a6670615 1446{
c811ab8c 1447 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
05c7cd39 1448 struct tty_port *tport = &port->state->port;
a6670615
CC		 1449 struct atmel_dma_buffer *pdc;
1450 int rx_idx = atmel_port->pdc_rx_idx;
1451 unsigned int head;
1452 unsigned int tail;
1453 unsigned int count;
1454
1455 do {
1456 /* Reset the UART timeout early so that we don't miss one */
4e7decda 1457 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
a6670615
CC		 1458
1459 pdc = &atmel_port->pdc_rx[rx_idx];
4e7decda 1460 head = atmel_uart_readl(port, ATMEL_PDC_RPR) - pdc->dma_addr;
a6670615
CC		 1461 tail = pdc->ofs;
1462
1463 /* If the PDC has switched buffers, RPR won't contain
1464 * any address within the current buffer. Since head
1465 * is unsigned, we just need a one-way comparison to
1466 * find out.
1467 *
1468 * In this case, we just need to consume the entire
1469 * buffer and resubmit it for DMA. This will clear the
1470 * ENDRX bit as well, so that we can safely re-enable
1471 * all interrupts below.
1472 */
1473 head = min(head, pdc->dma_size);
1474
1475 if (likely(head != tail)) {
1476 dma_sync_single_for_cpu(port->dev, pdc->dma_addr,
1477 pdc->dma_size, DMA_FROM_DEVICE);
1478
1479 /*
1480 * head will only wrap around when we recycle
1481 * the DMA buffer, and when that happens, we
1482 * explicitly set tail to 0. So head will
1483 * always be greater than tail.
1484 */
1485 count = head - tail;
1486
05c7cd39
JS		 1487 tty_insert_flip_string(tport, pdc->buf + pdc->ofs,
1488 count);
a6670615
CC		 1489
1490 dma_sync_single_for_device(port->dev, pdc->dma_addr,
1491 pdc->dma_size, DMA_FROM_DEVICE);
1492
1493 port->icount.rx += count;
1494 pdc->ofs = head;
1495 }
1496
1497 /*
1498 * If the current buffer is full, we need to check if
1499 * the next one contains any additional data.
1500 */
1501 if (head >= pdc->dma_size) {
1502 pdc->ofs = 0;
4e7decda
CP		 1503 atmel_uart_writel(port, ATMEL_PDC_RNPR, pdc->dma_addr);
1504 atmel_uart_writel(port, ATMEL_PDC_RNCR, pdc->dma_size);
a6670615
CC		 1505
1506 rx_idx = !rx_idx;
1507 atmel_port->pdc_rx_idx = rx_idx;
1508 }
1509 } while (head >= pdc->dma_size);
1510
1511 /*
1512 * Drop the lock here since it might end up calling
1513 * uart_start(), which takes the lock.
1514 */
1515 spin_unlock(&port->lock);
2e124b4a 1516 tty_flip_buffer_push(tport);
a6670615
CC		 1517 spin_lock(&port->lock);
1518
4e7decda
CP		 1519 atmel_uart_writel(port, ATMEL_US_IER,
1520 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT);
a6670615
CC		 1521}
1522
a930e528
ES		 1523static int atmel_prepare_rx_pdc(struct uart_port *port)
1524{
1525 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1526 int i;
1527
1528 for (i = 0; i < 2; i++) {
1529 struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i];
1530
1531 pdc->buf = kmalloc(PDC_BUFFER_SIZE, GFP_KERNEL);
1532 if (pdc->buf == NULL) {
1533 if (i != 0) {
1534 dma_unmap_single(port->dev,
1535 atmel_port->pdc_rx[0].dma_addr,
1536 PDC_BUFFER_SIZE,
1537 DMA_FROM_DEVICE);
1538 kfree(atmel_port->pdc_rx[0].buf);
1539 }
1540 atmel_port->use_pdc_rx = 0;
1541 return -ENOMEM;
1542 }
1543 pdc->dma_addr = dma_map_single(port->dev,
1544 pdc->buf,
1545 PDC_BUFFER_SIZE,
1546 DMA_FROM_DEVICE);
1547 pdc->dma_size = PDC_BUFFER_SIZE;
1548 pdc->ofs = 0;
1549 }
1550
1551 atmel_port->pdc_rx_idx = 0;
1552
4e7decda
CP		 1553 atmel_uart_writel(port, ATMEL_PDC_RPR, atmel_port->pdc_rx[0].dma_addr);
1554 atmel_uart_writel(port, ATMEL_PDC_RCR, PDC_BUFFER_SIZE);
a930e528 1555
4e7decda
CP		 1556 atmel_uart_writel(port, ATMEL_PDC_RNPR,
1557 atmel_port->pdc_rx[1].dma_addr);
1558 atmel_uart_writel(port, ATMEL_PDC_RNCR, PDC_BUFFER_SIZE);
a930e528
ES		 1559
1560 return 0;
1561}
1562
1ecc26bd
RB		 1563/*
1564 * tasklet handling tty stuff outside the interrupt handler.
1565 */
1566static void atmel_tasklet_func(unsigned long data)
1567{
1568 struct uart_port *port = (struct uart_port *)data;
c811ab8c 1569 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
d033e82d
LZ		 1570 unsigned int status = atmel_port->irq_status;
1571 unsigned int status_change = atmel_port->status_change;
1ecc26bd
RB		 1572
1573 /* The interrupt handler does not take the lock */
1574 spin_lock(&port->lock);
1575
a930e528 1576 atmel_port->schedule_tx(port);
1ecc26bd 1577
1ecc26bd
RB		 1578 if (status_change & (ATMEL_US_RI | ATMEL_US_DSR
1579 | ATMEL_US_DCD | ATMEL_US_CTS)) {
1580 /* TODO: All reads to CSR will clear these interrupts! */
1581 if (status_change & ATMEL_US_RI)
1582 port->icount.rng++;
1583 if (status_change & ATMEL_US_DSR)
1584 port->icount.dsr++;
1585 if (status_change & ATMEL_US_DCD)
1586 uart_handle_dcd_change(port, !(status & ATMEL_US_DCD));
1587 if (status_change & ATMEL_US_CTS)
1588 uart_handle_cts_change(port, !(status & ATMEL_US_CTS));
1589
bdc04e31 1590 wake_up_interruptible(&port->state->port.delta_msr_wait);
1ecc26bd 1591
d033e82d 1592 atmel_port->status_change = 0;
1ecc26bd
RB		 1593 }
1594
a930e528 1595 atmel_port->schedule_rx(port);
1ecc26bd
RB		 1596
1597 spin_unlock(&port->lock);
1598}
1599
4a1e8888 1600static void atmel_init_property(struct atmel_uart_port *atmel_port,
33d64c4f
ES		 1601 struct platform_device *pdev)
1602{
1603 struct device_node *np = pdev->dev.of_node;
574de559 1604 struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev);
33d64c4f
ES		 1605
1606 if (np) {
1607 /* DMA/PDC usage specification */
1608 if (of_get_property(np, "atmel,use-dma-rx", NULL)) {
1609 if (of_get_property(np, "dmas", NULL)) {
1610 atmel_port->use_dma_rx = true;
1611 atmel_port->use_pdc_rx = false;
1612 } else {
1613 atmel_port->use_dma_rx = false;
1614 atmel_port->use_pdc_rx = true;
1615 }
1616 } else {
1617 atmel_port->use_dma_rx = false;
1618 atmel_port->use_pdc_rx = false;
1619 }
1620
1621 if (of_get_property(np, "atmel,use-dma-tx", NULL)) {
1622 if (of_get_property(np, "dmas", NULL)) {
1623 atmel_port->use_dma_tx = true;
1624 atmel_port->use_pdc_tx = false;
1625 } else {
1626 atmel_port->use_dma_tx = false;
1627 atmel_port->use_pdc_tx = true;
1628 }
1629 } else {
1630 atmel_port->use_dma_tx = false;
1631 atmel_port->use_pdc_tx = false;
1632 }
1633
1634 } else {
1635 atmel_port->use_pdc_rx = pdata->use_dma_rx;
1636 atmel_port->use_pdc_tx = pdata->use_dma_tx;
1637 atmel_port->use_dma_rx = false;
1638 atmel_port->use_dma_tx = false;
1639 }
1640
33d64c4f
ES		 1641}
1642
13bd3e6f 1643static void atmel_init_rs485(struct uart_port *port,
33d64c4f
ES		 1644 struct platform_device *pdev)
1645{
1646 struct device_node *np = pdev->dev.of_node;
574de559 1647 struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev);
33d64c4f
ES		 1648
1649 if (np) {
77bdec6f 1650 struct serial_rs485 *rs485conf = &port->rs485;
33d64c4f
ES		 1651 u32 rs485_delay[2];
1652 /* rs485 properties */
1653 if (of_property_read_u32_array(np, "rs485-rts-delay",
1654 rs485_delay, 2) == 0) {
33d64c4f
ES		 1655 rs485conf->delay_rts_before_send = rs485_delay[0];
1656 rs485conf->delay_rts_after_send = rs485_delay[1];
1657 rs485conf->flags = 0;
77bdec6f 1658 }
33d64c4f
ES		 1659
1660 if (of_get_property(np, "rs485-rx-during-tx", NULL))
1661 rs485conf->flags |= SER_RS485_RX_DURING_TX;
1662
1663 if (of_get_property(np, "linux,rs485-enabled-at-boot-time",
1664 NULL))
1665 rs485conf->flags |= SER_RS485_ENABLED;
33d64c4f 1666 } else {
13bd3e6f 1667 port->rs485 = pdata->rs485;
33d64c4f
ES		 1668 }
1669
1670}
1671
a930e528
ES		 1672static void atmel_set_ops(struct uart_port *port)
1673{
1674 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1675
34df42f5
ES		 1676 if (atmel_use_dma_rx(port)) {
1677 atmel_port->prepare_rx = &atmel_prepare_rx_dma;
1678 atmel_port->schedule_rx = &atmel_rx_from_dma;
1679 atmel_port->release_rx = &atmel_release_rx_dma;
1680 } else if (atmel_use_pdc_rx(port)) {
a930e528
ES		 1681 atmel_port->prepare_rx = &atmel_prepare_rx_pdc;
1682 atmel_port->schedule_rx = &atmel_rx_from_pdc;
1683 atmel_port->release_rx = &atmel_release_rx_pdc;
1684 } else {
1685 atmel_port->prepare_rx = NULL;
1686 atmel_port->schedule_rx = &atmel_rx_from_ring;
1687 atmel_port->release_rx = NULL;
1688 }
1689
08f738be
ES		 1690 if (atmel_use_dma_tx(port)) {
1691 atmel_port->prepare_tx = &atmel_prepare_tx_dma;
1692 atmel_port->schedule_tx = &atmel_tx_dma;
1693 atmel_port->release_tx = &atmel_release_tx_dma;
1694 } else if (atmel_use_pdc_tx(port)) {
a930e528
ES		 1695 atmel_port->prepare_tx = &atmel_prepare_tx_pdc;
1696 atmel_port->schedule_tx = &atmel_tx_pdc;
1697 atmel_port->release_tx = &atmel_release_tx_pdc;
1698 } else {
1699 atmel_port->prepare_tx = NULL;
1700 atmel_port->schedule_tx = &atmel_tx_chars;
1701 atmel_port->release_tx = NULL;
1702 }
1703}
1704
055560b0
ES		 1705/*
1706 * Get ip name usart or uart
1707 */
892db58b 1708static void atmel_get_ip_name(struct uart_port *port)
055560b0
ES		 1709{
1710 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
4e7decda 1711 int name = atmel_uart_readl(port, ATMEL_US_NAME);
731d9cae 1712 u32 version;
1d673fb9 1713 u32 usart, dbgu_uart, new_uart;
4b769371
NF		 1714 /* ASCII decoding for IP version */
1715 usart = 0x55534152; /* USAR(T) */
1716 dbgu_uart = 0x44424755; /* DBGU */
1d673fb9 1717 new_uart = 0x55415254; /* UART */
055560b0 1718
4b769371 1719 atmel_port->has_hw_timer = false;
055560b0 1720
1d673fb9
NF		 1721 if (name == usart || name == new_uart) {
1722 dev_dbg(port->dev, "Usart or uart with hw timer\n");
4b769371
NF		 1723 atmel_port->has_hw_timer = true;
1724 } else if (name == dbgu_uart) {
1725 dev_dbg(port->dev, "Dbgu or uart without hw timer\n");
1726 atmel_port->has_hw_timer = false;
055560b0 1727 } else {
731d9cae 1728 /* fallback for older SoCs: use version field */
4e7decda 1729 version = atmel_uart_readl(port, ATMEL_US_VERSION);
731d9cae
NF		 1730 switch (version) {
1731 case 0x302:
1732 case 0x10213:
1733 dev_dbg(port->dev, "This version is usart\n");
4b769371 1734 atmel_port->has_hw_timer = true;
731d9cae
NF		 1735 break;
1736 case 0x203:
1737 case 0x10202:
1738 dev_dbg(port->dev, "This version is uart\n");
4b769371 1739 atmel_port->has_hw_timer = false;
731d9cae
NF		 1740 break;
1741 default:
1742 dev_err(port->dev, "Not supported ip name nor version, set to uart\n");
1743 }
055560b0 1744 }
055560b0
ES		 1745}
1746
1e6c9c28
AV		 1747/*
1748 * Perform initialization and enable port for reception
1749 */
7192f92c 1750static int atmel_startup(struct uart_port *port)
1e6c9c28 1751{
33d64c4f 1752 struct platform_device *pdev = to_platform_device(port->dev);
c811ab8c 1753 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
ebd2c8f6 1754 struct tty_struct *tty = port->state->port.tty;
1e6c9c28
AV		 1755 int retval;
1756
1757 /*
1758 * Ensure that no interrupts are enabled otherwise when
1759 * request_irq() is called we could get stuck trying to
1760 * handle an unexpected interrupt
1761 */
4e7decda 1762 atmel_uart_writel(port, ATMEL_US_IDR, -1);
ab5e4e41 1763 atmel_port->ms_irq_enabled = false;
1e6c9c28
AV		 1764
1765 /*
1766 * Allocate the IRQ
1767 */
2c7af5ba
BB		 1768 retval = request_irq(port->irq, atmel_interrupt,
1769 IRQF_SHARED | IRQF_COND_SUSPEND,
ae161068 1770 tty ? tty->name : "atmel_serial", port);
1e6c9c28 1771 if (retval) {
ddaa6037 1772 dev_err(port->dev, "atmel_startup - Can't get irq\n");
1e6c9c28
AV		 1773 return retval;
1774 }
1775
1e125786
LZ		 1776 tasklet_enable(&atmel_port->tasklet);
1777
a6670615
CC		 1778 /*
1779 * Initialize DMA (if necessary)
1780 */
33d64c4f 1781 atmel_init_property(atmel_port, pdev);
4d9628a1 1782 atmel_set_ops(port);
33d64c4f 1783
a930e528
ES		 1784 if (atmel_port->prepare_rx) {
1785 retval = atmel_port->prepare_rx(port);
1786 if (retval < 0)
1787 atmel_set_ops(port);
a6670615 1788 }
a6670615 1789
a930e528
ES		 1790 if (atmel_port->prepare_tx) {
1791 retval = atmel_port->prepare_tx(port);
1792 if (retval < 0)
1793 atmel_set_ops(port);
a6670615 1794 }
1e6c9c28 1795
b5199d46
CP		 1796 /*
1797 * Enable FIFO when available
1798 */
1799 if (atmel_port->fifo_size) {
1800 unsigned int txrdym = ATMEL_US_ONE_DATA;
1801 unsigned int rxrdym = ATMEL_US_ONE_DATA;
1802 unsigned int fmr;
1803
1804 atmel_uart_writel(port, ATMEL_US_CR,
1805 ATMEL_US_FIFOEN |
1806 ATMEL_US_RXFCLR |
1807 ATMEL_US_TXFLCLR);
1808
5f258b3e
CP		 1809 if (atmel_use_dma_tx(port))
1810 txrdym = ATMEL_US_FOUR_DATA;
1811
b5199d46
CP		 1812 fmr = ATMEL_US_TXRDYM(txrdym) | ATMEL_US_RXRDYM(rxrdym);
1813 if (atmel_port->rts_high &&
1814 atmel_port->rts_low)
1815 fmr |= ATMEL_US_FRTSC |
1816 ATMEL_US_RXFTHRES(atmel_port->rts_high) |
1817 ATMEL_US_RXFTHRES2(atmel_port->rts_low);
1818
1819 atmel_uart_writel(port, ATMEL_US_FMR, fmr);
1820 }
1821
27c0c8e5 1822 /* Save current CSR for comparison in atmel_tasklet_func() */
e0b0baad 1823 atmel_port->irq_status_prev = atmel_get_lines_status(port);
27c0c8e5
AN		 1824 atmel_port->irq_status = atmel_port->irq_status_prev;
1825
1e6c9c28
AV		 1826 /*
1827 * Finally, enable the serial port
1828 */
4e7decda 1829 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
b843aa21 1830 /* enable xmit & rcvr */
4e7decda 1831 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN);
afefc415 1832
8bc661bf
MR		 1833 setup_timer(&atmel_port->uart_timer,
1834 atmel_uart_timer_callback,
1835 (unsigned long)port);
1836
64e22ebe 1837 if (atmel_use_pdc_rx(port)) {
a6670615 1838 /* set UART timeout */
4b769371 1839 if (!atmel_port->has_hw_timer) {
2e68c22f
ES		 1840 mod_timer(&atmel_port->uart_timer,
1841 jiffies + uart_poll_timeout(port));
1842 /* set USART timeout */
1843 } else {
4e7decda
CP		 1844 atmel_uart_writel(port, ATMEL_US_RTOR, PDC_RX_TIMEOUT);
1845 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
a6670615 1846
4e7decda
CP		 1847 atmel_uart_writel(port, ATMEL_US_IER,
1848 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT);
2e68c22f 1849 }
a6670615 1850 /* enable PDC controller */
4e7decda 1851 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN);
34df42f5 1852 } else if (atmel_use_dma_rx(port)) {
2e68c22f 1853 /* set UART timeout */
4b769371 1854 if (!atmel_port->has_hw_timer) {
2e68c22f
ES		 1855 mod_timer(&atmel_port->uart_timer,
1856 jiffies + uart_poll_timeout(port));
1857 /* set USART timeout */
1858 } else {
4e7decda
CP		 1859 atmel_uart_writel(port, ATMEL_US_RTOR, PDC_RX_TIMEOUT);
1860 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
34df42f5 1861
4e7decda
CP		 1862 atmel_uart_writel(port, ATMEL_US_IER,
1863 ATMEL_US_TIMEOUT);
2e68c22f 1864 }
a6670615
CC		 1865 } else {
1866 /* enable receive only */
4e7decda 1867 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_RXRDY);
a6670615 1868 }
afefc415 1869
1e6c9c28
AV		 1870 return 0;
1871}
1872
479e9b94
PH		 1873/*
1874 * Flush any TX data submitted for DMA. Called when the TX circular
1875 * buffer is reset.
1876 */
1877static void atmel_flush_buffer(struct uart_port *port)
1878{
1879 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1880
1881 if (atmel_use_pdc_tx(port)) {
4e7decda 1882 atmel_uart_writel(port, ATMEL_PDC_TCR, 0);
479e9b94
PH		 1883 atmel_port->pdc_tx.ofs = 0;
1884 }
1885}
1886
1e6c9c28
AV		 1887/*
1888 * Disable the port
1889 */
7192f92c 1890static void atmel_shutdown(struct uart_port *port)
1e6c9c28 1891{
c811ab8c 1892 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
0cc7c6c7 1893
8bc661bf
MR		 1894 /*
1895 * Prevent any tasklets being scheduled during
1896 * cleanup
1897 */
1898 del_timer_sync(&atmel_port->uart_timer);
1899
0cc7c6c7
MR		 1900 /*
1901 * Clear out any scheduled tasklets before
1902 * we destroy the buffers
1903 */
1e125786 1904 tasklet_disable(&atmel_port->tasklet);
0cc7c6c7
MR		 1905 tasklet_kill(&atmel_port->tasklet);
1906
a6670615 1907 /*
0cc7c6c7
MR		 1908 * Ensure everything is stopped and
1909 * disable all interrupts, port and break condition.
a6670615
CC		 1910 */
1911 atmel_stop_rx(port);
1912 atmel_stop_tx(port);
1913
4e7decda
CP		 1914 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
1915 atmel_uart_writel(port, ATMEL_US_IDR, -1);
0cc7c6c7
MR		 1916
1917
a6670615
CC		 1918 /*
1919 * Shut-down the DMA.
1920 */
a930e528
ES		 1921 if (atmel_port->release_rx)
1922 atmel_port->release_rx(port);
1923 if (atmel_port->release_tx)
1924 atmel_port->release_tx(port);
a6670615 1925
bb7e73c5
MD		 1926 /*
1927 * Reset ring buffer pointers
1928 */
1929 atmel_port->rx_ring.head = 0;
1930 atmel_port->rx_ring.tail = 0;
1931
1e6c9c28 1932 /*
ab5e4e41 1933 * Free the interrupts
1e6c9c28
AV		 1934 */
1935 free_irq(port->irq, port);
ab5e4e41
RG		 1936
1937 atmel_port->ms_irq_enabled = false;
1e6c9c28 1938
479e9b94 1939 atmel_flush_buffer(port);
9afd561a
HS		 1940}
1941
1e6c9c28
AV		 1942/*
1943 * Power / Clock management.
1944 */
b843aa21
RB		 1945static void atmel_serial_pm(struct uart_port *port, unsigned int state,
1946 unsigned int oldstate)
1e6c9c28 1947{
c811ab8c 1948 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
afefc415 1949
1e6c9c28 1950 switch (state) {
b843aa21
RB		 1951 case 0:
1952 /*
1953 * Enable the peripheral clock for this serial port.
1954 * This is called on uart_open() or a resume event.
1955 */
91f8c2d8 1956 clk_prepare_enable(atmel_port->clk);
f05596db
AS		 1957
1958 /* re-enable interrupts if we disabled some on suspend */
4e7decda 1959 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->backup_imr);
b843aa21
RB		 1960 break;
1961 case 3:
f05596db 1962 /* Back up the interrupt mask and disable all interrupts */
4e7decda
CP		 1963 atmel_port->backup_imr = atmel_uart_readl(port, ATMEL_US_IMR);
1964 atmel_uart_writel(port, ATMEL_US_IDR, -1);
f05596db 1965
b843aa21
RB		 1966 /*
1967 * Disable the peripheral clock for this serial port.
1968 * This is called on uart_close() or a suspend event.
1969 */
91f8c2d8 1970 clk_disable_unprepare(atmel_port->clk);
b843aa21
RB		 1971 break;
1972 default:
ddaa6037 1973 dev_err(port->dev, "atmel_serial: unknown pm %d\n", state);
1e6c9c28
AV		 1974 }
1975}
1976
1977/*
1978 * Change the port parameters
1979 */
b843aa21
RB		 1980static void atmel_set_termios(struct uart_port *port, struct ktermios *termios,
1981 struct ktermios *old)
1e6c9c28
AV		 1982{
1983 unsigned long flags;
1cf6e8fc
CP		 1984 unsigned int old_mode, mode, imr, quot, baud;
1985
1986 /* save the current mode register */
4e7decda 1987 mode = old_mode = atmel_uart_readl(port, ATMEL_US_MR);
1e6c9c28 1988
1cf6e8fc
CP		 1989 /* reset the mode, clock divisor, parity, stop bits and data size */
1990 mode &= ~(ATMEL_US_USCLKS | ATMEL_US_CHRL | ATMEL_US_NBSTOP |
1991 ATMEL_US_PAR | ATMEL_US_USMODE);
03abeac0 1992
b843aa21 1993 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
1e6c9c28
AV		 1994 quot = uart_get_divisor(port, baud);
1995
b843aa21 1996 if (quot > 65535) { /* BRGR is 16-bit, so switch to slower clock */
03abeac0
AV		 1997 quot /= 8;
1998 mode |= ATMEL_US_USCLKS_MCK_DIV8;
1999 }
1e6c9c28
AV		 2000
2001 /* byte size */
2002 switch (termios->c_cflag & CSIZE) {
2003 case CS5:
7192f92c 2004 mode |= ATMEL_US_CHRL_5;
1e6c9c28
AV		 2005 break;
2006 case CS6:
7192f92c 2007 mode |= ATMEL_US_CHRL_6;
1e6c9c28
AV		 2008 break;
2009 case CS7:
7192f92c 2010 mode |= ATMEL_US_CHRL_7;
1e6c9c28
AV		 2011 break;
2012 default:
7192f92c 2013 mode |= ATMEL_US_CHRL_8;
1e6c9c28
AV		 2014 break;
2015 }
2016
2017 /* stop bits */
2018 if (termios->c_cflag & CSTOPB)
7192f92c 2019 mode |= ATMEL_US_NBSTOP_2;
1e6c9c28
AV		 2020
2021 /* parity */
2022 if (termios->c_cflag & PARENB) {
b843aa21
RB		 2023 /* Mark or Space parity */
2024 if (termios->c_cflag & CMSPAR) {
1e6c9c28 2025 if (termios->c_cflag & PARODD)
7192f92c 2026 mode |= ATMEL_US_PAR_MARK;
1e6c9c28 2027 else
7192f92c 2028 mode |= ATMEL_US_PAR_SPACE;
b843aa21 2029 } else if (termios->c_cflag & PARODD)
7192f92c 2030 mode |= ATMEL_US_PAR_ODD;
1e6c9c28 2031 else
7192f92c 2032 mode |= ATMEL_US_PAR_EVEN;
b843aa21 2033 } else
7192f92c 2034 mode |= ATMEL_US_PAR_NONE;
1e6c9c28
AV		 2035
2036 spin_lock_irqsave(&port->lock, flags);
2037
7192f92c 2038 port->read_status_mask = ATMEL_US_OVRE;
1e6c9c28 2039 if (termios->c_iflag & INPCK)
7192f92c 2040 port->read_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE);
ef8b9ddc 2041 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
7192f92c 2042 port->read_status_mask |= ATMEL_US_RXBRK;
1e6c9c28 2043
64e22ebe 2044 if (atmel_use_pdc_rx(port))
a6670615 2045 /* need to enable error interrupts */
4e7decda 2046 atmel_uart_writel(port, ATMEL_US_IER, port->read_status_mask);
a6670615 2047
1e6c9c28
AV		 2048 /*
2049 * Characters to ignore
2050 */
2051 port->ignore_status_mask = 0;
2052 if (termios->c_iflag & IGNPAR)
7192f92c 2053 port->ignore_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE);
1e6c9c28 2054 if (termios->c_iflag & IGNBRK) {
7192f92c 2055 port->ignore_status_mask |= ATMEL_US_RXBRK;
1e6c9c28
AV		 2056 /*
2057 * If we're ignoring parity and break indicators,
2058 * ignore overruns too (for real raw support).
2059 */
2060 if (termios->c_iflag & IGNPAR)
7192f92c 2061 port->ignore_status_mask |= ATMEL_US_OVRE;
1e6c9c28 2062 }
b843aa21 2063 /* TODO: Ignore all characters if CREAD is set.*/
1e6c9c28
AV		 2064
2065 /* update the per-port timeout */
2066 uart_update_timeout(port, termios->c_cflag, baud);
2067
0ccad870
HS		 2068 /*
2069 * save/disable interrupts. The tty layer will ensure that the
2070 * transmitter is empty if requested by the caller, so there's
2071 * no need to wait for it here.
2072 */
4e7decda
CP		 2073 imr = atmel_uart_readl(port, ATMEL_US_IMR);
2074 atmel_uart_writel(port, ATMEL_US_IDR, -1);
1e6c9c28
AV		 2075
2076 /* disable receiver and transmitter */
4e7decda 2077 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXDIS | ATMEL_US_RXDIS);
1e6c9c28 2078
1cf6e8fc 2079 /* mode */
13bd3e6f 2080 if (port->rs485.flags & SER_RS485_ENABLED) {
4e7decda
CP		 2081 atmel_uart_writel(port, ATMEL_US_TTGR,
2082 port->rs485.delay_rts_after_send);
e8faff73 2083 mode |= ATMEL_US_USMODE_RS485;
1cf6e8fc
CP		 2084 } else if (termios->c_cflag & CRTSCTS) {
2085 /* RS232 with hardware handshake (RTS/CTS) */
2086 mode |= ATMEL_US_USMODE_HWHS;
2087 } else {
2088 /* RS232 without hadware handshake */
2089 mode |= ATMEL_US_USMODE_NORMAL;
e8faff73
CS		 2090 }
2091
1cf6e8fc 2092 /* set the mode, clock divisor, parity, stop bits and data size */
4e7decda 2093 atmel_uart_writel(port, ATMEL_US_MR, mode);
1e6c9c28 2094
1cf6e8fc
CP		 2095 /*
2096 * when switching the mode, set the RTS line state according to the
2097 * new mode, otherwise keep the former state
2098 */
2099 if ((old_mode & ATMEL_US_USMODE) != (mode & ATMEL_US_USMODE)) {
2100 unsigned int rts_state;
2101
2102 if ((mode & ATMEL_US_USMODE) == ATMEL_US_USMODE_HWHS) {
2103 /* let the hardware control the RTS line */
2104 rts_state = ATMEL_US_RTSDIS;
2105 } else {
2106 /* force RTS line to low level */
2107 rts_state = ATMEL_US_RTSEN;
2108 }
2109
4e7decda 2110 atmel_uart_writel(port, ATMEL_US_CR, rts_state);
1cf6e8fc
CP		 2111 }
2112
1e6c9c28 2113 /* set the baud rate */
4e7decda
CP		 2114 atmel_uart_writel(port, ATMEL_US_BRGR, quot);
2115 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
2116 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN);
1e6c9c28
AV		 2117
2118 /* restore interrupts */
4e7decda 2119 atmel_uart_writel(port, ATMEL_US_IER, imr);
1e6c9c28
AV		 2120
2121 /* CTS flow-control and modem-status interrupts */
2122 if (UART_ENABLE_MS(port, termios->c_cflag))
35b675b9
RG		 2123 atmel_enable_ms(port);
2124 else
2125 atmel_disable_ms(port);
1e6c9c28
AV		 2126
2127 spin_unlock_irqrestore(&port->lock, flags);
2128}
2129
732a84a0 2130static void atmel_set_ldisc(struct uart_port *port, struct ktermios *termios)
42bd7a4f 2131{
732a84a0 2132 if (termios->c_line == N_PPS) {
42bd7a4f 2133 port->flags |= UPF_HARDPPS_CD;
d41510ce 2134 spin_lock_irq(&port->lock);
42bd7a4f 2135 atmel_enable_ms(port);
d41510ce 2136 spin_unlock_irq(&port->lock);
42bd7a4f
VP		 2137 } else {
2138 port->flags &= ~UPF_HARDPPS_CD;
cab68f89
PH		 2139 if (!UART_ENABLE_MS(port, termios->c_cflag)) {
2140 spin_lock_irq(&port->lock);
2141 atmel_disable_ms(port);
2142 spin_unlock_irq(&port->lock);
2143 }
42bd7a4f
VP		 2144 }
2145}
2146
1e6c9c28
AV		 2147/*
2148 * Return string describing the specified port
2149 */
7192f92c 2150static const char *atmel_type(struct uart_port *port)
1e6c9c28 2151{
9ab4f88b 2152 return (port->type == PORT_ATMEL) ? "ATMEL_SERIAL" : NULL;
1e6c9c28
AV		 2153}
2154
2155/*
2156 * Release the memory region(s) being used by 'port'.
2157 */
7192f92c 2158static void atmel_release_port(struct uart_port *port)
1e6c9c28 2159{
afefc415
AV		 2160 struct platform_device *pdev = to_platform_device(port->dev);
2161 int size = pdev->resource[0].end - pdev->resource[0].start + 1;
2162
2163 release_mem_region(port->mapbase, size);
2164
2165 if (port->flags & UPF_IOREMAP) {
2166 iounmap(port->membase);
2167 port->membase = NULL;
2168 }
1e6c9c28
AV		 2169}
2170
2171/*
2172 * Request the memory region(s) being used by 'port'.
2173 */
7192f92c 2174static int atmel_request_port(struct uart_port *port)
1e6c9c28 2175{
afefc415
AV		 2176 struct platform_device *pdev = to_platform_device(port->dev);
2177 int size = pdev->resource[0].end - pdev->resource[0].start + 1;
2178
7192f92c 2179 if (!request_mem_region(port->mapbase, size, "atmel_serial"))
afefc415
AV		 2180 return -EBUSY;
2181
2182 if (port->flags & UPF_IOREMAP) {
2183 port->membase = ioremap(port->mapbase, size);
2184 if (port->membase == NULL) {
2185 release_mem_region(port->mapbase, size);
2186 return -ENOMEM;
2187 }
2188 }
1e6c9c28 2189
afefc415 2190 return 0;
1e6c9c28
AV		 2191}
2192
2193/*
2194 * Configure/autoconfigure the port.
2195 */
7192f92c 2196static void atmel_config_port(struct uart_port *port, int flags)
1e6c9c28
AV		 2197{
2198 if (flags & UART_CONFIG_TYPE) {
9ab4f88b 2199 port->type = PORT_ATMEL;
7192f92c 2200 atmel_request_port(port);
1e6c9c28
AV		 2201 }
2202}
2203
2204/*
2205 * Verify the new serial_struct (for TIOCSSERIAL).
2206 */
7192f92c 2207static int atmel_verify_port(struct uart_port *port, struct serial_struct *ser)
1e6c9c28
AV		 2208{
2209 int ret = 0;
9ab4f88b 2210 if (ser->type != PORT_UNKNOWN && ser->type != PORT_ATMEL)
1e6c9c28
AV		 2211 ret = -EINVAL;
2212 if (port->irq != ser->irq)
2213 ret = -EINVAL;
2214 if (ser->io_type != SERIAL_IO_MEM)
2215 ret = -EINVAL;
2216 if (port->uartclk / 16 != ser->baud_base)
2217 ret = -EINVAL;
270c2ade 2218 if (port->mapbase != (unsigned long)ser->iomem_base)
1e6c9c28
AV		 2219 ret = -EINVAL;
2220 if (port->iobase != ser->port)
2221 ret = -EINVAL;
2222 if (ser->hub6 != 0)
2223 ret = -EINVAL;
2224 return ret;
2225}
2226
8fe2d541
AT		 2227#ifdef CONFIG_CONSOLE_POLL
2228static int atmel_poll_get_char(struct uart_port *port)
2229{
4e7decda 2230 while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_RXRDY))
8fe2d541
AT		 2231 cpu_relax();
2232
a6499435 2233 return atmel_uart_read_char(port);
8fe2d541
AT		 2234}
2235
2236static void atmel_poll_put_char(struct uart_port *port, unsigned char ch)
2237{
4e7decda 2238 while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXRDY))
8fe2d541
AT		 2239 cpu_relax();
2240
a6499435 2241 atmel_uart_write_char(port, ch);
8fe2d541
AT		 2242}
2243#endif
2244
7192f92c
HS		 2245static struct uart_ops atmel_pops = {
2246 .tx_empty = atmel_tx_empty,
2247 .set_mctrl = atmel_set_mctrl,
2248 .get_mctrl = atmel_get_mctrl,
2249 .stop_tx = atmel_stop_tx,
2250 .start_tx = atmel_start_tx,
2251 .stop_rx = atmel_stop_rx,
2252 .enable_ms = atmel_enable_ms,
2253 .break_ctl = atmel_break_ctl,
2254 .startup = atmel_startup,
2255 .shutdown = atmel_shutdown,
9afd561a 2256 .flush_buffer = atmel_flush_buffer,
7192f92c 2257 .set_termios = atmel_set_termios,
42bd7a4f 2258 .set_ldisc = atmel_set_ldisc,
7192f92c
HS		 2259 .type = atmel_type,
2260 .release_port = atmel_release_port,
2261 .request_port = atmel_request_port,
2262 .config_port = atmel_config_port,
2263 .verify_port = atmel_verify_port,
2264 .pm = atmel_serial_pm,
8fe2d541
AT		 2265#ifdef CONFIG_CONSOLE_POLL
2266 .poll_get_char = atmel_poll_get_char,
2267 .poll_put_char = atmel_poll_put_char,
2268#endif
1e6c9c28
AV		 2269};
2270
afefc415
AV		 2271/*
2272 * Configure the port from the platform device resource info.
2273 */
91f8c2d8 2274static int atmel_init_port(struct atmel_uart_port *atmel_port,
b843aa21 2275 struct platform_device *pdev)
1e6c9c28 2276{
91f8c2d8 2277 int ret;
7192f92c 2278 struct uart_port *port = &atmel_port->uart;
574de559 2279 struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev);
afefc415 2280
4a1e8888
LZ		 2281 atmel_init_property(atmel_port, pdev);
2282 atmel_set_ops(port);
afefc415 2283
13bd3e6f 2284 atmel_init_rs485(port, pdev);
a930e528 2285
e8faff73
CS		 2286 port->iotype = UPIO_MEM;
2287 port->flags = UPF_BOOT_AUTOCONF;
2288 port->ops = &atmel_pops;
2289 port->fifosize = 1;
e8faff73 2290 port->dev = &pdev->dev;
afefc415
AV		 2291 port->mapbase = pdev->resource[0].start;
2292 port->irq = pdev->resource[1].start;
13bd3e6f 2293 port->rs485_config = atmel_config_rs485;
afefc415 2294
1ecc26bd
RB		 2295 tasklet_init(&atmel_port->tasklet, atmel_tasklet_func,
2296 (unsigned long)port);
1e125786 2297 tasklet_disable(&atmel_port->tasklet);
1ecc26bd
RB		 2298
2299 memset(&atmel_port->rx_ring, 0, sizeof(atmel_port->rx_ring));
2300
5fbe46b6 2301 if (pdata && pdata->regs) {
75d35213 2302 /* Already mapped by setup code */
1acfc7ec 2303 port->membase = pdata->regs;
588edbf3 2304 } else {
afefc415
AV		 2305 port->flags |= UPF_IOREMAP;
2306 port->membase = NULL;
2307 }
1e6c9c28 2308
b843aa21
RB		 2309 /* for console, the clock could already be configured */
2310 if (!atmel_port->clk) {
7192f92c 2311 atmel_port->clk = clk_get(&pdev->dev, "usart");
91f8c2d8
BB		 2312 if (IS_ERR(atmel_port->clk)) {
2313 ret = PTR_ERR(atmel_port->clk);
2314 atmel_port->clk = NULL;
2315 return ret;
2316 }
2317 ret = clk_prepare_enable(atmel_port->clk);
2318 if (ret) {
2319 clk_put(atmel_port->clk);
2320 atmel_port->clk = NULL;
2321 return ret;
2322 }
7192f92c 2323 port->uartclk = clk_get_rate(atmel_port->clk);
91f8c2d8 2324 clk_disable_unprepare(atmel_port->clk);
06a7f058 2325 /* only enable clock when USART is in use */
afefc415 2326 }
a6670615 2327
e8faff73 2328 /* Use TXEMPTY for interrupt when rs485 else TXRDY or ENDTX|TXBUFE */
13bd3e6f 2329 if (port->rs485.flags & SER_RS485_ENABLED)
e8faff73 2330 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY;
64e22ebe 2331 else if (atmel_use_pdc_tx(port)) {
a6670615 2332 port->fifosize = PDC_BUFFER_SIZE;
e8faff73
CS		 2333 atmel_port->tx_done_mask = ATMEL_US_ENDTX | ATMEL_US_TXBUFE;
2334 } else {
2335 atmel_port->tx_done_mask = ATMEL_US_TXRDY;
2336 }
91f8c2d8
BB		 2337
2338 return 0;
1e6c9c28
AV		 2339}
2340
69f6a27b
JCPV		 2341struct platform_device *atmel_default_console_device; /* the serial console device */
2342
749c4e60 2343#ifdef CONFIG_SERIAL_ATMEL_CONSOLE
7192f92c 2344static void atmel_console_putchar(struct uart_port *port, int ch)
d358788f 2345{
4e7decda 2346 while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXRDY))
829dd811 2347 cpu_relax();
a6499435 2348 atmel_uart_write_char(port, ch);
d358788f 2349}
1e6c9c28
AV		 2350
2351/*
2352 * Interrupts are disabled on entering
2353 */
7192f92c 2354static void atmel_console_write(struct console *co, const char *s, u_int count)
1e6c9c28 2355{
7192f92c 2356 struct uart_port *port = &atmel_ports[co->index].uart;
e8faff73 2357 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
d358788f 2358 unsigned int status, imr;
39d4c922 2359 unsigned int pdc_tx;
1e6c9c28
AV		 2360
2361 /*
b843aa21 2362 * First, save IMR and then disable interrupts
1e6c9c28 2363 */
4e7decda
CP		 2364 imr = atmel_uart_readl(port, ATMEL_US_IMR);
2365 atmel_uart_writel(port, ATMEL_US_IDR,
2366 ATMEL_US_RXRDY | atmel_port->tx_done_mask);
1e6c9c28 2367
39d4c922 2368 /* Store PDC transmit status and disable it */
4e7decda
CP		 2369 pdc_tx = atmel_uart_readl(port, ATMEL_PDC_PTSR) & ATMEL_PDC_TXTEN;
2370 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS);
39d4c922 2371
7192f92c 2372 uart_console_write(port, s, count, atmel_console_putchar);
1e6c9c28
AV		 2373
2374 /*
b843aa21
RB		 2375 * Finally, wait for transmitter to become empty
2376 * and restore IMR
1e6c9c28
AV		 2377 */
2378 do {
4e7decda 2379 status = atmel_uart_readl(port, ATMEL_US_CSR);
7192f92c 2380 } while (!(status & ATMEL_US_TXRDY));
39d4c922
MP		 2381
2382 /* Restore PDC transmit status */
2383 if (pdc_tx)
4e7decda 2384 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
39d4c922 2385
b843aa21 2386 /* set interrupts back the way they were */
4e7decda 2387 atmel_uart_writel(port, ATMEL_US_IER, imr);
1e6c9c28
AV		 2388}
2389
2390/*
b843aa21
RB		 2391 * If the port was already initialised (eg, by a boot loader),
2392 * try to determine the current setup.
1e6c9c28 2393 */
b843aa21
RB		 2394static void __init atmel_console_get_options(struct uart_port *port, int *baud,
2395 int *parity, int *bits)
1e6c9c28
AV		 2396{
2397 unsigned int mr, quot;
2398
1c0fd82f
HS		 2399 /*
2400 * If the baud rate generator isn't running, the port wasn't
2401 * initialized by the boot loader.
2402 */
4e7decda 2403 quot = atmel_uart_readl(port, ATMEL_US_BRGR) & ATMEL_US_CD;
1c0fd82f
HS		 2404 if (!quot)
2405 return;
1e6c9c28 2406
4e7decda 2407 mr = atmel_uart_readl(port, ATMEL_US_MR) & ATMEL_US_CHRL;
7192f92c 2408 if (mr == ATMEL_US_CHRL_8)
1e6c9c28
AV		 2409 *bits = 8;
2410 else
2411 *bits = 7;
2412
4e7decda 2413 mr = atmel_uart_readl(port, ATMEL_US_MR) & ATMEL_US_PAR;
7192f92c 2414 if (mr == ATMEL_US_PAR_EVEN)
1e6c9c28 2415 *parity = 'e';
7192f92c 2416 else if (mr == ATMEL_US_PAR_ODD)
1e6c9c28
AV		 2417 *parity = 'o';
2418
4d5e392c
HS		 2419 /*
2420 * The serial core only rounds down when matching this to a
2421 * supported baud rate. Make sure we don't end up slightly
2422 * lower than one of those, as it would make us fall through
2423 * to a much lower baud rate than we really want.
2424 */
4d5e392c 2425 *baud = port->uartclk / (16 * (quot - 1));
1e6c9c28
AV		 2426}
2427
7192f92c 2428static int __init atmel_console_setup(struct console *co, char *options)
1e6c9c28 2429{
91f8c2d8 2430 int ret;
7192f92c 2431 struct uart_port *port = &atmel_ports[co->index].uart;
1e6c9c28
AV		 2432 int baud = 115200;
2433 int bits = 8;
2434 int parity = 'n';
2435 int flow = 'n';
2436
b843aa21
RB		 2437 if (port->membase == NULL) {
2438 /* Port not initialized yet - delay setup */
afefc415 2439 return -ENODEV;
b843aa21 2440 }
1e6c9c28 2441
91f8c2d8
BB		 2442 ret = clk_prepare_enable(atmel_ports[co->index].clk);
2443 if (ret)
2444 return ret;
06a7f058 2445
4e7decda
CP		 2446 atmel_uart_writel(port, ATMEL_US_IDR, -1);
2447 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
2448 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN);
1e6c9c28
AV		 2449
2450 if (options)
2451 uart_parse_options(options, &baud, &parity, &bits, &flow);
2452 else
7192f92c 2453 atmel_console_get_options(port, &baud, &parity, &bits);
1e6c9c28
AV		 2454
2455 return uart_set_options(port, co, baud, parity, bits, flow);
2456}
2457
7192f92c 2458static struct uart_driver atmel_uart;
1e6c9c28 2459
7192f92c
HS		 2460static struct console atmel_console = {
2461 .name = ATMEL_DEVICENAME,
2462 .write = atmel_console_write,
1e6c9c28 2463 .device = uart_console_device,
7192f92c 2464 .setup = atmel_console_setup,
1e6c9c28
AV		 2465 .flags = CON_PRINTBUFFER,
2466 .index = -1,
7192f92c 2467 .data = &atmel_uart,
1e6c9c28
AV		 2468};
2469
06a7f058 2470#define ATMEL_CONSOLE_DEVICE (&atmel_console)
1e6c9c28 2471
afefc415
AV		 2472/*
2473 * Early console initialization (before VM subsystem initialized).
2474 */
7192f92c 2475static int __init atmel_console_init(void)
1e6c9c28 2476{
91f8c2d8 2477 int ret;
73e2798b 2478 if (atmel_default_console_device) {
0d0a3cc1 2479 struct atmel_uart_data *pdata =
574de559 2480 dev_get_platdata(&atmel_default_console_device->dev);
efb8d21b 2481 int id = pdata->num;
b78cd169 2482 struct atmel_uart_port *atmel_port = &atmel_ports[id];
4cbf9f48 2483
b78cd169
JA		 2484 atmel_port->backup_imr = 0;
2485 atmel_port->uart.line = id;
0d0a3cc1 2486
4cbf9f48 2487 add_preferred_console(ATMEL_DEVICENAME, id, NULL);
b78cd169 2488 ret = atmel_init_port(atmel_port, atmel_default_console_device);
91f8c2d8
BB		 2489 if (ret)
2490 return ret;
7192f92c 2491 register_console(&atmel_console);
afefc415 2492 }
1e6c9c28 2493
1e6c9c28
AV		 2494 return 0;
2495}
b843aa21 2496
7192f92c 2497console_initcall(atmel_console_init);
1e6c9c28 2498
afefc415
AV		 2499/*
2500 * Late console initialization.
2501 */
7192f92c 2502static int __init atmel_late_console_init(void)
afefc415 2503{
b843aa21
RB		 2504 if (atmel_default_console_device
2505 && !(atmel_console.flags & CON_ENABLED))
7192f92c 2506 register_console(&atmel_console);
afefc415
AV		 2507
2508 return 0;
2509}
b843aa21 2510
7192f92c 2511core_initcall(atmel_late_console_init);
afefc415 2512
dfa7f343
HS		 2513static inline bool atmel_is_console_port(struct uart_port *port)
2514{
2515 return port->cons && port->cons->index == port->line;
2516}
2517
1e6c9c28 2518#else
7192f92c 2519#define ATMEL_CONSOLE_DEVICE NULL
dfa7f343
HS		 2520
2521static inline bool atmel_is_console_port(struct uart_port *port)
2522{
2523 return false;
2524}
1e6c9c28
AV		 2525#endif
2526
7192f92c 2527static struct uart_driver atmel_uart = {
b843aa21
RB		 2528 .owner = THIS_MODULE,
2529 .driver_name = "atmel_serial",
2530 .dev_name = ATMEL_DEVICENAME,
2531 .major = SERIAL_ATMEL_MAJOR,
2532 .minor = MINOR_START,
2533 .nr = ATMEL_MAX_UART,
2534 .cons = ATMEL_CONSOLE_DEVICE,
1e6c9c28
AV		 2535};
2536
afefc415 2537#ifdef CONFIG_PM
f826caa4
HS		 2538static bool atmel_serial_clk_will_stop(void)
2539{
2540#ifdef CONFIG_ARCH_AT91
2541 return at91_suspend_entering_slow_clock();
2542#else
2543 return false;
2544#endif
2545}
2546
b843aa21
RB		 2547static int atmel_serial_suspend(struct platform_device *pdev,
2548 pm_message_t state)
1e6c9c28 2549{
afefc415 2550 struct uart_port *port = platform_get_drvdata(pdev);
c811ab8c 2551 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
afefc415 2552
e1c609ef
HS		 2553 if (atmel_is_console_port(port) && console_suspend_enabled) {
2554 /* Drain the TX shifter */
4e7decda
CP		 2555 while (!(atmel_uart_readl(port, ATMEL_US_CSR) &
2556 ATMEL_US_TXEMPTY))
e1c609ef
HS		 2557 cpu_relax();
2558 }
2559
f05596db
AS		 2560 /* we can not wake up if we're running on slow clock */
2561 atmel_port->may_wakeup = device_may_wakeup(&pdev->dev);
2c7af5ba
BB		 2562 if (atmel_serial_clk_will_stop()) {
2563 unsigned long flags;
2564
2565 spin_lock_irqsave(&atmel_port->lock_suspended, flags);
2566 atmel_port->suspended = true;
2567 spin_unlock_irqrestore(&atmel_port->lock_suspended, flags);
f05596db 2568 device_set_wakeup_enable(&pdev->dev, 0);
2c7af5ba 2569 }
f05596db
AS		 2570
2571 uart_suspend_port(&atmel_uart, port);
1e6c9c28 2572
afefc415
AV		 2573 return 0;
2574}
1e6c9c28 2575
7192f92c 2576static int atmel_serial_resume(struct platform_device *pdev)
afefc415
AV		 2577{
2578 struct uart_port *port = platform_get_drvdata(pdev);
c811ab8c 2579 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2c7af5ba
BB		 2580 unsigned long flags;
2581
2582 spin_lock_irqsave(&atmel_port->lock_suspended, flags);
2583 if (atmel_port->pending) {
2584 atmel_handle_receive(port, atmel_port->pending);
2585 atmel_handle_status(port, atmel_port->pending,
2586 atmel_port->pending_status);
2587 atmel_handle_transmit(port, atmel_port->pending);
2588 atmel_port->pending = 0;
2589 }
2590 atmel_port->suspended = false;
2591 spin_unlock_irqrestore(&atmel_port->lock_suspended, flags);
1e6c9c28 2592
f05596db
AS		 2593 uart_resume_port(&atmel_uart, port);
2594 device_set_wakeup_enable(&pdev->dev, atmel_port->may_wakeup);
1e6c9c28
AV		 2595
2596 return 0;
2597}
afefc415 2598#else
7192f92c
HS		 2599#define atmel_serial_suspend NULL
2600#define atmel_serial_resume NULL
afefc415 2601#endif
1e6c9c28 2602
b78cd169 2603static void atmel_serial_probe_fifos(struct atmel_uart_port *atmel_port,
b5199d46
CP		 2604 struct platform_device *pdev)
2605{
b78cd169
JA		 2606 atmel_port->fifo_size = 0;
2607 atmel_port->rts_low = 0;
2608 atmel_port->rts_high = 0;
b5199d46
CP		 2609
2610 if (of_property_read_u32(pdev->dev.of_node,
2611 "atmel,fifo-size",
b78cd169 2612 &atmel_port->fifo_size))
b5199d46
CP		 2613 return;
2614
b78cd169 2615 if (!atmel_port->fifo_size)
b5199d46
CP		 2616 return;
2617
b78cd169
JA		 2618 if (atmel_port->fifo_size < ATMEL_MIN_FIFO_SIZE) {
2619 atmel_port->fifo_size = 0;
b5199d46
CP		 2620 dev_err(&pdev->dev, "Invalid FIFO size\n");
2621 return;
2622 }
2623
2624 /*
2625 * 0 <= rts_low <= rts_high <= fifo_size
2626 * Once their CTS line asserted by the remote peer, some x86 UARTs tend
2627 * to flush their internal TX FIFO, commonly up to 16 data, before
2628 * actually stopping to send new data. So we try to set the RTS High
2629 * Threshold to a reasonably high value respecting this 16 data
2630 * empirical rule when possible.
2631 */
b78cd169
JA		 2632 atmel_port->rts_high = max_t(int, atmel_port->fifo_size >> 1,
2633 atmel_port->fifo_size - ATMEL_RTS_HIGH_OFFSET);
2634 atmel_port->rts_low = max_t(int, atmel_port->fifo_size >> 2,
2635 atmel_port->fifo_size - ATMEL_RTS_LOW_OFFSET);
b5199d46
CP		 2636
2637 dev_info(&pdev->dev, "Using FIFO (%u data)\n",
b78cd169 2638 atmel_port->fifo_size);
b5199d46 2639 dev_dbg(&pdev->dev, "RTS High Threshold : %2u data\n",
b78cd169 2640 atmel_port->rts_high);
b5199d46 2641 dev_dbg(&pdev->dev, "RTS Low Threshold : %2u data\n",
b78cd169 2642 atmel_port->rts_low);
b5199d46
CP		 2643}
2644
9671f099 2645static int atmel_serial_probe(struct platform_device *pdev)
1e6c9c28 2646{
b78cd169 2647 struct atmel_uart_port *atmel_port;
5fbe46b6 2648 struct device_node *np = pdev->dev.of_node;
574de559 2649 struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev);
1ecc26bd 2650 void *data;
4cbf9f48 2651 int ret = -ENODEV;
bd737f87 2652 bool rs485_enabled;
1e6c9c28 2653
9d09daf8 2654 BUILD_BUG_ON(ATMEL_SERIAL_RINGSIZE & (ATMEL_SERIAL_RINGSIZE - 1));
1ecc26bd 2655
5fbe46b6
NF		 2656 if (np)
2657 ret = of_alias_get_id(np, "serial");
2658 else
2659 if (pdata)
2660 ret = pdata->num;
4cbf9f48
NF		 2661
2662 if (ret < 0)
5fbe46b6 2663 /* port id not found in platform data nor device-tree aliases:
4cbf9f48 2664 * auto-enumerate it */
503bded9 2665 ret = find_first_zero_bit(atmel_ports_in_use, ATMEL_MAX_UART);
4cbf9f48 2666
503bded9 2667 if (ret >= ATMEL_MAX_UART) {
4cbf9f48
NF		 2668 ret = -ENODEV;
2669 goto err;
2670 }
2671
503bded9 2672 if (test_and_set_bit(ret, atmel_ports_in_use)) {
4cbf9f48
NF		 2673 /* port already in use */
2674 ret = -EBUSY;
2675 goto err;
2676 }
2677
b78cd169
JA		 2678 atmel_port = &atmel_ports[ret];
2679 atmel_port->backup_imr = 0;
2680 atmel_port->uart.line = ret;
2681 atmel_serial_probe_fifos(atmel_port, pdev);
e0b0baad 2682
b78cd169 2683 spin_lock_init(&atmel_port->lock_suspended);
2c7af5ba 2684
b78cd169 2685 ret = atmel_init_port(atmel_port, pdev);
91f8c2d8 2686 if (ret)
6fbb9bdf 2687 goto err_clear_bit;
1e6c9c28 2688
b78cd169
JA		 2689 atmel_port->gpios = mctrl_gpio_init(&atmel_port->uart, 0);
2690 if (IS_ERR(atmel_port->gpios)) {
2691 ret = PTR_ERR(atmel_port->gpios);
18dfef9c
UKK		 2692 goto err_clear_bit;
2693 }
2694
b78cd169 2695 if (!atmel_use_pdc_rx(&atmel_port->uart)) {
a6670615 2696 ret = -ENOMEM;
6433471d
HS		 2697 data = kmalloc(sizeof(struct atmel_uart_char)
2698 * ATMEL_SERIAL_RINGSIZE, GFP_KERNEL);
a6670615
CC		 2699 if (!data)
2700 goto err_alloc_ring;
b78cd169 2701 atmel_port->rx_ring.buf = data;
a6670615 2702 }
1ecc26bd 2703
b78cd169 2704 rs485_enabled = atmel_port->uart.rs485.flags & SER_RS485_ENABLED;
bd737f87 2705
b78cd169 2706 ret = uart_add_one_port(&atmel_uart, &atmel_port->uart);
dfa7f343
HS		 2707 if (ret)
2708 goto err_add_port;
2709
8da14b5f 2710#ifdef CONFIG_SERIAL_ATMEL_CONSOLE
b78cd169 2711 if (atmel_is_console_port(&atmel_port->uart)
06a7f058
DB		 2712 && ATMEL_CONSOLE_DEVICE->flags & CON_ENABLED) {
2713 /*
2714 * The serial core enabled the clock for us, so undo
91f8c2d8 2715 * the clk_prepare_enable() in atmel_console_setup()
06a7f058 2716 */
b78cd169 2717 clk_disable_unprepare(atmel_port->clk);
06a7f058 2718 }
8da14b5f 2719#endif
06a7f058 2720
dfa7f343 2721 device_init_wakeup(&pdev->dev, 1);
b78cd169 2722 platform_set_drvdata(pdev, atmel_port);
dfa7f343 2723
d4f64187
CP		 2724 /*
2725 * The peripheral clock has been disabled by atmel_init_port():
2726 * enable it before accessing I/O registers
2727 */
b78cd169 2728 clk_prepare_enable(atmel_port->clk);
d4f64187 2729
bd737f87 2730 if (rs485_enabled) {
b78cd169 2731 atmel_uart_writel(&atmel_port->uart, ATMEL_US_MR,
4e7decda 2732 ATMEL_US_USMODE_NORMAL);
b78cd169
JA		 2733 atmel_uart_writel(&atmel_port->uart, ATMEL_US_CR,
2734 ATMEL_US_RTSEN);
5dfbd1d7
CS		 2735 }
2736
055560b0
ES		 2737 /*
2738 * Get port name of usart or uart
2739 */
b78cd169 2740 atmel_get_ip_name(&atmel_port->uart);
055560b0 2741
d4f64187
CP		 2742 /*
2743 * The peripheral clock can now safely be disabled till the port
2744 * is used
2745 */
b78cd169 2746 clk_disable_unprepare(atmel_port->clk);
d4f64187 2747
dfa7f343
HS		 2748 return 0;
2749
2750err_add_port:
b78cd169
JA		 2751 kfree(atmel_port->rx_ring.buf);
2752 atmel_port->rx_ring.buf = NULL;
1ecc26bd 2753err_alloc_ring:
b78cd169
JA		 2754 if (!atmel_is_console_port(&atmel_port->uart)) {
2755 clk_put(atmel_port->clk);
2756 atmel_port->clk = NULL;
afefc415 2757 }
6fbb9bdf 2758err_clear_bit:
b78cd169 2759 clear_bit(atmel_port->uart.line, atmel_ports_in_use);
4cbf9f48 2760err:
afefc415
AV		 2761 return ret;
2762}
2763
7192f92c
HS		 2764static struct platform_driver atmel_serial_driver = {
2765 .probe = atmel_serial_probe,
7192f92c
HS		 2766 .suspend = atmel_serial_suspend,
2767 .resume = atmel_serial_resume,
afefc415 2768 .driver = {
c39dfebc
PG		 2769 .name = "atmel_usart",
2770 .of_match_table = of_match_ptr(atmel_serial_dt_ids),
2771 .suppress_bind_attrs = true,
afefc415
AV		 2772 },
2773};
2774
7192f92c 2775static int __init atmel_serial_init(void)
afefc415
AV		 2776{
2777 int ret;
2778
7192f92c 2779 ret = uart_register_driver(&atmel_uart);
afefc415
AV		 2780 if (ret)
2781 return ret;
2782
7192f92c 2783 ret = platform_driver_register(&atmel_serial_driver);
afefc415 2784 if (ret)
7192f92c 2785 uart_unregister_driver(&atmel_uart);
afefc415
AV		 2786
2787 return ret;
2788}
c39dfebc 2789device_initcall(atmel_serial_init);
Linux 6.x block layer and io_uring tree(s)