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serial: arc: Use uart_xmit_advance()
[linux-block.git] / drivers / tty / serial / atmel_serial.c
CommitLineData
e3b3d0f5 1// SPDX-License-Identifier: GPL-2.0+
1e6c9c28 2/*
72ce5732 3 * Driver for Atmel AT91 Serial ports
1e6c9c28
AV		 4 * Copyright (C) 2003 Rick Bronson
5 *
6 * Based on drivers/char/serial_sa1100.c, by Deep Blue Solutions Ltd.
7 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
8 *
a6670615 9 * DMA support added by Chip Coldwell.
1e6c9c28 10 */
702d10a0 11#include <linux/circ_buf.h>
1e6c9c28
AV		 12#include <linux/tty.h>
13#include <linux/ioport.h>
14#include <linux/slab.h>
15#include <linux/init.h>
16#include <linux/serial.h>
afefc415 17#include <linux/clk.h>
5e3ce1f2 18#include <linux/clk-provider.h>
1e6c9c28
AV		 19#include <linux/console.h>
20#include <linux/sysrq.h>
21#include <linux/tty_flip.h>
afefc415 22#include <linux/platform_device.h>
5fbe46b6
NF		 23#include <linux/of.h>
24#include <linux/of_device.h>
a6670615 25#include <linux/dma-mapping.h>
6b997bab 26#include <linux/dmaengine.h>
93a3ddc2 27#include <linux/atmel_pdc.h>
e8faff73 28#include <linux/uaccess.h>
bcd2360c 29#include <linux/platform_data/atmel.h>
2e68c22f 30#include <linux/timer.h>
e0b0baad 31#include <linux/err.h>
ab5e4e41 32#include <linux/irq.h>
2c7af5ba 33#include <linux/suspend.h>
2b5cf14b 34#include <linux/mm.h>
635b2589 35#include <linux/io.h>
1e6c9c28 36
377fedd1 37#include <asm/div64.h>
f7512e7c 38#include <asm/ioctls.h>
1e6c9c28 39
a6670615
CC		 40#define PDC_BUFFER_SIZE 512
41/* Revisit: We should calculate this based on the actual port settings */
42#define PDC_RX_TIMEOUT (3 * 10) /* 3 bytes */
43
b5199d46
CP		 44/* The minium number of data FIFOs should be able to contain */
45#define ATMEL_MIN_FIFO_SIZE 8
46/*
47 * These two offsets are substracted from the RX FIFO size to define the RTS
48 * high and low thresholds
49 */
50#define ATMEL_RTS_HIGH_OFFSET 16
51#define ATMEL_RTS_LOW_OFFSET 20
52
1e6c9c28
AV		 53#include <linux/serial_core.h>
54
e0b0baad 55#include "serial_mctrl_gpio.h"
8961df89 56#include "atmel_serial.h"
e0b0baad 57
e8faff73
CS		 58static void atmel_start_rx(struct uart_port *port);
59static void atmel_stop_rx(struct uart_port *port);
60
749c4e60 61#ifdef CONFIG_SERIAL_ATMEL_TTYAT
1e6c9c28
AV		 62
63/* Use device name ttyAT, major 204 and minor 154-169. This is necessary if we
64 * should coexist with the 8250 driver, such as if we have an external 16C550
65 * UART. */
7192f92c 66#define SERIAL_ATMEL_MAJOR 204
1e6c9c28 67#define MINOR_START 154
7192f92c 68#define ATMEL_DEVICENAME "ttyAT"
1e6c9c28
AV		 69
70#else
71
72/* Use device name ttyS, major 4, minor 64-68. This is the usual serial port
73 * name, but it is legally reserved for the 8250 driver. */
7192f92c 74#define SERIAL_ATMEL_MAJOR TTY_MAJOR
1e6c9c28 75#define MINOR_START 64
7192f92c 76#define ATMEL_DEVICENAME "ttyS"
1e6c9c28
AV		 77
78#endif
79
7192f92c 80#define ATMEL_ISR_PASS_LIMIT 256
1e6c9c28 81
a6670615
CC		 82struct atmel_dma_buffer {
83 unsigned char *buf;
84 dma_addr_t dma_addr;
85 unsigned int dma_size;
86 unsigned int ofs;
87};
88
1ecc26bd
RB		 89struct atmel_uart_char {
90 u16 status;
91 u16 ch;
92};
93
637ba54f
LD		 94/*
95 * Be careful, the real size of the ring buffer is
96 * sizeof(atmel_uart_char) * ATMEL_SERIAL_RINGSIZE. It means that ring buffer
97 * can contain up to 1024 characters in PIO mode and up to 4096 characters in
98 * DMA mode.
99 */
1ecc26bd
RB		 100#define ATMEL_SERIAL_RINGSIZE 1024
101
9af92fbf
AB		 102/*
103 * at91: 6 USARTs and one DBGU port (SAM9260)
432f9748 104 * samx7: 3 USARTs and 5 UARTs
9af92fbf 105 */
432f9748 106#define ATMEL_MAX_UART 8
9af92fbf 107
afefc415
AV		 108/*
109 * We wrap our port structure around the generic uart_port.
110 */
7192f92c 111struct atmel_uart_port {
afefc415
AV		 112 struct uart_port uart; /* uart */
113 struct clk *clk; /* uart clock */
5e3ce1f2 114 struct clk *gclk; /* uart generic clock */
f05596db
AS		 115 int may_wakeup; /* cached value of device_may_wakeup for times we need to disable it */
116 u32 backup_imr; /* IMR saved during suspend */
9e6077bd 117 int break_active; /* break being received */
1ecc26bd 118
34df42f5 119 bool use_dma_rx; /* enable DMA receiver */
64e22ebe 120 bool use_pdc_rx; /* enable PDC receiver */
a6670615
CC		 121 short pdc_rx_idx; /* current PDC RX buffer */
122 struct atmel_dma_buffer pdc_rx[2]; /* PDC receier */
123
08f738be 124 bool use_dma_tx; /* enable DMA transmitter */
64e22ebe 125 bool use_pdc_tx; /* enable PDC transmitter */
a6670615
CC		 126 struct atmel_dma_buffer pdc_tx; /* PDC transmitter */
127
08f738be 128 spinlock_t lock_tx; /* port lock */
34df42f5 129 spinlock_t lock_rx; /* port lock */
08f738be 130 struct dma_chan *chan_tx;
34df42f5 131 struct dma_chan *chan_rx;
08f738be 132 struct dma_async_tx_descriptor *desc_tx;
34df42f5 133 struct dma_async_tx_descriptor *desc_rx;
08f738be 134 dma_cookie_t cookie_tx;
34df42f5 135 dma_cookie_t cookie_rx;
08f738be 136 struct scatterlist sg_tx;
34df42f5 137 struct scatterlist sg_rx;
00e8e658
NF		 138 struct tasklet_struct tasklet_rx;
139 struct tasklet_struct tasklet_tx;
98f2082c 140 atomic_t tasklet_shutdown;
1ecc26bd 141 unsigned int irq_status_prev;
5f258b3e 142 unsigned int tx_len;
1ecc26bd
RB		 143
144 struct circ_buf rx_ring;
e8faff73 145
e0b0baad 146 struct mctrl_gpios *gpios;
377fedd1
NF		 147 u32 backup_mode; /* MR saved during iso7816 operations */
148 u32 backup_brgr; /* BRGR saved during iso7816 operations */
e8faff73 149 unsigned int tx_done_mask;
b5199d46
CP		 150 u32 fifo_size;
151 u32 rts_high;
152 u32 rts_low;
ab5e4e41 153 bool ms_irq_enabled;
2958ccee 154 u32 rtor; /* address of receiver timeout register if it exists */
5644bf18 155 bool is_usart;
5bf5635a 156 bool has_frac_baudrate;
4b769371
NF		 157 bool has_hw_timer;
158 struct timer_list uart_timer;
2c7af5ba 159
ea04f82a 160 bool tx_stopped;
2c7af5ba
BB		 161 bool suspended;
162 unsigned int pending;
163 unsigned int pending_status;
164 spinlock_t lock_suspended;
165
69646d7a
RS		 166 bool hd_start_rx; /* can start RX during half-duplex operation */
167
377fedd1
NF		 168 /* ISO7816 */
169 unsigned int fidi_min;
170 unsigned int fidi_max;
171
6a5f0e2f
AB		 172 struct {
173 u32 cr;
174 u32 mr;
175 u32 imr;
176 u32 brgr;
177 u32 rtor;
178 u32 ttgr;
179 u32 fmr;
180 u32 fimr;
181 } cache;
182
a930e528
ES		 183 int (*prepare_rx)(struct uart_port *port);
184 int (*prepare_tx)(struct uart_port *port);
185 void (*schedule_rx)(struct uart_port *port);
186 void (*schedule_tx)(struct uart_port *port);
187 void (*release_rx)(struct uart_port *port);
188 void (*release_tx)(struct uart_port *port);
afefc415
AV		 189};
190
7192f92c 191static struct atmel_uart_port atmel_ports[ATMEL_MAX_UART];
503bded9 192static DECLARE_BITMAP(atmel_ports_in_use, ATMEL_MAX_UART);
afefc415 193
5fbe46b6
NF		 194#if defined(CONFIG_OF)
195static const struct of_device_id atmel_serial_dt_ids[] = {
c24d2531 196 { .compatible = "atmel,at91rm9200-usart-serial" },
5fbe46b6
NF		 197 { /* sentinel */ }
198};
5fbe46b6
NF		 199#endif
200
c811ab8c
HS		 201static inline struct atmel_uart_port *
202to_atmel_uart_port(struct uart_port *uart)
203{
204 return container_of(uart, struct atmel_uart_port, uart);
205}
206
4e7decda
CP		 207static inline u32 atmel_uart_readl(struct uart_port *port, u32 reg)
208{
209 return __raw_readl(port->membase + reg);
210}
211
212static inline void atmel_uart_writel(struct uart_port *port, u32 reg, u32 value)
213{
214 __raw_writel(value, port->membase + reg);
215}
216
a6499435 217static inline u8 atmel_uart_read_char(struct uart_port *port)
b5199d46 218{
a6499435 219 return __raw_readb(port->membase + ATMEL_US_RHR);
b5199d46
CP		 220}
221
a6499435
CP		 222static inline void atmel_uart_write_char(struct uart_port *port, u8 value)
223{
224 __raw_writeb(value, port->membase + ATMEL_US_THR);
225}
226
f3040983
RS		 227static inline int atmel_uart_is_half_duplex(struct uart_port *port)
228{
229 return ((port->rs485.flags & SER_RS485_ENABLED) &&
230 !(port->rs485.flags & SER_RS485_RX_DURING_TX)) ||
231 (port->iso7816.flags & SER_ISO7816_ENABLED);
232}
233
5e3ce1f2
SM		 234static inline int atmel_error_rate(int desired_value, int actual_value)
235{
236 return 100 - (desired_value * 100) / actual_value;
237}
238
a6670615 239#ifdef CONFIG_SERIAL_ATMEL_PDC
64e22ebe 240static bool atmel_use_pdc_rx(struct uart_port *port)
a6670615 241{
c811ab8c 242 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
a6670615 243
64e22ebe 244 return atmel_port->use_pdc_rx;
a6670615
CC		 245}
246
64e22ebe 247static bool atmel_use_pdc_tx(struct uart_port *port)
a6670615 248{
c811ab8c 249 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
a6670615 250
64e22ebe 251 return atmel_port->use_pdc_tx;
a6670615
CC		 252}
253#else
64e22ebe 254static bool atmel_use_pdc_rx(struct uart_port *port)
a6670615
CC		 255{
256 return false;
257}
258
64e22ebe 259static bool atmel_use_pdc_tx(struct uart_port *port)
a6670615
CC		 260{
261 return false;
262}
263#endif
264
08f738be
ES		 265static bool atmel_use_dma_tx(struct uart_port *port)
266{
267 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
268
269 return atmel_port->use_dma_tx;
270}
271
34df42f5
ES		 272static bool atmel_use_dma_rx(struct uart_port *port)
273{
274 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
275
276 return atmel_port->use_dma_rx;
277}
278
5be605ac
AB		 279static bool atmel_use_fifo(struct uart_port *port)
280{
281 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
282
283 return atmel_port->fifo_size;
284}
285
98f2082c
NF		 286static void atmel_tasklet_schedule(struct atmel_uart_port *atmel_port,
287 struct tasklet_struct *t)
288{
289 if (!atomic_read(&atmel_port->tasklet_shutdown))
290 tasklet_schedule(t);
291}
292
e8faff73 293/* Enable or disable the rs485 support */
ae50bb27 294static int atmel_config_rs485(struct uart_port *port, struct ktermios *termios,
13bd3e6f 295 struct serial_rs485 *rs485conf)
e8faff73
CS		 296{
297 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
298 unsigned int mode;
e8faff73
CS		 299
300 /* Disable interrupts */
4e7decda 301 atmel_uart_writel(port, ATMEL_US_IDR, atmel_port->tx_done_mask);
e8faff73 302
4e7decda 303 mode = atmel_uart_readl(port, ATMEL_US_MR);
e8faff73 304
e8faff73
CS		 305 if (rs485conf->flags & SER_RS485_ENABLED) {
306 dev_dbg(port->dev, "Setting UART to RS485\n");
60efd051 307 if (rs485conf->flags & SER_RS485_RX_DURING_TX)
477b8383
CC		 308 atmel_port->tx_done_mask = ATMEL_US_TXRDY;
309 else
310 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY;
311
4e7decda
CP		 312 atmel_uart_writel(port, ATMEL_US_TTGR,
313 rs485conf->delay_rts_after_send);
692a8ebc 314 mode &= ~ATMEL_US_USMODE;
e8faff73
CS		 315 mode |= ATMEL_US_USMODE_RS485;
316 } else {
317 dev_dbg(port->dev, "Setting UART to RS232\n");
64e22ebe 318 if (atmel_use_pdc_tx(port))
e8faff73
CS		 319 atmel_port->tx_done_mask = ATMEL_US_ENDTX |
320 ATMEL_US_TXBUFE;
321 else
322 atmel_port->tx_done_mask = ATMEL_US_TXRDY;
323 }
4e7decda 324 atmel_uart_writel(port, ATMEL_US_MR, mode);
e8faff73
CS		 325
326 /* Enable interrupts */
4e7decda 327 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->tx_done_mask);
e8faff73 328
13bd3e6f 329 return 0;
e8faff73
CS		 330}
331
377fedd1
NF		 332static unsigned int atmel_calc_cd(struct uart_port *port,
333 struct serial_iso7816 *iso7816conf)
334{
335 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
336 unsigned int cd;
337 u64 mck_rate;
338
339 mck_rate = (u64)clk_get_rate(atmel_port->clk);
340 do_div(mck_rate, iso7816conf->clk);
341 cd = mck_rate;
342 return cd;
343}
344
345static unsigned int atmel_calc_fidi(struct uart_port *port,
346 struct serial_iso7816 *iso7816conf)
347{
348 u64 fidi = 0;
349
350 if (iso7816conf->sc_fi && iso7816conf->sc_di) {
351 fidi = (u64)iso7816conf->sc_fi;
352 do_div(fidi, iso7816conf->sc_di);
353 }
354 return (u32)fidi;
355}
356
357/* Enable or disable the iso7816 support */
358/* Called with interrupts disabled */
359static int atmel_config_iso7816(struct uart_port *port,
360 struct serial_iso7816 *iso7816conf)
361{
362 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
363 unsigned int mode;
364 unsigned int cd, fidi;
365 int ret = 0;
366
367 /* Disable interrupts */
368 atmel_uart_writel(port, ATMEL_US_IDR, atmel_port->tx_done_mask);
369
370 mode = atmel_uart_readl(port, ATMEL_US_MR);
371
372 if (iso7816conf->flags & SER_ISO7816_ENABLED) {
373 mode &= ~ATMEL_US_USMODE;
374
375 if (iso7816conf->tg > 255) {
376 dev_err(port->dev, "ISO7816: Timeguard exceeding 255\n");
377 memset(iso7816conf, 0, sizeof(struct serial_iso7816));
378 ret = -EINVAL;
379 goto err_out;
380 }
381
382 if ((iso7816conf->flags & SER_ISO7816_T_PARAM)
383 == SER_ISO7816_T(0)) {
384 mode |= ATMEL_US_USMODE_ISO7816_T0 | ATMEL_US_DSNACK;
385 } else if ((iso7816conf->flags & SER_ISO7816_T_PARAM)
386 == SER_ISO7816_T(1)) {
387 mode |= ATMEL_US_USMODE_ISO7816_T1 | ATMEL_US_INACK;
388 } else {
389 dev_err(port->dev, "ISO7816: Type not supported\n");
390 memset(iso7816conf, 0, sizeof(struct serial_iso7816));
391 ret = -EINVAL;
392 goto err_out;
393 }
394
395 mode &= ~(ATMEL_US_USCLKS | ATMEL_US_NBSTOP | ATMEL_US_PAR);
396
397 /* select mck clock, and output */
398 mode |= ATMEL_US_USCLKS_MCK | ATMEL_US_CLKO;
399 /* set parity for normal/inverse mode + max iterations */
400 mode |= ATMEL_US_PAR_EVEN | ATMEL_US_NBSTOP_1 | ATMEL_US_MAX_ITER(3);
401
402 cd = atmel_calc_cd(port, iso7816conf);
403 fidi = atmel_calc_fidi(port, iso7816conf);
404 if (fidi == 0) {
405 dev_warn(port->dev, "ISO7816 fidi = 0, Generator generates no signal\n");
406 } else if (fidi < atmel_port->fidi_min
407 || fidi > atmel_port->fidi_max) {
408 dev_err(port->dev, "ISO7816 fidi = %u, value not supported\n", fidi);
409 memset(iso7816conf, 0, sizeof(struct serial_iso7816));
410 ret = -EINVAL;
411 goto err_out;
412 }
413
414 if (!(port->iso7816.flags & SER_ISO7816_ENABLED)) {
415 /* port not yet in iso7816 mode: store configuration */
416 atmel_port->backup_mode = atmel_uart_readl(port, ATMEL_US_MR);
417 atmel_port->backup_brgr = atmel_uart_readl(port, ATMEL_US_BRGR);
418 }
419
420 atmel_uart_writel(port, ATMEL_US_TTGR, iso7816conf->tg);
421 atmel_uart_writel(port, ATMEL_US_BRGR, cd);
422 atmel_uart_writel(port, ATMEL_US_FIDI, fidi);
423
424 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXDIS | ATMEL_US_RXEN);
425 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY | ATMEL_US_NACK | ATMEL_US_ITERATION;
426 } else {
427 dev_dbg(port->dev, "Setting UART back to RS232\n");
428 /* back to last RS232 settings */
429 mode = atmel_port->backup_mode;
430 memset(iso7816conf, 0, sizeof(struct serial_iso7816));
431 atmel_uart_writel(port, ATMEL_US_TTGR, 0);
432 atmel_uart_writel(port, ATMEL_US_BRGR, atmel_port->backup_brgr);
433 atmel_uart_writel(port, ATMEL_US_FIDI, 0x174);
434
435 if (atmel_use_pdc_tx(port))
436 atmel_port->tx_done_mask = ATMEL_US_ENDTX |
437 ATMEL_US_TXBUFE;
438 else
439 atmel_port->tx_done_mask = ATMEL_US_TXRDY;
440 }
441
442 port->iso7816 = *iso7816conf;
443
444 atmel_uart_writel(port, ATMEL_US_MR, mode);
445
446err_out:
447 /* Enable interrupts */
448 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->tx_done_mask);
449
450 return ret;
451}
452
1e6c9c28
AV		 453/*
454 * Return TIOCSER_TEMT when transmitter FIFO and Shift register is empty.
455 */
7192f92c 456static u_int atmel_tx_empty(struct uart_port *port)
1e6c9c28 457{
ea04f82a
RI		 458 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
459
460 if (atmel_port->tx_stopped)
461 return TIOCSER_TEMT;
4e7decda
CP		 462 return (atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXEMPTY) ?
463 TIOCSER_TEMT :
464 0;
1e6c9c28
AV		 465}
466
467/*
468 * Set state of the modem control output lines
469 */
7192f92c 470static void atmel_set_mctrl(struct uart_port *port, u_int mctrl)
1e6c9c28
AV		 471{
472 unsigned int control = 0;
4e7decda 473 unsigned int mode = atmel_uart_readl(port, ATMEL_US_MR);
1cf6e8fc 474 unsigned int rts_paused, rts_ready;
e8faff73 475 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1e6c9c28 476
1cf6e8fc
CP		 477 /* override mode to RS485 if needed, otherwise keep the current mode */
478 if (port->rs485.flags & SER_RS485_ENABLED) {
4e7decda
CP		 479 atmel_uart_writel(port, ATMEL_US_TTGR,
480 port->rs485.delay_rts_after_send);
1cf6e8fc
CP		 481 mode &= ~ATMEL_US_USMODE;
482 mode |= ATMEL_US_USMODE_RS485;
483 }
484
485 /* set the RTS line state according to the mode */
486 if ((mode & ATMEL_US_USMODE) == ATMEL_US_USMODE_HWHS) {
487 /* force RTS line to high level */
488 rts_paused = ATMEL_US_RTSEN;
489
490 /* give the control of the RTS line back to the hardware */
491 rts_ready = ATMEL_US_RTSDIS;
492 } else {
493 /* force RTS line to high level */
494 rts_paused = ATMEL_US_RTSDIS;
495
496 /* force RTS line to low level */
497 rts_ready = ATMEL_US_RTSEN;
498 }
499
1e6c9c28 500 if (mctrl & TIOCM_RTS)
1cf6e8fc 501 control |= rts_ready;
1e6c9c28 502 else
1cf6e8fc 503 control |= rts_paused;
1e6c9c28
AV		 504
505 if (mctrl & TIOCM_DTR)
7192f92c 506 control |= ATMEL_US_DTREN;
1e6c9c28 507 else
7192f92c 508 control |= ATMEL_US_DTRDIS;
1e6c9c28 509
4e7decda 510 atmel_uart_writel(port, ATMEL_US_CR, control);
afefc415 511
e0b0baad
RG		 512 mctrl_gpio_set(atmel_port->gpios, mctrl);
513
afefc415 514 /* Local loopback mode? */
1cf6e8fc 515 mode &= ~ATMEL_US_CHMODE;
afefc415 516 if (mctrl & TIOCM_LOOP)
7192f92c 517 mode |= ATMEL_US_CHMODE_LOC_LOOP;
afefc415 518 else
7192f92c 519 mode |= ATMEL_US_CHMODE_NORMAL;
e8faff73 520
4e7decda 521 atmel_uart_writel(port, ATMEL_US_MR, mode);
1e6c9c28
AV		 522}
523
524/*
525 * Get state of the modem control input lines
526 */
7192f92c 527static u_int atmel_get_mctrl(struct uart_port *port)
1e6c9c28 528{
e0b0baad
RG		 529 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
530 unsigned int ret = 0, status;
1e6c9c28 531
4e7decda 532 status = atmel_uart_readl(port, ATMEL_US_CSR);
1e6c9c28
AV		 533
534 /*
535 * The control signals are active low.
536 */
7192f92c 537 if (!(status & ATMEL_US_DCD))
1e6c9c28 538 ret |= TIOCM_CD;
7192f92c 539 if (!(status & ATMEL_US_CTS))
1e6c9c28 540 ret |= TIOCM_CTS;
7192f92c 541 if (!(status & ATMEL_US_DSR))
1e6c9c28 542 ret |= TIOCM_DSR;
7192f92c 543 if (!(status & ATMEL_US_RI))
1e6c9c28
AV		 544 ret |= TIOCM_RI;
545
e0b0baad 546 return mctrl_gpio_get(atmel_port->gpios, &ret);
1e6c9c28
AV		 547}
548
549/*
550 * Stop transmitting.
551 */
7192f92c 552static void atmel_stop_tx(struct uart_port *port)
1e6c9c28 553{
e8faff73
CS		 554 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
555
64e22ebe 556 if (atmel_use_pdc_tx(port)) {
a6670615 557 /* disable PDC transmit */
4e7decda 558 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS);
e8faff73 559 }
89d82324
RG		 560
561 /*
562 * Disable the transmitter.
563 * This is mandatory when DMA is used, otherwise the DMA buffer
564 * is fully transmitted.
565 */
566 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXDIS);
ea04f82a 567 atmel_port->tx_stopped = true;
89d82324 568
e8faff73 569 /* Disable interrupts */
4e7decda 570 atmel_uart_writel(port, ATMEL_US_IDR, atmel_port->tx_done_mask);
e8faff73 571
f3040983 572 if (atmel_uart_is_half_duplex(port))
04b5bfe3
NF		 573 if (!atomic_read(&atmel_port->tasklet_shutdown))
574 atmel_start_rx(port);
f3040983 575
1e6c9c28
AV		 576}
577
578/*
579 * Start transmitting.
580 */
7192f92c 581static void atmel_start_tx(struct uart_port *port)
1e6c9c28 582{
e8faff73
CS		 583 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
584
0058f087
AB		 585 if (atmel_use_pdc_tx(port) && (atmel_uart_readl(port, ATMEL_PDC_PTSR)
586 & ATMEL_PDC_TXTEN))
587 /* The transmitter is already running. Yes, we
588 really need this.*/
589 return;
a6670615 590
0058f087 591 if (atmel_use_pdc_tx(port) || atmel_use_dma_tx(port))
f3040983 592 if (atmel_uart_is_half_duplex(port))
e8faff73
CS		 593 atmel_stop_rx(port);
594
0058f087 595 if (atmel_use_pdc_tx(port))
a6670615 596 /* re-enable PDC transmit */
4e7decda 597 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
0058f087 598
e8faff73 599 /* Enable interrupts */
4e7decda 600 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->tx_done_mask);
89d82324
RG		 601
602 /* re-enable the transmitter */
603 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN);
ea04f82a 604 atmel_port->tx_stopped = false;
e8faff73
CS		 605}
606
607/*
608 * start receiving - port is in process of being opened.
609 */
610static void atmel_start_rx(struct uart_port *port)
611{
4e7decda
CP		 612 /* reset status and receiver */
613 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
e8faff73 614
4e7decda 615 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RXEN);
57c36868 616
64e22ebe 617 if (atmel_use_pdc_rx(port)) {
e8faff73 618 /* enable PDC controller */
4e7decda
CP		 619 atmel_uart_writel(port, ATMEL_US_IER,
620 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT |
621 port->read_status_mask);
622 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN);
e8faff73 623 } else {
4e7decda 624 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_RXRDY);
e8faff73 625 }
1e6c9c28
AV		 626}
627
628/*
629 * Stop receiving - port is in process of being closed.
630 */
7192f92c 631static void atmel_stop_rx(struct uart_port *port)
1e6c9c28 632{
4e7decda 633 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RXDIS);
57c36868 634
64e22ebe 635 if (atmel_use_pdc_rx(port)) {
a6670615 636 /* disable PDC receive */
4e7decda
CP		 637 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS);
638 atmel_uart_writel(port, ATMEL_US_IDR,
639 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT |
640 port->read_status_mask);
e8faff73 641 } else {
4e7decda 642 atmel_uart_writel(port, ATMEL_US_IDR, ATMEL_US_RXRDY);
e8faff73 643 }
1e6c9c28
AV		 644}
645
646/*
647 * Enable modem status interrupts
648 */
7192f92c 649static void atmel_enable_ms(struct uart_port *port)
1e6c9c28 650{
ab5e4e41
RG		 651 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
652 uint32_t ier = 0;
653
654 /*
655 * Interrupt should not be enabled twice
656 */
657 if (atmel_port->ms_irq_enabled)
658 return;
659
660 atmel_port->ms_irq_enabled = true;
661
18dfef9c 662 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_CTS))
ab5e4e41
RG		 663 ier |= ATMEL_US_CTSIC;
664
18dfef9c 665 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DSR))
ab5e4e41
RG		 666 ier |= ATMEL_US_DSRIC;
667
18dfef9c 668 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_RI))
ab5e4e41
RG		 669 ier |= ATMEL_US_RIIC;
670
18dfef9c 671 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DCD))
ab5e4e41
RG		 672 ier |= ATMEL_US_DCDIC;
673
4e7decda 674 atmel_uart_writel(port, ATMEL_US_IER, ier);
18dfef9c
UKK		 675
676 mctrl_gpio_enable_ms(atmel_port->gpios);
1e6c9c28
AV		 677}
678
35b675b9
RG		 679/*
680 * Disable modem status interrupts
681 */
682static void atmel_disable_ms(struct uart_port *port)
683{
684 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
685 uint32_t idr = 0;
686
687 /*
688 * Interrupt should not be disabled twice
689 */
690 if (!atmel_port->ms_irq_enabled)
691 return;
692
693 atmel_port->ms_irq_enabled = false;
694
18dfef9c
UKK		 695 mctrl_gpio_disable_ms(atmel_port->gpios);
696
697 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_CTS))
35b675b9
RG		 698 idr |= ATMEL_US_CTSIC;
699
18dfef9c 700 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DSR))
35b675b9
RG		 701 idr |= ATMEL_US_DSRIC;
702
18dfef9c 703 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_RI))
35b675b9
RG		 704 idr |= ATMEL_US_RIIC;
705
18dfef9c 706 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DCD))
35b675b9
RG		 707 idr |= ATMEL_US_DCDIC;
708
4e7decda 709 atmel_uart_writel(port, ATMEL_US_IDR, idr);
35b675b9
RG		 710}
711
1e6c9c28
AV		 712/*
713 * Control the transmission of a break signal
714 */
7192f92c 715static void atmel_break_ctl(struct uart_port *port, int break_state)
1e6c9c28
AV		 716{
717 if (break_state != 0)
4e7decda
CP		 718 /* start break */
719 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTBRK);
1e6c9c28 720 else
4e7decda
CP		 721 /* stop break */
722 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STPBRK);
1e6c9c28
AV		 723}
724
1ecc26bd
RB		 725/*
726 * Stores the incoming character in the ring buffer
727 */
728static void
729atmel_buffer_rx_char(struct uart_port *port, unsigned int status,
730 unsigned int ch)
731{
c811ab8c 732 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1ecc26bd
RB		 733 struct circ_buf *ring = &atmel_port->rx_ring;
734 struct atmel_uart_char *c;
735
736 if (!CIRC_SPACE(ring->head, ring->tail, ATMEL_SERIAL_RINGSIZE))
737 /* Buffer overflow, ignore char */
738 return;
739
740 c = &((struct atmel_uart_char *)ring->buf)[ring->head];
741 c->status = status;
742 c->ch = ch;
743
744 /* Make sure the character is stored before we update head. */
745 smp_wmb();
746
747 ring->head = (ring->head + 1) & (ATMEL_SERIAL_RINGSIZE - 1);
748}
749
a6670615
CC		 750/*
751 * Deal with parity, framing and overrun errors.
752 */
753static void atmel_pdc_rxerr(struct uart_port *port, unsigned int status)
754{
755 /* clear error */
4e7decda 756 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
a6670615
CC		 757
758 if (status & ATMEL_US_RXBRK) {
759 /* ignore side-effect */
760 status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME);
761 port->icount.brk++;
762 }
763 if (status & ATMEL_US_PARE)
764 port->icount.parity++;
765 if (status & ATMEL_US_FRAME)
766 port->icount.frame++;
767 if (status & ATMEL_US_OVRE)
768 port->icount.overrun++;
769}
770
1e6c9c28
AV		 771/*
772 * Characters received (called from interrupt handler)
773 */
7d12e780 774static void atmel_rx_chars(struct uart_port *port)
1e6c9c28 775{
c811ab8c 776 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1ecc26bd 777 unsigned int status, ch;
1e6c9c28 778
4e7decda 779 status = atmel_uart_readl(port, ATMEL_US_CSR);
7192f92c 780 while (status & ATMEL_US_RXRDY) {
a6499435 781 ch = atmel_uart_read_char(port);
1e6c9c28 782
1e6c9c28
AV		 783 /*
784 * note that the error handling code is
785 * out of the main execution path
786 */
9e6077bd
HS		 787 if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME
788 | ATMEL_US_OVRE | ATMEL_US_RXBRK)
789 || atmel_port->break_active)) {
1ecc26bd 790
b843aa21 791 /* clear error */
4e7decda 792 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
1ecc26bd 793
9e6077bd
HS		 794 if (status & ATMEL_US_RXBRK
795 && !atmel_port->break_active) {
9e6077bd 796 atmel_port->break_active = 1;
4e7decda
CP		 797 atmel_uart_writel(port, ATMEL_US_IER,
798 ATMEL_US_RXBRK);
9e6077bd
HS		 799 } else {
800 /*
801 * This is either the end-of-break
802 * condition or we've received at
803 * least one character without RXBRK
804 * being set. In both cases, the next
805 * RXBRK will indicate start-of-break.
806 */
4e7decda
CP		 807 atmel_uart_writel(port, ATMEL_US_IDR,
808 ATMEL_US_RXBRK);
9e6077bd
HS		 809 status &= ~ATMEL_US_RXBRK;
810 atmel_port->break_active = 0;
afefc415 811 }
1e6c9c28
AV		 812 }
813
1ecc26bd 814 atmel_buffer_rx_char(port, status, ch);
4e7decda 815 status = atmel_uart_readl(port, ATMEL_US_CSR);
1e6c9c28
AV		 816 }
817
98f2082c 818 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_rx);
1e6c9c28
AV		 819}
820
821/*
1ecc26bd
RB		 822 * Transmit characters (called from tasklet with TXRDY interrupt
823 * disabled)
1e6c9c28 824 */
7192f92c 825static void atmel_tx_chars(struct uart_port *port)
1e6c9c28 826{
e8faff73 827 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2d141e68
JSS		 828 bool pending;
829 u8 ch;
1e6c9c28 830
2d141e68
JSS		 831 pending = uart_port_tx(port, ch,
832 atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXRDY,
833 atmel_uart_write_char(port, ch));
834 if (pending) {
477b8383
CC		 835 /* we still have characters to transmit, so we should continue
836 * transmitting them when TX is ready, regardless of
837 * mode or duplexity
838 */
839 atmel_port->tx_done_mask |= ATMEL_US_TXRDY;
840
e8faff73 841 /* Enable interrupts */
4e7decda
CP		 842 atmel_uart_writel(port, ATMEL_US_IER,
843 atmel_port->tx_done_mask);
477b8383
CC		 844 } else {
845 if (atmel_uart_is_half_duplex(port))
846 atmel_port->tx_done_mask &= ~ATMEL_US_TXRDY;
847 }
1e6c9c28
AV		 848}
849
08f738be
ES		 850static void atmel_complete_tx_dma(void *arg)
851{
852 struct atmel_uart_port *atmel_port = arg;
853 struct uart_port *port = &atmel_port->uart;
854 struct circ_buf *xmit = &port->state->xmit;
855 struct dma_chan *chan = atmel_port->chan_tx;
856 unsigned long flags;
857
858 spin_lock_irqsave(&port->lock, flags);
859
860 if (chan)
861 dmaengine_terminate_all(chan);
5f258b3e 862 xmit->tail += atmel_port->tx_len;
08f738be
ES		 863 xmit->tail &= UART_XMIT_SIZE - 1;
864
5f258b3e 865 port->icount.tx += atmel_port->tx_len;
08f738be
ES		 866
867 spin_lock_irq(&atmel_port->lock_tx);
868 async_tx_ack(atmel_port->desc_tx);
869 atmel_port->cookie_tx = -EINVAL;
870 atmel_port->desc_tx = NULL;
871 spin_unlock_irq(&atmel_port->lock_tx);
872
873 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
874 uart_write_wakeup(port);
875
1842dc2e
CP		 876 /*
877 * xmit is a circular buffer so, if we have just send data from
878 * xmit->tail to the end of xmit->buf, now we have to transmit the
879 * remaining data from the beginning of xmit->buf to xmit->head.
880 */
08f738be 881 if (!uart_circ_empty(xmit))
98f2082c 882 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_tx);
f3040983 883 else if (atmel_uart_is_half_duplex(port)) {
69646d7a
RS		 884 /*
885 * DMA done, re-enable TXEMPTY and signal that we can stop
886 * TX and start RX for RS485
887 */
888 atmel_port->hd_start_rx = true;
889 atmel_uart_writel(port, ATMEL_US_IER,
890 atmel_port->tx_done_mask);
b389f173 891 }
08f738be
ES		 892
893 spin_unlock_irqrestore(&port->lock, flags);
894}
895
896static void atmel_release_tx_dma(struct uart_port *port)
897{
898 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
899 struct dma_chan *chan = atmel_port->chan_tx;
900
901 if (chan) {
902 dmaengine_terminate_all(chan);
903 dma_release_channel(chan);
904 dma_unmap_sg(port->dev, &atmel_port->sg_tx, 1,
48479148 905 DMA_TO_DEVICE);
08f738be
ES		 906 }
907
908 atmel_port->desc_tx = NULL;
909 atmel_port->chan_tx = NULL;
910 atmel_port->cookie_tx = -EINVAL;
911}
912
913/*
914 * Called from tasklet with TXRDY interrupt is disabled.
915 */
916static void atmel_tx_dma(struct uart_port *port)
917{
918 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
919 struct circ_buf *xmit = &port->state->xmit;
920 struct dma_chan *chan = atmel_port->chan_tx;
921 struct dma_async_tx_descriptor *desc;
5f258b3e
CP		 922 struct scatterlist sgl[2], *sg, *sg_tx = &atmel_port->sg_tx;
923 unsigned int tx_len, part1_len, part2_len, sg_len;
924 dma_addr_t phys_addr;
08f738be
ES		 925
926 /* Make sure we have an idle channel */
927 if (atmel_port->desc_tx != NULL)
928 return;
929
930 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) {
931 /*
932 * DMA is idle now.
933 * Port xmit buffer is already mapped,
934 * and it is one page... Just adjust
935 * offsets and lengths. Since it is a circular buffer,
936 * we have to transmit till the end, and then the rest.
937 * Take the port lock to get a
938 * consistent xmit buffer state.
939 */
5f258b3e
CP		 940 tx_len = CIRC_CNT_TO_END(xmit->head,
941 xmit->tail,
942 UART_XMIT_SIZE);
943
944 if (atmel_port->fifo_size) {
945 /* multi data mode */
946 part1_len = (tx_len & ~0x3); /* DWORD access */
947 part2_len = (tx_len & 0x3); /* BYTE access */
948 } else {
949 /* single data (legacy) mode */
950 part1_len = 0;
951 part2_len = tx_len; /* BYTE access only */
952 }
953
954 sg_init_table(sgl, 2);
955 sg_len = 0;
956 phys_addr = sg_dma_address(sg_tx) + xmit->tail;
957 if (part1_len) {
958 sg = &sgl[sg_len++];
959 sg_dma_address(sg) = phys_addr;
960 sg_dma_len(sg) = part1_len;
961
962 phys_addr += part1_len;
963 }
964
965 if (part2_len) {
966 sg = &sgl[sg_len++];
967 sg_dma_address(sg) = phys_addr;
968 sg_dma_len(sg) = part2_len;
969 }
970
971 /*
972 * save tx_len so atmel_complete_tx_dma() will increase
973 * xmit->tail correctly
974 */
975 atmel_port->tx_len = tx_len;
08f738be
ES		 976
977 desc = dmaengine_prep_slave_sg(chan,
5f258b3e
CP		 978 sgl,
979 sg_len,
1842dc2e
CP		 980 DMA_MEM_TO_DEV,
981 DMA_PREP_INTERRUPT |
982 DMA_CTRL_ACK);
08f738be
ES		 983 if (!desc) {
984 dev_err(port->dev, "Failed to send via dma!\n");
985 return;
986 }
987
5f258b3e 988 dma_sync_sg_for_device(port->dev, sg_tx, 1, DMA_TO_DEVICE);
08f738be
ES		 989
990 atmel_port->desc_tx = desc;
991 desc->callback = atmel_complete_tx_dma;
992 desc->callback_param = atmel_port;
993 atmel_port->cookie_tx = dmaengine_submit(desc);
1e67bd2b
TA		 994 if (dma_submit_error(atmel_port->cookie_tx)) {
995 dev_err(port->dev, "dma_submit_error %d\n",
996 atmel_port->cookie_tx);
997 return;
998 }
4f4b9b58
TA		 999
1000 dma_async_issue_pending(chan);
08f738be
ES		 1001 }
1002
1003 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1004 uart_write_wakeup(port);
1005}
1006
1007static int atmel_prepare_tx_dma(struct uart_port *port)
1008{
1009 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
c24d2531 1010 struct device *mfd_dev = port->dev->parent;
08f738be
ES		 1011 dma_cap_mask_t mask;
1012 struct dma_slave_config config;
1013 int ret, nent;
1014
1015 dma_cap_zero(mask);
1016 dma_cap_set(DMA_SLAVE, mask);
1017
c24d2531 1018 atmel_port->chan_tx = dma_request_slave_channel(mfd_dev, "tx");
08f738be
ES		 1019 if (atmel_port->chan_tx == NULL)
1020 goto chan_err;
1021 dev_info(port->dev, "using %s for tx DMA transfers\n",
1022 dma_chan_name(atmel_port->chan_tx));
1023
1024 spin_lock_init(&atmel_port->lock_tx);
1025 sg_init_table(&atmel_port->sg_tx, 1);
1026 /* UART circular tx buffer is an aligned page. */
2c277054 1027 BUG_ON(!PAGE_ALIGNED(port->state->xmit.buf));
08f738be
ES		 1028 sg_set_page(&atmel_port->sg_tx,
1029 virt_to_page(port->state->xmit.buf),
1030 UART_XMIT_SIZE,
2b5cf14b 1031 offset_in_page(port->state->xmit.buf));
08f738be
ES		 1032 nent = dma_map_sg(port->dev,
1033 &atmel_port->sg_tx,
1034 1,
48479148 1035 DMA_TO_DEVICE);
08f738be
ES		 1036
1037 if (!nent) {
1038 dev_dbg(port->dev, "need to release resource of dma\n");
1039 goto chan_err;
1040 } else {
c8d1f022 1041 dev_dbg(port->dev, "%s: mapped %d@%p to %pad\n", __func__,
08f738be
ES		 1042 sg_dma_len(&atmel_port->sg_tx),
1043 port->state->xmit.buf,
c8d1f022 1044 &sg_dma_address(&atmel_port->sg_tx));
08f738be
ES		 1045 }
1046
1047 /* Configure the slave DMA */
1048 memset(&config, 0, sizeof(config));
1049 config.direction = DMA_MEM_TO_DEV;
5f258b3e
CP		 1050 config.dst_addr_width = (atmel_port->fifo_size) ?
1051 DMA_SLAVE_BUSWIDTH_4_BYTES :
1052 DMA_SLAVE_BUSWIDTH_1_BYTE;
08f738be 1053 config.dst_addr = port->mapbase + ATMEL_US_THR;
a8d4e016 1054 config.dst_maxburst = 1;
08f738be 1055
5483c10e
MR		 1056 ret = dmaengine_slave_config(atmel_port->chan_tx,
1057 &config);
08f738be
ES		 1058 if (ret) {
1059 dev_err(port->dev, "DMA tx slave configuration failed\n");
1060 goto chan_err;
1061 }
1062
1063 return 0;
1064
1065chan_err:
1066 dev_err(port->dev, "TX channel not available, switch to pio\n");
36ce7cff 1067 atmel_port->use_dma_tx = false;
08f738be
ES		 1068 if (atmel_port->chan_tx)
1069 atmel_release_tx_dma(port);
1070 return -EINVAL;
1071}
1072
34df42f5
ES		 1073static void atmel_complete_rx_dma(void *arg)
1074{
1075 struct uart_port *port = arg;
1076 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1077
98f2082c 1078 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_rx);
34df42f5
ES		 1079}
1080
1081static void atmel_release_rx_dma(struct uart_port *port)
1082{
1083 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1084 struct dma_chan *chan = atmel_port->chan_rx;
1085
1086 if (chan) {
1087 dmaengine_terminate_all(chan);
1088 dma_release_channel(chan);
1089 dma_unmap_sg(port->dev, &atmel_port->sg_rx, 1,
48479148 1090 DMA_FROM_DEVICE);
34df42f5
ES		 1091 }
1092
1093 atmel_port->desc_rx = NULL;
1094 atmel_port->chan_rx = NULL;
1095 atmel_port->cookie_rx = -EINVAL;
1096}
1097
1098static void atmel_rx_from_dma(struct uart_port *port)
1099{
1100 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
66f37aaf 1101 struct tty_port *tport = &port->state->port;
34df42f5
ES		 1102 struct circ_buf *ring = &atmel_port->rx_ring;
1103 struct dma_chan *chan = atmel_port->chan_rx;
1104 struct dma_tx_state state;
1105 enum dma_status dmastat;
66f37aaf 1106 size_t count;
34df42f5
ES		 1107
1108
1109 /* Reset the UART timeout early so that we don't miss one */
4e7decda 1110 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
34df42f5
ES		 1111 dmastat = dmaengine_tx_status(chan,
1112 atmel_port->cookie_rx,
1113 &state);
1114 /* Restart a new tasklet if DMA status is error */
1115 if (dmastat == DMA_ERROR) {
1116 dev_dbg(port->dev, "Get residue error, restart tasklet\n");
4e7decda 1117 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_TIMEOUT);
98f2082c 1118 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_rx);
34df42f5
ES		 1119 return;
1120 }
34df42f5 1121
66f37aaf
CP		 1122 /* CPU claims ownership of RX DMA buffer */
1123 dma_sync_sg_for_cpu(port->dev,
1124 &atmel_port->sg_rx,
1125 1,
485819b5 1126 DMA_FROM_DEVICE);
66f37aaf
CP		 1127
1128 /*
1129 * ring->head points to the end of data already written by the DMA.
1130 * ring->tail points to the beginning of data to be read by the
1131 * framework.
1132 * The current transfer size should not be larger than the dma buffer
1133 * length.
1134 */
1135 ring->head = sg_dma_len(&atmel_port->sg_rx) - state.residue;
1136 BUG_ON(ring->head > sg_dma_len(&atmel_port->sg_rx));
34df42f5 1137 /*
66f37aaf
CP		 1138 * At this point ring->head may point to the first byte right after the
1139 * last byte of the dma buffer:
1140 * 0 <= ring->head <= sg_dma_len(&atmel_port->sg_rx)
1141 *
1142 * However ring->tail must always points inside the dma buffer:
1143 * 0 <= ring->tail <= sg_dma_len(&atmel_port->sg_rx) - 1
1144 *
1145 * Since we use a ring buffer, we have to handle the case
1146 * where head is lower than tail. In such a case, we first read from
1147 * tail to the end of the buffer then reset tail.
34df42f5 1148 */
66f37aaf
CP		 1149 if (ring->head < ring->tail) {
1150 count = sg_dma_len(&atmel_port->sg_rx) - ring->tail;
34df42f5 1151
66f37aaf
CP		 1152 tty_insert_flip_string(tport, ring->buf + ring->tail, count);
1153 ring->tail = 0;
1154 port->icount.rx += count;
1155 }
34df42f5 1156
66f37aaf
CP		 1157 /* Finally we read data from tail to head */
1158 if (ring->tail < ring->head) {
1159 count = ring->head - ring->tail;
34df42f5 1160
66f37aaf
CP		 1161 tty_insert_flip_string(tport, ring->buf + ring->tail, count);
1162 /* Wrap ring->head if needed */
1163 if (ring->head >= sg_dma_len(&atmel_port->sg_rx))
1164 ring->head = 0;
1165 ring->tail = ring->head;
34df42f5
ES		 1166 port->icount.rx += count;
1167 }
1168
66f37aaf
CP		 1169 /* USART retreives ownership of RX DMA buffer */
1170 dma_sync_sg_for_device(port->dev,
1171 &atmel_port->sg_rx,
1172 1,
485819b5 1173 DMA_FROM_DEVICE);
66f37aaf 1174
66f37aaf 1175 tty_flip_buffer_push(tport);
66f37aaf 1176
4e7decda 1177 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_TIMEOUT);
34df42f5
ES		 1178}
1179
1180static int atmel_prepare_rx_dma(struct uart_port *port)
1181{
1182 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
c24d2531 1183 struct device *mfd_dev = port->dev->parent;
34df42f5
ES		 1184 struct dma_async_tx_descriptor *desc;
1185 dma_cap_mask_t mask;
1186 struct dma_slave_config config;
1187 struct circ_buf *ring;
1188 int ret, nent;
1189
1190 ring = &atmel_port->rx_ring;
1191
1192 dma_cap_zero(mask);
1193 dma_cap_set(DMA_CYCLIC, mask);
1194
c24d2531 1195 atmel_port->chan_rx = dma_request_slave_channel(mfd_dev, "rx");
34df42f5
ES		 1196 if (atmel_port->chan_rx == NULL)
1197 goto chan_err;
1198 dev_info(port->dev, "using %s for rx DMA transfers\n",
1199 dma_chan_name(atmel_port->chan_rx));
1200
1201 spin_lock_init(&atmel_port->lock_rx);
1202 sg_init_table(&atmel_port->sg_rx, 1);
1203 /* UART circular rx buffer is an aligned page. */
2c277054 1204 BUG_ON(!PAGE_ALIGNED(ring->buf));
34df42f5 1205 sg_set_page(&atmel_port->sg_rx,
1842dc2e 1206 virt_to_page(ring->buf),
a510880f 1207 sizeof(struct atmel_uart_char) * ATMEL_SERIAL_RINGSIZE,
2b5cf14b 1208 offset_in_page(ring->buf));
1842dc2e
CP		 1209 nent = dma_map_sg(port->dev,
1210 &atmel_port->sg_rx,
1211 1,
1212 DMA_FROM_DEVICE);
34df42f5
ES		 1213
1214 if (!nent) {
1215 dev_dbg(port->dev, "need to release resource of dma\n");
1216 goto chan_err;
1217 } else {
c8d1f022 1218 dev_dbg(port->dev, "%s: mapped %d@%p to %pad\n", __func__,
34df42f5
ES		 1219 sg_dma_len(&atmel_port->sg_rx),
1220 ring->buf,
c8d1f022 1221 &sg_dma_address(&atmel_port->sg_rx));
34df42f5
ES		 1222 }
1223
1224 /* Configure the slave DMA */
1225 memset(&config, 0, sizeof(config));
1226 config.direction = DMA_DEV_TO_MEM;
1227 config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1228 config.src_addr = port->mapbase + ATMEL_US_RHR;
a8d4e016 1229 config.src_maxburst = 1;
34df42f5 1230
5483c10e
MR		 1231 ret = dmaengine_slave_config(atmel_port->chan_rx,
1232 &config);
34df42f5
ES		 1233 if (ret) {
1234 dev_err(port->dev, "DMA rx slave configuration failed\n");
1235 goto chan_err;
1236 }
1237 /*
1238 * Prepare a cyclic dma transfer, assign 2 descriptors,
1239 * each one is half ring buffer size
1240 */
1241 desc = dmaengine_prep_dma_cyclic(atmel_port->chan_rx,
1842dc2e
CP		 1242 sg_dma_address(&atmel_port->sg_rx),
1243 sg_dma_len(&atmel_port->sg_rx),
1244 sg_dma_len(&atmel_port->sg_rx)/2,
1245 DMA_DEV_TO_MEM,
1246 DMA_PREP_INTERRUPT);
c85be041
KL		 1247 if (!desc) {
1248 dev_err(port->dev, "Preparing DMA cyclic failed\n");
1249 goto chan_err;
1250 }
34df42f5
ES		 1251 desc->callback = atmel_complete_rx_dma;
1252 desc->callback_param = port;
1253 atmel_port->desc_rx = desc;
1254 atmel_port->cookie_rx = dmaengine_submit(desc);
1e67bd2b
TA		 1255 if (dma_submit_error(atmel_port->cookie_rx)) {
1256 dev_err(port->dev, "dma_submit_error %d\n",
1257 atmel_port->cookie_rx);
1258 goto chan_err;
1259 }
34df42f5 1260
4f4b9b58
TA		 1261 dma_async_issue_pending(atmel_port->chan_rx);
1262
34df42f5
ES		 1263 return 0;
1264
1265chan_err:
1266 dev_err(port->dev, "RX channel not available, switch to pio\n");
36ce7cff 1267 atmel_port->use_dma_rx = false;
34df42f5
ES		 1268 if (atmel_port->chan_rx)
1269 atmel_release_rx_dma(port);
1270 return -EINVAL;
1271}
1272
026cb432 1273static void atmel_uart_timer_callback(struct timer_list *t)
2e68c22f 1274{
026cb432
KC		 1275 struct atmel_uart_port *atmel_port = from_timer(atmel_port, t,
1276 uart_timer);
1277 struct uart_port *port = &atmel_port->uart;
2e68c22f 1278
98f2082c
NF		 1279 if (!atomic_read(&atmel_port->tasklet_shutdown)) {
1280 tasklet_schedule(&atmel_port->tasklet_rx);
1281 mod_timer(&atmel_port->uart_timer,
1282 jiffies + uart_poll_timeout(port));
1283 }
2e68c22f
ES		 1284}
1285
b843aa21
RB		 1286/*
1287 * receive interrupt handler.
1288 */
1289static void
1290atmel_handle_receive(struct uart_port *port, unsigned int pending)
1291{
c811ab8c 1292 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
b843aa21 1293
64e22ebe 1294 if (atmel_use_pdc_rx(port)) {
a6670615
CC		 1295 /*
1296 * PDC receive. Just schedule the tasklet and let it
1297 * figure out the details.
1298 *
1299 * TODO: We're not handling error flags correctly at
1300 * the moment.
1301 */
1302 if (pending & (ATMEL_US_ENDRX | ATMEL_US_TIMEOUT)) {
4e7decda
CP		 1303 atmel_uart_writel(port, ATMEL_US_IDR,
1304 (ATMEL_US_ENDRX | ATMEL_US_TIMEOUT));
98f2082c
NF		 1305 atmel_tasklet_schedule(atmel_port,
1306 &atmel_port->tasklet_rx);
a6670615
CC		 1307 }
1308
1309 if (pending & (ATMEL_US_RXBRK | ATMEL_US_OVRE |
1310 ATMEL_US_FRAME | ATMEL_US_PARE))
1311 atmel_pdc_rxerr(port, pending);
1312 }
1313
34df42f5
ES		 1314 if (atmel_use_dma_rx(port)) {
1315 if (pending & ATMEL_US_TIMEOUT) {
4e7decda
CP		 1316 atmel_uart_writel(port, ATMEL_US_IDR,
1317 ATMEL_US_TIMEOUT);
98f2082c
NF		 1318 atmel_tasklet_schedule(atmel_port,
1319 &atmel_port->tasklet_rx);
34df42f5
ES		 1320 }
1321 }
1322
b843aa21
RB		 1323 /* Interrupt receive */
1324 if (pending & ATMEL_US_RXRDY)
1325 atmel_rx_chars(port);
1326 else if (pending & ATMEL_US_RXBRK) {
1327 /*
1328 * End of break detected. If it came along with a
1329 * character, atmel_rx_chars will handle it.
1330 */
4e7decda
CP		 1331 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
1332 atmel_uart_writel(port, ATMEL_US_IDR, ATMEL_US_RXBRK);
b843aa21
RB		 1333 atmel_port->break_active = 0;
1334 }
1335}
1336
1337/*
1ecc26bd 1338 * transmit interrupt handler. (Transmit is IRQF_NODELAY safe)
b843aa21
RB		 1339 */
1340static void
1341atmel_handle_transmit(struct uart_port *port, unsigned int pending)
1342{
c811ab8c 1343 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1ecc26bd 1344
e8faff73 1345 if (pending & atmel_port->tx_done_mask) {
4e7decda
CP		 1346 atmel_uart_writel(port, ATMEL_US_IDR,
1347 atmel_port->tx_done_mask);
69646d7a
RS		 1348
1349 /* Start RX if flag was set and FIFO is empty */
1350 if (atmel_port->hd_start_rx) {
1351 if (!(atmel_uart_readl(port, ATMEL_US_CSR)
1352 & ATMEL_US_TXEMPTY))
1353 dev_warn(port->dev, "Should start RX, but TX fifo is not empty\n");
1354
1355 atmel_port->hd_start_rx = false;
1356 atmel_start_rx(port);
69646d7a
RS		 1357 }
1358
98f2082c 1359 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_tx);
1ecc26bd 1360 }
b843aa21
RB		 1361}
1362
1363/*
1364 * status flags interrupt handler.
1365 */
1366static void
1367atmel_handle_status(struct uart_port *port, unsigned int pending,
1368 unsigned int status)
1369{
c811ab8c 1370 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
9205218e 1371 unsigned int status_change;
1ecc26bd 1372
b843aa21 1373 if (pending & (ATMEL_US_RIIC | ATMEL_US_DSRIC | ATMEL_US_DCDIC
1ecc26bd 1374 | ATMEL_US_CTSIC)) {
9205218e 1375 status_change = status ^ atmel_port->irq_status_prev;
d033e82d 1376 atmel_port->irq_status_prev = status;
9205218e
NF		 1377
1378 if (status_change & (ATMEL_US_RI | ATMEL_US_DSR
1379 | ATMEL_US_DCD | ATMEL_US_CTS)) {
1380 /* TODO: All reads to CSR will clear these interrupts! */
1381 if (status_change & ATMEL_US_RI)
1382 port->icount.rng++;
1383 if (status_change & ATMEL_US_DSR)
1384 port->icount.dsr++;
1385 if (status_change & ATMEL_US_DCD)
1386 uart_handle_dcd_change(port, !(status & ATMEL_US_DCD));
1387 if (status_change & ATMEL_US_CTS)
1388 uart_handle_cts_change(port, !(status & ATMEL_US_CTS));
1389
1390 wake_up_interruptible(&port->state->port.delta_msr_wait);
1391 }
1ecc26bd 1392 }
377fedd1
NF		 1393
1394 if (pending & (ATMEL_US_NACK | ATMEL_US_ITERATION))
1395 dev_dbg(port->dev, "ISO7816 ERROR (0x%08x)\n", pending);
b843aa21
RB		 1396}
1397
1e6c9c28
AV		 1398/*
1399 * Interrupt handler
1400 */
7d12e780 1401static irqreturn_t atmel_interrupt(int irq, void *dev_id)
1e6c9c28
AV		 1402{
1403 struct uart_port *port = dev_id;
ab5e4e41 1404 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2c7af5ba 1405 unsigned int status, pending, mask, pass_counter = 0;
1e6c9c28 1406
2c7af5ba
BB		 1407 spin_lock(&atmel_port->lock_suspended);
1408
a6670615 1409 do {
d2d8d4c0 1410 status = atmel_uart_readl(port, ATMEL_US_CSR);
4e7decda 1411 mask = atmel_uart_readl(port, ATMEL_US_IMR);
2c7af5ba 1412 pending = status & mask;
a6670615
CC		 1413 if (!pending)
1414 break;
1415
2c7af5ba
BB		 1416 if (atmel_port->suspended) {
1417 atmel_port->pending |= pending;
1418 atmel_port->pending_status = status;
4e7decda 1419 atmel_uart_writel(port, ATMEL_US_IDR, mask);
2c7af5ba
BB		 1420 pm_system_wakeup();
1421 break;
1422 }
1423
b843aa21
RB		 1424 atmel_handle_receive(port, pending);
1425 atmel_handle_status(port, pending, status);
1426 atmel_handle_transmit(port, pending);
a6670615 1427 } while (pass_counter++ < ATMEL_ISR_PASS_LIMIT);
afefc415 1428
2c7af5ba
BB		 1429 spin_unlock(&atmel_port->lock_suspended);
1430
0400b697 1431 return pass_counter ? IRQ_HANDLED : IRQ_NONE;
a6670615 1432}
1e6c9c28 1433
a930e528
ES		 1434static void atmel_release_tx_pdc(struct uart_port *port)
1435{
1436 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1437 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1438
1439 dma_unmap_single(port->dev,
1440 pdc->dma_addr,
1441 pdc->dma_size,
1442 DMA_TO_DEVICE);
1443}
1444
a6670615
CC		 1445/*
1446 * Called from tasklet with ENDTX and TXBUFE interrupts disabled.
1447 */
64e22ebe 1448static void atmel_tx_pdc(struct uart_port *port)
a6670615 1449{
c811ab8c 1450 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
ebd2c8f6 1451 struct circ_buf *xmit = &port->state->xmit;
a6670615
CC		 1452 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1453 int count;
1454
ba0657ff 1455 /* nothing left to transmit? */
4e7decda 1456 if (atmel_uart_readl(port, ATMEL_PDC_TCR))
ba0657ff
MT		 1457 return;
1458
a6670615
CC		 1459 xmit->tail += pdc->ofs;
1460 xmit->tail &= UART_XMIT_SIZE - 1;
1461
1462 port->icount.tx += pdc->ofs;
1463 pdc->ofs = 0;
1464
ba0657ff 1465 /* more to transmit - setup next transfer */
a6670615 1466
ba0657ff 1467 /* disable PDC transmit */
4e7decda 1468 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS);
ba0657ff 1469
1f14081d 1470 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) {
a6670615
CC		 1471 dma_sync_single_for_device(port->dev,
1472 pdc->dma_addr,
1473 pdc->dma_size,
1474 DMA_TO_DEVICE);
1475
1476 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
1477 pdc->ofs = count;
1478
4e7decda
CP		 1479 atmel_uart_writel(port, ATMEL_PDC_TPR,
1480 pdc->dma_addr + xmit->tail);
1481 atmel_uart_writel(port, ATMEL_PDC_TCR, count);
e8faff73 1482 /* re-enable PDC transmit */
4e7decda 1483 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
e8faff73 1484 /* Enable interrupts */
4e7decda
CP		 1485 atmel_uart_writel(port, ATMEL_US_IER,
1486 atmel_port->tx_done_mask);
e8faff73 1487 } else {
f3040983 1488 if (atmel_uart_is_half_duplex(port)) {
e8faff73
CS		 1489 /* DMA done, stop TX, start RX for RS485 */
1490 atmel_start_rx(port);
1491 }
1e6c9c28 1492 }
a6670615
CC		 1493
1494 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1495 uart_write_wakeup(port);
1e6c9c28
AV		 1496}
1497
a930e528
ES		 1498static int atmel_prepare_tx_pdc(struct uart_port *port)
1499{
1500 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1501 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1502 struct circ_buf *xmit = &port->state->xmit;
1503
1504 pdc->buf = xmit->buf;
1505 pdc->dma_addr = dma_map_single(port->dev,
1506 pdc->buf,
1507 UART_XMIT_SIZE,
1508 DMA_TO_DEVICE);
1509 pdc->dma_size = UART_XMIT_SIZE;
1510 pdc->ofs = 0;
1511
1512 return 0;
1513}
1514
1ecc26bd
RB		 1515static void atmel_rx_from_ring(struct uart_port *port)
1516{
c811ab8c 1517 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1ecc26bd
RB		 1518 struct circ_buf *ring = &atmel_port->rx_ring;
1519 unsigned int flg;
1520 unsigned int status;
1521
1522 while (ring->head != ring->tail) {
1523 struct atmel_uart_char c;
1524
1525 /* Make sure c is loaded after head. */
1526 smp_rmb();
1527
1528 c = ((struct atmel_uart_char *)ring->buf)[ring->tail];
1529
1530 ring->tail = (ring->tail + 1) & (ATMEL_SERIAL_RINGSIZE - 1);
1531
1532 port->icount.rx++;
1533 status = c.status;
1534 flg = TTY_NORMAL;
1535
1536 /*
1537 * note that the error handling code is
1538 * out of the main execution path
1539 */
1540 if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME
1541 | ATMEL_US_OVRE | ATMEL_US_RXBRK))) {
1542 if (status & ATMEL_US_RXBRK) {
1543 /* ignore side-effect */
1544 status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME);
1545
1546 port->icount.brk++;
1547 if (uart_handle_break(port))
1548 continue;
1549 }
1550 if (status & ATMEL_US_PARE)
1551 port->icount.parity++;
1552 if (status & ATMEL_US_FRAME)
1553 port->icount.frame++;
1554 if (status & ATMEL_US_OVRE)
1555 port->icount.overrun++;
1556
1557 status &= port->read_status_mask;
1558
1559 if (status & ATMEL_US_RXBRK)
1560 flg = TTY_BREAK;
1561 else if (status & ATMEL_US_PARE)
1562 flg = TTY_PARITY;
1563 else if (status & ATMEL_US_FRAME)
1564 flg = TTY_FRAME;
1565 }
1566
1567
1568 if (uart_handle_sysrq_char(port, c.ch))
1569 continue;
1570
1571 uart_insert_char(port, status, ATMEL_US_OVRE, c.ch, flg);
1572 }
1573
2e124b4a 1574 tty_flip_buffer_push(&port->state->port);
1ecc26bd
RB		 1575}
1576
a930e528
ES		 1577static void atmel_release_rx_pdc(struct uart_port *port)
1578{
1579 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1580 int i;
1581
1582 for (i = 0; i < 2; i++) {
1583 struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i];
1584
1585 dma_unmap_single(port->dev,
1586 pdc->dma_addr,
1587 pdc->dma_size,
1588 DMA_FROM_DEVICE);
1589 kfree(pdc->buf);
1590 }
1591}
1592
64e22ebe 1593static void atmel_rx_from_pdc(struct uart_port *port)
a6670615 1594{
c811ab8c 1595 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
05c7cd39 1596 struct tty_port *tport = &port->state->port;
a6670615
CC		 1597 struct atmel_dma_buffer *pdc;
1598 int rx_idx = atmel_port->pdc_rx_idx;
1599 unsigned int head;
1600 unsigned int tail;
1601 unsigned int count;
1602
1603 do {
1604 /* Reset the UART timeout early so that we don't miss one */
4e7decda 1605 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
a6670615
CC		 1606
1607 pdc = &atmel_port->pdc_rx[rx_idx];
4e7decda 1608 head = atmel_uart_readl(port, ATMEL_PDC_RPR) - pdc->dma_addr;
a6670615
CC		 1609 tail = pdc->ofs;
1610
1611 /* If the PDC has switched buffers, RPR won't contain
1612 * any address within the current buffer. Since head
1613 * is unsigned, we just need a one-way comparison to
1614 * find out.
1615 *
1616 * In this case, we just need to consume the entire
1617 * buffer and resubmit it for DMA. This will clear the
1618 * ENDRX bit as well, so that we can safely re-enable
1619 * all interrupts below.
1620 */
1621 head = min(head, pdc->dma_size);
1622
1623 if (likely(head != tail)) {
1624 dma_sync_single_for_cpu(port->dev, pdc->dma_addr,
1625 pdc->dma_size, DMA_FROM_DEVICE);
1626
1627 /*
1628 * head will only wrap around when we recycle
1629 * the DMA buffer, and when that happens, we
1630 * explicitly set tail to 0. So head will
1631 * always be greater than tail.
1632 */
1633 count = head - tail;
1634
05c7cd39
JS		 1635 tty_insert_flip_string(tport, pdc->buf + pdc->ofs,
1636 count);
a6670615
CC		 1637
1638 dma_sync_single_for_device(port->dev, pdc->dma_addr,
1639 pdc->dma_size, DMA_FROM_DEVICE);
1640
1641 port->icount.rx += count;
1642 pdc->ofs = head;
1643 }
1644
1645 /*
1646 * If the current buffer is full, we need to check if
1647 * the next one contains any additional data.
1648 */
1649 if (head >= pdc->dma_size) {
1650 pdc->ofs = 0;
4e7decda
CP		 1651 atmel_uart_writel(port, ATMEL_PDC_RNPR, pdc->dma_addr);
1652 atmel_uart_writel(port, ATMEL_PDC_RNCR, pdc->dma_size);
a6670615
CC		 1653
1654 rx_idx = !rx_idx;
1655 atmel_port->pdc_rx_idx = rx_idx;
1656 }
1657 } while (head >= pdc->dma_size);
1658
2e124b4a 1659 tty_flip_buffer_push(tport);
a6670615 1660
4e7decda
CP		 1661 atmel_uart_writel(port, ATMEL_US_IER,
1662 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT);
a6670615
CC		 1663}
1664
a930e528
ES		 1665static int atmel_prepare_rx_pdc(struct uart_port *port)
1666{
1667 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1668 int i;
1669
1670 for (i = 0; i < 2; i++) {
1671 struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i];
1672
1673 pdc->buf = kmalloc(PDC_BUFFER_SIZE, GFP_KERNEL);
1674 if (pdc->buf == NULL) {
1675 if (i != 0) {
1676 dma_unmap_single(port->dev,
1677 atmel_port->pdc_rx[0].dma_addr,
1678 PDC_BUFFER_SIZE,
1679 DMA_FROM_DEVICE);
1680 kfree(atmel_port->pdc_rx[0].buf);
1681 }
36ce7cff 1682 atmel_port->use_pdc_rx = false;
a930e528
ES		 1683 return -ENOMEM;
1684 }
1685 pdc->dma_addr = dma_map_single(port->dev,
1686 pdc->buf,
1687 PDC_BUFFER_SIZE,
1688 DMA_FROM_DEVICE);
1689 pdc->dma_size = PDC_BUFFER_SIZE;
1690 pdc->ofs = 0;
1691 }
1692
1693 atmel_port->pdc_rx_idx = 0;
1694
4e7decda
CP		 1695 atmel_uart_writel(port, ATMEL_PDC_RPR, atmel_port->pdc_rx[0].dma_addr);
1696 atmel_uart_writel(port, ATMEL_PDC_RCR, PDC_BUFFER_SIZE);
a930e528 1697
4e7decda
CP		 1698 atmel_uart_writel(port, ATMEL_PDC_RNPR,
1699 atmel_port->pdc_rx[1].dma_addr);
1700 atmel_uart_writel(port, ATMEL_PDC_RNCR, PDC_BUFFER_SIZE);
a930e528
ES		 1701
1702 return 0;
1703}
1704
1ecc26bd
RB		 1705/*
1706 * tasklet handling tty stuff outside the interrupt handler.
1707 */
41e85e44 1708static void atmel_tasklet_rx_func(struct tasklet_struct *t)
1ecc26bd 1709{
41e85e44
AP		 1710 struct atmel_uart_port *atmel_port = from_tasklet(atmel_port, t,
1711 tasklet_rx);
1712 struct uart_port *port = &atmel_port->uart;
1ecc26bd
RB		 1713
1714 /* The interrupt handler does not take the lock */
1715 spin_lock(&port->lock);
a930e528 1716 atmel_port->schedule_rx(port);
00e8e658
NF		 1717 spin_unlock(&port->lock);
1718}
1ecc26bd 1719
41e85e44 1720static void atmel_tasklet_tx_func(struct tasklet_struct *t)
00e8e658 1721{
41e85e44
AP		 1722 struct atmel_uart_port *atmel_port = from_tasklet(atmel_port, t,
1723 tasklet_tx);
1724 struct uart_port *port = &atmel_port->uart;
00e8e658
NF		 1725
1726 /* The interrupt handler does not take the lock */
1727 spin_lock(&port->lock);
1728 atmel_port->schedule_tx(port);
1ecc26bd
RB		 1729 spin_unlock(&port->lock);
1730}
1731
4a1e8888 1732static void atmel_init_property(struct atmel_uart_port *atmel_port,
33d64c4f
ES		 1733 struct platform_device *pdev)
1734{
1735 struct device_node *np = pdev->dev.of_node;
92c8f7c0
AB		 1736
1737 /* DMA/PDC usage specification */
1738 if (of_property_read_bool(np, "atmel,use-dma-rx")) {
1739 if (of_property_read_bool(np, "dmas")) {
1740 atmel_port->use_dma_rx = true;
1741 atmel_port->use_pdc_rx = false;
33d64c4f
ES		 1742 } else {
1743 atmel_port->use_dma_rx = false;
92c8f7c0 1744 atmel_port->use_pdc_rx = true;
33d64c4f 1745 }
92c8f7c0
AB		 1746 } else {
1747 atmel_port->use_dma_rx = false;
1748 atmel_port->use_pdc_rx = false;
1749 }
33d64c4f 1750
92c8f7c0
AB		 1751 if (of_property_read_bool(np, "atmel,use-dma-tx")) {
1752 if (of_property_read_bool(np, "dmas")) {
1753 atmel_port->use_dma_tx = true;
1754 atmel_port->use_pdc_tx = false;
33d64c4f
ES		 1755 } else {
1756 atmel_port->use_dma_tx = false;
92c8f7c0 1757 atmel_port->use_pdc_tx = true;
33d64c4f 1758 }
33d64c4f 1759 } else {
33d64c4f 1760 atmel_port->use_dma_tx = false;
92c8f7c0 1761 atmel_port->use_pdc_tx = false;
33d64c4f 1762 }
33d64c4f
ES		 1763}
1764
a930e528
ES		 1765static void atmel_set_ops(struct uart_port *port)
1766{
1767 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1768
34df42f5
ES		 1769 if (atmel_use_dma_rx(port)) {
1770 atmel_port->prepare_rx = &atmel_prepare_rx_dma;
1771 atmel_port->schedule_rx = &atmel_rx_from_dma;
1772 atmel_port->release_rx = &atmel_release_rx_dma;
1773 } else if (atmel_use_pdc_rx(port)) {
a930e528
ES		 1774 atmel_port->prepare_rx = &atmel_prepare_rx_pdc;
1775 atmel_port->schedule_rx = &atmel_rx_from_pdc;
1776 atmel_port->release_rx = &atmel_release_rx_pdc;
1777 } else {
1778 atmel_port->prepare_rx = NULL;
1779 atmel_port->schedule_rx = &atmel_rx_from_ring;
1780 atmel_port->release_rx = NULL;
1781 }
1782
08f738be
ES		 1783 if (atmel_use_dma_tx(port)) {
1784 atmel_port->prepare_tx = &atmel_prepare_tx_dma;
1785 atmel_port->schedule_tx = &atmel_tx_dma;
1786 atmel_port->release_tx = &atmel_release_tx_dma;
1787 } else if (atmel_use_pdc_tx(port)) {
a930e528
ES		 1788 atmel_port->prepare_tx = &atmel_prepare_tx_pdc;
1789 atmel_port->schedule_tx = &atmel_tx_pdc;
1790 atmel_port->release_tx = &atmel_release_tx_pdc;
1791 } else {
1792 atmel_port->prepare_tx = NULL;
1793 atmel_port->schedule_tx = &atmel_tx_chars;
1794 atmel_port->release_tx = NULL;
1795 }
1796}
1797
055560b0
ES		 1798/*
1799 * Get ip name usart or uart
1800 */
892db58b 1801static void atmel_get_ip_name(struct uart_port *port)
055560b0
ES		 1802{
1803 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
4e7decda 1804 int name = atmel_uart_readl(port, ATMEL_US_NAME);
731d9cae 1805 u32 version;
1d673fb9 1806 u32 usart, dbgu_uart, new_uart;
4b769371
NF		 1807 /* ASCII decoding for IP version */
1808 usart = 0x55534152; /* USAR(T) */
1809 dbgu_uart = 0x44424755; /* DBGU */
1d673fb9 1810 new_uart = 0x55415254; /* UART */
055560b0 1811
5bf5635a
LD		 1812 /*
1813 * Only USART devices from at91sam9260 SOC implement fractional
2867af2d
RI		 1814 * baudrate. It is available for all asynchronous modes, with the
1815 * following restriction: the sampling clock's duty cycle is not
1816 * constant.
5bf5635a
LD		 1817 */
1818 atmel_port->has_frac_baudrate = false;
4b769371 1819 atmel_port->has_hw_timer = false;
5644bf18 1820 atmel_port->is_usart = false;
055560b0 1821
2958ccee
LD		 1822 if (name == new_uart) {
1823 dev_dbg(port->dev, "Uart with hw timer");
4b769371 1824 atmel_port->has_hw_timer = true;
2958ccee
LD		 1825 atmel_port->rtor = ATMEL_UA_RTOR;
1826 } else if (name == usart) {
1827 dev_dbg(port->dev, "Usart\n");
5bf5635a 1828 atmel_port->has_frac_baudrate = true;
2958ccee 1829 atmel_port->has_hw_timer = true;
5644bf18 1830 atmel_port->is_usart = true;
2958ccee 1831 atmel_port->rtor = ATMEL_US_RTOR;
377fedd1
NF		 1832 version = atmel_uart_readl(port, ATMEL_US_VERSION);
1833 switch (version) {
1834 case 0x814: /* sama5d2 */
df561f66 1835 fallthrough;
377fedd1
NF		 1836 case 0x701: /* sama5d4 */
1837 atmel_port->fidi_min = 3;
1838 atmel_port->fidi_max = 65535;
1839 break;
1840 case 0x502: /* sam9x5, sama5d3 */
1841 atmel_port->fidi_min = 3;
1842 atmel_port->fidi_max = 2047;
1843 break;
1844 default:
1845 atmel_port->fidi_min = 1;
1846 atmel_port->fidi_max = 2047;
1847 }
4b769371
NF		 1848 } else if (name == dbgu_uart) {
1849 dev_dbg(port->dev, "Dbgu or uart without hw timer\n");
055560b0 1850 } else {
731d9cae 1851 /* fallback for older SoCs: use version field */
4e7decda 1852 version = atmel_uart_readl(port, ATMEL_US_VERSION);
731d9cae
NF		 1853 switch (version) {
1854 case 0x302:
1855 case 0x10213:
fd63a890 1856 case 0x10302:
731d9cae 1857 dev_dbg(port->dev, "This version is usart\n");
5bf5635a 1858 atmel_port->has_frac_baudrate = true;
4b769371 1859 atmel_port->has_hw_timer = true;
5644bf18 1860 atmel_port->is_usart = true;
2958ccee 1861 atmel_port->rtor = ATMEL_US_RTOR;
731d9cae
NF		 1862 break;
1863 case 0x203:
1864 case 0x10202:
1865 dev_dbg(port->dev, "This version is uart\n");
731d9cae
NF		 1866 break;
1867 default:
1868 dev_err(port->dev, "Not supported ip name nor version, set to uart\n");
1869 }
055560b0 1870 }
055560b0
ES		 1871}
1872
1e6c9c28
AV		 1873/*
1874 * Perform initialization and enable port for reception
1875 */
7192f92c 1876static int atmel_startup(struct uart_port *port)
1e6c9c28 1877{
33d64c4f 1878 struct platform_device *pdev = to_platform_device(port->dev);
c811ab8c 1879 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1e6c9c28
AV		 1880 int retval;
1881
1882 /*
1883 * Ensure that no interrupts are enabled otherwise when
1884 * request_irq() is called we could get stuck trying to
1885 * handle an unexpected interrupt
1886 */
4e7decda 1887 atmel_uart_writel(port, ATMEL_US_IDR, -1);
ab5e4e41 1888 atmel_port->ms_irq_enabled = false;
1e6c9c28
AV		 1889
1890 /*
1891 * Allocate the IRQ
1892 */
2c7af5ba 1893 retval = request_irq(port->irq, atmel_interrupt,
9594b5be
SAS		 1894 IRQF_SHARED | IRQF_COND_SUSPEND,
1895 dev_name(&pdev->dev), port);
1e6c9c28 1896 if (retval) {
ddaa6037 1897 dev_err(port->dev, "atmel_startup - Can't get irq\n");
1e6c9c28
AV		 1898 return retval;
1899 }
1900
98f2082c 1901 atomic_set(&atmel_port->tasklet_shutdown, 0);
41e85e44
AP		 1902 tasklet_setup(&atmel_port->tasklet_rx, atmel_tasklet_rx_func);
1903 tasklet_setup(&atmel_port->tasklet_tx, atmel_tasklet_tx_func);
1e125786 1904
a6670615
CC		 1905 /*
1906 * Initialize DMA (if necessary)
1907 */
33d64c4f 1908 atmel_init_property(atmel_port, pdev);
4d9628a1 1909 atmel_set_ops(port);
33d64c4f 1910
a930e528
ES		 1911 if (atmel_port->prepare_rx) {
1912 retval = atmel_port->prepare_rx(port);
1913 if (retval < 0)
1914 atmel_set_ops(port);
a6670615 1915 }
a6670615 1916
a930e528
ES		 1917 if (atmel_port->prepare_tx) {
1918 retval = atmel_port->prepare_tx(port);
1919 if (retval < 0)
1920 atmel_set_ops(port);
a6670615 1921 }
1e6c9c28 1922
b5199d46
CP		 1923 /*
1924 * Enable FIFO when available
1925 */
1926 if (atmel_port->fifo_size) {
1927 unsigned int txrdym = ATMEL_US_ONE_DATA;
1928 unsigned int rxrdym = ATMEL_US_ONE_DATA;
1929 unsigned int fmr;
1930
1931 atmel_uart_writel(port, ATMEL_US_CR,
1932 ATMEL_US_FIFOEN |
1933 ATMEL_US_RXFCLR |
1934 ATMEL_US_TXFLCLR);
1935
5f258b3e
CP		 1936 if (atmel_use_dma_tx(port))
1937 txrdym = ATMEL_US_FOUR_DATA;
1938
b5199d46
CP		 1939 fmr = ATMEL_US_TXRDYM(txrdym) | ATMEL_US_RXRDYM(rxrdym);
1940 if (atmel_port->rts_high &&
1941 atmel_port->rts_low)
1942 fmr |= ATMEL_US_FRTSC |
1943 ATMEL_US_RXFTHRES(atmel_port->rts_high) |
1944 ATMEL_US_RXFTHRES2(atmel_port->rts_low);
1945
1946 atmel_uart_writel(port, ATMEL_US_FMR, fmr);
1947 }
1948
27c0c8e5 1949 /* Save current CSR for comparison in atmel_tasklet_func() */
d2d8d4c0 1950 atmel_port->irq_status_prev = atmel_uart_readl(port, ATMEL_US_CSR);
27c0c8e5 1951
1e6c9c28
AV		 1952 /*
1953 * Finally, enable the serial port
1954 */
4e7decda 1955 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
b843aa21 1956 /* enable xmit & rcvr */
4e7decda 1957 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN);
ea04f82a 1958 atmel_port->tx_stopped = false;
afefc415 1959
026cb432 1960 timer_setup(&atmel_port->uart_timer, atmel_uart_timer_callback, 0);
8bc661bf 1961
64e22ebe 1962 if (atmel_use_pdc_rx(port)) {
a6670615 1963 /* set UART timeout */
4b769371 1964 if (!atmel_port->has_hw_timer) {
2e68c22f
ES		 1965 mod_timer(&atmel_port->uart_timer,
1966 jiffies + uart_poll_timeout(port));
1967 /* set USART timeout */
1968 } else {
2958ccee
LD		 1969 atmel_uart_writel(port, atmel_port->rtor,
1970 PDC_RX_TIMEOUT);
4e7decda 1971 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
a6670615 1972
4e7decda
CP		 1973 atmel_uart_writel(port, ATMEL_US_IER,
1974 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT);
2e68c22f 1975 }
a6670615 1976 /* enable PDC controller */
4e7decda 1977 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN);
34df42f5 1978 } else if (atmel_use_dma_rx(port)) {
2e68c22f 1979 /* set UART timeout */
4b769371 1980 if (!atmel_port->has_hw_timer) {
2e68c22f
ES		 1981 mod_timer(&atmel_port->uart_timer,
1982 jiffies + uart_poll_timeout(port));
1983 /* set USART timeout */
1984 } else {
2958ccee
LD		 1985 atmel_uart_writel(port, atmel_port->rtor,
1986 PDC_RX_TIMEOUT);
4e7decda 1987 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
34df42f5 1988
4e7decda
CP		 1989 atmel_uart_writel(port, ATMEL_US_IER,
1990 ATMEL_US_TIMEOUT);
2e68c22f 1991 }
a6670615
CC		 1992 } else {
1993 /* enable receive only */
4e7decda 1994 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_RXRDY);
a6670615 1995 }
afefc415 1996
1e6c9c28
AV		 1997 return 0;
1998}
1999
479e9b94
PH		 2000/*
2001 * Flush any TX data submitted for DMA. Called when the TX circular
2002 * buffer is reset.
2003 */
2004static void atmel_flush_buffer(struct uart_port *port)
2005{
2006 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2007
2008 if (atmel_use_pdc_tx(port)) {
4e7decda 2009 atmel_uart_writel(port, ATMEL_PDC_TCR, 0);
479e9b94
PH		 2010 atmel_port->pdc_tx.ofs = 0;
2011 }
31ca2c63
RG		 2012 /*
2013 * in uart_flush_buffer(), the xmit circular buffer has just
2014 * been cleared, so we have to reset tx_len accordingly.
2015 */
2016 atmel_port->tx_len = 0;
479e9b94
PH		 2017}
2018
1e6c9c28
AV		 2019/*
2020 * Disable the port
2021 */
7192f92c 2022static void atmel_shutdown(struct uart_port *port)
1e6c9c28 2023{
c811ab8c 2024 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
0cc7c6c7 2025
0ae9fdef
RG		 2026 /* Disable modem control lines interrupts */
2027 atmel_disable_ms(port);
2028
98f2082c
NF		 2029 /* Disable interrupts at device level */
2030 atmel_uart_writel(port, ATMEL_US_IDR, -1);
2031
2032 /* Prevent spurious interrupts from scheduling the tasklet */
2033 atomic_inc(&atmel_port->tasklet_shutdown);
2034
8bc661bf
MR		 2035 /*
2036 * Prevent any tasklets being scheduled during
2037 * cleanup
2038 */
2039 del_timer_sync(&atmel_port->uart_timer);
2040
98f2082c
NF		 2041 /* Make sure that no interrupt is on the fly */
2042 synchronize_irq(port->irq);
2043
0cc7c6c7
MR		 2044 /*
2045 * Clear out any scheduled tasklets before
2046 * we destroy the buffers
2047 */
00e8e658
NF		 2048 tasklet_kill(&atmel_port->tasklet_rx);
2049 tasklet_kill(&atmel_port->tasklet_tx);
0cc7c6c7 2050
a6670615 2051 /*
0cc7c6c7 2052 * Ensure everything is stopped and
98f2082c 2053 * disable port and break condition.
a6670615
CC		 2054 */
2055 atmel_stop_rx(port);
2056 atmel_stop_tx(port);
2057
4e7decda 2058 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
0cc7c6c7 2059
a6670615
CC		 2060 /*
2061 * Shut-down the DMA.
2062 */
a930e528
ES		 2063 if (atmel_port->release_rx)
2064 atmel_port->release_rx(port);
2065 if (atmel_port->release_tx)
2066 atmel_port->release_tx(port);
a6670615 2067
bb7e73c5
MD		 2068 /*
2069 * Reset ring buffer pointers
2070 */
2071 atmel_port->rx_ring.head = 0;
2072 atmel_port->rx_ring.tail = 0;
2073
1e6c9c28 2074 /*
ab5e4e41 2075 * Free the interrupts
1e6c9c28
AV		 2076 */
2077 free_irq(port->irq, port);
ab5e4e41 2078
479e9b94 2079 atmel_flush_buffer(port);
9afd561a
HS		 2080}
2081
1e6c9c28
AV		 2082/*
2083 * Power / Clock management.
2084 */
b843aa21
RB		 2085static void atmel_serial_pm(struct uart_port *port, unsigned int state,
2086 unsigned int oldstate)
1e6c9c28 2087{
c811ab8c 2088 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
afefc415 2089
1e6c9c28 2090 switch (state) {
aec079f8 2091 case UART_PM_STATE_ON:
b843aa21
RB		 2092 /*
2093 * Enable the peripheral clock for this serial port.
2094 * This is called on uart_open() or a resume event.
2095 */
91f8c2d8 2096 clk_prepare_enable(atmel_port->clk);
f05596db
AS		 2097
2098 /* re-enable interrupts if we disabled some on suspend */
4e7decda 2099 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->backup_imr);
b843aa21 2100 break;
aec079f8 2101 case UART_PM_STATE_OFF:
f05596db 2102 /* Back up the interrupt mask and disable all interrupts */
4e7decda
CP		 2103 atmel_port->backup_imr = atmel_uart_readl(port, ATMEL_US_IMR);
2104 atmel_uart_writel(port, ATMEL_US_IDR, -1);
f05596db 2105
b843aa21
RB		 2106 /*
2107 * Disable the peripheral clock for this serial port.
2108 * This is called on uart_close() or a suspend event.
2109 */
91f8c2d8 2110 clk_disable_unprepare(atmel_port->clk);
5e3ce1f2
SM		 2111 if (__clk_is_enabled(atmel_port->gclk))
2112 clk_disable_unprepare(atmel_port->gclk);
b843aa21
RB		 2113 break;
2114 default:
ddaa6037 2115 dev_err(port->dev, "atmel_serial: unknown pm %d\n", state);
1e6c9c28
AV		 2116 }
2117}
2118
2119/*
2120 * Change the port parameters
2121 */
bec5b814
IJ		 2122static void atmel_set_termios(struct uart_port *port,
2123 struct ktermios *termios,
2124 const struct ktermios *old)
1e6c9c28 2125{
5bf5635a 2126 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1e6c9c28 2127 unsigned long flags;
5e3ce1f2
SM		 2128 unsigned int old_mode, mode, imr, quot, div, cd, fp = 0;
2129 unsigned int baud, actual_baud, gclk_rate;
2130 int ret;
1cf6e8fc
CP		 2131
2132 /* save the current mode register */
4e7decda 2133 mode = old_mode = atmel_uart_readl(port, ATMEL_US_MR);
1e6c9c28 2134
1cf6e8fc 2135 /* reset the mode, clock divisor, parity, stop bits and data size */
1a5a01a1
SM		 2136 if (atmel_port->is_usart)
2137 mode &= ~(ATMEL_US_NBSTOP | ATMEL_US_PAR | ATMEL_US_CHRL |
2138 ATMEL_US_USCLKS | ATMEL_US_USMODE);
2139 else
2140 mode &= ~(ATMEL_UA_BRSRCCK | ATMEL_US_PAR | ATMEL_UA_FILTER);
03abeac0 2141
b843aa21 2142 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
1e6c9c28
AV		 2143
2144 /* byte size */
2145 switch (termios->c_cflag & CSIZE) {
2146 case CS5:
7192f92c 2147 mode |= ATMEL_US_CHRL_5;
1e6c9c28
AV		 2148 break;
2149 case CS6:
7192f92c 2150 mode |= ATMEL_US_CHRL_6;
1e6c9c28
AV		 2151 break;
2152 case CS7:
7192f92c 2153 mode |= ATMEL_US_CHRL_7;
1e6c9c28
AV		 2154 break;
2155 default:
7192f92c 2156 mode |= ATMEL_US_CHRL_8;
1e6c9c28
AV		 2157 break;
2158 }
2159
2160 /* stop bits */
2161 if (termios->c_cflag & CSTOPB)
7192f92c 2162 mode |= ATMEL_US_NBSTOP_2;
1e6c9c28
AV		 2163
2164 /* parity */
2165 if (termios->c_cflag & PARENB) {
b843aa21
RB		 2166 /* Mark or Space parity */
2167 if (termios->c_cflag & CMSPAR) {
1e6c9c28 2168 if (termios->c_cflag & PARODD)
7192f92c 2169 mode |= ATMEL_US_PAR_MARK;
1e6c9c28 2170 else
7192f92c 2171 mode |= ATMEL_US_PAR_SPACE;
b843aa21 2172 } else if (termios->c_cflag & PARODD)
7192f92c 2173 mode |= ATMEL_US_PAR_ODD;
1e6c9c28 2174 else
7192f92c 2175 mode |= ATMEL_US_PAR_EVEN;
b843aa21 2176 } else
7192f92c 2177 mode |= ATMEL_US_PAR_NONE;
1e6c9c28
AV		 2178
2179 spin_lock_irqsave(&port->lock, flags);
2180
7192f92c 2181 port->read_status_mask = ATMEL_US_OVRE;
1e6c9c28 2182 if (termios->c_iflag & INPCK)
7192f92c 2183 port->read_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE);
ef8b9ddc 2184 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
7192f92c 2185 port->read_status_mask |= ATMEL_US_RXBRK;
1e6c9c28 2186
64e22ebe 2187 if (atmel_use_pdc_rx(port))
a6670615 2188 /* need to enable error interrupts */
4e7decda 2189 atmel_uart_writel(port, ATMEL_US_IER, port->read_status_mask);
a6670615 2190
1e6c9c28
AV		 2191 /*
2192 * Characters to ignore
2193 */
2194 port->ignore_status_mask = 0;
2195 if (termios->c_iflag & IGNPAR)
7192f92c 2196 port->ignore_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE);
1e6c9c28 2197 if (termios->c_iflag & IGNBRK) {
7192f92c 2198 port->ignore_status_mask |= ATMEL_US_RXBRK;
1e6c9c28
AV		 2199 /*
2200 * If we're ignoring parity and break indicators,
2201 * ignore overruns too (for real raw support).
2202 */
2203 if (termios->c_iflag & IGNPAR)
7192f92c 2204 port->ignore_status_mask |= ATMEL_US_OVRE;
1e6c9c28 2205 }
b843aa21 2206 /* TODO: Ignore all characters if CREAD is set.*/
1e6c9c28
AV		 2207
2208 /* update the per-port timeout */
2209 uart_update_timeout(port, termios->c_cflag, baud);
2210
0ccad870
HS		 2211 /*
2212 * save/disable interrupts. The tty layer will ensure that the
2213 * transmitter is empty if requested by the caller, so there's
2214 * no need to wait for it here.
2215 */
4e7decda
CP		 2216 imr = atmel_uart_readl(port, ATMEL_US_IMR);
2217 atmel_uart_writel(port, ATMEL_US_IDR, -1);
1e6c9c28
AV		 2218
2219 /* disable receiver and transmitter */
4e7decda 2220 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXDIS | ATMEL_US_RXDIS);
ea04f82a 2221 atmel_port->tx_stopped = true;
1e6c9c28 2222
1cf6e8fc 2223 /* mode */
13bd3e6f 2224 if (port->rs485.flags & SER_RS485_ENABLED) {
4e7decda
CP		 2225 atmel_uart_writel(port, ATMEL_US_TTGR,
2226 port->rs485.delay_rts_after_send);
e8faff73 2227 mode |= ATMEL_US_USMODE_RS485;
377fedd1
NF		 2228 } else if (port->iso7816.flags & SER_ISO7816_ENABLED) {
2229 atmel_uart_writel(port, ATMEL_US_TTGR, port->iso7816.tg);
2230 /* select mck clock, and output */
2231 mode |= ATMEL_US_USCLKS_MCK | ATMEL_US_CLKO;
2232 /* set max iterations */
2233 mode |= ATMEL_US_MAX_ITER(3);
2234 if ((port->iso7816.flags & SER_ISO7816_T_PARAM)
2235 == SER_ISO7816_T(0))
2236 mode |= ATMEL_US_USMODE_ISO7816_T0;
2237 else
2238 mode |= ATMEL_US_USMODE_ISO7816_T1;
1cf6e8fc
CP		 2239 } else if (termios->c_cflag & CRTSCTS) {
2240 /* RS232 with hardware handshake (RTS/CTS) */
9bcffe75
RG		 2241 if (atmel_use_fifo(port) &&
2242 !mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_CTS)) {
2243 /*
2244 * with ATMEL_US_USMODE_HWHS set, the controller will
2245 * be able to drive the RTS pin high/low when the RX
2246 * FIFO is above RXFTHRES/below RXFTHRES2.
2247 * It will also disable the transmitter when the CTS
2248 * pin is high.
2249 * This mode is not activated if CTS pin is a GPIO
2250 * because in this case, the transmitter is always
2251 * disabled (there must be an internal pull-up
2252 * responsible for this behaviour).
2253 * If the RTS pin is a GPIO, the controller won't be
2254 * able to drive it according to the FIFO thresholds,
2255 * but it will be handled by the driver.
2256 */
5be605ac 2257 mode |= ATMEL_US_USMODE_HWHS;
9bcffe75
RG		 2258 } else {
2259 /*
2260 * For platforms without FIFO, the flow control is
2261 * handled by the driver.
2262 */
2263 mode |= ATMEL_US_USMODE_NORMAL;
5be605ac 2264 }
1cf6e8fc
CP		 2265 } else {
2266 /* RS232 without hadware handshake */
2267 mode |= ATMEL_US_USMODE_NORMAL;
e8faff73
CS		 2268 }
2269
5bf5635a
LD		 2270 /*
2271 * Set the baud rate:
2272 * Fractional baudrate allows to setup output frequency more
2273 * accurately. This feature is enabled only when using normal mode.
2274 * baudrate = selected clock / (8 * (2 - OVER) * (CD + FP / 8))
2275 * Currently, OVER is always set to 0 so we get
36131cdf
AS		 2276 * baudrate = selected clock / (16 * (CD + FP / 8))
2277 * then
2278 * 8 CD + FP = selected clock / (2 * baudrate)
5bf5635a 2279 */
2867af2d 2280 if (atmel_port->has_frac_baudrate) {
36131cdf
AS		 2281 div = DIV_ROUND_CLOSEST(port->uartclk, baud * 2);
2282 cd = div >> 3;
2283 fp = div & ATMEL_US_FP_MASK;
5bf5635a
LD		 2284 } else {
2285 cd = uart_get_divisor(port, baud);
2286 }
2287
5644bf18
SM		 2288 /*
2289 * If the current value of the Clock Divisor surpasses the 16 bit
2290 * ATMEL_US_CD mask and the IP is USART, switch to the Peripheral
2291 * Clock implicitly divided by 8.
2292 * If the IP is UART however, keep the highest possible value for
2293 * the CD and avoid needless division of CD, since UART IP's do not
2294 * support implicit division of the Peripheral Clock.
2295 */
2296 if (atmel_port->is_usart && cd > ATMEL_US_CD) {
5bf5635a
LD		 2297 cd /= 8;
2298 mode |= ATMEL_US_USCLKS_MCK_DIV8;
5644bf18
SM		 2299 } else {
2300 cd = min_t(unsigned int, cd, ATMEL_US_CD);
5bf5635a 2301 }
5644bf18 2302
5e3ce1f2
SM		 2303 /*
2304 * If there is no Fractional Part, there is a high chance that
2305 * we may be able to generate a baudrate closer to the desired one
2306 * if we use the GCLK as the clock source driving the baudrate
2307 * generator.
2308 */
2309 if (!atmel_port->has_frac_baudrate) {
2310 if (__clk_is_enabled(atmel_port->gclk))
2311 clk_disable_unprepare(atmel_port->gclk);
2312 gclk_rate = clk_round_rate(atmel_port->gclk, 16 * baud);
2313 actual_baud = clk_get_rate(atmel_port->clk) / (16 * cd);
2314 if (gclk_rate && abs(atmel_error_rate(baud, actual_baud)) >
2315 abs(atmel_error_rate(baud, gclk_rate / 16))) {
2316 clk_set_rate(atmel_port->gclk, 16 * baud);
2317 ret = clk_prepare_enable(atmel_port->gclk);
2318 if (ret)
2319 goto gclk_fail;
2320
2321 if (atmel_port->is_usart) {
2322 mode &= ~ATMEL_US_USCLKS;
2323 mode |= ATMEL_US_USCLKS_GCLK;
2324 } else {
2325 mode |= ATMEL_UA_BRSRCCK;
2326 }
2327
2328 /*
2329 * Set the Clock Divisor for GCLK to 1.
2330 * Since we were able to generate the smallest
2331 * multiple of the desired baudrate times 16,
2332 * then we surely can generate a bigger multiple
2333 * with the exact error rate for an equally increased
2334 * CD. Thus no need to take into account
2335 * a higher value for CD.
2336 */
2337 cd = 1;
2338 }
2339 }
2340
2341gclk_fail:
5bf5635a
LD		 2342 quot = cd | fp << ATMEL_US_FP_OFFSET;
2343
377fedd1
NF		 2344 if (!(port->iso7816.flags & SER_ISO7816_ENABLED))
2345 atmel_uart_writel(port, ATMEL_US_BRGR, quot);
cb47b9f8
DE		 2346
2347 /* set the mode, clock divisor, parity, stop bits and data size */
2348 atmel_uart_writel(port, ATMEL_US_MR, mode);
2349
2350 /*
2351 * when switching the mode, set the RTS line state according to the
2352 * new mode, otherwise keep the former state
2353 */
2354 if ((old_mode & ATMEL_US_USMODE) != (mode & ATMEL_US_USMODE)) {
2355 unsigned int rts_state;
2356
2357 if ((mode & ATMEL_US_USMODE) == ATMEL_US_USMODE_HWHS) {
2358 /* let the hardware control the RTS line */
2359 rts_state = ATMEL_US_RTSDIS;
2360 } else {
2361 /* force RTS line to low level */
2362 rts_state = ATMEL_US_RTSEN;
2363 }
2364
2365 atmel_uart_writel(port, ATMEL_US_CR, rts_state);
2366 }
2367
4e7decda
CP		 2368 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
2369 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN);
ea04f82a 2370 atmel_port->tx_stopped = false;
1e6c9c28
AV		 2371
2372 /* restore interrupts */
4e7decda 2373 atmel_uart_writel(port, ATMEL_US_IER, imr);
1e6c9c28
AV		 2374
2375 /* CTS flow-control and modem-status interrupts */
2376 if (UART_ENABLE_MS(port, termios->c_cflag))
35b675b9
RG		 2377 atmel_enable_ms(port);
2378 else
2379 atmel_disable_ms(port);
1e6c9c28
AV		 2380
2381 spin_unlock_irqrestore(&port->lock, flags);
2382}
2383
732a84a0 2384static void atmel_set_ldisc(struct uart_port *port, struct ktermios *termios)
42bd7a4f 2385{
732a84a0 2386 if (termios->c_line == N_PPS) {
42bd7a4f 2387 port->flags |= UPF_HARDPPS_CD;
d41510ce 2388 spin_lock_irq(&port->lock);
42bd7a4f 2389 atmel_enable_ms(port);
d41510ce 2390 spin_unlock_irq(&port->lock);
42bd7a4f
VP		 2391 } else {
2392 port->flags &= ~UPF_HARDPPS_CD;
cab68f89
PH		 2393 if (!UART_ENABLE_MS(port, termios->c_cflag)) {
2394 spin_lock_irq(&port->lock);
2395 atmel_disable_ms(port);
2396 spin_unlock_irq(&port->lock);
2397 }
42bd7a4f
VP		 2398 }
2399}
2400
1e6c9c28
AV		 2401/*
2402 * Return string describing the specified port
2403 */
7192f92c 2404static const char *atmel_type(struct uart_port *port)
1e6c9c28 2405{
9ab4f88b 2406 return (port->type == PORT_ATMEL) ? "ATMEL_SERIAL" : NULL;
1e6c9c28
AV		 2407}
2408
2409/*
2410 * Release the memory region(s) being used by 'port'.
2411 */
7192f92c 2412static void atmel_release_port(struct uart_port *port)
1e6c9c28 2413{
c24d2531
RP		 2414 struct platform_device *mpdev = to_platform_device(port->dev->parent);
2415 int size = resource_size(mpdev->resource);
afefc415
AV		 2416
2417 release_mem_region(port->mapbase, size);
2418
2419 if (port->flags & UPF_IOREMAP) {
2420 iounmap(port->membase);
2421 port->membase = NULL;
2422 }
1e6c9c28
AV		 2423}
2424
2425/*
2426 * Request the memory region(s) being used by 'port'.
2427 */
7192f92c 2428static int atmel_request_port(struct uart_port *port)
1e6c9c28 2429{
c24d2531
RP		 2430 struct platform_device *mpdev = to_platform_device(port->dev->parent);
2431 int size = resource_size(mpdev->resource);
afefc415 2432
7192f92c 2433 if (!request_mem_region(port->mapbase, size, "atmel_serial"))
afefc415
AV		 2434 return -EBUSY;
2435
2436 if (port->flags & UPF_IOREMAP) {
2437 port->membase = ioremap(port->mapbase, size);
2438 if (port->membase == NULL) {
2439 release_mem_region(port->mapbase, size);
2440 return -ENOMEM;
2441 }
2442 }
1e6c9c28 2443
afefc415 2444 return 0;
1e6c9c28
AV		 2445}
2446
2447/*
2448 * Configure/autoconfigure the port.
2449 */
7192f92c 2450static void atmel_config_port(struct uart_port *port, int flags)
1e6c9c28
AV		 2451{
2452 if (flags & UART_CONFIG_TYPE) {
9ab4f88b 2453 port->type = PORT_ATMEL;
7192f92c 2454 atmel_request_port(port);
1e6c9c28
AV		 2455 }
2456}
2457
2458/*
2459 * Verify the new serial_struct (for TIOCSSERIAL).
2460 */
7192f92c 2461static int atmel_verify_port(struct uart_port *port, struct serial_struct *ser)
1e6c9c28
AV		 2462{
2463 int ret = 0;
9ab4f88b 2464 if (ser->type != PORT_UNKNOWN && ser->type != PORT_ATMEL)
1e6c9c28
AV		 2465 ret = -EINVAL;
2466 if (port->irq != ser->irq)
2467 ret = -EINVAL;
2468 if (ser->io_type != SERIAL_IO_MEM)
2469 ret = -EINVAL;
2470 if (port->uartclk / 16 != ser->baud_base)
2471 ret = -EINVAL;
270c2ade 2472 if (port->mapbase != (unsigned long)ser->iomem_base)
1e6c9c28
AV		 2473 ret = -EINVAL;
2474 if (port->iobase != ser->port)
2475 ret = -EINVAL;
2476 if (ser->hub6 != 0)
2477 ret = -EINVAL;
2478 return ret;
2479}
2480
8fe2d541
AT		 2481#ifdef CONFIG_CONSOLE_POLL
2482static int atmel_poll_get_char(struct uart_port *port)
2483{
4e7decda 2484 while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_RXRDY))
8fe2d541
AT		 2485 cpu_relax();
2486
a6499435 2487 return atmel_uart_read_char(port);
8fe2d541
AT		 2488}
2489
2490static void atmel_poll_put_char(struct uart_port *port, unsigned char ch)
2491{
4e7decda 2492 while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXRDY))
8fe2d541
AT		 2493 cpu_relax();
2494
a6499435 2495 atmel_uart_write_char(port, ch);
8fe2d541
AT		 2496}
2497#endif
2498
5c7dcdb6 2499static const struct uart_ops atmel_pops = {
7192f92c
HS		 2500 .tx_empty = atmel_tx_empty,
2501 .set_mctrl = atmel_set_mctrl,
2502 .get_mctrl = atmel_get_mctrl,
2503 .stop_tx = atmel_stop_tx,
2504 .start_tx = atmel_start_tx,
2505 .stop_rx = atmel_stop_rx,
2506 .enable_ms = atmel_enable_ms,
2507 .break_ctl = atmel_break_ctl,
2508 .startup = atmel_startup,
2509 .shutdown = atmel_shutdown,
9afd561a 2510 .flush_buffer = atmel_flush_buffer,
7192f92c 2511 .set_termios = atmel_set_termios,
42bd7a4f 2512 .set_ldisc = atmel_set_ldisc,
7192f92c
HS		 2513 .type = atmel_type,
2514 .release_port = atmel_release_port,
2515 .request_port = atmel_request_port,
2516 .config_port = atmel_config_port,
2517 .verify_port = atmel_verify_port,
2518 .pm = atmel_serial_pm,
8fe2d541
AT		 2519#ifdef CONFIG_CONSOLE_POLL
2520 .poll_get_char = atmel_poll_get_char,
2521 .poll_put_char = atmel_poll_put_char,
2522#endif
1e6c9c28
AV		 2523};
2524
af47c491
IJ		 2525static const struct serial_rs485 atmel_rs485_supported = {
2526 .flags = SER_RS485_ENABLED | SER_RS485_RTS_AFTER_SEND | SER_RS485_RX_DURING_TX,
2527 .delay_rts_before_send = 1,
2528 .delay_rts_after_send = 1,
2529};
2530
afefc415
AV		 2531/*
2532 * Configure the port from the platform device resource info.
2533 */
91f8c2d8 2534static int atmel_init_port(struct atmel_uart_port *atmel_port,
b843aa21 2535 struct platform_device *pdev)
1e6c9c28 2536{
91f8c2d8 2537 int ret;
7192f92c 2538 struct uart_port *port = &atmel_port->uart;
c24d2531 2539 struct platform_device *mpdev = to_platform_device(pdev->dev.parent);
afefc415 2540
4a1e8888
LZ		 2541 atmel_init_property(atmel_port, pdev);
2542 atmel_set_ops(port);
afefc415 2543
e8faff73 2544 port->iotype = UPIO_MEM;
92c8f7c0 2545 port->flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP;
e8faff73
CS		 2546 port->ops = &atmel_pops;
2547 port->fifosize = 1;
e8faff73 2548 port->dev = &pdev->dev;
c24d2531 2549 port->mapbase = mpdev->resource[0].start;
5bb221b0 2550 port->irq = platform_get_irq(mpdev, 0);
13bd3e6f 2551 port->rs485_config = atmel_config_rs485;
0139da50 2552 port->rs485_supported = atmel_rs485_supported;
377fedd1 2553 port->iso7816_config = atmel_config_iso7816;
c24d2531 2554 port->membase = NULL;
afefc415 2555
1ecc26bd
RB		 2556 memset(&atmel_port->rx_ring, 0, sizeof(atmel_port->rx_ring));
2557
c150c0f3
LW		 2558 ret = uart_get_rs485_mode(port);
2559 if (ret)
2560 return ret;
2561
84b476b1 2562 port->uartclk = clk_get_rate(atmel_port->clk);
a6670615 2563
377fedd1
NF		 2564 /*
2565 * Use TXEMPTY for interrupt when rs485 or ISO7816 else TXRDY or
2566 * ENDTX|TXBUFE
2567 */
477b8383 2568 if (atmel_uart_is_half_duplex(port))
e8faff73 2569 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY;
64e22ebe 2570 else if (atmel_use_pdc_tx(port)) {
a6670615 2571 port->fifosize = PDC_BUFFER_SIZE;
e8faff73
CS		 2572 atmel_port->tx_done_mask = ATMEL_US_ENDTX | ATMEL_US_TXBUFE;
2573 } else {
2574 atmel_port->tx_done_mask = ATMEL_US_TXRDY;
2575 }
91f8c2d8
BB		 2576
2577 return 0;
1e6c9c28
AV		 2578}
2579
749c4e60 2580#ifdef CONFIG_SERIAL_ATMEL_CONSOLE
3f8bab17 2581static void atmel_console_putchar(struct uart_port *port, unsigned char ch)
d358788f 2582{
4e7decda 2583 while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXRDY))
829dd811 2584 cpu_relax();
a6499435 2585 atmel_uart_write_char(port, ch);
d358788f 2586}
1e6c9c28
AV		 2587
2588/*
2589 * Interrupts are disabled on entering
2590 */
7192f92c 2591static void atmel_console_write(struct console *co, const char *s, u_int count)
1e6c9c28 2592{
7192f92c 2593 struct uart_port *port = &atmel_ports[co->index].uart;
e8faff73 2594 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
d358788f 2595 unsigned int status, imr;
39d4c922 2596 unsigned int pdc_tx;
1e6c9c28
AV		 2597
2598 /*
b843aa21 2599 * First, save IMR and then disable interrupts
1e6c9c28 2600 */
4e7decda
CP		 2601 imr = atmel_uart_readl(port, ATMEL_US_IMR);
2602 atmel_uart_writel(port, ATMEL_US_IDR,
2603 ATMEL_US_RXRDY | atmel_port->tx_done_mask);
1e6c9c28 2604
39d4c922 2605 /* Store PDC transmit status and disable it */
4e7decda
CP		 2606 pdc_tx = atmel_uart_readl(port, ATMEL_PDC_PTSR) & ATMEL_PDC_TXTEN;
2607 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS);
39d4c922 2608
497e1e16
NF		 2609 /* Make sure that tx path is actually able to send characters */
2610 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN);
ea04f82a 2611 atmel_port->tx_stopped = false;
497e1e16 2612
7192f92c 2613 uart_console_write(port, s, count, atmel_console_putchar);
1e6c9c28
AV		 2614
2615 /*
b843aa21
RB		 2616 * Finally, wait for transmitter to become empty
2617 * and restore IMR
1e6c9c28
AV		 2618 */
2619 do {
4e7decda 2620 status = atmel_uart_readl(port, ATMEL_US_CSR);
7192f92c 2621 } while (!(status & ATMEL_US_TXRDY));
39d4c922
MP		 2622
2623 /* Restore PDC transmit status */
2624 if (pdc_tx)
4e7decda 2625 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
39d4c922 2626
b843aa21 2627 /* set interrupts back the way they were */
4e7decda 2628 atmel_uart_writel(port, ATMEL_US_IER, imr);
1e6c9c28
AV		 2629}
2630
2631/*
b843aa21
RB		 2632 * If the port was already initialised (eg, by a boot loader),
2633 * try to determine the current setup.
1e6c9c28 2634 */
b843aa21
RB		 2635static void __init atmel_console_get_options(struct uart_port *port, int *baud,
2636 int *parity, int *bits)
1e6c9c28
AV		 2637{
2638 unsigned int mr, quot;
2639
1c0fd82f
HS		 2640 /*
2641 * If the baud rate generator isn't running, the port wasn't
2642 * initialized by the boot loader.
2643 */
4e7decda 2644 quot = atmel_uart_readl(port, ATMEL_US_BRGR) & ATMEL_US_CD;
1c0fd82f
HS		 2645 if (!quot)
2646 return;
1e6c9c28 2647
4e7decda 2648 mr = atmel_uart_readl(port, ATMEL_US_MR) & ATMEL_US_CHRL;
7192f92c 2649 if (mr == ATMEL_US_CHRL_8)
1e6c9c28
AV		 2650 *bits = 8;
2651 else
2652 *bits = 7;
2653
4e7decda 2654 mr = atmel_uart_readl(port, ATMEL_US_MR) & ATMEL_US_PAR;
7192f92c 2655 if (mr == ATMEL_US_PAR_EVEN)
1e6c9c28 2656 *parity = 'e';
7192f92c 2657 else if (mr == ATMEL_US_PAR_ODD)
1e6c9c28
AV		 2658 *parity = 'o';
2659
4d5e392c
HS		 2660 /*
2661 * The serial core only rounds down when matching this to a
2662 * supported baud rate. Make sure we don't end up slightly
2663 * lower than one of those, as it would make us fall through
2664 * to a much lower baud rate than we really want.
2665 */
4d5e392c 2666 *baud = port->uartclk / (16 * (quot - 1));
1e6c9c28
AV		 2667}
2668
7192f92c 2669static int __init atmel_console_setup(struct console *co, char *options)
1e6c9c28 2670{
7192f92c 2671 struct uart_port *port = &atmel_ports[co->index].uart;
ea04f82a 2672 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1e6c9c28
AV		 2673 int baud = 115200;
2674 int bits = 8;
2675 int parity = 'n';
2676 int flow = 'n';
2677
b843aa21
RB		 2678 if (port->membase == NULL) {
2679 /* Port not initialized yet - delay setup */
afefc415 2680 return -ENODEV;
b843aa21 2681 }
1e6c9c28 2682
4e7decda
CP		 2683 atmel_uart_writel(port, ATMEL_US_IDR, -1);
2684 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
2685 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN);
ea04f82a 2686 atmel_port->tx_stopped = false;
1e6c9c28
AV		 2687
2688 if (options)
2689 uart_parse_options(options, &baud, &parity, &bits, &flow);
2690 else
7192f92c 2691 atmel_console_get_options(port, &baud, &parity, &bits);
1e6c9c28
AV		 2692
2693 return uart_set_options(port, co, baud, parity, bits, flow);
2694}
2695
7192f92c 2696static struct uart_driver atmel_uart;
1e6c9c28 2697
7192f92c
HS		 2698static struct console atmel_console = {
2699 .name = ATMEL_DEVICENAME,
2700 .write = atmel_console_write,
1e6c9c28 2701 .device = uart_console_device,
7192f92c 2702 .setup = atmel_console_setup,
1e6c9c28
AV		 2703 .flags = CON_PRINTBUFFER,
2704 .index = -1,
7192f92c 2705 .data = &atmel_uart,
1e6c9c28
AV		 2706};
2707
aab68e95
MW		 2708static void atmel_serial_early_write(struct console *con, const char *s,
2709 unsigned int n)
2710{
2711 struct earlycon_device *dev = con->data;
2712
2713 uart_console_write(&dev->port, s, n, atmel_console_putchar);
2714}
2715
2716static int __init atmel_early_console_setup(struct earlycon_device *device,
2717 const char *options)
2718{
2719 if (!device->port.membase)
2720 return -ENODEV;
2721
2722 device->con->write = atmel_serial_early_write;
2723
2724 return 0;
2725}
2726
2727OF_EARLYCON_DECLARE(atmel_serial, "atmel,at91rm9200-usart",
2728 atmel_early_console_setup);
2729OF_EARLYCON_DECLARE(atmel_serial, "atmel,at91sam9260-usart",
2730 atmel_early_console_setup);
2731
06a7f058 2732#define ATMEL_CONSOLE_DEVICE (&atmel_console)
1e6c9c28 2733
1e6c9c28 2734#else
7192f92c 2735#define ATMEL_CONSOLE_DEVICE NULL
1e6c9c28
AV		 2736#endif
2737
7192f92c 2738static struct uart_driver atmel_uart = {
b843aa21
RB		 2739 .owner = THIS_MODULE,
2740 .driver_name = "atmel_serial",
2741 .dev_name = ATMEL_DEVICENAME,
2742 .major = SERIAL_ATMEL_MAJOR,
2743 .minor = MINOR_START,
2744 .nr = ATMEL_MAX_UART,
2745 .cons = ATMEL_CONSOLE_DEVICE,
1e6c9c28
AV		 2746};
2747
f826caa4
HS		 2748static bool atmel_serial_clk_will_stop(void)
2749{
2750#ifdef CONFIG_ARCH_AT91
2751 return at91_suspend_entering_slow_clock();
2752#else
2753 return false;
2754#endif
2755}
2756
b50058b8 2757static int __maybe_unused atmel_serial_suspend(struct device *dev)
1e6c9c28 2758{
b50058b8 2759 struct uart_port *port = dev_get_drvdata(dev);
c811ab8c 2760 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
afefc415 2761
207f6f34 2762 if (uart_console(port) && console_suspend_enabled) {
e1c609ef 2763 /* Drain the TX shifter */
4e7decda
CP		 2764 while (!(atmel_uart_readl(port, ATMEL_US_CSR) &
2765 ATMEL_US_TXEMPTY))
e1c609ef
HS		 2766 cpu_relax();
2767 }
2768
207f6f34 2769 if (uart_console(port) && !console_suspend_enabled) {
6a5f0e2f
AB		 2770 /* Cache register values as we won't get a full shutdown/startup
2771 * cycle
2772 */
2773 atmel_port->cache.mr = atmel_uart_readl(port, ATMEL_US_MR);
2774 atmel_port->cache.imr = atmel_uart_readl(port, ATMEL_US_IMR);
2775 atmel_port->cache.brgr = atmel_uart_readl(port, ATMEL_US_BRGR);
2776 atmel_port->cache.rtor = atmel_uart_readl(port,
2777 atmel_port->rtor);
2778 atmel_port->cache.ttgr = atmel_uart_readl(port, ATMEL_US_TTGR);
2779 atmel_port->cache.fmr = atmel_uart_readl(port, ATMEL_US_FMR);
2780 atmel_port->cache.fimr = atmel_uart_readl(port, ATMEL_US_FIMR);
2781 }
2782
f05596db 2783 /* we can not wake up if we're running on slow clock */
b50058b8 2784 atmel_port->may_wakeup = device_may_wakeup(dev);
2c7af5ba
BB		 2785 if (atmel_serial_clk_will_stop()) {
2786 unsigned long flags;
2787
2788 spin_lock_irqsave(&atmel_port->lock_suspended, flags);
2789 atmel_port->suspended = true;
2790 spin_unlock_irqrestore(&atmel_port->lock_suspended, flags);
b50058b8 2791 device_set_wakeup_enable(dev, 0);
2c7af5ba 2792 }
f05596db
AS		 2793
2794 uart_suspend_port(&atmel_uart, port);
1e6c9c28 2795
afefc415
AV		 2796 return 0;
2797}
1e6c9c28 2798
b50058b8 2799static int __maybe_unused atmel_serial_resume(struct device *dev)
afefc415 2800{
b50058b8 2801 struct uart_port *port = dev_get_drvdata(dev);
c811ab8c 2802 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2c7af5ba
BB		 2803 unsigned long flags;
2804
207f6f34 2805 if (uart_console(port) && !console_suspend_enabled) {
6a5f0e2f
AB		 2806 atmel_uart_writel(port, ATMEL_US_MR, atmel_port->cache.mr);
2807 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->cache.imr);
2808 atmel_uart_writel(port, ATMEL_US_BRGR, atmel_port->cache.brgr);
2809 atmel_uart_writel(port, atmel_port->rtor,
2810 atmel_port->cache.rtor);
2811 atmel_uart_writel(port, ATMEL_US_TTGR, atmel_port->cache.ttgr);
2812
2813 if (atmel_port->fifo_size) {
2814 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_FIFOEN |
2815 ATMEL_US_RXFCLR | ATMEL_US_TXFLCLR);
2816 atmel_uart_writel(port, ATMEL_US_FMR,
2817 atmel_port->cache.fmr);
2818 atmel_uart_writel(port, ATMEL_US_FIER,
2819 atmel_port->cache.fimr);
2820 }
2821 atmel_start_rx(port);
2822 }
2823
2c7af5ba
BB		 2824 spin_lock_irqsave(&atmel_port->lock_suspended, flags);
2825 if (atmel_port->pending) {
2826 atmel_handle_receive(port, atmel_port->pending);
2827 atmel_handle_status(port, atmel_port->pending,
2828 atmel_port->pending_status);
2829 atmel_handle_transmit(port, atmel_port->pending);
2830 atmel_port->pending = 0;
2831 }
2832 atmel_port->suspended = false;
2833 spin_unlock_irqrestore(&atmel_port->lock_suspended, flags);
1e6c9c28 2834
f05596db 2835 uart_resume_port(&atmel_uart, port);
b50058b8 2836 device_set_wakeup_enable(dev, atmel_port->may_wakeup);
1e6c9c28
AV		 2837
2838 return 0;
2839}
2840
b78cd169 2841static void atmel_serial_probe_fifos(struct atmel_uart_port *atmel_port,
b5199d46
CP		 2842 struct platform_device *pdev)
2843{
b78cd169
JA		 2844 atmel_port->fifo_size = 0;
2845 atmel_port->rts_low = 0;
2846 atmel_port->rts_high = 0;
b5199d46
CP		 2847
2848 if (of_property_read_u32(pdev->dev.of_node,
2849 "atmel,fifo-size",
b78cd169 2850 &atmel_port->fifo_size))
b5199d46
CP		 2851 return;
2852
b78cd169 2853 if (!atmel_port->fifo_size)
b5199d46
CP		 2854 return;
2855
b78cd169
JA		 2856 if (atmel_port->fifo_size < ATMEL_MIN_FIFO_SIZE) {
2857 atmel_port->fifo_size = 0;
b5199d46
CP		 2858 dev_err(&pdev->dev, "Invalid FIFO size\n");
2859 return;
2860 }
2861
2862 /*
2863 * 0 <= rts_low <= rts_high <= fifo_size
2864 * Once their CTS line asserted by the remote peer, some x86 UARTs tend
2865 * to flush their internal TX FIFO, commonly up to 16 data, before
2866 * actually stopping to send new data. So we try to set the RTS High
2867 * Threshold to a reasonably high value respecting this 16 data
2868 * empirical rule when possible.
2869 */
b78cd169
JA		 2870 atmel_port->rts_high = max_t(int, atmel_port->fifo_size >> 1,
2871 atmel_port->fifo_size - ATMEL_RTS_HIGH_OFFSET);
2872 atmel_port->rts_low = max_t(int, atmel_port->fifo_size >> 2,
2873 atmel_port->fifo_size - ATMEL_RTS_LOW_OFFSET);
b5199d46
CP		 2874
2875 dev_info(&pdev->dev, "Using FIFO (%u data)\n",
b78cd169 2876 atmel_port->fifo_size);
b5199d46 2877 dev_dbg(&pdev->dev, "RTS High Threshold : %2u data\n",
b78cd169 2878 atmel_port->rts_high);
b5199d46 2879 dev_dbg(&pdev->dev, "RTS Low Threshold : %2u data\n",
b78cd169 2880 atmel_port->rts_low);
b5199d46
CP		 2881}
2882
9671f099 2883static int atmel_serial_probe(struct platform_device *pdev)
1e6c9c28 2884{
b78cd169 2885 struct atmel_uart_port *atmel_port;
c24d2531 2886 struct device_node *np = pdev->dev.parent->of_node;
1ecc26bd 2887 void *data;
8d41ab87 2888 int ret;
bd737f87 2889 bool rs485_enabled;
1e6c9c28 2890
9d09daf8 2891 BUILD_BUG_ON(ATMEL_SERIAL_RINGSIZE & (ATMEL_SERIAL_RINGSIZE - 1));
1ecc26bd 2892
c24d2531
RP		 2893 /*
2894 * In device tree there is no node with "atmel,at91rm9200-usart-serial"
2895 * as compatible string. This driver is probed by at91-usart mfd driver
2896 * which is just a wrapper over the atmel_serial driver and
2897 * spi-at91-usart driver. All attributes needed by this driver are
2898 * found in of_node of parent.
2899 */
2900 pdev->dev.of_node = np;
2901
92c8f7c0 2902 ret = of_alias_get_id(np, "serial");
4cbf9f48 2903 if (ret < 0)
5fbe46b6 2904 /* port id not found in platform data nor device-tree aliases:
4cbf9f48 2905 * auto-enumerate it */
503bded9 2906 ret = find_first_zero_bit(atmel_ports_in_use, ATMEL_MAX_UART);
4cbf9f48 2907
503bded9 2908 if (ret >= ATMEL_MAX_UART) {
4cbf9f48
NF		 2909 ret = -ENODEV;
2910 goto err;
2911 }
2912
503bded9 2913 if (test_and_set_bit(ret, atmel_ports_in_use)) {
4cbf9f48
NF		 2914 /* port already in use */
2915 ret = -EBUSY;
2916 goto err;
2917 }
2918
b78cd169
JA		 2919 atmel_port = &atmel_ports[ret];
2920 atmel_port->backup_imr = 0;
2921 atmel_port->uart.line = ret;
078abd98 2922 atmel_port->uart.has_sysrq = IS_ENABLED(CONFIG_SERIAL_ATMEL_CONSOLE);
b78cd169 2923 atmel_serial_probe_fifos(atmel_port, pdev);
e0b0baad 2924
98f2082c 2925 atomic_set(&atmel_port->tasklet_shutdown, 0);
b78cd169 2926 spin_lock_init(&atmel_port->lock_suspended);
2c7af5ba 2927
84b476b1
CB		 2928 atmel_port->clk = devm_clk_get(&pdev->dev, "usart");
2929 if (IS_ERR(atmel_port->clk)) {
2930 ret = PTR_ERR(atmel_port->clk);
2931 goto err;
2932 }
2933 ret = clk_prepare_enable(atmel_port->clk);
2934 if (ret)
2935 goto err;
2936
5e3ce1f2
SM		 2937 atmel_port->gclk = devm_clk_get_optional(&pdev->dev, "gclk");
2938 if (IS_ERR(atmel_port->gclk)) {
2939 ret = PTR_ERR(atmel_port->gclk);
2940 goto err_clk_disable_unprepare;
2941 }
2942
b78cd169 2943 ret = atmel_init_port(atmel_port, pdev);
91f8c2d8 2944 if (ret)
84b476b1 2945 goto err_clk_disable_unprepare;
1e6c9c28 2946
b78cd169
JA		 2947 atmel_port->gpios = mctrl_gpio_init(&atmel_port->uart, 0);
2948 if (IS_ERR(atmel_port->gpios)) {
2949 ret = PTR_ERR(atmel_port->gpios);
84b476b1 2950 goto err_clk_disable_unprepare;
18dfef9c
UKK		 2951 }
2952
b78cd169 2953 if (!atmel_use_pdc_rx(&atmel_port->uart)) {
a6670615 2954 ret = -ENOMEM;
6da2ec56
KC		 2955 data = kmalloc_array(ATMEL_SERIAL_RINGSIZE,
2956 sizeof(struct atmel_uart_char),
2957 GFP_KERNEL);
a6670615 2958 if (!data)
84b476b1 2959 goto err_clk_disable_unprepare;
b78cd169 2960 atmel_port->rx_ring.buf = data;
a6670615 2961 }
1ecc26bd 2962
b78cd169 2963 rs485_enabled = atmel_port->uart.rs485.flags & SER_RS485_ENABLED;
bd737f87 2964
b78cd169 2965 ret = uart_add_one_port(&atmel_uart, &atmel_port->uart);
dfa7f343
HS		 2966 if (ret)
2967 goto err_add_port;
2968
2969 device_init_wakeup(&pdev->dev, 1);
b78cd169 2970 platform_set_drvdata(pdev, atmel_port);
dfa7f343 2971
bd737f87 2972 if (rs485_enabled) {
b78cd169 2973 atmel_uart_writel(&atmel_port->uart, ATMEL_US_MR,
4e7decda 2974 ATMEL_US_USMODE_NORMAL);
b78cd169
JA		 2975 atmel_uart_writel(&atmel_port->uart, ATMEL_US_CR,
2976 ATMEL_US_RTSEN);
5dfbd1d7
CS		 2977 }
2978
055560b0
ES		 2979 /*
2980 * Get port name of usart or uart
2981 */
b78cd169 2982 atmel_get_ip_name(&atmel_port->uart);
055560b0 2983
d4f64187
CP		 2984 /*
2985 * The peripheral clock can now safely be disabled till the port
2986 * is used
2987 */
b78cd169 2988 clk_disable_unprepare(atmel_port->clk);
d4f64187 2989
dfa7f343
HS		 2990 return 0;
2991
2992err_add_port:
b78cd169
JA		 2993 kfree(atmel_port->rx_ring.buf);
2994 atmel_port->rx_ring.buf = NULL;
84b476b1
CB		 2995err_clk_disable_unprepare:
2996 clk_disable_unprepare(atmel_port->clk);
b78cd169 2997 clear_bit(atmel_port->uart.line, atmel_ports_in_use);
4cbf9f48 2998err:
afefc415
AV		 2999 return ret;
3000}
3001
f4a8ab04
RI		 3002/*
3003 * Even if the driver is not modular, it makes sense to be able to
3004 * unbind a device: there can be many bound devices, and there are
3005 * situations where dynamic binding and unbinding can be useful.
3006 *
3007 * For example, a connected device can require a specific firmware update
3008 * protocol that needs bitbanging on IO lines, but use the regular serial
3009 * port in the normal case.
3010 */
3011static int atmel_serial_remove(struct platform_device *pdev)
3012{
3013 struct uart_port *port = platform_get_drvdata(pdev);
3014 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
3015 int ret = 0;
3016
00e8e658
NF		 3017 tasklet_kill(&atmel_port->tasklet_rx);
3018 tasklet_kill(&atmel_port->tasklet_tx);
f4a8ab04
RI		 3019
3020 device_init_wakeup(&pdev->dev, 0);
3021
3022 ret = uart_remove_one_port(&atmel_uart, port);
3023
3024 kfree(atmel_port->rx_ring.buf);
3025
3026 /* "port" is allocated statically, so we shouldn't free it */
3027
3028 clear_bit(port->line, atmel_ports_in_use);
3029
c24d2531 3030 pdev->dev.of_node = NULL;
f4a8ab04
RI		 3031
3032 return ret;
3033}
3034
b50058b8
CB		 3035static SIMPLE_DEV_PM_OPS(atmel_serial_pm_ops, atmel_serial_suspend,
3036 atmel_serial_resume);
3037
7192f92c
HS		 3038static struct platform_driver atmel_serial_driver = {
3039 .probe = atmel_serial_probe,
f4a8ab04 3040 .remove = atmel_serial_remove,
afefc415 3041 .driver = {
c24d2531 3042 .name = "atmel_usart_serial",
c39dfebc 3043 .of_match_table = of_match_ptr(atmel_serial_dt_ids),
b50058b8 3044 .pm = pm_ptr(&atmel_serial_pm_ops),
afefc415
AV		 3045 },
3046};
3047
7192f92c 3048static int __init atmel_serial_init(void)
afefc415
AV		 3049{
3050 int ret;
3051
7192f92c 3052 ret = uart_register_driver(&atmel_uart);
afefc415
AV		 3053 if (ret)
3054 return ret;
3055
7192f92c 3056 ret = platform_driver_register(&atmel_serial_driver);
afefc415 3057 if (ret)
7192f92c 3058 uart_unregister_driver(&atmel_uart);
afefc415
AV		 3059
3060 return ret;
3061}
c39dfebc 3062device_initcall(atmel_serial_init);
Linux 6.x block layer and io_uring tree(s)