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serial: 8250_exar: Fix spelling of "driver"
[linux-2.6-block.git] / drivers / tty / serial / atmel_serial.c
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1e6c9c28 1/*
7192f92c 2 * Driver for Atmel AT91 / AT32 Serial ports
1e6c9c28
AV		 3 * Copyright (C) 2003 Rick Bronson
4 *
5 * Based on drivers/char/serial_sa1100.c, by Deep Blue Solutions Ltd.
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
7 *
a6670615
CC		 8 * DMA support added by Chip Coldwell.
9 *
1e6c9c28
AV		 10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 *
24 */
1e6c9c28
AV		 25#include <linux/tty.h>
26#include <linux/ioport.h>
27#include <linux/slab.h>
28#include <linux/init.h>
29#include <linux/serial.h>
afefc415 30#include <linux/clk.h>
1e6c9c28
AV		 31#include <linux/console.h>
32#include <linux/sysrq.h>
33#include <linux/tty_flip.h>
afefc415 34#include <linux/platform_device.h>
5fbe46b6
NF		 35#include <linux/of.h>
36#include <linux/of_device.h>
354e57f3 37#include <linux/of_gpio.h>
a6670615 38#include <linux/dma-mapping.h>
6b997bab 39#include <linux/dmaengine.h>
93a3ddc2 40#include <linux/atmel_pdc.h>
fa3218d8 41#include <linux/atmel_serial.h>
e8faff73 42#include <linux/uaccess.h>
bcd2360c 43#include <linux/platform_data/atmel.h>
2e68c22f 44#include <linux/timer.h>
354e57f3 45#include <linux/gpio.h>
e0b0baad
RG		 46#include <linux/gpio/consumer.h>
47#include <linux/err.h>
ab5e4e41 48#include <linux/irq.h>
2c7af5ba 49#include <linux/suspend.h>
1e6c9c28
AV		 50
51#include <asm/io.h>
f7512e7c 52#include <asm/ioctls.h>
1e6c9c28 53
a6670615
CC		 54#define PDC_BUFFER_SIZE 512
55/* Revisit: We should calculate this based on the actual port settings */
56#define PDC_RX_TIMEOUT (3 * 10) /* 3 bytes */
57
b5199d46
CP		 58/* The minium number of data FIFOs should be able to contain */
59#define ATMEL_MIN_FIFO_SIZE 8
60/*
61 * These two offsets are substracted from the RX FIFO size to define the RTS
62 * high and low thresholds
63 */
64#define ATMEL_RTS_HIGH_OFFSET 16
65#define ATMEL_RTS_LOW_OFFSET 20
66
749c4e60 67#if defined(CONFIG_SERIAL_ATMEL_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
1e6c9c28
AV		 68#define SUPPORT_SYSRQ
69#endif
70
71#include <linux/serial_core.h>
72
e0b0baad
RG		 73#include "serial_mctrl_gpio.h"
74
e8faff73
CS		 75static void atmel_start_rx(struct uart_port *port);
76static void atmel_stop_rx(struct uart_port *port);
77
749c4e60 78#ifdef CONFIG_SERIAL_ATMEL_TTYAT
1e6c9c28
AV		 79
80/* Use device name ttyAT, major 204 and minor 154-169. This is necessary if we
81 * should coexist with the 8250 driver, such as if we have an external 16C550
82 * UART. */
7192f92c 83#define SERIAL_ATMEL_MAJOR 204
1e6c9c28 84#define MINOR_START 154
7192f92c 85#define ATMEL_DEVICENAME "ttyAT"
1e6c9c28
AV		 86
87#else
88
89/* Use device name ttyS, major 4, minor 64-68. This is the usual serial port
90 * name, but it is legally reserved for the 8250 driver. */
7192f92c 91#define SERIAL_ATMEL_MAJOR TTY_MAJOR
1e6c9c28 92#define MINOR_START 64
7192f92c 93#define ATMEL_DEVICENAME "ttyS"
1e6c9c28
AV		 94
95#endif
96
7192f92c 97#define ATMEL_ISR_PASS_LIMIT 256
1e6c9c28 98
a6670615
CC		 99struct atmel_dma_buffer {
100 unsigned char *buf;
101 dma_addr_t dma_addr;
102 unsigned int dma_size;
103 unsigned int ofs;
104};
105
1ecc26bd
RB		 106struct atmel_uart_char {
107 u16 status;
108 u16 ch;
109};
110
637ba54f
LD		 111/*
112 * Be careful, the real size of the ring buffer is
113 * sizeof(atmel_uart_char) * ATMEL_SERIAL_RINGSIZE. It means that ring buffer
114 * can contain up to 1024 characters in PIO mode and up to 4096 characters in
115 * DMA mode.
116 */
1ecc26bd
RB		 117#define ATMEL_SERIAL_RINGSIZE 1024
118
9af92fbf
AB		 119/*
120 * at91: 6 USARTs and one DBGU port (SAM9260)
121 * avr32: 4
432f9748 122 * samx7: 3 USARTs and 5 UARTs
9af92fbf 123 */
432f9748 124#define ATMEL_MAX_UART 8
9af92fbf 125
afefc415
AV		 126/*
127 * We wrap our port structure around the generic uart_port.
128 */
7192f92c 129struct atmel_uart_port {
afefc415
AV		 130 struct uart_port uart; /* uart */
131 struct clk *clk; /* uart clock */
f05596db
AS		 132 int may_wakeup; /* cached value of device_may_wakeup for times we need to disable it */
133 u32 backup_imr; /* IMR saved during suspend */
9e6077bd 134 int break_active; /* break being received */
1ecc26bd 135
34df42f5 136 bool use_dma_rx; /* enable DMA receiver */
64e22ebe 137 bool use_pdc_rx; /* enable PDC receiver */
a6670615
CC		 138 short pdc_rx_idx; /* current PDC RX buffer */
139 struct atmel_dma_buffer pdc_rx[2]; /* PDC receier */
140
08f738be 141 bool use_dma_tx; /* enable DMA transmitter */
64e22ebe 142 bool use_pdc_tx; /* enable PDC transmitter */
a6670615
CC		 143 struct atmel_dma_buffer pdc_tx; /* PDC transmitter */
144
08f738be 145 spinlock_t lock_tx; /* port lock */
34df42f5 146 spinlock_t lock_rx; /* port lock */
08f738be 147 struct dma_chan *chan_tx;
34df42f5 148 struct dma_chan *chan_rx;
08f738be 149 struct dma_async_tx_descriptor *desc_tx;
34df42f5 150 struct dma_async_tx_descriptor *desc_rx;
08f738be 151 dma_cookie_t cookie_tx;
34df42f5 152 dma_cookie_t cookie_rx;
08f738be 153 struct scatterlist sg_tx;
34df42f5 154 struct scatterlist sg_rx;
00e8e658
NF		 155 struct tasklet_struct tasklet_rx;
156 struct tasklet_struct tasklet_tx;
98f2082c 157 atomic_t tasklet_shutdown;
1ecc26bd 158 unsigned int irq_status_prev;
5f258b3e 159 unsigned int tx_len;
1ecc26bd
RB		 160
161 struct circ_buf rx_ring;
e8faff73 162
e0b0baad 163 struct mctrl_gpios *gpios;
e8faff73 164 unsigned int tx_done_mask;
b5199d46
CP		 165 u32 fifo_size;
166 u32 rts_high;
167 u32 rts_low;
ab5e4e41 168 bool ms_irq_enabled;
2958ccee 169 u32 rtor; /* address of receiver timeout register if it exists */
5bf5635a 170 bool has_frac_baudrate;
4b769371
NF		 171 bool has_hw_timer;
172 struct timer_list uart_timer;
2c7af5ba
BB		 173
174 bool suspended;
175 unsigned int pending;
176 unsigned int pending_status;
177 spinlock_t lock_suspended;
178
488ae82d 179#ifdef CONFIG_PM
6a5f0e2f
AB		 180 struct {
181 u32 cr;
182 u32 mr;
183 u32 imr;
184 u32 brgr;
185 u32 rtor;
186 u32 ttgr;
187 u32 fmr;
188 u32 fimr;
189 } cache;
488ae82d 190#endif
6a5f0e2f 191
a930e528
ES		 192 int (*prepare_rx)(struct uart_port *port);
193 int (*prepare_tx)(struct uart_port *port);
194 void (*schedule_rx)(struct uart_port *port);
195 void (*schedule_tx)(struct uart_port *port);
196 void (*release_rx)(struct uart_port *port);
197 void (*release_tx)(struct uart_port *port);
afefc415
AV		 198};
199
7192f92c 200static struct atmel_uart_port atmel_ports[ATMEL_MAX_UART];
503bded9 201static DECLARE_BITMAP(atmel_ports_in_use, ATMEL_MAX_UART);
afefc415 202
1e6c9c28 203#ifdef SUPPORT_SYSRQ
7192f92c 204static struct console atmel_console;
1e6c9c28
AV		 205#endif
206
5fbe46b6
NF		 207#if defined(CONFIG_OF)
208static const struct of_device_id atmel_serial_dt_ids[] = {
209 { .compatible = "atmel,at91rm9200-usart" },
210 { .compatible = "atmel,at91sam9260-usart" },
211 { /* sentinel */ }
212};
5fbe46b6
NF		 213#endif
214
c811ab8c
HS		 215static inline struct atmel_uart_port *
216to_atmel_uart_port(struct uart_port *uart)
217{
218 return container_of(uart, struct atmel_uart_port, uart);
219}
220
4e7decda
CP		 221static inline u32 atmel_uart_readl(struct uart_port *port, u32 reg)
222{
223 return __raw_readl(port->membase + reg);
224}
225
226static inline void atmel_uart_writel(struct uart_port *port, u32 reg, u32 value)
227{
228 __raw_writel(value, port->membase + reg);
229}
230
a6499435
CP		 231#ifdef CONFIG_AVR32
232
233/* AVR32 cannot handle 8 or 16bit I/O accesses but only 32bit I/O accesses */
234static inline u8 atmel_uart_read_char(struct uart_port *port)
235{
236 return __raw_readl(port->membase + ATMEL_US_RHR);
237}
238
239static inline void atmel_uart_write_char(struct uart_port *port, u8 value)
b5199d46 240{
a6499435 241 __raw_writel(value, port->membase + ATMEL_US_THR);
b5199d46
CP		 242}
243
a6499435
CP		 244#else
245
246static inline u8 atmel_uart_read_char(struct uart_port *port)
b5199d46 247{
a6499435 248 return __raw_readb(port->membase + ATMEL_US_RHR);
b5199d46
CP		 249}
250
a6499435
CP		 251static inline void atmel_uart_write_char(struct uart_port *port, u8 value)
252{
253 __raw_writeb(value, port->membase + ATMEL_US_THR);
254}
255
256#endif
257
a6670615 258#ifdef CONFIG_SERIAL_ATMEL_PDC
64e22ebe 259static bool atmel_use_pdc_rx(struct uart_port *port)
a6670615 260{
c811ab8c 261 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
a6670615 262
64e22ebe 263 return atmel_port->use_pdc_rx;
a6670615
CC		 264}
265
64e22ebe 266static bool atmel_use_pdc_tx(struct uart_port *port)
a6670615 267{
c811ab8c 268 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
a6670615 269
64e22ebe 270 return atmel_port->use_pdc_tx;
a6670615
CC		 271}
272#else
64e22ebe 273static bool atmel_use_pdc_rx(struct uart_port *port)
a6670615
CC		 274{
275 return false;
276}
277
64e22ebe 278static bool atmel_use_pdc_tx(struct uart_port *port)
a6670615
CC		 279{
280 return false;
281}
282#endif
283
08f738be
ES		 284static bool atmel_use_dma_tx(struct uart_port *port)
285{
286 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
287
288 return atmel_port->use_dma_tx;
289}
290
34df42f5
ES		 291static bool atmel_use_dma_rx(struct uart_port *port)
292{
293 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
294
295 return atmel_port->use_dma_rx;
296}
297
5be605ac
AB		 298static bool atmel_use_fifo(struct uart_port *port)
299{
300 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
301
302 return atmel_port->fifo_size;
303}
304
98f2082c
NF		 305static void atmel_tasklet_schedule(struct atmel_uart_port *atmel_port,
306 struct tasklet_struct *t)
307{
308 if (!atomic_read(&atmel_port->tasklet_shutdown))
309 tasklet_schedule(t);
310}
311
e0b0baad
RG		 312static unsigned int atmel_get_lines_status(struct uart_port *port)
313{
314 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
315 unsigned int status, ret = 0;
316
4e7decda 317 status = atmel_uart_readl(port, ATMEL_US_CSR);
e0b0baad
RG		 318
319 mctrl_gpio_get(atmel_port->gpios, &ret);
320
321 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios,
322 UART_GPIO_CTS))) {
323 if (ret & TIOCM_CTS)
324 status &= ~ATMEL_US_CTS;
325 else
326 status |= ATMEL_US_CTS;
327 }
328
329 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios,
330 UART_GPIO_DSR))) {
331 if (ret & TIOCM_DSR)
332 status &= ~ATMEL_US_DSR;
333 else
334 status |= ATMEL_US_DSR;
335 }
336
337 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios,
338 UART_GPIO_RI))) {
339 if (ret & TIOCM_RI)
340 status &= ~ATMEL_US_RI;
341 else
342 status |= ATMEL_US_RI;
343 }
344
345 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios,
346 UART_GPIO_DCD))) {
347 if (ret & TIOCM_CD)
348 status &= ~ATMEL_US_DCD;
349 else
350 status |= ATMEL_US_DCD;
351 }
352
353 return status;
354}
355
e8faff73 356/* Enable or disable the rs485 support */
13bd3e6f
RRD		 357static int atmel_config_rs485(struct uart_port *port,
358 struct serial_rs485 *rs485conf)
e8faff73
CS		 359{
360 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
361 unsigned int mode;
e8faff73
CS		 362
363 /* Disable interrupts */
4e7decda 364 atmel_uart_writel(port, ATMEL_US_IDR, atmel_port->tx_done_mask);
e8faff73 365
4e7decda 366 mode = atmel_uart_readl(port, ATMEL_US_MR);
e8faff73
CS		 367
368 /* Resetting serial mode to RS232 (0x0) */
369 mode &= ~ATMEL_US_USMODE;
370
13bd3e6f 371 port->rs485 = *rs485conf;
e8faff73
CS		 372
373 if (rs485conf->flags & SER_RS485_ENABLED) {
374 dev_dbg(port->dev, "Setting UART to RS485\n");
375 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY;
4e7decda
CP		 376 atmel_uart_writel(port, ATMEL_US_TTGR,
377 rs485conf->delay_rts_after_send);
e8faff73
CS		 378 mode |= ATMEL_US_USMODE_RS485;
379 } else {
380 dev_dbg(port->dev, "Setting UART to RS232\n");
64e22ebe 381 if (atmel_use_pdc_tx(port))
e8faff73
CS		 382 atmel_port->tx_done_mask = ATMEL_US_ENDTX |
383 ATMEL_US_TXBUFE;
384 else
385 atmel_port->tx_done_mask = ATMEL_US_TXRDY;
386 }
4e7decda 387 atmel_uart_writel(port, ATMEL_US_MR, mode);
e8faff73
CS		 388
389 /* Enable interrupts */
4e7decda 390 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->tx_done_mask);
e8faff73 391
13bd3e6f 392 return 0;
e8faff73
CS		 393}
394
1e6c9c28
AV		 395/*
396 * Return TIOCSER_TEMT when transmitter FIFO and Shift register is empty.
397 */
7192f92c 398static u_int atmel_tx_empty(struct uart_port *port)
1e6c9c28 399{
4e7decda
CP		 400 return (atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXEMPTY) ?
401 TIOCSER_TEMT :
402 0;
1e6c9c28
AV		 403}
404
405/*
406 * Set state of the modem control output lines
407 */
7192f92c 408static void atmel_set_mctrl(struct uart_port *port, u_int mctrl)
1e6c9c28
AV		 409{
410 unsigned int control = 0;
4e7decda 411 unsigned int mode = atmel_uart_readl(port, ATMEL_US_MR);
1cf6e8fc 412 unsigned int rts_paused, rts_ready;
e8faff73 413 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1e6c9c28 414
1cf6e8fc
CP		 415 /* override mode to RS485 if needed, otherwise keep the current mode */
416 if (port->rs485.flags & SER_RS485_ENABLED) {
4e7decda
CP		 417 atmel_uart_writel(port, ATMEL_US_TTGR,
418 port->rs485.delay_rts_after_send);
1cf6e8fc
CP		 419 mode &= ~ATMEL_US_USMODE;
420 mode |= ATMEL_US_USMODE_RS485;
421 }
422
423 /* set the RTS line state according to the mode */
424 if ((mode & ATMEL_US_USMODE) == ATMEL_US_USMODE_HWHS) {
425 /* force RTS line to high level */
426 rts_paused = ATMEL_US_RTSEN;
427
428 /* give the control of the RTS line back to the hardware */
429 rts_ready = ATMEL_US_RTSDIS;
430 } else {
431 /* force RTS line to high level */
432 rts_paused = ATMEL_US_RTSDIS;
433
434 /* force RTS line to low level */
435 rts_ready = ATMEL_US_RTSEN;
436 }
437
1e6c9c28 438 if (mctrl & TIOCM_RTS)
1cf6e8fc 439 control |= rts_ready;
1e6c9c28 440 else
1cf6e8fc 441 control |= rts_paused;
1e6c9c28
AV		 442
443 if (mctrl & TIOCM_DTR)
7192f92c 444 control |= ATMEL_US_DTREN;
1e6c9c28 445 else
7192f92c 446 control |= ATMEL_US_DTRDIS;
1e6c9c28 447
4e7decda 448 atmel_uart_writel(port, ATMEL_US_CR, control);
afefc415 449
e0b0baad
RG		 450 mctrl_gpio_set(atmel_port->gpios, mctrl);
451
afefc415 452 /* Local loopback mode? */
1cf6e8fc 453 mode &= ~ATMEL_US_CHMODE;
afefc415 454 if (mctrl & TIOCM_LOOP)
7192f92c 455 mode |= ATMEL_US_CHMODE_LOC_LOOP;
afefc415 456 else
7192f92c 457 mode |= ATMEL_US_CHMODE_NORMAL;
e8faff73 458
4e7decda 459 atmel_uart_writel(port, ATMEL_US_MR, mode);
1e6c9c28
AV		 460}
461
462/*
463 * Get state of the modem control input lines
464 */
7192f92c 465static u_int atmel_get_mctrl(struct uart_port *port)
1e6c9c28 466{
e0b0baad
RG		 467 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
468 unsigned int ret = 0, status;
1e6c9c28 469
4e7decda 470 status = atmel_uart_readl(port, ATMEL_US_CSR);
1e6c9c28
AV		 471
472 /*
473 * The control signals are active low.
474 */
7192f92c 475 if (!(status & ATMEL_US_DCD))
1e6c9c28 476 ret |= TIOCM_CD;
7192f92c 477 if (!(status & ATMEL_US_CTS))
1e6c9c28 478 ret |= TIOCM_CTS;
7192f92c 479 if (!(status & ATMEL_US_DSR))
1e6c9c28 480 ret |= TIOCM_DSR;
7192f92c 481 if (!(status & ATMEL_US_RI))
1e6c9c28
AV		 482 ret |= TIOCM_RI;
483
e0b0baad 484 return mctrl_gpio_get(atmel_port->gpios, &ret);
1e6c9c28
AV		 485}
486
487/*
488 * Stop transmitting.
489 */
7192f92c 490static void atmel_stop_tx(struct uart_port *port)
1e6c9c28 491{
e8faff73
CS		 492 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
493
64e22ebe 494 if (atmel_use_pdc_tx(port)) {
a6670615 495 /* disable PDC transmit */
4e7decda 496 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS);
e8faff73 497 }
89d82324
RG		 498
499 /*
500 * Disable the transmitter.
501 * This is mandatory when DMA is used, otherwise the DMA buffer
502 * is fully transmitted.
503 */
504 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXDIS);
505
e8faff73 506 /* Disable interrupts */
4e7decda 507 atmel_uart_writel(port, ATMEL_US_IDR, atmel_port->tx_done_mask);
e8faff73 508
13bd3e6f
RRD		 509 if ((port->rs485.flags & SER_RS485_ENABLED) &&
510 !(port->rs485.flags & SER_RS485_RX_DURING_TX))
e8faff73 511 atmel_start_rx(port);
1e6c9c28
AV		 512}
513
514/*
515 * Start transmitting.
516 */
7192f92c 517static void atmel_start_tx(struct uart_port *port)
1e6c9c28 518{
e8faff73
CS		 519 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
520
0058f087
AB		 521 if (atmel_use_pdc_tx(port) && (atmel_uart_readl(port, ATMEL_PDC_PTSR)
522 & ATMEL_PDC_TXTEN))
523 /* The transmitter is already running. Yes, we
524 really need this.*/
525 return;
a6670615 526
0058f087 527 if (atmel_use_pdc_tx(port) || atmel_use_dma_tx(port))
13bd3e6f
RRD		 528 if ((port->rs485.flags & SER_RS485_ENABLED) &&
529 !(port->rs485.flags & SER_RS485_RX_DURING_TX))
e8faff73
CS		 530 atmel_stop_rx(port);
531
0058f087 532 if (atmel_use_pdc_tx(port))
a6670615 533 /* re-enable PDC transmit */
4e7decda 534 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
0058f087 535
e8faff73 536 /* Enable interrupts */
4e7decda 537 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->tx_done_mask);
89d82324
RG		 538
539 /* re-enable the transmitter */
540 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN);
e8faff73
CS		 541}
542
543/*
544 * start receiving - port is in process of being opened.
545 */
546static void atmel_start_rx(struct uart_port *port)
547{
4e7decda
CP		 548 /* reset status and receiver */
549 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
e8faff73 550
4e7decda 551 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RXEN);
57c36868 552
64e22ebe 553 if (atmel_use_pdc_rx(port)) {
e8faff73 554 /* enable PDC controller */
4e7decda
CP		 555 atmel_uart_writel(port, ATMEL_US_IER,
556 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT |
557 port->read_status_mask);
558 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN);
e8faff73 559 } else {
4e7decda 560 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_RXRDY);
e8faff73 561 }
1e6c9c28
AV		 562}
563
564/*
565 * Stop receiving - port is in process of being closed.
566 */
7192f92c 567static void atmel_stop_rx(struct uart_port *port)
1e6c9c28 568{
4e7decda 569 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RXDIS);
57c36868 570
64e22ebe 571 if (atmel_use_pdc_rx(port)) {
a6670615 572 /* disable PDC receive */
4e7decda
CP		 573 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS);
574 atmel_uart_writel(port, ATMEL_US_IDR,
575 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT |
576 port->read_status_mask);
e8faff73 577 } else {
4e7decda 578 atmel_uart_writel(port, ATMEL_US_IDR, ATMEL_US_RXRDY);
e8faff73 579 }
1e6c9c28
AV		 580}
581
582/*
583 * Enable modem status interrupts
584 */
7192f92c 585static void atmel_enable_ms(struct uart_port *port)
1e6c9c28 586{
ab5e4e41
RG		 587 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
588 uint32_t ier = 0;
589
590 /*
591 * Interrupt should not be enabled twice
592 */
593 if (atmel_port->ms_irq_enabled)
594 return;
595
596 atmel_port->ms_irq_enabled = true;
597
18dfef9c 598 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_CTS))
ab5e4e41
RG		 599 ier |= ATMEL_US_CTSIC;
600
18dfef9c 601 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DSR))
ab5e4e41
RG		 602 ier |= ATMEL_US_DSRIC;
603
18dfef9c 604 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_RI))
ab5e4e41
RG		 605 ier |= ATMEL_US_RIIC;
606
18dfef9c 607 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DCD))
ab5e4e41
RG		 608 ier |= ATMEL_US_DCDIC;
609
4e7decda 610 atmel_uart_writel(port, ATMEL_US_IER, ier);
18dfef9c
UKK		 611
612 mctrl_gpio_enable_ms(atmel_port->gpios);
1e6c9c28
AV		 613}
614
35b675b9
RG		 615/*
616 * Disable modem status interrupts
617 */
618static void atmel_disable_ms(struct uart_port *port)
619{
620 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
621 uint32_t idr = 0;
622
623 /*
624 * Interrupt should not be disabled twice
625 */
626 if (!atmel_port->ms_irq_enabled)
627 return;
628
629 atmel_port->ms_irq_enabled = false;
630
18dfef9c
UKK		 631 mctrl_gpio_disable_ms(atmel_port->gpios);
632
633 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_CTS))
35b675b9
RG		 634 idr |= ATMEL_US_CTSIC;
635
18dfef9c 636 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DSR))
35b675b9
RG		 637 idr |= ATMEL_US_DSRIC;
638
18dfef9c 639 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_RI))
35b675b9
RG		 640 idr |= ATMEL_US_RIIC;
641
18dfef9c 642 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DCD))
35b675b9
RG		 643 idr |= ATMEL_US_DCDIC;
644
4e7decda 645 atmel_uart_writel(port, ATMEL_US_IDR, idr);
35b675b9
RG		 646}
647
1e6c9c28
AV		 648/*
649 * Control the transmission of a break signal
650 */
7192f92c 651static void atmel_break_ctl(struct uart_port *port, int break_state)
1e6c9c28
AV		 652{
653 if (break_state != 0)
4e7decda
CP		 654 /* start break */
655 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTBRK);
1e6c9c28 656 else
4e7decda
CP		 657 /* stop break */
658 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STPBRK);
1e6c9c28
AV		 659}
660
1ecc26bd
RB		 661/*
662 * Stores the incoming character in the ring buffer
663 */
664static void
665atmel_buffer_rx_char(struct uart_port *port, unsigned int status,
666 unsigned int ch)
667{
c811ab8c 668 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1ecc26bd
RB		 669 struct circ_buf *ring = &atmel_port->rx_ring;
670 struct atmel_uart_char *c;
671
672 if (!CIRC_SPACE(ring->head, ring->tail, ATMEL_SERIAL_RINGSIZE))
673 /* Buffer overflow, ignore char */
674 return;
675
676 c = &((struct atmel_uart_char *)ring->buf)[ring->head];
677 c->status = status;
678 c->ch = ch;
679
680 /* Make sure the character is stored before we update head. */
681 smp_wmb();
682
683 ring->head = (ring->head + 1) & (ATMEL_SERIAL_RINGSIZE - 1);
684}
685
a6670615
CC		 686/*
687 * Deal with parity, framing and overrun errors.
688 */
689static void atmel_pdc_rxerr(struct uart_port *port, unsigned int status)
690{
691 /* clear error */
4e7decda 692 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
a6670615
CC		 693
694 if (status & ATMEL_US_RXBRK) {
695 /* ignore side-effect */
696 status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME);
697 port->icount.brk++;
698 }
699 if (status & ATMEL_US_PARE)
700 port->icount.parity++;
701 if (status & ATMEL_US_FRAME)
702 port->icount.frame++;
703 if (status & ATMEL_US_OVRE)
704 port->icount.overrun++;
705}
706
1e6c9c28
AV		 707/*
708 * Characters received (called from interrupt handler)
709 */
7d12e780 710static void atmel_rx_chars(struct uart_port *port)
1e6c9c28 711{
c811ab8c 712 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1ecc26bd 713 unsigned int status, ch;
1e6c9c28 714
4e7decda 715 status = atmel_uart_readl(port, ATMEL_US_CSR);
7192f92c 716 while (status & ATMEL_US_RXRDY) {
a6499435 717 ch = atmel_uart_read_char(port);
1e6c9c28 718
1e6c9c28
AV		 719 /*
720 * note that the error handling code is
721 * out of the main execution path
722 */
9e6077bd
HS		 723 if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME
724 | ATMEL_US_OVRE | ATMEL_US_RXBRK)
725 || atmel_port->break_active)) {
1ecc26bd 726
b843aa21 727 /* clear error */
4e7decda 728 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
1ecc26bd 729
9e6077bd
HS		 730 if (status & ATMEL_US_RXBRK
731 && !atmel_port->break_active) {
9e6077bd 732 atmel_port->break_active = 1;
4e7decda
CP		 733 atmel_uart_writel(port, ATMEL_US_IER,
734 ATMEL_US_RXBRK);
9e6077bd
HS		 735 } else {
736 /*
737 * This is either the end-of-break
738 * condition or we've received at
739 * least one character without RXBRK
740 * being set. In both cases, the next
741 * RXBRK will indicate start-of-break.
742 */
4e7decda
CP		 743 atmel_uart_writel(port, ATMEL_US_IDR,
744 ATMEL_US_RXBRK);
9e6077bd
HS		 745 status &= ~ATMEL_US_RXBRK;
746 atmel_port->break_active = 0;
afefc415 747 }
1e6c9c28
AV		 748 }
749
1ecc26bd 750 atmel_buffer_rx_char(port, status, ch);
4e7decda 751 status = atmel_uart_readl(port, ATMEL_US_CSR);
1e6c9c28
AV		 752 }
753
98f2082c 754 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_rx);
1e6c9c28
AV		 755}
756
757/*
1ecc26bd
RB		 758 * Transmit characters (called from tasklet with TXRDY interrupt
759 * disabled)
1e6c9c28 760 */
7192f92c 761static void atmel_tx_chars(struct uart_port *port)
1e6c9c28 762{
ebd2c8f6 763 struct circ_buf *xmit = &port->state->xmit;
e8faff73 764 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1e6c9c28 765
4e7decda
CP		 766 if (port->x_char &&
767 (atmel_uart_readl(port, ATMEL_US_CSR) & atmel_port->tx_done_mask)) {
a6499435 768 atmel_uart_write_char(port, port->x_char);
1e6c9c28
AV		 769 port->icount.tx++;
770 port->x_char = 0;
1e6c9c28 771 }
1ecc26bd 772 if (uart_circ_empty(xmit) || uart_tx_stopped(port))
1e6c9c28 773 return;
1e6c9c28 774
4e7decda
CP		 775 while (atmel_uart_readl(port, ATMEL_US_CSR) &
776 atmel_port->tx_done_mask) {
a6499435 777 atmel_uart_write_char(port, xmit->buf[xmit->tail]);
1e6c9c28
AV		 778 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
779 port->icount.tx++;
780 if (uart_circ_empty(xmit))
781 break;
782 }
783
784 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
785 uart_write_wakeup(port);
786
1ecc26bd 787 if (!uart_circ_empty(xmit))
e8faff73 788 /* Enable interrupts */
4e7decda
CP		 789 atmel_uart_writel(port, ATMEL_US_IER,
790 atmel_port->tx_done_mask);
1e6c9c28
AV		 791}
792
08f738be
ES		 793static void atmel_complete_tx_dma(void *arg)
794{
795 struct atmel_uart_port *atmel_port = arg;
796 struct uart_port *port = &atmel_port->uart;
797 struct circ_buf *xmit = &port->state->xmit;
798 struct dma_chan *chan = atmel_port->chan_tx;
799 unsigned long flags;
800
801 spin_lock_irqsave(&port->lock, flags);
802
803 if (chan)
804 dmaengine_terminate_all(chan);
5f258b3e 805 xmit->tail += atmel_port->tx_len;
08f738be
ES		 806 xmit->tail &= UART_XMIT_SIZE - 1;
807
5f258b3e 808 port->icount.tx += atmel_port->tx_len;
08f738be
ES		 809
810 spin_lock_irq(&atmel_port->lock_tx);
811 async_tx_ack(atmel_port->desc_tx);
812 atmel_port->cookie_tx = -EINVAL;
813 atmel_port->desc_tx = NULL;
814 spin_unlock_irq(&atmel_port->lock_tx);
815
816 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
817 uart_write_wakeup(port);
818
1842dc2e
CP		 819 /*
820 * xmit is a circular buffer so, if we have just send data from
821 * xmit->tail to the end of xmit->buf, now we have to transmit the
822 * remaining data from the beginning of xmit->buf to xmit->head.
823 */
08f738be 824 if (!uart_circ_empty(xmit))
98f2082c 825 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_tx);
b389f173
RG		 826 else if ((port->rs485.flags & SER_RS485_ENABLED) &&
827 !(port->rs485.flags & SER_RS485_RX_DURING_TX)) {
828 /* DMA done, stop TX, start RX for RS485 */
829 atmel_start_rx(port);
830 }
08f738be
ES		 831
832 spin_unlock_irqrestore(&port->lock, flags);
833}
834
835static void atmel_release_tx_dma(struct uart_port *port)
836{
837 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
838 struct dma_chan *chan = atmel_port->chan_tx;
839
840 if (chan) {
841 dmaengine_terminate_all(chan);
842 dma_release_channel(chan);
843 dma_unmap_sg(port->dev, &atmel_port->sg_tx, 1,
48479148 844 DMA_TO_DEVICE);
08f738be
ES		 845 }
846
847 atmel_port->desc_tx = NULL;
848 atmel_port->chan_tx = NULL;
849 atmel_port->cookie_tx = -EINVAL;
850}
851
852/*
853 * Called from tasklet with TXRDY interrupt is disabled.
854 */
855static void atmel_tx_dma(struct uart_port *port)
856{
857 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
858 struct circ_buf *xmit = &port->state->xmit;
859 struct dma_chan *chan = atmel_port->chan_tx;
860 struct dma_async_tx_descriptor *desc;
5f258b3e
CP		 861 struct scatterlist sgl[2], *sg, *sg_tx = &atmel_port->sg_tx;
862 unsigned int tx_len, part1_len, part2_len, sg_len;
863 dma_addr_t phys_addr;
08f738be
ES		 864
865 /* Make sure we have an idle channel */
866 if (atmel_port->desc_tx != NULL)
867 return;
868
869 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) {
870 /*
871 * DMA is idle now.
872 * Port xmit buffer is already mapped,
873 * and it is one page... Just adjust
874 * offsets and lengths. Since it is a circular buffer,
875 * we have to transmit till the end, and then the rest.
876 * Take the port lock to get a
877 * consistent xmit buffer state.
878 */
5f258b3e
CP		 879 tx_len = CIRC_CNT_TO_END(xmit->head,
880 xmit->tail,
881 UART_XMIT_SIZE);
882
883 if (atmel_port->fifo_size) {
884 /* multi data mode */
885 part1_len = (tx_len & ~0x3); /* DWORD access */
886 part2_len = (tx_len & 0x3); /* BYTE access */
887 } else {
888 /* single data (legacy) mode */
889 part1_len = 0;
890 part2_len = tx_len; /* BYTE access only */
891 }
892
893 sg_init_table(sgl, 2);
894 sg_len = 0;
895 phys_addr = sg_dma_address(sg_tx) + xmit->tail;
896 if (part1_len) {
897 sg = &sgl[sg_len++];
898 sg_dma_address(sg) = phys_addr;
899 sg_dma_len(sg) = part1_len;
900
901 phys_addr += part1_len;
902 }
903
904 if (part2_len) {
905 sg = &sgl[sg_len++];
906 sg_dma_address(sg) = phys_addr;
907 sg_dma_len(sg) = part2_len;
908 }
909
910 /*
911 * save tx_len so atmel_complete_tx_dma() will increase
912 * xmit->tail correctly
913 */
914 atmel_port->tx_len = tx_len;
08f738be
ES		 915
916 desc = dmaengine_prep_slave_sg(chan,
5f258b3e
CP		 917 sgl,
918 sg_len,
1842dc2e
CP		 919 DMA_MEM_TO_DEV,
920 DMA_PREP_INTERRUPT |
921 DMA_CTRL_ACK);
08f738be
ES		 922 if (!desc) {
923 dev_err(port->dev, "Failed to send via dma!\n");
924 return;
925 }
926
5f258b3e 927 dma_sync_sg_for_device(port->dev, sg_tx, 1, DMA_TO_DEVICE);
08f738be
ES		 928
929 atmel_port->desc_tx = desc;
930 desc->callback = atmel_complete_tx_dma;
931 desc->callback_param = atmel_port;
932 atmel_port->cookie_tx = dmaengine_submit(desc);
08f738be
ES		 933 }
934
935 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
936 uart_write_wakeup(port);
937}
938
939static int atmel_prepare_tx_dma(struct uart_port *port)
940{
941 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
942 dma_cap_mask_t mask;
943 struct dma_slave_config config;
944 int ret, nent;
945
946 dma_cap_zero(mask);
947 dma_cap_set(DMA_SLAVE, mask);
948
949 atmel_port->chan_tx = dma_request_slave_channel(port->dev, "tx");
950 if (atmel_port->chan_tx == NULL)
951 goto chan_err;
952 dev_info(port->dev, "using %s for tx DMA transfers\n",
953 dma_chan_name(atmel_port->chan_tx));
954
955 spin_lock_init(&atmel_port->lock_tx);
956 sg_init_table(&atmel_port->sg_tx, 1);
957 /* UART circular tx buffer is an aligned page. */
2c277054 958 BUG_ON(!PAGE_ALIGNED(port->state->xmit.buf));
08f738be
ES		 959 sg_set_page(&atmel_port->sg_tx,
960 virt_to_page(port->state->xmit.buf),
961 UART_XMIT_SIZE,
c8d1f022 962 (unsigned long)port->state->xmit.buf & ~PAGE_MASK);
08f738be
ES		 963 nent = dma_map_sg(port->dev,
964 &atmel_port->sg_tx,
965 1,
48479148 966 DMA_TO_DEVICE);
08f738be
ES		 967
968 if (!nent) {
969 dev_dbg(port->dev, "need to release resource of dma\n");
970 goto chan_err;
971 } else {
c8d1f022 972 dev_dbg(port->dev, "%s: mapped %d@%p to %pad\n", __func__,
08f738be
ES		 973 sg_dma_len(&atmel_port->sg_tx),
974 port->state->xmit.buf,
c8d1f022 975 &sg_dma_address(&atmel_port->sg_tx));
08f738be
ES		 976 }
977
978 /* Configure the slave DMA */
979 memset(&config, 0, sizeof(config));
980 config.direction = DMA_MEM_TO_DEV;
5f258b3e
CP		 981 config.dst_addr_width = (atmel_port->fifo_size) ?
982 DMA_SLAVE_BUSWIDTH_4_BYTES :
983 DMA_SLAVE_BUSWIDTH_1_BYTE;
08f738be 984 config.dst_addr = port->mapbase + ATMEL_US_THR;
a8d4e016 985 config.dst_maxburst = 1;
08f738be 986
5483c10e
MR		 987 ret = dmaengine_slave_config(atmel_port->chan_tx,
988 &config);
08f738be
ES		 989 if (ret) {
990 dev_err(port->dev, "DMA tx slave configuration failed\n");
991 goto chan_err;
992 }
993
994 return 0;
995
996chan_err:
997 dev_err(port->dev, "TX channel not available, switch to pio\n");
998 atmel_port->use_dma_tx = 0;
999 if (atmel_port->chan_tx)
1000 atmel_release_tx_dma(port);
1001 return -EINVAL;
1002}
1003
34df42f5
ES		 1004static void atmel_complete_rx_dma(void *arg)
1005{
1006 struct uart_port *port = arg;
1007 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1008
98f2082c 1009 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_rx);
34df42f5
ES		 1010}
1011
1012static void atmel_release_rx_dma(struct uart_port *port)
1013{
1014 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1015 struct dma_chan *chan = atmel_port->chan_rx;
1016
1017 if (chan) {
1018 dmaengine_terminate_all(chan);
1019 dma_release_channel(chan);
1020 dma_unmap_sg(port->dev, &atmel_port->sg_rx, 1,
48479148 1021 DMA_FROM_DEVICE);
34df42f5
ES		 1022 }
1023
1024 atmel_port->desc_rx = NULL;
1025 atmel_port->chan_rx = NULL;
1026 atmel_port->cookie_rx = -EINVAL;
1027}
1028
1029static void atmel_rx_from_dma(struct uart_port *port)
1030{
1031 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
66f37aaf 1032 struct tty_port *tport = &port->state->port;
34df42f5
ES		 1033 struct circ_buf *ring = &atmel_port->rx_ring;
1034 struct dma_chan *chan = atmel_port->chan_rx;
1035 struct dma_tx_state state;
1036 enum dma_status dmastat;
66f37aaf 1037 size_t count;
34df42f5
ES		 1038
1039
1040 /* Reset the UART timeout early so that we don't miss one */
4e7decda 1041 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
34df42f5
ES		 1042 dmastat = dmaengine_tx_status(chan,
1043 atmel_port->cookie_rx,
1044 &state);
1045 /* Restart a new tasklet if DMA status is error */
1046 if (dmastat == DMA_ERROR) {
1047 dev_dbg(port->dev, "Get residue error, restart tasklet\n");
4e7decda 1048 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_TIMEOUT);
98f2082c 1049 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_rx);
34df42f5
ES		 1050 return;
1051 }
34df42f5 1052
66f37aaf
CP		 1053 /* CPU claims ownership of RX DMA buffer */
1054 dma_sync_sg_for_cpu(port->dev,
1055 &atmel_port->sg_rx,
1056 1,
485819b5 1057 DMA_FROM_DEVICE);
66f37aaf
CP		 1058
1059 /*
1060 * ring->head points to the end of data already written by the DMA.
1061 * ring->tail points to the beginning of data to be read by the
1062 * framework.
1063 * The current transfer size should not be larger than the dma buffer
1064 * length.
1065 */
1066 ring->head = sg_dma_len(&atmel_port->sg_rx) - state.residue;
1067 BUG_ON(ring->head > sg_dma_len(&atmel_port->sg_rx));
34df42f5 1068 /*
66f37aaf
CP		 1069 * At this point ring->head may point to the first byte right after the
1070 * last byte of the dma buffer:
1071 * 0 <= ring->head <= sg_dma_len(&atmel_port->sg_rx)
1072 *
1073 * However ring->tail must always points inside the dma buffer:
1074 * 0 <= ring->tail <= sg_dma_len(&atmel_port->sg_rx) - 1
1075 *
1076 * Since we use a ring buffer, we have to handle the case
1077 * where head is lower than tail. In such a case, we first read from
1078 * tail to the end of the buffer then reset tail.
34df42f5 1079 */
66f37aaf
CP		 1080 if (ring->head < ring->tail) {
1081 count = sg_dma_len(&atmel_port->sg_rx) - ring->tail;
34df42f5 1082
66f37aaf
CP		 1083 tty_insert_flip_string(tport, ring->buf + ring->tail, count);
1084 ring->tail = 0;
1085 port->icount.rx += count;
1086 }
34df42f5 1087
66f37aaf
CP		 1088 /* Finally we read data from tail to head */
1089 if (ring->tail < ring->head) {
1090 count = ring->head - ring->tail;
34df42f5 1091
66f37aaf
CP		 1092 tty_insert_flip_string(tport, ring->buf + ring->tail, count);
1093 /* Wrap ring->head if needed */
1094 if (ring->head >= sg_dma_len(&atmel_port->sg_rx))
1095 ring->head = 0;
1096 ring->tail = ring->head;
34df42f5
ES		 1097 port->icount.rx += count;
1098 }
1099
66f37aaf
CP		 1100 /* USART retreives ownership of RX DMA buffer */
1101 dma_sync_sg_for_device(port->dev,
1102 &atmel_port->sg_rx,
1103 1,
485819b5 1104 DMA_FROM_DEVICE);
66f37aaf
CP		 1105
1106 /*
1107 * Drop the lock here since it might end up calling
1108 * uart_start(), which takes the lock.
1109 */
1110 spin_unlock(&port->lock);
1111 tty_flip_buffer_push(tport);
1112 spin_lock(&port->lock);
1113
4e7decda 1114 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_TIMEOUT);
34df42f5
ES		 1115}
1116
1117static int atmel_prepare_rx_dma(struct uart_port *port)
1118{
1119 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1120 struct dma_async_tx_descriptor *desc;
1121 dma_cap_mask_t mask;
1122 struct dma_slave_config config;
1123 struct circ_buf *ring;
1124 int ret, nent;
1125
1126 ring = &atmel_port->rx_ring;
1127
1128 dma_cap_zero(mask);
1129 dma_cap_set(DMA_CYCLIC, mask);
1130
1131 atmel_port->chan_rx = dma_request_slave_channel(port->dev, "rx");
1132 if (atmel_port->chan_rx == NULL)
1133 goto chan_err;
1134 dev_info(port->dev, "using %s for rx DMA transfers\n",
1135 dma_chan_name(atmel_port->chan_rx));
1136
1137 spin_lock_init(&atmel_port->lock_rx);
1138 sg_init_table(&atmel_port->sg_rx, 1);
1139 /* UART circular rx buffer is an aligned page. */
2c277054 1140 BUG_ON(!PAGE_ALIGNED(ring->buf));
34df42f5 1141 sg_set_page(&atmel_port->sg_rx,
1842dc2e 1142 virt_to_page(ring->buf),
a510880f 1143 sizeof(struct atmel_uart_char) * ATMEL_SERIAL_RINGSIZE,
c8d1f022 1144 (unsigned long)ring->buf & ~PAGE_MASK);
1842dc2e
CP		 1145 nent = dma_map_sg(port->dev,
1146 &atmel_port->sg_rx,
1147 1,
1148 DMA_FROM_DEVICE);
34df42f5
ES		 1149
1150 if (!nent) {
1151 dev_dbg(port->dev, "need to release resource of dma\n");
1152 goto chan_err;
1153 } else {
c8d1f022 1154 dev_dbg(port->dev, "%s: mapped %d@%p to %pad\n", __func__,
34df42f5
ES		 1155 sg_dma_len(&atmel_port->sg_rx),
1156 ring->buf,
c8d1f022 1157 &sg_dma_address(&atmel_port->sg_rx));
34df42f5
ES		 1158 }
1159
1160 /* Configure the slave DMA */
1161 memset(&config, 0, sizeof(config));
1162 config.direction = DMA_DEV_TO_MEM;
1163 config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1164 config.src_addr = port->mapbase + ATMEL_US_RHR;
a8d4e016 1165 config.src_maxburst = 1;
34df42f5 1166
5483c10e
MR		 1167 ret = dmaengine_slave_config(atmel_port->chan_rx,
1168 &config);
34df42f5
ES		 1169 if (ret) {
1170 dev_err(port->dev, "DMA rx slave configuration failed\n");
1171 goto chan_err;
1172 }
1173 /*
1174 * Prepare a cyclic dma transfer, assign 2 descriptors,
1175 * each one is half ring buffer size
1176 */
1177 desc = dmaengine_prep_dma_cyclic(atmel_port->chan_rx,
1842dc2e
CP		 1178 sg_dma_address(&atmel_port->sg_rx),
1179 sg_dma_len(&atmel_port->sg_rx),
1180 sg_dma_len(&atmel_port->sg_rx)/2,
1181 DMA_DEV_TO_MEM,
1182 DMA_PREP_INTERRUPT);
34df42f5
ES		 1183 desc->callback = atmel_complete_rx_dma;
1184 desc->callback_param = port;
1185 atmel_port->desc_rx = desc;
1186 atmel_port->cookie_rx = dmaengine_submit(desc);
1187
1188 return 0;
1189
1190chan_err:
1191 dev_err(port->dev, "RX channel not available, switch to pio\n");
1192 atmel_port->use_dma_rx = 0;
1193 if (atmel_port->chan_rx)
1194 atmel_release_rx_dma(port);
1195 return -EINVAL;
1196}
1197
2e68c22f
ES		 1198static void atmel_uart_timer_callback(unsigned long data)
1199{
1200 struct uart_port *port = (void *)data;
1201 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1202
98f2082c
NF		 1203 if (!atomic_read(&atmel_port->tasklet_shutdown)) {
1204 tasklet_schedule(&atmel_port->tasklet_rx);
1205 mod_timer(&atmel_port->uart_timer,
1206 jiffies + uart_poll_timeout(port));
1207 }
2e68c22f
ES		 1208}
1209
b843aa21
RB		 1210/*
1211 * receive interrupt handler.
1212 */
1213static void
1214atmel_handle_receive(struct uart_port *port, unsigned int pending)
1215{
c811ab8c 1216 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
b843aa21 1217
64e22ebe 1218 if (atmel_use_pdc_rx(port)) {
a6670615
CC		 1219 /*
1220 * PDC receive. Just schedule the tasklet and let it
1221 * figure out the details.
1222 *
1223 * TODO: We're not handling error flags correctly at
1224 * the moment.
1225 */
1226 if (pending & (ATMEL_US_ENDRX | ATMEL_US_TIMEOUT)) {
4e7decda
CP		 1227 atmel_uart_writel(port, ATMEL_US_IDR,
1228 (ATMEL_US_ENDRX | ATMEL_US_TIMEOUT));
98f2082c
NF		 1229 atmel_tasklet_schedule(atmel_port,
1230 &atmel_port->tasklet_rx);
a6670615
CC		 1231 }
1232
1233 if (pending & (ATMEL_US_RXBRK | ATMEL_US_OVRE |
1234 ATMEL_US_FRAME | ATMEL_US_PARE))
1235 atmel_pdc_rxerr(port, pending);
1236 }
1237
34df42f5
ES		 1238 if (atmel_use_dma_rx(port)) {
1239 if (pending & ATMEL_US_TIMEOUT) {
4e7decda
CP		 1240 atmel_uart_writel(port, ATMEL_US_IDR,
1241 ATMEL_US_TIMEOUT);
98f2082c
NF		 1242 atmel_tasklet_schedule(atmel_port,
1243 &atmel_port->tasklet_rx);
34df42f5
ES		 1244 }
1245 }
1246
b843aa21
RB		 1247 /* Interrupt receive */
1248 if (pending & ATMEL_US_RXRDY)
1249 atmel_rx_chars(port);
1250 else if (pending & ATMEL_US_RXBRK) {
1251 /*
1252 * End of break detected. If it came along with a
1253 * character, atmel_rx_chars will handle it.
1254 */
4e7decda
CP		 1255 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
1256 atmel_uart_writel(port, ATMEL_US_IDR, ATMEL_US_RXBRK);
b843aa21
RB		 1257 atmel_port->break_active = 0;
1258 }
1259}
1260
1261/*
1ecc26bd 1262 * transmit interrupt handler. (Transmit is IRQF_NODELAY safe)
b843aa21
RB		 1263 */
1264static void
1265atmel_handle_transmit(struct uart_port *port, unsigned int pending)
1266{
c811ab8c 1267 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1ecc26bd 1268
e8faff73
CS		 1269 if (pending & atmel_port->tx_done_mask) {
1270 /* Either PDC or interrupt transmission */
4e7decda
CP		 1271 atmel_uart_writel(port, ATMEL_US_IDR,
1272 atmel_port->tx_done_mask);
98f2082c 1273 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_tx);
1ecc26bd 1274 }
b843aa21
RB		 1275}
1276
1277/*
1278 * status flags interrupt handler.
1279 */
1280static void
1281atmel_handle_status(struct uart_port *port, unsigned int pending,
1282 unsigned int status)
1283{
c811ab8c 1284 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
9205218e 1285 unsigned int status_change;
1ecc26bd 1286
b843aa21 1287 if (pending & (ATMEL_US_RIIC | ATMEL_US_DSRIC | ATMEL_US_DCDIC
1ecc26bd 1288 | ATMEL_US_CTSIC)) {
9205218e 1289 status_change = status ^ atmel_port->irq_status_prev;
d033e82d 1290 atmel_port->irq_status_prev = status;
9205218e
NF		 1291
1292 if (status_change & (ATMEL_US_RI | ATMEL_US_DSR
1293 | ATMEL_US_DCD | ATMEL_US_CTS)) {
1294 /* TODO: All reads to CSR will clear these interrupts! */
1295 if (status_change & ATMEL_US_RI)
1296 port->icount.rng++;
1297 if (status_change & ATMEL_US_DSR)
1298 port->icount.dsr++;
1299 if (status_change & ATMEL_US_DCD)
1300 uart_handle_dcd_change(port, !(status & ATMEL_US_DCD));
1301 if (status_change & ATMEL_US_CTS)
1302 uart_handle_cts_change(port, !(status & ATMEL_US_CTS));
1303
1304 wake_up_interruptible(&port->state->port.delta_msr_wait);
1305 }
1ecc26bd 1306 }
b843aa21
RB		 1307}
1308
1e6c9c28
AV		 1309/*
1310 * Interrupt handler
1311 */
7d12e780 1312static irqreturn_t atmel_interrupt(int irq, void *dev_id)
1e6c9c28
AV		 1313{
1314 struct uart_port *port = dev_id;
ab5e4e41 1315 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2c7af5ba 1316 unsigned int status, pending, mask, pass_counter = 0;
1e6c9c28 1317
2c7af5ba
BB		 1318 spin_lock(&atmel_port->lock_suspended);
1319
a6670615 1320 do {
e0b0baad 1321 status = atmel_get_lines_status(port);
4e7decda 1322 mask = atmel_uart_readl(port, ATMEL_US_IMR);
2c7af5ba 1323 pending = status & mask;
a6670615
CC		 1324 if (!pending)
1325 break;
1326
2c7af5ba
BB		 1327 if (atmel_port->suspended) {
1328 atmel_port->pending |= pending;
1329 atmel_port->pending_status = status;
4e7decda 1330 atmel_uart_writel(port, ATMEL_US_IDR, mask);
2c7af5ba
BB		 1331 pm_system_wakeup();
1332 break;
1333 }
1334
b843aa21
RB		 1335 atmel_handle_receive(port, pending);
1336 atmel_handle_status(port, pending, status);
1337 atmel_handle_transmit(port, pending);
a6670615 1338 } while (pass_counter++ < ATMEL_ISR_PASS_LIMIT);
afefc415 1339
2c7af5ba
BB		 1340 spin_unlock(&atmel_port->lock_suspended);
1341
0400b697 1342 return pass_counter ? IRQ_HANDLED : IRQ_NONE;
a6670615 1343}
1e6c9c28 1344
a930e528
ES		 1345static void atmel_release_tx_pdc(struct uart_port *port)
1346{
1347 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1348 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1349
1350 dma_unmap_single(port->dev,
1351 pdc->dma_addr,
1352 pdc->dma_size,
1353 DMA_TO_DEVICE);
1354}
1355
a6670615
CC		 1356/*
1357 * Called from tasklet with ENDTX and TXBUFE interrupts disabled.
1358 */
64e22ebe 1359static void atmel_tx_pdc(struct uart_port *port)
a6670615 1360{
c811ab8c 1361 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
ebd2c8f6 1362 struct circ_buf *xmit = &port->state->xmit;
a6670615
CC		 1363 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1364 int count;
1365
ba0657ff 1366 /* nothing left to transmit? */
4e7decda 1367 if (atmel_uart_readl(port, ATMEL_PDC_TCR))
ba0657ff
MT		 1368 return;
1369
a6670615
CC		 1370 xmit->tail += pdc->ofs;
1371 xmit->tail &= UART_XMIT_SIZE - 1;
1372
1373 port->icount.tx += pdc->ofs;
1374 pdc->ofs = 0;
1375
ba0657ff 1376 /* more to transmit - setup next transfer */
a6670615 1377
ba0657ff 1378 /* disable PDC transmit */
4e7decda 1379 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS);
ba0657ff 1380
1f14081d 1381 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) {
a6670615
CC		 1382 dma_sync_single_for_device(port->dev,
1383 pdc->dma_addr,
1384 pdc->dma_size,
1385 DMA_TO_DEVICE);
1386
1387 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
1388 pdc->ofs = count;
1389
4e7decda
CP		 1390 atmel_uart_writel(port, ATMEL_PDC_TPR,
1391 pdc->dma_addr + xmit->tail);
1392 atmel_uart_writel(port, ATMEL_PDC_TCR, count);
e8faff73 1393 /* re-enable PDC transmit */
4e7decda 1394 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
e8faff73 1395 /* Enable interrupts */
4e7decda
CP		 1396 atmel_uart_writel(port, ATMEL_US_IER,
1397 atmel_port->tx_done_mask);
e8faff73 1398 } else {
13bd3e6f
RRD		 1399 if ((port->rs485.flags & SER_RS485_ENABLED) &&
1400 !(port->rs485.flags & SER_RS485_RX_DURING_TX)) {
e8faff73
CS		 1401 /* DMA done, stop TX, start RX for RS485 */
1402 atmel_start_rx(port);
1403 }
1e6c9c28 1404 }
a6670615
CC		 1405
1406 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1407 uart_write_wakeup(port);
1e6c9c28
AV		 1408}
1409
a930e528
ES		 1410static int atmel_prepare_tx_pdc(struct uart_port *port)
1411{
1412 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1413 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1414 struct circ_buf *xmit = &port->state->xmit;
1415
1416 pdc->buf = xmit->buf;
1417 pdc->dma_addr = dma_map_single(port->dev,
1418 pdc->buf,
1419 UART_XMIT_SIZE,
1420 DMA_TO_DEVICE);
1421 pdc->dma_size = UART_XMIT_SIZE;
1422 pdc->ofs = 0;
1423
1424 return 0;
1425}
1426
1ecc26bd
RB		 1427static void atmel_rx_from_ring(struct uart_port *port)
1428{
c811ab8c 1429 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1ecc26bd
RB		 1430 struct circ_buf *ring = &atmel_port->rx_ring;
1431 unsigned int flg;
1432 unsigned int status;
1433
1434 while (ring->head != ring->tail) {
1435 struct atmel_uart_char c;
1436
1437 /* Make sure c is loaded after head. */
1438 smp_rmb();
1439
1440 c = ((struct atmel_uart_char *)ring->buf)[ring->tail];
1441
1442 ring->tail = (ring->tail + 1) & (ATMEL_SERIAL_RINGSIZE - 1);
1443
1444 port->icount.rx++;
1445 status = c.status;
1446 flg = TTY_NORMAL;
1447
1448 /*
1449 * note that the error handling code is
1450 * out of the main execution path
1451 */
1452 if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME
1453 | ATMEL_US_OVRE | ATMEL_US_RXBRK))) {
1454 if (status & ATMEL_US_RXBRK) {
1455 /* ignore side-effect */
1456 status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME);
1457
1458 port->icount.brk++;
1459 if (uart_handle_break(port))
1460 continue;
1461 }
1462 if (status & ATMEL_US_PARE)
1463 port->icount.parity++;
1464 if (status & ATMEL_US_FRAME)
1465 port->icount.frame++;
1466 if (status & ATMEL_US_OVRE)
1467 port->icount.overrun++;
1468
1469 status &= port->read_status_mask;
1470
1471 if (status & ATMEL_US_RXBRK)
1472 flg = TTY_BREAK;
1473 else if (status & ATMEL_US_PARE)
1474 flg = TTY_PARITY;
1475 else if (status & ATMEL_US_FRAME)
1476 flg = TTY_FRAME;
1477 }
1478
1479
1480 if (uart_handle_sysrq_char(port, c.ch))
1481 continue;
1482
1483 uart_insert_char(port, status, ATMEL_US_OVRE, c.ch, flg);
1484 }
1485
1486 /*
1487 * Drop the lock here since it might end up calling
1488 * uart_start(), which takes the lock.
1489 */
1490 spin_unlock(&port->lock);
2e124b4a 1491 tty_flip_buffer_push(&port->state->port);
1ecc26bd
RB		 1492 spin_lock(&port->lock);
1493}
1494
a930e528
ES		 1495static void atmel_release_rx_pdc(struct uart_port *port)
1496{
1497 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1498 int i;
1499
1500 for (i = 0; i < 2; i++) {
1501 struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i];
1502
1503 dma_unmap_single(port->dev,
1504 pdc->dma_addr,
1505 pdc->dma_size,
1506 DMA_FROM_DEVICE);
1507 kfree(pdc->buf);
1508 }
1509}
1510
64e22ebe 1511static void atmel_rx_from_pdc(struct uart_port *port)
a6670615 1512{
c811ab8c 1513 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
05c7cd39 1514 struct tty_port *tport = &port->state->port;
a6670615
CC		 1515 struct atmel_dma_buffer *pdc;
1516 int rx_idx = atmel_port->pdc_rx_idx;
1517 unsigned int head;
1518 unsigned int tail;
1519 unsigned int count;
1520
1521 do {
1522 /* Reset the UART timeout early so that we don't miss one */
4e7decda 1523 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
a6670615
CC		 1524
1525 pdc = &atmel_port->pdc_rx[rx_idx];
4e7decda 1526 head = atmel_uart_readl(port, ATMEL_PDC_RPR) - pdc->dma_addr;
a6670615
CC		 1527 tail = pdc->ofs;
1528
1529 /* If the PDC has switched buffers, RPR won't contain
1530 * any address within the current buffer. Since head
1531 * is unsigned, we just need a one-way comparison to
1532 * find out.
1533 *
1534 * In this case, we just need to consume the entire
1535 * buffer and resubmit it for DMA. This will clear the
1536 * ENDRX bit as well, so that we can safely re-enable
1537 * all interrupts below.
1538 */
1539 head = min(head, pdc->dma_size);
1540
1541 if (likely(head != tail)) {
1542 dma_sync_single_for_cpu(port->dev, pdc->dma_addr,
1543 pdc->dma_size, DMA_FROM_DEVICE);
1544
1545 /*
1546 * head will only wrap around when we recycle
1547 * the DMA buffer, and when that happens, we
1548 * explicitly set tail to 0. So head will
1549 * always be greater than tail.
1550 */
1551 count = head - tail;
1552
05c7cd39
JS		 1553 tty_insert_flip_string(tport, pdc->buf + pdc->ofs,
1554 count);
a6670615
CC		 1555
1556 dma_sync_single_for_device(port->dev, pdc->dma_addr,
1557 pdc->dma_size, DMA_FROM_DEVICE);
1558
1559 port->icount.rx += count;
1560 pdc->ofs = head;
1561 }
1562
1563 /*
1564 * If the current buffer is full, we need to check if
1565 * the next one contains any additional data.
1566 */
1567 if (head >= pdc->dma_size) {
1568 pdc->ofs = 0;
4e7decda
CP		 1569 atmel_uart_writel(port, ATMEL_PDC_RNPR, pdc->dma_addr);
1570 atmel_uart_writel(port, ATMEL_PDC_RNCR, pdc->dma_size);
a6670615
CC		 1571
1572 rx_idx = !rx_idx;
1573 atmel_port->pdc_rx_idx = rx_idx;
1574 }
1575 } while (head >= pdc->dma_size);
1576
1577 /*
1578 * Drop the lock here since it might end up calling
1579 * uart_start(), which takes the lock.
1580 */
1581 spin_unlock(&port->lock);
2e124b4a 1582 tty_flip_buffer_push(tport);
a6670615
CC		 1583 spin_lock(&port->lock);
1584
4e7decda
CP		 1585 atmel_uart_writel(port, ATMEL_US_IER,
1586 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT);
a6670615
CC		 1587}
1588
a930e528
ES		 1589static int atmel_prepare_rx_pdc(struct uart_port *port)
1590{
1591 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1592 int i;
1593
1594 for (i = 0; i < 2; i++) {
1595 struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i];
1596
1597 pdc->buf = kmalloc(PDC_BUFFER_SIZE, GFP_KERNEL);
1598 if (pdc->buf == NULL) {
1599 if (i != 0) {
1600 dma_unmap_single(port->dev,
1601 atmel_port->pdc_rx[0].dma_addr,
1602 PDC_BUFFER_SIZE,
1603 DMA_FROM_DEVICE);
1604 kfree(atmel_port->pdc_rx[0].buf);
1605 }
1606 atmel_port->use_pdc_rx = 0;
1607 return -ENOMEM;
1608 }
1609 pdc->dma_addr = dma_map_single(port->dev,
1610 pdc->buf,
1611 PDC_BUFFER_SIZE,
1612 DMA_FROM_DEVICE);
1613 pdc->dma_size = PDC_BUFFER_SIZE;
1614 pdc->ofs = 0;
1615 }
1616
1617 atmel_port->pdc_rx_idx = 0;
1618
4e7decda
CP		 1619 atmel_uart_writel(port, ATMEL_PDC_RPR, atmel_port->pdc_rx[0].dma_addr);
1620 atmel_uart_writel(port, ATMEL_PDC_RCR, PDC_BUFFER_SIZE);
a930e528 1621
4e7decda
CP		 1622 atmel_uart_writel(port, ATMEL_PDC_RNPR,
1623 atmel_port->pdc_rx[1].dma_addr);
1624 atmel_uart_writel(port, ATMEL_PDC_RNCR, PDC_BUFFER_SIZE);
a930e528
ES		 1625
1626 return 0;
1627}
1628
1ecc26bd
RB		 1629/*
1630 * tasklet handling tty stuff outside the interrupt handler.
1631 */
00e8e658 1632static void atmel_tasklet_rx_func(unsigned long data)
1ecc26bd
RB		 1633{
1634 struct uart_port *port = (struct uart_port *)data;
c811ab8c 1635 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1ecc26bd
RB		 1636
1637 /* The interrupt handler does not take the lock */
1638 spin_lock(&port->lock);
a930e528 1639 atmel_port->schedule_rx(port);
00e8e658
NF		 1640 spin_unlock(&port->lock);
1641}
1ecc26bd 1642
00e8e658
NF		 1643static void atmel_tasklet_tx_func(unsigned long data)
1644{
1645 struct uart_port *port = (struct uart_port *)data;
1646 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1647
1648 /* The interrupt handler does not take the lock */
1649 spin_lock(&port->lock);
1650 atmel_port->schedule_tx(port);
1ecc26bd
RB		 1651 spin_unlock(&port->lock);
1652}
1653
4a1e8888 1654static void atmel_init_property(struct atmel_uart_port *atmel_port,
33d64c4f
ES		 1655 struct platform_device *pdev)
1656{
1657 struct device_node *np = pdev->dev.of_node;
574de559 1658 struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev);
33d64c4f
ES		 1659
1660 if (np) {
1661 /* DMA/PDC usage specification */
490d5ce2
JL		 1662 if (of_property_read_bool(np, "atmel,use-dma-rx")) {
1663 if (of_property_read_bool(np, "dmas")) {
33d64c4f
ES		 1664 atmel_port->use_dma_rx = true;
1665 atmel_port->use_pdc_rx = false;
1666 } else {
1667 atmel_port->use_dma_rx = false;
1668 atmel_port->use_pdc_rx = true;
1669 }
1670 } else {
1671 atmel_port->use_dma_rx = false;
1672 atmel_port->use_pdc_rx = false;
1673 }
1674
490d5ce2
JL		 1675 if (of_property_read_bool(np, "atmel,use-dma-tx")) {
1676 if (of_property_read_bool(np, "dmas")) {
33d64c4f
ES		 1677 atmel_port->use_dma_tx = true;
1678 atmel_port->use_pdc_tx = false;
1679 } else {
1680 atmel_port->use_dma_tx = false;
1681 atmel_port->use_pdc_tx = true;
1682 }
1683 } else {
1684 atmel_port->use_dma_tx = false;
1685 atmel_port->use_pdc_tx = false;
1686 }
1687
1688 } else {
1689 atmel_port->use_pdc_rx = pdata->use_dma_rx;
1690 atmel_port->use_pdc_tx = pdata->use_dma_tx;
1691 atmel_port->use_dma_rx = false;
1692 atmel_port->use_dma_tx = false;
1693 }
1694
33d64c4f
ES		 1695}
1696
13bd3e6f 1697static void atmel_init_rs485(struct uart_port *port,
33d64c4f
ES		 1698 struct platform_device *pdev)
1699{
1700 struct device_node *np = pdev->dev.of_node;
574de559 1701 struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev);
33d64c4f
ES		 1702
1703 if (np) {
77bdec6f 1704 struct serial_rs485 *rs485conf = &port->rs485;
33d64c4f
ES		 1705 u32 rs485_delay[2];
1706 /* rs485 properties */
1707 if (of_property_read_u32_array(np, "rs485-rts-delay",
1708 rs485_delay, 2) == 0) {
33d64c4f
ES		 1709 rs485conf->delay_rts_before_send = rs485_delay[0];
1710 rs485conf->delay_rts_after_send = rs485_delay[1];
1711 rs485conf->flags = 0;
77bdec6f 1712 }
33d64c4f
ES		 1713
1714 if (of_get_property(np, "rs485-rx-during-tx", NULL))
1715 rs485conf->flags |= SER_RS485_RX_DURING_TX;
1716
1717 if (of_get_property(np, "linux,rs485-enabled-at-boot-time",
1718 NULL))
1719 rs485conf->flags |= SER_RS485_ENABLED;
33d64c4f 1720 } else {
13bd3e6f 1721 port->rs485 = pdata->rs485;
33d64c4f
ES		 1722 }
1723
1724}
1725
a930e528
ES		 1726static void atmel_set_ops(struct uart_port *port)
1727{
1728 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1729
34df42f5
ES		 1730 if (atmel_use_dma_rx(port)) {
1731 atmel_port->prepare_rx = &atmel_prepare_rx_dma;
1732 atmel_port->schedule_rx = &atmel_rx_from_dma;
1733 atmel_port->release_rx = &atmel_release_rx_dma;
1734 } else if (atmel_use_pdc_rx(port)) {
a930e528
ES		 1735 atmel_port->prepare_rx = &atmel_prepare_rx_pdc;
1736 atmel_port->schedule_rx = &atmel_rx_from_pdc;
1737 atmel_port->release_rx = &atmel_release_rx_pdc;
1738 } else {
1739 atmel_port->prepare_rx = NULL;
1740 atmel_port->schedule_rx = &atmel_rx_from_ring;
1741 atmel_port->release_rx = NULL;
1742 }
1743
08f738be
ES		 1744 if (atmel_use_dma_tx(port)) {
1745 atmel_port->prepare_tx = &atmel_prepare_tx_dma;
1746 atmel_port->schedule_tx = &atmel_tx_dma;
1747 atmel_port->release_tx = &atmel_release_tx_dma;
1748 } else if (atmel_use_pdc_tx(port)) {
a930e528
ES		 1749 atmel_port->prepare_tx = &atmel_prepare_tx_pdc;
1750 atmel_port->schedule_tx = &atmel_tx_pdc;
1751 atmel_port->release_tx = &atmel_release_tx_pdc;
1752 } else {
1753 atmel_port->prepare_tx = NULL;
1754 atmel_port->schedule_tx = &atmel_tx_chars;
1755 atmel_port->release_tx = NULL;
1756 }
1757}
1758
055560b0
ES		 1759/*
1760 * Get ip name usart or uart
1761 */
892db58b 1762static void atmel_get_ip_name(struct uart_port *port)
055560b0
ES		 1763{
1764 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
4e7decda 1765 int name = atmel_uart_readl(port, ATMEL_US_NAME);
731d9cae 1766 u32 version;
1d673fb9 1767 u32 usart, dbgu_uart, new_uart;
4b769371
NF		 1768 /* ASCII decoding for IP version */
1769 usart = 0x55534152; /* USAR(T) */
1770 dbgu_uart = 0x44424755; /* DBGU */
1d673fb9 1771 new_uart = 0x55415254; /* UART */
055560b0 1772
5bf5635a
LD		 1773 /*
1774 * Only USART devices from at91sam9260 SOC implement fractional
2867af2d
RI		 1775 * baudrate. It is available for all asynchronous modes, with the
1776 * following restriction: the sampling clock's duty cycle is not
1777 * constant.
5bf5635a
LD		 1778 */
1779 atmel_port->has_frac_baudrate = false;
4b769371 1780 atmel_port->has_hw_timer = false;
055560b0 1781
2958ccee
LD		 1782 if (name == new_uart) {
1783 dev_dbg(port->dev, "Uart with hw timer");
4b769371 1784 atmel_port->has_hw_timer = true;
2958ccee
LD		 1785 atmel_port->rtor = ATMEL_UA_RTOR;
1786 } else if (name == usart) {
1787 dev_dbg(port->dev, "Usart\n");
5bf5635a 1788 atmel_port->has_frac_baudrate = true;
2958ccee
LD		 1789 atmel_port->has_hw_timer = true;
1790 atmel_port->rtor = ATMEL_US_RTOR;
4b769371
NF		 1791 } else if (name == dbgu_uart) {
1792 dev_dbg(port->dev, "Dbgu or uart without hw timer\n");
055560b0 1793 } else {
731d9cae 1794 /* fallback for older SoCs: use version field */
4e7decda 1795 version = atmel_uart_readl(port, ATMEL_US_VERSION);
731d9cae
NF		 1796 switch (version) {
1797 case 0x302:
1798 case 0x10213:
1799 dev_dbg(port->dev, "This version is usart\n");
5bf5635a 1800 atmel_port->has_frac_baudrate = true;
4b769371 1801 atmel_port->has_hw_timer = true;
2958ccee 1802 atmel_port->rtor = ATMEL_US_RTOR;
731d9cae
NF		 1803 break;
1804 case 0x203:
1805 case 0x10202:
1806 dev_dbg(port->dev, "This version is uart\n");
731d9cae
NF		 1807 break;
1808 default:
1809 dev_err(port->dev, "Not supported ip name nor version, set to uart\n");
1810 }
055560b0 1811 }
055560b0
ES		 1812}
1813
1e6c9c28
AV		 1814/*
1815 * Perform initialization and enable port for reception
1816 */
7192f92c 1817static int atmel_startup(struct uart_port *port)
1e6c9c28 1818{
33d64c4f 1819 struct platform_device *pdev = to_platform_device(port->dev);
c811ab8c 1820 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
ebd2c8f6 1821 struct tty_struct *tty = port->state->port.tty;
1e6c9c28
AV		 1822 int retval;
1823
1824 /*
1825 * Ensure that no interrupts are enabled otherwise when
1826 * request_irq() is called we could get stuck trying to
1827 * handle an unexpected interrupt
1828 */
4e7decda 1829 atmel_uart_writel(port, ATMEL_US_IDR, -1);
ab5e4e41 1830 atmel_port->ms_irq_enabled = false;
1e6c9c28
AV		 1831
1832 /*
1833 * Allocate the IRQ
1834 */
2c7af5ba
BB		 1835 retval = request_irq(port->irq, atmel_interrupt,
1836 IRQF_SHARED | IRQF_COND_SUSPEND,
ae161068 1837 tty ? tty->name : "atmel_serial", port);
1e6c9c28 1838 if (retval) {
ddaa6037 1839 dev_err(port->dev, "atmel_startup - Can't get irq\n");
1e6c9c28
AV		 1840 return retval;
1841 }
1842
98f2082c
NF		 1843 atomic_set(&atmel_port->tasklet_shutdown, 0);
1844 tasklet_init(&atmel_port->tasklet_rx, atmel_tasklet_rx_func,
1845 (unsigned long)port);
1846 tasklet_init(&atmel_port->tasklet_tx, atmel_tasklet_tx_func,
1847 (unsigned long)port);
1e125786 1848
a6670615
CC		 1849 /*
1850 * Initialize DMA (if necessary)
1851 */
33d64c4f 1852 atmel_init_property(atmel_port, pdev);
4d9628a1 1853 atmel_set_ops(port);
33d64c4f 1854
a930e528
ES		 1855 if (atmel_port->prepare_rx) {
1856 retval = atmel_port->prepare_rx(port);
1857 if (retval < 0)
1858 atmel_set_ops(port);
a6670615 1859 }
a6670615 1860
a930e528
ES		 1861 if (atmel_port->prepare_tx) {
1862 retval = atmel_port->prepare_tx(port);
1863 if (retval < 0)
1864 atmel_set_ops(port);
a6670615 1865 }
1e6c9c28 1866
b5199d46
CP		 1867 /*
1868 * Enable FIFO when available
1869 */
1870 if (atmel_port->fifo_size) {
1871 unsigned int txrdym = ATMEL_US_ONE_DATA;
1872 unsigned int rxrdym = ATMEL_US_ONE_DATA;
1873 unsigned int fmr;
1874
1875 atmel_uart_writel(port, ATMEL_US_CR,
1876 ATMEL_US_FIFOEN |
1877 ATMEL_US_RXFCLR |
1878 ATMEL_US_TXFLCLR);
1879
5f258b3e
CP		 1880 if (atmel_use_dma_tx(port))
1881 txrdym = ATMEL_US_FOUR_DATA;
1882
b5199d46
CP		 1883 fmr = ATMEL_US_TXRDYM(txrdym) | ATMEL_US_RXRDYM(rxrdym);
1884 if (atmel_port->rts_high &&
1885 atmel_port->rts_low)
1886 fmr |= ATMEL_US_FRTSC |
1887 ATMEL_US_RXFTHRES(atmel_port->rts_high) |
1888 ATMEL_US_RXFTHRES2(atmel_port->rts_low);
1889
1890 atmel_uart_writel(port, ATMEL_US_FMR, fmr);
1891 }
1892
27c0c8e5 1893 /* Save current CSR for comparison in atmel_tasklet_func() */
e0b0baad 1894 atmel_port->irq_status_prev = atmel_get_lines_status(port);
27c0c8e5 1895
1e6c9c28
AV		 1896 /*
1897 * Finally, enable the serial port
1898 */
4e7decda 1899 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
b843aa21 1900 /* enable xmit & rcvr */
4e7decda 1901 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN);
afefc415 1902
8bc661bf
MR		 1903 setup_timer(&atmel_port->uart_timer,
1904 atmel_uart_timer_callback,
1905 (unsigned long)port);
1906
64e22ebe 1907 if (atmel_use_pdc_rx(port)) {
a6670615 1908 /* set UART timeout */
4b769371 1909 if (!atmel_port->has_hw_timer) {
2e68c22f
ES		 1910 mod_timer(&atmel_port->uart_timer,
1911 jiffies + uart_poll_timeout(port));
1912 /* set USART timeout */
1913 } else {
2958ccee
LD		 1914 atmel_uart_writel(port, atmel_port->rtor,
1915 PDC_RX_TIMEOUT);
4e7decda 1916 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
a6670615 1917
4e7decda
CP		 1918 atmel_uart_writel(port, ATMEL_US_IER,
1919 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT);
2e68c22f 1920 }
a6670615 1921 /* enable PDC controller */
4e7decda 1922 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN);
34df42f5 1923 } else if (atmel_use_dma_rx(port)) {
2e68c22f 1924 /* set UART timeout */
4b769371 1925 if (!atmel_port->has_hw_timer) {
2e68c22f
ES		 1926 mod_timer(&atmel_port->uart_timer,
1927 jiffies + uart_poll_timeout(port));
1928 /* set USART timeout */
1929 } else {
2958ccee
LD		 1930 atmel_uart_writel(port, atmel_port->rtor,
1931 PDC_RX_TIMEOUT);
4e7decda 1932 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
34df42f5 1933
4e7decda
CP		 1934 atmel_uart_writel(port, ATMEL_US_IER,
1935 ATMEL_US_TIMEOUT);
2e68c22f 1936 }
a6670615
CC		 1937 } else {
1938 /* enable receive only */
4e7decda 1939 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_RXRDY);
a6670615 1940 }
afefc415 1941
1e6c9c28
AV		 1942 return 0;
1943}
1944
479e9b94
PH		 1945/*
1946 * Flush any TX data submitted for DMA. Called when the TX circular
1947 * buffer is reset.
1948 */
1949static void atmel_flush_buffer(struct uart_port *port)
1950{
1951 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1952
1953 if (atmel_use_pdc_tx(port)) {
4e7decda 1954 atmel_uart_writel(port, ATMEL_PDC_TCR, 0);
479e9b94
PH		 1955 atmel_port->pdc_tx.ofs = 0;
1956 }
1957}
1958
1e6c9c28
AV		 1959/*
1960 * Disable the port
1961 */
7192f92c 1962static void atmel_shutdown(struct uart_port *port)
1e6c9c28 1963{
c811ab8c 1964 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
0cc7c6c7 1965
0ae9fdef
RG		 1966 /* Disable modem control lines interrupts */
1967 atmel_disable_ms(port);
1968
98f2082c
NF		 1969 /* Disable interrupts at device level */
1970 atmel_uart_writel(port, ATMEL_US_IDR, -1);
1971
1972 /* Prevent spurious interrupts from scheduling the tasklet */
1973 atomic_inc(&atmel_port->tasklet_shutdown);
1974
8bc661bf
MR		 1975 /*
1976 * Prevent any tasklets being scheduled during
1977 * cleanup
1978 */
1979 del_timer_sync(&atmel_port->uart_timer);
1980
98f2082c
NF		 1981 /* Make sure that no interrupt is on the fly */
1982 synchronize_irq(port->irq);
1983
0cc7c6c7
MR		 1984 /*
1985 * Clear out any scheduled tasklets before
1986 * we destroy the buffers
1987 */
00e8e658
NF		 1988 tasklet_kill(&atmel_port->tasklet_rx);
1989 tasklet_kill(&atmel_port->tasklet_tx);
0cc7c6c7 1990
a6670615 1991 /*
0cc7c6c7 1992 * Ensure everything is stopped and
98f2082c 1993 * disable port and break condition.
a6670615
CC		 1994 */
1995 atmel_stop_rx(port);
1996 atmel_stop_tx(port);
1997
4e7decda 1998 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
0cc7c6c7 1999
a6670615
CC		 2000 /*
2001 * Shut-down the DMA.
2002 */
a930e528
ES		 2003 if (atmel_port->release_rx)
2004 atmel_port->release_rx(port);
2005 if (atmel_port->release_tx)
2006 atmel_port->release_tx(port);
a6670615 2007
bb7e73c5
MD		 2008 /*
2009 * Reset ring buffer pointers
2010 */
2011 atmel_port->rx_ring.head = 0;
2012 atmel_port->rx_ring.tail = 0;
2013
1e6c9c28 2014 /*
ab5e4e41 2015 * Free the interrupts
1e6c9c28
AV		 2016 */
2017 free_irq(port->irq, port);
ab5e4e41 2018
479e9b94 2019 atmel_flush_buffer(port);
9afd561a
HS		 2020}
2021
1e6c9c28
AV		 2022/*
2023 * Power / Clock management.
2024 */
b843aa21
RB		 2025static void atmel_serial_pm(struct uart_port *port, unsigned int state,
2026 unsigned int oldstate)
1e6c9c28 2027{
c811ab8c 2028 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
afefc415 2029
1e6c9c28 2030 switch (state) {
b843aa21
RB		 2031 case 0:
2032 /*
2033 * Enable the peripheral clock for this serial port.
2034 * This is called on uart_open() or a resume event.
2035 */
91f8c2d8 2036 clk_prepare_enable(atmel_port->clk);
f05596db
AS		 2037
2038 /* re-enable interrupts if we disabled some on suspend */
4e7decda 2039 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->backup_imr);
b843aa21
RB		 2040 break;
2041 case 3:
f05596db 2042 /* Back up the interrupt mask and disable all interrupts */
4e7decda
CP		 2043 atmel_port->backup_imr = atmel_uart_readl(port, ATMEL_US_IMR);
2044 atmel_uart_writel(port, ATMEL_US_IDR, -1);
f05596db 2045
b843aa21
RB		 2046 /*
2047 * Disable the peripheral clock for this serial port.
2048 * This is called on uart_close() or a suspend event.
2049 */
91f8c2d8 2050 clk_disable_unprepare(atmel_port->clk);
b843aa21
RB		 2051 break;
2052 default:
ddaa6037 2053 dev_err(port->dev, "atmel_serial: unknown pm %d\n", state);
1e6c9c28
AV		 2054 }
2055}
2056
2057/*
2058 * Change the port parameters
2059 */
b843aa21
RB		 2060static void atmel_set_termios(struct uart_port *port, struct ktermios *termios,
2061 struct ktermios *old)
1e6c9c28 2062{
5bf5635a 2063 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1e6c9c28 2064 unsigned long flags;
5bf5635a 2065 unsigned int old_mode, mode, imr, quot, baud, div, cd, fp = 0;
1cf6e8fc
CP		 2066
2067 /* save the current mode register */
4e7decda 2068 mode = old_mode = atmel_uart_readl(port, ATMEL_US_MR);
1e6c9c28 2069
1cf6e8fc
CP		 2070 /* reset the mode, clock divisor, parity, stop bits and data size */
2071 mode &= ~(ATMEL_US_USCLKS | ATMEL_US_CHRL | ATMEL_US_NBSTOP |
2072 ATMEL_US_PAR | ATMEL_US_USMODE);
03abeac0 2073
b843aa21 2074 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
1e6c9c28
AV		 2075
2076 /* byte size */
2077 switch (termios->c_cflag & CSIZE) {
2078 case CS5:
7192f92c 2079 mode |= ATMEL_US_CHRL_5;
1e6c9c28
AV		 2080 break;
2081 case CS6:
7192f92c 2082 mode |= ATMEL_US_CHRL_6;
1e6c9c28
AV		 2083 break;
2084 case CS7:
7192f92c 2085 mode |= ATMEL_US_CHRL_7;
1e6c9c28
AV		 2086 break;
2087 default:
7192f92c 2088 mode |= ATMEL_US_CHRL_8;
1e6c9c28
AV		 2089 break;
2090 }
2091
2092 /* stop bits */
2093 if (termios->c_cflag & CSTOPB)
7192f92c 2094 mode |= ATMEL_US_NBSTOP_2;
1e6c9c28
AV		 2095
2096 /* parity */
2097 if (termios->c_cflag & PARENB) {
b843aa21
RB		 2098 /* Mark or Space parity */
2099 if (termios->c_cflag & CMSPAR) {
1e6c9c28 2100 if (termios->c_cflag & PARODD)
7192f92c 2101 mode |= ATMEL_US_PAR_MARK;
1e6c9c28 2102 else
7192f92c 2103 mode |= ATMEL_US_PAR_SPACE;
b843aa21 2104 } else if (termios->c_cflag & PARODD)
7192f92c 2105 mode |= ATMEL_US_PAR_ODD;
1e6c9c28 2106 else
7192f92c 2107 mode |= ATMEL_US_PAR_EVEN;
b843aa21 2108 } else
7192f92c 2109 mode |= ATMEL_US_PAR_NONE;
1e6c9c28
AV		 2110
2111 spin_lock_irqsave(&port->lock, flags);
2112
7192f92c 2113 port->read_status_mask = ATMEL_US_OVRE;
1e6c9c28 2114 if (termios->c_iflag & INPCK)
7192f92c 2115 port->read_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE);
ef8b9ddc 2116 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
7192f92c 2117 port->read_status_mask |= ATMEL_US_RXBRK;
1e6c9c28 2118
64e22ebe 2119 if (atmel_use_pdc_rx(port))
a6670615 2120 /* need to enable error interrupts */
4e7decda 2121 atmel_uart_writel(port, ATMEL_US_IER, port->read_status_mask);
a6670615 2122
1e6c9c28
AV		 2123 /*
2124 * Characters to ignore
2125 */
2126 port->ignore_status_mask = 0;
2127 if (termios->c_iflag & IGNPAR)
7192f92c 2128 port->ignore_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE);
1e6c9c28 2129 if (termios->c_iflag & IGNBRK) {
7192f92c 2130 port->ignore_status_mask |= ATMEL_US_RXBRK;
1e6c9c28
AV		 2131 /*
2132 * If we're ignoring parity and break indicators,
2133 * ignore overruns too (for real raw support).
2134 */
2135 if (termios->c_iflag & IGNPAR)
7192f92c 2136 port->ignore_status_mask |= ATMEL_US_OVRE;
1e6c9c28 2137 }
b843aa21 2138 /* TODO: Ignore all characters if CREAD is set.*/
1e6c9c28
AV		 2139
2140 /* update the per-port timeout */
2141 uart_update_timeout(port, termios->c_cflag, baud);
2142
0ccad870
HS		 2143 /*
2144 * save/disable interrupts. The tty layer will ensure that the
2145 * transmitter is empty if requested by the caller, so there's
2146 * no need to wait for it here.
2147 */
4e7decda
CP		 2148 imr = atmel_uart_readl(port, ATMEL_US_IMR);
2149 atmel_uart_writel(port, ATMEL_US_IDR, -1);
1e6c9c28
AV		 2150
2151 /* disable receiver and transmitter */
4e7decda 2152 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXDIS | ATMEL_US_RXDIS);
1e6c9c28 2153
1cf6e8fc 2154 /* mode */
13bd3e6f 2155 if (port->rs485.flags & SER_RS485_ENABLED) {
4e7decda
CP		 2156 atmel_uart_writel(port, ATMEL_US_TTGR,
2157 port->rs485.delay_rts_after_send);
e8faff73 2158 mode |= ATMEL_US_USMODE_RS485;
1cf6e8fc
CP		 2159 } else if (termios->c_cflag & CRTSCTS) {
2160 /* RS232 with hardware handshake (RTS/CTS) */
9bcffe75
RG		 2161 if (atmel_use_fifo(port) &&
2162 !mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_CTS)) {
2163 /*
2164 * with ATMEL_US_USMODE_HWHS set, the controller will
2165 * be able to drive the RTS pin high/low when the RX
2166 * FIFO is above RXFTHRES/below RXFTHRES2.
2167 * It will also disable the transmitter when the CTS
2168 * pin is high.
2169 * This mode is not activated if CTS pin is a GPIO
2170 * because in this case, the transmitter is always
2171 * disabled (there must be an internal pull-up
2172 * responsible for this behaviour).
2173 * If the RTS pin is a GPIO, the controller won't be
2174 * able to drive it according to the FIFO thresholds,
2175 * but it will be handled by the driver.
2176 */
5be605ac 2177 mode |= ATMEL_US_USMODE_HWHS;
9bcffe75
RG		 2178 } else {
2179 /*
2180 * For platforms without FIFO, the flow control is
2181 * handled by the driver.
2182 */
2183 mode |= ATMEL_US_USMODE_NORMAL;
5be605ac 2184 }
1cf6e8fc
CP		 2185 } else {
2186 /* RS232 without hadware handshake */
2187 mode |= ATMEL_US_USMODE_NORMAL;
e8faff73
CS		 2188 }
2189
1cf6e8fc 2190 /* set the mode, clock divisor, parity, stop bits and data size */
4e7decda 2191 atmel_uart_writel(port, ATMEL_US_MR, mode);
1e6c9c28 2192
1cf6e8fc
CP		 2193 /*
2194 * when switching the mode, set the RTS line state according to the
2195 * new mode, otherwise keep the former state
2196 */
2197 if ((old_mode & ATMEL_US_USMODE) != (mode & ATMEL_US_USMODE)) {
2198 unsigned int rts_state;
2199
2200 if ((mode & ATMEL_US_USMODE) == ATMEL_US_USMODE_HWHS) {
2201 /* let the hardware control the RTS line */
2202 rts_state = ATMEL_US_RTSDIS;
2203 } else {
2204 /* force RTS line to low level */
2205 rts_state = ATMEL_US_RTSEN;
2206 }
2207
4e7decda 2208 atmel_uart_writel(port, ATMEL_US_CR, rts_state);
1cf6e8fc
CP		 2209 }
2210
5bf5635a
LD		 2211 /*
2212 * Set the baud rate:
2213 * Fractional baudrate allows to setup output frequency more
2214 * accurately. This feature is enabled only when using normal mode.
2215 * baudrate = selected clock / (8 * (2 - OVER) * (CD + FP / 8))
2216 * Currently, OVER is always set to 0 so we get
36131cdf
AS		 2217 * baudrate = selected clock / (16 * (CD + FP / 8))
2218 * then
2219 * 8 CD + FP = selected clock / (2 * baudrate)
5bf5635a 2220 */
2867af2d 2221 if (atmel_port->has_frac_baudrate) {
36131cdf
AS		 2222 div = DIV_ROUND_CLOSEST(port->uartclk, baud * 2);
2223 cd = div >> 3;
2224 fp = div & ATMEL_US_FP_MASK;
5bf5635a
LD		 2225 } else {
2226 cd = uart_get_divisor(port, baud);
2227 }
2228
2229 if (cd > 65535) { /* BRGR is 16-bit, so switch to slower clock */
2230 cd /= 8;
2231 mode |= ATMEL_US_USCLKS_MCK_DIV8;
2232 }
2233 quot = cd | fp << ATMEL_US_FP_OFFSET;
2234
4e7decda
CP		 2235 atmel_uart_writel(port, ATMEL_US_BRGR, quot);
2236 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
2237 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN);
1e6c9c28
AV		 2238
2239 /* restore interrupts */
4e7decda 2240 atmel_uart_writel(port, ATMEL_US_IER, imr);
1e6c9c28
AV		 2241
2242 /* CTS flow-control and modem-status interrupts */
2243 if (UART_ENABLE_MS(port, termios->c_cflag))
35b675b9
RG		 2244 atmel_enable_ms(port);
2245 else
2246 atmel_disable_ms(port);
1e6c9c28
AV		 2247
2248 spin_unlock_irqrestore(&port->lock, flags);
2249}
2250
732a84a0 2251static void atmel_set_ldisc(struct uart_port *port, struct ktermios *termios)
42bd7a4f 2252{
732a84a0 2253 if (termios->c_line == N_PPS) {
42bd7a4f 2254 port->flags |= UPF_HARDPPS_CD;
d41510ce 2255 spin_lock_irq(&port->lock);
42bd7a4f 2256 atmel_enable_ms(port);
d41510ce 2257 spin_unlock_irq(&port->lock);
42bd7a4f
VP		 2258 } else {
2259 port->flags &= ~UPF_HARDPPS_CD;
cab68f89
PH		 2260 if (!UART_ENABLE_MS(port, termios->c_cflag)) {
2261 spin_lock_irq(&port->lock);
2262 atmel_disable_ms(port);
2263 spin_unlock_irq(&port->lock);
2264 }
42bd7a4f
VP		 2265 }
2266}
2267
1e6c9c28
AV		 2268/*
2269 * Return string describing the specified port
2270 */
7192f92c 2271static const char *atmel_type(struct uart_port *port)
1e6c9c28 2272{
9ab4f88b 2273 return (port->type == PORT_ATMEL) ? "ATMEL_SERIAL" : NULL;
1e6c9c28
AV		 2274}
2275
2276/*
2277 * Release the memory region(s) being used by 'port'.
2278 */
7192f92c 2279static void atmel_release_port(struct uart_port *port)
1e6c9c28 2280{
afefc415
AV		 2281 struct platform_device *pdev = to_platform_device(port->dev);
2282 int size = pdev->resource[0].end - pdev->resource[0].start + 1;
2283
2284 release_mem_region(port->mapbase, size);
2285
2286 if (port->flags & UPF_IOREMAP) {
2287 iounmap(port->membase);
2288 port->membase = NULL;
2289 }
1e6c9c28
AV		 2290}
2291
2292/*
2293 * Request the memory region(s) being used by 'port'.
2294 */
7192f92c 2295static int atmel_request_port(struct uart_port *port)
1e6c9c28 2296{
afefc415
AV		 2297 struct platform_device *pdev = to_platform_device(port->dev);
2298 int size = pdev->resource[0].end - pdev->resource[0].start + 1;
2299
7192f92c 2300 if (!request_mem_region(port->mapbase, size, "atmel_serial"))
afefc415
AV		 2301 return -EBUSY;
2302
2303 if (port->flags & UPF_IOREMAP) {
2304 port->membase = ioremap(port->mapbase, size);
2305 if (port->membase == NULL) {
2306 release_mem_region(port->mapbase, size);
2307 return -ENOMEM;
2308 }
2309 }
1e6c9c28 2310
afefc415 2311 return 0;
1e6c9c28
AV		 2312}
2313
2314/*
2315 * Configure/autoconfigure the port.
2316 */
7192f92c 2317static void atmel_config_port(struct uart_port *port, int flags)
1e6c9c28
AV		 2318{
2319 if (flags & UART_CONFIG_TYPE) {
9ab4f88b 2320 port->type = PORT_ATMEL;
7192f92c 2321 atmel_request_port(port);
1e6c9c28
AV		 2322 }
2323}
2324
2325/*
2326 * Verify the new serial_struct (for TIOCSSERIAL).
2327 */
7192f92c 2328static int atmel_verify_port(struct uart_port *port, struct serial_struct *ser)
1e6c9c28
AV		 2329{
2330 int ret = 0;
9ab4f88b 2331 if (ser->type != PORT_UNKNOWN && ser->type != PORT_ATMEL)
1e6c9c28
AV		 2332 ret = -EINVAL;
2333 if (port->irq != ser->irq)
2334 ret = -EINVAL;
2335 if (ser->io_type != SERIAL_IO_MEM)
2336 ret = -EINVAL;
2337 if (port->uartclk / 16 != ser->baud_base)
2338 ret = -EINVAL;
270c2ade 2339 if (port->mapbase != (unsigned long)ser->iomem_base)
1e6c9c28
AV		 2340 ret = -EINVAL;
2341 if (port->iobase != ser->port)
2342 ret = -EINVAL;
2343 if (ser->hub6 != 0)
2344 ret = -EINVAL;
2345 return ret;
2346}
2347
8fe2d541
AT		 2348#ifdef CONFIG_CONSOLE_POLL
2349static int atmel_poll_get_char(struct uart_port *port)
2350{
4e7decda 2351 while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_RXRDY))
8fe2d541
AT		 2352 cpu_relax();
2353
a6499435 2354 return atmel_uart_read_char(port);
8fe2d541
AT		 2355}
2356
2357static void atmel_poll_put_char(struct uart_port *port, unsigned char ch)
2358{
4e7decda 2359 while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXRDY))
8fe2d541
AT		 2360 cpu_relax();
2361
a6499435 2362 atmel_uart_write_char(port, ch);
8fe2d541
AT		 2363}
2364#endif
2365
5c7dcdb6 2366static const struct uart_ops atmel_pops = {
7192f92c
HS		 2367 .tx_empty = atmel_tx_empty,
2368 .set_mctrl = atmel_set_mctrl,
2369 .get_mctrl = atmel_get_mctrl,
2370 .stop_tx = atmel_stop_tx,
2371 .start_tx = atmel_start_tx,
2372 .stop_rx = atmel_stop_rx,
2373 .enable_ms = atmel_enable_ms,
2374 .break_ctl = atmel_break_ctl,
2375 .startup = atmel_startup,
2376 .shutdown = atmel_shutdown,
9afd561a 2377 .flush_buffer = atmel_flush_buffer,
7192f92c 2378 .set_termios = atmel_set_termios,
42bd7a4f 2379 .set_ldisc = atmel_set_ldisc,
7192f92c
HS		 2380 .type = atmel_type,
2381 .release_port = atmel_release_port,
2382 .request_port = atmel_request_port,
2383 .config_port = atmel_config_port,
2384 .verify_port = atmel_verify_port,
2385 .pm = atmel_serial_pm,
8fe2d541
AT		 2386#ifdef CONFIG_CONSOLE_POLL
2387 .poll_get_char = atmel_poll_get_char,
2388 .poll_put_char = atmel_poll_put_char,
2389#endif
1e6c9c28
AV		 2390};
2391
afefc415
AV		 2392/*
2393 * Configure the port from the platform device resource info.
2394 */
91f8c2d8 2395static int atmel_init_port(struct atmel_uart_port *atmel_port,
b843aa21 2396 struct platform_device *pdev)
1e6c9c28 2397{
91f8c2d8 2398 int ret;
7192f92c 2399 struct uart_port *port = &atmel_port->uart;
574de559 2400 struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev);
afefc415 2401
4a1e8888
LZ		 2402 atmel_init_property(atmel_port, pdev);
2403 atmel_set_ops(port);
afefc415 2404
13bd3e6f 2405 atmel_init_rs485(port, pdev);
a930e528 2406
e8faff73
CS		 2407 port->iotype = UPIO_MEM;
2408 port->flags = UPF_BOOT_AUTOCONF;
2409 port->ops = &atmel_pops;
2410 port->fifosize = 1;
e8faff73 2411 port->dev = &pdev->dev;
afefc415
AV		 2412 port->mapbase = pdev->resource[0].start;
2413 port->irq = pdev->resource[1].start;
13bd3e6f 2414 port->rs485_config = atmel_config_rs485;
afefc415 2415
1ecc26bd
RB		 2416 memset(&atmel_port->rx_ring, 0, sizeof(atmel_port->rx_ring));
2417
5fbe46b6 2418 if (pdata && pdata->regs) {
75d35213 2419 /* Already mapped by setup code */
1acfc7ec 2420 port->membase = pdata->regs;
588edbf3 2421 } else {
afefc415
AV		 2422 port->flags |= UPF_IOREMAP;
2423 port->membase = NULL;
2424 }
1e6c9c28 2425
b843aa21
RB		 2426 /* for console, the clock could already be configured */
2427 if (!atmel_port->clk) {
7192f92c 2428 atmel_port->clk = clk_get(&pdev->dev, "usart");
91f8c2d8
BB		 2429 if (IS_ERR(atmel_port->clk)) {
2430 ret = PTR_ERR(atmel_port->clk);
2431 atmel_port->clk = NULL;
2432 return ret;
2433 }
2434 ret = clk_prepare_enable(atmel_port->clk);
2435 if (ret) {
2436 clk_put(atmel_port->clk);
2437 atmel_port->clk = NULL;
2438 return ret;
2439 }
7192f92c 2440 port->uartclk = clk_get_rate(atmel_port->clk);
91f8c2d8 2441 clk_disable_unprepare(atmel_port->clk);
06a7f058 2442 /* only enable clock when USART is in use */
afefc415 2443 }
a6670615 2444
e8faff73 2445 /* Use TXEMPTY for interrupt when rs485 else TXRDY or ENDTX|TXBUFE */
13bd3e6f 2446 if (port->rs485.flags & SER_RS485_ENABLED)
e8faff73 2447 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY;
64e22ebe 2448 else if (atmel_use_pdc_tx(port)) {
a6670615 2449 port->fifosize = PDC_BUFFER_SIZE;
e8faff73
CS		 2450 atmel_port->tx_done_mask = ATMEL_US_ENDTX | ATMEL_US_TXBUFE;
2451 } else {
2452 atmel_port->tx_done_mask = ATMEL_US_TXRDY;
2453 }
91f8c2d8
BB		 2454
2455 return 0;
1e6c9c28
AV		 2456}
2457
69f6a27b
JCPV		 2458struct platform_device *atmel_default_console_device; /* the serial console device */
2459
749c4e60 2460#ifdef CONFIG_SERIAL_ATMEL_CONSOLE
7192f92c 2461static void atmel_console_putchar(struct uart_port *port, int ch)
d358788f 2462{
4e7decda 2463 while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXRDY))
829dd811 2464 cpu_relax();
a6499435 2465 atmel_uart_write_char(port, ch);
d358788f 2466}
1e6c9c28
AV		 2467
2468/*
2469 * Interrupts are disabled on entering
2470 */
7192f92c 2471static void atmel_console_write(struct console *co, const char *s, u_int count)
1e6c9c28 2472{
7192f92c 2473 struct uart_port *port = &atmel_ports[co->index].uart;
e8faff73 2474 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
d358788f 2475 unsigned int status, imr;
39d4c922 2476 unsigned int pdc_tx;
1e6c9c28
AV		 2477
2478 /*
b843aa21 2479 * First, save IMR and then disable interrupts
1e6c9c28 2480 */
4e7decda
CP		 2481 imr = atmel_uart_readl(port, ATMEL_US_IMR);
2482 atmel_uart_writel(port, ATMEL_US_IDR,
2483 ATMEL_US_RXRDY | atmel_port->tx_done_mask);
1e6c9c28 2484
39d4c922 2485 /* Store PDC transmit status and disable it */
4e7decda
CP		 2486 pdc_tx = atmel_uart_readl(port, ATMEL_PDC_PTSR) & ATMEL_PDC_TXTEN;
2487 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS);
39d4c922 2488
7192f92c 2489 uart_console_write(port, s, count, atmel_console_putchar);
1e6c9c28
AV		 2490
2491 /*
b843aa21
RB		 2492 * Finally, wait for transmitter to become empty
2493 * and restore IMR
1e6c9c28
AV		 2494 */
2495 do {
4e7decda 2496 status = atmel_uart_readl(port, ATMEL_US_CSR);
7192f92c 2497 } while (!(status & ATMEL_US_TXRDY));
39d4c922
MP		 2498
2499 /* Restore PDC transmit status */
2500 if (pdc_tx)
4e7decda 2501 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
39d4c922 2502
b843aa21 2503 /* set interrupts back the way they were */
4e7decda 2504 atmel_uart_writel(port, ATMEL_US_IER, imr);
1e6c9c28
AV		 2505}
2506
2507/*
b843aa21
RB		 2508 * If the port was already initialised (eg, by a boot loader),
2509 * try to determine the current setup.
1e6c9c28 2510 */
b843aa21
RB		 2511static void __init atmel_console_get_options(struct uart_port *port, int *baud,
2512 int *parity, int *bits)
1e6c9c28
AV		 2513{
2514 unsigned int mr, quot;
2515
1c0fd82f
HS		 2516 /*
2517 * If the baud rate generator isn't running, the port wasn't
2518 * initialized by the boot loader.
2519 */
4e7decda 2520 quot = atmel_uart_readl(port, ATMEL_US_BRGR) & ATMEL_US_CD;
1c0fd82f
HS		 2521 if (!quot)
2522 return;
1e6c9c28 2523
4e7decda 2524 mr = atmel_uart_readl(port, ATMEL_US_MR) & ATMEL_US_CHRL;
7192f92c 2525 if (mr == ATMEL_US_CHRL_8)
1e6c9c28
AV		 2526 *bits = 8;
2527 else
2528 *bits = 7;
2529
4e7decda 2530 mr = atmel_uart_readl(port, ATMEL_US_MR) & ATMEL_US_PAR;
7192f92c 2531 if (mr == ATMEL_US_PAR_EVEN)
1e6c9c28 2532 *parity = 'e';
7192f92c 2533 else if (mr == ATMEL_US_PAR_ODD)
1e6c9c28
AV		 2534 *parity = 'o';
2535
4d5e392c
HS		 2536 /*
2537 * The serial core only rounds down when matching this to a
2538 * supported baud rate. Make sure we don't end up slightly
2539 * lower than one of those, as it would make us fall through
2540 * to a much lower baud rate than we really want.
2541 */
4d5e392c 2542 *baud = port->uartclk / (16 * (quot - 1));
1e6c9c28
AV		 2543}
2544
7192f92c 2545static int __init atmel_console_setup(struct console *co, char *options)
1e6c9c28 2546{
91f8c2d8 2547 int ret;
7192f92c 2548 struct uart_port *port = &atmel_ports[co->index].uart;
1e6c9c28
AV		 2549 int baud = 115200;
2550 int bits = 8;
2551 int parity = 'n';
2552 int flow = 'n';
2553
b843aa21
RB		 2554 if (port->membase == NULL) {
2555 /* Port not initialized yet - delay setup */
afefc415 2556 return -ENODEV;
b843aa21 2557 }
1e6c9c28 2558
91f8c2d8
BB		 2559 ret = clk_prepare_enable(atmel_ports[co->index].clk);
2560 if (ret)
2561 return ret;
06a7f058 2562
4e7decda
CP		 2563 atmel_uart_writel(port, ATMEL_US_IDR, -1);
2564 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
2565 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN);
1e6c9c28
AV		 2566
2567 if (options)
2568 uart_parse_options(options, &baud, &parity, &bits, &flow);
2569 else
7192f92c 2570 atmel_console_get_options(port, &baud, &parity, &bits);
1e6c9c28
AV		 2571
2572 return uart_set_options(port, co, baud, parity, bits, flow);
2573}
2574
7192f92c 2575static struct uart_driver atmel_uart;
1e6c9c28 2576
7192f92c
HS		 2577static struct console atmel_console = {
2578 .name = ATMEL_DEVICENAME,
2579 .write = atmel_console_write,
1e6c9c28 2580 .device = uart_console_device,
7192f92c 2581 .setup = atmel_console_setup,
1e6c9c28
AV		 2582 .flags = CON_PRINTBUFFER,
2583 .index = -1,
7192f92c 2584 .data = &atmel_uart,
1e6c9c28
AV		 2585};
2586
06a7f058 2587#define ATMEL_CONSOLE_DEVICE (&atmel_console)
1e6c9c28 2588
afefc415
AV		 2589/*
2590 * Early console initialization (before VM subsystem initialized).
2591 */
7192f92c 2592static int __init atmel_console_init(void)
1e6c9c28 2593{
91f8c2d8 2594 int ret;
73e2798b 2595 if (atmel_default_console_device) {
0d0a3cc1 2596 struct atmel_uart_data *pdata =
574de559 2597 dev_get_platdata(&atmel_default_console_device->dev);
efb8d21b 2598 int id = pdata->num;
b78cd169 2599 struct atmel_uart_port *atmel_port = &atmel_ports[id];
4cbf9f48 2600
b78cd169
JA		 2601 atmel_port->backup_imr = 0;
2602 atmel_port->uart.line = id;
0d0a3cc1 2603
4cbf9f48 2604 add_preferred_console(ATMEL_DEVICENAME, id, NULL);
b78cd169 2605 ret = atmel_init_port(atmel_port, atmel_default_console_device);
91f8c2d8
BB		 2606 if (ret)
2607 return ret;
7192f92c 2608 register_console(&atmel_console);
afefc415 2609 }
1e6c9c28 2610
1e6c9c28
AV		 2611 return 0;
2612}
b843aa21 2613
7192f92c 2614console_initcall(atmel_console_init);
1e6c9c28 2615
afefc415
AV		 2616/*
2617 * Late console initialization.
2618 */
7192f92c 2619static int __init atmel_late_console_init(void)
afefc415 2620{
b843aa21
RB		 2621 if (atmel_default_console_device
2622 && !(atmel_console.flags & CON_ENABLED))
7192f92c 2623 register_console(&atmel_console);
afefc415
AV		 2624
2625 return 0;
2626}
b843aa21 2627
7192f92c 2628core_initcall(atmel_late_console_init);
afefc415 2629
dfa7f343
HS		 2630static inline bool atmel_is_console_port(struct uart_port *port)
2631{
2632 return port->cons && port->cons->index == port->line;
2633}
2634
1e6c9c28 2635#else
7192f92c 2636#define ATMEL_CONSOLE_DEVICE NULL
dfa7f343
HS		 2637
2638static inline bool atmel_is_console_port(struct uart_port *port)
2639{
2640 return false;
2641}
1e6c9c28
AV		 2642#endif
2643
7192f92c 2644static struct uart_driver atmel_uart = {
b843aa21
RB		 2645 .owner = THIS_MODULE,
2646 .driver_name = "atmel_serial",
2647 .dev_name = ATMEL_DEVICENAME,
2648 .major = SERIAL_ATMEL_MAJOR,
2649 .minor = MINOR_START,
2650 .nr = ATMEL_MAX_UART,
2651 .cons = ATMEL_CONSOLE_DEVICE,
1e6c9c28
AV		 2652};
2653
afefc415 2654#ifdef CONFIG_PM
f826caa4
HS		 2655static bool atmel_serial_clk_will_stop(void)
2656{
2657#ifdef CONFIG_ARCH_AT91
2658 return at91_suspend_entering_slow_clock();
2659#else
2660 return false;
2661#endif
2662}
2663
b843aa21
RB		 2664static int atmel_serial_suspend(struct platform_device *pdev,
2665 pm_message_t state)
1e6c9c28 2666{
afefc415 2667 struct uart_port *port = platform_get_drvdata(pdev);
c811ab8c 2668 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
afefc415 2669
e1c609ef
HS		 2670 if (atmel_is_console_port(port) && console_suspend_enabled) {
2671 /* Drain the TX shifter */
4e7decda
CP		 2672 while (!(atmel_uart_readl(port, ATMEL_US_CSR) &
2673 ATMEL_US_TXEMPTY))
e1c609ef
HS		 2674 cpu_relax();
2675 }
2676
6a5f0e2f
AB		 2677 if (atmel_is_console_port(port) && !console_suspend_enabled) {
2678 /* Cache register values as we won't get a full shutdown/startup
2679 * cycle
2680 */
2681 atmel_port->cache.mr = atmel_uart_readl(port, ATMEL_US_MR);
2682 atmel_port->cache.imr = atmel_uart_readl(port, ATMEL_US_IMR);
2683 atmel_port->cache.brgr = atmel_uart_readl(port, ATMEL_US_BRGR);
2684 atmel_port->cache.rtor = atmel_uart_readl(port,
2685 atmel_port->rtor);
2686 atmel_port->cache.ttgr = atmel_uart_readl(port, ATMEL_US_TTGR);
2687 atmel_port->cache.fmr = atmel_uart_readl(port, ATMEL_US_FMR);
2688 atmel_port->cache.fimr = atmel_uart_readl(port, ATMEL_US_FIMR);
2689 }
2690
f05596db
AS		 2691 /* we can not wake up if we're running on slow clock */
2692 atmel_port->may_wakeup = device_may_wakeup(&pdev->dev);
2c7af5ba
BB		 2693 if (atmel_serial_clk_will_stop()) {
2694 unsigned long flags;
2695
2696 spin_lock_irqsave(&atmel_port->lock_suspended, flags);
2697 atmel_port->suspended = true;
2698 spin_unlock_irqrestore(&atmel_port->lock_suspended, flags);
f05596db 2699 device_set_wakeup_enable(&pdev->dev, 0);
2c7af5ba 2700 }
f05596db
AS		 2701
2702 uart_suspend_port(&atmel_uart, port);
1e6c9c28 2703
afefc415
AV		 2704 return 0;
2705}
1e6c9c28 2706
7192f92c 2707static int atmel_serial_resume(struct platform_device *pdev)
afefc415
AV		 2708{
2709 struct uart_port *port = platform_get_drvdata(pdev);
c811ab8c 2710 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2c7af5ba
BB		 2711 unsigned long flags;
2712
6a5f0e2f
AB		 2713 if (atmel_is_console_port(port) && !console_suspend_enabled) {
2714 atmel_uart_writel(port, ATMEL_US_MR, atmel_port->cache.mr);
2715 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->cache.imr);
2716 atmel_uart_writel(port, ATMEL_US_BRGR, atmel_port->cache.brgr);
2717 atmel_uart_writel(port, atmel_port->rtor,
2718 atmel_port->cache.rtor);
2719 atmel_uart_writel(port, ATMEL_US_TTGR, atmel_port->cache.ttgr);
2720
2721 if (atmel_port->fifo_size) {
2722 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_FIFOEN |
2723 ATMEL_US_RXFCLR | ATMEL_US_TXFLCLR);
2724 atmel_uart_writel(port, ATMEL_US_FMR,
2725 atmel_port->cache.fmr);
2726 atmel_uart_writel(port, ATMEL_US_FIER,
2727 atmel_port->cache.fimr);
2728 }
2729 atmel_start_rx(port);
2730 }
2731
2c7af5ba
BB		 2732 spin_lock_irqsave(&atmel_port->lock_suspended, flags);
2733 if (atmel_port->pending) {
2734 atmel_handle_receive(port, atmel_port->pending);
2735 atmel_handle_status(port, atmel_port->pending,
2736 atmel_port->pending_status);
2737 atmel_handle_transmit(port, atmel_port->pending);
2738 atmel_port->pending = 0;
2739 }
2740 atmel_port->suspended = false;
2741 spin_unlock_irqrestore(&atmel_port->lock_suspended, flags);
1e6c9c28 2742
f05596db
AS		 2743 uart_resume_port(&atmel_uart, port);
2744 device_set_wakeup_enable(&pdev->dev, atmel_port->may_wakeup);
1e6c9c28
AV		 2745
2746 return 0;
2747}
afefc415 2748#else
7192f92c
HS		 2749#define atmel_serial_suspend NULL
2750#define atmel_serial_resume NULL
afefc415 2751#endif
1e6c9c28 2752
b78cd169 2753static void atmel_serial_probe_fifos(struct atmel_uart_port *atmel_port,
b5199d46
CP		 2754 struct platform_device *pdev)
2755{
b78cd169
JA		 2756 atmel_port->fifo_size = 0;
2757 atmel_port->rts_low = 0;
2758 atmel_port->rts_high = 0;
b5199d46
CP		 2759
2760 if (of_property_read_u32(pdev->dev.of_node,
2761 "atmel,fifo-size",
b78cd169 2762 &atmel_port->fifo_size))
b5199d46
CP		 2763 return;
2764
b78cd169 2765 if (!atmel_port->fifo_size)
b5199d46
CP		 2766 return;
2767
b78cd169
JA		 2768 if (atmel_port->fifo_size < ATMEL_MIN_FIFO_SIZE) {
2769 atmel_port->fifo_size = 0;
b5199d46
CP		 2770 dev_err(&pdev->dev, "Invalid FIFO size\n");
2771 return;
2772 }
2773
2774 /*
2775 * 0 <= rts_low <= rts_high <= fifo_size
2776 * Once their CTS line asserted by the remote peer, some x86 UARTs tend
2777 * to flush their internal TX FIFO, commonly up to 16 data, before
2778 * actually stopping to send new data. So we try to set the RTS High
2779 * Threshold to a reasonably high value respecting this 16 data
2780 * empirical rule when possible.
2781 */
b78cd169
JA		 2782 atmel_port->rts_high = max_t(int, atmel_port->fifo_size >> 1,
2783 atmel_port->fifo_size - ATMEL_RTS_HIGH_OFFSET);
2784 atmel_port->rts_low = max_t(int, atmel_port->fifo_size >> 2,
2785 atmel_port->fifo_size - ATMEL_RTS_LOW_OFFSET);
b5199d46
CP		 2786
2787 dev_info(&pdev->dev, "Using FIFO (%u data)\n",
b78cd169 2788 atmel_port->fifo_size);
b5199d46 2789 dev_dbg(&pdev->dev, "RTS High Threshold : %2u data\n",
b78cd169 2790 atmel_port->rts_high);
b5199d46 2791 dev_dbg(&pdev->dev, "RTS Low Threshold : %2u data\n",
b78cd169 2792 atmel_port->rts_low);
b5199d46
CP		 2793}
2794
9671f099 2795static int atmel_serial_probe(struct platform_device *pdev)
1e6c9c28 2796{
b78cd169 2797 struct atmel_uart_port *atmel_port;
5fbe46b6 2798 struct device_node *np = pdev->dev.of_node;
574de559 2799 struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev);
1ecc26bd 2800 void *data;
4cbf9f48 2801 int ret = -ENODEV;
bd737f87 2802 bool rs485_enabled;
1e6c9c28 2803
9d09daf8 2804 BUILD_BUG_ON(ATMEL_SERIAL_RINGSIZE & (ATMEL_SERIAL_RINGSIZE - 1));
1ecc26bd 2805
5fbe46b6
NF		 2806 if (np)
2807 ret = of_alias_get_id(np, "serial");
2808 else
2809 if (pdata)
2810 ret = pdata->num;
4cbf9f48
NF		 2811
2812 if (ret < 0)
5fbe46b6 2813 /* port id not found in platform data nor device-tree aliases:
4cbf9f48 2814 * auto-enumerate it */
503bded9 2815 ret = find_first_zero_bit(atmel_ports_in_use, ATMEL_MAX_UART);
4cbf9f48 2816
503bded9 2817 if (ret >= ATMEL_MAX_UART) {
4cbf9f48
NF		 2818 ret = -ENODEV;
2819 goto err;
2820 }
2821
503bded9 2822 if (test_and_set_bit(ret, atmel_ports_in_use)) {
4cbf9f48
NF		 2823 /* port already in use */
2824 ret = -EBUSY;
2825 goto err;
2826 }
2827
b78cd169
JA		 2828 atmel_port = &atmel_ports[ret];
2829 atmel_port->backup_imr = 0;
2830 atmel_port->uart.line = ret;
2831 atmel_serial_probe_fifos(atmel_port, pdev);
e0b0baad 2832
98f2082c 2833 atomic_set(&atmel_port->tasklet_shutdown, 0);
b78cd169 2834 spin_lock_init(&atmel_port->lock_suspended);
2c7af5ba 2835
b78cd169 2836 ret = atmel_init_port(atmel_port, pdev);
91f8c2d8 2837 if (ret)
6fbb9bdf 2838 goto err_clear_bit;
1e6c9c28 2839
b78cd169
JA		 2840 atmel_port->gpios = mctrl_gpio_init(&atmel_port->uart, 0);
2841 if (IS_ERR(atmel_port->gpios)) {
2842 ret = PTR_ERR(atmel_port->gpios);
18dfef9c
UKK		 2843 goto err_clear_bit;
2844 }
2845
b78cd169 2846 if (!atmel_use_pdc_rx(&atmel_port->uart)) {
a6670615 2847 ret = -ENOMEM;
6433471d
HS		 2848 data = kmalloc(sizeof(struct atmel_uart_char)
2849 * ATMEL_SERIAL_RINGSIZE, GFP_KERNEL);
a6670615
CC		 2850 if (!data)
2851 goto err_alloc_ring;
b78cd169 2852 atmel_port->rx_ring.buf = data;
a6670615 2853 }
1ecc26bd 2854
b78cd169 2855 rs485_enabled = atmel_port->uart.rs485.flags & SER_RS485_ENABLED;
bd737f87 2856
b78cd169 2857 ret = uart_add_one_port(&atmel_uart, &atmel_port->uart);
dfa7f343
HS		 2858 if (ret)
2859 goto err_add_port;
2860
8da14b5f 2861#ifdef CONFIG_SERIAL_ATMEL_CONSOLE
b78cd169 2862 if (atmel_is_console_port(&atmel_port->uart)
06a7f058
DB		 2863 && ATMEL_CONSOLE_DEVICE->flags & CON_ENABLED) {
2864 /*
2865 * The serial core enabled the clock for us, so undo
91f8c2d8 2866 * the clk_prepare_enable() in atmel_console_setup()
06a7f058 2867 */
b78cd169 2868 clk_disable_unprepare(atmel_port->clk);
06a7f058 2869 }
8da14b5f 2870#endif
06a7f058 2871
dfa7f343 2872 device_init_wakeup(&pdev->dev, 1);
b78cd169 2873 platform_set_drvdata(pdev, atmel_port);
dfa7f343 2874
d4f64187
CP		 2875 /*
2876 * The peripheral clock has been disabled by atmel_init_port():
2877 * enable it before accessing I/O registers
2878 */
b78cd169 2879 clk_prepare_enable(atmel_port->clk);
d4f64187 2880
bd737f87 2881 if (rs485_enabled) {
b78cd169 2882 atmel_uart_writel(&atmel_port->uart, ATMEL_US_MR,
4e7decda 2883 ATMEL_US_USMODE_NORMAL);
b78cd169
JA		 2884 atmel_uart_writel(&atmel_port->uart, ATMEL_US_CR,
2885 ATMEL_US_RTSEN);
5dfbd1d7
CS		 2886 }
2887
055560b0
ES		 2888 /*
2889 * Get port name of usart or uart
2890 */
b78cd169 2891 atmel_get_ip_name(&atmel_port->uart);
055560b0 2892
d4f64187
CP		 2893 /*
2894 * The peripheral clock can now safely be disabled till the port
2895 * is used
2896 */
b78cd169 2897 clk_disable_unprepare(atmel_port->clk);
d4f64187 2898
dfa7f343
HS		 2899 return 0;
2900
2901err_add_port:
b78cd169
JA		 2902 kfree(atmel_port->rx_ring.buf);
2903 atmel_port->rx_ring.buf = NULL;
1ecc26bd 2904err_alloc_ring:
b78cd169
JA		 2905 if (!atmel_is_console_port(&atmel_port->uart)) {
2906 clk_put(atmel_port->clk);
2907 atmel_port->clk = NULL;
afefc415 2908 }
6fbb9bdf 2909err_clear_bit:
b78cd169 2910 clear_bit(atmel_port->uart.line, atmel_ports_in_use);
4cbf9f48 2911err:
afefc415
AV		 2912 return ret;
2913}
2914
f4a8ab04
RI		 2915/*
2916 * Even if the driver is not modular, it makes sense to be able to
2917 * unbind a device: there can be many bound devices, and there are
2918 * situations where dynamic binding and unbinding can be useful.
2919 *
2920 * For example, a connected device can require a specific firmware update
2921 * protocol that needs bitbanging on IO lines, but use the regular serial
2922 * port in the normal case.
2923 */
2924static int atmel_serial_remove(struct platform_device *pdev)
2925{
2926 struct uart_port *port = platform_get_drvdata(pdev);
2927 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2928 int ret = 0;
2929
00e8e658
NF		 2930 tasklet_kill(&atmel_port->tasklet_rx);
2931 tasklet_kill(&atmel_port->tasklet_tx);
f4a8ab04
RI		 2932
2933 device_init_wakeup(&pdev->dev, 0);
2934
2935 ret = uart_remove_one_port(&atmel_uart, port);
2936
2937 kfree(atmel_port->rx_ring.buf);
2938
2939 /* "port" is allocated statically, so we shouldn't free it */
2940
2941 clear_bit(port->line, atmel_ports_in_use);
2942
2943 clk_put(atmel_port->clk);
2944 atmel_port->clk = NULL;
2945
2946 return ret;
2947}
2948
7192f92c
HS		 2949static struct platform_driver atmel_serial_driver = {
2950 .probe = atmel_serial_probe,
f4a8ab04 2951 .remove = atmel_serial_remove,
7192f92c
HS		 2952 .suspend = atmel_serial_suspend,
2953 .resume = atmel_serial_resume,
afefc415 2954 .driver = {
c39dfebc
PG		 2955 .name = "atmel_usart",
2956 .of_match_table = of_match_ptr(atmel_serial_dt_ids),
afefc415
AV		 2957 },
2958};
2959
7192f92c 2960static int __init atmel_serial_init(void)
afefc415
AV		 2961{
2962 int ret;
2963
7192f92c 2964 ret = uart_register_driver(&atmel_uart);
afefc415
AV		 2965 if (ret)
2966 return ret;
2967
7192f92c 2968 ret = platform_driver_register(&atmel_serial_driver);
afefc415 2969 if (ret)
7192f92c 2970 uart_unregister_driver(&atmel_uart);
afefc415
AV		 2971
2972 return ret;
2973}
c39dfebc 2974device_initcall(atmel_serial_init);
Linux 6.x block layer and io_uring tree(s)