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tty: serial: atmel: Check return code of dmaengine_submit()
[linux-block.git] / drivers / tty / serial / atmel_serial.c
CommitLineData
e3b3d0f5 1// SPDX-License-Identifier: GPL-2.0+
1e6c9c28 2/*
72ce5732 3 * Driver for Atmel AT91 Serial ports
1e6c9c28
AV		 4 * Copyright (C) 2003 Rick Bronson
5 *
6 * Based on drivers/char/serial_sa1100.c, by Deep Blue Solutions Ltd.
7 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
8 *
a6670615 9 * DMA support added by Chip Coldwell.
1e6c9c28 10 */
1e6c9c28
AV		 11#include <linux/tty.h>
12#include <linux/ioport.h>
13#include <linux/slab.h>
14#include <linux/init.h>
15#include <linux/serial.h>
afefc415 16#include <linux/clk.h>
1e6c9c28
AV		 17#include <linux/console.h>
18#include <linux/sysrq.h>
19#include <linux/tty_flip.h>
afefc415 20#include <linux/platform_device.h>
5fbe46b6
NF		 21#include <linux/of.h>
22#include <linux/of_device.h>
a6670615 23#include <linux/dma-mapping.h>
6b997bab 24#include <linux/dmaengine.h>
93a3ddc2 25#include <linux/atmel_pdc.h>
e8faff73 26#include <linux/uaccess.h>
bcd2360c 27#include <linux/platform_data/atmel.h>
2e68c22f 28#include <linux/timer.h>
e0b0baad 29#include <linux/err.h>
ab5e4e41 30#include <linux/irq.h>
2c7af5ba 31#include <linux/suspend.h>
2b5cf14b 32#include <linux/mm.h>
635b2589 33#include <linux/io.h>
1e6c9c28 34
377fedd1 35#include <asm/div64.h>
f7512e7c 36#include <asm/ioctls.h>
1e6c9c28 37
a6670615
CC		 38#define PDC_BUFFER_SIZE 512
39/* Revisit: We should calculate this based on the actual port settings */
40#define PDC_RX_TIMEOUT (3 * 10) /* 3 bytes */
41
b5199d46
CP		 42/* The minium number of data FIFOs should be able to contain */
43#define ATMEL_MIN_FIFO_SIZE 8
44/*
45 * These two offsets are substracted from the RX FIFO size to define the RTS
46 * high and low thresholds
47 */
48#define ATMEL_RTS_HIGH_OFFSET 16
49#define ATMEL_RTS_LOW_OFFSET 20
50
1e6c9c28
AV		 51#include <linux/serial_core.h>
52
e0b0baad 53#include "serial_mctrl_gpio.h"
8961df89 54#include "atmel_serial.h"
e0b0baad 55
e8faff73
CS		 56static void atmel_start_rx(struct uart_port *port);
57static void atmel_stop_rx(struct uart_port *port);
58
749c4e60 59#ifdef CONFIG_SERIAL_ATMEL_TTYAT
1e6c9c28
AV		 60
61/* Use device name ttyAT, major 204 and minor 154-169. This is necessary if we
62 * should coexist with the 8250 driver, such as if we have an external 16C550
63 * UART. */
7192f92c 64#define SERIAL_ATMEL_MAJOR 204
1e6c9c28 65#define MINOR_START 154
7192f92c 66#define ATMEL_DEVICENAME "ttyAT"
1e6c9c28
AV		 67
68#else
69
70/* Use device name ttyS, major 4, minor 64-68. This is the usual serial port
71 * name, but it is legally reserved for the 8250 driver. */
7192f92c 72#define SERIAL_ATMEL_MAJOR TTY_MAJOR
1e6c9c28 73#define MINOR_START 64
7192f92c 74#define ATMEL_DEVICENAME "ttyS"
1e6c9c28
AV		 75
76#endif
77
7192f92c 78#define ATMEL_ISR_PASS_LIMIT 256
1e6c9c28 79
a6670615
CC		 80struct atmel_dma_buffer {
81 unsigned char *buf;
82 dma_addr_t dma_addr;
83 unsigned int dma_size;
84 unsigned int ofs;
85};
86
1ecc26bd
RB		 87struct atmel_uart_char {
88 u16 status;
89 u16 ch;
90};
91
637ba54f
LD		 92/*
93 * Be careful, the real size of the ring buffer is
94 * sizeof(atmel_uart_char) * ATMEL_SERIAL_RINGSIZE. It means that ring buffer
95 * can contain up to 1024 characters in PIO mode and up to 4096 characters in
96 * DMA mode.
97 */
1ecc26bd
RB		 98#define ATMEL_SERIAL_RINGSIZE 1024
99
9af92fbf
AB		 100/*
101 * at91: 6 USARTs and one DBGU port (SAM9260)
432f9748 102 * samx7: 3 USARTs and 5 UARTs
9af92fbf 103 */
432f9748 104#define ATMEL_MAX_UART 8
9af92fbf 105
afefc415
AV		 106/*
107 * We wrap our port structure around the generic uart_port.
108 */
7192f92c 109struct atmel_uart_port {
afefc415
AV		 110 struct uart_port uart; /* uart */
111 struct clk *clk; /* uart clock */
f05596db
AS		 112 int may_wakeup; /* cached value of device_may_wakeup for times we need to disable it */
113 u32 backup_imr; /* IMR saved during suspend */
9e6077bd 114 int break_active; /* break being received */
1ecc26bd 115
34df42f5 116 bool use_dma_rx; /* enable DMA receiver */
64e22ebe 117 bool use_pdc_rx; /* enable PDC receiver */
a6670615
CC		 118 short pdc_rx_idx; /* current PDC RX buffer */
119 struct atmel_dma_buffer pdc_rx[2]; /* PDC receier */
120
08f738be 121 bool use_dma_tx; /* enable DMA transmitter */
64e22ebe 122 bool use_pdc_tx; /* enable PDC transmitter */
a6670615
CC		 123 struct atmel_dma_buffer pdc_tx; /* PDC transmitter */
124
08f738be 125 spinlock_t lock_tx; /* port lock */
34df42f5 126 spinlock_t lock_rx; /* port lock */
08f738be 127 struct dma_chan *chan_tx;
34df42f5 128 struct dma_chan *chan_rx;
08f738be 129 struct dma_async_tx_descriptor *desc_tx;
34df42f5 130 struct dma_async_tx_descriptor *desc_rx;
08f738be 131 dma_cookie_t cookie_tx;
34df42f5 132 dma_cookie_t cookie_rx;
08f738be 133 struct scatterlist sg_tx;
34df42f5 134 struct scatterlist sg_rx;
00e8e658
NF		 135 struct tasklet_struct tasklet_rx;
136 struct tasklet_struct tasklet_tx;
98f2082c 137 atomic_t tasklet_shutdown;
1ecc26bd 138 unsigned int irq_status_prev;
5f258b3e 139 unsigned int tx_len;
1ecc26bd
RB		 140
141 struct circ_buf rx_ring;
e8faff73 142
e0b0baad 143 struct mctrl_gpios *gpios;
377fedd1
NF		 144 u32 backup_mode; /* MR saved during iso7816 operations */
145 u32 backup_brgr; /* BRGR saved during iso7816 operations */
e8faff73 146 unsigned int tx_done_mask;
b5199d46
CP		 147 u32 fifo_size;
148 u32 rts_high;
149 u32 rts_low;
ab5e4e41 150 bool ms_irq_enabled;
2958ccee 151 u32 rtor; /* address of receiver timeout register if it exists */
5bf5635a 152 bool has_frac_baudrate;
4b769371
NF		 153 bool has_hw_timer;
154 struct timer_list uart_timer;
2c7af5ba 155
ea04f82a 156 bool tx_stopped;
2c7af5ba
BB		 157 bool suspended;
158 unsigned int pending;
159 unsigned int pending_status;
160 spinlock_t lock_suspended;
161
69646d7a
RS		 162 bool hd_start_rx; /* can start RX during half-duplex operation */
163
377fedd1
NF		 164 /* ISO7816 */
165 unsigned int fidi_min;
166 unsigned int fidi_max;
167
488ae82d 168#ifdef CONFIG_PM
6a5f0e2f
AB		 169 struct {
170 u32 cr;
171 u32 mr;
172 u32 imr;
173 u32 brgr;
174 u32 rtor;
175 u32 ttgr;
176 u32 fmr;
177 u32 fimr;
178 } cache;
488ae82d 179#endif
6a5f0e2f 180
a930e528
ES		 181 int (*prepare_rx)(struct uart_port *port);
182 int (*prepare_tx)(struct uart_port *port);
183 void (*schedule_rx)(struct uart_port *port);
184 void (*schedule_tx)(struct uart_port *port);
185 void (*release_rx)(struct uart_port *port);
186 void (*release_tx)(struct uart_port *port);
afefc415
AV		 187};
188
7192f92c 189static struct atmel_uart_port atmel_ports[ATMEL_MAX_UART];
503bded9 190static DECLARE_BITMAP(atmel_ports_in_use, ATMEL_MAX_UART);
afefc415 191
5fbe46b6
NF		 192#if defined(CONFIG_OF)
193static const struct of_device_id atmel_serial_dt_ids[] = {
c24d2531 194 { .compatible = "atmel,at91rm9200-usart-serial" },
5fbe46b6
NF		 195 { /* sentinel */ }
196};
5fbe46b6
NF		 197#endif
198
c811ab8c
HS		 199static inline struct atmel_uart_port *
200to_atmel_uart_port(struct uart_port *uart)
201{
202 return container_of(uart, struct atmel_uart_port, uart);
203}
204
4e7decda
CP		 205static inline u32 atmel_uart_readl(struct uart_port *port, u32 reg)
206{
207 return __raw_readl(port->membase + reg);
208}
209
210static inline void atmel_uart_writel(struct uart_port *port, u32 reg, u32 value)
211{
212 __raw_writel(value, port->membase + reg);
213}
214
a6499435 215static inline u8 atmel_uart_read_char(struct uart_port *port)
b5199d46 216{
a6499435 217 return __raw_readb(port->membase + ATMEL_US_RHR);
b5199d46
CP		 218}
219
a6499435
CP		 220static inline void atmel_uart_write_char(struct uart_port *port, u8 value)
221{
222 __raw_writeb(value, port->membase + ATMEL_US_THR);
223}
224
f3040983
RS		 225static inline int atmel_uart_is_half_duplex(struct uart_port *port)
226{
227 return ((port->rs485.flags & SER_RS485_ENABLED) &&
228 !(port->rs485.flags & SER_RS485_RX_DURING_TX)) ||
229 (port->iso7816.flags & SER_ISO7816_ENABLED);
230}
231
a6670615 232#ifdef CONFIG_SERIAL_ATMEL_PDC
64e22ebe 233static bool atmel_use_pdc_rx(struct uart_port *port)
a6670615 234{
c811ab8c 235 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
a6670615 236
64e22ebe 237 return atmel_port->use_pdc_rx;
a6670615
CC		 238}
239
64e22ebe 240static bool atmel_use_pdc_tx(struct uart_port *port)
a6670615 241{
c811ab8c 242 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
a6670615 243
64e22ebe 244 return atmel_port->use_pdc_tx;
a6670615
CC		 245}
246#else
64e22ebe 247static bool atmel_use_pdc_rx(struct uart_port *port)
a6670615
CC		 248{
249 return false;
250}
251
64e22ebe 252static bool atmel_use_pdc_tx(struct uart_port *port)
a6670615
CC		 253{
254 return false;
255}
256#endif
257
08f738be
ES		 258static bool atmel_use_dma_tx(struct uart_port *port)
259{
260 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
261
262 return atmel_port->use_dma_tx;
263}
264
34df42f5
ES		 265static bool atmel_use_dma_rx(struct uart_port *port)
266{
267 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
268
269 return atmel_port->use_dma_rx;
270}
271
5be605ac
AB		 272static bool atmel_use_fifo(struct uart_port *port)
273{
274 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
275
276 return atmel_port->fifo_size;
277}
278
98f2082c
NF		 279static void atmel_tasklet_schedule(struct atmel_uart_port *atmel_port,
280 struct tasklet_struct *t)
281{
282 if (!atomic_read(&atmel_port->tasklet_shutdown))
283 tasklet_schedule(t);
284}
285
e8faff73 286/* Enable or disable the rs485 support */
13bd3e6f
RRD		 287static int atmel_config_rs485(struct uart_port *port,
288 struct serial_rs485 *rs485conf)
e8faff73
CS		 289{
290 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
291 unsigned int mode;
e8faff73
CS		 292
293 /* Disable interrupts */
4e7decda 294 atmel_uart_writel(port, ATMEL_US_IDR, atmel_port->tx_done_mask);
e8faff73 295
4e7decda 296 mode = atmel_uart_readl(port, ATMEL_US_MR);
e8faff73
CS		 297
298 /* Resetting serial mode to RS232 (0x0) */
299 mode &= ~ATMEL_US_USMODE;
300
13bd3e6f 301 port->rs485 = *rs485conf;
e8faff73
CS		 302
303 if (rs485conf->flags & SER_RS485_ENABLED) {
304 dev_dbg(port->dev, "Setting UART to RS485\n");
477b8383
CC		 305 if (port->rs485.flags & SER_RS485_RX_DURING_TX)
306 atmel_port->tx_done_mask = ATMEL_US_TXRDY;
307 else
308 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY;
309
4e7decda
CP		 310 atmel_uart_writel(port, ATMEL_US_TTGR,
311 rs485conf->delay_rts_after_send);
e8faff73
CS		 312 mode |= ATMEL_US_USMODE_RS485;
313 } else {
314 dev_dbg(port->dev, "Setting UART to RS232\n");
64e22ebe 315 if (atmel_use_pdc_tx(port))
e8faff73
CS		 316 atmel_port->tx_done_mask = ATMEL_US_ENDTX |
317 ATMEL_US_TXBUFE;
318 else
319 atmel_port->tx_done_mask = ATMEL_US_TXRDY;
320 }
4e7decda 321 atmel_uart_writel(port, ATMEL_US_MR, mode);
e8faff73
CS		 322
323 /* Enable interrupts */
4e7decda 324 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->tx_done_mask);
e8faff73 325
13bd3e6f 326 return 0;
e8faff73
CS		 327}
328
377fedd1
NF		 329static unsigned int atmel_calc_cd(struct uart_port *port,
330 struct serial_iso7816 *iso7816conf)
331{
332 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
333 unsigned int cd;
334 u64 mck_rate;
335
336 mck_rate = (u64)clk_get_rate(atmel_port->clk);
337 do_div(mck_rate, iso7816conf->clk);
338 cd = mck_rate;
339 return cd;
340}
341
342static unsigned int atmel_calc_fidi(struct uart_port *port,
343 struct serial_iso7816 *iso7816conf)
344{
345 u64 fidi = 0;
346
347 if (iso7816conf->sc_fi && iso7816conf->sc_di) {
348 fidi = (u64)iso7816conf->sc_fi;
349 do_div(fidi, iso7816conf->sc_di);
350 }
351 return (u32)fidi;
352}
353
354/* Enable or disable the iso7816 support */
355/* Called with interrupts disabled */
356static int atmel_config_iso7816(struct uart_port *port,
357 struct serial_iso7816 *iso7816conf)
358{
359 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
360 unsigned int mode;
361 unsigned int cd, fidi;
362 int ret = 0;
363
364 /* Disable interrupts */
365 atmel_uart_writel(port, ATMEL_US_IDR, atmel_port->tx_done_mask);
366
367 mode = atmel_uart_readl(port, ATMEL_US_MR);
368
369 if (iso7816conf->flags & SER_ISO7816_ENABLED) {
370 mode &= ~ATMEL_US_USMODE;
371
372 if (iso7816conf->tg > 255) {
373 dev_err(port->dev, "ISO7816: Timeguard exceeding 255\n");
374 memset(iso7816conf, 0, sizeof(struct serial_iso7816));
375 ret = -EINVAL;
376 goto err_out;
377 }
378
379 if ((iso7816conf->flags & SER_ISO7816_T_PARAM)
380 == SER_ISO7816_T(0)) {
381 mode |= ATMEL_US_USMODE_ISO7816_T0 | ATMEL_US_DSNACK;
382 } else if ((iso7816conf->flags & SER_ISO7816_T_PARAM)
383 == SER_ISO7816_T(1)) {
384 mode |= ATMEL_US_USMODE_ISO7816_T1 | ATMEL_US_INACK;
385 } else {
386 dev_err(port->dev, "ISO7816: Type not supported\n");
387 memset(iso7816conf, 0, sizeof(struct serial_iso7816));
388 ret = -EINVAL;
389 goto err_out;
390 }
391
392 mode &= ~(ATMEL_US_USCLKS | ATMEL_US_NBSTOP | ATMEL_US_PAR);
393
394 /* select mck clock, and output */
395 mode |= ATMEL_US_USCLKS_MCK | ATMEL_US_CLKO;
396 /* set parity for normal/inverse mode + max iterations */
397 mode |= ATMEL_US_PAR_EVEN | ATMEL_US_NBSTOP_1 | ATMEL_US_MAX_ITER(3);
398
399 cd = atmel_calc_cd(port, iso7816conf);
400 fidi = atmel_calc_fidi(port, iso7816conf);
401 if (fidi == 0) {
402 dev_warn(port->dev, "ISO7816 fidi = 0, Generator generates no signal\n");
403 } else if (fidi < atmel_port->fidi_min
404 || fidi > atmel_port->fidi_max) {
405 dev_err(port->dev, "ISO7816 fidi = %u, value not supported\n", fidi);
406 memset(iso7816conf, 0, sizeof(struct serial_iso7816));
407 ret = -EINVAL;
408 goto err_out;
409 }
410
411 if (!(port->iso7816.flags & SER_ISO7816_ENABLED)) {
412 /* port not yet in iso7816 mode: store configuration */
413 atmel_port->backup_mode = atmel_uart_readl(port, ATMEL_US_MR);
414 atmel_port->backup_brgr = atmel_uart_readl(port, ATMEL_US_BRGR);
415 }
416
417 atmel_uart_writel(port, ATMEL_US_TTGR, iso7816conf->tg);
418 atmel_uart_writel(port, ATMEL_US_BRGR, cd);
419 atmel_uart_writel(port, ATMEL_US_FIDI, fidi);
420
421 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXDIS | ATMEL_US_RXEN);
422 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY | ATMEL_US_NACK | ATMEL_US_ITERATION;
423 } else {
424 dev_dbg(port->dev, "Setting UART back to RS232\n");
425 /* back to last RS232 settings */
426 mode = atmel_port->backup_mode;
427 memset(iso7816conf, 0, sizeof(struct serial_iso7816));
428 atmel_uart_writel(port, ATMEL_US_TTGR, 0);
429 atmel_uart_writel(port, ATMEL_US_BRGR, atmel_port->backup_brgr);
430 atmel_uart_writel(port, ATMEL_US_FIDI, 0x174);
431
432 if (atmel_use_pdc_tx(port))
433 atmel_port->tx_done_mask = ATMEL_US_ENDTX |
434 ATMEL_US_TXBUFE;
435 else
436 atmel_port->tx_done_mask = ATMEL_US_TXRDY;
437 }
438
439 port->iso7816 = *iso7816conf;
440
441 atmel_uart_writel(port, ATMEL_US_MR, mode);
442
443err_out:
444 /* Enable interrupts */
445 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->tx_done_mask);
446
447 return ret;
448}
449
1e6c9c28
AV		 450/*
451 * Return TIOCSER_TEMT when transmitter FIFO and Shift register is empty.
452 */
7192f92c 453static u_int atmel_tx_empty(struct uart_port *port)
1e6c9c28 454{
ea04f82a
RI		 455 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
456
457 if (atmel_port->tx_stopped)
458 return TIOCSER_TEMT;
4e7decda
CP		 459 return (atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXEMPTY) ?
460 TIOCSER_TEMT :
461 0;
1e6c9c28
AV		 462}
463
464/*
465 * Set state of the modem control output lines
466 */
7192f92c 467static void atmel_set_mctrl(struct uart_port *port, u_int mctrl)
1e6c9c28
AV		 468{
469 unsigned int control = 0;
4e7decda 470 unsigned int mode = atmel_uart_readl(port, ATMEL_US_MR);
1cf6e8fc 471 unsigned int rts_paused, rts_ready;
e8faff73 472 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1e6c9c28 473
1cf6e8fc
CP		 474 /* override mode to RS485 if needed, otherwise keep the current mode */
475 if (port->rs485.flags & SER_RS485_ENABLED) {
4e7decda
CP		 476 atmel_uart_writel(port, ATMEL_US_TTGR,
477 port->rs485.delay_rts_after_send);
1cf6e8fc
CP		 478 mode &= ~ATMEL_US_USMODE;
479 mode |= ATMEL_US_USMODE_RS485;
480 }
481
482 /* set the RTS line state according to the mode */
483 if ((mode & ATMEL_US_USMODE) == ATMEL_US_USMODE_HWHS) {
484 /* force RTS line to high level */
485 rts_paused = ATMEL_US_RTSEN;
486
487 /* give the control of the RTS line back to the hardware */
488 rts_ready = ATMEL_US_RTSDIS;
489 } else {
490 /* force RTS line to high level */
491 rts_paused = ATMEL_US_RTSDIS;
492
493 /* force RTS line to low level */
494 rts_ready = ATMEL_US_RTSEN;
495 }
496
1e6c9c28 497 if (mctrl & TIOCM_RTS)
1cf6e8fc 498 control |= rts_ready;
1e6c9c28 499 else
1cf6e8fc 500 control |= rts_paused;
1e6c9c28
AV		 501
502 if (mctrl & TIOCM_DTR)
7192f92c 503 control |= ATMEL_US_DTREN;
1e6c9c28 504 else
7192f92c 505 control |= ATMEL_US_DTRDIS;
1e6c9c28 506
4e7decda 507 atmel_uart_writel(port, ATMEL_US_CR, control);
afefc415 508
e0b0baad
RG		 509 mctrl_gpio_set(atmel_port->gpios, mctrl);
510
afefc415 511 /* Local loopback mode? */
1cf6e8fc 512 mode &= ~ATMEL_US_CHMODE;
afefc415 513 if (mctrl & TIOCM_LOOP)
7192f92c 514 mode |= ATMEL_US_CHMODE_LOC_LOOP;
afefc415 515 else
7192f92c 516 mode |= ATMEL_US_CHMODE_NORMAL;
e8faff73 517
4e7decda 518 atmel_uart_writel(port, ATMEL_US_MR, mode);
1e6c9c28
AV		 519}
520
521/*
522 * Get state of the modem control input lines
523 */
7192f92c 524static u_int atmel_get_mctrl(struct uart_port *port)
1e6c9c28 525{
e0b0baad
RG		 526 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
527 unsigned int ret = 0, status;
1e6c9c28 528
4e7decda 529 status = atmel_uart_readl(port, ATMEL_US_CSR);
1e6c9c28
AV		 530
531 /*
532 * The control signals are active low.
533 */
7192f92c 534 if (!(status & ATMEL_US_DCD))
1e6c9c28 535 ret |= TIOCM_CD;
7192f92c 536 if (!(status & ATMEL_US_CTS))
1e6c9c28 537 ret |= TIOCM_CTS;
7192f92c 538 if (!(status & ATMEL_US_DSR))
1e6c9c28 539 ret |= TIOCM_DSR;
7192f92c 540 if (!(status & ATMEL_US_RI))
1e6c9c28
AV		 541 ret |= TIOCM_RI;
542
e0b0baad 543 return mctrl_gpio_get(atmel_port->gpios, &ret);
1e6c9c28
AV		 544}
545
546/*
547 * Stop transmitting.
548 */
7192f92c 549static void atmel_stop_tx(struct uart_port *port)
1e6c9c28 550{
e8faff73
CS		 551 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
552
64e22ebe 553 if (atmel_use_pdc_tx(port)) {
a6670615 554 /* disable PDC transmit */
4e7decda 555 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS);
e8faff73 556 }
89d82324
RG		 557
558 /*
559 * Disable the transmitter.
560 * This is mandatory when DMA is used, otherwise the DMA buffer
561 * is fully transmitted.
562 */
563 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXDIS);
ea04f82a 564 atmel_port->tx_stopped = true;
89d82324 565
e8faff73 566 /* Disable interrupts */
4e7decda 567 atmel_uart_writel(port, ATMEL_US_IDR, atmel_port->tx_done_mask);
e8faff73 568
f3040983 569 if (atmel_uart_is_half_duplex(port))
04b5bfe3
NF		 570 if (!atomic_read(&atmel_port->tasklet_shutdown))
571 atmel_start_rx(port);
f3040983 572
1e6c9c28
AV		 573}
574
575/*
576 * Start transmitting.
577 */
7192f92c 578static void atmel_start_tx(struct uart_port *port)
1e6c9c28 579{
e8faff73
CS		 580 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
581
0058f087
AB		 582 if (atmel_use_pdc_tx(port) && (atmel_uart_readl(port, ATMEL_PDC_PTSR)
583 & ATMEL_PDC_TXTEN))
584 /* The transmitter is already running. Yes, we
585 really need this.*/
586 return;
a6670615 587
0058f087 588 if (atmel_use_pdc_tx(port) || atmel_use_dma_tx(port))
f3040983 589 if (atmel_uart_is_half_duplex(port))
e8faff73
CS		 590 atmel_stop_rx(port);
591
0058f087 592 if (atmel_use_pdc_tx(port))
a6670615 593 /* re-enable PDC transmit */
4e7decda 594 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
0058f087 595
e8faff73 596 /* Enable interrupts */
4e7decda 597 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->tx_done_mask);
89d82324
RG		 598
599 /* re-enable the transmitter */
600 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN);
ea04f82a 601 atmel_port->tx_stopped = false;
e8faff73
CS		 602}
603
604/*
605 * start receiving - port is in process of being opened.
606 */
607static void atmel_start_rx(struct uart_port *port)
608{
4e7decda
CP		 609 /* reset status and receiver */
610 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
e8faff73 611
4e7decda 612 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RXEN);
57c36868 613
64e22ebe 614 if (atmel_use_pdc_rx(port)) {
e8faff73 615 /* enable PDC controller */
4e7decda
CP		 616 atmel_uart_writel(port, ATMEL_US_IER,
617 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT |
618 port->read_status_mask);
619 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN);
e8faff73 620 } else {
4e7decda 621 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_RXRDY);
e8faff73 622 }
1e6c9c28
AV		 623}
624
625/*
626 * Stop receiving - port is in process of being closed.
627 */
7192f92c 628static void atmel_stop_rx(struct uart_port *port)
1e6c9c28 629{
4e7decda 630 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RXDIS);
57c36868 631
64e22ebe 632 if (atmel_use_pdc_rx(port)) {
a6670615 633 /* disable PDC receive */
4e7decda
CP		 634 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS);
635 atmel_uart_writel(port, ATMEL_US_IDR,
636 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT |
637 port->read_status_mask);
e8faff73 638 } else {
4e7decda 639 atmel_uart_writel(port, ATMEL_US_IDR, ATMEL_US_RXRDY);
e8faff73 640 }
1e6c9c28
AV		 641}
642
643/*
644 * Enable modem status interrupts
645 */
7192f92c 646static void atmel_enable_ms(struct uart_port *port)
1e6c9c28 647{
ab5e4e41
RG		 648 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
649 uint32_t ier = 0;
650
651 /*
652 * Interrupt should not be enabled twice
653 */
654 if (atmel_port->ms_irq_enabled)
655 return;
656
657 atmel_port->ms_irq_enabled = true;
658
18dfef9c 659 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_CTS))
ab5e4e41
RG		 660 ier |= ATMEL_US_CTSIC;
661
18dfef9c 662 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DSR))
ab5e4e41
RG		 663 ier |= ATMEL_US_DSRIC;
664
18dfef9c 665 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_RI))
ab5e4e41
RG		 666 ier |= ATMEL_US_RIIC;
667
18dfef9c 668 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DCD))
ab5e4e41
RG		 669 ier |= ATMEL_US_DCDIC;
670
4e7decda 671 atmel_uart_writel(port, ATMEL_US_IER, ier);
18dfef9c
UKK		 672
673 mctrl_gpio_enable_ms(atmel_port->gpios);
1e6c9c28
AV		 674}
675
35b675b9
RG		 676/*
677 * Disable modem status interrupts
678 */
679static void atmel_disable_ms(struct uart_port *port)
680{
681 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
682 uint32_t idr = 0;
683
684 /*
685 * Interrupt should not be disabled twice
686 */
687 if (!atmel_port->ms_irq_enabled)
688 return;
689
690 atmel_port->ms_irq_enabled = false;
691
18dfef9c
UKK		 692 mctrl_gpio_disable_ms(atmel_port->gpios);
693
694 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_CTS))
35b675b9
RG		 695 idr |= ATMEL_US_CTSIC;
696
18dfef9c 697 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DSR))
35b675b9
RG		 698 idr |= ATMEL_US_DSRIC;
699
18dfef9c 700 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_RI))
35b675b9
RG		 701 idr |= ATMEL_US_RIIC;
702
18dfef9c 703 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DCD))
35b675b9
RG		 704 idr |= ATMEL_US_DCDIC;
705
4e7decda 706 atmel_uart_writel(port, ATMEL_US_IDR, idr);
35b675b9
RG		 707}
708
1e6c9c28
AV		 709/*
710 * Control the transmission of a break signal
711 */
7192f92c 712static void atmel_break_ctl(struct uart_port *port, int break_state)
1e6c9c28
AV		 713{
714 if (break_state != 0)
4e7decda
CP		 715 /* start break */
716 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTBRK);
1e6c9c28 717 else
4e7decda
CP		 718 /* stop break */
719 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STPBRK);
1e6c9c28
AV		 720}
721
1ecc26bd
RB		 722/*
723 * Stores the incoming character in the ring buffer
724 */
725static void
726atmel_buffer_rx_char(struct uart_port *port, unsigned int status,
727 unsigned int ch)
728{
c811ab8c 729 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1ecc26bd
RB		 730 struct circ_buf *ring = &atmel_port->rx_ring;
731 struct atmel_uart_char *c;
732
733 if (!CIRC_SPACE(ring->head, ring->tail, ATMEL_SERIAL_RINGSIZE))
734 /* Buffer overflow, ignore char */
735 return;
736
737 c = &((struct atmel_uart_char *)ring->buf)[ring->head];
738 c->status = status;
739 c->ch = ch;
740
741 /* Make sure the character is stored before we update head. */
742 smp_wmb();
743
744 ring->head = (ring->head + 1) & (ATMEL_SERIAL_RINGSIZE - 1);
745}
746
a6670615
CC		 747/*
748 * Deal with parity, framing and overrun errors.
749 */
750static void atmel_pdc_rxerr(struct uart_port *port, unsigned int status)
751{
752 /* clear error */
4e7decda 753 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
a6670615
CC		 754
755 if (status & ATMEL_US_RXBRK) {
756 /* ignore side-effect */
757 status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME);
758 port->icount.brk++;
759 }
760 if (status & ATMEL_US_PARE)
761 port->icount.parity++;
762 if (status & ATMEL_US_FRAME)
763 port->icount.frame++;
764 if (status & ATMEL_US_OVRE)
765 port->icount.overrun++;
766}
767
1e6c9c28
AV		 768/*
769 * Characters received (called from interrupt handler)
770 */
7d12e780 771static void atmel_rx_chars(struct uart_port *port)
1e6c9c28 772{
c811ab8c 773 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1ecc26bd 774 unsigned int status, ch;
1e6c9c28 775
4e7decda 776 status = atmel_uart_readl(port, ATMEL_US_CSR);
7192f92c 777 while (status & ATMEL_US_RXRDY) {
a6499435 778 ch = atmel_uart_read_char(port);
1e6c9c28 779
1e6c9c28
AV		 780 /*
781 * note that the error handling code is
782 * out of the main execution path
783 */
9e6077bd
HS		 784 if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME
785 | ATMEL_US_OVRE | ATMEL_US_RXBRK)
786 || atmel_port->break_active)) {
1ecc26bd 787
b843aa21 788 /* clear error */
4e7decda 789 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
1ecc26bd 790
9e6077bd
HS		 791 if (status & ATMEL_US_RXBRK
792 && !atmel_port->break_active) {
9e6077bd 793 atmel_port->break_active = 1;
4e7decda
CP		 794 atmel_uart_writel(port, ATMEL_US_IER,
795 ATMEL_US_RXBRK);
9e6077bd
HS		 796 } else {
797 /*
798 * This is either the end-of-break
799 * condition or we've received at
800 * least one character without RXBRK
801 * being set. In both cases, the next
802 * RXBRK will indicate start-of-break.
803 */
4e7decda
CP		 804 atmel_uart_writel(port, ATMEL_US_IDR,
805 ATMEL_US_RXBRK);
9e6077bd
HS		 806 status &= ~ATMEL_US_RXBRK;
807 atmel_port->break_active = 0;
afefc415 808 }
1e6c9c28
AV		 809 }
810
1ecc26bd 811 atmel_buffer_rx_char(port, status, ch);
4e7decda 812 status = atmel_uart_readl(port, ATMEL_US_CSR);
1e6c9c28
AV		 813 }
814
98f2082c 815 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_rx);
1e6c9c28
AV		 816}
817
818/*
1ecc26bd
RB		 819 * Transmit characters (called from tasklet with TXRDY interrupt
820 * disabled)
1e6c9c28 821 */
7192f92c 822static void atmel_tx_chars(struct uart_port *port)
1e6c9c28 823{
ebd2c8f6 824 struct circ_buf *xmit = &port->state->xmit;
e8faff73 825 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1e6c9c28 826
4e7decda 827 if (port->x_char &&
477b8383 828 (atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXRDY)) {
a6499435 829 atmel_uart_write_char(port, port->x_char);
1e6c9c28
AV		 830 port->icount.tx++;
831 port->x_char = 0;
1e6c9c28 832 }
1ecc26bd 833 if (uart_circ_empty(xmit) || uart_tx_stopped(port))
1e6c9c28 834 return;
1e6c9c28 835
477b8383 836 while (atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXRDY) {
a6499435 837 atmel_uart_write_char(port, xmit->buf[xmit->tail]);
1e6c9c28
AV		 838 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
839 port->icount.tx++;
840 if (uart_circ_empty(xmit))
841 break;
842 }
843
844 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
845 uart_write_wakeup(port);
846
477b8383
CC		 847 if (!uart_circ_empty(xmit)) {
848 /* we still have characters to transmit, so we should continue
849 * transmitting them when TX is ready, regardless of
850 * mode or duplexity
851 */
852 atmel_port->tx_done_mask |= ATMEL_US_TXRDY;
853
e8faff73 854 /* Enable interrupts */
4e7decda
CP		 855 atmel_uart_writel(port, ATMEL_US_IER,
856 atmel_port->tx_done_mask);
477b8383
CC		 857 } else {
858 if (atmel_uart_is_half_duplex(port))
859 atmel_port->tx_done_mask &= ~ATMEL_US_TXRDY;
860 }
1e6c9c28
AV		 861}
862
08f738be
ES		 863static void atmel_complete_tx_dma(void *arg)
864{
865 struct atmel_uart_port *atmel_port = arg;
866 struct uart_port *port = &atmel_port->uart;
867 struct circ_buf *xmit = &port->state->xmit;
868 struct dma_chan *chan = atmel_port->chan_tx;
869 unsigned long flags;
870
871 spin_lock_irqsave(&port->lock, flags);
872
873 if (chan)
874 dmaengine_terminate_all(chan);
5f258b3e 875 xmit->tail += atmel_port->tx_len;
08f738be
ES		 876 xmit->tail &= UART_XMIT_SIZE - 1;
877
5f258b3e 878 port->icount.tx += atmel_port->tx_len;
08f738be
ES		 879
880 spin_lock_irq(&atmel_port->lock_tx);
881 async_tx_ack(atmel_port->desc_tx);
882 atmel_port->cookie_tx = -EINVAL;
883 atmel_port->desc_tx = NULL;
884 spin_unlock_irq(&atmel_port->lock_tx);
885
886 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
887 uart_write_wakeup(port);
888
1842dc2e
CP		 889 /*
890 * xmit is a circular buffer so, if we have just send data from
891 * xmit->tail to the end of xmit->buf, now we have to transmit the
892 * remaining data from the beginning of xmit->buf to xmit->head.
893 */
08f738be 894 if (!uart_circ_empty(xmit))
98f2082c 895 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_tx);
f3040983 896 else if (atmel_uart_is_half_duplex(port)) {
69646d7a
RS		 897 /*
898 * DMA done, re-enable TXEMPTY and signal that we can stop
899 * TX and start RX for RS485
900 */
901 atmel_port->hd_start_rx = true;
902 atmel_uart_writel(port, ATMEL_US_IER,
903 atmel_port->tx_done_mask);
b389f173 904 }
08f738be
ES		 905
906 spin_unlock_irqrestore(&port->lock, flags);
907}
908
909static void atmel_release_tx_dma(struct uart_port *port)
910{
911 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
912 struct dma_chan *chan = atmel_port->chan_tx;
913
914 if (chan) {
915 dmaengine_terminate_all(chan);
916 dma_release_channel(chan);
917 dma_unmap_sg(port->dev, &atmel_port->sg_tx, 1,
48479148 918 DMA_TO_DEVICE);
08f738be
ES		 919 }
920
921 atmel_port->desc_tx = NULL;
922 atmel_port->chan_tx = NULL;
923 atmel_port->cookie_tx = -EINVAL;
924}
925
926/*
927 * Called from tasklet with TXRDY interrupt is disabled.
928 */
929static void atmel_tx_dma(struct uart_port *port)
930{
931 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
932 struct circ_buf *xmit = &port->state->xmit;
933 struct dma_chan *chan = atmel_port->chan_tx;
934 struct dma_async_tx_descriptor *desc;
5f258b3e
CP		 935 struct scatterlist sgl[2], *sg, *sg_tx = &atmel_port->sg_tx;
936 unsigned int tx_len, part1_len, part2_len, sg_len;
937 dma_addr_t phys_addr;
08f738be
ES		 938
939 /* Make sure we have an idle channel */
940 if (atmel_port->desc_tx != NULL)
941 return;
942
943 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) {
944 /*
945 * DMA is idle now.
946 * Port xmit buffer is already mapped,
947 * and it is one page... Just adjust
948 * offsets and lengths. Since it is a circular buffer,
949 * we have to transmit till the end, and then the rest.
950 * Take the port lock to get a
951 * consistent xmit buffer state.
952 */
5f258b3e
CP		 953 tx_len = CIRC_CNT_TO_END(xmit->head,
954 xmit->tail,
955 UART_XMIT_SIZE);
956
957 if (atmel_port->fifo_size) {
958 /* multi data mode */
959 part1_len = (tx_len & ~0x3); /* DWORD access */
960 part2_len = (tx_len & 0x3); /* BYTE access */
961 } else {
962 /* single data (legacy) mode */
963 part1_len = 0;
964 part2_len = tx_len; /* BYTE access only */
965 }
966
967 sg_init_table(sgl, 2);
968 sg_len = 0;
969 phys_addr = sg_dma_address(sg_tx) + xmit->tail;
970 if (part1_len) {
971 sg = &sgl[sg_len++];
972 sg_dma_address(sg) = phys_addr;
973 sg_dma_len(sg) = part1_len;
974
975 phys_addr += part1_len;
976 }
977
978 if (part2_len) {
979 sg = &sgl[sg_len++];
980 sg_dma_address(sg) = phys_addr;
981 sg_dma_len(sg) = part2_len;
982 }
983
984 /*
985 * save tx_len so atmel_complete_tx_dma() will increase
986 * xmit->tail correctly
987 */
988 atmel_port->tx_len = tx_len;
08f738be
ES		 989
990 desc = dmaengine_prep_slave_sg(chan,
5f258b3e
CP		 991 sgl,
992 sg_len,
1842dc2e
CP		 993 DMA_MEM_TO_DEV,
994 DMA_PREP_INTERRUPT |
995 DMA_CTRL_ACK);
08f738be
ES		 996 if (!desc) {
997 dev_err(port->dev, "Failed to send via dma!\n");
998 return;
999 }
1000
5f258b3e 1001 dma_sync_sg_for_device(port->dev, sg_tx, 1, DMA_TO_DEVICE);
08f738be
ES		 1002
1003 atmel_port->desc_tx = desc;
1004 desc->callback = atmel_complete_tx_dma;
1005 desc->callback_param = atmel_port;
1006 atmel_port->cookie_tx = dmaengine_submit(desc);
1e67bd2b
TA		 1007 if (dma_submit_error(atmel_port->cookie_tx)) {
1008 dev_err(port->dev, "dma_submit_error %d\n",
1009 atmel_port->cookie_tx);
1010 return;
1011 }
08f738be
ES		 1012 }
1013
1014 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1015 uart_write_wakeup(port);
1016}
1017
1018static int atmel_prepare_tx_dma(struct uart_port *port)
1019{
1020 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
c24d2531 1021 struct device *mfd_dev = port->dev->parent;
08f738be
ES		 1022 dma_cap_mask_t mask;
1023 struct dma_slave_config config;
1024 int ret, nent;
1025
1026 dma_cap_zero(mask);
1027 dma_cap_set(DMA_SLAVE, mask);
1028
c24d2531 1029 atmel_port->chan_tx = dma_request_slave_channel(mfd_dev, "tx");
08f738be
ES		 1030 if (atmel_port->chan_tx == NULL)
1031 goto chan_err;
1032 dev_info(port->dev, "using %s for tx DMA transfers\n",
1033 dma_chan_name(atmel_port->chan_tx));
1034
1035 spin_lock_init(&atmel_port->lock_tx);
1036 sg_init_table(&atmel_port->sg_tx, 1);
1037 /* UART circular tx buffer is an aligned page. */
2c277054 1038 BUG_ON(!PAGE_ALIGNED(port->state->xmit.buf));
08f738be
ES		 1039 sg_set_page(&atmel_port->sg_tx,
1040 virt_to_page(port->state->xmit.buf),
1041 UART_XMIT_SIZE,
2b5cf14b 1042 offset_in_page(port->state->xmit.buf));
08f738be
ES		 1043 nent = dma_map_sg(port->dev,
1044 &atmel_port->sg_tx,
1045 1,
48479148 1046 DMA_TO_DEVICE);
08f738be
ES		 1047
1048 if (!nent) {
1049 dev_dbg(port->dev, "need to release resource of dma\n");
1050 goto chan_err;
1051 } else {
c8d1f022 1052 dev_dbg(port->dev, "%s: mapped %d@%p to %pad\n", __func__,
08f738be
ES		 1053 sg_dma_len(&atmel_port->sg_tx),
1054 port->state->xmit.buf,
c8d1f022 1055 &sg_dma_address(&atmel_port->sg_tx));
08f738be
ES		 1056 }
1057
1058 /* Configure the slave DMA */
1059 memset(&config, 0, sizeof(config));
1060 config.direction = DMA_MEM_TO_DEV;
5f258b3e
CP		 1061 config.dst_addr_width = (atmel_port->fifo_size) ?
1062 DMA_SLAVE_BUSWIDTH_4_BYTES :
1063 DMA_SLAVE_BUSWIDTH_1_BYTE;
08f738be 1064 config.dst_addr = port->mapbase + ATMEL_US_THR;
a8d4e016 1065 config.dst_maxburst = 1;
08f738be 1066
5483c10e
MR		 1067 ret = dmaengine_slave_config(atmel_port->chan_tx,
1068 &config);
08f738be
ES		 1069 if (ret) {
1070 dev_err(port->dev, "DMA tx slave configuration failed\n");
1071 goto chan_err;
1072 }
1073
1074 return 0;
1075
1076chan_err:
1077 dev_err(port->dev, "TX channel not available, switch to pio\n");
36ce7cff 1078 atmel_port->use_dma_tx = false;
08f738be
ES		 1079 if (atmel_port->chan_tx)
1080 atmel_release_tx_dma(port);
1081 return -EINVAL;
1082}
1083
34df42f5
ES		 1084static void atmel_complete_rx_dma(void *arg)
1085{
1086 struct uart_port *port = arg;
1087 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1088
98f2082c 1089 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_rx);
34df42f5
ES		 1090}
1091
1092static void atmel_release_rx_dma(struct uart_port *port)
1093{
1094 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1095 struct dma_chan *chan = atmel_port->chan_rx;
1096
1097 if (chan) {
1098 dmaengine_terminate_all(chan);
1099 dma_release_channel(chan);
1100 dma_unmap_sg(port->dev, &atmel_port->sg_rx, 1,
48479148 1101 DMA_FROM_DEVICE);
34df42f5
ES		 1102 }
1103
1104 atmel_port->desc_rx = NULL;
1105 atmel_port->chan_rx = NULL;
1106 atmel_port->cookie_rx = -EINVAL;
1107}
1108
1109static void atmel_rx_from_dma(struct uart_port *port)
1110{
1111 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
66f37aaf 1112 struct tty_port *tport = &port->state->port;
34df42f5
ES		 1113 struct circ_buf *ring = &atmel_port->rx_ring;
1114 struct dma_chan *chan = atmel_port->chan_rx;
1115 struct dma_tx_state state;
1116 enum dma_status dmastat;
66f37aaf 1117 size_t count;
34df42f5
ES		 1118
1119
1120 /* Reset the UART timeout early so that we don't miss one */
4e7decda 1121 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
34df42f5
ES		 1122 dmastat = dmaengine_tx_status(chan,
1123 atmel_port->cookie_rx,
1124 &state);
1125 /* Restart a new tasklet if DMA status is error */
1126 if (dmastat == DMA_ERROR) {
1127 dev_dbg(port->dev, "Get residue error, restart tasklet\n");
4e7decda 1128 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_TIMEOUT);
98f2082c 1129 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_rx);
34df42f5
ES		 1130 return;
1131 }
34df42f5 1132
66f37aaf
CP		 1133 /* CPU claims ownership of RX DMA buffer */
1134 dma_sync_sg_for_cpu(port->dev,
1135 &atmel_port->sg_rx,
1136 1,
485819b5 1137 DMA_FROM_DEVICE);
66f37aaf
CP		 1138
1139 /*
1140 * ring->head points to the end of data already written by the DMA.
1141 * ring->tail points to the beginning of data to be read by the
1142 * framework.
1143 * The current transfer size should not be larger than the dma buffer
1144 * length.
1145 */
1146 ring->head = sg_dma_len(&atmel_port->sg_rx) - state.residue;
1147 BUG_ON(ring->head > sg_dma_len(&atmel_port->sg_rx));
34df42f5 1148 /*
66f37aaf
CP		 1149 * At this point ring->head may point to the first byte right after the
1150 * last byte of the dma buffer:
1151 * 0 <= ring->head <= sg_dma_len(&atmel_port->sg_rx)
1152 *
1153 * However ring->tail must always points inside the dma buffer:
1154 * 0 <= ring->tail <= sg_dma_len(&atmel_port->sg_rx) - 1
1155 *
1156 * Since we use a ring buffer, we have to handle the case
1157 * where head is lower than tail. In such a case, we first read from
1158 * tail to the end of the buffer then reset tail.
34df42f5 1159 */
66f37aaf
CP		 1160 if (ring->head < ring->tail) {
1161 count = sg_dma_len(&atmel_port->sg_rx) - ring->tail;
34df42f5 1162
66f37aaf
CP		 1163 tty_insert_flip_string(tport, ring->buf + ring->tail, count);
1164 ring->tail = 0;
1165 port->icount.rx += count;
1166 }
34df42f5 1167
66f37aaf
CP		 1168 /* Finally we read data from tail to head */
1169 if (ring->tail < ring->head) {
1170 count = ring->head - ring->tail;
34df42f5 1171
66f37aaf
CP		 1172 tty_insert_flip_string(tport, ring->buf + ring->tail, count);
1173 /* Wrap ring->head if needed */
1174 if (ring->head >= sg_dma_len(&atmel_port->sg_rx))
1175 ring->head = 0;
1176 ring->tail = ring->head;
34df42f5
ES		 1177 port->icount.rx += count;
1178 }
1179
66f37aaf
CP		 1180 /* USART retreives ownership of RX DMA buffer */
1181 dma_sync_sg_for_device(port->dev,
1182 &atmel_port->sg_rx,
1183 1,
485819b5 1184 DMA_FROM_DEVICE);
66f37aaf 1185
66f37aaf 1186 tty_flip_buffer_push(tport);
66f37aaf 1187
4e7decda 1188 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_TIMEOUT);
34df42f5
ES		 1189}
1190
1191static int atmel_prepare_rx_dma(struct uart_port *port)
1192{
1193 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
c24d2531 1194 struct device *mfd_dev = port->dev->parent;
34df42f5
ES		 1195 struct dma_async_tx_descriptor *desc;
1196 dma_cap_mask_t mask;
1197 struct dma_slave_config config;
1198 struct circ_buf *ring;
1199 int ret, nent;
1200
1201 ring = &atmel_port->rx_ring;
1202
1203 dma_cap_zero(mask);
1204 dma_cap_set(DMA_CYCLIC, mask);
1205
c24d2531 1206 atmel_port->chan_rx = dma_request_slave_channel(mfd_dev, "rx");
34df42f5
ES		 1207 if (atmel_port->chan_rx == NULL)
1208 goto chan_err;
1209 dev_info(port->dev, "using %s for rx DMA transfers\n",
1210 dma_chan_name(atmel_port->chan_rx));
1211
1212 spin_lock_init(&atmel_port->lock_rx);
1213 sg_init_table(&atmel_port->sg_rx, 1);
1214 /* UART circular rx buffer is an aligned page. */
2c277054 1215 BUG_ON(!PAGE_ALIGNED(ring->buf));
34df42f5 1216 sg_set_page(&atmel_port->sg_rx,
1842dc2e 1217 virt_to_page(ring->buf),
a510880f 1218 sizeof(struct atmel_uart_char) * ATMEL_SERIAL_RINGSIZE,
2b5cf14b 1219 offset_in_page(ring->buf));
1842dc2e
CP		 1220 nent = dma_map_sg(port->dev,
1221 &atmel_port->sg_rx,
1222 1,
1223 DMA_FROM_DEVICE);
34df42f5
ES		 1224
1225 if (!nent) {
1226 dev_dbg(port->dev, "need to release resource of dma\n");
1227 goto chan_err;
1228 } else {
c8d1f022 1229 dev_dbg(port->dev, "%s: mapped %d@%p to %pad\n", __func__,
34df42f5
ES		 1230 sg_dma_len(&atmel_port->sg_rx),
1231 ring->buf,
c8d1f022 1232 &sg_dma_address(&atmel_port->sg_rx));
34df42f5
ES		 1233 }
1234
1235 /* Configure the slave DMA */
1236 memset(&config, 0, sizeof(config));
1237 config.direction = DMA_DEV_TO_MEM;
1238 config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1239 config.src_addr = port->mapbase + ATMEL_US_RHR;
a8d4e016 1240 config.src_maxburst = 1;
34df42f5 1241
5483c10e
MR		 1242 ret = dmaengine_slave_config(atmel_port->chan_rx,
1243 &config);
34df42f5
ES		 1244 if (ret) {
1245 dev_err(port->dev, "DMA rx slave configuration failed\n");
1246 goto chan_err;
1247 }
1248 /*
1249 * Prepare a cyclic dma transfer, assign 2 descriptors,
1250 * each one is half ring buffer size
1251 */
1252 desc = dmaengine_prep_dma_cyclic(atmel_port->chan_rx,
1842dc2e
CP		 1253 sg_dma_address(&atmel_port->sg_rx),
1254 sg_dma_len(&atmel_port->sg_rx),
1255 sg_dma_len(&atmel_port->sg_rx)/2,
1256 DMA_DEV_TO_MEM,
1257 DMA_PREP_INTERRUPT);
c85be041
KL		 1258 if (!desc) {
1259 dev_err(port->dev, "Preparing DMA cyclic failed\n");
1260 goto chan_err;
1261 }
34df42f5
ES		 1262 desc->callback = atmel_complete_rx_dma;
1263 desc->callback_param = port;
1264 atmel_port->desc_rx = desc;
1265 atmel_port->cookie_rx = dmaengine_submit(desc);
1e67bd2b
TA		 1266 if (dma_submit_error(atmel_port->cookie_rx)) {
1267 dev_err(port->dev, "dma_submit_error %d\n",
1268 atmel_port->cookie_rx);
1269 goto chan_err;
1270 }
34df42f5
ES		 1271
1272 return 0;
1273
1274chan_err:
1275 dev_err(port->dev, "RX channel not available, switch to pio\n");
36ce7cff 1276 atmel_port->use_dma_rx = false;
34df42f5
ES		 1277 if (atmel_port->chan_rx)
1278 atmel_release_rx_dma(port);
1279 return -EINVAL;
1280}
1281
026cb432 1282static void atmel_uart_timer_callback(struct timer_list *t)
2e68c22f 1283{
026cb432
KC		 1284 struct atmel_uart_port *atmel_port = from_timer(atmel_port, t,
1285 uart_timer);
1286 struct uart_port *port = &atmel_port->uart;
2e68c22f 1287
98f2082c
NF		 1288 if (!atomic_read(&atmel_port->tasklet_shutdown)) {
1289 tasklet_schedule(&atmel_port->tasklet_rx);
1290 mod_timer(&atmel_port->uart_timer,
1291 jiffies + uart_poll_timeout(port));
1292 }
2e68c22f
ES		 1293}
1294
b843aa21
RB		 1295/*
1296 * receive interrupt handler.
1297 */
1298static void
1299atmel_handle_receive(struct uart_port *port, unsigned int pending)
1300{
c811ab8c 1301 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
b843aa21 1302
64e22ebe 1303 if (atmel_use_pdc_rx(port)) {
a6670615
CC		 1304 /*
1305 * PDC receive. Just schedule the tasklet and let it
1306 * figure out the details.
1307 *
1308 * TODO: We're not handling error flags correctly at
1309 * the moment.
1310 */
1311 if (pending & (ATMEL_US_ENDRX | ATMEL_US_TIMEOUT)) {
4e7decda
CP		 1312 atmel_uart_writel(port, ATMEL_US_IDR,
1313 (ATMEL_US_ENDRX | ATMEL_US_TIMEOUT));
98f2082c
NF		 1314 atmel_tasklet_schedule(atmel_port,
1315 &atmel_port->tasklet_rx);
a6670615
CC		 1316 }
1317
1318 if (pending & (ATMEL_US_RXBRK | ATMEL_US_OVRE |
1319 ATMEL_US_FRAME | ATMEL_US_PARE))
1320 atmel_pdc_rxerr(port, pending);
1321 }
1322
34df42f5
ES		 1323 if (atmel_use_dma_rx(port)) {
1324 if (pending & ATMEL_US_TIMEOUT) {
4e7decda
CP		 1325 atmel_uart_writel(port, ATMEL_US_IDR,
1326 ATMEL_US_TIMEOUT);
98f2082c
NF		 1327 atmel_tasklet_schedule(atmel_port,
1328 &atmel_port->tasklet_rx);
34df42f5
ES		 1329 }
1330 }
1331
b843aa21
RB		 1332 /* Interrupt receive */
1333 if (pending & ATMEL_US_RXRDY)
1334 atmel_rx_chars(port);
1335 else if (pending & ATMEL_US_RXBRK) {
1336 /*
1337 * End of break detected. If it came along with a
1338 * character, atmel_rx_chars will handle it.
1339 */
4e7decda
CP		 1340 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
1341 atmel_uart_writel(port, ATMEL_US_IDR, ATMEL_US_RXBRK);
b843aa21
RB		 1342 atmel_port->break_active = 0;
1343 }
1344}
1345
1346/*
1ecc26bd 1347 * transmit interrupt handler. (Transmit is IRQF_NODELAY safe)
b843aa21
RB		 1348 */
1349static void
1350atmel_handle_transmit(struct uart_port *port, unsigned int pending)
1351{
c811ab8c 1352 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1ecc26bd 1353
e8faff73 1354 if (pending & atmel_port->tx_done_mask) {
4e7decda
CP		 1355 atmel_uart_writel(port, ATMEL_US_IDR,
1356 atmel_port->tx_done_mask);
69646d7a
RS		 1357
1358 /* Start RX if flag was set and FIFO is empty */
1359 if (atmel_port->hd_start_rx) {
1360 if (!(atmel_uart_readl(port, ATMEL_US_CSR)
1361 & ATMEL_US_TXEMPTY))
1362 dev_warn(port->dev, "Should start RX, but TX fifo is not empty\n");
1363
1364 atmel_port->hd_start_rx = false;
1365 atmel_start_rx(port);
69646d7a
RS		 1366 }
1367
98f2082c 1368 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_tx);
1ecc26bd 1369 }
b843aa21
RB		 1370}
1371
1372/*
1373 * status flags interrupt handler.
1374 */
1375static void
1376atmel_handle_status(struct uart_port *port, unsigned int pending,
1377 unsigned int status)
1378{
c811ab8c 1379 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
9205218e 1380 unsigned int status_change;
1ecc26bd 1381
b843aa21 1382 if (pending & (ATMEL_US_RIIC | ATMEL_US_DSRIC | ATMEL_US_DCDIC
1ecc26bd 1383 | ATMEL_US_CTSIC)) {
9205218e 1384 status_change = status ^ atmel_port->irq_status_prev;
d033e82d 1385 atmel_port->irq_status_prev = status;
9205218e
NF		 1386
1387 if (status_change & (ATMEL_US_RI | ATMEL_US_DSR
1388 | ATMEL_US_DCD | ATMEL_US_CTS)) {
1389 /* TODO: All reads to CSR will clear these interrupts! */
1390 if (status_change & ATMEL_US_RI)
1391 port->icount.rng++;
1392 if (status_change & ATMEL_US_DSR)
1393 port->icount.dsr++;
1394 if (status_change & ATMEL_US_DCD)
1395 uart_handle_dcd_change(port, !(status & ATMEL_US_DCD));
1396 if (status_change & ATMEL_US_CTS)
1397 uart_handle_cts_change(port, !(status & ATMEL_US_CTS));
1398
1399 wake_up_interruptible(&port->state->port.delta_msr_wait);
1400 }
1ecc26bd 1401 }
377fedd1
NF		 1402
1403 if (pending & (ATMEL_US_NACK | ATMEL_US_ITERATION))
1404 dev_dbg(port->dev, "ISO7816 ERROR (0x%08x)\n", pending);
b843aa21
RB		 1405}
1406
1e6c9c28
AV		 1407/*
1408 * Interrupt handler
1409 */
7d12e780 1410static irqreturn_t atmel_interrupt(int irq, void *dev_id)
1e6c9c28
AV		 1411{
1412 struct uart_port *port = dev_id;
ab5e4e41 1413 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2c7af5ba 1414 unsigned int status, pending, mask, pass_counter = 0;
1e6c9c28 1415
2c7af5ba
BB		 1416 spin_lock(&atmel_port->lock_suspended);
1417
a6670615 1418 do {
d2d8d4c0 1419 status = atmel_uart_readl(port, ATMEL_US_CSR);
4e7decda 1420 mask = atmel_uart_readl(port, ATMEL_US_IMR);
2c7af5ba 1421 pending = status & mask;
a6670615
CC		 1422 if (!pending)
1423 break;
1424
2c7af5ba
BB		 1425 if (atmel_port->suspended) {
1426 atmel_port->pending |= pending;
1427 atmel_port->pending_status = status;
4e7decda 1428 atmel_uart_writel(port, ATMEL_US_IDR, mask);
2c7af5ba
BB		 1429 pm_system_wakeup();
1430 break;
1431 }
1432
b843aa21
RB		 1433 atmel_handle_receive(port, pending);
1434 atmel_handle_status(port, pending, status);
1435 atmel_handle_transmit(port, pending);
a6670615 1436 } while (pass_counter++ < ATMEL_ISR_PASS_LIMIT);
afefc415 1437
2c7af5ba
BB		 1438 spin_unlock(&atmel_port->lock_suspended);
1439
0400b697 1440 return pass_counter ? IRQ_HANDLED : IRQ_NONE;
a6670615 1441}
1e6c9c28 1442
a930e528
ES		 1443static void atmel_release_tx_pdc(struct uart_port *port)
1444{
1445 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1446 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1447
1448 dma_unmap_single(port->dev,
1449 pdc->dma_addr,
1450 pdc->dma_size,
1451 DMA_TO_DEVICE);
1452}
1453
a6670615
CC		 1454/*
1455 * Called from tasklet with ENDTX and TXBUFE interrupts disabled.
1456 */
64e22ebe 1457static void atmel_tx_pdc(struct uart_port *port)
a6670615 1458{
c811ab8c 1459 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
ebd2c8f6 1460 struct circ_buf *xmit = &port->state->xmit;
a6670615
CC		 1461 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1462 int count;
1463
ba0657ff 1464 /* nothing left to transmit? */
4e7decda 1465 if (atmel_uart_readl(port, ATMEL_PDC_TCR))
ba0657ff
MT		 1466 return;
1467
a6670615
CC		 1468 xmit->tail += pdc->ofs;
1469 xmit->tail &= UART_XMIT_SIZE - 1;
1470
1471 port->icount.tx += pdc->ofs;
1472 pdc->ofs = 0;
1473
ba0657ff 1474 /* more to transmit - setup next transfer */
a6670615 1475
ba0657ff 1476 /* disable PDC transmit */
4e7decda 1477 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS);
ba0657ff 1478
1f14081d 1479 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) {
a6670615
CC		 1480 dma_sync_single_for_device(port->dev,
1481 pdc->dma_addr,
1482 pdc->dma_size,
1483 DMA_TO_DEVICE);
1484
1485 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
1486 pdc->ofs = count;
1487
4e7decda
CP		 1488 atmel_uart_writel(port, ATMEL_PDC_TPR,
1489 pdc->dma_addr + xmit->tail);
1490 atmel_uart_writel(port, ATMEL_PDC_TCR, count);
e8faff73 1491 /* re-enable PDC transmit */
4e7decda 1492 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
e8faff73 1493 /* Enable interrupts */
4e7decda
CP		 1494 atmel_uart_writel(port, ATMEL_US_IER,
1495 atmel_port->tx_done_mask);
e8faff73 1496 } else {
f3040983 1497 if (atmel_uart_is_half_duplex(port)) {
e8faff73
CS		 1498 /* DMA done, stop TX, start RX for RS485 */
1499 atmel_start_rx(port);
1500 }
1e6c9c28 1501 }
a6670615
CC		 1502
1503 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1504 uart_write_wakeup(port);
1e6c9c28
AV		 1505}
1506
a930e528
ES		 1507static int atmel_prepare_tx_pdc(struct uart_port *port)
1508{
1509 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1510 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1511 struct circ_buf *xmit = &port->state->xmit;
1512
1513 pdc->buf = xmit->buf;
1514 pdc->dma_addr = dma_map_single(port->dev,
1515 pdc->buf,
1516 UART_XMIT_SIZE,
1517 DMA_TO_DEVICE);
1518 pdc->dma_size = UART_XMIT_SIZE;
1519 pdc->ofs = 0;
1520
1521 return 0;
1522}
1523
1ecc26bd
RB		 1524static void atmel_rx_from_ring(struct uart_port *port)
1525{
c811ab8c 1526 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1ecc26bd
RB		 1527 struct circ_buf *ring = &atmel_port->rx_ring;
1528 unsigned int flg;
1529 unsigned int status;
1530
1531 while (ring->head != ring->tail) {
1532 struct atmel_uart_char c;
1533
1534 /* Make sure c is loaded after head. */
1535 smp_rmb();
1536
1537 c = ((struct atmel_uart_char *)ring->buf)[ring->tail];
1538
1539 ring->tail = (ring->tail + 1) & (ATMEL_SERIAL_RINGSIZE - 1);
1540
1541 port->icount.rx++;
1542 status = c.status;
1543 flg = TTY_NORMAL;
1544
1545 /*
1546 * note that the error handling code is
1547 * out of the main execution path
1548 */
1549 if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME
1550 | ATMEL_US_OVRE | ATMEL_US_RXBRK))) {
1551 if (status & ATMEL_US_RXBRK) {
1552 /* ignore side-effect */
1553 status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME);
1554
1555 port->icount.brk++;
1556 if (uart_handle_break(port))
1557 continue;
1558 }
1559 if (status & ATMEL_US_PARE)
1560 port->icount.parity++;
1561 if (status & ATMEL_US_FRAME)
1562 port->icount.frame++;
1563 if (status & ATMEL_US_OVRE)
1564 port->icount.overrun++;
1565
1566 status &= port->read_status_mask;
1567
1568 if (status & ATMEL_US_RXBRK)
1569 flg = TTY_BREAK;
1570 else if (status & ATMEL_US_PARE)
1571 flg = TTY_PARITY;
1572 else if (status & ATMEL_US_FRAME)
1573 flg = TTY_FRAME;
1574 }
1575
1576
1577 if (uart_handle_sysrq_char(port, c.ch))
1578 continue;
1579
1580 uart_insert_char(port, status, ATMEL_US_OVRE, c.ch, flg);
1581 }
1582
2e124b4a 1583 tty_flip_buffer_push(&port->state->port);
1ecc26bd
RB		 1584}
1585
a930e528
ES		 1586static void atmel_release_rx_pdc(struct uart_port *port)
1587{
1588 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1589 int i;
1590
1591 for (i = 0; i < 2; i++) {
1592 struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i];
1593
1594 dma_unmap_single(port->dev,
1595 pdc->dma_addr,
1596 pdc->dma_size,
1597 DMA_FROM_DEVICE);
1598 kfree(pdc->buf);
1599 }
1600}
1601
64e22ebe 1602static void atmel_rx_from_pdc(struct uart_port *port)
a6670615 1603{
c811ab8c 1604 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
05c7cd39 1605 struct tty_port *tport = &port->state->port;
a6670615
CC		 1606 struct atmel_dma_buffer *pdc;
1607 int rx_idx = atmel_port->pdc_rx_idx;
1608 unsigned int head;
1609 unsigned int tail;
1610 unsigned int count;
1611
1612 do {
1613 /* Reset the UART timeout early so that we don't miss one */
4e7decda 1614 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
a6670615
CC		 1615
1616 pdc = &atmel_port->pdc_rx[rx_idx];
4e7decda 1617 head = atmel_uart_readl(port, ATMEL_PDC_RPR) - pdc->dma_addr;
a6670615
CC		 1618 tail = pdc->ofs;
1619
1620 /* If the PDC has switched buffers, RPR won't contain
1621 * any address within the current buffer. Since head
1622 * is unsigned, we just need a one-way comparison to
1623 * find out.
1624 *
1625 * In this case, we just need to consume the entire
1626 * buffer and resubmit it for DMA. This will clear the
1627 * ENDRX bit as well, so that we can safely re-enable
1628 * all interrupts below.
1629 */
1630 head = min(head, pdc->dma_size);
1631
1632 if (likely(head != tail)) {
1633 dma_sync_single_for_cpu(port->dev, pdc->dma_addr,
1634 pdc->dma_size, DMA_FROM_DEVICE);
1635
1636 /*
1637 * head will only wrap around when we recycle
1638 * the DMA buffer, and when that happens, we
1639 * explicitly set tail to 0. So head will
1640 * always be greater than tail.
1641 */
1642 count = head - tail;
1643
05c7cd39
JS		 1644 tty_insert_flip_string(tport, pdc->buf + pdc->ofs,
1645 count);
a6670615
CC		 1646
1647 dma_sync_single_for_device(port->dev, pdc->dma_addr,
1648 pdc->dma_size, DMA_FROM_DEVICE);
1649
1650 port->icount.rx += count;
1651 pdc->ofs = head;
1652 }
1653
1654 /*
1655 * If the current buffer is full, we need to check if
1656 * the next one contains any additional data.
1657 */
1658 if (head >= pdc->dma_size) {
1659 pdc->ofs = 0;
4e7decda
CP		 1660 atmel_uart_writel(port, ATMEL_PDC_RNPR, pdc->dma_addr);
1661 atmel_uart_writel(port, ATMEL_PDC_RNCR, pdc->dma_size);
a6670615
CC		 1662
1663 rx_idx = !rx_idx;
1664 atmel_port->pdc_rx_idx = rx_idx;
1665 }
1666 } while (head >= pdc->dma_size);
1667
2e124b4a 1668 tty_flip_buffer_push(tport);
a6670615 1669
4e7decda
CP		 1670 atmel_uart_writel(port, ATMEL_US_IER,
1671 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT);
a6670615
CC		 1672}
1673
a930e528
ES		 1674static int atmel_prepare_rx_pdc(struct uart_port *port)
1675{
1676 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1677 int i;
1678
1679 for (i = 0; i < 2; i++) {
1680 struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i];
1681
1682 pdc->buf = kmalloc(PDC_BUFFER_SIZE, GFP_KERNEL);
1683 if (pdc->buf == NULL) {
1684 if (i != 0) {
1685 dma_unmap_single(port->dev,
1686 atmel_port->pdc_rx[0].dma_addr,
1687 PDC_BUFFER_SIZE,
1688 DMA_FROM_DEVICE);
1689 kfree(atmel_port->pdc_rx[0].buf);
1690 }
36ce7cff 1691 atmel_port->use_pdc_rx = false;
a930e528
ES		 1692 return -ENOMEM;
1693 }
1694 pdc->dma_addr = dma_map_single(port->dev,
1695 pdc->buf,
1696 PDC_BUFFER_SIZE,
1697 DMA_FROM_DEVICE);
1698 pdc->dma_size = PDC_BUFFER_SIZE;
1699 pdc->ofs = 0;
1700 }
1701
1702 atmel_port->pdc_rx_idx = 0;
1703
4e7decda
CP		 1704 atmel_uart_writel(port, ATMEL_PDC_RPR, atmel_port->pdc_rx[0].dma_addr);
1705 atmel_uart_writel(port, ATMEL_PDC_RCR, PDC_BUFFER_SIZE);
a930e528 1706
4e7decda
CP		 1707 atmel_uart_writel(port, ATMEL_PDC_RNPR,
1708 atmel_port->pdc_rx[1].dma_addr);
1709 atmel_uart_writel(port, ATMEL_PDC_RNCR, PDC_BUFFER_SIZE);
a930e528
ES		 1710
1711 return 0;
1712}
1713
1ecc26bd
RB		 1714/*
1715 * tasklet handling tty stuff outside the interrupt handler.
1716 */
41e85e44 1717static void atmel_tasklet_rx_func(struct tasklet_struct *t)
1ecc26bd 1718{
41e85e44
AP		 1719 struct atmel_uart_port *atmel_port = from_tasklet(atmel_port, t,
1720 tasklet_rx);
1721 struct uart_port *port = &atmel_port->uart;
1ecc26bd
RB		 1722
1723 /* The interrupt handler does not take the lock */
1724 spin_lock(&port->lock);
a930e528 1725 atmel_port->schedule_rx(port);
00e8e658
NF		 1726 spin_unlock(&port->lock);
1727}
1ecc26bd 1728
41e85e44 1729static void atmel_tasklet_tx_func(struct tasklet_struct *t)
00e8e658 1730{
41e85e44
AP		 1731 struct atmel_uart_port *atmel_port = from_tasklet(atmel_port, t,
1732 tasklet_tx);
1733 struct uart_port *port = &atmel_port->uart;
00e8e658
NF		 1734
1735 /* The interrupt handler does not take the lock */
1736 spin_lock(&port->lock);
1737 atmel_port->schedule_tx(port);
1ecc26bd
RB		 1738 spin_unlock(&port->lock);
1739}
1740
4a1e8888 1741static void atmel_init_property(struct atmel_uart_port *atmel_port,
33d64c4f
ES		 1742 struct platform_device *pdev)
1743{
1744 struct device_node *np = pdev->dev.of_node;
92c8f7c0
AB		 1745
1746 /* DMA/PDC usage specification */
1747 if (of_property_read_bool(np, "atmel,use-dma-rx")) {
1748 if (of_property_read_bool(np, "dmas")) {
1749 atmel_port->use_dma_rx = true;
1750 atmel_port->use_pdc_rx = false;
33d64c4f
ES		 1751 } else {
1752 atmel_port->use_dma_rx = false;
92c8f7c0 1753 atmel_port->use_pdc_rx = true;
33d64c4f 1754 }
92c8f7c0
AB		 1755 } else {
1756 atmel_port->use_dma_rx = false;
1757 atmel_port->use_pdc_rx = false;
1758 }
33d64c4f 1759
92c8f7c0
AB		 1760 if (of_property_read_bool(np, "atmel,use-dma-tx")) {
1761 if (of_property_read_bool(np, "dmas")) {
1762 atmel_port->use_dma_tx = true;
1763 atmel_port->use_pdc_tx = false;
33d64c4f
ES		 1764 } else {
1765 atmel_port->use_dma_tx = false;
92c8f7c0 1766 atmel_port->use_pdc_tx = true;
33d64c4f 1767 }
33d64c4f 1768 } else {
33d64c4f 1769 atmel_port->use_dma_tx = false;
92c8f7c0 1770 atmel_port->use_pdc_tx = false;
33d64c4f 1771 }
33d64c4f
ES		 1772}
1773
a930e528
ES		 1774static void atmel_set_ops(struct uart_port *port)
1775{
1776 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1777
34df42f5
ES		 1778 if (atmel_use_dma_rx(port)) {
1779 atmel_port->prepare_rx = &atmel_prepare_rx_dma;
1780 atmel_port->schedule_rx = &atmel_rx_from_dma;
1781 atmel_port->release_rx = &atmel_release_rx_dma;
1782 } else if (atmel_use_pdc_rx(port)) {
a930e528
ES		 1783 atmel_port->prepare_rx = &atmel_prepare_rx_pdc;
1784 atmel_port->schedule_rx = &atmel_rx_from_pdc;
1785 atmel_port->release_rx = &atmel_release_rx_pdc;
1786 } else {
1787 atmel_port->prepare_rx = NULL;
1788 atmel_port->schedule_rx = &atmel_rx_from_ring;
1789 atmel_port->release_rx = NULL;
1790 }
1791
08f738be
ES		 1792 if (atmel_use_dma_tx(port)) {
1793 atmel_port->prepare_tx = &atmel_prepare_tx_dma;
1794 atmel_port->schedule_tx = &atmel_tx_dma;
1795 atmel_port->release_tx = &atmel_release_tx_dma;
1796 } else if (atmel_use_pdc_tx(port)) {
a930e528
ES		 1797 atmel_port->prepare_tx = &atmel_prepare_tx_pdc;
1798 atmel_port->schedule_tx = &atmel_tx_pdc;
1799 atmel_port->release_tx = &atmel_release_tx_pdc;
1800 } else {
1801 atmel_port->prepare_tx = NULL;
1802 atmel_port->schedule_tx = &atmel_tx_chars;
1803 atmel_port->release_tx = NULL;
1804 }
1805}
1806
055560b0
ES		 1807/*
1808 * Get ip name usart or uart
1809 */
892db58b 1810static void atmel_get_ip_name(struct uart_port *port)
055560b0
ES		 1811{
1812 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
4e7decda 1813 int name = atmel_uart_readl(port, ATMEL_US_NAME);
731d9cae 1814 u32 version;
1d673fb9 1815 u32 usart, dbgu_uart, new_uart;
4b769371
NF		 1816 /* ASCII decoding for IP version */
1817 usart = 0x55534152; /* USAR(T) */
1818 dbgu_uart = 0x44424755; /* DBGU */
1d673fb9 1819 new_uart = 0x55415254; /* UART */
055560b0 1820
5bf5635a
LD		 1821 /*
1822 * Only USART devices from at91sam9260 SOC implement fractional
2867af2d
RI		 1823 * baudrate. It is available for all asynchronous modes, with the
1824 * following restriction: the sampling clock's duty cycle is not
1825 * constant.
5bf5635a
LD		 1826 */
1827 atmel_port->has_frac_baudrate = false;
4b769371 1828 atmel_port->has_hw_timer = false;
055560b0 1829
2958ccee
LD		 1830 if (name == new_uart) {
1831 dev_dbg(port->dev, "Uart with hw timer");
4b769371 1832 atmel_port->has_hw_timer = true;
2958ccee
LD		 1833 atmel_port->rtor = ATMEL_UA_RTOR;
1834 } else if (name == usart) {
1835 dev_dbg(port->dev, "Usart\n");
5bf5635a 1836 atmel_port->has_frac_baudrate = true;
2958ccee
LD		 1837 atmel_port->has_hw_timer = true;
1838 atmel_port->rtor = ATMEL_US_RTOR;
377fedd1
NF		 1839 version = atmel_uart_readl(port, ATMEL_US_VERSION);
1840 switch (version) {
1841 case 0x814: /* sama5d2 */
df561f66 1842 fallthrough;
377fedd1
NF		 1843 case 0x701: /* sama5d4 */
1844 atmel_port->fidi_min = 3;
1845 atmel_port->fidi_max = 65535;
1846 break;
1847 case 0x502: /* sam9x5, sama5d3 */
1848 atmel_port->fidi_min = 3;
1849 atmel_port->fidi_max = 2047;
1850 break;
1851 default:
1852 atmel_port->fidi_min = 1;
1853 atmel_port->fidi_max = 2047;
1854 }
4b769371
NF		 1855 } else if (name == dbgu_uart) {
1856 dev_dbg(port->dev, "Dbgu or uart without hw timer\n");
055560b0 1857 } else {
731d9cae 1858 /* fallback for older SoCs: use version field */
4e7decda 1859 version = atmel_uart_readl(port, ATMEL_US_VERSION);
731d9cae
NF		 1860 switch (version) {
1861 case 0x302:
1862 case 0x10213:
fd63a890 1863 case 0x10302:
731d9cae 1864 dev_dbg(port->dev, "This version is usart\n");
5bf5635a 1865 atmel_port->has_frac_baudrate = true;
4b769371 1866 atmel_port->has_hw_timer = true;
2958ccee 1867 atmel_port->rtor = ATMEL_US_RTOR;
731d9cae
NF		 1868 break;
1869 case 0x203:
1870 case 0x10202:
1871 dev_dbg(port->dev, "This version is uart\n");
731d9cae
NF		 1872 break;
1873 default:
1874 dev_err(port->dev, "Not supported ip name nor version, set to uart\n");
1875 }
055560b0 1876 }
055560b0
ES		 1877}
1878
1e6c9c28
AV		 1879/*
1880 * Perform initialization and enable port for reception
1881 */
7192f92c 1882static int atmel_startup(struct uart_port *port)
1e6c9c28 1883{
33d64c4f 1884 struct platform_device *pdev = to_platform_device(port->dev);
c811ab8c 1885 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1e6c9c28
AV		 1886 int retval;
1887
1888 /*
1889 * Ensure that no interrupts are enabled otherwise when
1890 * request_irq() is called we could get stuck trying to
1891 * handle an unexpected interrupt
1892 */
4e7decda 1893 atmel_uart_writel(port, ATMEL_US_IDR, -1);
ab5e4e41 1894 atmel_port->ms_irq_enabled = false;
1e6c9c28
AV		 1895
1896 /*
1897 * Allocate the IRQ
1898 */
2c7af5ba 1899 retval = request_irq(port->irq, atmel_interrupt,
9594b5be
SAS		 1900 IRQF_SHARED | IRQF_COND_SUSPEND,
1901 dev_name(&pdev->dev), port);
1e6c9c28 1902 if (retval) {
ddaa6037 1903 dev_err(port->dev, "atmel_startup - Can't get irq\n");
1e6c9c28
AV		 1904 return retval;
1905 }
1906
98f2082c 1907 atomic_set(&atmel_port->tasklet_shutdown, 0);
41e85e44
AP		 1908 tasklet_setup(&atmel_port->tasklet_rx, atmel_tasklet_rx_func);
1909 tasklet_setup(&atmel_port->tasklet_tx, atmel_tasklet_tx_func);
1e125786 1910
a6670615
CC		 1911 /*
1912 * Initialize DMA (if necessary)
1913 */
33d64c4f 1914 atmel_init_property(atmel_port, pdev);
4d9628a1 1915 atmel_set_ops(port);
33d64c4f 1916
a930e528
ES		 1917 if (atmel_port->prepare_rx) {
1918 retval = atmel_port->prepare_rx(port);
1919 if (retval < 0)
1920 atmel_set_ops(port);
a6670615 1921 }
a6670615 1922
a930e528
ES		 1923 if (atmel_port->prepare_tx) {
1924 retval = atmel_port->prepare_tx(port);
1925 if (retval < 0)
1926 atmel_set_ops(port);
a6670615 1927 }
1e6c9c28 1928
b5199d46
CP		 1929 /*
1930 * Enable FIFO when available
1931 */
1932 if (atmel_port->fifo_size) {
1933 unsigned int txrdym = ATMEL_US_ONE_DATA;
1934 unsigned int rxrdym = ATMEL_US_ONE_DATA;
1935 unsigned int fmr;
1936
1937 atmel_uart_writel(port, ATMEL_US_CR,
1938 ATMEL_US_FIFOEN |
1939 ATMEL_US_RXFCLR |
1940 ATMEL_US_TXFLCLR);
1941
5f258b3e
CP		 1942 if (atmel_use_dma_tx(port))
1943 txrdym = ATMEL_US_FOUR_DATA;
1944
b5199d46
CP		 1945 fmr = ATMEL_US_TXRDYM(txrdym) | ATMEL_US_RXRDYM(rxrdym);
1946 if (atmel_port->rts_high &&
1947 atmel_port->rts_low)
1948 fmr |= ATMEL_US_FRTSC |
1949 ATMEL_US_RXFTHRES(atmel_port->rts_high) |
1950 ATMEL_US_RXFTHRES2(atmel_port->rts_low);
1951
1952 atmel_uart_writel(port, ATMEL_US_FMR, fmr);
1953 }
1954
27c0c8e5 1955 /* Save current CSR for comparison in atmel_tasklet_func() */
d2d8d4c0 1956 atmel_port->irq_status_prev = atmel_uart_readl(port, ATMEL_US_CSR);
27c0c8e5 1957
1e6c9c28
AV		 1958 /*
1959 * Finally, enable the serial port
1960 */
4e7decda 1961 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
b843aa21 1962 /* enable xmit & rcvr */
4e7decda 1963 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN);
ea04f82a 1964 atmel_port->tx_stopped = false;
afefc415 1965
026cb432 1966 timer_setup(&atmel_port->uart_timer, atmel_uart_timer_callback, 0);
8bc661bf 1967
64e22ebe 1968 if (atmel_use_pdc_rx(port)) {
a6670615 1969 /* set UART timeout */
4b769371 1970 if (!atmel_port->has_hw_timer) {
2e68c22f
ES		 1971 mod_timer(&atmel_port->uart_timer,
1972 jiffies + uart_poll_timeout(port));
1973 /* set USART timeout */
1974 } else {
2958ccee
LD		 1975 atmel_uart_writel(port, atmel_port->rtor,
1976 PDC_RX_TIMEOUT);
4e7decda 1977 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
a6670615 1978
4e7decda
CP		 1979 atmel_uart_writel(port, ATMEL_US_IER,
1980 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT);
2e68c22f 1981 }
a6670615 1982 /* enable PDC controller */
4e7decda 1983 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN);
34df42f5 1984 } else if (atmel_use_dma_rx(port)) {
2e68c22f 1985 /* set UART timeout */
4b769371 1986 if (!atmel_port->has_hw_timer) {
2e68c22f
ES		 1987 mod_timer(&atmel_port->uart_timer,
1988 jiffies + uart_poll_timeout(port));
1989 /* set USART timeout */
1990 } else {
2958ccee
LD		 1991 atmel_uart_writel(port, atmel_port->rtor,
1992 PDC_RX_TIMEOUT);
4e7decda 1993 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
34df42f5 1994
4e7decda
CP		 1995 atmel_uart_writel(port, ATMEL_US_IER,
1996 ATMEL_US_TIMEOUT);
2e68c22f 1997 }
a6670615
CC		 1998 } else {
1999 /* enable receive only */
4e7decda 2000 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_RXRDY);
a6670615 2001 }
afefc415 2002
1e6c9c28
AV		 2003 return 0;
2004}
2005
479e9b94
PH		 2006/*
2007 * Flush any TX data submitted for DMA. Called when the TX circular
2008 * buffer is reset.
2009 */
2010static void atmel_flush_buffer(struct uart_port *port)
2011{
2012 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2013
2014 if (atmel_use_pdc_tx(port)) {
4e7decda 2015 atmel_uart_writel(port, ATMEL_PDC_TCR, 0);
479e9b94
PH		 2016 atmel_port->pdc_tx.ofs = 0;
2017 }
31ca2c63
RG		 2018 /*
2019 * in uart_flush_buffer(), the xmit circular buffer has just
2020 * been cleared, so we have to reset tx_len accordingly.
2021 */
2022 atmel_port->tx_len = 0;
479e9b94
PH		 2023}
2024
1e6c9c28
AV		 2025/*
2026 * Disable the port
2027 */
7192f92c 2028static void atmel_shutdown(struct uart_port *port)
1e6c9c28 2029{
c811ab8c 2030 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
0cc7c6c7 2031
0ae9fdef
RG		 2032 /* Disable modem control lines interrupts */
2033 atmel_disable_ms(port);
2034
98f2082c
NF		 2035 /* Disable interrupts at device level */
2036 atmel_uart_writel(port, ATMEL_US_IDR, -1);
2037
2038 /* Prevent spurious interrupts from scheduling the tasklet */
2039 atomic_inc(&atmel_port->tasklet_shutdown);
2040
8bc661bf
MR		 2041 /*
2042 * Prevent any tasklets being scheduled during
2043 * cleanup
2044 */
2045 del_timer_sync(&atmel_port->uart_timer);
2046
98f2082c
NF		 2047 /* Make sure that no interrupt is on the fly */
2048 synchronize_irq(port->irq);
2049
0cc7c6c7
MR		 2050 /*
2051 * Clear out any scheduled tasklets before
2052 * we destroy the buffers
2053 */
00e8e658
NF		 2054 tasklet_kill(&atmel_port->tasklet_rx);
2055 tasklet_kill(&atmel_port->tasklet_tx);
0cc7c6c7 2056
a6670615 2057 /*
0cc7c6c7 2058 * Ensure everything is stopped and
98f2082c 2059 * disable port and break condition.
a6670615
CC		 2060 */
2061 atmel_stop_rx(port);
2062 atmel_stop_tx(port);
2063
4e7decda 2064 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
0cc7c6c7 2065
a6670615
CC		 2066 /*
2067 * Shut-down the DMA.
2068 */
a930e528
ES		 2069 if (atmel_port->release_rx)
2070 atmel_port->release_rx(port);
2071 if (atmel_port->release_tx)
2072 atmel_port->release_tx(port);
a6670615 2073
bb7e73c5
MD		 2074 /*
2075 * Reset ring buffer pointers
2076 */
2077 atmel_port->rx_ring.head = 0;
2078 atmel_port->rx_ring.tail = 0;
2079
1e6c9c28 2080 /*
ab5e4e41 2081 * Free the interrupts
1e6c9c28
AV		 2082 */
2083 free_irq(port->irq, port);
ab5e4e41 2084
479e9b94 2085 atmel_flush_buffer(port);
9afd561a
HS		 2086}
2087
1e6c9c28
AV		 2088/*
2089 * Power / Clock management.
2090 */
b843aa21
RB		 2091static void atmel_serial_pm(struct uart_port *port, unsigned int state,
2092 unsigned int oldstate)
1e6c9c28 2093{
c811ab8c 2094 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
afefc415 2095
1e6c9c28 2096 switch (state) {
aec079f8 2097 case UART_PM_STATE_ON:
b843aa21
RB		 2098 /*
2099 * Enable the peripheral clock for this serial port.
2100 * This is called on uart_open() or a resume event.
2101 */
91f8c2d8 2102 clk_prepare_enable(atmel_port->clk);
f05596db
AS		 2103
2104 /* re-enable interrupts if we disabled some on suspend */
4e7decda 2105 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->backup_imr);
b843aa21 2106 break;
aec079f8 2107 case UART_PM_STATE_OFF:
f05596db 2108 /* Back up the interrupt mask and disable all interrupts */
4e7decda
CP		 2109 atmel_port->backup_imr = atmel_uart_readl(port, ATMEL_US_IMR);
2110 atmel_uart_writel(port, ATMEL_US_IDR, -1);
f05596db 2111
b843aa21
RB		 2112 /*
2113 * Disable the peripheral clock for this serial port.
2114 * This is called on uart_close() or a suspend event.
2115 */
91f8c2d8 2116 clk_disable_unprepare(atmel_port->clk);
b843aa21
RB		 2117 break;
2118 default:
ddaa6037 2119 dev_err(port->dev, "atmel_serial: unknown pm %d\n", state);
1e6c9c28
AV		 2120 }
2121}
2122
2123/*
2124 * Change the port parameters
2125 */
b843aa21
RB		 2126static void atmel_set_termios(struct uart_port *port, struct ktermios *termios,
2127 struct ktermios *old)
1e6c9c28 2128{
5bf5635a 2129 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1e6c9c28 2130 unsigned long flags;
5bf5635a 2131 unsigned int old_mode, mode, imr, quot, baud, div, cd, fp = 0;
1cf6e8fc
CP		 2132
2133 /* save the current mode register */
4e7decda 2134 mode = old_mode = atmel_uart_readl(port, ATMEL_US_MR);
1e6c9c28 2135
1cf6e8fc
CP		 2136 /* reset the mode, clock divisor, parity, stop bits and data size */
2137 mode &= ~(ATMEL_US_USCLKS | ATMEL_US_CHRL | ATMEL_US_NBSTOP |
2138 ATMEL_US_PAR | ATMEL_US_USMODE);
03abeac0 2139
b843aa21 2140 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
1e6c9c28
AV		 2141
2142 /* byte size */
2143 switch (termios->c_cflag & CSIZE) {
2144 case CS5:
7192f92c 2145 mode |= ATMEL_US_CHRL_5;
1e6c9c28
AV		 2146 break;
2147 case CS6:
7192f92c 2148 mode |= ATMEL_US_CHRL_6;
1e6c9c28
AV		 2149 break;
2150 case CS7:
7192f92c 2151 mode |= ATMEL_US_CHRL_7;
1e6c9c28
AV		 2152 break;
2153 default:
7192f92c 2154 mode |= ATMEL_US_CHRL_8;
1e6c9c28
AV		 2155 break;
2156 }
2157
2158 /* stop bits */
2159 if (termios->c_cflag & CSTOPB)
7192f92c 2160 mode |= ATMEL_US_NBSTOP_2;
1e6c9c28
AV		 2161
2162 /* parity */
2163 if (termios->c_cflag & PARENB) {
b843aa21
RB		 2164 /* Mark or Space parity */
2165 if (termios->c_cflag & CMSPAR) {
1e6c9c28 2166 if (termios->c_cflag & PARODD)
7192f92c 2167 mode |= ATMEL_US_PAR_MARK;
1e6c9c28 2168 else
7192f92c 2169 mode |= ATMEL_US_PAR_SPACE;
b843aa21 2170 } else if (termios->c_cflag & PARODD)
7192f92c 2171 mode |= ATMEL_US_PAR_ODD;
1e6c9c28 2172 else
7192f92c 2173 mode |= ATMEL_US_PAR_EVEN;
b843aa21 2174 } else
7192f92c 2175 mode |= ATMEL_US_PAR_NONE;
1e6c9c28
AV		 2176
2177 spin_lock_irqsave(&port->lock, flags);
2178
7192f92c 2179 port->read_status_mask = ATMEL_US_OVRE;
1e6c9c28 2180 if (termios->c_iflag & INPCK)
7192f92c 2181 port->read_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE);
ef8b9ddc 2182 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
7192f92c 2183 port->read_status_mask |= ATMEL_US_RXBRK;
1e6c9c28 2184
64e22ebe 2185 if (atmel_use_pdc_rx(port))
a6670615 2186 /* need to enable error interrupts */
4e7decda 2187 atmel_uart_writel(port, ATMEL_US_IER, port->read_status_mask);
a6670615 2188
1e6c9c28
AV		 2189 /*
2190 * Characters to ignore
2191 */
2192 port->ignore_status_mask = 0;
2193 if (termios->c_iflag & IGNPAR)
7192f92c 2194 port->ignore_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE);
1e6c9c28 2195 if (termios->c_iflag & IGNBRK) {
7192f92c 2196 port->ignore_status_mask |= ATMEL_US_RXBRK;
1e6c9c28
AV		 2197 /*
2198 * If we're ignoring parity and break indicators,
2199 * ignore overruns too (for real raw support).
2200 */
2201 if (termios->c_iflag & IGNPAR)
7192f92c 2202 port->ignore_status_mask |= ATMEL_US_OVRE;
1e6c9c28 2203 }
b843aa21 2204 /* TODO: Ignore all characters if CREAD is set.*/
1e6c9c28
AV		 2205
2206 /* update the per-port timeout */
2207 uart_update_timeout(port, termios->c_cflag, baud);
2208
0ccad870
HS		 2209 /*
2210 * save/disable interrupts. The tty layer will ensure that the
2211 * transmitter is empty if requested by the caller, so there's
2212 * no need to wait for it here.
2213 */
4e7decda
CP		 2214 imr = atmel_uart_readl(port, ATMEL_US_IMR);
2215 atmel_uart_writel(port, ATMEL_US_IDR, -1);
1e6c9c28
AV		 2216
2217 /* disable receiver and transmitter */
4e7decda 2218 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXDIS | ATMEL_US_RXDIS);
ea04f82a 2219 atmel_port->tx_stopped = true;
1e6c9c28 2220
1cf6e8fc 2221 /* mode */
13bd3e6f 2222 if (port->rs485.flags & SER_RS485_ENABLED) {
4e7decda
CP		 2223 atmel_uart_writel(port, ATMEL_US_TTGR,
2224 port->rs485.delay_rts_after_send);
e8faff73 2225 mode |= ATMEL_US_USMODE_RS485;
377fedd1
NF		 2226 } else if (port->iso7816.flags & SER_ISO7816_ENABLED) {
2227 atmel_uart_writel(port, ATMEL_US_TTGR, port->iso7816.tg);
2228 /* select mck clock, and output */
2229 mode |= ATMEL_US_USCLKS_MCK | ATMEL_US_CLKO;
2230 /* set max iterations */
2231 mode |= ATMEL_US_MAX_ITER(3);
2232 if ((port->iso7816.flags & SER_ISO7816_T_PARAM)
2233 == SER_ISO7816_T(0))
2234 mode |= ATMEL_US_USMODE_ISO7816_T0;
2235 else
2236 mode |= ATMEL_US_USMODE_ISO7816_T1;
1cf6e8fc
CP		 2237 } else if (termios->c_cflag & CRTSCTS) {
2238 /* RS232 with hardware handshake (RTS/CTS) */
9bcffe75
RG		 2239 if (atmel_use_fifo(port) &&
2240 !mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_CTS)) {
2241 /*
2242 * with ATMEL_US_USMODE_HWHS set, the controller will
2243 * be able to drive the RTS pin high/low when the RX
2244 * FIFO is above RXFTHRES/below RXFTHRES2.
2245 * It will also disable the transmitter when the CTS
2246 * pin is high.
2247 * This mode is not activated if CTS pin is a GPIO
2248 * because in this case, the transmitter is always
2249 * disabled (there must be an internal pull-up
2250 * responsible for this behaviour).
2251 * If the RTS pin is a GPIO, the controller won't be
2252 * able to drive it according to the FIFO thresholds,
2253 * but it will be handled by the driver.
2254 */
5be605ac 2255 mode |= ATMEL_US_USMODE_HWHS;
9bcffe75
RG		 2256 } else {
2257 /*
2258 * For platforms without FIFO, the flow control is
2259 * handled by the driver.
2260 */
2261 mode |= ATMEL_US_USMODE_NORMAL;
5be605ac 2262 }
1cf6e8fc
CP		 2263 } else {
2264 /* RS232 without hadware handshake */
2265 mode |= ATMEL_US_USMODE_NORMAL;
e8faff73
CS		 2266 }
2267
5bf5635a
LD		 2268 /*
2269 * Set the baud rate:
2270 * Fractional baudrate allows to setup output frequency more
2271 * accurately. This feature is enabled only when using normal mode.
2272 * baudrate = selected clock / (8 * (2 - OVER) * (CD + FP / 8))
2273 * Currently, OVER is always set to 0 so we get
36131cdf
AS		 2274 * baudrate = selected clock / (16 * (CD + FP / 8))
2275 * then
2276 * 8 CD + FP = selected clock / (2 * baudrate)
5bf5635a 2277 */
2867af2d 2278 if (atmel_port->has_frac_baudrate) {
36131cdf
AS		 2279 div = DIV_ROUND_CLOSEST(port->uartclk, baud * 2);
2280 cd = div >> 3;
2281 fp = div & ATMEL_US_FP_MASK;
5bf5635a
LD		 2282 } else {
2283 cd = uart_get_divisor(port, baud);
2284 }
2285
2286 if (cd > 65535) { /* BRGR is 16-bit, so switch to slower clock */
2287 cd /= 8;
2288 mode |= ATMEL_US_USCLKS_MCK_DIV8;
2289 }
2290 quot = cd | fp << ATMEL_US_FP_OFFSET;
2291
377fedd1
NF		 2292 if (!(port->iso7816.flags & SER_ISO7816_ENABLED))
2293 atmel_uart_writel(port, ATMEL_US_BRGR, quot);
cb47b9f8
DE		 2294
2295 /* set the mode, clock divisor, parity, stop bits and data size */
2296 atmel_uart_writel(port, ATMEL_US_MR, mode);
2297
2298 /*
2299 * when switching the mode, set the RTS line state according to the
2300 * new mode, otherwise keep the former state
2301 */
2302 if ((old_mode & ATMEL_US_USMODE) != (mode & ATMEL_US_USMODE)) {
2303 unsigned int rts_state;
2304
2305 if ((mode & ATMEL_US_USMODE) == ATMEL_US_USMODE_HWHS) {
2306 /* let the hardware control the RTS line */
2307 rts_state = ATMEL_US_RTSDIS;
2308 } else {
2309 /* force RTS line to low level */
2310 rts_state = ATMEL_US_RTSEN;
2311 }
2312
2313 atmel_uart_writel(port, ATMEL_US_CR, rts_state);
2314 }
2315
4e7decda
CP		 2316 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
2317 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN);
ea04f82a 2318 atmel_port->tx_stopped = false;
1e6c9c28
AV		 2319
2320 /* restore interrupts */
4e7decda 2321 atmel_uart_writel(port, ATMEL_US_IER, imr);
1e6c9c28
AV		 2322
2323 /* CTS flow-control and modem-status interrupts */
2324 if (UART_ENABLE_MS(port, termios->c_cflag))
35b675b9
RG		 2325 atmel_enable_ms(port);
2326 else
2327 atmel_disable_ms(port);
1e6c9c28
AV		 2328
2329 spin_unlock_irqrestore(&port->lock, flags);
2330}
2331
732a84a0 2332static void atmel_set_ldisc(struct uart_port *port, struct ktermios *termios)
42bd7a4f 2333{
732a84a0 2334 if (termios->c_line == N_PPS) {
42bd7a4f 2335 port->flags |= UPF_HARDPPS_CD;
d41510ce 2336 spin_lock_irq(&port->lock);
42bd7a4f 2337 atmel_enable_ms(port);
d41510ce 2338 spin_unlock_irq(&port->lock);
42bd7a4f
VP		 2339 } else {
2340 port->flags &= ~UPF_HARDPPS_CD;
cab68f89
PH		 2341 if (!UART_ENABLE_MS(port, termios->c_cflag)) {
2342 spin_lock_irq(&port->lock);
2343 atmel_disable_ms(port);
2344 spin_unlock_irq(&port->lock);
2345 }
42bd7a4f
VP		 2346 }
2347}
2348
1e6c9c28
AV		 2349/*
2350 * Return string describing the specified port
2351 */
7192f92c 2352static const char *atmel_type(struct uart_port *port)
1e6c9c28 2353{
9ab4f88b 2354 return (port->type == PORT_ATMEL) ? "ATMEL_SERIAL" : NULL;
1e6c9c28
AV		 2355}
2356
2357/*
2358 * Release the memory region(s) being used by 'port'.
2359 */
7192f92c 2360static void atmel_release_port(struct uart_port *port)
1e6c9c28 2361{
c24d2531
RP		 2362 struct platform_device *mpdev = to_platform_device(port->dev->parent);
2363 int size = resource_size(mpdev->resource);
afefc415
AV		 2364
2365 release_mem_region(port->mapbase, size);
2366
2367 if (port->flags & UPF_IOREMAP) {
2368 iounmap(port->membase);
2369 port->membase = NULL;
2370 }
1e6c9c28
AV		 2371}
2372
2373/*
2374 * Request the memory region(s) being used by 'port'.
2375 */
7192f92c 2376static int atmel_request_port(struct uart_port *port)
1e6c9c28 2377{
c24d2531
RP		 2378 struct platform_device *mpdev = to_platform_device(port->dev->parent);
2379 int size = resource_size(mpdev->resource);
afefc415 2380
7192f92c 2381 if (!request_mem_region(port->mapbase, size, "atmel_serial"))
afefc415
AV		 2382 return -EBUSY;
2383
2384 if (port->flags & UPF_IOREMAP) {
2385 port->membase = ioremap(port->mapbase, size);
2386 if (port->membase == NULL) {
2387 release_mem_region(port->mapbase, size);
2388 return -ENOMEM;
2389 }
2390 }
1e6c9c28 2391
afefc415 2392 return 0;
1e6c9c28
AV		 2393}
2394
2395/*
2396 * Configure/autoconfigure the port.
2397 */
7192f92c 2398static void atmel_config_port(struct uart_port *port, int flags)
1e6c9c28
AV		 2399{
2400 if (flags & UART_CONFIG_TYPE) {
9ab4f88b 2401 port->type = PORT_ATMEL;
7192f92c 2402 atmel_request_port(port);
1e6c9c28
AV		 2403 }
2404}
2405
2406/*
2407 * Verify the new serial_struct (for TIOCSSERIAL).
2408 */
7192f92c 2409static int atmel_verify_port(struct uart_port *port, struct serial_struct *ser)
1e6c9c28
AV		 2410{
2411 int ret = 0;
9ab4f88b 2412 if (ser->type != PORT_UNKNOWN && ser->type != PORT_ATMEL)
1e6c9c28
AV		 2413 ret = -EINVAL;
2414 if (port->irq != ser->irq)
2415 ret = -EINVAL;
2416 if (ser->io_type != SERIAL_IO_MEM)
2417 ret = -EINVAL;
2418 if (port->uartclk / 16 != ser->baud_base)
2419 ret = -EINVAL;
270c2ade 2420 if (port->mapbase != (unsigned long)ser->iomem_base)
1e6c9c28
AV		 2421 ret = -EINVAL;
2422 if (port->iobase != ser->port)
2423 ret = -EINVAL;
2424 if (ser->hub6 != 0)
2425 ret = -EINVAL;
2426 return ret;
2427}
2428
8fe2d541
AT		 2429#ifdef CONFIG_CONSOLE_POLL
2430static int atmel_poll_get_char(struct uart_port *port)
2431{
4e7decda 2432 while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_RXRDY))
8fe2d541
AT		 2433 cpu_relax();
2434
a6499435 2435 return atmel_uart_read_char(port);
8fe2d541
AT		 2436}
2437
2438static void atmel_poll_put_char(struct uart_port *port, unsigned char ch)
2439{
4e7decda 2440 while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXRDY))
8fe2d541
AT		 2441 cpu_relax();
2442
a6499435 2443 atmel_uart_write_char(port, ch);
8fe2d541
AT		 2444}
2445#endif
2446
5c7dcdb6 2447static const struct uart_ops atmel_pops = {
7192f92c
HS		 2448 .tx_empty = atmel_tx_empty,
2449 .set_mctrl = atmel_set_mctrl,
2450 .get_mctrl = atmel_get_mctrl,
2451 .stop_tx = atmel_stop_tx,
2452 .start_tx = atmel_start_tx,
2453 .stop_rx = atmel_stop_rx,
2454 .enable_ms = atmel_enable_ms,
2455 .break_ctl = atmel_break_ctl,
2456 .startup = atmel_startup,
2457 .shutdown = atmel_shutdown,
9afd561a 2458 .flush_buffer = atmel_flush_buffer,
7192f92c 2459 .set_termios = atmel_set_termios,
42bd7a4f 2460 .set_ldisc = atmel_set_ldisc,
7192f92c
HS		 2461 .type = atmel_type,
2462 .release_port = atmel_release_port,
2463 .request_port = atmel_request_port,
2464 .config_port = atmel_config_port,
2465 .verify_port = atmel_verify_port,
2466 .pm = atmel_serial_pm,
8fe2d541
AT		 2467#ifdef CONFIG_CONSOLE_POLL
2468 .poll_get_char = atmel_poll_get_char,
2469 .poll_put_char = atmel_poll_put_char,
2470#endif
1e6c9c28
AV		 2471};
2472
afefc415
AV		 2473/*
2474 * Configure the port from the platform device resource info.
2475 */
91f8c2d8 2476static int atmel_init_port(struct atmel_uart_port *atmel_port,
b843aa21 2477 struct platform_device *pdev)
1e6c9c28 2478{
91f8c2d8 2479 int ret;
7192f92c 2480 struct uart_port *port = &atmel_port->uart;
c24d2531 2481 struct platform_device *mpdev = to_platform_device(pdev->dev.parent);
afefc415 2482
4a1e8888
LZ		 2483 atmel_init_property(atmel_port, pdev);
2484 atmel_set_ops(port);
afefc415 2485
e8faff73 2486 port->iotype = UPIO_MEM;
92c8f7c0 2487 port->flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP;
e8faff73
CS		 2488 port->ops = &atmel_pops;
2489 port->fifosize = 1;
e8faff73 2490 port->dev = &pdev->dev;
c24d2531
RP		 2491 port->mapbase = mpdev->resource[0].start;
2492 port->irq = mpdev->resource[1].start;
13bd3e6f 2493 port->rs485_config = atmel_config_rs485;
377fedd1 2494 port->iso7816_config = atmel_config_iso7816;
c24d2531 2495 port->membase = NULL;
afefc415 2496
1ecc26bd
RB		 2497 memset(&atmel_port->rx_ring, 0, sizeof(atmel_port->rx_ring));
2498
c150c0f3
LW		 2499 ret = uart_get_rs485_mode(port);
2500 if (ret)
2501 return ret;
2502
b843aa21
RB		 2503 /* for console, the clock could already be configured */
2504 if (!atmel_port->clk) {
c24d2531 2505 atmel_port->clk = clk_get(&mpdev->dev, "usart");
91f8c2d8
BB		 2506 if (IS_ERR(atmel_port->clk)) {
2507 ret = PTR_ERR(atmel_port->clk);
2508 atmel_port->clk = NULL;
2509 return ret;
2510 }
2511 ret = clk_prepare_enable(atmel_port->clk);
2512 if (ret) {
2513 clk_put(atmel_port->clk);
2514 atmel_port->clk = NULL;
2515 return ret;
2516 }
7192f92c 2517 port->uartclk = clk_get_rate(atmel_port->clk);
91f8c2d8 2518 clk_disable_unprepare(atmel_port->clk);
06a7f058 2519 /* only enable clock when USART is in use */
afefc415 2520 }
a6670615 2521
377fedd1
NF		 2522 /*
2523 * Use TXEMPTY for interrupt when rs485 or ISO7816 else TXRDY or
2524 * ENDTX|TXBUFE
2525 */
477b8383 2526 if (atmel_uart_is_half_duplex(port))
e8faff73 2527 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY;
64e22ebe 2528 else if (atmel_use_pdc_tx(port)) {
a6670615 2529 port->fifosize = PDC_BUFFER_SIZE;
e8faff73
CS		 2530 atmel_port->tx_done_mask = ATMEL_US_ENDTX | ATMEL_US_TXBUFE;
2531 } else {
2532 atmel_port->tx_done_mask = ATMEL_US_TXRDY;
2533 }
91f8c2d8
BB		 2534
2535 return 0;
1e6c9c28
AV		 2536}
2537
749c4e60 2538#ifdef CONFIG_SERIAL_ATMEL_CONSOLE
7192f92c 2539static void atmel_console_putchar(struct uart_port *port, int ch)
d358788f 2540{
4e7decda 2541 while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXRDY))
829dd811 2542 cpu_relax();
a6499435 2543 atmel_uart_write_char(port, ch);
d358788f 2544}
1e6c9c28
AV		 2545
2546/*
2547 * Interrupts are disabled on entering
2548 */
7192f92c 2549static void atmel_console_write(struct console *co, const char *s, u_int count)
1e6c9c28 2550{
7192f92c 2551 struct uart_port *port = &atmel_ports[co->index].uart;
e8faff73 2552 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
d358788f 2553 unsigned int status, imr;
39d4c922 2554 unsigned int pdc_tx;
1e6c9c28
AV		 2555
2556 /*
b843aa21 2557 * First, save IMR and then disable interrupts
1e6c9c28 2558 */
4e7decda
CP		 2559 imr = atmel_uart_readl(port, ATMEL_US_IMR);
2560 atmel_uart_writel(port, ATMEL_US_IDR,
2561 ATMEL_US_RXRDY | atmel_port->tx_done_mask);
1e6c9c28 2562
39d4c922 2563 /* Store PDC transmit status and disable it */
4e7decda
CP		 2564 pdc_tx = atmel_uart_readl(port, ATMEL_PDC_PTSR) & ATMEL_PDC_TXTEN;
2565 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS);
39d4c922 2566
497e1e16
NF		 2567 /* Make sure that tx path is actually able to send characters */
2568 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN);
ea04f82a 2569 atmel_port->tx_stopped = false;
497e1e16 2570
7192f92c 2571 uart_console_write(port, s, count, atmel_console_putchar);
1e6c9c28
AV		 2572
2573 /*
b843aa21
RB		 2574 * Finally, wait for transmitter to become empty
2575 * and restore IMR
1e6c9c28
AV		 2576 */
2577 do {
4e7decda 2578 status = atmel_uart_readl(port, ATMEL_US_CSR);
7192f92c 2579 } while (!(status & ATMEL_US_TXRDY));
39d4c922
MP		 2580
2581 /* Restore PDC transmit status */
2582 if (pdc_tx)
4e7decda 2583 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
39d4c922 2584
b843aa21 2585 /* set interrupts back the way they were */
4e7decda 2586 atmel_uart_writel(port, ATMEL_US_IER, imr);
1e6c9c28
AV		 2587}
2588
2589/*
b843aa21
RB		 2590 * If the port was already initialised (eg, by a boot loader),
2591 * try to determine the current setup.
1e6c9c28 2592 */
b843aa21
RB		 2593static void __init atmel_console_get_options(struct uart_port *port, int *baud,
2594 int *parity, int *bits)
1e6c9c28
AV		 2595{
2596 unsigned int mr, quot;
2597
1c0fd82f
HS		 2598 /*
2599 * If the baud rate generator isn't running, the port wasn't
2600 * initialized by the boot loader.
2601 */
4e7decda 2602 quot = atmel_uart_readl(port, ATMEL_US_BRGR) & ATMEL_US_CD;
1c0fd82f
HS		 2603 if (!quot)
2604 return;
1e6c9c28 2605
4e7decda 2606 mr = atmel_uart_readl(port, ATMEL_US_MR) & ATMEL_US_CHRL;
7192f92c 2607 if (mr == ATMEL_US_CHRL_8)
1e6c9c28
AV		 2608 *bits = 8;
2609 else
2610 *bits = 7;
2611
4e7decda 2612 mr = atmel_uart_readl(port, ATMEL_US_MR) & ATMEL_US_PAR;
7192f92c 2613 if (mr == ATMEL_US_PAR_EVEN)
1e6c9c28 2614 *parity = 'e';
7192f92c 2615 else if (mr == ATMEL_US_PAR_ODD)
1e6c9c28
AV		 2616 *parity = 'o';
2617
4d5e392c
HS		 2618 /*
2619 * The serial core only rounds down when matching this to a
2620 * supported baud rate. Make sure we don't end up slightly
2621 * lower than one of those, as it would make us fall through
2622 * to a much lower baud rate than we really want.
2623 */
4d5e392c 2624 *baud = port->uartclk / (16 * (quot - 1));
1e6c9c28
AV		 2625}
2626
7192f92c 2627static int __init atmel_console_setup(struct console *co, char *options)
1e6c9c28 2628{
91f8c2d8 2629 int ret;
7192f92c 2630 struct uart_port *port = &atmel_ports[co->index].uart;
ea04f82a 2631 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1e6c9c28
AV		 2632 int baud = 115200;
2633 int bits = 8;
2634 int parity = 'n';
2635 int flow = 'n';
2636
b843aa21
RB		 2637 if (port->membase == NULL) {
2638 /* Port not initialized yet - delay setup */
afefc415 2639 return -ENODEV;
b843aa21 2640 }
1e6c9c28 2641
91f8c2d8
BB		 2642 ret = clk_prepare_enable(atmel_ports[co->index].clk);
2643 if (ret)
2644 return ret;
06a7f058 2645
4e7decda
CP		 2646 atmel_uart_writel(port, ATMEL_US_IDR, -1);
2647 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
2648 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN);
ea04f82a 2649 atmel_port->tx_stopped = false;
1e6c9c28
AV		 2650
2651 if (options)
2652 uart_parse_options(options, &baud, &parity, &bits, &flow);
2653 else
7192f92c 2654 atmel_console_get_options(port, &baud, &parity, &bits);
1e6c9c28
AV		 2655
2656 return uart_set_options(port, co, baud, parity, bits, flow);
2657}
2658
7192f92c 2659static struct uart_driver atmel_uart;
1e6c9c28 2660
7192f92c
HS		 2661static struct console atmel_console = {
2662 .name = ATMEL_DEVICENAME,
2663 .write = atmel_console_write,
1e6c9c28 2664 .device = uart_console_device,
7192f92c 2665 .setup = atmel_console_setup,
1e6c9c28
AV		 2666 .flags = CON_PRINTBUFFER,
2667 .index = -1,
7192f92c 2668 .data = &atmel_uart,
1e6c9c28
AV		 2669};
2670
06a7f058 2671#define ATMEL_CONSOLE_DEVICE (&atmel_console)
1e6c9c28 2672
1e6c9c28 2673#else
7192f92c 2674#define ATMEL_CONSOLE_DEVICE NULL
1e6c9c28
AV		 2675#endif
2676
7192f92c 2677static struct uart_driver atmel_uart = {
b843aa21
RB		 2678 .owner = THIS_MODULE,
2679 .driver_name = "atmel_serial",
2680 .dev_name = ATMEL_DEVICENAME,
2681 .major = SERIAL_ATMEL_MAJOR,
2682 .minor = MINOR_START,
2683 .nr = ATMEL_MAX_UART,
2684 .cons = ATMEL_CONSOLE_DEVICE,
1e6c9c28
AV		 2685};
2686
afefc415 2687#ifdef CONFIG_PM
f826caa4
HS		 2688static bool atmel_serial_clk_will_stop(void)
2689{
2690#ifdef CONFIG_ARCH_AT91
2691 return at91_suspend_entering_slow_clock();
2692#else
2693 return false;
2694#endif
2695}
2696
b843aa21
RB		 2697static int atmel_serial_suspend(struct platform_device *pdev,
2698 pm_message_t state)
1e6c9c28 2699{
afefc415 2700 struct uart_port *port = platform_get_drvdata(pdev);
c811ab8c 2701 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
afefc415 2702
207f6f34 2703 if (uart_console(port) && console_suspend_enabled) {
e1c609ef 2704 /* Drain the TX shifter */
4e7decda
CP		 2705 while (!(atmel_uart_readl(port, ATMEL_US_CSR) &
2706 ATMEL_US_TXEMPTY))
e1c609ef
HS		 2707 cpu_relax();
2708 }
2709
207f6f34 2710 if (uart_console(port) && !console_suspend_enabled) {
6a5f0e2f
AB		 2711 /* Cache register values as we won't get a full shutdown/startup
2712 * cycle
2713 */
2714 atmel_port->cache.mr = atmel_uart_readl(port, ATMEL_US_MR);
2715 atmel_port->cache.imr = atmel_uart_readl(port, ATMEL_US_IMR);
2716 atmel_port->cache.brgr = atmel_uart_readl(port, ATMEL_US_BRGR);
2717 atmel_port->cache.rtor = atmel_uart_readl(port,
2718 atmel_port->rtor);
2719 atmel_port->cache.ttgr = atmel_uart_readl(port, ATMEL_US_TTGR);
2720 atmel_port->cache.fmr = atmel_uart_readl(port, ATMEL_US_FMR);
2721 atmel_port->cache.fimr = atmel_uart_readl(port, ATMEL_US_FIMR);
2722 }
2723
f05596db
AS		 2724 /* we can not wake up if we're running on slow clock */
2725 atmel_port->may_wakeup = device_may_wakeup(&pdev->dev);
2c7af5ba
BB		 2726 if (atmel_serial_clk_will_stop()) {
2727 unsigned long flags;
2728
2729 spin_lock_irqsave(&atmel_port->lock_suspended, flags);
2730 atmel_port->suspended = true;
2731 spin_unlock_irqrestore(&atmel_port->lock_suspended, flags);
f05596db 2732 device_set_wakeup_enable(&pdev->dev, 0);
2c7af5ba 2733 }
f05596db
AS		 2734
2735 uart_suspend_port(&atmel_uart, port);
1e6c9c28 2736
afefc415
AV		 2737 return 0;
2738}
1e6c9c28 2739
7192f92c 2740static int atmel_serial_resume(struct platform_device *pdev)
afefc415
AV		 2741{
2742 struct uart_port *port = platform_get_drvdata(pdev);
c811ab8c 2743 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2c7af5ba
BB		 2744 unsigned long flags;
2745
207f6f34 2746 if (uart_console(port) && !console_suspend_enabled) {
6a5f0e2f
AB		 2747 atmel_uart_writel(port, ATMEL_US_MR, atmel_port->cache.mr);
2748 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->cache.imr);
2749 atmel_uart_writel(port, ATMEL_US_BRGR, atmel_port->cache.brgr);
2750 atmel_uart_writel(port, atmel_port->rtor,
2751 atmel_port->cache.rtor);
2752 atmel_uart_writel(port, ATMEL_US_TTGR, atmel_port->cache.ttgr);
2753
2754 if (atmel_port->fifo_size) {
2755 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_FIFOEN |
2756 ATMEL_US_RXFCLR | ATMEL_US_TXFLCLR);
2757 atmel_uart_writel(port, ATMEL_US_FMR,
2758 atmel_port->cache.fmr);
2759 atmel_uart_writel(port, ATMEL_US_FIER,
2760 atmel_port->cache.fimr);
2761 }
2762 atmel_start_rx(port);
2763 }
2764
2c7af5ba
BB		 2765 spin_lock_irqsave(&atmel_port->lock_suspended, flags);
2766 if (atmel_port->pending) {
2767 atmel_handle_receive(port, atmel_port->pending);
2768 atmel_handle_status(port, atmel_port->pending,
2769 atmel_port->pending_status);
2770 atmel_handle_transmit(port, atmel_port->pending);
2771 atmel_port->pending = 0;
2772 }
2773 atmel_port->suspended = false;
2774 spin_unlock_irqrestore(&atmel_port->lock_suspended, flags);
1e6c9c28 2775
f05596db
AS		 2776 uart_resume_port(&atmel_uart, port);
2777 device_set_wakeup_enable(&pdev->dev, atmel_port->may_wakeup);
1e6c9c28
AV		 2778
2779 return 0;
2780}
afefc415 2781#else
7192f92c
HS		 2782#define atmel_serial_suspend NULL
2783#define atmel_serial_resume NULL
afefc415 2784#endif
1e6c9c28 2785
b78cd169 2786static void atmel_serial_probe_fifos(struct atmel_uart_port *atmel_port,
b5199d46
CP		 2787 struct platform_device *pdev)
2788{
b78cd169
JA		 2789 atmel_port->fifo_size = 0;
2790 atmel_port->rts_low = 0;
2791 atmel_port->rts_high = 0;
b5199d46
CP		 2792
2793 if (of_property_read_u32(pdev->dev.of_node,
2794 "atmel,fifo-size",
b78cd169 2795 &atmel_port->fifo_size))
b5199d46
CP		 2796 return;
2797
b78cd169 2798 if (!atmel_port->fifo_size)
b5199d46
CP		 2799 return;
2800
b78cd169
JA		 2801 if (atmel_port->fifo_size < ATMEL_MIN_FIFO_SIZE) {
2802 atmel_port->fifo_size = 0;
b5199d46
CP		 2803 dev_err(&pdev->dev, "Invalid FIFO size\n");
2804 return;
2805 }
2806
2807 /*
2808 * 0 <= rts_low <= rts_high <= fifo_size
2809 * Once their CTS line asserted by the remote peer, some x86 UARTs tend
2810 * to flush their internal TX FIFO, commonly up to 16 data, before
2811 * actually stopping to send new data. So we try to set the RTS High
2812 * Threshold to a reasonably high value respecting this 16 data
2813 * empirical rule when possible.
2814 */
b78cd169
JA		 2815 atmel_port->rts_high = max_t(int, atmel_port->fifo_size >> 1,
2816 atmel_port->fifo_size - ATMEL_RTS_HIGH_OFFSET);
2817 atmel_port->rts_low = max_t(int, atmel_port->fifo_size >> 2,
2818 atmel_port->fifo_size - ATMEL_RTS_LOW_OFFSET);
b5199d46
CP		 2819
2820 dev_info(&pdev->dev, "Using FIFO (%u data)\n",
b78cd169 2821 atmel_port->fifo_size);
b5199d46 2822 dev_dbg(&pdev->dev, "RTS High Threshold : %2u data\n",
b78cd169 2823 atmel_port->rts_high);
b5199d46 2824 dev_dbg(&pdev->dev, "RTS Low Threshold : %2u data\n",
b78cd169 2825 atmel_port->rts_low);
b5199d46
CP		 2826}
2827
9671f099 2828static int atmel_serial_probe(struct platform_device *pdev)
1e6c9c28 2829{
b78cd169 2830 struct atmel_uart_port *atmel_port;
c24d2531 2831 struct device_node *np = pdev->dev.parent->of_node;
1ecc26bd 2832 void *data;
8d41ab87 2833 int ret;
bd737f87 2834 bool rs485_enabled;
1e6c9c28 2835
9d09daf8 2836 BUILD_BUG_ON(ATMEL_SERIAL_RINGSIZE & (ATMEL_SERIAL_RINGSIZE - 1));
1ecc26bd 2837
c24d2531
RP		 2838 /*
2839 * In device tree there is no node with "atmel,at91rm9200-usart-serial"
2840 * as compatible string. This driver is probed by at91-usart mfd driver
2841 * which is just a wrapper over the atmel_serial driver and
2842 * spi-at91-usart driver. All attributes needed by this driver are
2843 * found in of_node of parent.
2844 */
2845 pdev->dev.of_node = np;
2846
92c8f7c0 2847 ret = of_alias_get_id(np, "serial");
4cbf9f48 2848 if (ret < 0)
5fbe46b6 2849 /* port id not found in platform data nor device-tree aliases:
4cbf9f48 2850 * auto-enumerate it */
503bded9 2851 ret = find_first_zero_bit(atmel_ports_in_use, ATMEL_MAX_UART);
4cbf9f48 2852
503bded9 2853 if (ret >= ATMEL_MAX_UART) {
4cbf9f48
NF		 2854 ret = -ENODEV;
2855 goto err;
2856 }
2857
503bded9 2858 if (test_and_set_bit(ret, atmel_ports_in_use)) {
4cbf9f48
NF		 2859 /* port already in use */
2860 ret = -EBUSY;
2861 goto err;
2862 }
2863
b78cd169
JA		 2864 atmel_port = &atmel_ports[ret];
2865 atmel_port->backup_imr = 0;
2866 atmel_port->uart.line = ret;
078abd98 2867 atmel_port->uart.has_sysrq = IS_ENABLED(CONFIG_SERIAL_ATMEL_CONSOLE);
b78cd169 2868 atmel_serial_probe_fifos(atmel_port, pdev);
e0b0baad 2869
98f2082c 2870 atomic_set(&atmel_port->tasklet_shutdown, 0);
b78cd169 2871 spin_lock_init(&atmel_port->lock_suspended);
2c7af5ba 2872
b78cd169 2873 ret = atmel_init_port(atmel_port, pdev);
91f8c2d8 2874 if (ret)
6fbb9bdf 2875 goto err_clear_bit;
1e6c9c28 2876
b78cd169
JA		 2877 atmel_port->gpios = mctrl_gpio_init(&atmel_port->uart, 0);
2878 if (IS_ERR(atmel_port->gpios)) {
2879 ret = PTR_ERR(atmel_port->gpios);
18dfef9c
UKK		 2880 goto err_clear_bit;
2881 }
2882
b78cd169 2883 if (!atmel_use_pdc_rx(&atmel_port->uart)) {
a6670615 2884 ret = -ENOMEM;
6da2ec56
KC		 2885 data = kmalloc_array(ATMEL_SERIAL_RINGSIZE,
2886 sizeof(struct atmel_uart_char),
2887 GFP_KERNEL);
a6670615
CC		 2888 if (!data)
2889 goto err_alloc_ring;
b78cd169 2890 atmel_port->rx_ring.buf = data;
a6670615 2891 }
1ecc26bd 2892
b78cd169 2893 rs485_enabled = atmel_port->uart.rs485.flags & SER_RS485_ENABLED;
bd737f87 2894
b78cd169 2895 ret = uart_add_one_port(&atmel_uart, &atmel_port->uart);
dfa7f343
HS		 2896 if (ret)
2897 goto err_add_port;
2898
8da14b5f 2899#ifdef CONFIG_SERIAL_ATMEL_CONSOLE
207f6f34 2900 if (uart_console(&atmel_port->uart)
06a7f058
DB		 2901 && ATMEL_CONSOLE_DEVICE->flags & CON_ENABLED) {
2902 /*
2903 * The serial core enabled the clock for us, so undo
91f8c2d8 2904 * the clk_prepare_enable() in atmel_console_setup()
06a7f058 2905 */
b78cd169 2906 clk_disable_unprepare(atmel_port->clk);
06a7f058 2907 }
8da14b5f 2908#endif
06a7f058 2909
dfa7f343 2910 device_init_wakeup(&pdev->dev, 1);
b78cd169 2911 platform_set_drvdata(pdev, atmel_port);
dfa7f343 2912
d4f64187
CP		 2913 /*
2914 * The peripheral clock has been disabled by atmel_init_port():
2915 * enable it before accessing I/O registers
2916 */
b78cd169 2917 clk_prepare_enable(atmel_port->clk);
d4f64187 2918
bd737f87 2919 if (rs485_enabled) {
b78cd169 2920 atmel_uart_writel(&atmel_port->uart, ATMEL_US_MR,
4e7decda 2921 ATMEL_US_USMODE_NORMAL);
b78cd169
JA		 2922 atmel_uart_writel(&atmel_port->uart, ATMEL_US_CR,
2923 ATMEL_US_RTSEN);
5dfbd1d7
CS		 2924 }
2925
055560b0
ES		 2926 /*
2927 * Get port name of usart or uart
2928 */
b78cd169 2929 atmel_get_ip_name(&atmel_port->uart);
055560b0 2930
d4f64187
CP		 2931 /*
2932 * The peripheral clock can now safely be disabled till the port
2933 * is used
2934 */
b78cd169 2935 clk_disable_unprepare(atmel_port->clk);
d4f64187 2936
dfa7f343
HS		 2937 return 0;
2938
2939err_add_port:
b78cd169
JA		 2940 kfree(atmel_port->rx_ring.buf);
2941 atmel_port->rx_ring.buf = NULL;
1ecc26bd 2942err_alloc_ring:
207f6f34 2943 if (!uart_console(&atmel_port->uart)) {
b78cd169
JA		 2944 clk_put(atmel_port->clk);
2945 atmel_port->clk = NULL;
afefc415 2946 }
6fbb9bdf 2947err_clear_bit:
b78cd169 2948 clear_bit(atmel_port->uart.line, atmel_ports_in_use);
4cbf9f48 2949err:
afefc415
AV		 2950 return ret;
2951}
2952
f4a8ab04
RI		 2953/*
2954 * Even if the driver is not modular, it makes sense to be able to
2955 * unbind a device: there can be many bound devices, and there are
2956 * situations where dynamic binding and unbinding can be useful.
2957 *
2958 * For example, a connected device can require a specific firmware update
2959 * protocol that needs bitbanging on IO lines, but use the regular serial
2960 * port in the normal case.
2961 */
2962static int atmel_serial_remove(struct platform_device *pdev)
2963{
2964 struct uart_port *port = platform_get_drvdata(pdev);
2965 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2966 int ret = 0;
2967
00e8e658
NF		 2968 tasklet_kill(&atmel_port->tasklet_rx);
2969 tasklet_kill(&atmel_port->tasklet_tx);
f4a8ab04
RI		 2970
2971 device_init_wakeup(&pdev->dev, 0);
2972
2973 ret = uart_remove_one_port(&atmel_uart, port);
2974
2975 kfree(atmel_port->rx_ring.buf);
2976
2977 /* "port" is allocated statically, so we shouldn't free it */
2978
2979 clear_bit(port->line, atmel_ports_in_use);
2980
2981 clk_put(atmel_port->clk);
2982 atmel_port->clk = NULL;
c24d2531 2983 pdev->dev.of_node = NULL;
f4a8ab04
RI		 2984
2985 return ret;
2986}
2987
7192f92c
HS		 2988static struct platform_driver atmel_serial_driver = {
2989 .probe = atmel_serial_probe,
f4a8ab04 2990 .remove = atmel_serial_remove,
7192f92c
HS		 2991 .suspend = atmel_serial_suspend,
2992 .resume = atmel_serial_resume,
afefc415 2993 .driver = {
c24d2531 2994 .name = "atmel_usart_serial",
c39dfebc 2995 .of_match_table = of_match_ptr(atmel_serial_dt_ids),
afefc415
AV		 2996 },
2997};
2998
7192f92c 2999static int __init atmel_serial_init(void)
afefc415
AV		 3000{
3001 int ret;
3002
7192f92c 3003 ret = uart_register_driver(&atmel_uart);
afefc415
AV		 3004 if (ret)
3005 return ret;
3006
7192f92c 3007 ret = platform_driver_register(&atmel_serial_driver);
afefc415 3008 if (ret)
7192f92c 3009 uart_unregister_driver(&atmel_uart);
afefc415
AV		 3010
3011 return ret;
3012}
c39dfebc 3013device_initcall(atmel_serial_init);
Linux 6.x block layer and io_uring tree(s)