projects / linux-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
tty: serial: switch from circ_buf to kfifo
[linux-block.git] / drivers / tty / serial / atmel_serial.c
CommitLineData
e3b3d0f5 1// SPDX-License-Identifier: GPL-2.0+
1e6c9c28 2/*
72ce5732 3 * Driver for Atmel AT91 Serial ports
1e6c9c28
AV		 4 * Copyright (C) 2003 Rick Bronson
5 *
6 * Based on drivers/char/serial_sa1100.c, by Deep Blue Solutions Ltd.
7 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
8 *
a6670615 9 * DMA support added by Chip Coldwell.
1e6c9c28 10 */
702d10a0 11#include <linux/circ_buf.h>
1e6c9c28
AV		 12#include <linux/tty.h>
13#include <linux/ioport.h>
14#include <linux/slab.h>
15#include <linux/init.h>
16#include <linux/serial.h>
afefc415 17#include <linux/clk.h>
5e3ce1f2 18#include <linux/clk-provider.h>
1e6c9c28
AV		 19#include <linux/console.h>
20#include <linux/sysrq.h>
21#include <linux/tty_flip.h>
afefc415 22#include <linux/platform_device.h>
5fbe46b6 23#include <linux/of.h>
a6670615 24#include <linux/dma-mapping.h>
6b997bab 25#include <linux/dmaengine.h>
93a3ddc2 26#include <linux/atmel_pdc.h>
e8faff73 27#include <linux/uaccess.h>
bcd2360c 28#include <linux/platform_data/atmel.h>
2e68c22f 29#include <linux/timer.h>
e0b0baad 30#include <linux/err.h>
ab5e4e41 31#include <linux/irq.h>
2c7af5ba 32#include <linux/suspend.h>
2b5cf14b 33#include <linux/mm.h>
635b2589 34#include <linux/io.h>
1e6c9c28 35
377fedd1 36#include <asm/div64.h>
f7512e7c 37#include <asm/ioctls.h>
1e6c9c28 38
a6670615
CC		 39#define PDC_BUFFER_SIZE 512
40/* Revisit: We should calculate this based on the actual port settings */
41#define PDC_RX_TIMEOUT (3 * 10) /* 3 bytes */
42
b5199d46
CP		 43/* The minium number of data FIFOs should be able to contain */
44#define ATMEL_MIN_FIFO_SIZE 8
45/*
46 * These two offsets are substracted from the RX FIFO size to define the RTS
47 * high and low thresholds
48 */
49#define ATMEL_RTS_HIGH_OFFSET 16
50#define ATMEL_RTS_LOW_OFFSET 20
51
1e6c9c28
AV		 52#include <linux/serial_core.h>
53
e0b0baad 54#include "serial_mctrl_gpio.h"
8961df89 55#include "atmel_serial.h"
e0b0baad 56
e8faff73
CS		 57static void atmel_start_rx(struct uart_port *port);
58static void atmel_stop_rx(struct uart_port *port);
59
749c4e60 60#ifdef CONFIG_SERIAL_ATMEL_TTYAT
1e6c9c28
AV		 61
62/* Use device name ttyAT, major 204 and minor 154-169. This is necessary if we
63 * should coexist with the 8250 driver, such as if we have an external 16C550
64 * UART. */
7192f92c 65#define SERIAL_ATMEL_MAJOR 204
1e6c9c28 66#define MINOR_START 154
7192f92c 67#define ATMEL_DEVICENAME "ttyAT"
1e6c9c28
AV		 68
69#else
70
71/* Use device name ttyS, major 4, minor 64-68. This is the usual serial port
72 * name, but it is legally reserved for the 8250 driver. */
7192f92c 73#define SERIAL_ATMEL_MAJOR TTY_MAJOR
1e6c9c28 74#define MINOR_START 64
7192f92c 75#define ATMEL_DEVICENAME "ttyS"
1e6c9c28
AV		 76
77#endif
78
7192f92c 79#define ATMEL_ISR_PASS_LIMIT 256
1e6c9c28 80
a6670615
CC		 81struct atmel_dma_buffer {
82 unsigned char *buf;
83 dma_addr_t dma_addr;
84 unsigned int dma_size;
85 unsigned int ofs;
86};
87
1ecc26bd
RB		 88struct atmel_uart_char {
89 u16 status;
90 u16 ch;
91};
92
637ba54f
LD		 93/*
94 * Be careful, the real size of the ring buffer is
95 * sizeof(atmel_uart_char) * ATMEL_SERIAL_RINGSIZE. It means that ring buffer
96 * can contain up to 1024 characters in PIO mode and up to 4096 characters in
97 * DMA mode.
98 */
1ecc26bd
RB		 99#define ATMEL_SERIAL_RINGSIZE 1024
100
9af92fbf
AB		 101/*
102 * at91: 6 USARTs and one DBGU port (SAM9260)
432f9748 103 * samx7: 3 USARTs and 5 UARTs
9af92fbf 104 */
432f9748 105#define ATMEL_MAX_UART 8
9af92fbf 106
afefc415
AV		 107/*
108 * We wrap our port structure around the generic uart_port.
109 */
7192f92c 110struct atmel_uart_port {
afefc415
AV		 111 struct uart_port uart; /* uart */
112 struct clk *clk; /* uart clock */
5e3ce1f2 113 struct clk *gclk; /* uart generic clock */
f05596db
AS		 114 int may_wakeup; /* cached value of device_may_wakeup for times we need to disable it */
115 u32 backup_imr; /* IMR saved during suspend */
9e6077bd 116 int break_active; /* break being received */
1ecc26bd 117
34df42f5 118 bool use_dma_rx; /* enable DMA receiver */
64e22ebe 119 bool use_pdc_rx; /* enable PDC receiver */
a6670615
CC		 120 short pdc_rx_idx; /* current PDC RX buffer */
121 struct atmel_dma_buffer pdc_rx[2]; /* PDC receier */
122
08f738be 123 bool use_dma_tx; /* enable DMA transmitter */
64e22ebe 124 bool use_pdc_tx; /* enable PDC transmitter */
a6670615
CC		 125 struct atmel_dma_buffer pdc_tx; /* PDC transmitter */
126
08f738be 127 spinlock_t lock_tx; /* port lock */
34df42f5 128 spinlock_t lock_rx; /* port lock */
08f738be 129 struct dma_chan *chan_tx;
34df42f5 130 struct dma_chan *chan_rx;
08f738be 131 struct dma_async_tx_descriptor *desc_tx;
34df42f5 132 struct dma_async_tx_descriptor *desc_rx;
08f738be 133 dma_cookie_t cookie_tx;
34df42f5 134 dma_cookie_t cookie_rx;
08f738be 135 struct scatterlist sg_tx;
34df42f5 136 struct scatterlist sg_rx;
00e8e658
NF		 137 struct tasklet_struct tasklet_rx;
138 struct tasklet_struct tasklet_tx;
98f2082c 139 atomic_t tasklet_shutdown;
1ecc26bd 140 unsigned int irq_status_prev;
5f258b3e 141 unsigned int tx_len;
1ecc26bd
RB		 142
143 struct circ_buf rx_ring;
e8faff73 144
e0b0baad 145 struct mctrl_gpios *gpios;
377fedd1
NF		 146 u32 backup_mode; /* MR saved during iso7816 operations */
147 u32 backup_brgr; /* BRGR saved during iso7816 operations */
e8faff73 148 unsigned int tx_done_mask;
b5199d46
CP		 149 u32 fifo_size;
150 u32 rts_high;
151 u32 rts_low;
ab5e4e41 152 bool ms_irq_enabled;
2958ccee 153 u32 rtor; /* address of receiver timeout register if it exists */
5644bf18 154 bool is_usart;
5bf5635a 155 bool has_frac_baudrate;
4b769371
NF		 156 bool has_hw_timer;
157 struct timer_list uart_timer;
2c7af5ba 158
ea04f82a 159 bool tx_stopped;
2c7af5ba
BB		 160 bool suspended;
161 unsigned int pending;
162 unsigned int pending_status;
163 spinlock_t lock_suspended;
164
69646d7a
RS		 165 bool hd_start_rx; /* can start RX during half-duplex operation */
166
377fedd1
NF		 167 /* ISO7816 */
168 unsigned int fidi_min;
169 unsigned int fidi_max;
170
6a5f0e2f
AB		 171 struct {
172 u32 cr;
173 u32 mr;
174 u32 imr;
175 u32 brgr;
176 u32 rtor;
177 u32 ttgr;
178 u32 fmr;
179 u32 fimr;
180 } cache;
181
a930e528
ES		 182 int (*prepare_rx)(struct uart_port *port);
183 int (*prepare_tx)(struct uart_port *port);
184 void (*schedule_rx)(struct uart_port *port);
185 void (*schedule_tx)(struct uart_port *port);
186 void (*release_rx)(struct uart_port *port);
187 void (*release_tx)(struct uart_port *port);
afefc415
AV		 188};
189
7192f92c 190static struct atmel_uart_port atmel_ports[ATMEL_MAX_UART];
503bded9 191static DECLARE_BITMAP(atmel_ports_in_use, ATMEL_MAX_UART);
afefc415 192
5fbe46b6
NF		 193#if defined(CONFIG_OF)
194static const struct of_device_id atmel_serial_dt_ids[] = {
c24d2531 195 { .compatible = "atmel,at91rm9200-usart-serial" },
5fbe46b6
NF		 196 { /* sentinel */ }
197};
5fbe46b6
NF		 198#endif
199
c811ab8c
HS		 200static inline struct atmel_uart_port *
201to_atmel_uart_port(struct uart_port *uart)
202{
203 return container_of(uart, struct atmel_uart_port, uart);
204}
205
4e7decda
CP		 206static inline u32 atmel_uart_readl(struct uart_port *port, u32 reg)
207{
208 return __raw_readl(port->membase + reg);
209}
210
211static inline void atmel_uart_writel(struct uart_port *port, u32 reg, u32 value)
212{
213 __raw_writel(value, port->membase + reg);
214}
215
a6499435 216static inline u8 atmel_uart_read_char(struct uart_port *port)
b5199d46 217{
a6499435 218 return __raw_readb(port->membase + ATMEL_US_RHR);
b5199d46
CP		 219}
220
a6499435
CP		 221static inline void atmel_uart_write_char(struct uart_port *port, u8 value)
222{
223 __raw_writeb(value, port->membase + ATMEL_US_THR);
224}
225
f3040983
RS		 226static inline int atmel_uart_is_half_duplex(struct uart_port *port)
227{
228 return ((port->rs485.flags & SER_RS485_ENABLED) &&
229 !(port->rs485.flags & SER_RS485_RX_DURING_TX)) ||
230 (port->iso7816.flags & SER_ISO7816_ENABLED);
231}
232
5e3ce1f2
SM		 233static inline int atmel_error_rate(int desired_value, int actual_value)
234{
235 return 100 - (desired_value * 100) / actual_value;
236}
237
a6670615 238#ifdef CONFIG_SERIAL_ATMEL_PDC
64e22ebe 239static bool atmel_use_pdc_rx(struct uart_port *port)
a6670615 240{
c811ab8c 241 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
a6670615 242
64e22ebe 243 return atmel_port->use_pdc_rx;
a6670615
CC		 244}
245
64e22ebe 246static bool atmel_use_pdc_tx(struct uart_port *port)
a6670615 247{
c811ab8c 248 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
a6670615 249
64e22ebe 250 return atmel_port->use_pdc_tx;
a6670615
CC		 251}
252#else
64e22ebe 253static bool atmel_use_pdc_rx(struct uart_port *port)
a6670615
CC		 254{
255 return false;
256}
257
64e22ebe 258static bool atmel_use_pdc_tx(struct uart_port *port)
a6670615
CC		 259{
260 return false;
261}
262#endif
263
08f738be
ES		 264static bool atmel_use_dma_tx(struct uart_port *port)
265{
266 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
267
268 return atmel_port->use_dma_tx;
269}
270
34df42f5
ES		 271static bool atmel_use_dma_rx(struct uart_port *port)
272{
273 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
274
275 return atmel_port->use_dma_rx;
276}
277
5be605ac
AB		 278static bool atmel_use_fifo(struct uart_port *port)
279{
280 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
281
282 return atmel_port->fifo_size;
283}
284
98f2082c
NF		 285static void atmel_tasklet_schedule(struct atmel_uart_port *atmel_port,
286 struct tasklet_struct *t)
287{
288 if (!atomic_read(&atmel_port->tasklet_shutdown))
289 tasklet_schedule(t);
290}
291
e8faff73 292/* Enable or disable the rs485 support */
ae50bb27 293static int atmel_config_rs485(struct uart_port *port, struct ktermios *termios,
13bd3e6f 294 struct serial_rs485 *rs485conf)
e8faff73
CS		 295{
296 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
297 unsigned int mode;
e8faff73
CS		 298
299 /* Disable interrupts */
4e7decda 300 atmel_uart_writel(port, ATMEL_US_IDR, atmel_port->tx_done_mask);
e8faff73 301
4e7decda 302 mode = atmel_uart_readl(port, ATMEL_US_MR);
e8faff73 303
e8faff73
CS		 304 if (rs485conf->flags & SER_RS485_ENABLED) {
305 dev_dbg(port->dev, "Setting UART to RS485\n");
60efd051 306 if (rs485conf->flags & SER_RS485_RX_DURING_TX)
477b8383
CC		 307 atmel_port->tx_done_mask = ATMEL_US_TXRDY;
308 else
309 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY;
310
4e7decda
CP		 311 atmel_uart_writel(port, ATMEL_US_TTGR,
312 rs485conf->delay_rts_after_send);
692a8ebc 313 mode &= ~ATMEL_US_USMODE;
e8faff73
CS		 314 mode |= ATMEL_US_USMODE_RS485;
315 } else {
316 dev_dbg(port->dev, "Setting UART to RS232\n");
64e22ebe 317 if (atmel_use_pdc_tx(port))
e8faff73
CS		 318 atmel_port->tx_done_mask = ATMEL_US_ENDTX |
319 ATMEL_US_TXBUFE;
320 else
321 atmel_port->tx_done_mask = ATMEL_US_TXRDY;
322 }
4e7decda 323 atmel_uart_writel(port, ATMEL_US_MR, mode);
e8faff73
CS		 324
325 /* Enable interrupts */
4e7decda 326 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->tx_done_mask);
e8faff73 327
13bd3e6f 328 return 0;
e8faff73
CS		 329}
330
377fedd1
NF		 331static unsigned int atmel_calc_cd(struct uart_port *port,
332 struct serial_iso7816 *iso7816conf)
333{
334 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
335 unsigned int cd;
336 u64 mck_rate;
337
338 mck_rate = (u64)clk_get_rate(atmel_port->clk);
339 do_div(mck_rate, iso7816conf->clk);
340 cd = mck_rate;
341 return cd;
342}
343
344static unsigned int atmel_calc_fidi(struct uart_port *port,
345 struct serial_iso7816 *iso7816conf)
346{
347 u64 fidi = 0;
348
349 if (iso7816conf->sc_fi && iso7816conf->sc_di) {
350 fidi = (u64)iso7816conf->sc_fi;
351 do_div(fidi, iso7816conf->sc_di);
352 }
353 return (u32)fidi;
354}
355
356/* Enable or disable the iso7816 support */
357/* Called with interrupts disabled */
358static int atmel_config_iso7816(struct uart_port *port,
359 struct serial_iso7816 *iso7816conf)
360{
361 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
362 unsigned int mode;
363 unsigned int cd, fidi;
364 int ret = 0;
365
366 /* Disable interrupts */
367 atmel_uart_writel(port, ATMEL_US_IDR, atmel_port->tx_done_mask);
368
369 mode = atmel_uart_readl(port, ATMEL_US_MR);
370
371 if (iso7816conf->flags & SER_ISO7816_ENABLED) {
372 mode &= ~ATMEL_US_USMODE;
373
374 if (iso7816conf->tg > 255) {
375 dev_err(port->dev, "ISO7816: Timeguard exceeding 255\n");
376 memset(iso7816conf, 0, sizeof(struct serial_iso7816));
377 ret = -EINVAL;
378 goto err_out;
379 }
380
381 if ((iso7816conf->flags & SER_ISO7816_T_PARAM)
382 == SER_ISO7816_T(0)) {
383 mode |= ATMEL_US_USMODE_ISO7816_T0 | ATMEL_US_DSNACK;
384 } else if ((iso7816conf->flags & SER_ISO7816_T_PARAM)
385 == SER_ISO7816_T(1)) {
386 mode |= ATMEL_US_USMODE_ISO7816_T1 | ATMEL_US_INACK;
387 } else {
388 dev_err(port->dev, "ISO7816: Type not supported\n");
389 memset(iso7816conf, 0, sizeof(struct serial_iso7816));
390 ret = -EINVAL;
391 goto err_out;
392 }
393
394 mode &= ~(ATMEL_US_USCLKS | ATMEL_US_NBSTOP | ATMEL_US_PAR);
395
396 /* select mck clock, and output */
397 mode |= ATMEL_US_USCLKS_MCK | ATMEL_US_CLKO;
398 /* set parity for normal/inverse mode + max iterations */
399 mode |= ATMEL_US_PAR_EVEN | ATMEL_US_NBSTOP_1 | ATMEL_US_MAX_ITER(3);
400
401 cd = atmel_calc_cd(port, iso7816conf);
402 fidi = atmel_calc_fidi(port, iso7816conf);
403 if (fidi == 0) {
404 dev_warn(port->dev, "ISO7816 fidi = 0, Generator generates no signal\n");
405 } else if (fidi < atmel_port->fidi_min
406 || fidi > atmel_port->fidi_max) {
407 dev_err(port->dev, "ISO7816 fidi = %u, value not supported\n", fidi);
408 memset(iso7816conf, 0, sizeof(struct serial_iso7816));
409 ret = -EINVAL;
410 goto err_out;
411 }
412
413 if (!(port->iso7816.flags & SER_ISO7816_ENABLED)) {
414 /* port not yet in iso7816 mode: store configuration */
415 atmel_port->backup_mode = atmel_uart_readl(port, ATMEL_US_MR);
416 atmel_port->backup_brgr = atmel_uart_readl(port, ATMEL_US_BRGR);
417 }
418
419 atmel_uart_writel(port, ATMEL_US_TTGR, iso7816conf->tg);
420 atmel_uart_writel(port, ATMEL_US_BRGR, cd);
421 atmel_uart_writel(port, ATMEL_US_FIDI, fidi);
422
423 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXDIS | ATMEL_US_RXEN);
424 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY | ATMEL_US_NACK | ATMEL_US_ITERATION;
425 } else {
426 dev_dbg(port->dev, "Setting UART back to RS232\n");
427 /* back to last RS232 settings */
428 mode = atmel_port->backup_mode;
429 memset(iso7816conf, 0, sizeof(struct serial_iso7816));
430 atmel_uart_writel(port, ATMEL_US_TTGR, 0);
431 atmel_uart_writel(port, ATMEL_US_BRGR, atmel_port->backup_brgr);
432 atmel_uart_writel(port, ATMEL_US_FIDI, 0x174);
433
434 if (atmel_use_pdc_tx(port))
435 atmel_port->tx_done_mask = ATMEL_US_ENDTX |
436 ATMEL_US_TXBUFE;
437 else
438 atmel_port->tx_done_mask = ATMEL_US_TXRDY;
439 }
440
441 port->iso7816 = *iso7816conf;
442
443 atmel_uart_writel(port, ATMEL_US_MR, mode);
444
445err_out:
446 /* Enable interrupts */
447 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->tx_done_mask);
448
449 return ret;
450}
451
1e6c9c28
AV		 452/*
453 * Return TIOCSER_TEMT when transmitter FIFO and Shift register is empty.
454 */
7192f92c 455static u_int atmel_tx_empty(struct uart_port *port)
1e6c9c28 456{
ea04f82a
RI		 457 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
458
459 if (atmel_port->tx_stopped)
460 return TIOCSER_TEMT;
4e7decda
CP		 461 return (atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXEMPTY) ?
462 TIOCSER_TEMT :
463 0;
1e6c9c28
AV		 464}
465
466/*
467 * Set state of the modem control output lines
468 */
7192f92c 469static void atmel_set_mctrl(struct uart_port *port, u_int mctrl)
1e6c9c28
AV		 470{
471 unsigned int control = 0;
4e7decda 472 unsigned int mode = atmel_uart_readl(port, ATMEL_US_MR);
1cf6e8fc 473 unsigned int rts_paused, rts_ready;
e8faff73 474 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1e6c9c28 475
1cf6e8fc
CP		 476 /* override mode to RS485 if needed, otherwise keep the current mode */
477 if (port->rs485.flags & SER_RS485_ENABLED) {
4e7decda
CP		 478 atmel_uart_writel(port, ATMEL_US_TTGR,
479 port->rs485.delay_rts_after_send);
1cf6e8fc
CP		 480 mode &= ~ATMEL_US_USMODE;
481 mode |= ATMEL_US_USMODE_RS485;
482 }
483
484 /* set the RTS line state according to the mode */
485 if ((mode & ATMEL_US_USMODE) == ATMEL_US_USMODE_HWHS) {
486 /* force RTS line to high level */
487 rts_paused = ATMEL_US_RTSEN;
488
489 /* give the control of the RTS line back to the hardware */
490 rts_ready = ATMEL_US_RTSDIS;
491 } else {
492 /* force RTS line to high level */
493 rts_paused = ATMEL_US_RTSDIS;
494
495 /* force RTS line to low level */
496 rts_ready = ATMEL_US_RTSEN;
497 }
498
1e6c9c28 499 if (mctrl & TIOCM_RTS)
1cf6e8fc 500 control |= rts_ready;
1e6c9c28 501 else
1cf6e8fc 502 control |= rts_paused;
1e6c9c28
AV		 503
504 if (mctrl & TIOCM_DTR)
7192f92c 505 control |= ATMEL_US_DTREN;
1e6c9c28 506 else
7192f92c 507 control |= ATMEL_US_DTRDIS;
1e6c9c28 508
4e7decda 509 atmel_uart_writel(port, ATMEL_US_CR, control);
afefc415 510
e0b0baad
RG		 511 mctrl_gpio_set(atmel_port->gpios, mctrl);
512
afefc415 513 /* Local loopback mode? */
1cf6e8fc 514 mode &= ~ATMEL_US_CHMODE;
afefc415 515 if (mctrl & TIOCM_LOOP)
7192f92c 516 mode |= ATMEL_US_CHMODE_LOC_LOOP;
afefc415 517 else
7192f92c 518 mode |= ATMEL_US_CHMODE_NORMAL;
e8faff73 519
4e7decda 520 atmel_uart_writel(port, ATMEL_US_MR, mode);
1e6c9c28
AV		 521}
522
523/*
524 * Get state of the modem control input lines
525 */
7192f92c 526static u_int atmel_get_mctrl(struct uart_port *port)
1e6c9c28 527{
e0b0baad
RG		 528 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
529 unsigned int ret = 0, status;
1e6c9c28 530
4e7decda 531 status = atmel_uart_readl(port, ATMEL_US_CSR);
1e6c9c28
AV		 532
533 /*
534 * The control signals are active low.
535 */
7192f92c 536 if (!(status & ATMEL_US_DCD))
1e6c9c28 537 ret |= TIOCM_CD;
7192f92c 538 if (!(status & ATMEL_US_CTS))
1e6c9c28 539 ret |= TIOCM_CTS;
7192f92c 540 if (!(status & ATMEL_US_DSR))
1e6c9c28 541 ret |= TIOCM_DSR;
7192f92c 542 if (!(status & ATMEL_US_RI))
1e6c9c28
AV		 543 ret |= TIOCM_RI;
544
e0b0baad 545 return mctrl_gpio_get(atmel_port->gpios, &ret);
1e6c9c28
AV		 546}
547
548/*
549 * Stop transmitting.
550 */
7192f92c 551static void atmel_stop_tx(struct uart_port *port)
1e6c9c28 552{
e8faff73 553 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
94ec165c 554 bool is_pdc = atmel_use_pdc_tx(port);
6373ab4d 555 bool is_dma = is_pdc || atmel_use_dma_tx(port);
e8faff73 556
94ec165c 557 if (is_pdc) {
a6670615 558 /* disable PDC transmit */
4e7decda 559 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS);
e8faff73 560 }
89d82324 561
6373ab4d
JSS		 562 if (is_dma) {
563 /*
564 * Disable the transmitter.
565 * This is mandatory when DMA is used, otherwise the DMA buffer
566 * is fully transmitted.
567 */
568 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXDIS);
569 atmel_port->tx_stopped = true;
570 }
89d82324 571
e8faff73 572 /* Disable interrupts */
4e7decda 573 atmel_uart_writel(port, ATMEL_US_IDR, atmel_port->tx_done_mask);
e8faff73 574
f3040983 575 if (atmel_uart_is_half_duplex(port))
04b5bfe3
NF		 576 if (!atomic_read(&atmel_port->tasklet_shutdown))
577 atmel_start_rx(port);
1e6c9c28
AV		 578}
579
580/*
581 * Start transmitting.
582 */
7192f92c 583static void atmel_start_tx(struct uart_port *port)
1e6c9c28 584{
e8faff73 585 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
94ec165c
JSS		 586 bool is_pdc = atmel_use_pdc_tx(port);
587 bool is_dma = is_pdc || atmel_use_dma_tx(port);
e8faff73 588
94ec165c 589 if (is_pdc && (atmel_uart_readl(port, ATMEL_PDC_PTSR)
0058f087
AB		 590 & ATMEL_PDC_TXTEN))
591 /* The transmitter is already running. Yes, we
592 really need this.*/
593 return;
a6670615 594
94ec165c
JSS		 595 if (is_dma && atmel_uart_is_half_duplex(port))
596 atmel_stop_rx(port);
e8faff73 597
94ec165c 598 if (is_pdc) {
a6670615 599 /* re-enable PDC transmit */
4e7decda 600 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
94ec165c 601 }
0058f087 602
e8faff73 603 /* Enable interrupts */
4e7decda 604 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->tx_done_mask);
89d82324 605
6373ab4d
JSS		 606 if (is_dma) {
607 /* re-enable the transmitter */
608 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN);
609 atmel_port->tx_stopped = false;
610 }
e8faff73
CS		 611}
612
613/*
614 * start receiving - port is in process of being opened.
615 */
616static void atmel_start_rx(struct uart_port *port)
617{
4e7decda
CP		 618 /* reset status and receiver */
619 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
e8faff73 620
4e7decda 621 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RXEN);
57c36868 622
64e22ebe 623 if (atmel_use_pdc_rx(port)) {
e8faff73 624 /* enable PDC controller */
4e7decda
CP		 625 atmel_uart_writel(port, ATMEL_US_IER,
626 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT |
627 port->read_status_mask);
628 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN);
e8faff73 629 } else {
4e7decda 630 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_RXRDY);
e8faff73 631 }
1e6c9c28
AV		 632}
633
634/*
635 * Stop receiving - port is in process of being closed.
636 */
7192f92c 637static void atmel_stop_rx(struct uart_port *port)
1e6c9c28 638{
4e7decda 639 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RXDIS);
57c36868 640
64e22ebe 641 if (atmel_use_pdc_rx(port)) {
a6670615 642 /* disable PDC receive */
4e7decda
CP		 643 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS);
644 atmel_uart_writel(port, ATMEL_US_IDR,
645 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT |
646 port->read_status_mask);
e8faff73 647 } else {
4e7decda 648 atmel_uart_writel(port, ATMEL_US_IDR, ATMEL_US_RXRDY);
e8faff73 649 }
1e6c9c28
AV		 650}
651
652/*
653 * Enable modem status interrupts
654 */
7192f92c 655static void atmel_enable_ms(struct uart_port *port)
1e6c9c28 656{
ab5e4e41
RG		 657 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
658 uint32_t ier = 0;
659
660 /*
661 * Interrupt should not be enabled twice
662 */
663 if (atmel_port->ms_irq_enabled)
664 return;
665
666 atmel_port->ms_irq_enabled = true;
667
18dfef9c 668 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_CTS))
ab5e4e41
RG		 669 ier |= ATMEL_US_CTSIC;
670
18dfef9c 671 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DSR))
ab5e4e41
RG		 672 ier |= ATMEL_US_DSRIC;
673
18dfef9c 674 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_RI))
ab5e4e41
RG		 675 ier |= ATMEL_US_RIIC;
676
18dfef9c 677 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DCD))
ab5e4e41
RG		 678 ier |= ATMEL_US_DCDIC;
679
4e7decda 680 atmel_uart_writel(port, ATMEL_US_IER, ier);
18dfef9c
UKK		 681
682 mctrl_gpio_enable_ms(atmel_port->gpios);
1e6c9c28
AV		 683}
684
35b675b9
RG		 685/*
686 * Disable modem status interrupts
687 */
688static void atmel_disable_ms(struct uart_port *port)
689{
690 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
691 uint32_t idr = 0;
692
693 /*
694 * Interrupt should not be disabled twice
695 */
696 if (!atmel_port->ms_irq_enabled)
697 return;
698
699 atmel_port->ms_irq_enabled = false;
700
18dfef9c
UKK		 701 mctrl_gpio_disable_ms(atmel_port->gpios);
702
703 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_CTS))
35b675b9
RG		 704 idr |= ATMEL_US_CTSIC;
705
18dfef9c 706 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DSR))
35b675b9
RG		 707 idr |= ATMEL_US_DSRIC;
708
18dfef9c 709 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_RI))
35b675b9
RG		 710 idr |= ATMEL_US_RIIC;
711
18dfef9c 712 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DCD))
35b675b9
RG		 713 idr |= ATMEL_US_DCDIC;
714
4e7decda 715 atmel_uart_writel(port, ATMEL_US_IDR, idr);
35b675b9
RG		 716}
717
1e6c9c28
AV		 718/*
719 * Control the transmission of a break signal
720 */
7192f92c 721static void atmel_break_ctl(struct uart_port *port, int break_state)
1e6c9c28
AV		 722{
723 if (break_state != 0)
4e7decda
CP		 724 /* start break */
725 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTBRK);
1e6c9c28 726 else
4e7decda
CP		 727 /* stop break */
728 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STPBRK);
1e6c9c28
AV		 729}
730
1ecc26bd
RB		 731/*
732 * Stores the incoming character in the ring buffer
733 */
734static void
735atmel_buffer_rx_char(struct uart_port *port, unsigned int status,
736 unsigned int ch)
737{
c811ab8c 738 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1ecc26bd
RB		 739 struct circ_buf *ring = &atmel_port->rx_ring;
740 struct atmel_uart_char *c;
741
742 if (!CIRC_SPACE(ring->head, ring->tail, ATMEL_SERIAL_RINGSIZE))
743 /* Buffer overflow, ignore char */
744 return;
745
746 c = &((struct atmel_uart_char *)ring->buf)[ring->head];
747 c->status = status;
748 c->ch = ch;
749
750 /* Make sure the character is stored before we update head. */
751 smp_wmb();
752
753 ring->head = (ring->head + 1) & (ATMEL_SERIAL_RINGSIZE - 1);
754}
755
a6670615
CC		 756/*
757 * Deal with parity, framing and overrun errors.
758 */
759static void atmel_pdc_rxerr(struct uart_port *port, unsigned int status)
760{
761 /* clear error */
4e7decda 762 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
a6670615
CC		 763
764 if (status & ATMEL_US_RXBRK) {
765 /* ignore side-effect */
766 status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME);
767 port->icount.brk++;
768 }
769 if (status & ATMEL_US_PARE)
770 port->icount.parity++;
771 if (status & ATMEL_US_FRAME)
772 port->icount.frame++;
773 if (status & ATMEL_US_OVRE)
774 port->icount.overrun++;
775}
776
1e6c9c28
AV		 777/*
778 * Characters received (called from interrupt handler)
779 */
7d12e780 780static void atmel_rx_chars(struct uart_port *port)
1e6c9c28 781{
c811ab8c 782 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1ecc26bd 783 unsigned int status, ch;
1e6c9c28 784
4e7decda 785 status = atmel_uart_readl(port, ATMEL_US_CSR);
7192f92c 786 while (status & ATMEL_US_RXRDY) {
a6499435 787 ch = atmel_uart_read_char(port);
1e6c9c28 788
1e6c9c28
AV		 789 /*
790 * note that the error handling code is
791 * out of the main execution path
792 */
9e6077bd
HS		 793 if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME
794 | ATMEL_US_OVRE | ATMEL_US_RXBRK)
795 || atmel_port->break_active)) {
1ecc26bd 796
b843aa21 797 /* clear error */
4e7decda 798 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
1ecc26bd 799
9e6077bd
HS		 800 if (status & ATMEL_US_RXBRK
801 && !atmel_port->break_active) {
9e6077bd 802 atmel_port->break_active = 1;
4e7decda
CP		 803 atmel_uart_writel(port, ATMEL_US_IER,
804 ATMEL_US_RXBRK);
9e6077bd
HS		 805 } else {
806 /*
807 * This is either the end-of-break
808 * condition or we've received at
809 * least one character without RXBRK
810 * being set. In both cases, the next
811 * RXBRK will indicate start-of-break.
812 */
4e7decda
CP		 813 atmel_uart_writel(port, ATMEL_US_IDR,
814 ATMEL_US_RXBRK);
9e6077bd
HS		 815 status &= ~ATMEL_US_RXBRK;
816 atmel_port->break_active = 0;
afefc415 817 }
1e6c9c28
AV		 818 }
819
1ecc26bd 820 atmel_buffer_rx_char(port, status, ch);
4e7decda 821 status = atmel_uart_readl(port, ATMEL_US_CSR);
1e6c9c28
AV		 822 }
823
98f2082c 824 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_rx);
1e6c9c28
AV		 825}
826
827/*
1ecc26bd
RB		 828 * Transmit characters (called from tasklet with TXRDY interrupt
829 * disabled)
1e6c9c28 830 */
7192f92c 831static void atmel_tx_chars(struct uart_port *port)
1e6c9c28 832{
e8faff73 833 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2d141e68
JSS		 834 bool pending;
835 u8 ch;
1e6c9c28 836
2d141e68
JSS		 837 pending = uart_port_tx(port, ch,
838 atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXRDY,
839 atmel_uart_write_char(port, ch));
840 if (pending) {
477b8383
CC		 841 /* we still have characters to transmit, so we should continue
842 * transmitting them when TX is ready, regardless of
843 * mode or duplexity
844 */
845 atmel_port->tx_done_mask |= ATMEL_US_TXRDY;
846
e8faff73 847 /* Enable interrupts */
4e7decda
CP		 848 atmel_uart_writel(port, ATMEL_US_IER,
849 atmel_port->tx_done_mask);
477b8383
CC		 850 } else {
851 if (atmel_uart_is_half_duplex(port))
852 atmel_port->tx_done_mask &= ~ATMEL_US_TXRDY;
853 }
1e6c9c28
AV		 854}
855
08f738be
ES		 856static void atmel_complete_tx_dma(void *arg)
857{
858 struct atmel_uart_port *atmel_port = arg;
859 struct uart_port *port = &atmel_port->uart;
1788cf6a 860 struct tty_port *tport = &port->state->port;
08f738be
ES		 861 struct dma_chan *chan = atmel_port->chan_tx;
862 unsigned long flags;
863
cb9936f8 864 uart_port_lock_irqsave(port, &flags);
08f738be
ES		 865
866 if (chan)
867 dmaengine_terminate_all(chan);
add147a4 868 uart_xmit_advance(port, atmel_port->tx_len);
08f738be 869
27a82683 870 spin_lock(&atmel_port->lock_tx);
08f738be
ES		 871 async_tx_ack(atmel_port->desc_tx);
872 atmel_port->cookie_tx = -EINVAL;
873 atmel_port->desc_tx = NULL;
27a82683 874 spin_unlock(&atmel_port->lock_tx);
08f738be 875
1788cf6a 876 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS)
08f738be
ES		 877 uart_write_wakeup(port);
878
1842dc2e 879 /*
1788cf6a
JSS		 880 * xmit is a circular buffer so, if we have just send data from the
881 * tail to the end, now we have to transmit the remaining data from the
882 * beginning to the head.
1842dc2e 883 */
1788cf6a 884 if (!kfifo_is_empty(&tport->xmit_fifo))
98f2082c 885 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_tx);
f3040983 886 else if (atmel_uart_is_half_duplex(port)) {
69646d7a
RS		 887 /*
888 * DMA done, re-enable TXEMPTY and signal that we can stop
889 * TX and start RX for RS485
890 */
891 atmel_port->hd_start_rx = true;
892 atmel_uart_writel(port, ATMEL_US_IER,
893 atmel_port->tx_done_mask);
b389f173 894 }
08f738be 895
cb9936f8 896 uart_port_unlock_irqrestore(port, flags);
08f738be
ES		 897}
898
899static void atmel_release_tx_dma(struct uart_port *port)
900{
901 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
902 struct dma_chan *chan = atmel_port->chan_tx;
903
904 if (chan) {
905 dmaengine_terminate_all(chan);
906 dma_release_channel(chan);
907 dma_unmap_sg(port->dev, &atmel_port->sg_tx, 1,
48479148 908 DMA_TO_DEVICE);
08f738be
ES		 909 }
910
911 atmel_port->desc_tx = NULL;
912 atmel_port->chan_tx = NULL;
913 atmel_port->cookie_tx = -EINVAL;
914}
915
916/*
917 * Called from tasklet with TXRDY interrupt is disabled.
918 */
919static void atmel_tx_dma(struct uart_port *port)
920{
921 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1788cf6a 922 struct tty_port *tport = &port->state->port;
08f738be
ES		 923 struct dma_chan *chan = atmel_port->chan_tx;
924 struct dma_async_tx_descriptor *desc;
5f258b3e 925 struct scatterlist sgl[2], *sg, *sg_tx = &atmel_port->sg_tx;
1788cf6a 926 unsigned int tx_len, tail, part1_len, part2_len, sg_len;
5f258b3e 927 dma_addr_t phys_addr;
08f738be
ES		 928
929 /* Make sure we have an idle channel */
930 if (atmel_port->desc_tx != NULL)
931 return;
932
1788cf6a 933 if (!kfifo_is_empty(&tport->xmit_fifo) && !uart_tx_stopped(port)) {
08f738be
ES		 934 /*
935 * DMA is idle now.
936 * Port xmit buffer is already mapped,
937 * and it is one page... Just adjust
938 * offsets and lengths. Since it is a circular buffer,
939 * we have to transmit till the end, and then the rest.
940 * Take the port lock to get a
941 * consistent xmit buffer state.
942 */
1788cf6a
JSS		 943 tx_len = kfifo_out_linear(&tport->xmit_fifo, &tail,
944 UART_XMIT_SIZE);
5f258b3e
CP		 945
946 if (atmel_port->fifo_size) {
947 /* multi data mode */
948 part1_len = (tx_len & ~0x3); /* DWORD access */
949 part2_len = (tx_len & 0x3); /* BYTE access */
950 } else {
951 /* single data (legacy) mode */
952 part1_len = 0;
953 part2_len = tx_len; /* BYTE access only */
954 }
955
956 sg_init_table(sgl, 2);
957 sg_len = 0;
1788cf6a 958 phys_addr = sg_dma_address(sg_tx) + tail;
5f258b3e
CP		 959 if (part1_len) {
960 sg = &sgl[sg_len++];
961 sg_dma_address(sg) = phys_addr;
962 sg_dma_len(sg) = part1_len;
963
964 phys_addr += part1_len;
965 }
966
967 if (part2_len) {
968 sg = &sgl[sg_len++];
969 sg_dma_address(sg) = phys_addr;
970 sg_dma_len(sg) = part2_len;
971 }
972
973 /*
974 * save tx_len so atmel_complete_tx_dma() will increase
1788cf6a 975 * tail correctly
5f258b3e
CP		 976 */
977 atmel_port->tx_len = tx_len;
08f738be
ES		 978
979 desc = dmaengine_prep_slave_sg(chan,
5f258b3e
CP		 980 sgl,
981 sg_len,
1842dc2e
CP		 982 DMA_MEM_TO_DEV,
983 DMA_PREP_INTERRUPT |
984 DMA_CTRL_ACK);
08f738be
ES		 985 if (!desc) {
986 dev_err(port->dev, "Failed to send via dma!\n");
987 return;
988 }
989
5f258b3e 990 dma_sync_sg_for_device(port->dev, sg_tx, 1, DMA_TO_DEVICE);
08f738be
ES		 991
992 atmel_port->desc_tx = desc;
993 desc->callback = atmel_complete_tx_dma;
994 desc->callback_param = atmel_port;
995 atmel_port->cookie_tx = dmaengine_submit(desc);
1e67bd2b
TA		 996 if (dma_submit_error(atmel_port->cookie_tx)) {
997 dev_err(port->dev, "dma_submit_error %d\n",
998 atmel_port->cookie_tx);
999 return;
1000 }
4f4b9b58
TA		 1001
1002 dma_async_issue_pending(chan);
08f738be
ES		 1003 }
1004
1788cf6a 1005 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS)
08f738be
ES		 1006 uart_write_wakeup(port);
1007}
1008
1009static int atmel_prepare_tx_dma(struct uart_port *port)
1010{
1011 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1788cf6a 1012 struct tty_port *tport = &port->state->port;
c24d2531 1013 struct device *mfd_dev = port->dev->parent;
08f738be
ES		 1014 dma_cap_mask_t mask;
1015 struct dma_slave_config config;
ec9fc2cf 1016 struct dma_chan *chan;
08f738be
ES		 1017 int ret, nent;
1018
1019 dma_cap_zero(mask);
1020 dma_cap_set(DMA_SLAVE, mask);
1021
ec9fc2cf
CJ		 1022 chan = dma_request_chan(mfd_dev, "tx");
1023 if (IS_ERR(chan)) {
1024 atmel_port->chan_tx = NULL;
08f738be 1025 goto chan_err;
ec9fc2cf
CJ		 1026 }
1027 atmel_port->chan_tx = chan;
08f738be
ES		 1028 dev_info(port->dev, "using %s for tx DMA transfers\n",
1029 dma_chan_name(atmel_port->chan_tx));
1030
1031 spin_lock_init(&atmel_port->lock_tx);
1032 sg_init_table(&atmel_port->sg_tx, 1);
1033 /* UART circular tx buffer is an aligned page. */
1788cf6a 1034 BUG_ON(!PAGE_ALIGNED(tport->xmit_buf));
08f738be 1035 sg_set_page(&atmel_port->sg_tx,
1788cf6a 1036 virt_to_page(tport->xmit_buf),
08f738be 1037 UART_XMIT_SIZE,
1788cf6a 1038 offset_in_page(tport->xmit_buf));
08f738be
ES		 1039 nent = dma_map_sg(port->dev,
1040 &atmel_port->sg_tx,
1041 1,
48479148 1042 DMA_TO_DEVICE);
08f738be
ES		 1043
1044 if (!nent) {
1045 dev_dbg(port->dev, "need to release resource of dma\n");
1046 goto chan_err;
1047 } else {
c8d1f022 1048 dev_dbg(port->dev, "%s: mapped %d@%p to %pad\n", __func__,
08f738be 1049 sg_dma_len(&atmel_port->sg_tx),
1788cf6a 1050 tport->xmit_buf,
c8d1f022 1051 &sg_dma_address(&atmel_port->sg_tx));
08f738be
ES		 1052 }
1053
1054 /* Configure the slave DMA */
1055 memset(&config, 0, sizeof(config));
1056 config.direction = DMA_MEM_TO_DEV;
5f258b3e
CP		 1057 config.dst_addr_width = (atmel_port->fifo_size) ?
1058 DMA_SLAVE_BUSWIDTH_4_BYTES :
1059 DMA_SLAVE_BUSWIDTH_1_BYTE;
08f738be 1060 config.dst_addr = port->mapbase + ATMEL_US_THR;
a8d4e016 1061 config.dst_maxburst = 1;
08f738be 1062
5483c10e
MR		 1063 ret = dmaengine_slave_config(atmel_port->chan_tx,
1064 &config);
08f738be
ES		 1065 if (ret) {
1066 dev_err(port->dev, "DMA tx slave configuration failed\n");
1067 goto chan_err;
1068 }
1069
1070 return 0;
1071
1072chan_err:
1073 dev_err(port->dev, "TX channel not available, switch to pio\n");
36ce7cff 1074 atmel_port->use_dma_tx = false;
08f738be
ES		 1075 if (atmel_port->chan_tx)
1076 atmel_release_tx_dma(port);
1077 return -EINVAL;
1078}
1079
34df42f5
ES		 1080static void atmel_complete_rx_dma(void *arg)
1081{
1082 struct uart_port *port = arg;
1083 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1084
98f2082c 1085 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_rx);
34df42f5
ES		 1086}
1087
1088static void atmel_release_rx_dma(struct uart_port *port)
1089{
1090 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1091 struct dma_chan *chan = atmel_port->chan_rx;
1092
1093 if (chan) {
1094 dmaengine_terminate_all(chan);
1095 dma_release_channel(chan);
1096 dma_unmap_sg(port->dev, &atmel_port->sg_rx, 1,
48479148 1097 DMA_FROM_DEVICE);
34df42f5
ES		 1098 }
1099
1100 atmel_port->desc_rx = NULL;
1101 atmel_port->chan_rx = NULL;
1102 atmel_port->cookie_rx = -EINVAL;
1103}
1104
1105static void atmel_rx_from_dma(struct uart_port *port)
1106{
1107 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
66f37aaf 1108 struct tty_port *tport = &port->state->port;
34df42f5
ES		 1109 struct circ_buf *ring = &atmel_port->rx_ring;
1110 struct dma_chan *chan = atmel_port->chan_rx;
1111 struct dma_tx_state state;
1112 enum dma_status dmastat;
66f37aaf 1113 size_t count;
34df42f5
ES		 1114
1115
1116 /* Reset the UART timeout early so that we don't miss one */
4e7decda 1117 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
34df42f5
ES		 1118 dmastat = dmaengine_tx_status(chan,
1119 atmel_port->cookie_rx,
1120 &state);
1121 /* Restart a new tasklet if DMA status is error */
1122 if (dmastat == DMA_ERROR) {
1123 dev_dbg(port->dev, "Get residue error, restart tasklet\n");
4e7decda 1124 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_TIMEOUT);
98f2082c 1125 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_rx);
34df42f5
ES		 1126 return;
1127 }
34df42f5 1128
66f37aaf
CP		 1129 /* CPU claims ownership of RX DMA buffer */
1130 dma_sync_sg_for_cpu(port->dev,
1131 &atmel_port->sg_rx,
1132 1,
485819b5 1133 DMA_FROM_DEVICE);
66f37aaf
CP		 1134
1135 /*
1136 * ring->head points to the end of data already written by the DMA.
1137 * ring->tail points to the beginning of data to be read by the
1138 * framework.
1139 * The current transfer size should not be larger than the dma buffer
1140 * length.
1141 */
1142 ring->head = sg_dma_len(&atmel_port->sg_rx) - state.residue;
1143 BUG_ON(ring->head > sg_dma_len(&atmel_port->sg_rx));
34df42f5 1144 /*
66f37aaf
CP		 1145 * At this point ring->head may point to the first byte right after the
1146 * last byte of the dma buffer:
1147 * 0 <= ring->head <= sg_dma_len(&atmel_port->sg_rx)
1148 *
1149 * However ring->tail must always points inside the dma buffer:
1150 * 0 <= ring->tail <= sg_dma_len(&atmel_port->sg_rx) - 1
1151 *
1152 * Since we use a ring buffer, we have to handle the case
1153 * where head is lower than tail. In such a case, we first read from
1154 * tail to the end of the buffer then reset tail.
34df42f5 1155 */
66f37aaf
CP		 1156 if (ring->head < ring->tail) {
1157 count = sg_dma_len(&atmel_port->sg_rx) - ring->tail;
34df42f5 1158
66f37aaf
CP		 1159 tty_insert_flip_string(tport, ring->buf + ring->tail, count);
1160 ring->tail = 0;
1161 port->icount.rx += count;
1162 }
34df42f5 1163
66f37aaf
CP		 1164 /* Finally we read data from tail to head */
1165 if (ring->tail < ring->head) {
1166 count = ring->head - ring->tail;
34df42f5 1167
66f37aaf
CP		 1168 tty_insert_flip_string(tport, ring->buf + ring->tail, count);
1169 /* Wrap ring->head if needed */
1170 if (ring->head >= sg_dma_len(&atmel_port->sg_rx))
1171 ring->head = 0;
1172 ring->tail = ring->head;
34df42f5
ES		 1173 port->icount.rx += count;
1174 }
1175
66f37aaf
CP		 1176 /* USART retreives ownership of RX DMA buffer */
1177 dma_sync_sg_for_device(port->dev,
1178 &atmel_port->sg_rx,
1179 1,
485819b5 1180 DMA_FROM_DEVICE);
66f37aaf 1181
66f37aaf 1182 tty_flip_buffer_push(tport);
66f37aaf 1183
4e7decda 1184 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_TIMEOUT);
34df42f5
ES		 1185}
1186
1187static int atmel_prepare_rx_dma(struct uart_port *port)
1188{
1189 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
c24d2531 1190 struct device *mfd_dev = port->dev->parent;
34df42f5
ES		 1191 struct dma_async_tx_descriptor *desc;
1192 dma_cap_mask_t mask;
1193 struct dma_slave_config config;
1194 struct circ_buf *ring;
ec9fc2cf 1195 struct dma_chan *chan;
34df42f5
ES		 1196 int ret, nent;
1197
1198 ring = &atmel_port->rx_ring;
1199
1200 dma_cap_zero(mask);
1201 dma_cap_set(DMA_CYCLIC, mask);
1202
ec9fc2cf
CJ		 1203 chan = dma_request_chan(mfd_dev, "rx");
1204 if (IS_ERR(chan)) {
1205 atmel_port->chan_rx = NULL;
34df42f5 1206 goto chan_err;
ec9fc2cf
CJ		 1207 }
1208 atmel_port->chan_rx = chan;
34df42f5
ES		 1209 dev_info(port->dev, "using %s for rx DMA transfers\n",
1210 dma_chan_name(atmel_port->chan_rx));
1211
1212 spin_lock_init(&atmel_port->lock_rx);
1213 sg_init_table(&atmel_port->sg_rx, 1);
1214 /* UART circular rx buffer is an aligned page. */
2c277054 1215 BUG_ON(!PAGE_ALIGNED(ring->buf));
34df42f5 1216 sg_set_page(&atmel_port->sg_rx,
1842dc2e 1217 virt_to_page(ring->buf),
a510880f 1218 sizeof(struct atmel_uart_char) * ATMEL_SERIAL_RINGSIZE,
2b5cf14b 1219 offset_in_page(ring->buf));
1842dc2e
CP		 1220 nent = dma_map_sg(port->dev,
1221 &atmel_port->sg_rx,
1222 1,
1223 DMA_FROM_DEVICE);
34df42f5
ES		 1224
1225 if (!nent) {
1226 dev_dbg(port->dev, "need to release resource of dma\n");
1227 goto chan_err;
1228 } else {
c8d1f022 1229 dev_dbg(port->dev, "%s: mapped %d@%p to %pad\n", __func__,
34df42f5
ES		 1230 sg_dma_len(&atmel_port->sg_rx),
1231 ring->buf,
c8d1f022 1232 &sg_dma_address(&atmel_port->sg_rx));
34df42f5
ES		 1233 }
1234
1235 /* Configure the slave DMA */
1236 memset(&config, 0, sizeof(config));
1237 config.direction = DMA_DEV_TO_MEM;
1238 config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1239 config.src_addr = port->mapbase + ATMEL_US_RHR;
a8d4e016 1240 config.src_maxburst = 1;
34df42f5 1241
5483c10e
MR		 1242 ret = dmaengine_slave_config(atmel_port->chan_rx,
1243 &config);
34df42f5
ES		 1244 if (ret) {
1245 dev_err(port->dev, "DMA rx slave configuration failed\n");
1246 goto chan_err;
1247 }
1248 /*
1249 * Prepare a cyclic dma transfer, assign 2 descriptors,
1250 * each one is half ring buffer size
1251 */
1252 desc = dmaengine_prep_dma_cyclic(atmel_port->chan_rx,
1842dc2e
CP		 1253 sg_dma_address(&atmel_port->sg_rx),
1254 sg_dma_len(&atmel_port->sg_rx),
1255 sg_dma_len(&atmel_port->sg_rx)/2,
1256 DMA_DEV_TO_MEM,
1257 DMA_PREP_INTERRUPT);
c85be041
KL		 1258 if (!desc) {
1259 dev_err(port->dev, "Preparing DMA cyclic failed\n");
1260 goto chan_err;
1261 }
34df42f5
ES		 1262 desc->callback = atmel_complete_rx_dma;
1263 desc->callback_param = port;
1264 atmel_port->desc_rx = desc;
1265 atmel_port->cookie_rx = dmaengine_submit(desc);
1e67bd2b
TA		 1266 if (dma_submit_error(atmel_port->cookie_rx)) {
1267 dev_err(port->dev, "dma_submit_error %d\n",
1268 atmel_port->cookie_rx);
1269 goto chan_err;
1270 }
34df42f5 1271
4f4b9b58
TA		 1272 dma_async_issue_pending(atmel_port->chan_rx);
1273
34df42f5
ES		 1274 return 0;
1275
1276chan_err:
1277 dev_err(port->dev, "RX channel not available, switch to pio\n");
36ce7cff 1278 atmel_port->use_dma_rx = false;
34df42f5
ES		 1279 if (atmel_port->chan_rx)
1280 atmel_release_rx_dma(port);
1281 return -EINVAL;
1282}
1283
026cb432 1284static void atmel_uart_timer_callback(struct timer_list *t)
2e68c22f 1285{
026cb432
KC		 1286 struct atmel_uart_port *atmel_port = from_timer(atmel_port, t,
1287 uart_timer);
1288 struct uart_port *port = &atmel_port->uart;
2e68c22f 1289
98f2082c
NF		 1290 if (!atomic_read(&atmel_port->tasklet_shutdown)) {
1291 tasklet_schedule(&atmel_port->tasklet_rx);
1292 mod_timer(&atmel_port->uart_timer,
1293 jiffies + uart_poll_timeout(port));
1294 }
2e68c22f
ES		 1295}
1296
b843aa21
RB		 1297/*
1298 * receive interrupt handler.
1299 */
1300static void
1301atmel_handle_receive(struct uart_port *port, unsigned int pending)
1302{
c811ab8c 1303 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
b843aa21 1304
64e22ebe 1305 if (atmel_use_pdc_rx(port)) {
a6670615
CC		 1306 /*
1307 * PDC receive. Just schedule the tasklet and let it
1308 * figure out the details.
1309 *
1310 * TODO: We're not handling error flags correctly at
1311 * the moment.
1312 */
1313 if (pending & (ATMEL_US_ENDRX | ATMEL_US_TIMEOUT)) {
4e7decda
CP		 1314 atmel_uart_writel(port, ATMEL_US_IDR,
1315 (ATMEL_US_ENDRX | ATMEL_US_TIMEOUT));
98f2082c
NF		 1316 atmel_tasklet_schedule(atmel_port,
1317 &atmel_port->tasklet_rx);
a6670615
CC		 1318 }
1319
1320 if (pending & (ATMEL_US_RXBRK | ATMEL_US_OVRE |
1321 ATMEL_US_FRAME | ATMEL_US_PARE))
1322 atmel_pdc_rxerr(port, pending);
1323 }
1324
34df42f5
ES		 1325 if (atmel_use_dma_rx(port)) {
1326 if (pending & ATMEL_US_TIMEOUT) {
4e7decda
CP		 1327 atmel_uart_writel(port, ATMEL_US_IDR,
1328 ATMEL_US_TIMEOUT);
98f2082c
NF		 1329 atmel_tasklet_schedule(atmel_port,
1330 &atmel_port->tasklet_rx);
34df42f5
ES		 1331 }
1332 }
1333
b843aa21
RB		 1334 /* Interrupt receive */
1335 if (pending & ATMEL_US_RXRDY)
1336 atmel_rx_chars(port);
1337 else if (pending & ATMEL_US_RXBRK) {
1338 /*
1339 * End of break detected. If it came along with a
1340 * character, atmel_rx_chars will handle it.
1341 */
4e7decda
CP		 1342 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
1343 atmel_uart_writel(port, ATMEL_US_IDR, ATMEL_US_RXBRK);
b843aa21
RB		 1344 atmel_port->break_active = 0;
1345 }
1346}
1347
1348/*
1ecc26bd 1349 * transmit interrupt handler. (Transmit is IRQF_NODELAY safe)
b843aa21
RB		 1350 */
1351static void
1352atmel_handle_transmit(struct uart_port *port, unsigned int pending)
1353{
c811ab8c 1354 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1ecc26bd 1355
e8faff73 1356 if (pending & atmel_port->tx_done_mask) {
4e7decda
CP		 1357 atmel_uart_writel(port, ATMEL_US_IDR,
1358 atmel_port->tx_done_mask);
69646d7a
RS		 1359
1360 /* Start RX if flag was set and FIFO is empty */
1361 if (atmel_port->hd_start_rx) {
1362 if (!(atmel_uart_readl(port, ATMEL_US_CSR)
1363 & ATMEL_US_TXEMPTY))
1364 dev_warn(port->dev, "Should start RX, but TX fifo is not empty\n");
1365
1366 atmel_port->hd_start_rx = false;
1367 atmel_start_rx(port);
69646d7a
RS		 1368 }
1369
98f2082c 1370 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_tx);
1ecc26bd 1371 }
b843aa21
RB		 1372}
1373
1374/*
1375 * status flags interrupt handler.
1376 */
1377static void
1378atmel_handle_status(struct uart_port *port, unsigned int pending,
1379 unsigned int status)
1380{
c811ab8c 1381 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
9205218e 1382 unsigned int status_change;
1ecc26bd 1383
b843aa21 1384 if (pending & (ATMEL_US_RIIC | ATMEL_US_DSRIC | ATMEL_US_DCDIC
1ecc26bd 1385 | ATMEL_US_CTSIC)) {
9205218e 1386 status_change = status ^ atmel_port->irq_status_prev;
d033e82d 1387 atmel_port->irq_status_prev = status;
9205218e
NF		 1388
1389 if (status_change & (ATMEL_US_RI | ATMEL_US_DSR
1390 | ATMEL_US_DCD | ATMEL_US_CTS)) {
1391 /* TODO: All reads to CSR will clear these interrupts! */
1392 if (status_change & ATMEL_US_RI)
1393 port->icount.rng++;
1394 if (status_change & ATMEL_US_DSR)
1395 port->icount.dsr++;
1396 if (status_change & ATMEL_US_DCD)
1397 uart_handle_dcd_change(port, !(status & ATMEL_US_DCD));
1398 if (status_change & ATMEL_US_CTS)
1399 uart_handle_cts_change(port, !(status & ATMEL_US_CTS));
1400
1401 wake_up_interruptible(&port->state->port.delta_msr_wait);
1402 }
1ecc26bd 1403 }
377fedd1
NF		 1404
1405 if (pending & (ATMEL_US_NACK | ATMEL_US_ITERATION))
1406 dev_dbg(port->dev, "ISO7816 ERROR (0x%08x)\n", pending);
b843aa21
RB		 1407}
1408
1e6c9c28
AV		 1409/*
1410 * Interrupt handler
1411 */
7d12e780 1412static irqreturn_t atmel_interrupt(int irq, void *dev_id)
1e6c9c28
AV		 1413{
1414 struct uart_port *port = dev_id;
ab5e4e41 1415 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2c7af5ba 1416 unsigned int status, pending, mask, pass_counter = 0;
1e6c9c28 1417
2c7af5ba
BB		 1418 spin_lock(&atmel_port->lock_suspended);
1419
a6670615 1420 do {
d2d8d4c0 1421 status = atmel_uart_readl(port, ATMEL_US_CSR);
4e7decda 1422 mask = atmel_uart_readl(port, ATMEL_US_IMR);
2c7af5ba 1423 pending = status & mask;
a6670615
CC		 1424 if (!pending)
1425 break;
1426
2c7af5ba
BB		 1427 if (atmel_port->suspended) {
1428 atmel_port->pending |= pending;
1429 atmel_port->pending_status = status;
4e7decda 1430 atmel_uart_writel(port, ATMEL_US_IDR, mask);
2c7af5ba
BB		 1431 pm_system_wakeup();
1432 break;
1433 }
1434
b843aa21
RB		 1435 atmel_handle_receive(port, pending);
1436 atmel_handle_status(port, pending, status);
1437 atmel_handle_transmit(port, pending);
a6670615 1438 } while (pass_counter++ < ATMEL_ISR_PASS_LIMIT);
afefc415 1439
2c7af5ba
BB		 1440 spin_unlock(&atmel_port->lock_suspended);
1441
0400b697 1442 return pass_counter ? IRQ_HANDLED : IRQ_NONE;
a6670615 1443}
1e6c9c28 1444
a930e528
ES		 1445static void atmel_release_tx_pdc(struct uart_port *port)
1446{
1447 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1448 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1449
1450 dma_unmap_single(port->dev,
1451 pdc->dma_addr,
1452 pdc->dma_size,
1453 DMA_TO_DEVICE);
1454}
1455
a6670615
CC		 1456/*
1457 * Called from tasklet with ENDTX and TXBUFE interrupts disabled.
1458 */
64e22ebe 1459static void atmel_tx_pdc(struct uart_port *port)
a6670615 1460{
c811ab8c 1461 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1788cf6a 1462 struct tty_port *tport = &port->state->port;
a6670615 1463 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
a6670615 1464
ba0657ff 1465 /* nothing left to transmit? */
4e7decda 1466 if (atmel_uart_readl(port, ATMEL_PDC_TCR))
ba0657ff 1467 return;
add147a4 1468 uart_xmit_advance(port, pdc->ofs);
a6670615
CC		 1469 pdc->ofs = 0;
1470
ba0657ff 1471 /* more to transmit - setup next transfer */
a6670615 1472
ba0657ff 1473 /* disable PDC transmit */
4e7decda 1474 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS);
ba0657ff 1475
1788cf6a
JSS		 1476 if (!kfifo_is_empty(&tport->xmit_fifo) && !uart_tx_stopped(port)) {
1477 unsigned int count, tail;
1478
a6670615
CC		 1479 dma_sync_single_for_device(port->dev,
1480 pdc->dma_addr,
1481 pdc->dma_size,
1482 DMA_TO_DEVICE);
1483
1788cf6a
JSS		 1484 count = kfifo_out_linear(&tport->xmit_fifo, &tail,
1485 UART_XMIT_SIZE);
a6670615
CC		 1486 pdc->ofs = count;
1487
1788cf6a 1488 atmel_uart_writel(port, ATMEL_PDC_TPR, pdc->dma_addr + tail);
4e7decda 1489 atmel_uart_writel(port, ATMEL_PDC_TCR, count);
e8faff73 1490 /* re-enable PDC transmit */
4e7decda 1491 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
e8faff73 1492 /* Enable interrupts */
4e7decda
CP		 1493 atmel_uart_writel(port, ATMEL_US_IER,
1494 atmel_port->tx_done_mask);
e8faff73 1495 } else {
f3040983 1496 if (atmel_uart_is_half_duplex(port)) {
e8faff73
CS		 1497 /* DMA done, stop TX, start RX for RS485 */
1498 atmel_start_rx(port);
1499 }
1e6c9c28 1500 }
a6670615 1501
1788cf6a 1502 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS)
a6670615 1503 uart_write_wakeup(port);
1e6c9c28
AV		 1504}
1505
a930e528
ES		 1506static int atmel_prepare_tx_pdc(struct uart_port *port)
1507{
1508 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1509 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1788cf6a 1510 struct tty_port *tport = &port->state->port;
a930e528 1511
1788cf6a 1512 pdc->buf = tport->xmit_buf;
a930e528
ES		 1513 pdc->dma_addr = dma_map_single(port->dev,
1514 pdc->buf,
1515 UART_XMIT_SIZE,
1516 DMA_TO_DEVICE);
1517 pdc->dma_size = UART_XMIT_SIZE;
1518 pdc->ofs = 0;
1519
1520 return 0;
1521}
1522
1ecc26bd
RB		 1523static void atmel_rx_from_ring(struct uart_port *port)
1524{
c811ab8c 1525 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1ecc26bd 1526 struct circ_buf *ring = &atmel_port->rx_ring;
1ecc26bd 1527 unsigned int status;
fd2b55f8 1528 u8 flg;
1ecc26bd
RB		 1529
1530 while (ring->head != ring->tail) {
1531 struct atmel_uart_char c;
1532
1533 /* Make sure c is loaded after head. */
1534 smp_rmb();
1535
1536 c = ((struct atmel_uart_char *)ring->buf)[ring->tail];
1537
1538 ring->tail = (ring->tail + 1) & (ATMEL_SERIAL_RINGSIZE - 1);
1539
1540 port->icount.rx++;
1541 status = c.status;
1542 flg = TTY_NORMAL;
1543
1544 /*
1545 * note that the error handling code is
1546 * out of the main execution path
1547 */
1548 if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME
1549 | ATMEL_US_OVRE | ATMEL_US_RXBRK))) {
1550 if (status & ATMEL_US_RXBRK) {
1551 /* ignore side-effect */
1552 status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME);
1553
1554 port->icount.brk++;
1555 if (uart_handle_break(port))
1556 continue;
1557 }
1558 if (status & ATMEL_US_PARE)
1559 port->icount.parity++;
1560 if (status & ATMEL_US_FRAME)
1561 port->icount.frame++;
1562 if (status & ATMEL_US_OVRE)
1563 port->icount.overrun++;
1564
1565 status &= port->read_status_mask;
1566
1567 if (status & ATMEL_US_RXBRK)
1568 flg = TTY_BREAK;
1569 else if (status & ATMEL_US_PARE)
1570 flg = TTY_PARITY;
1571 else if (status & ATMEL_US_FRAME)
1572 flg = TTY_FRAME;
1573 }
1574
1575
1576 if (uart_handle_sysrq_char(port, c.ch))
1577 continue;
1578
1579 uart_insert_char(port, status, ATMEL_US_OVRE, c.ch, flg);
1580 }
1581
2e124b4a 1582 tty_flip_buffer_push(&port->state->port);
1ecc26bd
RB		 1583}
1584
a930e528
ES		 1585static void atmel_release_rx_pdc(struct uart_port *port)
1586{
1587 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1588 int i;
1589
1590 for (i = 0; i < 2; i++) {
1591 struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i];
1592
1593 dma_unmap_single(port->dev,
1594 pdc->dma_addr,
1595 pdc->dma_size,
1596 DMA_FROM_DEVICE);
1597 kfree(pdc->buf);
1598 }
1599}
1600
64e22ebe 1601static void atmel_rx_from_pdc(struct uart_port *port)
a6670615 1602{
c811ab8c 1603 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
05c7cd39 1604 struct tty_port *tport = &port->state->port;
a6670615
CC		 1605 struct atmel_dma_buffer *pdc;
1606 int rx_idx = atmel_port->pdc_rx_idx;
1607 unsigned int head;
1608 unsigned int tail;
1609 unsigned int count;
1610
1611 do {
1612 /* Reset the UART timeout early so that we don't miss one */
4e7decda 1613 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
a6670615
CC		 1614
1615 pdc = &atmel_port->pdc_rx[rx_idx];
4e7decda 1616 head = atmel_uart_readl(port, ATMEL_PDC_RPR) - pdc->dma_addr;
a6670615
CC		 1617 tail = pdc->ofs;
1618
1619 /* If the PDC has switched buffers, RPR won't contain
1620 * any address within the current buffer. Since head
1621 * is unsigned, we just need a one-way comparison to
1622 * find out.
1623 *
1624 * In this case, we just need to consume the entire
1625 * buffer and resubmit it for DMA. This will clear the
1626 * ENDRX bit as well, so that we can safely re-enable
1627 * all interrupts below.
1628 */
1629 head = min(head, pdc->dma_size);
1630
1631 if (likely(head != tail)) {
1632 dma_sync_single_for_cpu(port->dev, pdc->dma_addr,
1633 pdc->dma_size, DMA_FROM_DEVICE);
1634
1635 /*
1636 * head will only wrap around when we recycle
1637 * the DMA buffer, and when that happens, we
1638 * explicitly set tail to 0. So head will
1639 * always be greater than tail.
1640 */
1641 count = head - tail;
1642
05c7cd39
JS		 1643 tty_insert_flip_string(tport, pdc->buf + pdc->ofs,
1644 count);
a6670615
CC		 1645
1646 dma_sync_single_for_device(port->dev, pdc->dma_addr,
1647 pdc->dma_size, DMA_FROM_DEVICE);
1648
1649 port->icount.rx += count;
1650 pdc->ofs = head;
1651 }
1652
1653 /*
1654 * If the current buffer is full, we need to check if
1655 * the next one contains any additional data.
1656 */
1657 if (head >= pdc->dma_size) {
1658 pdc->ofs = 0;
4e7decda
CP		 1659 atmel_uart_writel(port, ATMEL_PDC_RNPR, pdc->dma_addr);
1660 atmel_uart_writel(port, ATMEL_PDC_RNCR, pdc->dma_size);
a6670615
CC		 1661
1662 rx_idx = !rx_idx;
1663 atmel_port->pdc_rx_idx = rx_idx;
1664 }
1665 } while (head >= pdc->dma_size);
1666
2e124b4a 1667 tty_flip_buffer_push(tport);
a6670615 1668
4e7decda
CP		 1669 atmel_uart_writel(port, ATMEL_US_IER,
1670 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT);
a6670615
CC		 1671}
1672
a930e528
ES		 1673static int atmel_prepare_rx_pdc(struct uart_port *port)
1674{
1675 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1676 int i;
1677
1678 for (i = 0; i < 2; i++) {
1679 struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i];
1680
1681 pdc->buf = kmalloc(PDC_BUFFER_SIZE, GFP_KERNEL);
1682 if (pdc->buf == NULL) {
1683 if (i != 0) {
1684 dma_unmap_single(port->dev,
1685 atmel_port->pdc_rx[0].dma_addr,
1686 PDC_BUFFER_SIZE,
1687 DMA_FROM_DEVICE);
1688 kfree(atmel_port->pdc_rx[0].buf);
1689 }
36ce7cff 1690 atmel_port->use_pdc_rx = false;
a930e528
ES		 1691 return -ENOMEM;
1692 }
1693 pdc->dma_addr = dma_map_single(port->dev,
1694 pdc->buf,
1695 PDC_BUFFER_SIZE,
1696 DMA_FROM_DEVICE);
1697 pdc->dma_size = PDC_BUFFER_SIZE;
1698 pdc->ofs = 0;
1699 }
1700
1701 atmel_port->pdc_rx_idx = 0;
1702
4e7decda
CP		 1703 atmel_uart_writel(port, ATMEL_PDC_RPR, atmel_port->pdc_rx[0].dma_addr);
1704 atmel_uart_writel(port, ATMEL_PDC_RCR, PDC_BUFFER_SIZE);
a930e528 1705
4e7decda
CP		 1706 atmel_uart_writel(port, ATMEL_PDC_RNPR,
1707 atmel_port->pdc_rx[1].dma_addr);
1708 atmel_uart_writel(port, ATMEL_PDC_RNCR, PDC_BUFFER_SIZE);
a930e528
ES		 1709
1710 return 0;
1711}
1712
1ecc26bd
RB		 1713/*
1714 * tasklet handling tty stuff outside the interrupt handler.
1715 */
41e85e44 1716static void atmel_tasklet_rx_func(struct tasklet_struct *t)
1ecc26bd 1717{
41e85e44
AP		 1718 struct atmel_uart_port *atmel_port = from_tasklet(atmel_port, t,
1719 tasklet_rx);
1720 struct uart_port *port = &atmel_port->uart;
1ecc26bd
RB		 1721
1722 /* The interrupt handler does not take the lock */
cb9936f8 1723 uart_port_lock(port);
a930e528 1724 atmel_port->schedule_rx(port);
cb9936f8 1725 uart_port_unlock(port);
00e8e658 1726}
1ecc26bd 1727
41e85e44 1728static void atmel_tasklet_tx_func(struct tasklet_struct *t)
00e8e658 1729{
41e85e44
AP		 1730 struct atmel_uart_port *atmel_port = from_tasklet(atmel_port, t,
1731 tasklet_tx);
1732 struct uart_port *port = &atmel_port->uart;
00e8e658
NF		 1733
1734 /* The interrupt handler does not take the lock */
cb9936f8 1735 uart_port_lock(port);
00e8e658 1736 atmel_port->schedule_tx(port);
cb9936f8 1737 uart_port_unlock(port);
1ecc26bd
RB		 1738}
1739
4a1e8888 1740static void atmel_init_property(struct atmel_uart_port *atmel_port,
33d64c4f
ES		 1741 struct platform_device *pdev)
1742{
1743 struct device_node *np = pdev->dev.of_node;
92c8f7c0
AB		 1744
1745 /* DMA/PDC usage specification */
1746 if (of_property_read_bool(np, "atmel,use-dma-rx")) {
1747 if (of_property_read_bool(np, "dmas")) {
1748 atmel_port->use_dma_rx = true;
1749 atmel_port->use_pdc_rx = false;
33d64c4f
ES		 1750 } else {
1751 atmel_port->use_dma_rx = false;
92c8f7c0 1752 atmel_port->use_pdc_rx = true;
33d64c4f 1753 }
92c8f7c0
AB		 1754 } else {
1755 atmel_port->use_dma_rx = false;
1756 atmel_port->use_pdc_rx = false;
1757 }
33d64c4f 1758
92c8f7c0
AB		 1759 if (of_property_read_bool(np, "atmel,use-dma-tx")) {
1760 if (of_property_read_bool(np, "dmas")) {
1761 atmel_port->use_dma_tx = true;
1762 atmel_port->use_pdc_tx = false;
33d64c4f
ES		 1763 } else {
1764 atmel_port->use_dma_tx = false;
92c8f7c0 1765 atmel_port->use_pdc_tx = true;
33d64c4f 1766 }
33d64c4f 1767 } else {
33d64c4f 1768 atmel_port->use_dma_tx = false;
92c8f7c0 1769 atmel_port->use_pdc_tx = false;
33d64c4f 1770 }
33d64c4f
ES		 1771}
1772
a930e528
ES		 1773static void atmel_set_ops(struct uart_port *port)
1774{
1775 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1776
34df42f5
ES		 1777 if (atmel_use_dma_rx(port)) {
1778 atmel_port->prepare_rx = &atmel_prepare_rx_dma;
1779 atmel_port->schedule_rx = &atmel_rx_from_dma;
1780 atmel_port->release_rx = &atmel_release_rx_dma;
1781 } else if (atmel_use_pdc_rx(port)) {
a930e528
ES		 1782 atmel_port->prepare_rx = &atmel_prepare_rx_pdc;
1783 atmel_port->schedule_rx = &atmel_rx_from_pdc;
1784 atmel_port->release_rx = &atmel_release_rx_pdc;
1785 } else {
1786 atmel_port->prepare_rx = NULL;
1787 atmel_port->schedule_rx = &atmel_rx_from_ring;
1788 atmel_port->release_rx = NULL;
1789 }
1790
08f738be
ES		 1791 if (atmel_use_dma_tx(port)) {
1792 atmel_port->prepare_tx = &atmel_prepare_tx_dma;
1793 atmel_port->schedule_tx = &atmel_tx_dma;
1794 atmel_port->release_tx = &atmel_release_tx_dma;
1795 } else if (atmel_use_pdc_tx(port)) {
a930e528
ES		 1796 atmel_port->prepare_tx = &atmel_prepare_tx_pdc;
1797 atmel_port->schedule_tx = &atmel_tx_pdc;
1798 atmel_port->release_tx = &atmel_release_tx_pdc;
1799 } else {
1800 atmel_port->prepare_tx = NULL;
1801 atmel_port->schedule_tx = &atmel_tx_chars;
1802 atmel_port->release_tx = NULL;
1803 }
1804}
1805
055560b0
ES		 1806/*
1807 * Get ip name usart or uart
1808 */
892db58b 1809static void atmel_get_ip_name(struct uart_port *port)
055560b0
ES		 1810{
1811 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
4e7decda 1812 int name = atmel_uart_readl(port, ATMEL_US_NAME);
731d9cae 1813 u32 version;
1d673fb9 1814 u32 usart, dbgu_uart, new_uart;
4b769371
NF		 1815 /* ASCII decoding for IP version */
1816 usart = 0x55534152; /* USAR(T) */
1817 dbgu_uart = 0x44424755; /* DBGU */
1d673fb9 1818 new_uart = 0x55415254; /* UART */
055560b0 1819
5bf5635a
LD		 1820 /*
1821 * Only USART devices from at91sam9260 SOC implement fractional
2867af2d
RI		 1822 * baudrate. It is available for all asynchronous modes, with the
1823 * following restriction: the sampling clock's duty cycle is not
1824 * constant.
5bf5635a
LD		 1825 */
1826 atmel_port->has_frac_baudrate = false;
4b769371 1827 atmel_port->has_hw_timer = false;
5644bf18 1828 atmel_port->is_usart = false;
055560b0 1829
2958ccee
LD		 1830 if (name == new_uart) {
1831 dev_dbg(port->dev, "Uart with hw timer");
4b769371 1832 atmel_port->has_hw_timer = true;
2958ccee
LD		 1833 atmel_port->rtor = ATMEL_UA_RTOR;
1834 } else if (name == usart) {
1835 dev_dbg(port->dev, "Usart\n");
5bf5635a 1836 atmel_port->has_frac_baudrate = true;
2958ccee 1837 atmel_port->has_hw_timer = true;
5644bf18 1838 atmel_port->is_usart = true;
2958ccee 1839 atmel_port->rtor = ATMEL_US_RTOR;
377fedd1
NF		 1840 version = atmel_uart_readl(port, ATMEL_US_VERSION);
1841 switch (version) {
1842 case 0x814: /* sama5d2 */
df561f66 1843 fallthrough;
377fedd1
NF		 1844 case 0x701: /* sama5d4 */
1845 atmel_port->fidi_min = 3;
1846 atmel_port->fidi_max = 65535;
1847 break;
1848 case 0x502: /* sam9x5, sama5d3 */
1849 atmel_port->fidi_min = 3;
1850 atmel_port->fidi_max = 2047;
1851 break;
1852 default:
1853 atmel_port->fidi_min = 1;
1854 atmel_port->fidi_max = 2047;
1855 }
4b769371
NF		 1856 } else if (name == dbgu_uart) {
1857 dev_dbg(port->dev, "Dbgu or uart without hw timer\n");
055560b0 1858 } else {
731d9cae 1859 /* fallback for older SoCs: use version field */
4e7decda 1860 version = atmel_uart_readl(port, ATMEL_US_VERSION);
731d9cae
NF		 1861 switch (version) {
1862 case 0x302:
1863 case 0x10213:
fd63a890 1864 case 0x10302:
731d9cae 1865 dev_dbg(port->dev, "This version is usart\n");
5bf5635a 1866 atmel_port->has_frac_baudrate = true;
4b769371 1867 atmel_port->has_hw_timer = true;
5644bf18 1868 atmel_port->is_usart = true;
2958ccee 1869 atmel_port->rtor = ATMEL_US_RTOR;
731d9cae
NF		 1870 break;
1871 case 0x203:
1872 case 0x10202:
1873 dev_dbg(port->dev, "This version is uart\n");
731d9cae
NF		 1874 break;
1875 default:
1876 dev_err(port->dev, "Not supported ip name nor version, set to uart\n");
1877 }
055560b0 1878 }
055560b0
ES		 1879}
1880
1e6c9c28
AV		 1881/*
1882 * Perform initialization and enable port for reception
1883 */
7192f92c 1884static int atmel_startup(struct uart_port *port)
1e6c9c28 1885{
33d64c4f 1886 struct platform_device *pdev = to_platform_device(port->dev);
c811ab8c 1887 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1e6c9c28
AV		 1888 int retval;
1889
1890 /*
1891 * Ensure that no interrupts are enabled otherwise when
1892 * request_irq() is called we could get stuck trying to
1893 * handle an unexpected interrupt
1894 */
4e7decda 1895 atmel_uart_writel(port, ATMEL_US_IDR, -1);
ab5e4e41 1896 atmel_port->ms_irq_enabled = false;
1e6c9c28
AV		 1897
1898 /*
1899 * Allocate the IRQ
1900 */
2c7af5ba 1901 retval = request_irq(port->irq, atmel_interrupt,
9594b5be
SAS		 1902 IRQF_SHARED | IRQF_COND_SUSPEND,
1903 dev_name(&pdev->dev), port);
1e6c9c28 1904 if (retval) {
ddaa6037 1905 dev_err(port->dev, "atmel_startup - Can't get irq\n");
1e6c9c28
AV		 1906 return retval;
1907 }
1908
98f2082c 1909 atomic_set(&atmel_port->tasklet_shutdown, 0);
41e85e44
AP		 1910 tasklet_setup(&atmel_port->tasklet_rx, atmel_tasklet_rx_func);
1911 tasklet_setup(&atmel_port->tasklet_tx, atmel_tasklet_tx_func);
1e125786 1912
a6670615
CC		 1913 /*
1914 * Initialize DMA (if necessary)
1915 */
33d64c4f 1916 atmel_init_property(atmel_port, pdev);
4d9628a1 1917 atmel_set_ops(port);
33d64c4f 1918
a930e528
ES		 1919 if (atmel_port->prepare_rx) {
1920 retval = atmel_port->prepare_rx(port);
1921 if (retval < 0)
1922 atmel_set_ops(port);
a6670615 1923 }
a6670615 1924
a930e528
ES		 1925 if (atmel_port->prepare_tx) {
1926 retval = atmel_port->prepare_tx(port);
1927 if (retval < 0)
1928 atmel_set_ops(port);
a6670615 1929 }
1e6c9c28 1930
b5199d46
CP		 1931 /*
1932 * Enable FIFO when available
1933 */
1934 if (atmel_port->fifo_size) {
1935 unsigned int txrdym = ATMEL_US_ONE_DATA;
1936 unsigned int rxrdym = ATMEL_US_ONE_DATA;
1937 unsigned int fmr;
1938
1939 atmel_uart_writel(port, ATMEL_US_CR,
1940 ATMEL_US_FIFOEN |
1941 ATMEL_US_RXFCLR |
1942 ATMEL_US_TXFLCLR);
1943
5f258b3e
CP		 1944 if (atmel_use_dma_tx(port))
1945 txrdym = ATMEL_US_FOUR_DATA;
1946
b5199d46
CP		 1947 fmr = ATMEL_US_TXRDYM(txrdym) | ATMEL_US_RXRDYM(rxrdym);
1948 if (atmel_port->rts_high &&
1949 atmel_port->rts_low)
1950 fmr |= ATMEL_US_FRTSC |
1951 ATMEL_US_RXFTHRES(atmel_port->rts_high) |
1952 ATMEL_US_RXFTHRES2(atmel_port->rts_low);
1953
1954 atmel_uart_writel(port, ATMEL_US_FMR, fmr);
1955 }
1956
27c0c8e5 1957 /* Save current CSR for comparison in atmel_tasklet_func() */
d2d8d4c0 1958 atmel_port->irq_status_prev = atmel_uart_readl(port, ATMEL_US_CSR);
27c0c8e5 1959
1e6c9c28
AV		 1960 /*
1961 * Finally, enable the serial port
1962 */
4e7decda 1963 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
b843aa21 1964 /* enable xmit & rcvr */
4e7decda 1965 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN);
ea04f82a 1966 atmel_port->tx_stopped = false;
afefc415 1967
026cb432 1968 timer_setup(&atmel_port->uart_timer, atmel_uart_timer_callback, 0);
8bc661bf 1969
64e22ebe 1970 if (atmel_use_pdc_rx(port)) {
a6670615 1971 /* set UART timeout */
4b769371 1972 if (!atmel_port->has_hw_timer) {
2e68c22f
ES		 1973 mod_timer(&atmel_port->uart_timer,
1974 jiffies + uart_poll_timeout(port));
1975 /* set USART timeout */
1976 } else {
2958ccee
LD		 1977 atmel_uart_writel(port, atmel_port->rtor,
1978 PDC_RX_TIMEOUT);
4e7decda 1979 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
a6670615 1980
4e7decda
CP		 1981 atmel_uart_writel(port, ATMEL_US_IER,
1982 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT);
2e68c22f 1983 }
a6670615 1984 /* enable PDC controller */
4e7decda 1985 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN);
34df42f5 1986 } else if (atmel_use_dma_rx(port)) {
2e68c22f 1987 /* set UART timeout */
4b769371 1988 if (!atmel_port->has_hw_timer) {
2e68c22f
ES		 1989 mod_timer(&atmel_port->uart_timer,
1990 jiffies + uart_poll_timeout(port));
1991 /* set USART timeout */
1992 } else {
2958ccee
LD		 1993 atmel_uart_writel(port, atmel_port->rtor,
1994 PDC_RX_TIMEOUT);
4e7decda 1995 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
34df42f5 1996
4e7decda
CP		 1997 atmel_uart_writel(port, ATMEL_US_IER,
1998 ATMEL_US_TIMEOUT);
2e68c22f 1999 }
a6670615
CC		 2000 } else {
2001 /* enable receive only */
4e7decda 2002 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_RXRDY);
a6670615 2003 }
afefc415 2004
1e6c9c28
AV		 2005 return 0;
2006}
2007
479e9b94
PH		 2008/*
2009 * Flush any TX data submitted for DMA. Called when the TX circular
2010 * buffer is reset.
2011 */
2012static void atmel_flush_buffer(struct uart_port *port)
2013{
2014 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2015
2016 if (atmel_use_pdc_tx(port)) {
4e7decda 2017 atmel_uart_writel(port, ATMEL_PDC_TCR, 0);
479e9b94
PH		 2018 atmel_port->pdc_tx.ofs = 0;
2019 }
31ca2c63
RG		 2020 /*
2021 * in uart_flush_buffer(), the xmit circular buffer has just
2022 * been cleared, so we have to reset tx_len accordingly.
2023 */
2024 atmel_port->tx_len = 0;
479e9b94
PH		 2025}
2026
1e6c9c28
AV		 2027/*
2028 * Disable the port
2029 */
7192f92c 2030static void atmel_shutdown(struct uart_port *port)
1e6c9c28 2031{
c811ab8c 2032 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
0cc7c6c7 2033
0ae9fdef
RG		 2034 /* Disable modem control lines interrupts */
2035 atmel_disable_ms(port);
2036
98f2082c
NF		 2037 /* Disable interrupts at device level */
2038 atmel_uart_writel(port, ATMEL_US_IDR, -1);
2039
2040 /* Prevent spurious interrupts from scheduling the tasklet */
2041 atomic_inc(&atmel_port->tasklet_shutdown);
2042
8bc661bf
MR		 2043 /*
2044 * Prevent any tasklets being scheduled during
2045 * cleanup
2046 */
2047 del_timer_sync(&atmel_port->uart_timer);
2048
98f2082c
NF		 2049 /* Make sure that no interrupt is on the fly */
2050 synchronize_irq(port->irq);
2051
0cc7c6c7
MR		 2052 /*
2053 * Clear out any scheduled tasklets before
2054 * we destroy the buffers
2055 */
00e8e658
NF		 2056 tasklet_kill(&atmel_port->tasklet_rx);
2057 tasklet_kill(&atmel_port->tasklet_tx);
0cc7c6c7 2058
a6670615 2059 /*
0cc7c6c7 2060 * Ensure everything is stopped and
98f2082c 2061 * disable port and break condition.
a6670615
CC		 2062 */
2063 atmel_stop_rx(port);
2064 atmel_stop_tx(port);
2065
4e7decda 2066 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
0cc7c6c7 2067
a6670615
CC		 2068 /*
2069 * Shut-down the DMA.
2070 */
a930e528
ES		 2071 if (atmel_port->release_rx)
2072 atmel_port->release_rx(port);
2073 if (atmel_port->release_tx)
2074 atmel_port->release_tx(port);
a6670615 2075
bb7e73c5
MD		 2076 /*
2077 * Reset ring buffer pointers
2078 */
2079 atmel_port->rx_ring.head = 0;
2080 atmel_port->rx_ring.tail = 0;
2081
1e6c9c28 2082 /*
ab5e4e41 2083 * Free the interrupts
1e6c9c28
AV		 2084 */
2085 free_irq(port->irq, port);
ab5e4e41 2086
479e9b94 2087 atmel_flush_buffer(port);
9afd561a
HS		 2088}
2089
1e6c9c28
AV		 2090/*
2091 * Power / Clock management.
2092 */
b843aa21
RB		 2093static void atmel_serial_pm(struct uart_port *port, unsigned int state,
2094 unsigned int oldstate)
1e6c9c28 2095{
c811ab8c 2096 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
afefc415 2097
1e6c9c28 2098 switch (state) {
aec079f8 2099 case UART_PM_STATE_ON:
b843aa21
RB		 2100 /*
2101 * Enable the peripheral clock for this serial port.
2102 * This is called on uart_open() or a resume event.
2103 */
91f8c2d8 2104 clk_prepare_enable(atmel_port->clk);
f05596db
AS		 2105
2106 /* re-enable interrupts if we disabled some on suspend */
4e7decda 2107 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->backup_imr);
b843aa21 2108 break;
aec079f8 2109 case UART_PM_STATE_OFF:
f05596db 2110 /* Back up the interrupt mask and disable all interrupts */
4e7decda
CP		 2111 atmel_port->backup_imr = atmel_uart_readl(port, ATMEL_US_IMR);
2112 atmel_uart_writel(port, ATMEL_US_IDR, -1);
f05596db 2113
b843aa21
RB		 2114 /*
2115 * Disable the peripheral clock for this serial port.
2116 * This is called on uart_close() or a suspend event.
2117 */
91f8c2d8 2118 clk_disable_unprepare(atmel_port->clk);
5e3ce1f2
SM		 2119 if (__clk_is_enabled(atmel_port->gclk))
2120 clk_disable_unprepare(atmel_port->gclk);
b843aa21
RB		 2121 break;
2122 default:
ddaa6037 2123 dev_err(port->dev, "atmel_serial: unknown pm %d\n", state);
1e6c9c28
AV		 2124 }
2125}
2126
2127/*
2128 * Change the port parameters
2129 */
bec5b814
IJ		 2130static void atmel_set_termios(struct uart_port *port,
2131 struct ktermios *termios,
2132 const struct ktermios *old)
1e6c9c28 2133{
5bf5635a 2134 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1e6c9c28 2135 unsigned long flags;
5e3ce1f2
SM		 2136 unsigned int old_mode, mode, imr, quot, div, cd, fp = 0;
2137 unsigned int baud, actual_baud, gclk_rate;
2138 int ret;
1cf6e8fc
CP		 2139
2140 /* save the current mode register */
4e7decda 2141 mode = old_mode = atmel_uart_readl(port, ATMEL_US_MR);
1e6c9c28 2142
1cf6e8fc 2143 /* reset the mode, clock divisor, parity, stop bits and data size */
1a5a01a1
SM		 2144 if (atmel_port->is_usart)
2145 mode &= ~(ATMEL_US_NBSTOP | ATMEL_US_PAR | ATMEL_US_CHRL |
2146 ATMEL_US_USCLKS | ATMEL_US_USMODE);
2147 else
2148 mode &= ~(ATMEL_UA_BRSRCCK | ATMEL_US_PAR | ATMEL_UA_FILTER);
03abeac0 2149
b843aa21 2150 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
1e6c9c28
AV		 2151
2152 /* byte size */
2153 switch (termios->c_cflag & CSIZE) {
2154 case CS5:
7192f92c 2155 mode |= ATMEL_US_CHRL_5;
1e6c9c28
AV		 2156 break;
2157 case CS6:
7192f92c 2158 mode |= ATMEL_US_CHRL_6;
1e6c9c28
AV		 2159 break;
2160 case CS7:
7192f92c 2161 mode |= ATMEL_US_CHRL_7;
1e6c9c28
AV		 2162 break;
2163 default:
7192f92c 2164 mode |= ATMEL_US_CHRL_8;
1e6c9c28
AV		 2165 break;
2166 }
2167
2168 /* stop bits */
2169 if (termios->c_cflag & CSTOPB)
7192f92c 2170 mode |= ATMEL_US_NBSTOP_2;
1e6c9c28
AV		 2171
2172 /* parity */
2173 if (termios->c_cflag & PARENB) {
b843aa21
RB		 2174 /* Mark or Space parity */
2175 if (termios->c_cflag & CMSPAR) {
1e6c9c28 2176 if (termios->c_cflag & PARODD)
7192f92c 2177 mode |= ATMEL_US_PAR_MARK;
1e6c9c28 2178 else
7192f92c 2179 mode |= ATMEL_US_PAR_SPACE;
b843aa21 2180 } else if (termios->c_cflag & PARODD)
7192f92c 2181 mode |= ATMEL_US_PAR_ODD;
1e6c9c28 2182 else
7192f92c 2183 mode |= ATMEL_US_PAR_EVEN;
b843aa21 2184 } else
7192f92c 2185 mode |= ATMEL_US_PAR_NONE;
1e6c9c28 2186
cb9936f8 2187 uart_port_lock_irqsave(port, &flags);
1e6c9c28 2188
7192f92c 2189 port->read_status_mask = ATMEL_US_OVRE;
1e6c9c28 2190 if (termios->c_iflag & INPCK)
7192f92c 2191 port->read_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE);
ef8b9ddc 2192 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
7192f92c 2193 port->read_status_mask |= ATMEL_US_RXBRK;
1e6c9c28 2194
64e22ebe 2195 if (atmel_use_pdc_rx(port))
a6670615 2196 /* need to enable error interrupts */
4e7decda 2197 atmel_uart_writel(port, ATMEL_US_IER, port->read_status_mask);
a6670615 2198
1e6c9c28
AV		 2199 /*
2200 * Characters to ignore
2201 */
2202 port->ignore_status_mask = 0;
2203 if (termios->c_iflag & IGNPAR)
7192f92c 2204 port->ignore_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE);
1e6c9c28 2205 if (termios->c_iflag & IGNBRK) {
7192f92c 2206 port->ignore_status_mask |= ATMEL_US_RXBRK;
1e6c9c28
AV		 2207 /*
2208 * If we're ignoring parity and break indicators,
2209 * ignore overruns too (for real raw support).
2210 */
2211 if (termios->c_iflag & IGNPAR)
7192f92c 2212 port->ignore_status_mask |= ATMEL_US_OVRE;
1e6c9c28 2213 }
b843aa21 2214 /* TODO: Ignore all characters if CREAD is set.*/
1e6c9c28
AV		 2215
2216 /* update the per-port timeout */
2217 uart_update_timeout(port, termios->c_cflag, baud);
2218
0ccad870
HS		 2219 /*
2220 * save/disable interrupts. The tty layer will ensure that the
2221 * transmitter is empty if requested by the caller, so there's
2222 * no need to wait for it here.
2223 */
4e7decda
CP		 2224 imr = atmel_uart_readl(port, ATMEL_US_IMR);
2225 atmel_uart_writel(port, ATMEL_US_IDR, -1);
1e6c9c28
AV		 2226
2227 /* disable receiver and transmitter */
4e7decda 2228 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXDIS | ATMEL_US_RXDIS);
ea04f82a 2229 atmel_port->tx_stopped = true;
1e6c9c28 2230
1cf6e8fc 2231 /* mode */
13bd3e6f 2232 if (port->rs485.flags & SER_RS485_ENABLED) {
4e7decda
CP		 2233 atmel_uart_writel(port, ATMEL_US_TTGR,
2234 port->rs485.delay_rts_after_send);
e8faff73 2235 mode |= ATMEL_US_USMODE_RS485;
377fedd1
NF		 2236 } else if (port->iso7816.flags & SER_ISO7816_ENABLED) {
2237 atmel_uart_writel(port, ATMEL_US_TTGR, port->iso7816.tg);
2238 /* select mck clock, and output */
2239 mode |= ATMEL_US_USCLKS_MCK | ATMEL_US_CLKO;
2240 /* set max iterations */
2241 mode |= ATMEL_US_MAX_ITER(3);
2242 if ((port->iso7816.flags & SER_ISO7816_T_PARAM)
2243 == SER_ISO7816_T(0))
2244 mode |= ATMEL_US_USMODE_ISO7816_T0;
2245 else
2246 mode |= ATMEL_US_USMODE_ISO7816_T1;
1cf6e8fc
CP		 2247 } else if (termios->c_cflag & CRTSCTS) {
2248 /* RS232 with hardware handshake (RTS/CTS) */
9bcffe75
RG		 2249 if (atmel_use_fifo(port) &&
2250 !mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_CTS)) {
2251 /*
2252 * with ATMEL_US_USMODE_HWHS set, the controller will
2253 * be able to drive the RTS pin high/low when the RX
2254 * FIFO is above RXFTHRES/below RXFTHRES2.
2255 * It will also disable the transmitter when the CTS
2256 * pin is high.
2257 * This mode is not activated if CTS pin is a GPIO
2258 * because in this case, the transmitter is always
2259 * disabled (there must be an internal pull-up
2260 * responsible for this behaviour).
2261 * If the RTS pin is a GPIO, the controller won't be
2262 * able to drive it according to the FIFO thresholds,
2263 * but it will be handled by the driver.
2264 */
5be605ac 2265 mode |= ATMEL_US_USMODE_HWHS;
9bcffe75
RG		 2266 } else {
2267 /*
2268 * For platforms without FIFO, the flow control is
2269 * handled by the driver.
2270 */
2271 mode |= ATMEL_US_USMODE_NORMAL;
5be605ac 2272 }
1cf6e8fc
CP		 2273 } else {
2274 /* RS232 without hadware handshake */
2275 mode |= ATMEL_US_USMODE_NORMAL;
e8faff73
CS		 2276 }
2277
5bf5635a
LD		 2278 /*
2279 * Set the baud rate:
2280 * Fractional baudrate allows to setup output frequency more
2281 * accurately. This feature is enabled only when using normal mode.
2282 * baudrate = selected clock / (8 * (2 - OVER) * (CD + FP / 8))
2283 * Currently, OVER is always set to 0 so we get
36131cdf
AS		 2284 * baudrate = selected clock / (16 * (CD + FP / 8))
2285 * then
2286 * 8 CD + FP = selected clock / (2 * baudrate)
5bf5635a 2287 */
2867af2d 2288 if (atmel_port->has_frac_baudrate) {
36131cdf
AS		 2289 div = DIV_ROUND_CLOSEST(port->uartclk, baud * 2);
2290 cd = div >> 3;
2291 fp = div & ATMEL_US_FP_MASK;
5bf5635a
LD		 2292 } else {
2293 cd = uart_get_divisor(port, baud);
2294 }
2295
5644bf18
SM		 2296 /*
2297 * If the current value of the Clock Divisor surpasses the 16 bit
2298 * ATMEL_US_CD mask and the IP is USART, switch to the Peripheral
2299 * Clock implicitly divided by 8.
2300 * If the IP is UART however, keep the highest possible value for
2301 * the CD and avoid needless division of CD, since UART IP's do not
2302 * support implicit division of the Peripheral Clock.
2303 */
2304 if (atmel_port->is_usart && cd > ATMEL_US_CD) {
5bf5635a
LD		 2305 cd /= 8;
2306 mode |= ATMEL_US_USCLKS_MCK_DIV8;
5644bf18
SM		 2307 } else {
2308 cd = min_t(unsigned int, cd, ATMEL_US_CD);
5bf5635a 2309 }
5644bf18 2310
5e3ce1f2
SM		 2311 /*
2312 * If there is no Fractional Part, there is a high chance that
2313 * we may be able to generate a baudrate closer to the desired one
2314 * if we use the GCLK as the clock source driving the baudrate
2315 * generator.
2316 */
2317 if (!atmel_port->has_frac_baudrate) {
2318 if (__clk_is_enabled(atmel_port->gclk))
2319 clk_disable_unprepare(atmel_port->gclk);
2320 gclk_rate = clk_round_rate(atmel_port->gclk, 16 * baud);
2321 actual_baud = clk_get_rate(atmel_port->clk) / (16 * cd);
2322 if (gclk_rate && abs(atmel_error_rate(baud, actual_baud)) >
2323 abs(atmel_error_rate(baud, gclk_rate / 16))) {
2324 clk_set_rate(atmel_port->gclk, 16 * baud);
2325 ret = clk_prepare_enable(atmel_port->gclk);
2326 if (ret)
2327 goto gclk_fail;
2328
2329 if (atmel_port->is_usart) {
2330 mode &= ~ATMEL_US_USCLKS;
2331 mode |= ATMEL_US_USCLKS_GCLK;
2332 } else {
2333 mode |= ATMEL_UA_BRSRCCK;
2334 }
2335
2336 /*
2337 * Set the Clock Divisor for GCLK to 1.
2338 * Since we were able to generate the smallest
2339 * multiple of the desired baudrate times 16,
2340 * then we surely can generate a bigger multiple
2341 * with the exact error rate for an equally increased
2342 * CD. Thus no need to take into account
2343 * a higher value for CD.
2344 */
2345 cd = 1;
2346 }
2347 }
2348
2349gclk_fail:
5bf5635a
LD		 2350 quot = cd | fp << ATMEL_US_FP_OFFSET;
2351
377fedd1
NF		 2352 if (!(port->iso7816.flags & SER_ISO7816_ENABLED))
2353 atmel_uart_writel(port, ATMEL_US_BRGR, quot);
cb47b9f8
DE		 2354
2355 /* set the mode, clock divisor, parity, stop bits and data size */
2356 atmel_uart_writel(port, ATMEL_US_MR, mode);
2357
2358 /*
2359 * when switching the mode, set the RTS line state according to the
2360 * new mode, otherwise keep the former state
2361 */
2362 if ((old_mode & ATMEL_US_USMODE) != (mode & ATMEL_US_USMODE)) {
2363 unsigned int rts_state;
2364
2365 if ((mode & ATMEL_US_USMODE) == ATMEL_US_USMODE_HWHS) {
2366 /* let the hardware control the RTS line */
2367 rts_state = ATMEL_US_RTSDIS;
2368 } else {
2369 /* force RTS line to low level */
2370 rts_state = ATMEL_US_RTSEN;
2371 }
2372
2373 atmel_uart_writel(port, ATMEL_US_CR, rts_state);
2374 }
2375
4e7decda
CP		 2376 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
2377 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN);
ea04f82a 2378 atmel_port->tx_stopped = false;
1e6c9c28
AV		 2379
2380 /* restore interrupts */
4e7decda 2381 atmel_uart_writel(port, ATMEL_US_IER, imr);
1e6c9c28
AV		 2382
2383 /* CTS flow-control and modem-status interrupts */
2384 if (UART_ENABLE_MS(port, termios->c_cflag))
35b675b9
RG		 2385 atmel_enable_ms(port);
2386 else
2387 atmel_disable_ms(port);
1e6c9c28 2388
cb9936f8 2389 uart_port_unlock_irqrestore(port, flags);
1e6c9c28
AV		 2390}
2391
732a84a0 2392static void atmel_set_ldisc(struct uart_port *port, struct ktermios *termios)
42bd7a4f 2393{
732a84a0 2394 if (termios->c_line == N_PPS) {
42bd7a4f 2395 port->flags |= UPF_HARDPPS_CD;
cb9936f8 2396 uart_port_lock_irq(port);
42bd7a4f 2397 atmel_enable_ms(port);
cb9936f8 2398 uart_port_unlock_irq(port);
42bd7a4f
VP		 2399 } else {
2400 port->flags &= ~UPF_HARDPPS_CD;
cab68f89 2401 if (!UART_ENABLE_MS(port, termios->c_cflag)) {
cb9936f8 2402 uart_port_lock_irq(port);
cab68f89 2403 atmel_disable_ms(port);
cb9936f8 2404 uart_port_unlock_irq(port);
cab68f89 2405 }
42bd7a4f
VP		 2406 }
2407}
2408
1e6c9c28
AV		 2409/*
2410 * Return string describing the specified port
2411 */
7192f92c 2412static const char *atmel_type(struct uart_port *port)
1e6c9c28 2413{
9ab4f88b 2414 return (port->type == PORT_ATMEL) ? "ATMEL_SERIAL" : NULL;
1e6c9c28
AV		 2415}
2416
2417/*
2418 * Release the memory region(s) being used by 'port'.
2419 */
7192f92c 2420static void atmel_release_port(struct uart_port *port)
1e6c9c28 2421{
c24d2531
RP		 2422 struct platform_device *mpdev = to_platform_device(port->dev->parent);
2423 int size = resource_size(mpdev->resource);
afefc415
AV		 2424
2425 release_mem_region(port->mapbase, size);
2426
2427 if (port->flags & UPF_IOREMAP) {
2428 iounmap(port->membase);
2429 port->membase = NULL;
2430 }
1e6c9c28
AV		 2431}
2432
2433/*
2434 * Request the memory region(s) being used by 'port'.
2435 */
7192f92c 2436static int atmel_request_port(struct uart_port *port)
1e6c9c28 2437{
c24d2531
RP		 2438 struct platform_device *mpdev = to_platform_device(port->dev->parent);
2439 int size = resource_size(mpdev->resource);
afefc415 2440
7192f92c 2441 if (!request_mem_region(port->mapbase, size, "atmel_serial"))
afefc415
AV		 2442 return -EBUSY;
2443
2444 if (port->flags & UPF_IOREMAP) {
2445 port->membase = ioremap(port->mapbase, size);
2446 if (port->membase == NULL) {
2447 release_mem_region(port->mapbase, size);
2448 return -ENOMEM;
2449 }
2450 }
1e6c9c28 2451
afefc415 2452 return 0;
1e6c9c28
AV		 2453}
2454
2455/*
2456 * Configure/autoconfigure the port.
2457 */
7192f92c 2458static void atmel_config_port(struct uart_port *port, int flags)
1e6c9c28
AV		 2459{
2460 if (flags & UART_CONFIG_TYPE) {
9ab4f88b 2461 port->type = PORT_ATMEL;
7192f92c 2462 atmel_request_port(port);
1e6c9c28
AV		 2463 }
2464}
2465
2466/*
2467 * Verify the new serial_struct (for TIOCSSERIAL).
2468 */
7192f92c 2469static int atmel_verify_port(struct uart_port *port, struct serial_struct *ser)
1e6c9c28
AV		 2470{
2471 int ret = 0;
9ab4f88b 2472 if (ser->type != PORT_UNKNOWN && ser->type != PORT_ATMEL)
1e6c9c28
AV		 2473 ret = -EINVAL;
2474 if (port->irq != ser->irq)
2475 ret = -EINVAL;
2476 if (ser->io_type != SERIAL_IO_MEM)
2477 ret = -EINVAL;
2478 if (port->uartclk / 16 != ser->baud_base)
2479 ret = -EINVAL;
270c2ade 2480 if (port->mapbase != (unsigned long)ser->iomem_base)
1e6c9c28
AV		 2481 ret = -EINVAL;
2482 if (port->iobase != ser->port)
2483 ret = -EINVAL;
2484 if (ser->hub6 != 0)
2485 ret = -EINVAL;
2486 return ret;
2487}
2488
8fe2d541
AT		 2489#ifdef CONFIG_CONSOLE_POLL
2490static int atmel_poll_get_char(struct uart_port *port)
2491{
4e7decda 2492 while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_RXRDY))
8fe2d541
AT		 2493 cpu_relax();
2494
a6499435 2495 return atmel_uart_read_char(port);
8fe2d541
AT		 2496}
2497
2498static void atmel_poll_put_char(struct uart_port *port, unsigned char ch)
2499{
4e7decda 2500 while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXRDY))
8fe2d541
AT		 2501 cpu_relax();
2502
a6499435 2503 atmel_uart_write_char(port, ch);
8fe2d541
AT		 2504}
2505#endif
2506
5c7dcdb6 2507static const struct uart_ops atmel_pops = {
7192f92c
HS		 2508 .tx_empty = atmel_tx_empty,
2509 .set_mctrl = atmel_set_mctrl,
2510 .get_mctrl = atmel_get_mctrl,
2511 .stop_tx = atmel_stop_tx,
2512 .start_tx = atmel_start_tx,
2513 .stop_rx = atmel_stop_rx,
2514 .enable_ms = atmel_enable_ms,
2515 .break_ctl = atmel_break_ctl,
2516 .startup = atmel_startup,
2517 .shutdown = atmel_shutdown,
9afd561a 2518 .flush_buffer = atmel_flush_buffer,
7192f92c 2519 .set_termios = atmel_set_termios,
42bd7a4f 2520 .set_ldisc = atmel_set_ldisc,
7192f92c
HS		 2521 .type = atmel_type,
2522 .release_port = atmel_release_port,
2523 .request_port = atmel_request_port,
2524 .config_port = atmel_config_port,
2525 .verify_port = atmel_verify_port,
2526 .pm = atmel_serial_pm,
8fe2d541
AT		 2527#ifdef CONFIG_CONSOLE_POLL
2528 .poll_get_char = atmel_poll_get_char,
2529 .poll_put_char = atmel_poll_put_char,
2530#endif
1e6c9c28
AV		 2531};
2532
af47c491
IJ		 2533static const struct serial_rs485 atmel_rs485_supported = {
2534 .flags = SER_RS485_ENABLED | SER_RS485_RTS_AFTER_SEND | SER_RS485_RX_DURING_TX,
2535 .delay_rts_before_send = 1,
2536 .delay_rts_after_send = 1,
2537};
2538
afefc415
AV		 2539/*
2540 * Configure the port from the platform device resource info.
2541 */
91f8c2d8 2542static int atmel_init_port(struct atmel_uart_port *atmel_port,
b843aa21 2543 struct platform_device *pdev)
1e6c9c28 2544{
91f8c2d8 2545 int ret;
7192f92c 2546 struct uart_port *port = &atmel_port->uart;
c24d2531 2547 struct platform_device *mpdev = to_platform_device(pdev->dev.parent);
afefc415 2548
4a1e8888
LZ		 2549 atmel_init_property(atmel_port, pdev);
2550 atmel_set_ops(port);
afefc415 2551
e8faff73 2552 port->iotype = UPIO_MEM;
92c8f7c0 2553 port->flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP;
e8faff73
CS		 2554 port->ops = &atmel_pops;
2555 port->fifosize = 1;
e8faff73 2556 port->dev = &pdev->dev;
c24d2531 2557 port->mapbase = mpdev->resource[0].start;
5bb221b0 2558 port->irq = platform_get_irq(mpdev, 0);
13bd3e6f 2559 port->rs485_config = atmel_config_rs485;
0139da50 2560 port->rs485_supported = atmel_rs485_supported;
377fedd1 2561 port->iso7816_config = atmel_config_iso7816;
c24d2531 2562 port->membase = NULL;
afefc415 2563
1ecc26bd
RB		 2564 memset(&atmel_port->rx_ring, 0, sizeof(atmel_port->rx_ring));
2565
c150c0f3
LW		 2566 ret = uart_get_rs485_mode(port);
2567 if (ret)
2568 return ret;
2569
84b476b1 2570 port->uartclk = clk_get_rate(atmel_port->clk);
a6670615 2571
377fedd1
NF		 2572 /*
2573 * Use TXEMPTY for interrupt when rs485 or ISO7816 else TXRDY or
2574 * ENDTX|TXBUFE
2575 */
477b8383 2576 if (atmel_uart_is_half_duplex(port))
e8faff73 2577 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY;
64e22ebe 2578 else if (atmel_use_pdc_tx(port)) {
a6670615 2579 port->fifosize = PDC_BUFFER_SIZE;
e8faff73
CS		 2580 atmel_port->tx_done_mask = ATMEL_US_ENDTX | ATMEL_US_TXBUFE;
2581 } else {
2582 atmel_port->tx_done_mask = ATMEL_US_TXRDY;
2583 }
91f8c2d8
BB		 2584
2585 return 0;
1e6c9c28
AV		 2586}
2587
749c4e60 2588#ifdef CONFIG_SERIAL_ATMEL_CONSOLE
3f8bab17 2589static void atmel_console_putchar(struct uart_port *port, unsigned char ch)
d358788f 2590{
4e7decda 2591 while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXRDY))
829dd811 2592 cpu_relax();
a6499435 2593 atmel_uart_write_char(port, ch);
d358788f 2594}
1e6c9c28
AV		 2595
2596/*
2597 * Interrupts are disabled on entering
2598 */
7192f92c 2599static void atmel_console_write(struct console *co, const char *s, u_int count)
1e6c9c28 2600{
7192f92c 2601 struct uart_port *port = &atmel_ports[co->index].uart;
e8faff73 2602 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
d358788f 2603 unsigned int status, imr;
39d4c922 2604 unsigned int pdc_tx;
1e6c9c28
AV		 2605
2606 /*
b843aa21 2607 * First, save IMR and then disable interrupts
1e6c9c28 2608 */
4e7decda
CP		 2609 imr = atmel_uart_readl(port, ATMEL_US_IMR);
2610 atmel_uart_writel(port, ATMEL_US_IDR,
2611 ATMEL_US_RXRDY | atmel_port->tx_done_mask);
1e6c9c28 2612
39d4c922 2613 /* Store PDC transmit status and disable it */
4e7decda
CP		 2614 pdc_tx = atmel_uart_readl(port, ATMEL_PDC_PTSR) & ATMEL_PDC_TXTEN;
2615 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS);
39d4c922 2616
497e1e16
NF		 2617 /* Make sure that tx path is actually able to send characters */
2618 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN);
ea04f82a 2619 atmel_port->tx_stopped = false;
497e1e16 2620
7192f92c 2621 uart_console_write(port, s, count, atmel_console_putchar);
1e6c9c28
AV		 2622
2623 /*
b843aa21
RB		 2624 * Finally, wait for transmitter to become empty
2625 * and restore IMR
1e6c9c28
AV		 2626 */
2627 do {
4e7decda 2628 status = atmel_uart_readl(port, ATMEL_US_CSR);
7192f92c 2629 } while (!(status & ATMEL_US_TXRDY));
39d4c922
MP		 2630
2631 /* Restore PDC transmit status */
2632 if (pdc_tx)
4e7decda 2633 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
39d4c922 2634
b843aa21 2635 /* set interrupts back the way they were */
4e7decda 2636 atmel_uart_writel(port, ATMEL_US_IER, imr);
1e6c9c28
AV		 2637}
2638
2639/*
b843aa21
RB		 2640 * If the port was already initialised (eg, by a boot loader),
2641 * try to determine the current setup.
1e6c9c28 2642 */
b843aa21
RB		 2643static void __init atmel_console_get_options(struct uart_port *port, int *baud,
2644 int *parity, int *bits)
1e6c9c28
AV		 2645{
2646 unsigned int mr, quot;
2647
1c0fd82f
HS		 2648 /*
2649 * If the baud rate generator isn't running, the port wasn't
2650 * initialized by the boot loader.
2651 */
4e7decda 2652 quot = atmel_uart_readl(port, ATMEL_US_BRGR) & ATMEL_US_CD;
1c0fd82f
HS		 2653 if (!quot)
2654 return;
1e6c9c28 2655
4e7decda 2656 mr = atmel_uart_readl(port, ATMEL_US_MR) & ATMEL_US_CHRL;
7192f92c 2657 if (mr == ATMEL_US_CHRL_8)
1e6c9c28
AV		 2658 *bits = 8;
2659 else
2660 *bits = 7;
2661
4e7decda 2662 mr = atmel_uart_readl(port, ATMEL_US_MR) & ATMEL_US_PAR;
7192f92c 2663 if (mr == ATMEL_US_PAR_EVEN)
1e6c9c28 2664 *parity = 'e';
7192f92c 2665 else if (mr == ATMEL_US_PAR_ODD)
1e6c9c28
AV		 2666 *parity = 'o';
2667
5bfdd3c6 2668 *baud = port->uartclk / (16 * quot);
1e6c9c28
AV		 2669}
2670
7192f92c 2671static int __init atmel_console_setup(struct console *co, char *options)
1e6c9c28 2672{
7192f92c 2673 struct uart_port *port = &atmel_ports[co->index].uart;
ea04f82a 2674 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1e6c9c28
AV		 2675 int baud = 115200;
2676 int bits = 8;
2677 int parity = 'n';
2678 int flow = 'n';
2679
b843aa21
RB		 2680 if (port->membase == NULL) {
2681 /* Port not initialized yet - delay setup */
afefc415 2682 return -ENODEV;
b843aa21 2683 }
1e6c9c28 2684
4e7decda
CP		 2685 atmel_uart_writel(port, ATMEL_US_IDR, -1);
2686 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
2687 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN);
ea04f82a 2688 atmel_port->tx_stopped = false;
1e6c9c28
AV		 2689
2690 if (options)
2691 uart_parse_options(options, &baud, &parity, &bits, &flow);
2692 else
7192f92c 2693 atmel_console_get_options(port, &baud, &parity, &bits);
1e6c9c28
AV		 2694
2695 return uart_set_options(port, co, baud, parity, bits, flow);
2696}
2697
7192f92c 2698static struct uart_driver atmel_uart;
1e6c9c28 2699
7192f92c
HS		 2700static struct console atmel_console = {
2701 .name = ATMEL_DEVICENAME,
2702 .write = atmel_console_write,
1e6c9c28 2703 .device = uart_console_device,
7192f92c 2704 .setup = atmel_console_setup,
1e6c9c28
AV		 2705 .flags = CON_PRINTBUFFER,
2706 .index = -1,
7192f92c 2707 .data = &atmel_uart,
1e6c9c28
AV		 2708};
2709
aab68e95
MW		 2710static void atmel_serial_early_write(struct console *con, const char *s,
2711 unsigned int n)
2712{
2713 struct earlycon_device *dev = con->data;
2714
2715 uart_console_write(&dev->port, s, n, atmel_console_putchar);
2716}
2717
2718static int __init atmel_early_console_setup(struct earlycon_device *device,
2719 const char *options)
2720{
2721 if (!device->port.membase)
2722 return -ENODEV;
2723
2724 device->con->write = atmel_serial_early_write;
2725
2726 return 0;
2727}
2728
2729OF_EARLYCON_DECLARE(atmel_serial, "atmel,at91rm9200-usart",
2730 atmel_early_console_setup);
2731OF_EARLYCON_DECLARE(atmel_serial, "atmel,at91sam9260-usart",
2732 atmel_early_console_setup);
2733
06a7f058 2734#define ATMEL_CONSOLE_DEVICE (&atmel_console)
1e6c9c28 2735
1e6c9c28 2736#else
7192f92c 2737#define ATMEL_CONSOLE_DEVICE NULL
1e6c9c28
AV		 2738#endif
2739
7192f92c 2740static struct uart_driver atmel_uart = {
b843aa21
RB		 2741 .owner = THIS_MODULE,
2742 .driver_name = "atmel_serial",
2743 .dev_name = ATMEL_DEVICENAME,
2744 .major = SERIAL_ATMEL_MAJOR,
2745 .minor = MINOR_START,
2746 .nr = ATMEL_MAX_UART,
2747 .cons = ATMEL_CONSOLE_DEVICE,
1e6c9c28
AV		 2748};
2749
f826caa4
HS		 2750static bool atmel_serial_clk_will_stop(void)
2751{
2752#ifdef CONFIG_ARCH_AT91
2753 return at91_suspend_entering_slow_clock();
2754#else
2755 return false;
2756#endif
2757}
2758
b50058b8 2759static int __maybe_unused atmel_serial_suspend(struct device *dev)
1e6c9c28 2760{
b50058b8 2761 struct uart_port *port = dev_get_drvdata(dev);
c811ab8c 2762 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
afefc415 2763
207f6f34 2764 if (uart_console(port) && console_suspend_enabled) {
e1c609ef 2765 /* Drain the TX shifter */
4e7decda
CP		 2766 while (!(atmel_uart_readl(port, ATMEL_US_CSR) &
2767 ATMEL_US_TXEMPTY))
e1c609ef
HS		 2768 cpu_relax();
2769 }
2770
207f6f34 2771 if (uart_console(port) && !console_suspend_enabled) {
6a5f0e2f
AB		 2772 /* Cache register values as we won't get a full shutdown/startup
2773 * cycle
2774 */
2775 atmel_port->cache.mr = atmel_uart_readl(port, ATMEL_US_MR);
2776 atmel_port->cache.imr = atmel_uart_readl(port, ATMEL_US_IMR);
2777 atmel_port->cache.brgr = atmel_uart_readl(port, ATMEL_US_BRGR);
2778 atmel_port->cache.rtor = atmel_uart_readl(port,
2779 atmel_port->rtor);
2780 atmel_port->cache.ttgr = atmel_uart_readl(port, ATMEL_US_TTGR);
2781 atmel_port->cache.fmr = atmel_uart_readl(port, ATMEL_US_FMR);
2782 atmel_port->cache.fimr = atmel_uart_readl(port, ATMEL_US_FIMR);
2783 }
2784
f05596db 2785 /* we can not wake up if we're running on slow clock */
b50058b8 2786 atmel_port->may_wakeup = device_may_wakeup(dev);
2c7af5ba
BB		 2787 if (atmel_serial_clk_will_stop()) {
2788 unsigned long flags;
2789
2790 spin_lock_irqsave(&atmel_port->lock_suspended, flags);
2791 atmel_port->suspended = true;
2792 spin_unlock_irqrestore(&atmel_port->lock_suspended, flags);
b50058b8 2793 device_set_wakeup_enable(dev, 0);
2c7af5ba 2794 }
f05596db
AS		 2795
2796 uart_suspend_port(&atmel_uart, port);
1e6c9c28 2797
afefc415
AV		 2798 return 0;
2799}
1e6c9c28 2800
b50058b8 2801static int __maybe_unused atmel_serial_resume(struct device *dev)
afefc415 2802{
b50058b8 2803 struct uart_port *port = dev_get_drvdata(dev);
c811ab8c 2804 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2c7af5ba
BB		 2805 unsigned long flags;
2806
207f6f34 2807 if (uart_console(port) && !console_suspend_enabled) {
6a5f0e2f
AB		 2808 atmel_uart_writel(port, ATMEL_US_MR, atmel_port->cache.mr);
2809 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->cache.imr);
2810 atmel_uart_writel(port, ATMEL_US_BRGR, atmel_port->cache.brgr);
2811 atmel_uart_writel(port, atmel_port->rtor,
2812 atmel_port->cache.rtor);
2813 atmel_uart_writel(port, ATMEL_US_TTGR, atmel_port->cache.ttgr);
2814
2815 if (atmel_port->fifo_size) {
2816 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_FIFOEN |
2817 ATMEL_US_RXFCLR | ATMEL_US_TXFLCLR);
2818 atmel_uart_writel(port, ATMEL_US_FMR,
2819 atmel_port->cache.fmr);
2820 atmel_uart_writel(port, ATMEL_US_FIER,
2821 atmel_port->cache.fimr);
2822 }
2823 atmel_start_rx(port);
2824 }
2825
2c7af5ba
BB		 2826 spin_lock_irqsave(&atmel_port->lock_suspended, flags);
2827 if (atmel_port->pending) {
2828 atmel_handle_receive(port, atmel_port->pending);
2829 atmel_handle_status(port, atmel_port->pending,
2830 atmel_port->pending_status);
2831 atmel_handle_transmit(port, atmel_port->pending);
2832 atmel_port->pending = 0;
2833 }
2834 atmel_port->suspended = false;
2835 spin_unlock_irqrestore(&atmel_port->lock_suspended, flags);
1e6c9c28 2836
f05596db 2837 uart_resume_port(&atmel_uart, port);
b50058b8 2838 device_set_wakeup_enable(dev, atmel_port->may_wakeup);
1e6c9c28
AV		 2839
2840 return 0;
2841}
2842
b78cd169 2843static void atmel_serial_probe_fifos(struct atmel_uart_port *atmel_port,
b5199d46
CP		 2844 struct platform_device *pdev)
2845{
b78cd169
JA		 2846 atmel_port->fifo_size = 0;
2847 atmel_port->rts_low = 0;
2848 atmel_port->rts_high = 0;
b5199d46
CP		 2849
2850 if (of_property_read_u32(pdev->dev.of_node,
2851 "atmel,fifo-size",
b78cd169 2852 &atmel_port->fifo_size))
b5199d46
CP		 2853 return;
2854
b78cd169 2855 if (!atmel_port->fifo_size)
b5199d46
CP		 2856 return;
2857
b78cd169
JA		 2858 if (atmel_port->fifo_size < ATMEL_MIN_FIFO_SIZE) {
2859 atmel_port->fifo_size = 0;
b5199d46
CP		 2860 dev_err(&pdev->dev, "Invalid FIFO size\n");
2861 return;
2862 }
2863
2864 /*
2865 * 0 <= rts_low <= rts_high <= fifo_size
2866 * Once their CTS line asserted by the remote peer, some x86 UARTs tend
2867 * to flush their internal TX FIFO, commonly up to 16 data, before
2868 * actually stopping to send new data. So we try to set the RTS High
2869 * Threshold to a reasonably high value respecting this 16 data
2870 * empirical rule when possible.
2871 */
b78cd169
JA		 2872 atmel_port->rts_high = max_t(int, atmel_port->fifo_size >> 1,
2873 atmel_port->fifo_size - ATMEL_RTS_HIGH_OFFSET);
2874 atmel_port->rts_low = max_t(int, atmel_port->fifo_size >> 2,
2875 atmel_port->fifo_size - ATMEL_RTS_LOW_OFFSET);
b5199d46
CP		 2876
2877 dev_info(&pdev->dev, "Using FIFO (%u data)\n",
b78cd169 2878 atmel_port->fifo_size);
b5199d46 2879 dev_dbg(&pdev->dev, "RTS High Threshold : %2u data\n",
b78cd169 2880 atmel_port->rts_high);
b5199d46 2881 dev_dbg(&pdev->dev, "RTS Low Threshold : %2u data\n",
b78cd169 2882 atmel_port->rts_low);
b5199d46
CP		 2883}
2884
9671f099 2885static int atmel_serial_probe(struct platform_device *pdev)
1e6c9c28 2886{
b78cd169 2887 struct atmel_uart_port *atmel_port;
c24d2531 2888 struct device_node *np = pdev->dev.parent->of_node;
1ecc26bd 2889 void *data;
8d41ab87 2890 int ret;
bd737f87 2891 bool rs485_enabled;
1e6c9c28 2892
9d09daf8 2893 BUILD_BUG_ON(ATMEL_SERIAL_RINGSIZE & (ATMEL_SERIAL_RINGSIZE - 1));
1ecc26bd 2894
c24d2531
RP		 2895 /*
2896 * In device tree there is no node with "atmel,at91rm9200-usart-serial"
2897 * as compatible string. This driver is probed by at91-usart mfd driver
2898 * which is just a wrapper over the atmel_serial driver and
2899 * spi-at91-usart driver. All attributes needed by this driver are
2900 * found in of_node of parent.
2901 */
2902 pdev->dev.of_node = np;
2903
92c8f7c0 2904 ret = of_alias_get_id(np, "serial");
4cbf9f48 2905 if (ret < 0)
5fbe46b6 2906 /* port id not found in platform data nor device-tree aliases:
4cbf9f48 2907 * auto-enumerate it */
503bded9 2908 ret = find_first_zero_bit(atmel_ports_in_use, ATMEL_MAX_UART);
4cbf9f48 2909
503bded9 2910 if (ret >= ATMEL_MAX_UART) {
4cbf9f48
NF		 2911 ret = -ENODEV;
2912 goto err;
2913 }
2914
503bded9 2915 if (test_and_set_bit(ret, atmel_ports_in_use)) {
4cbf9f48
NF		 2916 /* port already in use */
2917 ret = -EBUSY;
2918 goto err;
2919 }
2920
b78cd169
JA		 2921 atmel_port = &atmel_ports[ret];
2922 atmel_port->backup_imr = 0;
2923 atmel_port->uart.line = ret;
078abd98 2924 atmel_port->uart.has_sysrq = IS_ENABLED(CONFIG_SERIAL_ATMEL_CONSOLE);
b78cd169 2925 atmel_serial_probe_fifos(atmel_port, pdev);
e0b0baad 2926
98f2082c 2927 atomic_set(&atmel_port->tasklet_shutdown, 0);
b78cd169 2928 spin_lock_init(&atmel_port->lock_suspended);
2c7af5ba 2929
84b476b1
CB		 2930 atmel_port->clk = devm_clk_get(&pdev->dev, "usart");
2931 if (IS_ERR(atmel_port->clk)) {
2932 ret = PTR_ERR(atmel_port->clk);
2933 goto err;
2934 }
2935 ret = clk_prepare_enable(atmel_port->clk);
2936 if (ret)
2937 goto err;
2938
5e3ce1f2
SM		 2939 atmel_port->gclk = devm_clk_get_optional(&pdev->dev, "gclk");
2940 if (IS_ERR(atmel_port->gclk)) {
2941 ret = PTR_ERR(atmel_port->gclk);
2942 goto err_clk_disable_unprepare;
2943 }
2944
b78cd169 2945 ret = atmel_init_port(atmel_port, pdev);
91f8c2d8 2946 if (ret)
84b476b1 2947 goto err_clk_disable_unprepare;
1e6c9c28 2948
b78cd169
JA		 2949 atmel_port->gpios = mctrl_gpio_init(&atmel_port->uart, 0);
2950 if (IS_ERR(atmel_port->gpios)) {
2951 ret = PTR_ERR(atmel_port->gpios);
84b476b1 2952 goto err_clk_disable_unprepare;
18dfef9c
UKK		 2953 }
2954
b78cd169 2955 if (!atmel_use_pdc_rx(&atmel_port->uart)) {
a6670615 2956 ret = -ENOMEM;
6da2ec56
KC		 2957 data = kmalloc_array(ATMEL_SERIAL_RINGSIZE,
2958 sizeof(struct atmel_uart_char),
2959 GFP_KERNEL);
a6670615 2960 if (!data)
84b476b1 2961 goto err_clk_disable_unprepare;
b78cd169 2962 atmel_port->rx_ring.buf = data;
a6670615 2963 }
1ecc26bd 2964
b78cd169 2965 rs485_enabled = atmel_port->uart.rs485.flags & SER_RS485_ENABLED;
bd737f87 2966
b78cd169 2967 ret = uart_add_one_port(&atmel_uart, &atmel_port->uart);
dfa7f343
HS		 2968 if (ret)
2969 goto err_add_port;
2970
2971 device_init_wakeup(&pdev->dev, 1);
b78cd169 2972 platform_set_drvdata(pdev, atmel_port);
dfa7f343 2973
bd737f87 2974 if (rs485_enabled) {
b78cd169 2975 atmel_uart_writel(&atmel_port->uart, ATMEL_US_MR,
4e7decda 2976 ATMEL_US_USMODE_NORMAL);
b78cd169
JA		 2977 atmel_uart_writel(&atmel_port->uart, ATMEL_US_CR,
2978 ATMEL_US_RTSEN);
5dfbd1d7
CS		 2979 }
2980
055560b0
ES		 2981 /*
2982 * Get port name of usart or uart
2983 */
b78cd169 2984 atmel_get_ip_name(&atmel_port->uart);
055560b0 2985
d4f64187
CP		 2986 /*
2987 * The peripheral clock can now safely be disabled till the port
2988 * is used
2989 */
b78cd169 2990 clk_disable_unprepare(atmel_port->clk);
d4f64187 2991
dfa7f343
HS		 2992 return 0;
2993
2994err_add_port:
b78cd169
JA		 2995 kfree(atmel_port->rx_ring.buf);
2996 atmel_port->rx_ring.buf = NULL;
84b476b1
CB		 2997err_clk_disable_unprepare:
2998 clk_disable_unprepare(atmel_port->clk);
b78cd169 2999 clear_bit(atmel_port->uart.line, atmel_ports_in_use);
4cbf9f48 3000err:
afefc415
AV		 3001 return ret;
3002}
3003
f4a8ab04
RI		 3004/*
3005 * Even if the driver is not modular, it makes sense to be able to
3006 * unbind a device: there can be many bound devices, and there are
3007 * situations where dynamic binding and unbinding can be useful.
3008 *
3009 * For example, a connected device can require a specific firmware update
3010 * protocol that needs bitbanging on IO lines, but use the regular serial
3011 * port in the normal case.
3012 */
144b47cd 3013static void atmel_serial_remove(struct platform_device *pdev)
f4a8ab04
RI		 3014{
3015 struct uart_port *port = platform_get_drvdata(pdev);
3016 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
f4a8ab04 3017
00e8e658
NF		 3018 tasklet_kill(&atmel_port->tasklet_rx);
3019 tasklet_kill(&atmel_port->tasklet_tx);
f4a8ab04
RI		 3020
3021 device_init_wakeup(&pdev->dev, 0);
3022
d5b3d02d 3023 uart_remove_one_port(&atmel_uart, port);
f4a8ab04
RI		 3024
3025 kfree(atmel_port->rx_ring.buf);
3026
3027 /* "port" is allocated statically, so we shouldn't free it */
3028
3029 clear_bit(port->line, atmel_ports_in_use);
3030
c24d2531 3031 pdev->dev.of_node = NULL;
f4a8ab04
RI		 3032}
3033
b50058b8
CB		 3034static SIMPLE_DEV_PM_OPS(atmel_serial_pm_ops, atmel_serial_suspend,
3035 atmel_serial_resume);
3036
7192f92c
HS		 3037static struct platform_driver atmel_serial_driver = {
3038 .probe = atmel_serial_probe,
144b47cd 3039 .remove_new = atmel_serial_remove,
afefc415 3040 .driver = {
c24d2531 3041 .name = "atmel_usart_serial",
c39dfebc 3042 .of_match_table = of_match_ptr(atmel_serial_dt_ids),
b50058b8 3043 .pm = pm_ptr(&atmel_serial_pm_ops),
afefc415
AV		 3044 },
3045};
3046
7192f92c 3047static int __init atmel_serial_init(void)
afefc415
AV		 3048{
3049 int ret;
3050
7192f92c 3051 ret = uart_register_driver(&atmel_uart);
afefc415
AV		 3052 if (ret)
3053 return ret;
3054
7192f92c 3055 ret = platform_driver_register(&atmel_serial_driver);
afefc415 3056 if (ret)
7192f92c 3057 uart_unregister_driver(&atmel_uart);
afefc415
AV		 3058
3059 return ret;
3060}
c39dfebc 3061device_initcall(atmel_serial_init);
Linux 6.x block layer and io_uring tree(s)