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serial: core: clean up EXPORT_SYMBOLs
[linux-block.git] / drivers / tty / serial / atmel_serial.c
CommitLineData
e3b3d0f5 1// SPDX-License-Identifier: GPL-2.0+
1e6c9c28 2/*
72ce5732 3 * Driver for Atmel AT91 Serial ports
1e6c9c28
AV		 4 * Copyright (C) 2003 Rick Bronson
5 *
6 * Based on drivers/char/serial_sa1100.c, by Deep Blue Solutions Ltd.
7 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
8 *
a6670615 9 * DMA support added by Chip Coldwell.
1e6c9c28 10 */
1e6c9c28
AV		 11#include <linux/tty.h>
12#include <linux/ioport.h>
13#include <linux/slab.h>
14#include <linux/init.h>
15#include <linux/serial.h>
afefc415 16#include <linux/clk.h>
1e6c9c28
AV		 17#include <linux/console.h>
18#include <linux/sysrq.h>
19#include <linux/tty_flip.h>
afefc415 20#include <linux/platform_device.h>
5fbe46b6
NF		 21#include <linux/of.h>
22#include <linux/of_device.h>
a6670615 23#include <linux/dma-mapping.h>
6b997bab 24#include <linux/dmaengine.h>
93a3ddc2 25#include <linux/atmel_pdc.h>
e8faff73 26#include <linux/uaccess.h>
bcd2360c 27#include <linux/platform_data/atmel.h>
2e68c22f 28#include <linux/timer.h>
e0b0baad 29#include <linux/err.h>
ab5e4e41 30#include <linux/irq.h>
2c7af5ba 31#include <linux/suspend.h>
2b5cf14b 32#include <linux/mm.h>
635b2589 33#include <linux/io.h>
1e6c9c28 34
377fedd1 35#include <asm/div64.h>
f7512e7c 36#include <asm/ioctls.h>
1e6c9c28 37
a6670615
CC		 38#define PDC_BUFFER_SIZE 512
39/* Revisit: We should calculate this based on the actual port settings */
40#define PDC_RX_TIMEOUT (3 * 10) /* 3 bytes */
41
b5199d46
CP		 42/* The minium number of data FIFOs should be able to contain */
43#define ATMEL_MIN_FIFO_SIZE 8
44/*
45 * These two offsets are substracted from the RX FIFO size to define the RTS
46 * high and low thresholds
47 */
48#define ATMEL_RTS_HIGH_OFFSET 16
49#define ATMEL_RTS_LOW_OFFSET 20
50
1e6c9c28
AV		 51#include <linux/serial_core.h>
52
e0b0baad 53#include "serial_mctrl_gpio.h"
8961df89 54#include "atmel_serial.h"
e0b0baad 55
e8faff73
CS		 56static void atmel_start_rx(struct uart_port *port);
57static void atmel_stop_rx(struct uart_port *port);
58
749c4e60 59#ifdef CONFIG_SERIAL_ATMEL_TTYAT
1e6c9c28
AV		 60
61/* Use device name ttyAT, major 204 and minor 154-169. This is necessary if we
62 * should coexist with the 8250 driver, such as if we have an external 16C550
63 * UART. */
7192f92c 64#define SERIAL_ATMEL_MAJOR 204
1e6c9c28 65#define MINOR_START 154
7192f92c 66#define ATMEL_DEVICENAME "ttyAT"
1e6c9c28
AV		 67
68#else
69
70/* Use device name ttyS, major 4, minor 64-68. This is the usual serial port
71 * name, but it is legally reserved for the 8250 driver. */
7192f92c 72#define SERIAL_ATMEL_MAJOR TTY_MAJOR
1e6c9c28 73#define MINOR_START 64
7192f92c 74#define ATMEL_DEVICENAME "ttyS"
1e6c9c28
AV		 75
76#endif
77
7192f92c 78#define ATMEL_ISR_PASS_LIMIT 256
1e6c9c28 79
a6670615
CC		 80struct atmel_dma_buffer {
81 unsigned char *buf;
82 dma_addr_t dma_addr;
83 unsigned int dma_size;
84 unsigned int ofs;
85};
86
1ecc26bd
RB		 87struct atmel_uart_char {
88 u16 status;
89 u16 ch;
90};
91
637ba54f
LD		 92/*
93 * Be careful, the real size of the ring buffer is
94 * sizeof(atmel_uart_char) * ATMEL_SERIAL_RINGSIZE. It means that ring buffer
95 * can contain up to 1024 characters in PIO mode and up to 4096 characters in
96 * DMA mode.
97 */
1ecc26bd
RB		 98#define ATMEL_SERIAL_RINGSIZE 1024
99
9af92fbf
AB		 100/*
101 * at91: 6 USARTs and one DBGU port (SAM9260)
432f9748 102 * samx7: 3 USARTs and 5 UARTs
9af92fbf 103 */
432f9748 104#define ATMEL_MAX_UART 8
9af92fbf 105
afefc415
AV		 106/*
107 * We wrap our port structure around the generic uart_port.
108 */
7192f92c 109struct atmel_uart_port {
afefc415
AV		 110 struct uart_port uart; /* uart */
111 struct clk *clk; /* uart clock */
f05596db
AS		 112 int may_wakeup; /* cached value of device_may_wakeup for times we need to disable it */
113 u32 backup_imr; /* IMR saved during suspend */
9e6077bd 114 int break_active; /* break being received */
1ecc26bd 115
34df42f5 116 bool use_dma_rx; /* enable DMA receiver */
64e22ebe 117 bool use_pdc_rx; /* enable PDC receiver */
a6670615
CC		 118 short pdc_rx_idx; /* current PDC RX buffer */
119 struct atmel_dma_buffer pdc_rx[2]; /* PDC receier */
120
08f738be 121 bool use_dma_tx; /* enable DMA transmitter */
64e22ebe 122 bool use_pdc_tx; /* enable PDC transmitter */
a6670615
CC		 123 struct atmel_dma_buffer pdc_tx; /* PDC transmitter */
124
08f738be 125 spinlock_t lock_tx; /* port lock */
34df42f5 126 spinlock_t lock_rx; /* port lock */
08f738be 127 struct dma_chan *chan_tx;
34df42f5 128 struct dma_chan *chan_rx;
08f738be 129 struct dma_async_tx_descriptor *desc_tx;
34df42f5 130 struct dma_async_tx_descriptor *desc_rx;
08f738be 131 dma_cookie_t cookie_tx;
34df42f5 132 dma_cookie_t cookie_rx;
08f738be 133 struct scatterlist sg_tx;
34df42f5 134 struct scatterlist sg_rx;
00e8e658
NF		 135 struct tasklet_struct tasklet_rx;
136 struct tasklet_struct tasklet_tx;
98f2082c 137 atomic_t tasklet_shutdown;
1ecc26bd 138 unsigned int irq_status_prev;
5f258b3e 139 unsigned int tx_len;
1ecc26bd
RB		 140
141 struct circ_buf rx_ring;
e8faff73 142
e0b0baad 143 struct mctrl_gpios *gpios;
377fedd1
NF		 144 u32 backup_mode; /* MR saved during iso7816 operations */
145 u32 backup_brgr; /* BRGR saved during iso7816 operations */
e8faff73 146 unsigned int tx_done_mask;
b5199d46
CP		 147 u32 fifo_size;
148 u32 rts_high;
149 u32 rts_low;
ab5e4e41 150 bool ms_irq_enabled;
2958ccee 151 u32 rtor; /* address of receiver timeout register if it exists */
5bf5635a 152 bool has_frac_baudrate;
4b769371
NF		 153 bool has_hw_timer;
154 struct timer_list uart_timer;
2c7af5ba 155
ea04f82a 156 bool tx_stopped;
2c7af5ba
BB		 157 bool suspended;
158 unsigned int pending;
159 unsigned int pending_status;
160 spinlock_t lock_suspended;
161
69646d7a
RS		 162 bool hd_start_rx; /* can start RX during half-duplex operation */
163
377fedd1
NF		 164 /* ISO7816 */
165 unsigned int fidi_min;
166 unsigned int fidi_max;
167
488ae82d 168#ifdef CONFIG_PM
6a5f0e2f
AB		 169 struct {
170 u32 cr;
171 u32 mr;
172 u32 imr;
173 u32 brgr;
174 u32 rtor;
175 u32 ttgr;
176 u32 fmr;
177 u32 fimr;
178 } cache;
488ae82d 179#endif
6a5f0e2f 180
a930e528
ES		 181 int (*prepare_rx)(struct uart_port *port);
182 int (*prepare_tx)(struct uart_port *port);
183 void (*schedule_rx)(struct uart_port *port);
184 void (*schedule_tx)(struct uart_port *port);
185 void (*release_rx)(struct uart_port *port);
186 void (*release_tx)(struct uart_port *port);
afefc415
AV		 187};
188
7192f92c 189static struct atmel_uart_port atmel_ports[ATMEL_MAX_UART];
503bded9 190static DECLARE_BITMAP(atmel_ports_in_use, ATMEL_MAX_UART);
afefc415 191
5fbe46b6
NF		 192#if defined(CONFIG_OF)
193static const struct of_device_id atmel_serial_dt_ids[] = {
c24d2531 194 { .compatible = "atmel,at91rm9200-usart-serial" },
5fbe46b6
NF		 195 { /* sentinel */ }
196};
5fbe46b6
NF		 197#endif
198
c811ab8c
HS		 199static inline struct atmel_uart_port *
200to_atmel_uart_port(struct uart_port *uart)
201{
202 return container_of(uart, struct atmel_uart_port, uart);
203}
204
4e7decda
CP		 205static inline u32 atmel_uart_readl(struct uart_port *port, u32 reg)
206{
207 return __raw_readl(port->membase + reg);
208}
209
210static inline void atmel_uart_writel(struct uart_port *port, u32 reg, u32 value)
211{
212 __raw_writel(value, port->membase + reg);
213}
214
a6499435 215static inline u8 atmel_uart_read_char(struct uart_port *port)
b5199d46 216{
a6499435 217 return __raw_readb(port->membase + ATMEL_US_RHR);
b5199d46
CP		 218}
219
a6499435
CP		 220static inline void atmel_uart_write_char(struct uart_port *port, u8 value)
221{
222 __raw_writeb(value, port->membase + ATMEL_US_THR);
223}
224
f3040983
RS		 225static inline int atmel_uart_is_half_duplex(struct uart_port *port)
226{
227 return ((port->rs485.flags & SER_RS485_ENABLED) &&
228 !(port->rs485.flags & SER_RS485_RX_DURING_TX)) ||
229 (port->iso7816.flags & SER_ISO7816_ENABLED);
230}
231
a6670615 232#ifdef CONFIG_SERIAL_ATMEL_PDC
64e22ebe 233static bool atmel_use_pdc_rx(struct uart_port *port)
a6670615 234{
c811ab8c 235 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
a6670615 236
64e22ebe 237 return atmel_port->use_pdc_rx;
a6670615
CC		 238}
239
64e22ebe 240static bool atmel_use_pdc_tx(struct uart_port *port)
a6670615 241{
c811ab8c 242 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
a6670615 243
64e22ebe 244 return atmel_port->use_pdc_tx;
a6670615
CC		 245}
246#else
64e22ebe 247static bool atmel_use_pdc_rx(struct uart_port *port)
a6670615
CC		 248{
249 return false;
250}
251
64e22ebe 252static bool atmel_use_pdc_tx(struct uart_port *port)
a6670615
CC		 253{
254 return false;
255}
256#endif
257
08f738be
ES		 258static bool atmel_use_dma_tx(struct uart_port *port)
259{
260 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
261
262 return atmel_port->use_dma_tx;
263}
264
34df42f5
ES		 265static bool atmel_use_dma_rx(struct uart_port *port)
266{
267 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
268
269 return atmel_port->use_dma_rx;
270}
271
5be605ac
AB		 272static bool atmel_use_fifo(struct uart_port *port)
273{
274 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
275
276 return atmel_port->fifo_size;
277}
278
98f2082c
NF		 279static void atmel_tasklet_schedule(struct atmel_uart_port *atmel_port,
280 struct tasklet_struct *t)
281{
282 if (!atomic_read(&atmel_port->tasklet_shutdown))
283 tasklet_schedule(t);
284}
285
e8faff73 286/* Enable or disable the rs485 support */
13bd3e6f
RRD		 287static int atmel_config_rs485(struct uart_port *port,
288 struct serial_rs485 *rs485conf)
e8faff73
CS		 289{
290 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
291 unsigned int mode;
e8faff73
CS		 292
293 /* Disable interrupts */
4e7decda 294 atmel_uart_writel(port, ATMEL_US_IDR, atmel_port->tx_done_mask);
e8faff73 295
4e7decda 296 mode = atmel_uart_readl(port, ATMEL_US_MR);
e8faff73
CS		 297
298 /* Resetting serial mode to RS232 (0x0) */
299 mode &= ~ATMEL_US_USMODE;
300
13bd3e6f 301 port->rs485 = *rs485conf;
e8faff73
CS		 302
303 if (rs485conf->flags & SER_RS485_ENABLED) {
304 dev_dbg(port->dev, "Setting UART to RS485\n");
477b8383
CC		 305 if (port->rs485.flags & SER_RS485_RX_DURING_TX)
306 atmel_port->tx_done_mask = ATMEL_US_TXRDY;
307 else
308 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY;
309
4e7decda
CP		 310 atmel_uart_writel(port, ATMEL_US_TTGR,
311 rs485conf->delay_rts_after_send);
e8faff73
CS		 312 mode |= ATMEL_US_USMODE_RS485;
313 } else {
314 dev_dbg(port->dev, "Setting UART to RS232\n");
64e22ebe 315 if (atmel_use_pdc_tx(port))
e8faff73
CS		 316 atmel_port->tx_done_mask = ATMEL_US_ENDTX |
317 ATMEL_US_TXBUFE;
318 else
319 atmel_port->tx_done_mask = ATMEL_US_TXRDY;
320 }
4e7decda 321 atmel_uart_writel(port, ATMEL_US_MR, mode);
e8faff73
CS		 322
323 /* Enable interrupts */
4e7decda 324 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->tx_done_mask);
e8faff73 325
13bd3e6f 326 return 0;
e8faff73
CS		 327}
328
377fedd1
NF		 329static unsigned int atmel_calc_cd(struct uart_port *port,
330 struct serial_iso7816 *iso7816conf)
331{
332 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
333 unsigned int cd;
334 u64 mck_rate;
335
336 mck_rate = (u64)clk_get_rate(atmel_port->clk);
337 do_div(mck_rate, iso7816conf->clk);
338 cd = mck_rate;
339 return cd;
340}
341
342static unsigned int atmel_calc_fidi(struct uart_port *port,
343 struct serial_iso7816 *iso7816conf)
344{
345 u64 fidi = 0;
346
347 if (iso7816conf->sc_fi && iso7816conf->sc_di) {
348 fidi = (u64)iso7816conf->sc_fi;
349 do_div(fidi, iso7816conf->sc_di);
350 }
351 return (u32)fidi;
352}
353
354/* Enable or disable the iso7816 support */
355/* Called with interrupts disabled */
356static int atmel_config_iso7816(struct uart_port *port,
357 struct serial_iso7816 *iso7816conf)
358{
359 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
360 unsigned int mode;
361 unsigned int cd, fidi;
362 int ret = 0;
363
364 /* Disable interrupts */
365 atmel_uart_writel(port, ATMEL_US_IDR, atmel_port->tx_done_mask);
366
367 mode = atmel_uart_readl(port, ATMEL_US_MR);
368
369 if (iso7816conf->flags & SER_ISO7816_ENABLED) {
370 mode &= ~ATMEL_US_USMODE;
371
372 if (iso7816conf->tg > 255) {
373 dev_err(port->dev, "ISO7816: Timeguard exceeding 255\n");
374 memset(iso7816conf, 0, sizeof(struct serial_iso7816));
375 ret = -EINVAL;
376 goto err_out;
377 }
378
379 if ((iso7816conf->flags & SER_ISO7816_T_PARAM)
380 == SER_ISO7816_T(0)) {
381 mode |= ATMEL_US_USMODE_ISO7816_T0 | ATMEL_US_DSNACK;
382 } else if ((iso7816conf->flags & SER_ISO7816_T_PARAM)
383 == SER_ISO7816_T(1)) {
384 mode |= ATMEL_US_USMODE_ISO7816_T1 | ATMEL_US_INACK;
385 } else {
386 dev_err(port->dev, "ISO7816: Type not supported\n");
387 memset(iso7816conf, 0, sizeof(struct serial_iso7816));
388 ret = -EINVAL;
389 goto err_out;
390 }
391
392 mode &= ~(ATMEL_US_USCLKS | ATMEL_US_NBSTOP | ATMEL_US_PAR);
393
394 /* select mck clock, and output */
395 mode |= ATMEL_US_USCLKS_MCK | ATMEL_US_CLKO;
396 /* set parity for normal/inverse mode + max iterations */
397 mode |= ATMEL_US_PAR_EVEN | ATMEL_US_NBSTOP_1 | ATMEL_US_MAX_ITER(3);
398
399 cd = atmel_calc_cd(port, iso7816conf);
400 fidi = atmel_calc_fidi(port, iso7816conf);
401 if (fidi == 0) {
402 dev_warn(port->dev, "ISO7816 fidi = 0, Generator generates no signal\n");
403 } else if (fidi < atmel_port->fidi_min
404 || fidi > atmel_port->fidi_max) {
405 dev_err(port->dev, "ISO7816 fidi = %u, value not supported\n", fidi);
406 memset(iso7816conf, 0, sizeof(struct serial_iso7816));
407 ret = -EINVAL;
408 goto err_out;
409 }
410
411 if (!(port->iso7816.flags & SER_ISO7816_ENABLED)) {
412 /* port not yet in iso7816 mode: store configuration */
413 atmel_port->backup_mode = atmel_uart_readl(port, ATMEL_US_MR);
414 atmel_port->backup_brgr = atmel_uart_readl(port, ATMEL_US_BRGR);
415 }
416
417 atmel_uart_writel(port, ATMEL_US_TTGR, iso7816conf->tg);
418 atmel_uart_writel(port, ATMEL_US_BRGR, cd);
419 atmel_uart_writel(port, ATMEL_US_FIDI, fidi);
420
421 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXDIS | ATMEL_US_RXEN);
422 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY | ATMEL_US_NACK | ATMEL_US_ITERATION;
423 } else {
424 dev_dbg(port->dev, "Setting UART back to RS232\n");
425 /* back to last RS232 settings */
426 mode = atmel_port->backup_mode;
427 memset(iso7816conf, 0, sizeof(struct serial_iso7816));
428 atmel_uart_writel(port, ATMEL_US_TTGR, 0);
429 atmel_uart_writel(port, ATMEL_US_BRGR, atmel_port->backup_brgr);
430 atmel_uart_writel(port, ATMEL_US_FIDI, 0x174);
431
432 if (atmel_use_pdc_tx(port))
433 atmel_port->tx_done_mask = ATMEL_US_ENDTX |
434 ATMEL_US_TXBUFE;
435 else
436 atmel_port->tx_done_mask = ATMEL_US_TXRDY;
437 }
438
439 port->iso7816 = *iso7816conf;
440
441 atmel_uart_writel(port, ATMEL_US_MR, mode);
442
443err_out:
444 /* Enable interrupts */
445 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->tx_done_mask);
446
447 return ret;
448}
449
1e6c9c28
AV		 450/*
451 * Return TIOCSER_TEMT when transmitter FIFO and Shift register is empty.
452 */
7192f92c 453static u_int atmel_tx_empty(struct uart_port *port)
1e6c9c28 454{
ea04f82a
RI		 455 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
456
457 if (atmel_port->tx_stopped)
458 return TIOCSER_TEMT;
4e7decda
CP		 459 return (atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXEMPTY) ?
460 TIOCSER_TEMT :
461 0;
1e6c9c28
AV		 462}
463
464/*
465 * Set state of the modem control output lines
466 */
7192f92c 467static void atmel_set_mctrl(struct uart_port *port, u_int mctrl)
1e6c9c28
AV		 468{
469 unsigned int control = 0;
4e7decda 470 unsigned int mode = atmel_uart_readl(port, ATMEL_US_MR);
1cf6e8fc 471 unsigned int rts_paused, rts_ready;
e8faff73 472 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1e6c9c28 473
1cf6e8fc
CP		 474 /* override mode to RS485 if needed, otherwise keep the current mode */
475 if (port->rs485.flags & SER_RS485_ENABLED) {
4e7decda
CP		 476 atmel_uart_writel(port, ATMEL_US_TTGR,
477 port->rs485.delay_rts_after_send);
1cf6e8fc
CP		 478 mode &= ~ATMEL_US_USMODE;
479 mode |= ATMEL_US_USMODE_RS485;
480 }
481
482 /* set the RTS line state according to the mode */
483 if ((mode & ATMEL_US_USMODE) == ATMEL_US_USMODE_HWHS) {
484 /* force RTS line to high level */
485 rts_paused = ATMEL_US_RTSEN;
486
487 /* give the control of the RTS line back to the hardware */
488 rts_ready = ATMEL_US_RTSDIS;
489 } else {
490 /* force RTS line to high level */
491 rts_paused = ATMEL_US_RTSDIS;
492
493 /* force RTS line to low level */
494 rts_ready = ATMEL_US_RTSEN;
495 }
496
1e6c9c28 497 if (mctrl & TIOCM_RTS)
1cf6e8fc 498 control |= rts_ready;
1e6c9c28 499 else
1cf6e8fc 500 control |= rts_paused;
1e6c9c28
AV		 501
502 if (mctrl & TIOCM_DTR)
7192f92c 503 control |= ATMEL_US_DTREN;
1e6c9c28 504 else
7192f92c 505 control |= ATMEL_US_DTRDIS;
1e6c9c28 506
4e7decda 507 atmel_uart_writel(port, ATMEL_US_CR, control);
afefc415 508
e0b0baad
RG		 509 mctrl_gpio_set(atmel_port->gpios, mctrl);
510
afefc415 511 /* Local loopback mode? */
1cf6e8fc 512 mode &= ~ATMEL_US_CHMODE;
afefc415 513 if (mctrl & TIOCM_LOOP)
7192f92c 514 mode |= ATMEL_US_CHMODE_LOC_LOOP;
afefc415 515 else
7192f92c 516 mode |= ATMEL_US_CHMODE_NORMAL;
e8faff73 517
4e7decda 518 atmel_uart_writel(port, ATMEL_US_MR, mode);
1e6c9c28
AV		 519}
520
521/*
522 * Get state of the modem control input lines
523 */
7192f92c 524static u_int atmel_get_mctrl(struct uart_port *port)
1e6c9c28 525{
e0b0baad
RG		 526 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
527 unsigned int ret = 0, status;
1e6c9c28 528
4e7decda 529 status = atmel_uart_readl(port, ATMEL_US_CSR);
1e6c9c28
AV		 530
531 /*
532 * The control signals are active low.
533 */
7192f92c 534 if (!(status & ATMEL_US_DCD))
1e6c9c28 535 ret |= TIOCM_CD;
7192f92c 536 if (!(status & ATMEL_US_CTS))
1e6c9c28 537 ret |= TIOCM_CTS;
7192f92c 538 if (!(status & ATMEL_US_DSR))
1e6c9c28 539 ret |= TIOCM_DSR;
7192f92c 540 if (!(status & ATMEL_US_RI))
1e6c9c28
AV		 541 ret |= TIOCM_RI;
542
e0b0baad 543 return mctrl_gpio_get(atmel_port->gpios, &ret);
1e6c9c28
AV		 544}
545
546/*
547 * Stop transmitting.
548 */
7192f92c 549static void atmel_stop_tx(struct uart_port *port)
1e6c9c28 550{
e8faff73
CS		 551 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
552
64e22ebe 553 if (atmel_use_pdc_tx(port)) {
a6670615 554 /* disable PDC transmit */
4e7decda 555 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS);
e8faff73 556 }
89d82324
RG		 557
558 /*
559 * Disable the transmitter.
560 * This is mandatory when DMA is used, otherwise the DMA buffer
561 * is fully transmitted.
562 */
563 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXDIS);
ea04f82a 564 atmel_port->tx_stopped = true;
89d82324 565
e8faff73 566 /* Disable interrupts */
4e7decda 567 atmel_uart_writel(port, ATMEL_US_IDR, atmel_port->tx_done_mask);
e8faff73 568
f3040983 569 if (atmel_uart_is_half_duplex(port))
04b5bfe3
NF		 570 if (!atomic_read(&atmel_port->tasklet_shutdown))
571 atmel_start_rx(port);
f3040983 572
1e6c9c28
AV		 573}
574
575/*
576 * Start transmitting.
577 */
7192f92c 578static void atmel_start_tx(struct uart_port *port)
1e6c9c28 579{
e8faff73
CS		 580 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
581
0058f087
AB		 582 if (atmel_use_pdc_tx(port) && (atmel_uart_readl(port, ATMEL_PDC_PTSR)
583 & ATMEL_PDC_TXTEN))
584 /* The transmitter is already running. Yes, we
585 really need this.*/
586 return;
a6670615 587
0058f087 588 if (atmel_use_pdc_tx(port) || atmel_use_dma_tx(port))
f3040983 589 if (atmel_uart_is_half_duplex(port))
e8faff73
CS		 590 atmel_stop_rx(port);
591
0058f087 592 if (atmel_use_pdc_tx(port))
a6670615 593 /* re-enable PDC transmit */
4e7decda 594 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
0058f087 595
e8faff73 596 /* Enable interrupts */
4e7decda 597 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->tx_done_mask);
89d82324
RG		 598
599 /* re-enable the transmitter */
600 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN);
ea04f82a 601 atmel_port->tx_stopped = false;
e8faff73
CS		 602}
603
604/*
605 * start receiving - port is in process of being opened.
606 */
607static void atmel_start_rx(struct uart_port *port)
608{
4e7decda
CP		 609 /* reset status and receiver */
610 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
e8faff73 611
4e7decda 612 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RXEN);
57c36868 613
64e22ebe 614 if (atmel_use_pdc_rx(port)) {
e8faff73 615 /* enable PDC controller */
4e7decda
CP		 616 atmel_uart_writel(port, ATMEL_US_IER,
617 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT |
618 port->read_status_mask);
619 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN);
e8faff73 620 } else {
4e7decda 621 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_RXRDY);
e8faff73 622 }
1e6c9c28
AV		 623}
624
625/*
626 * Stop receiving - port is in process of being closed.
627 */
7192f92c 628static void atmel_stop_rx(struct uart_port *port)
1e6c9c28 629{
4e7decda 630 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RXDIS);
57c36868 631
64e22ebe 632 if (atmel_use_pdc_rx(port)) {
a6670615 633 /* disable PDC receive */
4e7decda
CP		 634 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS);
635 atmel_uart_writel(port, ATMEL_US_IDR,
636 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT |
637 port->read_status_mask);
e8faff73 638 } else {
4e7decda 639 atmel_uart_writel(port, ATMEL_US_IDR, ATMEL_US_RXRDY);
e8faff73 640 }
1e6c9c28
AV		 641}
642
643/*
644 * Enable modem status interrupts
645 */
7192f92c 646static void atmel_enable_ms(struct uart_port *port)
1e6c9c28 647{
ab5e4e41
RG		 648 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
649 uint32_t ier = 0;
650
651 /*
652 * Interrupt should not be enabled twice
653 */
654 if (atmel_port->ms_irq_enabled)
655 return;
656
657 atmel_port->ms_irq_enabled = true;
658
18dfef9c 659 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_CTS))
ab5e4e41
RG		 660 ier |= ATMEL_US_CTSIC;
661
18dfef9c 662 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DSR))
ab5e4e41
RG		 663 ier |= ATMEL_US_DSRIC;
664
18dfef9c 665 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_RI))
ab5e4e41
RG		 666 ier |= ATMEL_US_RIIC;
667
18dfef9c 668 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DCD))
ab5e4e41
RG		 669 ier |= ATMEL_US_DCDIC;
670
4e7decda 671 atmel_uart_writel(port, ATMEL_US_IER, ier);
18dfef9c
UKK		 672
673 mctrl_gpio_enable_ms(atmel_port->gpios);
1e6c9c28
AV		 674}
675
35b675b9
RG		 676/*
677 * Disable modem status interrupts
678 */
679static void atmel_disable_ms(struct uart_port *port)
680{
681 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
682 uint32_t idr = 0;
683
684 /*
685 * Interrupt should not be disabled twice
686 */
687 if (!atmel_port->ms_irq_enabled)
688 return;
689
690 atmel_port->ms_irq_enabled = false;
691
18dfef9c
UKK		 692 mctrl_gpio_disable_ms(atmel_port->gpios);
693
694 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_CTS))
35b675b9
RG		 695 idr |= ATMEL_US_CTSIC;
696
18dfef9c 697 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DSR))
35b675b9
RG		 698 idr |= ATMEL_US_DSRIC;
699
18dfef9c 700 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_RI))
35b675b9
RG		 701 idr |= ATMEL_US_RIIC;
702
18dfef9c 703 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DCD))
35b675b9
RG		 704 idr |= ATMEL_US_DCDIC;
705
4e7decda 706 atmel_uart_writel(port, ATMEL_US_IDR, idr);
35b675b9
RG		 707}
708
1e6c9c28
AV		 709/*
710 * Control the transmission of a break signal
711 */
7192f92c 712static void atmel_break_ctl(struct uart_port *port, int break_state)
1e6c9c28
AV		 713{
714 if (break_state != 0)
4e7decda
CP		 715 /* start break */
716 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTBRK);
1e6c9c28 717 else
4e7decda
CP		 718 /* stop break */
719 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STPBRK);
1e6c9c28
AV		 720}
721
1ecc26bd
RB		 722/*
723 * Stores the incoming character in the ring buffer
724 */
725static void
726atmel_buffer_rx_char(struct uart_port *port, unsigned int status,
727 unsigned int ch)
728{
c811ab8c 729 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1ecc26bd
RB		 730 struct circ_buf *ring = &atmel_port->rx_ring;
731 struct atmel_uart_char *c;
732
733 if (!CIRC_SPACE(ring->head, ring->tail, ATMEL_SERIAL_RINGSIZE))
734 /* Buffer overflow, ignore char */
735 return;
736
737 c = &((struct atmel_uart_char *)ring->buf)[ring->head];
738 c->status = status;
739 c->ch = ch;
740
741 /* Make sure the character is stored before we update head. */
742 smp_wmb();
743
744 ring->head = (ring->head + 1) & (ATMEL_SERIAL_RINGSIZE - 1);
745}
746
a6670615
CC		 747/*
748 * Deal with parity, framing and overrun errors.
749 */
750static void atmel_pdc_rxerr(struct uart_port *port, unsigned int status)
751{
752 /* clear error */
4e7decda 753 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
a6670615
CC		 754
755 if (status & ATMEL_US_RXBRK) {
756 /* ignore side-effect */
757 status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME);
758 port->icount.brk++;
759 }
760 if (status & ATMEL_US_PARE)
761 port->icount.parity++;
762 if (status & ATMEL_US_FRAME)
763 port->icount.frame++;
764 if (status & ATMEL_US_OVRE)
765 port->icount.overrun++;
766}
767
1e6c9c28
AV		 768/*
769 * Characters received (called from interrupt handler)
770 */
7d12e780 771static void atmel_rx_chars(struct uart_port *port)
1e6c9c28 772{
c811ab8c 773 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1ecc26bd 774 unsigned int status, ch;
1e6c9c28 775
4e7decda 776 status = atmel_uart_readl(port, ATMEL_US_CSR);
7192f92c 777 while (status & ATMEL_US_RXRDY) {
a6499435 778 ch = atmel_uart_read_char(port);
1e6c9c28 779
1e6c9c28
AV		 780 /*
781 * note that the error handling code is
782 * out of the main execution path
783 */
9e6077bd
HS		 784 if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME
785 | ATMEL_US_OVRE | ATMEL_US_RXBRK)
786 || atmel_port->break_active)) {
1ecc26bd 787
b843aa21 788 /* clear error */
4e7decda 789 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
1ecc26bd 790
9e6077bd
HS		 791 if (status & ATMEL_US_RXBRK
792 && !atmel_port->break_active) {
9e6077bd 793 atmel_port->break_active = 1;
4e7decda
CP		 794 atmel_uart_writel(port, ATMEL_US_IER,
795 ATMEL_US_RXBRK);
9e6077bd
HS		 796 } else {
797 /*
798 * This is either the end-of-break
799 * condition or we've received at
800 * least one character without RXBRK
801 * being set. In both cases, the next
802 * RXBRK will indicate start-of-break.
803 */
4e7decda
CP		 804 atmel_uart_writel(port, ATMEL_US_IDR,
805 ATMEL_US_RXBRK);
9e6077bd
HS		 806 status &= ~ATMEL_US_RXBRK;
807 atmel_port->break_active = 0;
afefc415 808 }
1e6c9c28
AV		 809 }
810
1ecc26bd 811 atmel_buffer_rx_char(port, status, ch);
4e7decda 812 status = atmel_uart_readl(port, ATMEL_US_CSR);
1e6c9c28
AV		 813 }
814
98f2082c 815 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_rx);
1e6c9c28
AV		 816}
817
818/*
1ecc26bd
RB		 819 * Transmit characters (called from tasklet with TXRDY interrupt
820 * disabled)
1e6c9c28 821 */
7192f92c 822static void atmel_tx_chars(struct uart_port *port)
1e6c9c28 823{
ebd2c8f6 824 struct circ_buf *xmit = &port->state->xmit;
e8faff73 825 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1e6c9c28 826
4e7decda 827 if (port->x_char &&
477b8383 828 (atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXRDY)) {
a6499435 829 atmel_uart_write_char(port, port->x_char);
1e6c9c28
AV		 830 port->icount.tx++;
831 port->x_char = 0;
1e6c9c28 832 }
1ecc26bd 833 if (uart_circ_empty(xmit) || uart_tx_stopped(port))
1e6c9c28 834 return;
1e6c9c28 835
477b8383 836 while (atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXRDY) {
a6499435 837 atmel_uart_write_char(port, xmit->buf[xmit->tail]);
1e6c9c28
AV		 838 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
839 port->icount.tx++;
840 if (uart_circ_empty(xmit))
841 break;
842 }
843
844 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
845 uart_write_wakeup(port);
846
477b8383
CC		 847 if (!uart_circ_empty(xmit)) {
848 /* we still have characters to transmit, so we should continue
849 * transmitting them when TX is ready, regardless of
850 * mode or duplexity
851 */
852 atmel_port->tx_done_mask |= ATMEL_US_TXRDY;
853
e8faff73 854 /* Enable interrupts */
4e7decda
CP		 855 atmel_uart_writel(port, ATMEL_US_IER,
856 atmel_port->tx_done_mask);
477b8383
CC		 857 } else {
858 if (atmel_uart_is_half_duplex(port))
859 atmel_port->tx_done_mask &= ~ATMEL_US_TXRDY;
860 }
1e6c9c28
AV		 861}
862
08f738be
ES		 863static void atmel_complete_tx_dma(void *arg)
864{
865 struct atmel_uart_port *atmel_port = arg;
866 struct uart_port *port = &atmel_port->uart;
867 struct circ_buf *xmit = &port->state->xmit;
868 struct dma_chan *chan = atmel_port->chan_tx;
869 unsigned long flags;
870
871 spin_lock_irqsave(&port->lock, flags);
872
873 if (chan)
874 dmaengine_terminate_all(chan);
5f258b3e 875 xmit->tail += atmel_port->tx_len;
08f738be
ES		 876 xmit->tail &= UART_XMIT_SIZE - 1;
877
5f258b3e 878 port->icount.tx += atmel_port->tx_len;
08f738be
ES		 879
880 spin_lock_irq(&atmel_port->lock_tx);
881 async_tx_ack(atmel_port->desc_tx);
882 atmel_port->cookie_tx = -EINVAL;
883 atmel_port->desc_tx = NULL;
884 spin_unlock_irq(&atmel_port->lock_tx);
885
886 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
887 uart_write_wakeup(port);
888
1842dc2e
CP		 889 /*
890 * xmit is a circular buffer so, if we have just send data from
891 * xmit->tail to the end of xmit->buf, now we have to transmit the
892 * remaining data from the beginning of xmit->buf to xmit->head.
893 */
08f738be 894 if (!uart_circ_empty(xmit))
98f2082c 895 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_tx);
f3040983 896 else if (atmel_uart_is_half_duplex(port)) {
69646d7a
RS		 897 /*
898 * DMA done, re-enable TXEMPTY and signal that we can stop
899 * TX and start RX for RS485
900 */
901 atmel_port->hd_start_rx = true;
902 atmel_uart_writel(port, ATMEL_US_IER,
903 atmel_port->tx_done_mask);
b389f173 904 }
08f738be
ES		 905
906 spin_unlock_irqrestore(&port->lock, flags);
907}
908
909static void atmel_release_tx_dma(struct uart_port *port)
910{
911 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
912 struct dma_chan *chan = atmel_port->chan_tx;
913
914 if (chan) {
915 dmaengine_terminate_all(chan);
916 dma_release_channel(chan);
917 dma_unmap_sg(port->dev, &atmel_port->sg_tx, 1,
48479148 918 DMA_TO_DEVICE);
08f738be
ES		 919 }
920
921 atmel_port->desc_tx = NULL;
922 atmel_port->chan_tx = NULL;
923 atmel_port->cookie_tx = -EINVAL;
924}
925
926/*
927 * Called from tasklet with TXRDY interrupt is disabled.
928 */
929static void atmel_tx_dma(struct uart_port *port)
930{
931 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
932 struct circ_buf *xmit = &port->state->xmit;
933 struct dma_chan *chan = atmel_port->chan_tx;
934 struct dma_async_tx_descriptor *desc;
5f258b3e
CP		 935 struct scatterlist sgl[2], *sg, *sg_tx = &atmel_port->sg_tx;
936 unsigned int tx_len, part1_len, part2_len, sg_len;
937 dma_addr_t phys_addr;
08f738be
ES		 938
939 /* Make sure we have an idle channel */
940 if (atmel_port->desc_tx != NULL)
941 return;
942
943 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) {
944 /*
945 * DMA is idle now.
946 * Port xmit buffer is already mapped,
947 * and it is one page... Just adjust
948 * offsets and lengths. Since it is a circular buffer,
949 * we have to transmit till the end, and then the rest.
950 * Take the port lock to get a
951 * consistent xmit buffer state.
952 */
5f258b3e
CP		 953 tx_len = CIRC_CNT_TO_END(xmit->head,
954 xmit->tail,
955 UART_XMIT_SIZE);
956
957 if (atmel_port->fifo_size) {
958 /* multi data mode */
959 part1_len = (tx_len & ~0x3); /* DWORD access */
960 part2_len = (tx_len & 0x3); /* BYTE access */
961 } else {
962 /* single data (legacy) mode */
963 part1_len = 0;
964 part2_len = tx_len; /* BYTE access only */
965 }
966
967 sg_init_table(sgl, 2);
968 sg_len = 0;
969 phys_addr = sg_dma_address(sg_tx) + xmit->tail;
970 if (part1_len) {
971 sg = &sgl[sg_len++];
972 sg_dma_address(sg) = phys_addr;
973 sg_dma_len(sg) = part1_len;
974
975 phys_addr += part1_len;
976 }
977
978 if (part2_len) {
979 sg = &sgl[sg_len++];
980 sg_dma_address(sg) = phys_addr;
981 sg_dma_len(sg) = part2_len;
982 }
983
984 /*
985 * save tx_len so atmel_complete_tx_dma() will increase
986 * xmit->tail correctly
987 */
988 atmel_port->tx_len = tx_len;
08f738be
ES		 989
990 desc = dmaengine_prep_slave_sg(chan,
5f258b3e
CP		 991 sgl,
992 sg_len,
1842dc2e
CP		 993 DMA_MEM_TO_DEV,
994 DMA_PREP_INTERRUPT |
995 DMA_CTRL_ACK);
08f738be
ES		 996 if (!desc) {
997 dev_err(port->dev, "Failed to send via dma!\n");
998 return;
999 }
1000
5f258b3e 1001 dma_sync_sg_for_device(port->dev, sg_tx, 1, DMA_TO_DEVICE);
08f738be
ES		 1002
1003 atmel_port->desc_tx = desc;
1004 desc->callback = atmel_complete_tx_dma;
1005 desc->callback_param = atmel_port;
1006 atmel_port->cookie_tx = dmaengine_submit(desc);
1e67bd2b
TA		 1007 if (dma_submit_error(atmel_port->cookie_tx)) {
1008 dev_err(port->dev, "dma_submit_error %d\n",
1009 atmel_port->cookie_tx);
1010 return;
1011 }
4f4b9b58
TA		 1012
1013 dma_async_issue_pending(chan);
08f738be
ES		 1014 }
1015
1016 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1017 uart_write_wakeup(port);
1018}
1019
1020static int atmel_prepare_tx_dma(struct uart_port *port)
1021{
1022 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
c24d2531 1023 struct device *mfd_dev = port->dev->parent;
08f738be
ES		 1024 dma_cap_mask_t mask;
1025 struct dma_slave_config config;
1026 int ret, nent;
1027
1028 dma_cap_zero(mask);
1029 dma_cap_set(DMA_SLAVE, mask);
1030
c24d2531 1031 atmel_port->chan_tx = dma_request_slave_channel(mfd_dev, "tx");
08f738be
ES		 1032 if (atmel_port->chan_tx == NULL)
1033 goto chan_err;
1034 dev_info(port->dev, "using %s for tx DMA transfers\n",
1035 dma_chan_name(atmel_port->chan_tx));
1036
1037 spin_lock_init(&atmel_port->lock_tx);
1038 sg_init_table(&atmel_port->sg_tx, 1);
1039 /* UART circular tx buffer is an aligned page. */
2c277054 1040 BUG_ON(!PAGE_ALIGNED(port->state->xmit.buf));
08f738be
ES		 1041 sg_set_page(&atmel_port->sg_tx,
1042 virt_to_page(port->state->xmit.buf),
1043 UART_XMIT_SIZE,
2b5cf14b 1044 offset_in_page(port->state->xmit.buf));
08f738be
ES		 1045 nent = dma_map_sg(port->dev,
1046 &atmel_port->sg_tx,
1047 1,
48479148 1048 DMA_TO_DEVICE);
08f738be
ES		 1049
1050 if (!nent) {
1051 dev_dbg(port->dev, "need to release resource of dma\n");
1052 goto chan_err;
1053 } else {
c8d1f022 1054 dev_dbg(port->dev, "%s: mapped %d@%p to %pad\n", __func__,
08f738be
ES		 1055 sg_dma_len(&atmel_port->sg_tx),
1056 port->state->xmit.buf,
c8d1f022 1057 &sg_dma_address(&atmel_port->sg_tx));
08f738be
ES		 1058 }
1059
1060 /* Configure the slave DMA */
1061 memset(&config, 0, sizeof(config));
1062 config.direction = DMA_MEM_TO_DEV;
5f258b3e
CP		 1063 config.dst_addr_width = (atmel_port->fifo_size) ?
1064 DMA_SLAVE_BUSWIDTH_4_BYTES :
1065 DMA_SLAVE_BUSWIDTH_1_BYTE;
08f738be 1066 config.dst_addr = port->mapbase + ATMEL_US_THR;
a8d4e016 1067 config.dst_maxburst = 1;
08f738be 1068
5483c10e
MR		 1069 ret = dmaengine_slave_config(atmel_port->chan_tx,
1070 &config);
08f738be
ES		 1071 if (ret) {
1072 dev_err(port->dev, "DMA tx slave configuration failed\n");
1073 goto chan_err;
1074 }
1075
1076 return 0;
1077
1078chan_err:
1079 dev_err(port->dev, "TX channel not available, switch to pio\n");
36ce7cff 1080 atmel_port->use_dma_tx = false;
08f738be
ES		 1081 if (atmel_port->chan_tx)
1082 atmel_release_tx_dma(port);
1083 return -EINVAL;
1084}
1085
34df42f5
ES		 1086static void atmel_complete_rx_dma(void *arg)
1087{
1088 struct uart_port *port = arg;
1089 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1090
98f2082c 1091 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_rx);
34df42f5
ES		 1092}
1093
1094static void atmel_release_rx_dma(struct uart_port *port)
1095{
1096 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1097 struct dma_chan *chan = atmel_port->chan_rx;
1098
1099 if (chan) {
1100 dmaengine_terminate_all(chan);
1101 dma_release_channel(chan);
1102 dma_unmap_sg(port->dev, &atmel_port->sg_rx, 1,
48479148 1103 DMA_FROM_DEVICE);
34df42f5
ES		 1104 }
1105
1106 atmel_port->desc_rx = NULL;
1107 atmel_port->chan_rx = NULL;
1108 atmel_port->cookie_rx = -EINVAL;
1109}
1110
1111static void atmel_rx_from_dma(struct uart_port *port)
1112{
1113 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
66f37aaf 1114 struct tty_port *tport = &port->state->port;
34df42f5
ES		 1115 struct circ_buf *ring = &atmel_port->rx_ring;
1116 struct dma_chan *chan = atmel_port->chan_rx;
1117 struct dma_tx_state state;
1118 enum dma_status dmastat;
66f37aaf 1119 size_t count;
34df42f5
ES		 1120
1121
1122 /* Reset the UART timeout early so that we don't miss one */
4e7decda 1123 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
34df42f5
ES		 1124 dmastat = dmaengine_tx_status(chan,
1125 atmel_port->cookie_rx,
1126 &state);
1127 /* Restart a new tasklet if DMA status is error */
1128 if (dmastat == DMA_ERROR) {
1129 dev_dbg(port->dev, "Get residue error, restart tasklet\n");
4e7decda 1130 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_TIMEOUT);
98f2082c 1131 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_rx);
34df42f5
ES		 1132 return;
1133 }
34df42f5 1134
66f37aaf
CP		 1135 /* CPU claims ownership of RX DMA buffer */
1136 dma_sync_sg_for_cpu(port->dev,
1137 &atmel_port->sg_rx,
1138 1,
485819b5 1139 DMA_FROM_DEVICE);
66f37aaf
CP		 1140
1141 /*
1142 * ring->head points to the end of data already written by the DMA.
1143 * ring->tail points to the beginning of data to be read by the
1144 * framework.
1145 * The current transfer size should not be larger than the dma buffer
1146 * length.
1147 */
1148 ring->head = sg_dma_len(&atmel_port->sg_rx) - state.residue;
1149 BUG_ON(ring->head > sg_dma_len(&atmel_port->sg_rx));
34df42f5 1150 /*
66f37aaf
CP		 1151 * At this point ring->head may point to the first byte right after the
1152 * last byte of the dma buffer:
1153 * 0 <= ring->head <= sg_dma_len(&atmel_port->sg_rx)
1154 *
1155 * However ring->tail must always points inside the dma buffer:
1156 * 0 <= ring->tail <= sg_dma_len(&atmel_port->sg_rx) - 1
1157 *
1158 * Since we use a ring buffer, we have to handle the case
1159 * where head is lower than tail. In such a case, we first read from
1160 * tail to the end of the buffer then reset tail.
34df42f5 1161 */
66f37aaf
CP		 1162 if (ring->head < ring->tail) {
1163 count = sg_dma_len(&atmel_port->sg_rx) - ring->tail;
34df42f5 1164
66f37aaf
CP		 1165 tty_insert_flip_string(tport, ring->buf + ring->tail, count);
1166 ring->tail = 0;
1167 port->icount.rx += count;
1168 }
34df42f5 1169
66f37aaf
CP		 1170 /* Finally we read data from tail to head */
1171 if (ring->tail < ring->head) {
1172 count = ring->head - ring->tail;
34df42f5 1173
66f37aaf
CP		 1174 tty_insert_flip_string(tport, ring->buf + ring->tail, count);
1175 /* Wrap ring->head if needed */
1176 if (ring->head >= sg_dma_len(&atmel_port->sg_rx))
1177 ring->head = 0;
1178 ring->tail = ring->head;
34df42f5
ES		 1179 port->icount.rx += count;
1180 }
1181
66f37aaf
CP		 1182 /* USART retreives ownership of RX DMA buffer */
1183 dma_sync_sg_for_device(port->dev,
1184 &atmel_port->sg_rx,
1185 1,
485819b5 1186 DMA_FROM_DEVICE);
66f37aaf 1187
66f37aaf 1188 tty_flip_buffer_push(tport);
66f37aaf 1189
4e7decda 1190 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_TIMEOUT);
34df42f5
ES		 1191}
1192
1193static int atmel_prepare_rx_dma(struct uart_port *port)
1194{
1195 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
c24d2531 1196 struct device *mfd_dev = port->dev->parent;
34df42f5
ES		 1197 struct dma_async_tx_descriptor *desc;
1198 dma_cap_mask_t mask;
1199 struct dma_slave_config config;
1200 struct circ_buf *ring;
1201 int ret, nent;
1202
1203 ring = &atmel_port->rx_ring;
1204
1205 dma_cap_zero(mask);
1206 dma_cap_set(DMA_CYCLIC, mask);
1207
c24d2531 1208 atmel_port->chan_rx = dma_request_slave_channel(mfd_dev, "rx");
34df42f5
ES		 1209 if (atmel_port->chan_rx == NULL)
1210 goto chan_err;
1211 dev_info(port->dev, "using %s for rx DMA transfers\n",
1212 dma_chan_name(atmel_port->chan_rx));
1213
1214 spin_lock_init(&atmel_port->lock_rx);
1215 sg_init_table(&atmel_port->sg_rx, 1);
1216 /* UART circular rx buffer is an aligned page. */
2c277054 1217 BUG_ON(!PAGE_ALIGNED(ring->buf));
34df42f5 1218 sg_set_page(&atmel_port->sg_rx,
1842dc2e 1219 virt_to_page(ring->buf),
a510880f 1220 sizeof(struct atmel_uart_char) * ATMEL_SERIAL_RINGSIZE,
2b5cf14b 1221 offset_in_page(ring->buf));
1842dc2e
CP		 1222 nent = dma_map_sg(port->dev,
1223 &atmel_port->sg_rx,
1224 1,
1225 DMA_FROM_DEVICE);
34df42f5
ES		 1226
1227 if (!nent) {
1228 dev_dbg(port->dev, "need to release resource of dma\n");
1229 goto chan_err;
1230 } else {
c8d1f022 1231 dev_dbg(port->dev, "%s: mapped %d@%p to %pad\n", __func__,
34df42f5
ES		 1232 sg_dma_len(&atmel_port->sg_rx),
1233 ring->buf,
c8d1f022 1234 &sg_dma_address(&atmel_port->sg_rx));
34df42f5
ES		 1235 }
1236
1237 /* Configure the slave DMA */
1238 memset(&config, 0, sizeof(config));
1239 config.direction = DMA_DEV_TO_MEM;
1240 config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1241 config.src_addr = port->mapbase + ATMEL_US_RHR;
a8d4e016 1242 config.src_maxburst = 1;
34df42f5 1243
5483c10e
MR		 1244 ret = dmaengine_slave_config(atmel_port->chan_rx,
1245 &config);
34df42f5
ES		 1246 if (ret) {
1247 dev_err(port->dev, "DMA rx slave configuration failed\n");
1248 goto chan_err;
1249 }
1250 /*
1251 * Prepare a cyclic dma transfer, assign 2 descriptors,
1252 * each one is half ring buffer size
1253 */
1254 desc = dmaengine_prep_dma_cyclic(atmel_port->chan_rx,
1842dc2e
CP		 1255 sg_dma_address(&atmel_port->sg_rx),
1256 sg_dma_len(&atmel_port->sg_rx),
1257 sg_dma_len(&atmel_port->sg_rx)/2,
1258 DMA_DEV_TO_MEM,
1259 DMA_PREP_INTERRUPT);
c85be041
KL		 1260 if (!desc) {
1261 dev_err(port->dev, "Preparing DMA cyclic failed\n");
1262 goto chan_err;
1263 }
34df42f5
ES		 1264 desc->callback = atmel_complete_rx_dma;
1265 desc->callback_param = port;
1266 atmel_port->desc_rx = desc;
1267 atmel_port->cookie_rx = dmaengine_submit(desc);
1e67bd2b
TA		 1268 if (dma_submit_error(atmel_port->cookie_rx)) {
1269 dev_err(port->dev, "dma_submit_error %d\n",
1270 atmel_port->cookie_rx);
1271 goto chan_err;
1272 }
34df42f5 1273
4f4b9b58
TA		 1274 dma_async_issue_pending(atmel_port->chan_rx);
1275
34df42f5
ES		 1276 return 0;
1277
1278chan_err:
1279 dev_err(port->dev, "RX channel not available, switch to pio\n");
36ce7cff 1280 atmel_port->use_dma_rx = false;
34df42f5
ES		 1281 if (atmel_port->chan_rx)
1282 atmel_release_rx_dma(port);
1283 return -EINVAL;
1284}
1285
026cb432 1286static void atmel_uart_timer_callback(struct timer_list *t)
2e68c22f 1287{
026cb432
KC		 1288 struct atmel_uart_port *atmel_port = from_timer(atmel_port, t,
1289 uart_timer);
1290 struct uart_port *port = &atmel_port->uart;
2e68c22f 1291
98f2082c
NF		 1292 if (!atomic_read(&atmel_port->tasklet_shutdown)) {
1293 tasklet_schedule(&atmel_port->tasklet_rx);
1294 mod_timer(&atmel_port->uart_timer,
1295 jiffies + uart_poll_timeout(port));
1296 }
2e68c22f
ES		 1297}
1298
b843aa21
RB		 1299/*
1300 * receive interrupt handler.
1301 */
1302static void
1303atmel_handle_receive(struct uart_port *port, unsigned int pending)
1304{
c811ab8c 1305 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
b843aa21 1306
64e22ebe 1307 if (atmel_use_pdc_rx(port)) {
a6670615
CC		 1308 /*
1309 * PDC receive. Just schedule the tasklet and let it
1310 * figure out the details.
1311 *
1312 * TODO: We're not handling error flags correctly at
1313 * the moment.
1314 */
1315 if (pending & (ATMEL_US_ENDRX | ATMEL_US_TIMEOUT)) {
4e7decda
CP		 1316 atmel_uart_writel(port, ATMEL_US_IDR,
1317 (ATMEL_US_ENDRX | ATMEL_US_TIMEOUT));
98f2082c
NF		 1318 atmel_tasklet_schedule(atmel_port,
1319 &atmel_port->tasklet_rx);
a6670615
CC		 1320 }
1321
1322 if (pending & (ATMEL_US_RXBRK | ATMEL_US_OVRE |
1323 ATMEL_US_FRAME | ATMEL_US_PARE))
1324 atmel_pdc_rxerr(port, pending);
1325 }
1326
34df42f5
ES		 1327 if (atmel_use_dma_rx(port)) {
1328 if (pending & ATMEL_US_TIMEOUT) {
4e7decda
CP		 1329 atmel_uart_writel(port, ATMEL_US_IDR,
1330 ATMEL_US_TIMEOUT);
98f2082c
NF		 1331 atmel_tasklet_schedule(atmel_port,
1332 &atmel_port->tasklet_rx);
34df42f5
ES		 1333 }
1334 }
1335
b843aa21
RB		 1336 /* Interrupt receive */
1337 if (pending & ATMEL_US_RXRDY)
1338 atmel_rx_chars(port);
1339 else if (pending & ATMEL_US_RXBRK) {
1340 /*
1341 * End of break detected. If it came along with a
1342 * character, atmel_rx_chars will handle it.
1343 */
4e7decda
CP		 1344 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
1345 atmel_uart_writel(port, ATMEL_US_IDR, ATMEL_US_RXBRK);
b843aa21
RB		 1346 atmel_port->break_active = 0;
1347 }
1348}
1349
1350/*
1ecc26bd 1351 * transmit interrupt handler. (Transmit is IRQF_NODELAY safe)
b843aa21
RB		 1352 */
1353static void
1354atmel_handle_transmit(struct uart_port *port, unsigned int pending)
1355{
c811ab8c 1356 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1ecc26bd 1357
e8faff73 1358 if (pending & atmel_port->tx_done_mask) {
4e7decda
CP		 1359 atmel_uart_writel(port, ATMEL_US_IDR,
1360 atmel_port->tx_done_mask);
69646d7a
RS		 1361
1362 /* Start RX if flag was set and FIFO is empty */
1363 if (atmel_port->hd_start_rx) {
1364 if (!(atmel_uart_readl(port, ATMEL_US_CSR)
1365 & ATMEL_US_TXEMPTY))
1366 dev_warn(port->dev, "Should start RX, but TX fifo is not empty\n");
1367
1368 atmel_port->hd_start_rx = false;
1369 atmel_start_rx(port);
69646d7a
RS		 1370 }
1371
98f2082c 1372 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_tx);
1ecc26bd 1373 }
b843aa21
RB		 1374}
1375
1376/*
1377 * status flags interrupt handler.
1378 */
1379static void
1380atmel_handle_status(struct uart_port *port, unsigned int pending,
1381 unsigned int status)
1382{
c811ab8c 1383 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
9205218e 1384 unsigned int status_change;
1ecc26bd 1385
b843aa21 1386 if (pending & (ATMEL_US_RIIC | ATMEL_US_DSRIC | ATMEL_US_DCDIC
1ecc26bd 1387 | ATMEL_US_CTSIC)) {
9205218e 1388 status_change = status ^ atmel_port->irq_status_prev;
d033e82d 1389 atmel_port->irq_status_prev = status;
9205218e
NF		 1390
1391 if (status_change & (ATMEL_US_RI | ATMEL_US_DSR
1392 | ATMEL_US_DCD | ATMEL_US_CTS)) {
1393 /* TODO: All reads to CSR will clear these interrupts! */
1394 if (status_change & ATMEL_US_RI)
1395 port->icount.rng++;
1396 if (status_change & ATMEL_US_DSR)
1397 port->icount.dsr++;
1398 if (status_change & ATMEL_US_DCD)
1399 uart_handle_dcd_change(port, !(status & ATMEL_US_DCD));
1400 if (status_change & ATMEL_US_CTS)
1401 uart_handle_cts_change(port, !(status & ATMEL_US_CTS));
1402
1403 wake_up_interruptible(&port->state->port.delta_msr_wait);
1404 }
1ecc26bd 1405 }
377fedd1
NF		 1406
1407 if (pending & (ATMEL_US_NACK | ATMEL_US_ITERATION))
1408 dev_dbg(port->dev, "ISO7816 ERROR (0x%08x)\n", pending);
b843aa21
RB		 1409}
1410
1e6c9c28
AV		 1411/*
1412 * Interrupt handler
1413 */
7d12e780 1414static irqreturn_t atmel_interrupt(int irq, void *dev_id)
1e6c9c28
AV		 1415{
1416 struct uart_port *port = dev_id;
ab5e4e41 1417 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2c7af5ba 1418 unsigned int status, pending, mask, pass_counter = 0;
1e6c9c28 1419
2c7af5ba
BB		 1420 spin_lock(&atmel_port->lock_suspended);
1421
a6670615 1422 do {
d2d8d4c0 1423 status = atmel_uart_readl(port, ATMEL_US_CSR);
4e7decda 1424 mask = atmel_uart_readl(port, ATMEL_US_IMR);
2c7af5ba 1425 pending = status & mask;
a6670615
CC		 1426 if (!pending)
1427 break;
1428
2c7af5ba
BB		 1429 if (atmel_port->suspended) {
1430 atmel_port->pending |= pending;
1431 atmel_port->pending_status = status;
4e7decda 1432 atmel_uart_writel(port, ATMEL_US_IDR, mask);
2c7af5ba
BB		 1433 pm_system_wakeup();
1434 break;
1435 }
1436
b843aa21
RB		 1437 atmel_handle_receive(port, pending);
1438 atmel_handle_status(port, pending, status);
1439 atmel_handle_transmit(port, pending);
a6670615 1440 } while (pass_counter++ < ATMEL_ISR_PASS_LIMIT);
afefc415 1441
2c7af5ba
BB		 1442 spin_unlock(&atmel_port->lock_suspended);
1443
0400b697 1444 return pass_counter ? IRQ_HANDLED : IRQ_NONE;
a6670615 1445}
1e6c9c28 1446
a930e528
ES		 1447static void atmel_release_tx_pdc(struct uart_port *port)
1448{
1449 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1450 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1451
1452 dma_unmap_single(port->dev,
1453 pdc->dma_addr,
1454 pdc->dma_size,
1455 DMA_TO_DEVICE);
1456}
1457
a6670615
CC		 1458/*
1459 * Called from tasklet with ENDTX and TXBUFE interrupts disabled.
1460 */
64e22ebe 1461static void atmel_tx_pdc(struct uart_port *port)
a6670615 1462{
c811ab8c 1463 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
ebd2c8f6 1464 struct circ_buf *xmit = &port->state->xmit;
a6670615
CC		 1465 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1466 int count;
1467
ba0657ff 1468 /* nothing left to transmit? */
4e7decda 1469 if (atmel_uart_readl(port, ATMEL_PDC_TCR))
ba0657ff
MT		 1470 return;
1471
a6670615
CC		 1472 xmit->tail += pdc->ofs;
1473 xmit->tail &= UART_XMIT_SIZE - 1;
1474
1475 port->icount.tx += pdc->ofs;
1476 pdc->ofs = 0;
1477
ba0657ff 1478 /* more to transmit - setup next transfer */
a6670615 1479
ba0657ff 1480 /* disable PDC transmit */
4e7decda 1481 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS);
ba0657ff 1482
1f14081d 1483 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) {
a6670615
CC		 1484 dma_sync_single_for_device(port->dev,
1485 pdc->dma_addr,
1486 pdc->dma_size,
1487 DMA_TO_DEVICE);
1488
1489 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
1490 pdc->ofs = count;
1491
4e7decda
CP		 1492 atmel_uart_writel(port, ATMEL_PDC_TPR,
1493 pdc->dma_addr + xmit->tail);
1494 atmel_uart_writel(port, ATMEL_PDC_TCR, count);
e8faff73 1495 /* re-enable PDC transmit */
4e7decda 1496 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
e8faff73 1497 /* Enable interrupts */
4e7decda
CP		 1498 atmel_uart_writel(port, ATMEL_US_IER,
1499 atmel_port->tx_done_mask);
e8faff73 1500 } else {
f3040983 1501 if (atmel_uart_is_half_duplex(port)) {
e8faff73
CS		 1502 /* DMA done, stop TX, start RX for RS485 */
1503 atmel_start_rx(port);
1504 }
1e6c9c28 1505 }
a6670615
CC		 1506
1507 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1508 uart_write_wakeup(port);
1e6c9c28
AV		 1509}
1510
a930e528
ES		 1511static int atmel_prepare_tx_pdc(struct uart_port *port)
1512{
1513 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1514 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1515 struct circ_buf *xmit = &port->state->xmit;
1516
1517 pdc->buf = xmit->buf;
1518 pdc->dma_addr = dma_map_single(port->dev,
1519 pdc->buf,
1520 UART_XMIT_SIZE,
1521 DMA_TO_DEVICE);
1522 pdc->dma_size = UART_XMIT_SIZE;
1523 pdc->ofs = 0;
1524
1525 return 0;
1526}
1527
1ecc26bd
RB		 1528static void atmel_rx_from_ring(struct uart_port *port)
1529{
c811ab8c 1530 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1ecc26bd
RB		 1531 struct circ_buf *ring = &atmel_port->rx_ring;
1532 unsigned int flg;
1533 unsigned int status;
1534
1535 while (ring->head != ring->tail) {
1536 struct atmel_uart_char c;
1537
1538 /* Make sure c is loaded after head. */
1539 smp_rmb();
1540
1541 c = ((struct atmel_uart_char *)ring->buf)[ring->tail];
1542
1543 ring->tail = (ring->tail + 1) & (ATMEL_SERIAL_RINGSIZE - 1);
1544
1545 port->icount.rx++;
1546 status = c.status;
1547 flg = TTY_NORMAL;
1548
1549 /*
1550 * note that the error handling code is
1551 * out of the main execution path
1552 */
1553 if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME
1554 | ATMEL_US_OVRE | ATMEL_US_RXBRK))) {
1555 if (status & ATMEL_US_RXBRK) {
1556 /* ignore side-effect */
1557 status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME);
1558
1559 port->icount.brk++;
1560 if (uart_handle_break(port))
1561 continue;
1562 }
1563 if (status & ATMEL_US_PARE)
1564 port->icount.parity++;
1565 if (status & ATMEL_US_FRAME)
1566 port->icount.frame++;
1567 if (status & ATMEL_US_OVRE)
1568 port->icount.overrun++;
1569
1570 status &= port->read_status_mask;
1571
1572 if (status & ATMEL_US_RXBRK)
1573 flg = TTY_BREAK;
1574 else if (status & ATMEL_US_PARE)
1575 flg = TTY_PARITY;
1576 else if (status & ATMEL_US_FRAME)
1577 flg = TTY_FRAME;
1578 }
1579
1580
1581 if (uart_handle_sysrq_char(port, c.ch))
1582 continue;
1583
1584 uart_insert_char(port, status, ATMEL_US_OVRE, c.ch, flg);
1585 }
1586
2e124b4a 1587 tty_flip_buffer_push(&port->state->port);
1ecc26bd
RB		 1588}
1589
a930e528
ES		 1590static void atmel_release_rx_pdc(struct uart_port *port)
1591{
1592 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1593 int i;
1594
1595 for (i = 0; i < 2; i++) {
1596 struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i];
1597
1598 dma_unmap_single(port->dev,
1599 pdc->dma_addr,
1600 pdc->dma_size,
1601 DMA_FROM_DEVICE);
1602 kfree(pdc->buf);
1603 }
1604}
1605
64e22ebe 1606static void atmel_rx_from_pdc(struct uart_port *port)
a6670615 1607{
c811ab8c 1608 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
05c7cd39 1609 struct tty_port *tport = &port->state->port;
a6670615
CC		 1610 struct atmel_dma_buffer *pdc;
1611 int rx_idx = atmel_port->pdc_rx_idx;
1612 unsigned int head;
1613 unsigned int tail;
1614 unsigned int count;
1615
1616 do {
1617 /* Reset the UART timeout early so that we don't miss one */
4e7decda 1618 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
a6670615
CC		 1619
1620 pdc = &atmel_port->pdc_rx[rx_idx];
4e7decda 1621 head = atmel_uart_readl(port, ATMEL_PDC_RPR) - pdc->dma_addr;
a6670615
CC		 1622 tail = pdc->ofs;
1623
1624 /* If the PDC has switched buffers, RPR won't contain
1625 * any address within the current buffer. Since head
1626 * is unsigned, we just need a one-way comparison to
1627 * find out.
1628 *
1629 * In this case, we just need to consume the entire
1630 * buffer and resubmit it for DMA. This will clear the
1631 * ENDRX bit as well, so that we can safely re-enable
1632 * all interrupts below.
1633 */
1634 head = min(head, pdc->dma_size);
1635
1636 if (likely(head != tail)) {
1637 dma_sync_single_for_cpu(port->dev, pdc->dma_addr,
1638 pdc->dma_size, DMA_FROM_DEVICE);
1639
1640 /*
1641 * head will only wrap around when we recycle
1642 * the DMA buffer, and when that happens, we
1643 * explicitly set tail to 0. So head will
1644 * always be greater than tail.
1645 */
1646 count = head - tail;
1647
05c7cd39
JS		 1648 tty_insert_flip_string(tport, pdc->buf + pdc->ofs,
1649 count);
a6670615
CC		 1650
1651 dma_sync_single_for_device(port->dev, pdc->dma_addr,
1652 pdc->dma_size, DMA_FROM_DEVICE);
1653
1654 port->icount.rx += count;
1655 pdc->ofs = head;
1656 }
1657
1658 /*
1659 * If the current buffer is full, we need to check if
1660 * the next one contains any additional data.
1661 */
1662 if (head >= pdc->dma_size) {
1663 pdc->ofs = 0;
4e7decda
CP		 1664 atmel_uart_writel(port, ATMEL_PDC_RNPR, pdc->dma_addr);
1665 atmel_uart_writel(port, ATMEL_PDC_RNCR, pdc->dma_size);
a6670615
CC		 1666
1667 rx_idx = !rx_idx;
1668 atmel_port->pdc_rx_idx = rx_idx;
1669 }
1670 } while (head >= pdc->dma_size);
1671
2e124b4a 1672 tty_flip_buffer_push(tport);
a6670615 1673
4e7decda
CP		 1674 atmel_uart_writel(port, ATMEL_US_IER,
1675 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT);
a6670615
CC		 1676}
1677
a930e528
ES		 1678static int atmel_prepare_rx_pdc(struct uart_port *port)
1679{
1680 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1681 int i;
1682
1683 for (i = 0; i < 2; i++) {
1684 struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i];
1685
1686 pdc->buf = kmalloc(PDC_BUFFER_SIZE, GFP_KERNEL);
1687 if (pdc->buf == NULL) {
1688 if (i != 0) {
1689 dma_unmap_single(port->dev,
1690 atmel_port->pdc_rx[0].dma_addr,
1691 PDC_BUFFER_SIZE,
1692 DMA_FROM_DEVICE);
1693 kfree(atmel_port->pdc_rx[0].buf);
1694 }
36ce7cff 1695 atmel_port->use_pdc_rx = false;
a930e528
ES		 1696 return -ENOMEM;
1697 }
1698 pdc->dma_addr = dma_map_single(port->dev,
1699 pdc->buf,
1700 PDC_BUFFER_SIZE,
1701 DMA_FROM_DEVICE);
1702 pdc->dma_size = PDC_BUFFER_SIZE;
1703 pdc->ofs = 0;
1704 }
1705
1706 atmel_port->pdc_rx_idx = 0;
1707
4e7decda
CP		 1708 atmel_uart_writel(port, ATMEL_PDC_RPR, atmel_port->pdc_rx[0].dma_addr);
1709 atmel_uart_writel(port, ATMEL_PDC_RCR, PDC_BUFFER_SIZE);
a930e528 1710
4e7decda
CP		 1711 atmel_uart_writel(port, ATMEL_PDC_RNPR,
1712 atmel_port->pdc_rx[1].dma_addr);
1713 atmel_uart_writel(port, ATMEL_PDC_RNCR, PDC_BUFFER_SIZE);
a930e528
ES		 1714
1715 return 0;
1716}
1717
1ecc26bd
RB		 1718/*
1719 * tasklet handling tty stuff outside the interrupt handler.
1720 */
41e85e44 1721static void atmel_tasklet_rx_func(struct tasklet_struct *t)
1ecc26bd 1722{
41e85e44
AP		 1723 struct atmel_uart_port *atmel_port = from_tasklet(atmel_port, t,
1724 tasklet_rx);
1725 struct uart_port *port = &atmel_port->uart;
1ecc26bd
RB		 1726
1727 /* The interrupt handler does not take the lock */
1728 spin_lock(&port->lock);
a930e528 1729 atmel_port->schedule_rx(port);
00e8e658
NF		 1730 spin_unlock(&port->lock);
1731}
1ecc26bd 1732
41e85e44 1733static void atmel_tasklet_tx_func(struct tasklet_struct *t)
00e8e658 1734{
41e85e44
AP		 1735 struct atmel_uart_port *atmel_port = from_tasklet(atmel_port, t,
1736 tasklet_tx);
1737 struct uart_port *port = &atmel_port->uart;
00e8e658
NF		 1738
1739 /* The interrupt handler does not take the lock */
1740 spin_lock(&port->lock);
1741 atmel_port->schedule_tx(port);
1ecc26bd
RB		 1742 spin_unlock(&port->lock);
1743}
1744
4a1e8888 1745static void atmel_init_property(struct atmel_uart_port *atmel_port,
33d64c4f
ES		 1746 struct platform_device *pdev)
1747{
1748 struct device_node *np = pdev->dev.of_node;
92c8f7c0
AB		 1749
1750 /* DMA/PDC usage specification */
1751 if (of_property_read_bool(np, "atmel,use-dma-rx")) {
1752 if (of_property_read_bool(np, "dmas")) {
1753 atmel_port->use_dma_rx = true;
1754 atmel_port->use_pdc_rx = false;
33d64c4f
ES		 1755 } else {
1756 atmel_port->use_dma_rx = false;
92c8f7c0 1757 atmel_port->use_pdc_rx = true;
33d64c4f 1758 }
92c8f7c0
AB		 1759 } else {
1760 atmel_port->use_dma_rx = false;
1761 atmel_port->use_pdc_rx = false;
1762 }
33d64c4f 1763
92c8f7c0
AB		 1764 if (of_property_read_bool(np, "atmel,use-dma-tx")) {
1765 if (of_property_read_bool(np, "dmas")) {
1766 atmel_port->use_dma_tx = true;
1767 atmel_port->use_pdc_tx = false;
33d64c4f
ES		 1768 } else {
1769 atmel_port->use_dma_tx = false;
92c8f7c0 1770 atmel_port->use_pdc_tx = true;
33d64c4f 1771 }
33d64c4f 1772 } else {
33d64c4f 1773 atmel_port->use_dma_tx = false;
92c8f7c0 1774 atmel_port->use_pdc_tx = false;
33d64c4f 1775 }
33d64c4f
ES		 1776}
1777
a930e528
ES		 1778static void atmel_set_ops(struct uart_port *port)
1779{
1780 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1781
34df42f5
ES		 1782 if (atmel_use_dma_rx(port)) {
1783 atmel_port->prepare_rx = &atmel_prepare_rx_dma;
1784 atmel_port->schedule_rx = &atmel_rx_from_dma;
1785 atmel_port->release_rx = &atmel_release_rx_dma;
1786 } else if (atmel_use_pdc_rx(port)) {
a930e528
ES		 1787 atmel_port->prepare_rx = &atmel_prepare_rx_pdc;
1788 atmel_port->schedule_rx = &atmel_rx_from_pdc;
1789 atmel_port->release_rx = &atmel_release_rx_pdc;
1790 } else {
1791 atmel_port->prepare_rx = NULL;
1792 atmel_port->schedule_rx = &atmel_rx_from_ring;
1793 atmel_port->release_rx = NULL;
1794 }
1795
08f738be
ES		 1796 if (atmel_use_dma_tx(port)) {
1797 atmel_port->prepare_tx = &atmel_prepare_tx_dma;
1798 atmel_port->schedule_tx = &atmel_tx_dma;
1799 atmel_port->release_tx = &atmel_release_tx_dma;
1800 } else if (atmel_use_pdc_tx(port)) {
a930e528
ES		 1801 atmel_port->prepare_tx = &atmel_prepare_tx_pdc;
1802 atmel_port->schedule_tx = &atmel_tx_pdc;
1803 atmel_port->release_tx = &atmel_release_tx_pdc;
1804 } else {
1805 atmel_port->prepare_tx = NULL;
1806 atmel_port->schedule_tx = &atmel_tx_chars;
1807 atmel_port->release_tx = NULL;
1808 }
1809}
1810
055560b0
ES		 1811/*
1812 * Get ip name usart or uart
1813 */
892db58b 1814static void atmel_get_ip_name(struct uart_port *port)
055560b0
ES		 1815{
1816 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
4e7decda 1817 int name = atmel_uart_readl(port, ATMEL_US_NAME);
731d9cae 1818 u32 version;
1d673fb9 1819 u32 usart, dbgu_uart, new_uart;
4b769371
NF		 1820 /* ASCII decoding for IP version */
1821 usart = 0x55534152; /* USAR(T) */
1822 dbgu_uart = 0x44424755; /* DBGU */
1d673fb9 1823 new_uart = 0x55415254; /* UART */
055560b0 1824
5bf5635a
LD		 1825 /*
1826 * Only USART devices from at91sam9260 SOC implement fractional
2867af2d
RI		 1827 * baudrate. It is available for all asynchronous modes, with the
1828 * following restriction: the sampling clock's duty cycle is not
1829 * constant.
5bf5635a
LD		 1830 */
1831 atmel_port->has_frac_baudrate = false;
4b769371 1832 atmel_port->has_hw_timer = false;
055560b0 1833
2958ccee
LD		 1834 if (name == new_uart) {
1835 dev_dbg(port->dev, "Uart with hw timer");
4b769371 1836 atmel_port->has_hw_timer = true;
2958ccee
LD		 1837 atmel_port->rtor = ATMEL_UA_RTOR;
1838 } else if (name == usart) {
1839 dev_dbg(port->dev, "Usart\n");
5bf5635a 1840 atmel_port->has_frac_baudrate = true;
2958ccee
LD		 1841 atmel_port->has_hw_timer = true;
1842 atmel_port->rtor = ATMEL_US_RTOR;
377fedd1
NF		 1843 version = atmel_uart_readl(port, ATMEL_US_VERSION);
1844 switch (version) {
1845 case 0x814: /* sama5d2 */
df561f66 1846 fallthrough;
377fedd1
NF		 1847 case 0x701: /* sama5d4 */
1848 atmel_port->fidi_min = 3;
1849 atmel_port->fidi_max = 65535;
1850 break;
1851 case 0x502: /* sam9x5, sama5d3 */
1852 atmel_port->fidi_min = 3;
1853 atmel_port->fidi_max = 2047;
1854 break;
1855 default:
1856 atmel_port->fidi_min = 1;
1857 atmel_port->fidi_max = 2047;
1858 }
4b769371
NF		 1859 } else if (name == dbgu_uart) {
1860 dev_dbg(port->dev, "Dbgu or uart without hw timer\n");
055560b0 1861 } else {
731d9cae 1862 /* fallback for older SoCs: use version field */
4e7decda 1863 version = atmel_uart_readl(port, ATMEL_US_VERSION);
731d9cae
NF		 1864 switch (version) {
1865 case 0x302:
1866 case 0x10213:
fd63a890 1867 case 0x10302:
731d9cae 1868 dev_dbg(port->dev, "This version is usart\n");
5bf5635a 1869 atmel_port->has_frac_baudrate = true;
4b769371 1870 atmel_port->has_hw_timer = true;
2958ccee 1871 atmel_port->rtor = ATMEL_US_RTOR;
731d9cae
NF		 1872 break;
1873 case 0x203:
1874 case 0x10202:
1875 dev_dbg(port->dev, "This version is uart\n");
731d9cae
NF		 1876 break;
1877 default:
1878 dev_err(port->dev, "Not supported ip name nor version, set to uart\n");
1879 }
055560b0 1880 }
055560b0
ES		 1881}
1882
1e6c9c28
AV		 1883/*
1884 * Perform initialization and enable port for reception
1885 */
7192f92c 1886static int atmel_startup(struct uart_port *port)
1e6c9c28 1887{
33d64c4f 1888 struct platform_device *pdev = to_platform_device(port->dev);
c811ab8c 1889 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1e6c9c28
AV		 1890 int retval;
1891
1892 /*
1893 * Ensure that no interrupts are enabled otherwise when
1894 * request_irq() is called we could get stuck trying to
1895 * handle an unexpected interrupt
1896 */
4e7decda 1897 atmel_uart_writel(port, ATMEL_US_IDR, -1);
ab5e4e41 1898 atmel_port->ms_irq_enabled = false;
1e6c9c28
AV		 1899
1900 /*
1901 * Allocate the IRQ
1902 */
2c7af5ba 1903 retval = request_irq(port->irq, atmel_interrupt,
9594b5be
SAS		 1904 IRQF_SHARED | IRQF_COND_SUSPEND,
1905 dev_name(&pdev->dev), port);
1e6c9c28 1906 if (retval) {
ddaa6037 1907 dev_err(port->dev, "atmel_startup - Can't get irq\n");
1e6c9c28
AV		 1908 return retval;
1909 }
1910
98f2082c 1911 atomic_set(&atmel_port->tasklet_shutdown, 0);
41e85e44
AP		 1912 tasklet_setup(&atmel_port->tasklet_rx, atmel_tasklet_rx_func);
1913 tasklet_setup(&atmel_port->tasklet_tx, atmel_tasklet_tx_func);
1e125786 1914
a6670615
CC		 1915 /*
1916 * Initialize DMA (if necessary)
1917 */
33d64c4f 1918 atmel_init_property(atmel_port, pdev);
4d9628a1 1919 atmel_set_ops(port);
33d64c4f 1920
a930e528
ES		 1921 if (atmel_port->prepare_rx) {
1922 retval = atmel_port->prepare_rx(port);
1923 if (retval < 0)
1924 atmel_set_ops(port);
a6670615 1925 }
a6670615 1926
a930e528
ES		 1927 if (atmel_port->prepare_tx) {
1928 retval = atmel_port->prepare_tx(port);
1929 if (retval < 0)
1930 atmel_set_ops(port);
a6670615 1931 }
1e6c9c28 1932
b5199d46
CP		 1933 /*
1934 * Enable FIFO when available
1935 */
1936 if (atmel_port->fifo_size) {
1937 unsigned int txrdym = ATMEL_US_ONE_DATA;
1938 unsigned int rxrdym = ATMEL_US_ONE_DATA;
1939 unsigned int fmr;
1940
1941 atmel_uart_writel(port, ATMEL_US_CR,
1942 ATMEL_US_FIFOEN |
1943 ATMEL_US_RXFCLR |
1944 ATMEL_US_TXFLCLR);
1945
5f258b3e
CP		 1946 if (atmel_use_dma_tx(port))
1947 txrdym = ATMEL_US_FOUR_DATA;
1948
b5199d46
CP		 1949 fmr = ATMEL_US_TXRDYM(txrdym) | ATMEL_US_RXRDYM(rxrdym);
1950 if (atmel_port->rts_high &&
1951 atmel_port->rts_low)
1952 fmr |= ATMEL_US_FRTSC |
1953 ATMEL_US_RXFTHRES(atmel_port->rts_high) |
1954 ATMEL_US_RXFTHRES2(atmel_port->rts_low);
1955
1956 atmel_uart_writel(port, ATMEL_US_FMR, fmr);
1957 }
1958
27c0c8e5 1959 /* Save current CSR for comparison in atmel_tasklet_func() */
d2d8d4c0 1960 atmel_port->irq_status_prev = atmel_uart_readl(port, ATMEL_US_CSR);
27c0c8e5 1961
1e6c9c28
AV		 1962 /*
1963 * Finally, enable the serial port
1964 */
4e7decda 1965 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
b843aa21 1966 /* enable xmit & rcvr */
4e7decda 1967 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN);
ea04f82a 1968 atmel_port->tx_stopped = false;
afefc415 1969
026cb432 1970 timer_setup(&atmel_port->uart_timer, atmel_uart_timer_callback, 0);
8bc661bf 1971
64e22ebe 1972 if (atmel_use_pdc_rx(port)) {
a6670615 1973 /* set UART timeout */
4b769371 1974 if (!atmel_port->has_hw_timer) {
2e68c22f
ES		 1975 mod_timer(&atmel_port->uart_timer,
1976 jiffies + uart_poll_timeout(port));
1977 /* set USART timeout */
1978 } else {
2958ccee
LD		 1979 atmel_uart_writel(port, atmel_port->rtor,
1980 PDC_RX_TIMEOUT);
4e7decda 1981 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
a6670615 1982
4e7decda
CP		 1983 atmel_uart_writel(port, ATMEL_US_IER,
1984 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT);
2e68c22f 1985 }
a6670615 1986 /* enable PDC controller */
4e7decda 1987 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN);
34df42f5 1988 } else if (atmel_use_dma_rx(port)) {
2e68c22f 1989 /* set UART timeout */
4b769371 1990 if (!atmel_port->has_hw_timer) {
2e68c22f
ES		 1991 mod_timer(&atmel_port->uart_timer,
1992 jiffies + uart_poll_timeout(port));
1993 /* set USART timeout */
1994 } else {
2958ccee
LD		 1995 atmel_uart_writel(port, atmel_port->rtor,
1996 PDC_RX_TIMEOUT);
4e7decda 1997 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
34df42f5 1998
4e7decda
CP		 1999 atmel_uart_writel(port, ATMEL_US_IER,
2000 ATMEL_US_TIMEOUT);
2e68c22f 2001 }
a6670615
CC		 2002 } else {
2003 /* enable receive only */
4e7decda 2004 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_RXRDY);
a6670615 2005 }
afefc415 2006
1e6c9c28
AV		 2007 return 0;
2008}
2009
479e9b94
PH		 2010/*
2011 * Flush any TX data submitted for DMA. Called when the TX circular
2012 * buffer is reset.
2013 */
2014static void atmel_flush_buffer(struct uart_port *port)
2015{
2016 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2017
2018 if (atmel_use_pdc_tx(port)) {
4e7decda 2019 atmel_uart_writel(port, ATMEL_PDC_TCR, 0);
479e9b94
PH		 2020 atmel_port->pdc_tx.ofs = 0;
2021 }
31ca2c63
RG		 2022 /*
2023 * in uart_flush_buffer(), the xmit circular buffer has just
2024 * been cleared, so we have to reset tx_len accordingly.
2025 */
2026 atmel_port->tx_len = 0;
479e9b94
PH		 2027}
2028
1e6c9c28
AV		 2029/*
2030 * Disable the port
2031 */
7192f92c 2032static void atmel_shutdown(struct uart_port *port)
1e6c9c28 2033{
c811ab8c 2034 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
0cc7c6c7 2035
0ae9fdef
RG		 2036 /* Disable modem control lines interrupts */
2037 atmel_disable_ms(port);
2038
98f2082c
NF		 2039 /* Disable interrupts at device level */
2040 atmel_uart_writel(port, ATMEL_US_IDR, -1);
2041
2042 /* Prevent spurious interrupts from scheduling the tasklet */
2043 atomic_inc(&atmel_port->tasklet_shutdown);
2044
8bc661bf
MR		 2045 /*
2046 * Prevent any tasklets being scheduled during
2047 * cleanup
2048 */
2049 del_timer_sync(&atmel_port->uart_timer);
2050
98f2082c
NF		 2051 /* Make sure that no interrupt is on the fly */
2052 synchronize_irq(port->irq);
2053
0cc7c6c7
MR		 2054 /*
2055 * Clear out any scheduled tasklets before
2056 * we destroy the buffers
2057 */
00e8e658
NF		 2058 tasklet_kill(&atmel_port->tasklet_rx);
2059 tasklet_kill(&atmel_port->tasklet_tx);
0cc7c6c7 2060
a6670615 2061 /*
0cc7c6c7 2062 * Ensure everything is stopped and
98f2082c 2063 * disable port and break condition.
a6670615
CC		 2064 */
2065 atmel_stop_rx(port);
2066 atmel_stop_tx(port);
2067
4e7decda 2068 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
0cc7c6c7 2069
a6670615
CC		 2070 /*
2071 * Shut-down the DMA.
2072 */
a930e528
ES		 2073 if (atmel_port->release_rx)
2074 atmel_port->release_rx(port);
2075 if (atmel_port->release_tx)
2076 atmel_port->release_tx(port);
a6670615 2077
bb7e73c5
MD		 2078 /*
2079 * Reset ring buffer pointers
2080 */
2081 atmel_port->rx_ring.head = 0;
2082 atmel_port->rx_ring.tail = 0;
2083
1e6c9c28 2084 /*
ab5e4e41 2085 * Free the interrupts
1e6c9c28
AV		 2086 */
2087 free_irq(port->irq, port);
ab5e4e41 2088
479e9b94 2089 atmel_flush_buffer(port);
9afd561a
HS		 2090}
2091
1e6c9c28
AV		 2092/*
2093 * Power / Clock management.
2094 */
b843aa21
RB		 2095static void atmel_serial_pm(struct uart_port *port, unsigned int state,
2096 unsigned int oldstate)
1e6c9c28 2097{
c811ab8c 2098 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
afefc415 2099
1e6c9c28 2100 switch (state) {
aec079f8 2101 case UART_PM_STATE_ON:
b843aa21
RB		 2102 /*
2103 * Enable the peripheral clock for this serial port.
2104 * This is called on uart_open() or a resume event.
2105 */
91f8c2d8 2106 clk_prepare_enable(atmel_port->clk);
f05596db
AS		 2107
2108 /* re-enable interrupts if we disabled some on suspend */
4e7decda 2109 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->backup_imr);
b843aa21 2110 break;
aec079f8 2111 case UART_PM_STATE_OFF:
f05596db 2112 /* Back up the interrupt mask and disable all interrupts */
4e7decda
CP		 2113 atmel_port->backup_imr = atmel_uart_readl(port, ATMEL_US_IMR);
2114 atmel_uart_writel(port, ATMEL_US_IDR, -1);
f05596db 2115
b843aa21
RB		 2116 /*
2117 * Disable the peripheral clock for this serial port.
2118 * This is called on uart_close() or a suspend event.
2119 */
91f8c2d8 2120 clk_disable_unprepare(atmel_port->clk);
b843aa21
RB		 2121 break;
2122 default:
ddaa6037 2123 dev_err(port->dev, "atmel_serial: unknown pm %d\n", state);
1e6c9c28
AV		 2124 }
2125}
2126
2127/*
2128 * Change the port parameters
2129 */
b843aa21
RB		 2130static void atmel_set_termios(struct uart_port *port, struct ktermios *termios,
2131 struct ktermios *old)
1e6c9c28 2132{
5bf5635a 2133 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1e6c9c28 2134 unsigned long flags;
5bf5635a 2135 unsigned int old_mode, mode, imr, quot, baud, div, cd, fp = 0;
1cf6e8fc
CP		 2136
2137 /* save the current mode register */
4e7decda 2138 mode = old_mode = atmel_uart_readl(port, ATMEL_US_MR);
1e6c9c28 2139
1cf6e8fc
CP		 2140 /* reset the mode, clock divisor, parity, stop bits and data size */
2141 mode &= ~(ATMEL_US_USCLKS | ATMEL_US_CHRL | ATMEL_US_NBSTOP |
2142 ATMEL_US_PAR | ATMEL_US_USMODE);
03abeac0 2143
b843aa21 2144 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
1e6c9c28
AV		 2145
2146 /* byte size */
2147 switch (termios->c_cflag & CSIZE) {
2148 case CS5:
7192f92c 2149 mode |= ATMEL_US_CHRL_5;
1e6c9c28
AV		 2150 break;
2151 case CS6:
7192f92c 2152 mode |= ATMEL_US_CHRL_6;
1e6c9c28
AV		 2153 break;
2154 case CS7:
7192f92c 2155 mode |= ATMEL_US_CHRL_7;
1e6c9c28
AV		 2156 break;
2157 default:
7192f92c 2158 mode |= ATMEL_US_CHRL_8;
1e6c9c28
AV		 2159 break;
2160 }
2161
2162 /* stop bits */
2163 if (termios->c_cflag & CSTOPB)
7192f92c 2164 mode |= ATMEL_US_NBSTOP_2;
1e6c9c28
AV		 2165
2166 /* parity */
2167 if (termios->c_cflag & PARENB) {
b843aa21
RB		 2168 /* Mark or Space parity */
2169 if (termios->c_cflag & CMSPAR) {
1e6c9c28 2170 if (termios->c_cflag & PARODD)
7192f92c 2171 mode |= ATMEL_US_PAR_MARK;
1e6c9c28 2172 else
7192f92c 2173 mode |= ATMEL_US_PAR_SPACE;
b843aa21 2174 } else if (termios->c_cflag & PARODD)
7192f92c 2175 mode |= ATMEL_US_PAR_ODD;
1e6c9c28 2176 else
7192f92c 2177 mode |= ATMEL_US_PAR_EVEN;
b843aa21 2178 } else
7192f92c 2179 mode |= ATMEL_US_PAR_NONE;
1e6c9c28
AV		 2180
2181 spin_lock_irqsave(&port->lock, flags);
2182
7192f92c 2183 port->read_status_mask = ATMEL_US_OVRE;
1e6c9c28 2184 if (termios->c_iflag & INPCK)
7192f92c 2185 port->read_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE);
ef8b9ddc 2186 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
7192f92c 2187 port->read_status_mask |= ATMEL_US_RXBRK;
1e6c9c28 2188
64e22ebe 2189 if (atmel_use_pdc_rx(port))
a6670615 2190 /* need to enable error interrupts */
4e7decda 2191 atmel_uart_writel(port, ATMEL_US_IER, port->read_status_mask);
a6670615 2192
1e6c9c28
AV		 2193 /*
2194 * Characters to ignore
2195 */
2196 port->ignore_status_mask = 0;
2197 if (termios->c_iflag & IGNPAR)
7192f92c 2198 port->ignore_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE);
1e6c9c28 2199 if (termios->c_iflag & IGNBRK) {
7192f92c 2200 port->ignore_status_mask |= ATMEL_US_RXBRK;
1e6c9c28
AV		 2201 /*
2202 * If we're ignoring parity and break indicators,
2203 * ignore overruns too (for real raw support).
2204 */
2205 if (termios->c_iflag & IGNPAR)
7192f92c 2206 port->ignore_status_mask |= ATMEL_US_OVRE;
1e6c9c28 2207 }
b843aa21 2208 /* TODO: Ignore all characters if CREAD is set.*/
1e6c9c28
AV		 2209
2210 /* update the per-port timeout */
2211 uart_update_timeout(port, termios->c_cflag, baud);
2212
0ccad870
HS		 2213 /*
2214 * save/disable interrupts. The tty layer will ensure that the
2215 * transmitter is empty if requested by the caller, so there's
2216 * no need to wait for it here.
2217 */
4e7decda
CP		 2218 imr = atmel_uart_readl(port, ATMEL_US_IMR);
2219 atmel_uart_writel(port, ATMEL_US_IDR, -1);
1e6c9c28
AV		 2220
2221 /* disable receiver and transmitter */
4e7decda 2222 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXDIS | ATMEL_US_RXDIS);
ea04f82a 2223 atmel_port->tx_stopped = true;
1e6c9c28 2224
1cf6e8fc 2225 /* mode */
13bd3e6f 2226 if (port->rs485.flags & SER_RS485_ENABLED) {
4e7decda
CP		 2227 atmel_uart_writel(port, ATMEL_US_TTGR,
2228 port->rs485.delay_rts_after_send);
e8faff73 2229 mode |= ATMEL_US_USMODE_RS485;
377fedd1
NF		 2230 } else if (port->iso7816.flags & SER_ISO7816_ENABLED) {
2231 atmel_uart_writel(port, ATMEL_US_TTGR, port->iso7816.tg);
2232 /* select mck clock, and output */
2233 mode |= ATMEL_US_USCLKS_MCK | ATMEL_US_CLKO;
2234 /* set max iterations */
2235 mode |= ATMEL_US_MAX_ITER(3);
2236 if ((port->iso7816.flags & SER_ISO7816_T_PARAM)
2237 == SER_ISO7816_T(0))
2238 mode |= ATMEL_US_USMODE_ISO7816_T0;
2239 else
2240 mode |= ATMEL_US_USMODE_ISO7816_T1;
1cf6e8fc
CP		 2241 } else if (termios->c_cflag & CRTSCTS) {
2242 /* RS232 with hardware handshake (RTS/CTS) */
9bcffe75
RG		 2243 if (atmel_use_fifo(port) &&
2244 !mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_CTS)) {
2245 /*
2246 * with ATMEL_US_USMODE_HWHS set, the controller will
2247 * be able to drive the RTS pin high/low when the RX
2248 * FIFO is above RXFTHRES/below RXFTHRES2.
2249 * It will also disable the transmitter when the CTS
2250 * pin is high.
2251 * This mode is not activated if CTS pin is a GPIO
2252 * because in this case, the transmitter is always
2253 * disabled (there must be an internal pull-up
2254 * responsible for this behaviour).
2255 * If the RTS pin is a GPIO, the controller won't be
2256 * able to drive it according to the FIFO thresholds,
2257 * but it will be handled by the driver.
2258 */
5be605ac 2259 mode |= ATMEL_US_USMODE_HWHS;
9bcffe75
RG		 2260 } else {
2261 /*
2262 * For platforms without FIFO, the flow control is
2263 * handled by the driver.
2264 */
2265 mode |= ATMEL_US_USMODE_NORMAL;
5be605ac 2266 }
1cf6e8fc
CP		 2267 } else {
2268 /* RS232 without hadware handshake */
2269 mode |= ATMEL_US_USMODE_NORMAL;
e8faff73
CS		 2270 }
2271
5bf5635a
LD		 2272 /*
2273 * Set the baud rate:
2274 * Fractional baudrate allows to setup output frequency more
2275 * accurately. This feature is enabled only when using normal mode.
2276 * baudrate = selected clock / (8 * (2 - OVER) * (CD + FP / 8))
2277 * Currently, OVER is always set to 0 so we get
36131cdf
AS		 2278 * baudrate = selected clock / (16 * (CD + FP / 8))
2279 * then
2280 * 8 CD + FP = selected clock / (2 * baudrate)
5bf5635a 2281 */
2867af2d 2282 if (atmel_port->has_frac_baudrate) {
36131cdf
AS		 2283 div = DIV_ROUND_CLOSEST(port->uartclk, baud * 2);
2284 cd = div >> 3;
2285 fp = div & ATMEL_US_FP_MASK;
5bf5635a
LD		 2286 } else {
2287 cd = uart_get_divisor(port, baud);
2288 }
2289
2290 if (cd > 65535) { /* BRGR is 16-bit, so switch to slower clock */
2291 cd /= 8;
2292 mode |= ATMEL_US_USCLKS_MCK_DIV8;
2293 }
2294 quot = cd | fp << ATMEL_US_FP_OFFSET;
2295
377fedd1
NF		 2296 if (!(port->iso7816.flags & SER_ISO7816_ENABLED))
2297 atmel_uart_writel(port, ATMEL_US_BRGR, quot);
cb47b9f8
DE		 2298
2299 /* set the mode, clock divisor, parity, stop bits and data size */
2300 atmel_uart_writel(port, ATMEL_US_MR, mode);
2301
2302 /*
2303 * when switching the mode, set the RTS line state according to the
2304 * new mode, otherwise keep the former state
2305 */
2306 if ((old_mode & ATMEL_US_USMODE) != (mode & ATMEL_US_USMODE)) {
2307 unsigned int rts_state;
2308
2309 if ((mode & ATMEL_US_USMODE) == ATMEL_US_USMODE_HWHS) {
2310 /* let the hardware control the RTS line */
2311 rts_state = ATMEL_US_RTSDIS;
2312 } else {
2313 /* force RTS line to low level */
2314 rts_state = ATMEL_US_RTSEN;
2315 }
2316
2317 atmel_uart_writel(port, ATMEL_US_CR, rts_state);
2318 }
2319
4e7decda
CP		 2320 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
2321 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN);
ea04f82a 2322 atmel_port->tx_stopped = false;
1e6c9c28
AV		 2323
2324 /* restore interrupts */
4e7decda 2325 atmel_uart_writel(port, ATMEL_US_IER, imr);
1e6c9c28
AV		 2326
2327 /* CTS flow-control and modem-status interrupts */
2328 if (UART_ENABLE_MS(port, termios->c_cflag))
35b675b9
RG		 2329 atmel_enable_ms(port);
2330 else
2331 atmel_disable_ms(port);
1e6c9c28
AV		 2332
2333 spin_unlock_irqrestore(&port->lock, flags);
2334}
2335
732a84a0 2336static void atmel_set_ldisc(struct uart_port *port, struct ktermios *termios)
42bd7a4f 2337{
732a84a0 2338 if (termios->c_line == N_PPS) {
42bd7a4f 2339 port->flags |= UPF_HARDPPS_CD;
d41510ce 2340 spin_lock_irq(&port->lock);
42bd7a4f 2341 atmel_enable_ms(port);
d41510ce 2342 spin_unlock_irq(&port->lock);
42bd7a4f
VP		 2343 } else {
2344 port->flags &= ~UPF_HARDPPS_CD;
cab68f89
PH		 2345 if (!UART_ENABLE_MS(port, termios->c_cflag)) {
2346 spin_lock_irq(&port->lock);
2347 atmel_disable_ms(port);
2348 spin_unlock_irq(&port->lock);
2349 }
42bd7a4f
VP		 2350 }
2351}
2352
1e6c9c28
AV		 2353/*
2354 * Return string describing the specified port
2355 */
7192f92c 2356static const char *atmel_type(struct uart_port *port)
1e6c9c28 2357{
9ab4f88b 2358 return (port->type == PORT_ATMEL) ? "ATMEL_SERIAL" : NULL;
1e6c9c28
AV		 2359}
2360
2361/*
2362 * Release the memory region(s) being used by 'port'.
2363 */
7192f92c 2364static void atmel_release_port(struct uart_port *port)
1e6c9c28 2365{
c24d2531
RP		 2366 struct platform_device *mpdev = to_platform_device(port->dev->parent);
2367 int size = resource_size(mpdev->resource);
afefc415
AV		 2368
2369 release_mem_region(port->mapbase, size);
2370
2371 if (port->flags & UPF_IOREMAP) {
2372 iounmap(port->membase);
2373 port->membase = NULL;
2374 }
1e6c9c28
AV		 2375}
2376
2377/*
2378 * Request the memory region(s) being used by 'port'.
2379 */
7192f92c 2380static int atmel_request_port(struct uart_port *port)
1e6c9c28 2381{
c24d2531
RP		 2382 struct platform_device *mpdev = to_platform_device(port->dev->parent);
2383 int size = resource_size(mpdev->resource);
afefc415 2384
7192f92c 2385 if (!request_mem_region(port->mapbase, size, "atmel_serial"))
afefc415
AV		 2386 return -EBUSY;
2387
2388 if (port->flags & UPF_IOREMAP) {
2389 port->membase = ioremap(port->mapbase, size);
2390 if (port->membase == NULL) {
2391 release_mem_region(port->mapbase, size);
2392 return -ENOMEM;
2393 }
2394 }
1e6c9c28 2395
afefc415 2396 return 0;
1e6c9c28
AV		 2397}
2398
2399/*
2400 * Configure/autoconfigure the port.
2401 */
7192f92c 2402static void atmel_config_port(struct uart_port *port, int flags)
1e6c9c28
AV		 2403{
2404 if (flags & UART_CONFIG_TYPE) {
9ab4f88b 2405 port->type = PORT_ATMEL;
7192f92c 2406 atmel_request_port(port);
1e6c9c28
AV		 2407 }
2408}
2409
2410/*
2411 * Verify the new serial_struct (for TIOCSSERIAL).
2412 */
7192f92c 2413static int atmel_verify_port(struct uart_port *port, struct serial_struct *ser)
1e6c9c28
AV		 2414{
2415 int ret = 0;
9ab4f88b 2416 if (ser->type != PORT_UNKNOWN && ser->type != PORT_ATMEL)
1e6c9c28
AV		 2417 ret = -EINVAL;
2418 if (port->irq != ser->irq)
2419 ret = -EINVAL;
2420 if (ser->io_type != SERIAL_IO_MEM)
2421 ret = -EINVAL;
2422 if (port->uartclk / 16 != ser->baud_base)
2423 ret = -EINVAL;
270c2ade 2424 if (port->mapbase != (unsigned long)ser->iomem_base)
1e6c9c28
AV		 2425 ret = -EINVAL;
2426 if (port->iobase != ser->port)
2427 ret = -EINVAL;
2428 if (ser->hub6 != 0)
2429 ret = -EINVAL;
2430 return ret;
2431}
2432
8fe2d541
AT		 2433#ifdef CONFIG_CONSOLE_POLL
2434static int atmel_poll_get_char(struct uart_port *port)
2435{
4e7decda 2436 while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_RXRDY))
8fe2d541
AT		 2437 cpu_relax();
2438
a6499435 2439 return atmel_uart_read_char(port);
8fe2d541
AT		 2440}
2441
2442static void atmel_poll_put_char(struct uart_port *port, unsigned char ch)
2443{
4e7decda 2444 while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXRDY))
8fe2d541
AT		 2445 cpu_relax();
2446
a6499435 2447 atmel_uart_write_char(port, ch);
8fe2d541
AT		 2448}
2449#endif
2450
5c7dcdb6 2451static const struct uart_ops atmel_pops = {
7192f92c
HS		 2452 .tx_empty = atmel_tx_empty,
2453 .set_mctrl = atmel_set_mctrl,
2454 .get_mctrl = atmel_get_mctrl,
2455 .stop_tx = atmel_stop_tx,
2456 .start_tx = atmel_start_tx,
2457 .stop_rx = atmel_stop_rx,
2458 .enable_ms = atmel_enable_ms,
2459 .break_ctl = atmel_break_ctl,
2460 .startup = atmel_startup,
2461 .shutdown = atmel_shutdown,
9afd561a 2462 .flush_buffer = atmel_flush_buffer,
7192f92c 2463 .set_termios = atmel_set_termios,
42bd7a4f 2464 .set_ldisc = atmel_set_ldisc,
7192f92c
HS		 2465 .type = atmel_type,
2466 .release_port = atmel_release_port,
2467 .request_port = atmel_request_port,
2468 .config_port = atmel_config_port,
2469 .verify_port = atmel_verify_port,
2470 .pm = atmel_serial_pm,
8fe2d541
AT		 2471#ifdef CONFIG_CONSOLE_POLL
2472 .poll_get_char = atmel_poll_get_char,
2473 .poll_put_char = atmel_poll_put_char,
2474#endif
1e6c9c28
AV		 2475};
2476
afefc415
AV		 2477/*
2478 * Configure the port from the platform device resource info.
2479 */
91f8c2d8 2480static int atmel_init_port(struct atmel_uart_port *atmel_port,
b843aa21 2481 struct platform_device *pdev)
1e6c9c28 2482{
91f8c2d8 2483 int ret;
7192f92c 2484 struct uart_port *port = &atmel_port->uart;
c24d2531 2485 struct platform_device *mpdev = to_platform_device(pdev->dev.parent);
afefc415 2486
4a1e8888
LZ		 2487 atmel_init_property(atmel_port, pdev);
2488 atmel_set_ops(port);
afefc415 2489
e8faff73 2490 port->iotype = UPIO_MEM;
92c8f7c0 2491 port->flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP;
e8faff73
CS		 2492 port->ops = &atmel_pops;
2493 port->fifosize = 1;
e8faff73 2494 port->dev = &pdev->dev;
c24d2531 2495 port->mapbase = mpdev->resource[0].start;
5bb221b0 2496 port->irq = platform_get_irq(mpdev, 0);
13bd3e6f 2497 port->rs485_config = atmel_config_rs485;
377fedd1 2498 port->iso7816_config = atmel_config_iso7816;
c24d2531 2499 port->membase = NULL;
afefc415 2500
1ecc26bd
RB		 2501 memset(&atmel_port->rx_ring, 0, sizeof(atmel_port->rx_ring));
2502
c150c0f3
LW		 2503 ret = uart_get_rs485_mode(port);
2504 if (ret)
2505 return ret;
2506
b843aa21
RB		 2507 /* for console, the clock could already be configured */
2508 if (!atmel_port->clk) {
c24d2531 2509 atmel_port->clk = clk_get(&mpdev->dev, "usart");
91f8c2d8
BB		 2510 if (IS_ERR(atmel_port->clk)) {
2511 ret = PTR_ERR(atmel_port->clk);
2512 atmel_port->clk = NULL;
2513 return ret;
2514 }
2515 ret = clk_prepare_enable(atmel_port->clk);
2516 if (ret) {
2517 clk_put(atmel_port->clk);
2518 atmel_port->clk = NULL;
2519 return ret;
2520 }
7192f92c 2521 port->uartclk = clk_get_rate(atmel_port->clk);
91f8c2d8 2522 clk_disable_unprepare(atmel_port->clk);
06a7f058 2523 /* only enable clock when USART is in use */
afefc415 2524 }
a6670615 2525
377fedd1
NF		 2526 /*
2527 * Use TXEMPTY for interrupt when rs485 or ISO7816 else TXRDY or
2528 * ENDTX|TXBUFE
2529 */
477b8383 2530 if (atmel_uart_is_half_duplex(port))
e8faff73 2531 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY;
64e22ebe 2532 else if (atmel_use_pdc_tx(port)) {
a6670615 2533 port->fifosize = PDC_BUFFER_SIZE;
e8faff73
CS		 2534 atmel_port->tx_done_mask = ATMEL_US_ENDTX | ATMEL_US_TXBUFE;
2535 } else {
2536 atmel_port->tx_done_mask = ATMEL_US_TXRDY;
2537 }
91f8c2d8
BB		 2538
2539 return 0;
1e6c9c28
AV		 2540}
2541
749c4e60 2542#ifdef CONFIG_SERIAL_ATMEL_CONSOLE
7192f92c 2543static void atmel_console_putchar(struct uart_port *port, int ch)
d358788f 2544{
4e7decda 2545 while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXRDY))
829dd811 2546 cpu_relax();
a6499435 2547 atmel_uart_write_char(port, ch);
d358788f 2548}
1e6c9c28
AV		 2549
2550/*
2551 * Interrupts are disabled on entering
2552 */
7192f92c 2553static void atmel_console_write(struct console *co, const char *s, u_int count)
1e6c9c28 2554{
7192f92c 2555 struct uart_port *port = &atmel_ports[co->index].uart;
e8faff73 2556 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
d358788f 2557 unsigned int status, imr;
39d4c922 2558 unsigned int pdc_tx;
1e6c9c28
AV		 2559
2560 /*
b843aa21 2561 * First, save IMR and then disable interrupts
1e6c9c28 2562 */
4e7decda
CP		 2563 imr = atmel_uart_readl(port, ATMEL_US_IMR);
2564 atmel_uart_writel(port, ATMEL_US_IDR,
2565 ATMEL_US_RXRDY | atmel_port->tx_done_mask);
1e6c9c28 2566
39d4c922 2567 /* Store PDC transmit status and disable it */
4e7decda
CP		 2568 pdc_tx = atmel_uart_readl(port, ATMEL_PDC_PTSR) & ATMEL_PDC_TXTEN;
2569 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS);
39d4c922 2570
497e1e16
NF		 2571 /* Make sure that tx path is actually able to send characters */
2572 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN);
ea04f82a 2573 atmel_port->tx_stopped = false;
497e1e16 2574
7192f92c 2575 uart_console_write(port, s, count, atmel_console_putchar);
1e6c9c28
AV		 2576
2577 /*
b843aa21
RB		 2578 * Finally, wait for transmitter to become empty
2579 * and restore IMR
1e6c9c28
AV		 2580 */
2581 do {
4e7decda 2582 status = atmel_uart_readl(port, ATMEL_US_CSR);
7192f92c 2583 } while (!(status & ATMEL_US_TXRDY));
39d4c922
MP		 2584
2585 /* Restore PDC transmit status */
2586 if (pdc_tx)
4e7decda 2587 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
39d4c922 2588
b843aa21 2589 /* set interrupts back the way they were */
4e7decda 2590 atmel_uart_writel(port, ATMEL_US_IER, imr);
1e6c9c28
AV		 2591}
2592
2593/*
b843aa21
RB		 2594 * If the port was already initialised (eg, by a boot loader),
2595 * try to determine the current setup.
1e6c9c28 2596 */
b843aa21
RB		 2597static void __init atmel_console_get_options(struct uart_port *port, int *baud,
2598 int *parity, int *bits)
1e6c9c28
AV		 2599{
2600 unsigned int mr, quot;
2601
1c0fd82f
HS		 2602 /*
2603 * If the baud rate generator isn't running, the port wasn't
2604 * initialized by the boot loader.
2605 */
4e7decda 2606 quot = atmel_uart_readl(port, ATMEL_US_BRGR) & ATMEL_US_CD;
1c0fd82f
HS		 2607 if (!quot)
2608 return;
1e6c9c28 2609
4e7decda 2610 mr = atmel_uart_readl(port, ATMEL_US_MR) & ATMEL_US_CHRL;
7192f92c 2611 if (mr == ATMEL_US_CHRL_8)
1e6c9c28
AV		 2612 *bits = 8;
2613 else
2614 *bits = 7;
2615
4e7decda 2616 mr = atmel_uart_readl(port, ATMEL_US_MR) & ATMEL_US_PAR;
7192f92c 2617 if (mr == ATMEL_US_PAR_EVEN)
1e6c9c28 2618 *parity = 'e';
7192f92c 2619 else if (mr == ATMEL_US_PAR_ODD)
1e6c9c28
AV		 2620 *parity = 'o';
2621
4d5e392c
HS		 2622 /*
2623 * The serial core only rounds down when matching this to a
2624 * supported baud rate. Make sure we don't end up slightly
2625 * lower than one of those, as it would make us fall through
2626 * to a much lower baud rate than we really want.
2627 */
4d5e392c 2628 *baud = port->uartclk / (16 * (quot - 1));
1e6c9c28
AV		 2629}
2630
7192f92c 2631static int __init atmel_console_setup(struct console *co, char *options)
1e6c9c28 2632{
91f8c2d8 2633 int ret;
7192f92c 2634 struct uart_port *port = &atmel_ports[co->index].uart;
ea04f82a 2635 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1e6c9c28
AV		 2636 int baud = 115200;
2637 int bits = 8;
2638 int parity = 'n';
2639 int flow = 'n';
2640
b843aa21
RB		 2641 if (port->membase == NULL) {
2642 /* Port not initialized yet - delay setup */
afefc415 2643 return -ENODEV;
b843aa21 2644 }
1e6c9c28 2645
91f8c2d8
BB		 2646 ret = clk_prepare_enable(atmel_ports[co->index].clk);
2647 if (ret)
2648 return ret;
06a7f058 2649
4e7decda
CP		 2650 atmel_uart_writel(port, ATMEL_US_IDR, -1);
2651 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
2652 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN);
ea04f82a 2653 atmel_port->tx_stopped = false;
1e6c9c28
AV		 2654
2655 if (options)
2656 uart_parse_options(options, &baud, &parity, &bits, &flow);
2657 else
7192f92c 2658 atmel_console_get_options(port, &baud, &parity, &bits);
1e6c9c28
AV		 2659
2660 return uart_set_options(port, co, baud, parity, bits, flow);
2661}
2662
7192f92c 2663static struct uart_driver atmel_uart;
1e6c9c28 2664
7192f92c
HS		 2665static struct console atmel_console = {
2666 .name = ATMEL_DEVICENAME,
2667 .write = atmel_console_write,
1e6c9c28 2668 .device = uart_console_device,
7192f92c 2669 .setup = atmel_console_setup,
1e6c9c28
AV		 2670 .flags = CON_PRINTBUFFER,
2671 .index = -1,
7192f92c 2672 .data = &atmel_uart,
1e6c9c28
AV		 2673};
2674
06a7f058 2675#define ATMEL_CONSOLE_DEVICE (&atmel_console)
1e6c9c28 2676
1e6c9c28 2677#else
7192f92c 2678#define ATMEL_CONSOLE_DEVICE NULL
1e6c9c28
AV		 2679#endif
2680
7192f92c 2681static struct uart_driver atmel_uart = {
b843aa21
RB		 2682 .owner = THIS_MODULE,
2683 .driver_name = "atmel_serial",
2684 .dev_name = ATMEL_DEVICENAME,
2685 .major = SERIAL_ATMEL_MAJOR,
2686 .minor = MINOR_START,
2687 .nr = ATMEL_MAX_UART,
2688 .cons = ATMEL_CONSOLE_DEVICE,
1e6c9c28
AV		 2689};
2690
afefc415 2691#ifdef CONFIG_PM
f826caa4
HS		 2692static bool atmel_serial_clk_will_stop(void)
2693{
2694#ifdef CONFIG_ARCH_AT91
2695 return at91_suspend_entering_slow_clock();
2696#else
2697 return false;
2698#endif
2699}
2700
b843aa21
RB		 2701static int atmel_serial_suspend(struct platform_device *pdev,
2702 pm_message_t state)
1e6c9c28 2703{
afefc415 2704 struct uart_port *port = platform_get_drvdata(pdev);
c811ab8c 2705 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
afefc415 2706
207f6f34 2707 if (uart_console(port) && console_suspend_enabled) {
e1c609ef 2708 /* Drain the TX shifter */
4e7decda
CP		 2709 while (!(atmel_uart_readl(port, ATMEL_US_CSR) &
2710 ATMEL_US_TXEMPTY))
e1c609ef
HS		 2711 cpu_relax();
2712 }
2713
207f6f34 2714 if (uart_console(port) && !console_suspend_enabled) {
6a5f0e2f
AB		 2715 /* Cache register values as we won't get a full shutdown/startup
2716 * cycle
2717 */
2718 atmel_port->cache.mr = atmel_uart_readl(port, ATMEL_US_MR);
2719 atmel_port->cache.imr = atmel_uart_readl(port, ATMEL_US_IMR);
2720 atmel_port->cache.brgr = atmel_uart_readl(port, ATMEL_US_BRGR);
2721 atmel_port->cache.rtor = atmel_uart_readl(port,
2722 atmel_port->rtor);
2723 atmel_port->cache.ttgr = atmel_uart_readl(port, ATMEL_US_TTGR);
2724 atmel_port->cache.fmr = atmel_uart_readl(port, ATMEL_US_FMR);
2725 atmel_port->cache.fimr = atmel_uart_readl(port, ATMEL_US_FIMR);
2726 }
2727
f05596db
AS		 2728 /* we can not wake up if we're running on slow clock */
2729 atmel_port->may_wakeup = device_may_wakeup(&pdev->dev);
2c7af5ba
BB		 2730 if (atmel_serial_clk_will_stop()) {
2731 unsigned long flags;
2732
2733 spin_lock_irqsave(&atmel_port->lock_suspended, flags);
2734 atmel_port->suspended = true;
2735 spin_unlock_irqrestore(&atmel_port->lock_suspended, flags);
f05596db 2736 device_set_wakeup_enable(&pdev->dev, 0);
2c7af5ba 2737 }
f05596db
AS		 2738
2739 uart_suspend_port(&atmel_uart, port);
1e6c9c28 2740
afefc415
AV		 2741 return 0;
2742}
1e6c9c28 2743
7192f92c 2744static int atmel_serial_resume(struct platform_device *pdev)
afefc415
AV		 2745{
2746 struct uart_port *port = platform_get_drvdata(pdev);
c811ab8c 2747 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2c7af5ba
BB		 2748 unsigned long flags;
2749
207f6f34 2750 if (uart_console(port) && !console_suspend_enabled) {
6a5f0e2f
AB		 2751 atmel_uart_writel(port, ATMEL_US_MR, atmel_port->cache.mr);
2752 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->cache.imr);
2753 atmel_uart_writel(port, ATMEL_US_BRGR, atmel_port->cache.brgr);
2754 atmel_uart_writel(port, atmel_port->rtor,
2755 atmel_port->cache.rtor);
2756 atmel_uart_writel(port, ATMEL_US_TTGR, atmel_port->cache.ttgr);
2757
2758 if (atmel_port->fifo_size) {
2759 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_FIFOEN |
2760 ATMEL_US_RXFCLR | ATMEL_US_TXFLCLR);
2761 atmel_uart_writel(port, ATMEL_US_FMR,
2762 atmel_port->cache.fmr);
2763 atmel_uart_writel(port, ATMEL_US_FIER,
2764 atmel_port->cache.fimr);
2765 }
2766 atmel_start_rx(port);
2767 }
2768
2c7af5ba
BB		 2769 spin_lock_irqsave(&atmel_port->lock_suspended, flags);
2770 if (atmel_port->pending) {
2771 atmel_handle_receive(port, atmel_port->pending);
2772 atmel_handle_status(port, atmel_port->pending,
2773 atmel_port->pending_status);
2774 atmel_handle_transmit(port, atmel_port->pending);
2775 atmel_port->pending = 0;
2776 }
2777 atmel_port->suspended = false;
2778 spin_unlock_irqrestore(&atmel_port->lock_suspended, flags);
1e6c9c28 2779
f05596db
AS		 2780 uart_resume_port(&atmel_uart, port);
2781 device_set_wakeup_enable(&pdev->dev, atmel_port->may_wakeup);
1e6c9c28
AV		 2782
2783 return 0;
2784}
afefc415 2785#else
7192f92c
HS		 2786#define atmel_serial_suspend NULL
2787#define atmel_serial_resume NULL
afefc415 2788#endif
1e6c9c28 2789
b78cd169 2790static void atmel_serial_probe_fifos(struct atmel_uart_port *atmel_port,
b5199d46
CP		 2791 struct platform_device *pdev)
2792{
b78cd169
JA		 2793 atmel_port->fifo_size = 0;
2794 atmel_port->rts_low = 0;
2795 atmel_port->rts_high = 0;
b5199d46
CP		 2796
2797 if (of_property_read_u32(pdev->dev.of_node,
2798 "atmel,fifo-size",
b78cd169 2799 &atmel_port->fifo_size))
b5199d46
CP		 2800 return;
2801
b78cd169 2802 if (!atmel_port->fifo_size)
b5199d46
CP		 2803 return;
2804
b78cd169
JA		 2805 if (atmel_port->fifo_size < ATMEL_MIN_FIFO_SIZE) {
2806 atmel_port->fifo_size = 0;
b5199d46
CP		 2807 dev_err(&pdev->dev, "Invalid FIFO size\n");
2808 return;
2809 }
2810
2811 /*
2812 * 0 <= rts_low <= rts_high <= fifo_size
2813 * Once their CTS line asserted by the remote peer, some x86 UARTs tend
2814 * to flush their internal TX FIFO, commonly up to 16 data, before
2815 * actually stopping to send new data. So we try to set the RTS High
2816 * Threshold to a reasonably high value respecting this 16 data
2817 * empirical rule when possible.
2818 */
b78cd169
JA		 2819 atmel_port->rts_high = max_t(int, atmel_port->fifo_size >> 1,
2820 atmel_port->fifo_size - ATMEL_RTS_HIGH_OFFSET);
2821 atmel_port->rts_low = max_t(int, atmel_port->fifo_size >> 2,
2822 atmel_port->fifo_size - ATMEL_RTS_LOW_OFFSET);
b5199d46
CP		 2823
2824 dev_info(&pdev->dev, "Using FIFO (%u data)\n",
b78cd169 2825 atmel_port->fifo_size);
b5199d46 2826 dev_dbg(&pdev->dev, "RTS High Threshold : %2u data\n",
b78cd169 2827 atmel_port->rts_high);
b5199d46 2828 dev_dbg(&pdev->dev, "RTS Low Threshold : %2u data\n",
b78cd169 2829 atmel_port->rts_low);
b5199d46
CP		 2830}
2831
9671f099 2832static int atmel_serial_probe(struct platform_device *pdev)
1e6c9c28 2833{
b78cd169 2834 struct atmel_uart_port *atmel_port;
c24d2531 2835 struct device_node *np = pdev->dev.parent->of_node;
1ecc26bd 2836 void *data;
8d41ab87 2837 int ret;
bd737f87 2838 bool rs485_enabled;
1e6c9c28 2839
9d09daf8 2840 BUILD_BUG_ON(ATMEL_SERIAL_RINGSIZE & (ATMEL_SERIAL_RINGSIZE - 1));
1ecc26bd 2841
c24d2531
RP		 2842 /*
2843 * In device tree there is no node with "atmel,at91rm9200-usart-serial"
2844 * as compatible string. This driver is probed by at91-usart mfd driver
2845 * which is just a wrapper over the atmel_serial driver and
2846 * spi-at91-usart driver. All attributes needed by this driver are
2847 * found in of_node of parent.
2848 */
2849 pdev->dev.of_node = np;
2850
92c8f7c0 2851 ret = of_alias_get_id(np, "serial");
4cbf9f48 2852 if (ret < 0)
5fbe46b6 2853 /* port id not found in platform data nor device-tree aliases:
4cbf9f48 2854 * auto-enumerate it */
503bded9 2855 ret = find_first_zero_bit(atmel_ports_in_use, ATMEL_MAX_UART);
4cbf9f48 2856
503bded9 2857 if (ret >= ATMEL_MAX_UART) {
4cbf9f48
NF		 2858 ret = -ENODEV;
2859 goto err;
2860 }
2861
503bded9 2862 if (test_and_set_bit(ret, atmel_ports_in_use)) {
4cbf9f48
NF		 2863 /* port already in use */
2864 ret = -EBUSY;
2865 goto err;
2866 }
2867
b78cd169
JA		 2868 atmel_port = &atmel_ports[ret];
2869 atmel_port->backup_imr = 0;
2870 atmel_port->uart.line = ret;
078abd98 2871 atmel_port->uart.has_sysrq = IS_ENABLED(CONFIG_SERIAL_ATMEL_CONSOLE);
b78cd169 2872 atmel_serial_probe_fifos(atmel_port, pdev);
e0b0baad 2873
98f2082c 2874 atomic_set(&atmel_port->tasklet_shutdown, 0);
b78cd169 2875 spin_lock_init(&atmel_port->lock_suspended);
2c7af5ba 2876
b78cd169 2877 ret = atmel_init_port(atmel_port, pdev);
91f8c2d8 2878 if (ret)
6fbb9bdf 2879 goto err_clear_bit;
1e6c9c28 2880
b78cd169
JA		 2881 atmel_port->gpios = mctrl_gpio_init(&atmel_port->uart, 0);
2882 if (IS_ERR(atmel_port->gpios)) {
2883 ret = PTR_ERR(atmel_port->gpios);
18dfef9c
UKK		 2884 goto err_clear_bit;
2885 }
2886
b78cd169 2887 if (!atmel_use_pdc_rx(&atmel_port->uart)) {
a6670615 2888 ret = -ENOMEM;
6da2ec56
KC		 2889 data = kmalloc_array(ATMEL_SERIAL_RINGSIZE,
2890 sizeof(struct atmel_uart_char),
2891 GFP_KERNEL);
a6670615
CC		 2892 if (!data)
2893 goto err_alloc_ring;
b78cd169 2894 atmel_port->rx_ring.buf = data;
a6670615 2895 }
1ecc26bd 2896
b78cd169 2897 rs485_enabled = atmel_port->uart.rs485.flags & SER_RS485_ENABLED;
bd737f87 2898
b78cd169 2899 ret = uart_add_one_port(&atmel_uart, &atmel_port->uart);
dfa7f343
HS		 2900 if (ret)
2901 goto err_add_port;
2902
8da14b5f 2903#ifdef CONFIG_SERIAL_ATMEL_CONSOLE
207f6f34 2904 if (uart_console(&atmel_port->uart)
06a7f058
DB		 2905 && ATMEL_CONSOLE_DEVICE->flags & CON_ENABLED) {
2906 /*
2907 * The serial core enabled the clock for us, so undo
91f8c2d8 2908 * the clk_prepare_enable() in atmel_console_setup()
06a7f058 2909 */
b78cd169 2910 clk_disable_unprepare(atmel_port->clk);
06a7f058 2911 }
8da14b5f 2912#endif
06a7f058 2913
dfa7f343 2914 device_init_wakeup(&pdev->dev, 1);
b78cd169 2915 platform_set_drvdata(pdev, atmel_port);
dfa7f343 2916
d4f64187
CP		 2917 /*
2918 * The peripheral clock has been disabled by atmel_init_port():
2919 * enable it before accessing I/O registers
2920 */
b78cd169 2921 clk_prepare_enable(atmel_port->clk);
d4f64187 2922
bd737f87 2923 if (rs485_enabled) {
b78cd169 2924 atmel_uart_writel(&atmel_port->uart, ATMEL_US_MR,
4e7decda 2925 ATMEL_US_USMODE_NORMAL);
b78cd169
JA		 2926 atmel_uart_writel(&atmel_port->uart, ATMEL_US_CR,
2927 ATMEL_US_RTSEN);
5dfbd1d7
CS		 2928 }
2929
055560b0
ES		 2930 /*
2931 * Get port name of usart or uart
2932 */
b78cd169 2933 atmel_get_ip_name(&atmel_port->uart);
055560b0 2934
d4f64187
CP		 2935 /*
2936 * The peripheral clock can now safely be disabled till the port
2937 * is used
2938 */
b78cd169 2939 clk_disable_unprepare(atmel_port->clk);
d4f64187 2940
dfa7f343
HS		 2941 return 0;
2942
2943err_add_port:
b78cd169
JA		 2944 kfree(atmel_port->rx_ring.buf);
2945 atmel_port->rx_ring.buf = NULL;
1ecc26bd 2946err_alloc_ring:
207f6f34 2947 if (!uart_console(&atmel_port->uart)) {
b78cd169
JA		 2948 clk_put(atmel_port->clk);
2949 atmel_port->clk = NULL;
afefc415 2950 }
6fbb9bdf 2951err_clear_bit:
b78cd169 2952 clear_bit(atmel_port->uart.line, atmel_ports_in_use);
4cbf9f48 2953err:
afefc415
AV		 2954 return ret;
2955}
2956
f4a8ab04
RI		 2957/*
2958 * Even if the driver is not modular, it makes sense to be able to
2959 * unbind a device: there can be many bound devices, and there are
2960 * situations where dynamic binding and unbinding can be useful.
2961 *
2962 * For example, a connected device can require a specific firmware update
2963 * protocol that needs bitbanging on IO lines, but use the regular serial
2964 * port in the normal case.
2965 */
2966static int atmel_serial_remove(struct platform_device *pdev)
2967{
2968 struct uart_port *port = platform_get_drvdata(pdev);
2969 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2970 int ret = 0;
2971
00e8e658
NF		 2972 tasklet_kill(&atmel_port->tasklet_rx);
2973 tasklet_kill(&atmel_port->tasklet_tx);
f4a8ab04
RI		 2974
2975 device_init_wakeup(&pdev->dev, 0);
2976
2977 ret = uart_remove_one_port(&atmel_uart, port);
2978
2979 kfree(atmel_port->rx_ring.buf);
2980
2981 /* "port" is allocated statically, so we shouldn't free it */
2982
2983 clear_bit(port->line, atmel_ports_in_use);
2984
2985 clk_put(atmel_port->clk);
2986 atmel_port->clk = NULL;
c24d2531 2987 pdev->dev.of_node = NULL;
f4a8ab04
RI		 2988
2989 return ret;
2990}
2991
7192f92c
HS		 2992static struct platform_driver atmel_serial_driver = {
2993 .probe = atmel_serial_probe,
f4a8ab04 2994 .remove = atmel_serial_remove,
7192f92c
HS		 2995 .suspend = atmel_serial_suspend,
2996 .resume = atmel_serial_resume,
afefc415 2997 .driver = {
c24d2531 2998 .name = "atmel_usart_serial",
c39dfebc 2999 .of_match_table = of_match_ptr(atmel_serial_dt_ids),
afefc415
AV		 3000 },
3001};
3002
7192f92c 3003static int __init atmel_serial_init(void)
afefc415
AV		 3004{
3005 int ret;
3006
7192f92c 3007 ret = uart_register_driver(&atmel_uart);
afefc415
AV		 3008 if (ret)
3009 return ret;
3010
7192f92c 3011 ret = platform_driver_register(&atmel_serial_driver);
afefc415 3012 if (ret)
7192f92c 3013 uart_unregister_driver(&atmel_uart);
afefc415
AV		 3014
3015 return ret;
3016}
c39dfebc 3017device_initcall(atmel_serial_init);
Linux 6.x block layer and io_uring tree(s)