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e3b3d0f5 | 1 | // SPDX-License-Identifier: GPL-2.0 |
2ac4ad2a VG |
2 | /* |
3 | * ARC On-Chip(fpga) UART Driver | |
4 | * | |
5 | * Copyright (C) 2010-2012 Synopsys, Inc. (www.synopsys.com) | |
6 | * | |
2ac4ad2a VG |
7 | * vineetg: July 10th 2012 |
8 | * -Decoupled the driver from arch/arc | |
9 | * +Using platform_get_resource() for irq/membase (thx to bfin_uart.c) | |
10 | * +Using early_platform_xxx() for early console (thx to mach-shmobile/xxx) | |
11 | * | |
12 | * Vineetg: Aug 21st 2010 | |
13 | * -Is uart_tx_stopped() not done in tty write path as it has already been | |
14 | * taken care of, in serial core | |
15 | * | |
16 | * Vineetg: Aug 18th 2010 | |
17 | * -New Serial Core based ARC UART driver | |
18 | * -Derived largely from blackfin driver albiet with some major tweaks | |
19 | * | |
20 | * TODO: | |
21 | * -check if sysreq works | |
22 | */ | |
23 | ||
24 | #if defined(CONFIG_SERIAL_ARC_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) | |
25 | #define SUPPORT_SYSRQ | |
26 | #endif | |
27 | ||
28 | #include <linux/module.h> | |
29 | #include <linux/serial.h> | |
30 | #include <linux/console.h> | |
31 | #include <linux/sysrq.h> | |
32 | #include <linux/platform_device.h> | |
33 | #include <linux/tty.h> | |
34 | #include <linux/tty_flip.h> | |
35 | #include <linux/serial_core.h> | |
36 | #include <linux/io.h> | |
91f1b62a VG |
37 | #include <linux/of_irq.h> |
38 | #include <linux/of_address.h> | |
2ac4ad2a VG |
39 | |
40 | /************************************* | |
41 | * ARC UART Hardware Specs | |
42 | ************************************/ | |
43 | #define ARC_UART_TX_FIFO_SIZE 1 | |
44 | ||
45 | /* | |
46 | * UART Register set (this is not a Standards Compliant IP) | |
47 | * Also each reg is Word aligned, but only 8 bits wide | |
48 | */ | |
49 | #define R_ID0 0 | |
50 | #define R_ID1 4 | |
51 | #define R_ID2 8 | |
52 | #define R_ID3 12 | |
53 | #define R_DATA 16 | |
54 | #define R_STS 20 | |
55 | #define R_BAUDL 24 | |
56 | #define R_BAUDH 28 | |
57 | ||
58 | /* Bits for UART Status Reg (R/W) */ | |
59 | #define RXIENB 0x04 /* Receive Interrupt Enable */ | |
60 | #define TXIENB 0x40 /* Transmit Interrupt Enable */ | |
61 | ||
62 | #define RXEMPTY 0x20 /* Receive FIFO Empty: No char receivede */ | |
63 | #define TXEMPTY 0x80 /* Transmit FIFO Empty, thus char can be written into */ | |
64 | ||
65 | #define RXFULL 0x08 /* Receive FIFO full */ | |
66 | #define RXFULL1 0x10 /* Receive FIFO has space for 1 char (tot space=4) */ | |
67 | ||
68 | #define RXFERR 0x01 /* Frame Error: Stop Bit not detected */ | |
69 | #define RXOERR 0x02 /* OverFlow Err: Char recv but RXFULL still set */ | |
70 | ||
71 | /* Uart bit fiddling helpers: lowest level */ | |
12d15e6f | 72 | #define RBASE(port, reg) (port->membase + reg) |
2ac4ad2a VG |
73 | #define UART_REG_SET(u, r, v) writeb((v), RBASE(u, r)) |
74 | #define UART_REG_GET(u, r) readb(RBASE(u, r)) | |
75 | ||
76 | #define UART_REG_OR(u, r, v) UART_REG_SET(u, r, UART_REG_GET(u, r) | (v)) | |
77 | #define UART_REG_CLR(u, r, v) UART_REG_SET(u, r, UART_REG_GET(u, r) & ~(v)) | |
78 | ||
79 | /* Uart bit fiddling helpers: API level */ | |
80 | #define UART_SET_DATA(uart, val) UART_REG_SET(uart, R_DATA, val) | |
81 | #define UART_GET_DATA(uart) UART_REG_GET(uart, R_DATA) | |
82 | ||
83 | #define UART_SET_BAUDH(uart, val) UART_REG_SET(uart, R_BAUDH, val) | |
84 | #define UART_SET_BAUDL(uart, val) UART_REG_SET(uart, R_BAUDL, val) | |
85 | ||
86 | #define UART_CLR_STATUS(uart, val) UART_REG_CLR(uart, R_STS, val) | |
87 | #define UART_GET_STATUS(uart) UART_REG_GET(uart, R_STS) | |
88 | ||
89 | #define UART_ALL_IRQ_DISABLE(uart) UART_REG_CLR(uart, R_STS, RXIENB|TXIENB) | |
90 | #define UART_RX_IRQ_DISABLE(uart) UART_REG_CLR(uart, R_STS, RXIENB) | |
91 | #define UART_TX_IRQ_DISABLE(uart) UART_REG_CLR(uart, R_STS, TXIENB) | |
92 | ||
93 | #define UART_ALL_IRQ_ENABLE(uart) UART_REG_OR(uart, R_STS, RXIENB|TXIENB) | |
94 | #define UART_RX_IRQ_ENABLE(uart) UART_REG_OR(uart, R_STS, RXIENB) | |
95 | #define UART_TX_IRQ_ENABLE(uart) UART_REG_OR(uart, R_STS, TXIENB) | |
96 | ||
97 | #define ARC_SERIAL_DEV_NAME "ttyARC" | |
98 | ||
99 | struct arc_uart_port { | |
100 | struct uart_port port; | |
101 | unsigned long baud; | |
2ac4ad2a VG |
102 | }; |
103 | ||
104 | #define to_arc_port(uport) container_of(uport, struct arc_uart_port, port) | |
105 | ||
106 | static struct arc_uart_port arc_uart_ports[CONFIG_SERIAL_ARC_NR_PORTS]; | |
107 | ||
108 | #ifdef CONFIG_SERIAL_ARC_CONSOLE | |
109 | static struct console arc_console; | |
110 | #endif | |
111 | ||
112 | #define DRIVER_NAME "arc-uart" | |
113 | ||
114 | static struct uart_driver arc_uart_driver = { | |
115 | .owner = THIS_MODULE, | |
116 | .driver_name = DRIVER_NAME, | |
117 | .dev_name = ARC_SERIAL_DEV_NAME, | |
118 | .major = 0, | |
119 | .minor = 0, | |
120 | .nr = CONFIG_SERIAL_ARC_NR_PORTS, | |
121 | #ifdef CONFIG_SERIAL_ARC_CONSOLE | |
122 | .cons = &arc_console, | |
123 | #endif | |
124 | }; | |
125 | ||
126 | static void arc_serial_stop_rx(struct uart_port *port) | |
127 | { | |
12d15e6f | 128 | UART_RX_IRQ_DISABLE(port); |
2ac4ad2a VG |
129 | } |
130 | ||
131 | static void arc_serial_stop_tx(struct uart_port *port) | |
132 | { | |
12d15e6f | 133 | while (!(UART_GET_STATUS(port) & TXEMPTY)) |
2ac4ad2a VG |
134 | cpu_relax(); |
135 | ||
12d15e6f | 136 | UART_TX_IRQ_DISABLE(port); |
2ac4ad2a VG |
137 | } |
138 | ||
139 | /* | |
140 | * Return TIOCSER_TEMT when transmitter is not busy. | |
141 | */ | |
142 | static unsigned int arc_serial_tx_empty(struct uart_port *port) | |
143 | { | |
2ac4ad2a VG |
144 | unsigned int stat; |
145 | ||
12d15e6f | 146 | stat = UART_GET_STATUS(port); |
2ac4ad2a VG |
147 | if (stat & TXEMPTY) |
148 | return TIOCSER_TEMT; | |
149 | ||
150 | return 0; | |
151 | } | |
152 | ||
153 | /* | |
154 | * Driver internal routine, used by both tty(serial core) as well as tx-isr | |
155 | * -Called under spinlock in either cases | |
ee797069 | 156 | * -also tty->stopped has already been checked |
2ac4ad2a VG |
157 | * = by uart_start( ) before calling us |
158 | * = tx_ist checks that too before calling | |
159 | */ | |
12d15e6f | 160 | static void arc_serial_tx_chars(struct uart_port *port) |
2ac4ad2a | 161 | { |
12d15e6f | 162 | struct circ_buf *xmit = &port->state->xmit; |
2ac4ad2a VG |
163 | int sent = 0; |
164 | unsigned char ch; | |
165 | ||
12d15e6f VG |
166 | if (unlikely(port->x_char)) { |
167 | UART_SET_DATA(port, port->x_char); | |
168 | port->icount.tx++; | |
169 | port->x_char = 0; | |
2ac4ad2a | 170 | sent = 1; |
99ecb001 | 171 | } else if (!uart_circ_empty(xmit)) { |
2ac4ad2a VG |
172 | ch = xmit->buf[xmit->tail]; |
173 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); | |
12d15e6f VG |
174 | port->icount.tx++; |
175 | while (!(UART_GET_STATUS(port) & TXEMPTY)) | |
2ac4ad2a | 176 | cpu_relax(); |
12d15e6f | 177 | UART_SET_DATA(port, ch); |
2ac4ad2a VG |
178 | sent = 1; |
179 | } | |
180 | ||
181 | /* | |
182 | * If num chars in xmit buffer are too few, ask tty layer for more. | |
183 | * By Hard ISR to schedule processing in software interrupt part | |
184 | */ | |
185 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
12d15e6f | 186 | uart_write_wakeup(port); |
2ac4ad2a VG |
187 | |
188 | if (sent) | |
12d15e6f | 189 | UART_TX_IRQ_ENABLE(port); |
2ac4ad2a VG |
190 | } |
191 | ||
192 | /* | |
193 | * port is locked and interrupts are disabled | |
194 | * uart_start( ) calls us under the port spinlock irqsave | |
195 | */ | |
196 | static void arc_serial_start_tx(struct uart_port *port) | |
197 | { | |
12d15e6f | 198 | arc_serial_tx_chars(port); |
2ac4ad2a VG |
199 | } |
200 | ||
12d15e6f | 201 | static void arc_serial_rx_chars(struct uart_port *port, unsigned int status) |
2ac4ad2a | 202 | { |
5284eba7 | 203 | unsigned int ch, flg = 0; |
2ac4ad2a | 204 | |
2ac4ad2a VG |
205 | /* |
206 | * UART has 4 deep RX-FIFO. Driver's recongnition of this fact | |
207 | * is very subtle. Here's how ... | |
208 | * Upon getting a RX-Intr, such that RX-EMPTY=0, meaning data available, | |
209 | * driver reads the DATA Reg and keeps doing that in a loop, until | |
210 | * RX-EMPTY=1. Multiple chars being avail, with a single Interrupt, | |
211 | * before RX-EMPTY=0, implies some sort of buffering going on in the | |
212 | * controller, which is indeed the Rx-FIFO. | |
213 | */ | |
5284eba7 VG |
214 | do { |
215 | /* | |
216 | * This could be an Rx Intr for err (no data), | |
217 | * so check err and clear that Intr first | |
218 | */ | |
2ac4ad2a VG |
219 | if (unlikely(status & (RXOERR | RXFERR))) { |
220 | if (status & RXOERR) { | |
12d15e6f | 221 | port->icount.overrun++; |
2ac4ad2a | 222 | flg = TTY_OVERRUN; |
12d15e6f | 223 | UART_CLR_STATUS(port, RXOERR); |
2ac4ad2a VG |
224 | } |
225 | ||
226 | if (status & RXFERR) { | |
12d15e6f | 227 | port->icount.frame++; |
2ac4ad2a | 228 | flg = TTY_FRAME; |
12d15e6f | 229 | UART_CLR_STATUS(port, RXFERR); |
2ac4ad2a VG |
230 | } |
231 | } else | |
232 | flg = TTY_NORMAL; | |
233 | ||
5284eba7 VG |
234 | if (status & RXEMPTY) |
235 | continue; | |
236 | ||
12d15e6f VG |
237 | ch = UART_GET_DATA(port); |
238 | port->icount.rx++; | |
5284eba7 | 239 | |
12d15e6f VG |
240 | if (!(uart_handle_sysrq_char(port, ch))) |
241 | uart_insert_char(port, status, RXOERR, ch, flg); | |
2ac4ad2a | 242 | |
12d15e6f VG |
243 | spin_unlock(&port->lock); |
244 | tty_flip_buffer_push(&port->state->port); | |
245 | spin_lock(&port->lock); | |
246 | } while (!((status = UART_GET_STATUS(port)) & RXEMPTY)); | |
2ac4ad2a VG |
247 | } |
248 | ||
249 | /* | |
250 | * A note on the Interrupt handling state machine of this driver | |
251 | * | |
252 | * kernel printk writes funnel thru the console driver framework and in order | |
253 | * to keep things simple as well as efficient, it writes to UART in polled | |
254 | * mode, in one shot, and exits. | |
255 | * | |
256 | * OTOH, Userland output (via tty layer), uses interrupt based writes as there | |
257 | * can be undeterministic delay between char writes. | |
258 | * | |
259 | * Thus Rx-interrupts are always enabled, while tx-interrupts are by default | |
260 | * disabled. | |
261 | * | |
262 | * When tty has some data to send out, serial core calls driver's start_tx | |
263 | * which | |
264 | * -checks-if-tty-buffer-has-char-to-send | |
265 | * -writes-data-to-uart | |
266 | * -enable-tx-intr | |
267 | * | |
268 | * Once data bits are pushed out, controller raises the Tx-room-avail-Interrupt. | |
269 | * The first thing Tx ISR does is disable further Tx interrupts (as this could | |
270 | * be the last char to send, before settling down into the quiet polled mode). | |
271 | * It then calls the exact routine used by tty layer write to send out any | |
272 | * more char in tty buffer. In case of sending, it re-enables Tx-intr. In case | |
273 | * of no data, it remains disabled. | |
274 | * This is how the transmit state machine is dynamically switched on/off | |
275 | */ | |
276 | ||
277 | static irqreturn_t arc_serial_isr(int irq, void *dev_id) | |
278 | { | |
12d15e6f | 279 | struct uart_port *port = dev_id; |
2ac4ad2a VG |
280 | unsigned int status; |
281 | ||
12d15e6f | 282 | status = UART_GET_STATUS(port); |
2ac4ad2a VG |
283 | |
284 | /* | |
285 | * Single IRQ for both Rx (data available) Tx (room available) Interrupt | |
286 | * notifications from the UART Controller. | |
287 | * To demultiplex between the two, we check the relevant bits | |
288 | */ | |
5284eba7 | 289 | if (status & RXIENB) { |
2ac4ad2a VG |
290 | |
291 | /* already in ISR, no need of xx_irqsave */ | |
12d15e6f VG |
292 | spin_lock(&port->lock); |
293 | arc_serial_rx_chars(port, status); | |
294 | spin_unlock(&port->lock); | |
2ac4ad2a VG |
295 | } |
296 | ||
297 | if ((status & TXIENB) && (status & TXEMPTY)) { | |
298 | ||
299 | /* Unconditionally disable further Tx-Interrupts. | |
300 | * will be enabled by tx_chars() if needed. | |
301 | */ | |
12d15e6f | 302 | UART_TX_IRQ_DISABLE(port); |
2ac4ad2a | 303 | |
12d15e6f | 304 | spin_lock(&port->lock); |
2ac4ad2a | 305 | |
12d15e6f VG |
306 | if (!uart_tx_stopped(port)) |
307 | arc_serial_tx_chars(port); | |
2ac4ad2a | 308 | |
12d15e6f | 309 | spin_unlock(&port->lock); |
2ac4ad2a VG |
310 | } |
311 | ||
312 | return IRQ_HANDLED; | |
313 | } | |
314 | ||
315 | static unsigned int arc_serial_get_mctrl(struct uart_port *port) | |
316 | { | |
317 | /* | |
318 | * Pretend we have a Modem status reg and following bits are | |
319 | * always set, to satify the serial core state machine | |
320 | * (DSR) Data Set Ready | |
321 | * (CTS) Clear To Send | |
322 | * (CAR) Carrier Detect | |
323 | */ | |
324 | return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR; | |
325 | } | |
326 | ||
327 | static void arc_serial_set_mctrl(struct uart_port *port, unsigned int mctrl) | |
328 | { | |
329 | /* MCR not present */ | |
330 | } | |
331 | ||
2ac4ad2a VG |
332 | static void arc_serial_break_ctl(struct uart_port *port, int break_state) |
333 | { | |
334 | /* ARC UART doesn't support sending Break signal */ | |
335 | } | |
336 | ||
337 | static int arc_serial_startup(struct uart_port *port) | |
338 | { | |
2ac4ad2a | 339 | /* Before we hook up the ISR, Disable all UART Interrupts */ |
12d15e6f | 340 | UART_ALL_IRQ_DISABLE(port); |
2ac4ad2a | 341 | |
12d15e6f VG |
342 | if (request_irq(port->irq, arc_serial_isr, 0, "arc uart rx-tx", port)) { |
343 | dev_warn(port->dev, "Unable to attach ARC UART intr\n"); | |
2ac4ad2a VG |
344 | return -EBUSY; |
345 | } | |
346 | ||
12d15e6f | 347 | UART_RX_IRQ_ENABLE(port); /* Only Rx IRQ enabled to begin with */ |
2ac4ad2a VG |
348 | |
349 | return 0; | |
350 | } | |
351 | ||
352 | /* This is not really needed */ | |
353 | static void arc_serial_shutdown(struct uart_port *port) | |
354 | { | |
12d15e6f | 355 | free_irq(port->irq, port); |
2ac4ad2a VG |
356 | } |
357 | ||
358 | static void | |
359 | arc_serial_set_termios(struct uart_port *port, struct ktermios *new, | |
360 | struct ktermios *old) | |
361 | { | |
362 | struct arc_uart_port *uart = to_arc_port(port); | |
363 | unsigned int baud, uartl, uarth, hw_val; | |
364 | unsigned long flags; | |
365 | ||
366 | /* | |
367 | * Use the generic handler so that any specially encoded baud rates | |
368 | * such as SPD_xx flags or "%B0" can be handled | |
369 | * Max Baud I suppose will not be more than current 115K * 4 | |
370 | * Formula for ARC UART is: hw-val = ((CLK/(BAUD*4)) -1) | |
371 | * spread over two 8-bit registers | |
372 | */ | |
373 | baud = uart_get_baud_rate(port, new, old, 0, 460800); | |
374 | ||
375 | hw_val = port->uartclk / (uart->baud * 4) - 1; | |
376 | uartl = hw_val & 0xFF; | |
377 | uarth = (hw_val >> 8) & 0xFF; | |
378 | ||
2ac4ad2a VG |
379 | spin_lock_irqsave(&port->lock, flags); |
380 | ||
12d15e6f | 381 | UART_ALL_IRQ_DISABLE(port); |
2ac4ad2a | 382 | |
12d15e6f VG |
383 | UART_SET_BAUDL(port, uartl); |
384 | UART_SET_BAUDH(port, uarth); | |
2ac4ad2a | 385 | |
12d15e6f | 386 | UART_RX_IRQ_ENABLE(port); |
2ac4ad2a VG |
387 | |
388 | /* | |
389 | * UART doesn't support Parity/Hardware Flow Control; | |
390 | * Only supports 8N1 character size | |
391 | */ | |
392 | new->c_cflag &= ~(CMSPAR|CRTSCTS|CSIZE); | |
393 | new->c_cflag |= CS8; | |
394 | ||
395 | if (old) | |
396 | tty_termios_copy_hw(new, old); | |
397 | ||
398 | /* Don't rewrite B0 */ | |
399 | if (tty_termios_baud_rate(new)) | |
400 | tty_termios_encode_baud_rate(new, baud, baud); | |
401 | ||
402 | uart_update_timeout(port, new->c_cflag, baud); | |
403 | ||
404 | spin_unlock_irqrestore(&port->lock, flags); | |
405 | } | |
406 | ||
407 | static const char *arc_serial_type(struct uart_port *port) | |
408 | { | |
12d15e6f | 409 | return port->type == PORT_ARC ? DRIVER_NAME : NULL; |
2ac4ad2a VG |
410 | } |
411 | ||
412 | static void arc_serial_release_port(struct uart_port *port) | |
413 | { | |
414 | } | |
415 | ||
416 | static int arc_serial_request_port(struct uart_port *port) | |
417 | { | |
418 | return 0; | |
419 | } | |
420 | ||
421 | /* | |
422 | * Verify the new serial_struct (for TIOCSSERIAL). | |
423 | */ | |
424 | static int | |
425 | arc_serial_verify_port(struct uart_port *port, struct serial_struct *ser) | |
426 | { | |
427 | if (port->type != PORT_UNKNOWN && ser->type != PORT_ARC) | |
428 | return -EINVAL; | |
429 | ||
430 | return 0; | |
431 | } | |
432 | ||
433 | /* | |
434 | * Configure/autoconfigure the port. | |
435 | */ | |
436 | static void arc_serial_config_port(struct uart_port *port, int flags) | |
437 | { | |
2ac4ad2a | 438 | if (flags & UART_CONFIG_TYPE) |
12d15e6f | 439 | port->type = PORT_ARC; |
2ac4ad2a VG |
440 | } |
441 | ||
f363ca2f | 442 | #ifdef CONFIG_CONSOLE_POLL |
2ac4ad2a | 443 | |
f363ca2f | 444 | static void arc_serial_poll_putchar(struct uart_port *port, unsigned char chr) |
2ac4ad2a | 445 | { |
12d15e6f | 446 | while (!(UART_GET_STATUS(port) & TXEMPTY)) |
2ac4ad2a VG |
447 | cpu_relax(); |
448 | ||
f363ca2f | 449 | UART_SET_DATA(port, chr); |
2ac4ad2a | 450 | } |
2ac4ad2a | 451 | |
2ac4ad2a VG |
452 | static int arc_serial_poll_getchar(struct uart_port *port) |
453 | { | |
2ac4ad2a VG |
454 | unsigned char chr; |
455 | ||
12d15e6f | 456 | while (!(UART_GET_STATUS(port) & RXEMPTY)) |
2ac4ad2a VG |
457 | cpu_relax(); |
458 | ||
12d15e6f | 459 | chr = UART_GET_DATA(port); |
2ac4ad2a VG |
460 | return chr; |
461 | } | |
462 | #endif | |
463 | ||
8232884e | 464 | static const struct uart_ops arc_serial_pops = { |
2ac4ad2a VG |
465 | .tx_empty = arc_serial_tx_empty, |
466 | .set_mctrl = arc_serial_set_mctrl, | |
467 | .get_mctrl = arc_serial_get_mctrl, | |
468 | .stop_tx = arc_serial_stop_tx, | |
469 | .start_tx = arc_serial_start_tx, | |
470 | .stop_rx = arc_serial_stop_rx, | |
2ac4ad2a VG |
471 | .break_ctl = arc_serial_break_ctl, |
472 | .startup = arc_serial_startup, | |
473 | .shutdown = arc_serial_shutdown, | |
474 | .set_termios = arc_serial_set_termios, | |
475 | .type = arc_serial_type, | |
476 | .release_port = arc_serial_release_port, | |
477 | .request_port = arc_serial_request_port, | |
478 | .config_port = arc_serial_config_port, | |
479 | .verify_port = arc_serial_verify_port, | |
480 | #ifdef CONFIG_CONSOLE_POLL | |
481 | .poll_put_char = arc_serial_poll_putchar, | |
482 | .poll_get_char = arc_serial_poll_getchar, | |
483 | #endif | |
484 | }; | |
485 | ||
2ac4ad2a VG |
486 | #ifdef CONFIG_SERIAL_ARC_CONSOLE |
487 | ||
9671f099 | 488 | static int arc_serial_console_setup(struct console *co, char *options) |
2ac4ad2a VG |
489 | { |
490 | struct uart_port *port; | |
491 | int baud = 115200; | |
492 | int bits = 8; | |
493 | int parity = 'n'; | |
494 | int flow = 'n'; | |
495 | ||
496 | if (co->index < 0 || co->index >= CONFIG_SERIAL_ARC_NR_PORTS) | |
497 | return -ENODEV; | |
498 | ||
499 | /* | |
500 | * The uart port backing the console (e.g. ttyARC1) might not have been | |
501 | * init yet. If so, defer the console setup to after the port. | |
502 | */ | |
503 | port = &arc_uart_ports[co->index].port; | |
504 | if (!port->membase) | |
505 | return -ENODEV; | |
506 | ||
507 | if (options) | |
508 | uart_parse_options(options, &baud, &parity, &bits, &flow); | |
509 | ||
510 | /* | |
511 | * Serial core will call port->ops->set_termios( ) | |
512 | * which will set the baud reg | |
513 | */ | |
514 | return uart_set_options(port, co, baud, parity, bits, flow); | |
515 | } | |
516 | ||
f363ca2f VG |
517 | static void arc_serial_console_putchar(struct uart_port *port, int ch) |
518 | { | |
519 | while (!(UART_GET_STATUS(port) & TXEMPTY)) | |
520 | cpu_relax(); | |
521 | ||
522 | UART_SET_DATA(port, (unsigned char)ch); | |
523 | } | |
524 | ||
2ac4ad2a VG |
525 | /* |
526 | * Interrupts are disabled on entering | |
527 | */ | |
528 | static void arc_serial_console_write(struct console *co, const char *s, | |
529 | unsigned int count) | |
530 | { | |
531 | struct uart_port *port = &arc_uart_ports[co->index].port; | |
532 | unsigned long flags; | |
533 | ||
534 | spin_lock_irqsave(&port->lock, flags); | |
f363ca2f | 535 | uart_console_write(port, s, count, arc_serial_console_putchar); |
2ac4ad2a VG |
536 | spin_unlock_irqrestore(&port->lock, flags); |
537 | } | |
538 | ||
539 | static struct console arc_console = { | |
540 | .name = ARC_SERIAL_DEV_NAME, | |
541 | .write = arc_serial_console_write, | |
542 | .device = uart_console_device, | |
543 | .setup = arc_serial_console_setup, | |
544 | .flags = CON_PRINTBUFFER, | |
545 | .index = -1, | |
546 | .data = &arc_uart_driver | |
547 | }; | |
548 | ||
ac1e6965 JC |
549 | static void arc_early_serial_write(struct console *con, const char *s, |
550 | unsigned int n) | |
27cfe4ec VG |
551 | { |
552 | struct earlycon_device *dev = con->data; | |
553 | ||
f363ca2f | 554 | uart_console_write(&dev->port, s, n, arc_serial_console_putchar); |
27cfe4ec VG |
555 | } |
556 | ||
557 | static int __init arc_early_console_setup(struct earlycon_device *dev, | |
558 | const char *opt) | |
559 | { | |
560 | struct uart_port *port = &dev->port; | |
561 | unsigned int l, h, hw_val; | |
562 | ||
563 | if (!dev->port.membase) | |
564 | return -ENODEV; | |
565 | ||
566 | hw_val = port->uartclk / (dev->baud * 4) - 1; | |
567 | l = hw_val & 0xFF; | |
568 | h = (hw_val >> 8) & 0xFF; | |
569 | ||
570 | UART_SET_BAUDL(port, l); | |
571 | UART_SET_BAUDH(port, h); | |
572 | ||
573 | dev->con->write = arc_early_serial_write; | |
574 | return 0; | |
575 | } | |
8c6abf7a | 576 | OF_EARLYCON_DECLARE(arc_uart, "snps,arc-uart", arc_early_console_setup); |
27cfe4ec | 577 | |
2ac4ad2a VG |
578 | #endif /* CONFIG_SERIAL_ARC_CONSOLE */ |
579 | ||
9671f099 | 580 | static int arc_serial_probe(struct platform_device *pdev) |
2ac4ad2a | 581 | { |
ea28fd56 | 582 | struct device_node *np = pdev->dev.of_node; |
8dbe1d5e VG |
583 | struct arc_uart_port *uart; |
584 | struct uart_port *port; | |
585 | int dev_id; | |
586 | u32 val; | |
ea28fd56 VG |
587 | |
588 | /* no device tree device */ | |
589 | if (!np) | |
590 | return -ENODEV; | |
591 | ||
592 | dev_id = of_alias_get_id(np, "serial"); | |
11c62d4f VG |
593 | if (dev_id < 0) |
594 | dev_id = 0; | |
2ac4ad2a | 595 | |
f9f57869 GU |
596 | if (dev_id >= ARRAY_SIZE(arc_uart_ports)) { |
597 | dev_err(&pdev->dev, "serial%d out of range\n", dev_id); | |
598 | return -EINVAL; | |
599 | } | |
600 | ||
8dbe1d5e VG |
601 | uart = &arc_uart_ports[dev_id]; |
602 | port = &uart->port; | |
603 | ||
604 | if (of_property_read_u32(np, "clock-frequency", &val)) { | |
605 | dev_err(&pdev->dev, "clock-frequency property NOTset\n"); | |
606 | return -EINVAL; | |
607 | } | |
608 | port->uartclk = val; | |
609 | ||
610 | if (of_property_read_u32(np, "current-speed", &val)) { | |
611 | dev_err(&pdev->dev, "current-speed property NOT set\n"); | |
612 | return -EINVAL; | |
613 | } | |
614 | uart->baud = val; | |
615 | ||
616 | port->membase = of_iomap(np, 0); | |
617 | if (!port->membase) | |
618 | /* No point of dev_err since UART itself is hosed here */ | |
619 | return -ENXIO; | |
620 | ||
621 | port->irq = irq_of_parse_and_map(np, 0); | |
622 | ||
623 | port->dev = &pdev->dev; | |
624 | port->iotype = UPIO_MEM; | |
625 | port->flags = UPF_BOOT_AUTOCONF; | |
626 | port->line = dev_id; | |
627 | port->ops = &arc_serial_pops; | |
628 | ||
629 | port->fifosize = ARC_UART_TX_FIFO_SIZE; | |
630 | ||
631 | /* | |
632 | * uart_insert_char( ) uses it in decideding whether to ignore a | |
633 | * char or not. Explicitly setting it here, removes the subtelty | |
634 | */ | |
635 | port->ignore_status_mask = 0; | |
2ac4ad2a | 636 | |
8dbe1d5e | 637 | return uart_add_one_port(&arc_uart_driver, &arc_uart_ports[dev_id].port); |
2ac4ad2a VG |
638 | } |
639 | ||
ae8d8a14 | 640 | static int arc_serial_remove(struct platform_device *pdev) |
2ac4ad2a VG |
641 | { |
642 | /* This will never be called */ | |
643 | return 0; | |
644 | } | |
645 | ||
ea28fd56 VG |
646 | static const struct of_device_id arc_uart_dt_ids[] = { |
647 | { .compatible = "snps,arc-uart" }, | |
648 | { /* Sentinel */ } | |
649 | }; | |
650 | MODULE_DEVICE_TABLE(of, arc_uart_dt_ids); | |
651 | ||
2ac4ad2a VG |
652 | static struct platform_driver arc_platform_driver = { |
653 | .probe = arc_serial_probe, | |
2d47b716 | 654 | .remove = arc_serial_remove, |
2ac4ad2a VG |
655 | .driver = { |
656 | .name = DRIVER_NAME, | |
ea28fd56 | 657 | .of_match_table = arc_uart_dt_ids, |
2ac4ad2a VG |
658 | }, |
659 | }; | |
660 | ||
2ac4ad2a VG |
661 | static int __init arc_serial_init(void) |
662 | { | |
663 | int ret; | |
664 | ||
665 | ret = uart_register_driver(&arc_uart_driver); | |
666 | if (ret) | |
667 | return ret; | |
668 | ||
669 | ret = platform_driver_register(&arc_platform_driver); | |
670 | if (ret) | |
671 | uart_unregister_driver(&arc_uart_driver); | |
672 | ||
673 | return ret; | |
674 | } | |
675 | ||
676 | static void __exit arc_serial_exit(void) | |
677 | { | |
678 | platform_driver_unregister(&arc_platform_driver); | |
679 | uart_unregister_driver(&arc_uart_driver); | |
680 | } | |
681 | ||
682 | module_init(arc_serial_init); | |
683 | module_exit(arc_serial_exit); | |
684 | ||
685 | MODULE_LICENSE("GPL"); | |
d5a12ea7 | 686 | MODULE_ALIAS("platform:" DRIVER_NAME); |
2ac4ad2a VG |
687 | MODULE_AUTHOR("Vineet Gupta"); |
688 | MODULE_DESCRIPTION("ARC(Synopsys) On-Chip(fpga) serial driver"); |