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e3b3d0f5 | 1 | // SPDX-License-Identifier: GPL-2.0+ |
1da177e4 | 2 | /* |
1da177e4 LT |
3 | * Driver for AMBA serial ports |
4 | * | |
5 | * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. | |
6 | * | |
7 | * Copyright 1999 ARM Limited | |
8 | * Copyright (C) 2000 Deep Blue Solutions Ltd. | |
68b65f73 | 9 | * Copyright (C) 2010 ST-Ericsson SA |
1da177e4 | 10 | * |
1da177e4 LT |
11 | * This is a generic driver for ARM AMBA-type serial ports. They |
12 | * have a lot of 16550-like features, but are not register compatible. | |
13 | * Note that although they do have CTS, DCD and DSR inputs, they do | |
14 | * not have an RI input, nor do they have DTR or RTS outputs. If | |
15 | * required, these have to be supplied via some other means (eg, GPIO) | |
16 | * and hooked into this driver. | |
17 | */ | |
1da177e4 | 18 | |
1da177e4 LT |
19 | #include <linux/module.h> |
20 | #include <linux/ioport.h> | |
21 | #include <linux/init.h> | |
22 | #include <linux/console.h> | |
29e5c442 | 23 | #include <linux/platform_device.h> |
1da177e4 LT |
24 | #include <linux/sysrq.h> |
25 | #include <linux/device.h> | |
26 | #include <linux/tty.h> | |
27 | #include <linux/tty_flip.h> | |
28 | #include <linux/serial_core.h> | |
29 | #include <linux/serial.h> | |
a62c80e5 RK |
30 | #include <linux/amba/bus.h> |
31 | #include <linux/amba/serial.h> | |
f8ce2547 | 32 | #include <linux/clk.h> |
5a0e3ad6 | 33 | #include <linux/slab.h> |
68b65f73 RK |
34 | #include <linux/dmaengine.h> |
35 | #include <linux/dma-mapping.h> | |
36 | #include <linux/scatterlist.h> | |
c16d51a3 | 37 | #include <linux/delay.h> |
258aea76 | 38 | #include <linux/types.h> |
32614aad | 39 | #include <linux/of.h> |
258e0551 | 40 | #include <linux/pinctrl/consumer.h> |
cb70706c | 41 | #include <linux/sizes.h> |
de609582 | 42 | #include <linux/io.h> |
3db9ab0b | 43 | #include <linux/acpi.h> |
1da177e4 LT |
44 | |
45 | #define UART_NR 14 | |
46 | ||
47 | #define SERIAL_AMBA_MAJOR 204 | |
48 | #define SERIAL_AMBA_MINOR 64 | |
49 | #define SERIAL_AMBA_NR UART_NR | |
50 | ||
51 | #define AMBA_ISR_PASS_LIMIT 256 | |
52 | ||
d93ebe0f | 53 | #define UART_DR_ERROR (UART011_DR_OE | UART011_DR_BE | UART011_DR_PE | UART011_DR_FE) |
826bd77a | 54 | #define UART_DUMMY_DR_RX BIT(16) |
1da177e4 | 55 | |
9bb13b2f JS |
56 | enum { |
57 | REG_DR, | |
58 | REG_ST_DMAWM, | |
59 | REG_ST_TIMEOUT, | |
60 | REG_FR, | |
61 | REG_LCRH_RX, | |
62 | REG_LCRH_TX, | |
63 | REG_IBRD, | |
64 | REG_FBRD, | |
65 | REG_CR, | |
66 | REG_IFLS, | |
67 | REG_IMSC, | |
68 | REG_RIS, | |
69 | REG_MIS, | |
70 | REG_ICR, | |
71 | REG_DMACR, | |
72 | REG_ST_XFCR, | |
73 | REG_ST_XON1, | |
74 | REG_ST_XON2, | |
75 | REG_ST_XOFF1, | |
76 | REG_ST_XOFF2, | |
77 | REG_ST_ITCR, | |
78 | REG_ST_ITIP, | |
79 | REG_ST_ABCR, | |
80 | REG_ST_ABIMSC, | |
81 | ||
82 | /* The size of the array - must be last */ | |
83 | REG_ARRAY_SIZE, | |
84 | }; | |
85 | ||
debb7f64 RK |
86 | static u16 pl011_std_offsets[REG_ARRAY_SIZE] = { |
87 | [REG_DR] = UART01x_DR, | |
debb7f64 | 88 | [REG_FR] = UART01x_FR, |
e4df9a80 RK |
89 | [REG_LCRH_RX] = UART011_LCRH, |
90 | [REG_LCRH_TX] = UART011_LCRH, | |
debb7f64 RK |
91 | [REG_IBRD] = UART011_IBRD, |
92 | [REG_FBRD] = UART011_FBRD, | |
debb7f64 RK |
93 | [REG_CR] = UART011_CR, |
94 | [REG_IFLS] = UART011_IFLS, | |
95 | [REG_IMSC] = UART011_IMSC, | |
96 | [REG_RIS] = UART011_RIS, | |
97 | [REG_MIS] = UART011_MIS, | |
98 | [REG_ICR] = UART011_ICR, | |
99 | [REG_DMACR] = UART011_DMACR, | |
debb7f64 RK |
100 | }; |
101 | ||
5926a295 AR |
102 | /* There is by now at least one vendor with differing details, so handle it */ |
103 | struct vendor_data { | |
439403bd | 104 | const u16 *reg_offset; |
5926a295 | 105 | unsigned int ifls; |
0e125a5f SG |
106 | unsigned int fr_busy; |
107 | unsigned int fr_dsr; | |
108 | unsigned int fr_cts; | |
109 | unsigned int fr_ri; | |
d8a4995b | 110 | unsigned int inv_fr; |
84c3e03b | 111 | bool access_32b; |
ac3e3fb4 | 112 | bool oversampling; |
38d62436 | 113 | bool dma_threshold; |
4fd0690b | 114 | bool cts_event_workaround; |
71eec483 | 115 | bool always_enabled; |
cefc2d1d | 116 | bool fixed_options; |
78506f22 | 117 | |
ea33640a | 118 | unsigned int (*get_fifosize)(struct amba_device *dev); |
5926a295 AR |
119 | }; |
120 | ||
ea33640a | 121 | static unsigned int get_fifosize_arm(struct amba_device *dev) |
78506f22 | 122 | { |
ea33640a | 123 | return amba_rev(dev) < 3 ? 16 : 32; |
78506f22 JK |
124 | } |
125 | ||
5926a295 | 126 | static struct vendor_data vendor_arm = { |
439403bd | 127 | .reg_offset = pl011_std_offsets, |
d93ebe0f | 128 | .ifls = UART011_IFLS_RX4_8 | UART011_IFLS_TX4_8, |
0e125a5f SG |
129 | .fr_busy = UART01x_FR_BUSY, |
130 | .fr_dsr = UART01x_FR_DSR, | |
131 | .fr_cts = UART01x_FR_CTS, | |
132 | .fr_ri = UART011_FR_RI, | |
ac3e3fb4 | 133 | .oversampling = false, |
38d62436 | 134 | .dma_threshold = false, |
4fd0690b | 135 | .cts_event_workaround = false, |
71eec483 | 136 | .always_enabled = false, |
cefc2d1d | 137 | .fixed_options = false, |
78506f22 | 138 | .get_fifosize = get_fifosize_arm, |
5926a295 AR |
139 | }; |
140 | ||
d054b3ac | 141 | static const struct vendor_data vendor_sbsa = { |
439403bd | 142 | .reg_offset = pl011_std_offsets, |
0e125a5f SG |
143 | .fr_busy = UART01x_FR_BUSY, |
144 | .fr_dsr = UART01x_FR_DSR, | |
145 | .fr_cts = UART01x_FR_CTS, | |
146 | .fr_ri = UART011_FR_RI, | |
1aabf523 | 147 | .access_32b = true, |
0dd1e247 AP |
148 | .oversampling = false, |
149 | .dma_threshold = false, | |
150 | .cts_event_workaround = false, | |
151 | .always_enabled = true, | |
152 | .fixed_options = true, | |
153 | }; | |
154 | ||
37ef38f3 | 155 | #ifdef CONFIG_ACPI_SPCR_TABLE |
d054b3ac | 156 | static const struct vendor_data vendor_qdt_qdf2400_e44 = { |
d8a4995b CC |
157 | .reg_offset = pl011_std_offsets, |
158 | .fr_busy = UART011_FR_TXFE, | |
159 | .fr_dsr = UART01x_FR_DSR, | |
160 | .fr_cts = UART01x_FR_CTS, | |
161 | .fr_ri = UART011_FR_RI, | |
162 | .inv_fr = UART011_FR_TXFE, | |
163 | .access_32b = true, | |
164 | .oversampling = false, | |
165 | .dma_threshold = false, | |
166 | .cts_event_workaround = false, | |
167 | .always_enabled = true, | |
168 | .fixed_options = true, | |
169 | }; | |
37ef38f3 | 170 | #endif |
d8a4995b | 171 | |
bf69ff8a RK |
172 | static u16 pl011_st_offsets[REG_ARRAY_SIZE] = { |
173 | [REG_DR] = UART01x_DR, | |
174 | [REG_ST_DMAWM] = ST_UART011_DMAWM, | |
175 | [REG_ST_TIMEOUT] = ST_UART011_TIMEOUT, | |
176 | [REG_FR] = UART01x_FR, | |
e4df9a80 RK |
177 | [REG_LCRH_RX] = ST_UART011_LCRH_RX, |
178 | [REG_LCRH_TX] = ST_UART011_LCRH_TX, | |
bf69ff8a RK |
179 | [REG_IBRD] = UART011_IBRD, |
180 | [REG_FBRD] = UART011_FBRD, | |
bf69ff8a RK |
181 | [REG_CR] = UART011_CR, |
182 | [REG_IFLS] = UART011_IFLS, | |
183 | [REG_IMSC] = UART011_IMSC, | |
184 | [REG_RIS] = UART011_RIS, | |
185 | [REG_MIS] = UART011_MIS, | |
186 | [REG_ICR] = UART011_ICR, | |
187 | [REG_DMACR] = UART011_DMACR, | |
188 | [REG_ST_XFCR] = ST_UART011_XFCR, | |
189 | [REG_ST_XON1] = ST_UART011_XON1, | |
190 | [REG_ST_XON2] = ST_UART011_XON2, | |
191 | [REG_ST_XOFF1] = ST_UART011_XOFF1, | |
192 | [REG_ST_XOFF2] = ST_UART011_XOFF2, | |
193 | [REG_ST_ITCR] = ST_UART011_ITCR, | |
194 | [REG_ST_ITIP] = ST_UART011_ITIP, | |
195 | [REG_ST_ABCR] = ST_UART011_ABCR, | |
196 | [REG_ST_ABIMSC] = ST_UART011_ABIMSC, | |
197 | }; | |
198 | ||
ea33640a | 199 | static unsigned int get_fifosize_st(struct amba_device *dev) |
78506f22 JK |
200 | { |
201 | return 64; | |
202 | } | |
203 | ||
5926a295 | 204 | static struct vendor_data vendor_st = { |
bf69ff8a | 205 | .reg_offset = pl011_st_offsets, |
d93ebe0f | 206 | .ifls = UART011_IFLS_RX_HALF | UART011_IFLS_TX_HALF, |
0e125a5f SG |
207 | .fr_busy = UART01x_FR_BUSY, |
208 | .fr_dsr = UART01x_FR_DSR, | |
209 | .fr_cts = UART01x_FR_CTS, | |
210 | .fr_ri = UART011_FR_RI, | |
ac3e3fb4 | 211 | .oversampling = true, |
38d62436 | 212 | .dma_threshold = true, |
4fd0690b | 213 | .cts_event_workaround = true, |
71eec483 | 214 | .always_enabled = false, |
cefc2d1d | 215 | .fixed_options = false, |
78506f22 | 216 | .get_fifosize = get_fifosize_st, |
1da177e4 LT |
217 | }; |
218 | ||
68b65f73 | 219 | /* Deals with DMA transactions */ |
ead76f32 | 220 | |
58ac1b37 AB |
221 | struct pl011_dmabuf { |
222 | dma_addr_t dma; | |
223 | size_t len; | |
224 | char *buf; | |
ead76f32 LW |
225 | }; |
226 | ||
227 | struct pl011_dmarx_data { | |
228 | struct dma_chan *chan; | |
229 | struct completion complete; | |
230 | bool use_buf_b; | |
58ac1b37 AB |
231 | struct pl011_dmabuf dbuf_a; |
232 | struct pl011_dmabuf dbuf_b; | |
ead76f32 LW |
233 | dma_cookie_t cookie; |
234 | bool running; | |
cb06ff10 CM |
235 | struct timer_list timer; |
236 | unsigned int last_residue; | |
237 | unsigned long last_jiffies; | |
238 | bool auto_poll_rate; | |
239 | unsigned int poll_rate; | |
240 | unsigned int poll_timeout; | |
ead76f32 LW |
241 | }; |
242 | ||
68b65f73 RK |
243 | struct pl011_dmatx_data { |
244 | struct dma_chan *chan; | |
58ac1b37 AB |
245 | dma_addr_t dma; |
246 | size_t len; | |
68b65f73 RK |
247 | char *buf; |
248 | bool queued; | |
249 | }; | |
250 | ||
c19f12b5 RK |
251 | /* |
252 | * We wrap our port structure around the generic uart_port. | |
253 | */ | |
254 | struct uart_amba_port { | |
255 | struct uart_port port; | |
debb7f64 | 256 | const u16 *reg_offset; |
c19f12b5 RK |
257 | struct clk *clk; |
258 | const struct vendor_data *vendor; | |
68b65f73 | 259 | unsigned int dmacr; /* dma control reg */ |
c19f12b5 RK |
260 | unsigned int im; /* interrupt mask */ |
261 | unsigned int old_status; | |
ffca2b11 | 262 | unsigned int fifosize; /* vendor-specific */ |
cefc2d1d | 263 | unsigned int fixed_baud; /* vendor-set fixed baud rate */ |
c19f12b5 | 264 | char type[12]; |
8d479237 LS |
265 | bool rs485_tx_started; |
266 | unsigned int rs485_tx_drain_interval; /* usecs */ | |
68b65f73 RK |
267 | #ifdef CONFIG_DMA_ENGINE |
268 | /* DMA stuff */ | |
ead76f32 LW |
269 | bool using_tx_dma; |
270 | bool using_rx_dma; | |
271 | struct pl011_dmarx_data dmarx; | |
68b65f73 | 272 | struct pl011_dmatx_data dmatx; |
1c9be310 | 273 | bool dma_probed; |
68b65f73 RK |
274 | #endif |
275 | }; | |
276 | ||
8d479237 LS |
277 | static unsigned int pl011_tx_empty(struct uart_port *port); |
278 | ||
9f25bc51 | 279 | static unsigned int pl011_reg_to_offset(const struct uart_amba_port *uap, |
d93ebe0f | 280 | unsigned int reg) |
9f25bc51 | 281 | { |
debb7f64 | 282 | return uap->reg_offset[reg]; |
9f25bc51 RK |
283 | } |
284 | ||
b2a4e24c | 285 | static unsigned int pl011_read(const struct uart_amba_port *uap, |
d93ebe0f | 286 | unsigned int reg) |
75836339 | 287 | { |
84c3e03b RK |
288 | void __iomem *addr = uap->port.membase + pl011_reg_to_offset(uap, reg); |
289 | ||
3b78fae7 TT |
290 | return (uap->port.iotype == UPIO_MEM32) ? |
291 | readl_relaxed(addr) : readw_relaxed(addr); | |
75836339 RK |
292 | } |
293 | ||
b2a4e24c | 294 | static void pl011_write(unsigned int val, const struct uart_amba_port *uap, |
d93ebe0f | 295 | unsigned int reg) |
75836339 | 296 | { |
84c3e03b RK |
297 | void __iomem *addr = uap->port.membase + pl011_reg_to_offset(uap, reg); |
298 | ||
3b78fae7 | 299 | if (uap->port.iotype == UPIO_MEM32) |
f5ce6edd | 300 | writel_relaxed(val, addr); |
84c3e03b | 301 | else |
f5ce6edd | 302 | writew_relaxed(val, addr); |
75836339 RK |
303 | } |
304 | ||
29772c4e LW |
305 | /* |
306 | * Reads up to 256 characters from the FIFO or until it's empty and | |
307 | * inserts them into the TTY layer. Returns the number of characters | |
308 | * read from the FIFO. | |
309 | */ | |
310 | static int pl011_fifo_to_tty(struct uart_amba_port *uap) | |
311 | { | |
fd2b55f8 | 312 | unsigned int ch, fifotaken; |
534cf755 PZ |
313 | int sysrq; |
314 | u16 status; | |
fd2b55f8 | 315 | u8 flag; |
29772c4e | 316 | |
e73be92d | 317 | for (fifotaken = 0; fifotaken != 256; fifotaken++) { |
9f25bc51 | 318 | status = pl011_read(uap, REG_FR); |
29772c4e LW |
319 | if (status & UART01x_FR_RXFE) |
320 | break; | |
321 | ||
322 | /* Take chars from the FIFO and update status */ | |
9f25bc51 | 323 | ch = pl011_read(uap, REG_DR) | UART_DUMMY_DR_RX; |
29772c4e LW |
324 | flag = TTY_NORMAL; |
325 | uap->port.icount.rx++; | |
29772c4e LW |
326 | |
327 | if (unlikely(ch & UART_DR_ERROR)) { | |
328 | if (ch & UART011_DR_BE) { | |
329 | ch &= ~(UART011_DR_FE | UART011_DR_PE); | |
330 | uap->port.icount.brk++; | |
331 | if (uart_handle_break(&uap->port)) | |
332 | continue; | |
28a7ec8c | 333 | } else if (ch & UART011_DR_PE) { |
29772c4e | 334 | uap->port.icount.parity++; |
28a7ec8c | 335 | } else if (ch & UART011_DR_FE) { |
29772c4e | 336 | uap->port.icount.frame++; |
28a7ec8c | 337 | } |
29772c4e LW |
338 | if (ch & UART011_DR_OE) |
339 | uap->port.icount.overrun++; | |
340 | ||
341 | ch &= uap->port.read_status_mask; | |
342 | ||
343 | if (ch & UART011_DR_BE) | |
344 | flag = TTY_BREAK; | |
345 | else if (ch & UART011_DR_PE) | |
346 | flag = TTY_PARITY; | |
347 | else if (ch & UART011_DR_FE) | |
348 | flag = TTY_FRAME; | |
349 | } | |
350 | ||
68ca3e72 | 351 | uart_port_unlock(&uap->port); |
534cf755 | 352 | sysrq = uart_handle_sysrq_char(&uap->port, ch & 255); |
68ca3e72 | 353 | uart_port_lock(&uap->port); |
29772c4e | 354 | |
534cf755 PZ |
355 | if (!sysrq) |
356 | uart_insert_char(&uap->port, ch, UART011_DR_OE, ch, flag); | |
29772c4e LW |
357 | } |
358 | ||
359 | return fifotaken; | |
360 | } | |
361 | ||
68b65f73 RK |
362 | /* |
363 | * All the DMA operation mode stuff goes inside this ifdef. | |
364 | * This assumes that you have a generic DMA device interface, | |
365 | * no custom DMA interfaces are supported. | |
366 | */ | |
367 | #ifdef CONFIG_DMA_ENGINE | |
368 | ||
369 | #define PL011_DMA_BUFFER_SIZE PAGE_SIZE | |
370 | ||
58ac1b37 | 371 | static int pl011_dmabuf_init(struct dma_chan *chan, struct pl011_dmabuf *db, |
d93ebe0f | 372 | enum dma_data_direction dir) |
ead76f32 | 373 | { |
58ac1b37 AB |
374 | db->buf = dma_alloc_coherent(chan->device->dev, PL011_DMA_BUFFER_SIZE, |
375 | &db->dma, GFP_KERNEL); | |
376 | if (!db->buf) | |
ead76f32 | 377 | return -ENOMEM; |
58ac1b37 | 378 | db->len = PL011_DMA_BUFFER_SIZE; |
ead76f32 | 379 | |
ead76f32 LW |
380 | return 0; |
381 | } | |
382 | ||
58ac1b37 | 383 | static void pl011_dmabuf_free(struct dma_chan *chan, struct pl011_dmabuf *db, |
d93ebe0f | 384 | enum dma_data_direction dir) |
ead76f32 | 385 | { |
58ac1b37 | 386 | if (db->buf) { |
cb06ff10 | 387 | dma_free_coherent(chan->device->dev, |
58ac1b37 | 388 | PL011_DMA_BUFFER_SIZE, db->buf, db->dma); |
ead76f32 LW |
389 | } |
390 | } | |
391 | ||
1c9be310 | 392 | static void pl011_dma_probe(struct uart_amba_port *uap) |
68b65f73 RK |
393 | { |
394 | /* DMA is the sole user of the platform data right now */ | |
574de559 | 395 | struct amba_pl011_data *plat = dev_get_platdata(uap->port.dev); |
1c9be310 | 396 | struct device *dev = uap->port.dev; |
68b65f73 | 397 | struct dma_slave_config tx_conf = { |
9f25bc51 RK |
398 | .dst_addr = uap->port.mapbase + |
399 | pl011_reg_to_offset(uap, REG_DR), | |
68b65f73 | 400 | .dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE, |
a485df4b | 401 | .direction = DMA_MEM_TO_DEV, |
68b65f73 | 402 | .dst_maxburst = uap->fifosize >> 1, |
258aea76 | 403 | .device_fc = false, |
68b65f73 RK |
404 | }; |
405 | struct dma_chan *chan; | |
406 | dma_cap_mask_t mask; | |
407 | ||
1c9be310 | 408 | uap->dma_probed = true; |
61b37b04 | 409 | chan = dma_request_chan(dev, "tx"); |
1c9be310 JRO |
410 | if (IS_ERR(chan)) { |
411 | if (PTR_ERR(chan) == -EPROBE_DEFER) { | |
1c9be310 JRO |
412 | uap->dma_probed = false; |
413 | return; | |
414 | } | |
68b65f73 | 415 | |
787b0c1f AB |
416 | /* We need platform data */ |
417 | if (!plat || !plat->dma_filter) { | |
6905ab83 | 418 | dev_dbg(uap->port.dev, "no DMA platform data\n"); |
787b0c1f AB |
419 | return; |
420 | } | |
421 | ||
422 | /* Try to acquire a generic DMA engine slave TX channel */ | |
423 | dma_cap_zero(mask); | |
424 | dma_cap_set(DMA_SLAVE, mask); | |
425 | ||
426 | chan = dma_request_channel(mask, plat->dma_filter, | |
d93ebe0f | 427 | plat->dma_tx_param); |
787b0c1f AB |
428 | if (!chan) { |
429 | dev_err(uap->port.dev, "no TX DMA channel!\n"); | |
430 | return; | |
431 | } | |
68b65f73 RK |
432 | } |
433 | ||
434 | dmaengine_slave_config(chan, &tx_conf); | |
435 | uap->dmatx.chan = chan; | |
436 | ||
437 | dev_info(uap->port.dev, "DMA channel TX %s\n", | |
438 | dma_chan_name(uap->dmatx.chan)); | |
ead76f32 LW |
439 | |
440 | /* Optionally make use of an RX channel as well */ | |
e6cc3948 | 441 | chan = dma_request_chan(dev, "rx"); |
0d3c673e | 442 | |
e6cc3948 | 443 | if (IS_ERR(chan) && plat && plat->dma_rx_param) { |
787b0c1f AB |
444 | chan = dma_request_channel(mask, plat->dma_filter, plat->dma_rx_param); |
445 | ||
446 | if (!chan) { | |
447 | dev_err(uap->port.dev, "no RX DMA channel!\n"); | |
448 | return; | |
449 | } | |
450 | } | |
451 | ||
e6cc3948 | 452 | if (!IS_ERR(chan)) { |
ead76f32 | 453 | struct dma_slave_config rx_conf = { |
9f25bc51 RK |
454 | .src_addr = uap->port.mapbase + |
455 | pl011_reg_to_offset(uap, REG_DR), | |
ead76f32 | 456 | .src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE, |
a485df4b | 457 | .direction = DMA_DEV_TO_MEM, |
b2aeb775 | 458 | .src_maxburst = uap->fifosize >> 2, |
258aea76 | 459 | .device_fc = false, |
ead76f32 | 460 | }; |
2d3b7d6e AJ |
461 | struct dma_slave_caps caps; |
462 | ||
463 | /* | |
464 | * Some DMA controllers provide information on their capabilities. | |
465 | * If the controller does, check for suitable residue processing | |
466 | * otherwise assime all is well. | |
467 | */ | |
28a7ec8c | 468 | if (dma_get_slave_caps(chan, &caps) == 0) { |
2d3b7d6e AJ |
469 | if (caps.residue_granularity == |
470 | DMA_RESIDUE_GRANULARITY_DESCRIPTOR) { | |
471 | dma_release_channel(chan); | |
472 | dev_info(uap->port.dev, | |
d93ebe0f | 473 | "RX DMA disabled - no residue processing\n"); |
2d3b7d6e AJ |
474 | return; |
475 | } | |
476 | } | |
ead76f32 LW |
477 | dmaengine_slave_config(chan, &rx_conf); |
478 | uap->dmarx.chan = chan; | |
479 | ||
98267d33 | 480 | uap->dmarx.auto_poll_rate = false; |
8f898bfd | 481 | if (plat && plat->dma_rx_poll_enable) { |
cb06ff10 CM |
482 | /* Set poll rate if specified. */ |
483 | if (plat->dma_rx_poll_rate) { | |
484 | uap->dmarx.auto_poll_rate = false; | |
485 | uap->dmarx.poll_rate = plat->dma_rx_poll_rate; | |
486 | } else { | |
487 | /* | |
488 | * 100 ms defaults to poll rate if not | |
489 | * specified. This will be adjusted with | |
490 | * the baud rate at set_termios. | |
491 | */ | |
492 | uap->dmarx.auto_poll_rate = true; | |
493 | uap->dmarx.poll_rate = 100; | |
494 | } | |
495 | /* 3 secs defaults poll_timeout if not specified. */ | |
496 | if (plat->dma_rx_poll_timeout) | |
497 | uap->dmarx.poll_timeout = | |
498 | plat->dma_rx_poll_timeout; | |
499 | else | |
500 | uap->dmarx.poll_timeout = 3000; | |
98267d33 | 501 | } else if (!plat && dev->of_node) { |
d93ebe0f TL |
502 | uap->dmarx.auto_poll_rate = |
503 | of_property_read_bool(dev->of_node, "auto-poll"); | |
98267d33 AJ |
504 | if (uap->dmarx.auto_poll_rate) { |
505 | u32 x; | |
506 | ||
28a7ec8c | 507 | if (of_property_read_u32(dev->of_node, "poll-rate-ms", &x) == 0) |
98267d33 AJ |
508 | uap->dmarx.poll_rate = x; |
509 | else | |
510 | uap->dmarx.poll_rate = 100; | |
28a7ec8c | 511 | if (of_property_read_u32(dev->of_node, "poll-timeout-ms", &x) == 0) |
98267d33 AJ |
512 | uap->dmarx.poll_timeout = x; |
513 | else | |
514 | uap->dmarx.poll_timeout = 3000; | |
515 | } | |
516 | } | |
ead76f32 LW |
517 | dev_info(uap->port.dev, "DMA channel RX %s\n", |
518 | dma_chan_name(uap->dmarx.chan)); | |
519 | } | |
68b65f73 RK |
520 | } |
521 | ||
68b65f73 RK |
522 | static void pl011_dma_remove(struct uart_amba_port *uap) |
523 | { | |
68b65f73 RK |
524 | if (uap->dmatx.chan) |
525 | dma_release_channel(uap->dmatx.chan); | |
ead76f32 LW |
526 | if (uap->dmarx.chan) |
527 | dma_release_channel(uap->dmarx.chan); | |
68b65f73 RK |
528 | } |
529 | ||
734745ca | 530 | /* Forward declare these for the refill routine */ |
68b65f73 | 531 | static int pl011_dma_tx_refill(struct uart_amba_port *uap); |
734745ca | 532 | static void pl011_start_tx_pio(struct uart_amba_port *uap); |
68b65f73 RK |
533 | |
534 | /* | |
535 | * The current DMA TX buffer has been sent. | |
536 | * Try to queue up another DMA buffer. | |
537 | */ | |
538 | static void pl011_dma_tx_callback(void *data) | |
539 | { | |
540 | struct uart_amba_port *uap = data; | |
541 | struct pl011_dmatx_data *dmatx = &uap->dmatx; | |
542 | unsigned long flags; | |
543 | u16 dmacr; | |
544 | ||
68ca3e72 | 545 | uart_port_lock_irqsave(&uap->port, &flags); |
68b65f73 | 546 | if (uap->dmatx.queued) |
58ac1b37 | 547 | dma_unmap_single(dmatx->chan->device->dev, dmatx->dma, |
d93ebe0f | 548 | dmatx->len, DMA_TO_DEVICE); |
68b65f73 RK |
549 | |
550 | dmacr = uap->dmacr; | |
551 | uap->dmacr = dmacr & ~UART011_TXDMAE; | |
9f25bc51 | 552 | pl011_write(uap->dmacr, uap, REG_DMACR); |
68b65f73 RK |
553 | |
554 | /* | |
555 | * If TX DMA was disabled, it means that we've stopped the DMA for | |
556 | * some reason (eg, XOFF received, or we want to send an X-char.) | |
557 | * | |
558 | * Note: we need to be careful here of a potential race between DMA | |
559 | * and the rest of the driver - if the driver disables TX DMA while | |
560 | * a TX buffer completing, we must update the tx queued status to | |
561 | * get further refills (hence we check dmacr). | |
562 | */ | |
563 | if (!(dmacr & UART011_TXDMAE) || uart_tx_stopped(&uap->port) || | |
564 | uart_circ_empty(&uap->port.state->xmit)) { | |
565 | uap->dmatx.queued = false; | |
68ca3e72 | 566 | uart_port_unlock_irqrestore(&uap->port, flags); |
68b65f73 RK |
567 | return; |
568 | } | |
569 | ||
734745ca | 570 | if (pl011_dma_tx_refill(uap) <= 0) |
68b65f73 RK |
571 | /* |
572 | * We didn't queue a DMA buffer for some reason, but we | |
573 | * have data pending to be sent. Re-enable the TX IRQ. | |
574 | */ | |
734745ca DM |
575 | pl011_start_tx_pio(uap); |
576 | ||
68ca3e72 | 577 | uart_port_unlock_irqrestore(&uap->port, flags); |
68b65f73 RK |
578 | } |
579 | ||
580 | /* | |
581 | * Try to refill the TX DMA buffer. | |
582 | * Locking: called with port lock held and IRQs disabled. | |
583 | * Returns: | |
584 | * 1 if we queued up a TX DMA buffer. | |
585 | * 0 if we didn't want to handle this by DMA | |
586 | * <0 on error | |
587 | */ | |
588 | static int pl011_dma_tx_refill(struct uart_amba_port *uap) | |
589 | { | |
590 | struct pl011_dmatx_data *dmatx = &uap->dmatx; | |
591 | struct dma_chan *chan = dmatx->chan; | |
592 | struct dma_device *dma_dev = chan->device; | |
593 | struct dma_async_tx_descriptor *desc; | |
594 | struct circ_buf *xmit = &uap->port.state->xmit; | |
595 | unsigned int count; | |
596 | ||
597 | /* | |
598 | * Try to avoid the overhead involved in using DMA if the | |
599 | * transaction fits in the first half of the FIFO, by using | |
600 | * the standard interrupt handling. This ensures that we | |
601 | * issue a uart_write_wakeup() at the appropriate time. | |
602 | */ | |
603 | count = uart_circ_chars_pending(xmit); | |
604 | if (count < (uap->fifosize >> 1)) { | |
605 | uap->dmatx.queued = false; | |
606 | return 0; | |
607 | } | |
608 | ||
609 | /* | |
610 | * Bodge: don't send the last character by DMA, as this | |
611 | * will prevent XON from notifying us to restart DMA. | |
612 | */ | |
613 | count -= 1; | |
614 | ||
615 | /* Else proceed to copy the TX chars to the DMA buffer and fire DMA */ | |
616 | if (count > PL011_DMA_BUFFER_SIZE) | |
617 | count = PL011_DMA_BUFFER_SIZE; | |
618 | ||
28a7ec8c | 619 | if (xmit->tail < xmit->head) { |
68b65f73 | 620 | memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], count); |
28a7ec8c | 621 | } else { |
68b65f73 | 622 | size_t first = UART_XMIT_SIZE - xmit->tail; |
e2a545a6 AJ |
623 | size_t second; |
624 | ||
625 | if (first > count) | |
626 | first = count; | |
627 | second = count - first; | |
68b65f73 RK |
628 | |
629 | memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], first); | |
630 | if (second) | |
631 | memcpy(&dmatx->buf[first], &xmit->buf[0], second); | |
632 | } | |
633 | ||
58ac1b37 AB |
634 | dmatx->len = count; |
635 | dmatx->dma = dma_map_single(dma_dev->dev, dmatx->buf, count, | |
636 | DMA_TO_DEVICE); | |
637 | if (dmatx->dma == DMA_MAPPING_ERROR) { | |
68b65f73 RK |
638 | uap->dmatx.queued = false; |
639 | dev_dbg(uap->port.dev, "unable to map TX DMA\n"); | |
640 | return -EBUSY; | |
641 | } | |
642 | ||
58ac1b37 | 643 | desc = dmaengine_prep_slave_single(chan, dmatx->dma, dmatx->len, DMA_MEM_TO_DEV, |
d93ebe0f | 644 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
68b65f73 | 645 | if (!desc) { |
58ac1b37 | 646 | dma_unmap_single(dma_dev->dev, dmatx->dma, dmatx->len, DMA_TO_DEVICE); |
68b65f73 RK |
647 | uap->dmatx.queued = false; |
648 | /* | |
649 | * If DMA cannot be used right now, we complete this | |
650 | * transaction via IRQ and let the TTY layer retry. | |
651 | */ | |
652 | dev_dbg(uap->port.dev, "TX DMA busy\n"); | |
653 | return -EBUSY; | |
654 | } | |
655 | ||
656 | /* Some data to go along to the callback */ | |
657 | desc->callback = pl011_dma_tx_callback; | |
658 | desc->callback_param = uap; | |
659 | ||
660 | /* All errors should happen at prepare time */ | |
661 | dmaengine_submit(desc); | |
662 | ||
663 | /* Fire the DMA transaction */ | |
664 | dma_dev->device_issue_pending(chan); | |
665 | ||
666 | uap->dmacr |= UART011_TXDMAE; | |
9f25bc51 | 667 | pl011_write(uap->dmacr, uap, REG_DMACR); |
68b65f73 RK |
668 | uap->dmatx.queued = true; |
669 | ||
670 | /* | |
671 | * Now we know that DMA will fire, so advance the ring buffer | |
672 | * with the stuff we just dispatched. | |
673 | */ | |
71a67573 | 674 | uart_xmit_advance(&uap->port, count); |
68b65f73 RK |
675 | |
676 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
677 | uart_write_wakeup(&uap->port); | |
678 | ||
679 | return 1; | |
680 | } | |
681 | ||
682 | /* | |
683 | * We received a transmit interrupt without a pending X-char but with | |
684 | * pending characters. | |
685 | * Locking: called with port lock held and IRQs disabled. | |
686 | * Returns: | |
687 | * false if we want to use PIO to transmit | |
688 | * true if we queued a DMA buffer | |
689 | */ | |
690 | static bool pl011_dma_tx_irq(struct uart_amba_port *uap) | |
691 | { | |
ead76f32 | 692 | if (!uap->using_tx_dma) |
68b65f73 RK |
693 | return false; |
694 | ||
695 | /* | |
696 | * If we already have a TX buffer queued, but received a | |
697 | * TX interrupt, it will be because we've just sent an X-char. | |
698 | * Ensure the TX DMA is enabled and the TX IRQ is disabled. | |
699 | */ | |
700 | if (uap->dmatx.queued) { | |
701 | uap->dmacr |= UART011_TXDMAE; | |
9f25bc51 | 702 | pl011_write(uap->dmacr, uap, REG_DMACR); |
68b65f73 | 703 | uap->im &= ~UART011_TXIM; |
9f25bc51 | 704 | pl011_write(uap->im, uap, REG_IMSC); |
68b65f73 RK |
705 | return true; |
706 | } | |
707 | ||
708 | /* | |
709 | * We don't have a TX buffer queued, so try to queue one. | |
25985edc | 710 | * If we successfully queued a buffer, mask the TX IRQ. |
68b65f73 RK |
711 | */ |
712 | if (pl011_dma_tx_refill(uap) > 0) { | |
713 | uap->im &= ~UART011_TXIM; | |
9f25bc51 | 714 | pl011_write(uap->im, uap, REG_IMSC); |
68b65f73 RK |
715 | return true; |
716 | } | |
717 | return false; | |
718 | } | |
719 | ||
720 | /* | |
721 | * Stop the DMA transmit (eg, due to received XOFF). | |
722 | * Locking: called with port lock held and IRQs disabled. | |
723 | */ | |
724 | static inline void pl011_dma_tx_stop(struct uart_amba_port *uap) | |
725 | { | |
726 | if (uap->dmatx.queued) { | |
727 | uap->dmacr &= ~UART011_TXDMAE; | |
9f25bc51 | 728 | pl011_write(uap->dmacr, uap, REG_DMACR); |
68b65f73 RK |
729 | } |
730 | } | |
731 | ||
732 | /* | |
733 | * Try to start a DMA transmit, or in the case of an XON/OFF | |
734 | * character queued for send, try to get that character out ASAP. | |
735 | * Locking: called with port lock held and IRQs disabled. | |
736 | * Returns: | |
737 | * false if we want the TX IRQ to be enabled | |
738 | * true if we have a buffer queued | |
739 | */ | |
740 | static inline bool pl011_dma_tx_start(struct uart_amba_port *uap) | |
741 | { | |
742 | u16 dmacr; | |
743 | ||
ead76f32 | 744 | if (!uap->using_tx_dma) |
68b65f73 RK |
745 | return false; |
746 | ||
747 | if (!uap->port.x_char) { | |
748 | /* no X-char, try to push chars out in DMA mode */ | |
749 | bool ret = true; | |
750 | ||
751 | if (!uap->dmatx.queued) { | |
752 | if (pl011_dma_tx_refill(uap) > 0) { | |
753 | uap->im &= ~UART011_TXIM; | |
9f25bc51 | 754 | pl011_write(uap->im, uap, REG_IMSC); |
28a7ec8c | 755 | } else { |
68b65f73 | 756 | ret = false; |
28a7ec8c | 757 | } |
68b65f73 RK |
758 | } else if (!(uap->dmacr & UART011_TXDMAE)) { |
759 | uap->dmacr |= UART011_TXDMAE; | |
9f25bc51 | 760 | pl011_write(uap->dmacr, uap, REG_DMACR); |
68b65f73 RK |
761 | } |
762 | return ret; | |
763 | } | |
764 | ||
765 | /* | |
766 | * We have an X-char to send. Disable DMA to prevent it loading | |
767 | * the TX fifo, and then see if we can stuff it into the FIFO. | |
768 | */ | |
769 | dmacr = uap->dmacr; | |
770 | uap->dmacr &= ~UART011_TXDMAE; | |
9f25bc51 | 771 | pl011_write(uap->dmacr, uap, REG_DMACR); |
68b65f73 | 772 | |
9f25bc51 | 773 | if (pl011_read(uap, REG_FR) & UART01x_FR_TXFF) { |
68b65f73 RK |
774 | /* |
775 | * No space in the FIFO, so enable the transmit interrupt | |
776 | * so we know when there is space. Note that once we've | |
777 | * loaded the character, we should just re-enable DMA. | |
778 | */ | |
779 | return false; | |
780 | } | |
781 | ||
9f25bc51 | 782 | pl011_write(uap->port.x_char, uap, REG_DR); |
68b65f73 RK |
783 | uap->port.icount.tx++; |
784 | uap->port.x_char = 0; | |
785 | ||
786 | /* Success - restore the DMA state */ | |
787 | uap->dmacr = dmacr; | |
9f25bc51 | 788 | pl011_write(dmacr, uap, REG_DMACR); |
68b65f73 RK |
789 | |
790 | return true; | |
791 | } | |
792 | ||
793 | /* | |
794 | * Flush the transmit buffer. | |
795 | * Locking: called with port lock held and IRQs disabled. | |
796 | */ | |
797 | static void pl011_dma_flush_buffer(struct uart_port *port) | |
b83286bf FE |
798 | __releases(&uap->port.lock) |
799 | __acquires(&uap->port.lock) | |
68b65f73 | 800 | { |
a5820c24 DT |
801 | struct uart_amba_port *uap = |
802 | container_of(port, struct uart_amba_port, port); | |
68b65f73 | 803 | |
ead76f32 | 804 | if (!uap->using_tx_dma) |
68b65f73 RK |
805 | return; |
806 | ||
f6a19647 VW |
807 | dmaengine_terminate_async(uap->dmatx.chan); |
808 | ||
68b65f73 | 809 | if (uap->dmatx.queued) { |
58ac1b37 AB |
810 | dma_unmap_single(uap->dmatx.chan->device->dev, uap->dmatx.dma, |
811 | uap->dmatx.len, DMA_TO_DEVICE); | |
68b65f73 RK |
812 | uap->dmatx.queued = false; |
813 | uap->dmacr &= ~UART011_TXDMAE; | |
9f25bc51 | 814 | pl011_write(uap->dmacr, uap, REG_DMACR); |
68b65f73 RK |
815 | } |
816 | } | |
817 | ||
ead76f32 LW |
818 | static void pl011_dma_rx_callback(void *data); |
819 | ||
820 | static int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap) | |
821 | { | |
822 | struct dma_chan *rxchan = uap->dmarx.chan; | |
ead76f32 LW |
823 | struct pl011_dmarx_data *dmarx = &uap->dmarx; |
824 | struct dma_async_tx_descriptor *desc; | |
58ac1b37 | 825 | struct pl011_dmabuf *dbuf; |
ead76f32 LW |
826 | |
827 | if (!rxchan) | |
828 | return -EIO; | |
829 | ||
830 | /* Start the RX DMA job */ | |
58ac1b37 AB |
831 | dbuf = uap->dmarx.use_buf_b ? |
832 | &uap->dmarx.dbuf_b : &uap->dmarx.dbuf_a; | |
833 | desc = dmaengine_prep_slave_single(rxchan, dbuf->dma, dbuf->len, | |
d93ebe0f TL |
834 | DMA_DEV_TO_MEM, |
835 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
ead76f32 LW |
836 | /* |
837 | * If the DMA engine is busy and cannot prepare a | |
838 | * channel, no big deal, the driver will fall back | |
839 | * to interrupt mode as a result of this error code. | |
840 | */ | |
841 | if (!desc) { | |
842 | uap->dmarx.running = false; | |
843 | dmaengine_terminate_all(rxchan); | |
844 | return -EBUSY; | |
845 | } | |
846 | ||
847 | /* Some data to go along to the callback */ | |
848 | desc->callback = pl011_dma_rx_callback; | |
849 | desc->callback_param = uap; | |
850 | dmarx->cookie = dmaengine_submit(desc); | |
851 | dma_async_issue_pending(rxchan); | |
852 | ||
853 | uap->dmacr |= UART011_RXDMAE; | |
9f25bc51 | 854 | pl011_write(uap->dmacr, uap, REG_DMACR); |
ead76f32 LW |
855 | uap->dmarx.running = true; |
856 | ||
857 | uap->im &= ~UART011_RXIM; | |
9f25bc51 | 858 | pl011_write(uap->im, uap, REG_IMSC); |
ead76f32 LW |
859 | |
860 | return 0; | |
861 | } | |
862 | ||
863 | /* | |
864 | * This is called when either the DMA job is complete, or | |
865 | * the FIFO timeout interrupt occurred. This must be called | |
866 | * with the port spinlock uap->port.lock held. | |
867 | */ | |
868 | static void pl011_dma_rx_chars(struct uart_amba_port *uap, | |
869 | u32 pending, bool use_buf_b, | |
870 | bool readfifo) | |
871 | { | |
05c7cd39 | 872 | struct tty_port *port = &uap->port.state->port; |
58ac1b37 AB |
873 | struct pl011_dmabuf *dbuf = use_buf_b ? |
874 | &uap->dmarx.dbuf_b : &uap->dmarx.dbuf_a; | |
ead76f32 LW |
875 | int dma_count = 0; |
876 | u32 fifotaken = 0; /* only used for vdbg() */ | |
877 | ||
cb06ff10 CM |
878 | struct pl011_dmarx_data *dmarx = &uap->dmarx; |
879 | int dmataken = 0; | |
880 | ||
881 | if (uap->dmarx.poll_rate) { | |
882 | /* The data can be taken by polling */ | |
58ac1b37 | 883 | dmataken = dbuf->len - dmarx->last_residue; |
cb06ff10 CM |
884 | /* Recalculate the pending size */ |
885 | if (pending >= dmataken) | |
886 | pending -= dmataken; | |
887 | } | |
888 | ||
889 | /* Pick the remain data from the DMA */ | |
ead76f32 | 890 | if (pending) { |
ead76f32 LW |
891 | /* |
892 | * First take all chars in the DMA pipe, then look in the FIFO. | |
893 | * Note that tty_insert_flip_buf() tries to take as many chars | |
894 | * as it can. | |
895 | */ | |
d93ebe0f | 896 | dma_count = tty_insert_flip_string(port, dbuf->buf + dmataken, pending); |
ead76f32 LW |
897 | |
898 | uap->port.icount.rx += dma_count; | |
899 | if (dma_count < pending) | |
900 | dev_warn(uap->port.dev, | |
901 | "couldn't insert all characters (TTY is full?)\n"); | |
902 | } | |
903 | ||
cb06ff10 CM |
904 | /* Reset the last_residue for Rx DMA poll */ |
905 | if (uap->dmarx.poll_rate) | |
58ac1b37 | 906 | dmarx->last_residue = dbuf->len; |
cb06ff10 | 907 | |
ead76f32 LW |
908 | /* |
909 | * Only continue with trying to read the FIFO if all DMA chars have | |
910 | * been taken first. | |
911 | */ | |
912 | if (dma_count == pending && readfifo) { | |
913 | /* Clear any error flags */ | |
75836339 | 914 | pl011_write(UART011_OEIS | UART011_BEIS | UART011_PEIS | |
9f25bc51 | 915 | UART011_FEIS, uap, REG_ICR); |
ead76f32 LW |
916 | |
917 | /* | |
918 | * If we read all the DMA'd characters, and we had an | |
29772c4e LW |
919 | * incomplete buffer, that could be due to an rx error, or |
920 | * maybe we just timed out. Read any pending chars and check | |
921 | * the error status. | |
922 | * | |
923 | * Error conditions will only occur in the FIFO, these will | |
924 | * trigger an immediate interrupt and stop the DMA job, so we | |
925 | * will always find the error in the FIFO, never in the DMA | |
926 | * buffer. | |
ead76f32 | 927 | */ |
29772c4e | 928 | fifotaken = pl011_fifo_to_tty(uap); |
ead76f32 LW |
929 | } |
930 | ||
ead76f32 LW |
931 | dev_vdbg(uap->port.dev, |
932 | "Took %d chars from DMA buffer and %d chars from the FIFO\n", | |
933 | dma_count, fifotaken); | |
2e124b4a | 934 | tty_flip_buffer_push(port); |
ead76f32 LW |
935 | } |
936 | ||
937 | static void pl011_dma_rx_irq(struct uart_amba_port *uap) | |
938 | { | |
939 | struct pl011_dmarx_data *dmarx = &uap->dmarx; | |
940 | struct dma_chan *rxchan = dmarx->chan; | |
58ac1b37 AB |
941 | struct pl011_dmabuf *dbuf = dmarx->use_buf_b ? |
942 | &dmarx->dbuf_b : &dmarx->dbuf_a; | |
ead76f32 LW |
943 | size_t pending; |
944 | struct dma_tx_state state; | |
945 | enum dma_status dmastat; | |
946 | ||
947 | /* | |
948 | * Pause the transfer so we can trust the current counter, | |
949 | * do this before we pause the PL011 block, else we may | |
950 | * overflow the FIFO. | |
951 | */ | |
952 | if (dmaengine_pause(rxchan)) | |
953 | dev_err(uap->port.dev, "unable to pause DMA transfer\n"); | |
954 | dmastat = rxchan->device->device_tx_status(rxchan, | |
955 | dmarx->cookie, &state); | |
956 | if (dmastat != DMA_PAUSED) | |
957 | dev_err(uap->port.dev, "unable to pause DMA transfer\n"); | |
958 | ||
959 | /* Disable RX DMA - incoming data will wait in the FIFO */ | |
960 | uap->dmacr &= ~UART011_RXDMAE; | |
9f25bc51 | 961 | pl011_write(uap->dmacr, uap, REG_DMACR); |
ead76f32 LW |
962 | uap->dmarx.running = false; |
963 | ||
58ac1b37 | 964 | pending = dbuf->len - state.residue; |
ead76f32 LW |
965 | BUG_ON(pending > PL011_DMA_BUFFER_SIZE); |
966 | /* Then we terminate the transfer - we now know our residue */ | |
967 | dmaengine_terminate_all(rxchan); | |
968 | ||
969 | /* | |
970 | * This will take the chars we have so far and insert | |
971 | * into the framework. | |
972 | */ | |
973 | pl011_dma_rx_chars(uap, pending, dmarx->use_buf_b, true); | |
974 | ||
975 | /* Switch buffer & re-trigger DMA job */ | |
976 | dmarx->use_buf_b = !dmarx->use_buf_b; | |
977 | if (pl011_dma_rx_trigger_dma(uap)) { | |
fd64ff09 TL |
978 | dev_dbg(uap->port.dev, |
979 | "could not retrigger RX DMA job fall back to interrupt mode\n"); | |
ead76f32 | 980 | uap->im |= UART011_RXIM; |
9f25bc51 | 981 | pl011_write(uap->im, uap, REG_IMSC); |
ead76f32 LW |
982 | } |
983 | } | |
984 | ||
985 | static void pl011_dma_rx_callback(void *data) | |
986 | { | |
987 | struct uart_amba_port *uap = data; | |
988 | struct pl011_dmarx_data *dmarx = &uap->dmarx; | |
6dc01aa6 | 989 | struct dma_chan *rxchan = dmarx->chan; |
ead76f32 | 990 | bool lastbuf = dmarx->use_buf_b; |
58ac1b37 AB |
991 | struct pl011_dmabuf *dbuf = dmarx->use_buf_b ? |
992 | &dmarx->dbuf_b : &dmarx->dbuf_a; | |
6dc01aa6 CM |
993 | size_t pending; |
994 | struct dma_tx_state state; | |
ead76f32 LW |
995 | int ret; |
996 | ||
997 | /* | |
998 | * This completion interrupt occurs typically when the | |
999 | * RX buffer is totally stuffed but no timeout has yet | |
1000 | * occurred. When that happens, we just want the RX | |
1001 | * routine to flush out the secondary DMA buffer while | |
1002 | * we immediately trigger the next DMA job. | |
1003 | */ | |
68ca3e72 | 1004 | uart_port_lock_irq(&uap->port); |
6dc01aa6 CM |
1005 | /* |
1006 | * Rx data can be taken by the UART interrupts during | |
1007 | * the DMA irq handler. So we check the residue here. | |
1008 | */ | |
1009 | rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state); | |
58ac1b37 | 1010 | pending = dbuf->len - state.residue; |
6dc01aa6 CM |
1011 | BUG_ON(pending > PL011_DMA_BUFFER_SIZE); |
1012 | /* Then we terminate the transfer - we now know our residue */ | |
1013 | dmaengine_terminate_all(rxchan); | |
1014 | ||
ead76f32 LW |
1015 | uap->dmarx.running = false; |
1016 | dmarx->use_buf_b = !lastbuf; | |
1017 | ret = pl011_dma_rx_trigger_dma(uap); | |
1018 | ||
6dc01aa6 | 1019 | pl011_dma_rx_chars(uap, pending, lastbuf, false); |
68ca3e72 | 1020 | uart_port_unlock_irq(&uap->port); |
ead76f32 LW |
1021 | /* |
1022 | * Do this check after we picked the DMA chars so we don't | |
1023 | * get some IRQ immediately from RX. | |
1024 | */ | |
1025 | if (ret) { | |
fd64ff09 TL |
1026 | dev_dbg(uap->port.dev, |
1027 | "could not retrigger RX DMA job fall back to interrupt mode\n"); | |
ead76f32 | 1028 | uap->im |= UART011_RXIM; |
9f25bc51 | 1029 | pl011_write(uap->im, uap, REG_IMSC); |
ead76f32 LW |
1030 | } |
1031 | } | |
1032 | ||
1033 | /* | |
1034 | * Stop accepting received characters, when we're shutting down or | |
1035 | * suspending this port. | |
1036 | * Locking: called with port lock held and IRQs disabled. | |
1037 | */ | |
1038 | static inline void pl011_dma_rx_stop(struct uart_amba_port *uap) | |
1039 | { | |
94cdb9f3 JX |
1040 | if (!uap->using_rx_dma) |
1041 | return; | |
1042 | ||
ead76f32 LW |
1043 | /* FIXME. Just disable the DMA enable */ |
1044 | uap->dmacr &= ~UART011_RXDMAE; | |
9f25bc51 | 1045 | pl011_write(uap->dmacr, uap, REG_DMACR); |
ead76f32 | 1046 | } |
68b65f73 | 1047 | |
cb06ff10 CM |
1048 | /* |
1049 | * Timer handler for Rx DMA polling. | |
1050 | * Every polling, It checks the residue in the dma buffer and transfer | |
1051 | * data to the tty. Also, last_residue is updated for the next polling. | |
1052 | */ | |
f7f73096 | 1053 | static void pl011_dma_rx_poll(struct timer_list *t) |
cb06ff10 | 1054 | { |
f7f73096 | 1055 | struct uart_amba_port *uap = from_timer(uap, t, dmarx.timer); |
cb06ff10 CM |
1056 | struct tty_port *port = &uap->port.state->port; |
1057 | struct pl011_dmarx_data *dmarx = &uap->dmarx; | |
1058 | struct dma_chan *rxchan = uap->dmarx.chan; | |
18ee37e1 | 1059 | unsigned long flags; |
cb06ff10 CM |
1060 | unsigned int dmataken = 0; |
1061 | unsigned int size = 0; | |
58ac1b37 | 1062 | struct pl011_dmabuf *dbuf; |
cb06ff10 CM |
1063 | int dma_count; |
1064 | struct dma_tx_state state; | |
1065 | ||
58ac1b37 | 1066 | dbuf = dmarx->use_buf_b ? &uap->dmarx.dbuf_b : &uap->dmarx.dbuf_a; |
cb06ff10 CM |
1067 | rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state); |
1068 | if (likely(state.residue < dmarx->last_residue)) { | |
58ac1b37 | 1069 | dmataken = dbuf->len - dmarx->last_residue; |
cb06ff10 | 1070 | size = dmarx->last_residue - state.residue; |
58ac1b37 | 1071 | dma_count = tty_insert_flip_string(port, dbuf->buf + dmataken, |
d93ebe0f | 1072 | size); |
cb06ff10 CM |
1073 | if (dma_count == size) |
1074 | dmarx->last_residue = state.residue; | |
1075 | dmarx->last_jiffies = jiffies; | |
1076 | } | |
1077 | tty_flip_buffer_push(port); | |
1078 | ||
1079 | /* | |
1080 | * If no data is received in poll_timeout, the driver will fall back | |
1081 | * to interrupt mode. We will retrigger DMA at the first interrupt. | |
1082 | */ | |
1083 | if (jiffies_to_msecs(jiffies - dmarx->last_jiffies) | |
1084 | > uap->dmarx.poll_timeout) { | |
68ca3e72 | 1085 | uart_port_lock_irqsave(&uap->port, &flags); |
cb06ff10 | 1086 | pl011_dma_rx_stop(uap); |
c25a1ad7 | 1087 | uap->im |= UART011_RXIM; |
9f25bc51 | 1088 | pl011_write(uap->im, uap, REG_IMSC); |
68ca3e72 | 1089 | uart_port_unlock_irqrestore(&uap->port, flags); |
cb06ff10 CM |
1090 | |
1091 | uap->dmarx.running = false; | |
1092 | dmaengine_terminate_all(rxchan); | |
1093 | del_timer(&uap->dmarx.timer); | |
1094 | } else { | |
1095 | mod_timer(&uap->dmarx.timer, | |
d93ebe0f | 1096 | jiffies + msecs_to_jiffies(uap->dmarx.poll_rate)); |
cb06ff10 CM |
1097 | } |
1098 | } | |
1099 | ||
68b65f73 RK |
1100 | static void pl011_dma_startup(struct uart_amba_port *uap) |
1101 | { | |
ead76f32 LW |
1102 | int ret; |
1103 | ||
1c9be310 JRO |
1104 | if (!uap->dma_probed) |
1105 | pl011_dma_probe(uap); | |
1106 | ||
68b65f73 RK |
1107 | if (!uap->dmatx.chan) |
1108 | return; | |
1109 | ||
4c0be45b | 1110 | uap->dmatx.buf = kmalloc(PL011_DMA_BUFFER_SIZE, GFP_KERNEL | __GFP_DMA); |
68b65f73 | 1111 | if (!uap->dmatx.buf) { |
68b65f73 RK |
1112 | uap->port.fifosize = uap->fifosize; |
1113 | return; | |
1114 | } | |
1115 | ||
58ac1b37 | 1116 | uap->dmatx.len = PL011_DMA_BUFFER_SIZE; |
68b65f73 RK |
1117 | |
1118 | /* The DMA buffer is now the FIFO the TTY subsystem can use */ | |
1119 | uap->port.fifosize = PL011_DMA_BUFFER_SIZE; | |
ead76f32 LW |
1120 | uap->using_tx_dma = true; |
1121 | ||
1122 | if (!uap->dmarx.chan) | |
1123 | goto skip_rx; | |
1124 | ||
1125 | /* Allocate and map DMA RX buffers */ | |
58ac1b37 | 1126 | ret = pl011_dmabuf_init(uap->dmarx.chan, &uap->dmarx.dbuf_a, |
d93ebe0f | 1127 | DMA_FROM_DEVICE); |
ead76f32 LW |
1128 | if (ret) { |
1129 | dev_err(uap->port.dev, "failed to init DMA %s: %d\n", | |
1130 | "RX buffer A", ret); | |
1131 | goto skip_rx; | |
1132 | } | |
68b65f73 | 1133 | |
58ac1b37 | 1134 | ret = pl011_dmabuf_init(uap->dmarx.chan, &uap->dmarx.dbuf_b, |
d93ebe0f | 1135 | DMA_FROM_DEVICE); |
ead76f32 LW |
1136 | if (ret) { |
1137 | dev_err(uap->port.dev, "failed to init DMA %s: %d\n", | |
1138 | "RX buffer B", ret); | |
58ac1b37 | 1139 | pl011_dmabuf_free(uap->dmarx.chan, &uap->dmarx.dbuf_a, |
d93ebe0f | 1140 | DMA_FROM_DEVICE); |
ead76f32 LW |
1141 | goto skip_rx; |
1142 | } | |
1143 | ||
1144 | uap->using_rx_dma = true; | |
68b65f73 | 1145 | |
ead76f32 | 1146 | skip_rx: |
68b65f73 RK |
1147 | /* Turn on DMA error (RX/TX will be enabled on demand) */ |
1148 | uap->dmacr |= UART011_DMAONERR; | |
9f25bc51 | 1149 | pl011_write(uap->dmacr, uap, REG_DMACR); |
38d62436 RK |
1150 | |
1151 | /* | |
1152 | * ST Micro variants has some specific dma burst threshold | |
1153 | * compensation. Set this to 16 bytes, so burst will only | |
1154 | * be issued above/below 16 bytes. | |
1155 | */ | |
1156 | if (uap->vendor->dma_threshold) | |
75836339 | 1157 | pl011_write(ST_UART011_DMAWM_RX_16 | ST_UART011_DMAWM_TX_16, |
9f25bc51 | 1158 | uap, REG_ST_DMAWM); |
ead76f32 LW |
1159 | |
1160 | if (uap->using_rx_dma) { | |
1161 | if (pl011_dma_rx_trigger_dma(uap)) | |
fd64ff09 TL |
1162 | dev_dbg(uap->port.dev, |
1163 | "could not trigger initial RX DMA job, fall back to interrupt mode\n"); | |
cb06ff10 | 1164 | if (uap->dmarx.poll_rate) { |
f7f73096 | 1165 | timer_setup(&uap->dmarx.timer, pl011_dma_rx_poll, 0); |
cb06ff10 | 1166 | mod_timer(&uap->dmarx.timer, |
d93ebe0f | 1167 | jiffies + msecs_to_jiffies(uap->dmarx.poll_rate)); |
cb06ff10 CM |
1168 | uap->dmarx.last_residue = PL011_DMA_BUFFER_SIZE; |
1169 | uap->dmarx.last_jiffies = jiffies; | |
1170 | } | |
ead76f32 | 1171 | } |
68b65f73 RK |
1172 | } |
1173 | ||
1174 | static void pl011_dma_shutdown(struct uart_amba_port *uap) | |
1175 | { | |
ead76f32 | 1176 | if (!(uap->using_tx_dma || uap->using_rx_dma)) |
68b65f73 RK |
1177 | return; |
1178 | ||
1179 | /* Disable RX and TX DMA */ | |
0e125a5f | 1180 | while (pl011_read(uap, REG_FR) & uap->vendor->fr_busy) |
2f2fd089 | 1181 | cpu_relax(); |
68b65f73 | 1182 | |
68ca3e72 | 1183 | uart_port_lock_irq(&uap->port); |
68b65f73 | 1184 | uap->dmacr &= ~(UART011_DMAONERR | UART011_RXDMAE | UART011_TXDMAE); |
9f25bc51 | 1185 | pl011_write(uap->dmacr, uap, REG_DMACR); |
68ca3e72 | 1186 | uart_port_unlock_irq(&uap->port); |
68b65f73 | 1187 | |
ead76f32 LW |
1188 | if (uap->using_tx_dma) { |
1189 | /* In theory, this should already be done by pl011_dma_flush_buffer */ | |
1190 | dmaengine_terminate_all(uap->dmatx.chan); | |
1191 | if (uap->dmatx.queued) { | |
58ac1b37 AB |
1192 | dma_unmap_single(uap->dmatx.chan->device->dev, |
1193 | uap->dmatx.dma, uap->dmatx.len, | |
1194 | DMA_TO_DEVICE); | |
ead76f32 LW |
1195 | uap->dmatx.queued = false; |
1196 | } | |
1197 | ||
1198 | kfree(uap->dmatx.buf); | |
1199 | uap->using_tx_dma = false; | |
68b65f73 RK |
1200 | } |
1201 | ||
ead76f32 LW |
1202 | if (uap->using_rx_dma) { |
1203 | dmaengine_terminate_all(uap->dmarx.chan); | |
1204 | /* Clean up the RX DMA */ | |
58ac1b37 AB |
1205 | pl011_dmabuf_free(uap->dmarx.chan, &uap->dmarx.dbuf_a, DMA_FROM_DEVICE); |
1206 | pl011_dmabuf_free(uap->dmarx.chan, &uap->dmarx.dbuf_b, DMA_FROM_DEVICE); | |
cb06ff10 CM |
1207 | if (uap->dmarx.poll_rate) |
1208 | del_timer_sync(&uap->dmarx.timer); | |
ead76f32 LW |
1209 | uap->using_rx_dma = false; |
1210 | } | |
1211 | } | |
68b65f73 | 1212 | |
ead76f32 LW |
1213 | static inline bool pl011_dma_rx_available(struct uart_amba_port *uap) |
1214 | { | |
1215 | return uap->using_rx_dma; | |
68b65f73 RK |
1216 | } |
1217 | ||
ead76f32 LW |
1218 | static inline bool pl011_dma_rx_running(struct uart_amba_port *uap) |
1219 | { | |
1220 | return uap->using_rx_dma && uap->dmarx.running; | |
1221 | } | |
1222 | ||
68b65f73 RK |
1223 | #else |
1224 | /* Blank functions if the DMA engine is not available */ | |
68b65f73 RK |
1225 | static inline void pl011_dma_remove(struct uart_amba_port *uap) |
1226 | { | |
1227 | } | |
1228 | ||
1229 | static inline void pl011_dma_startup(struct uart_amba_port *uap) | |
1230 | { | |
1231 | } | |
1232 | ||
1233 | static inline void pl011_dma_shutdown(struct uart_amba_port *uap) | |
1234 | { | |
1235 | } | |
1236 | ||
1237 | static inline bool pl011_dma_tx_irq(struct uart_amba_port *uap) | |
1238 | { | |
1239 | return false; | |
1240 | } | |
1241 | ||
1242 | static inline void pl011_dma_tx_stop(struct uart_amba_port *uap) | |
1243 | { | |
1244 | } | |
1245 | ||
1246 | static inline bool pl011_dma_tx_start(struct uart_amba_port *uap) | |
1247 | { | |
1248 | return false; | |
1249 | } | |
1250 | ||
ead76f32 LW |
1251 | static inline void pl011_dma_rx_irq(struct uart_amba_port *uap) |
1252 | { | |
1253 | } | |
1254 | ||
1255 | static inline void pl011_dma_rx_stop(struct uart_amba_port *uap) | |
1256 | { | |
1257 | } | |
1258 | ||
1259 | static inline int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap) | |
1260 | { | |
1261 | return -EIO; | |
1262 | } | |
1263 | ||
1264 | static inline bool pl011_dma_rx_available(struct uart_amba_port *uap) | |
1265 | { | |
1266 | return false; | |
1267 | } | |
1268 | ||
1269 | static inline bool pl011_dma_rx_running(struct uart_amba_port *uap) | |
1270 | { | |
1271 | return false; | |
1272 | } | |
1273 | ||
68b65f73 RK |
1274 | #define pl011_dma_flush_buffer NULL |
1275 | #endif | |
1276 | ||
8d479237 LS |
1277 | static void pl011_rs485_tx_stop(struct uart_amba_port *uap) |
1278 | { | |
0e4deb56 LS |
1279 | /* |
1280 | * To be on the safe side only time out after twice as many iterations | |
1281 | * as fifo size. | |
1282 | */ | |
1283 | const int MAX_TX_DRAIN_ITERS = uap->port.fifosize * 2; | |
8d479237 LS |
1284 | struct uart_port *port = &uap->port; |
1285 | int i = 0; | |
1286 | u32 cr; | |
1287 | ||
1288 | /* Wait until hardware tx queue is empty */ | |
1289 | while (!pl011_tx_empty(port)) { | |
0e4deb56 | 1290 | if (i > MAX_TX_DRAIN_ITERS) { |
8d479237 LS |
1291 | dev_warn(port->dev, |
1292 | "timeout while draining hardware tx queue\n"); | |
1293 | break; | |
1294 | } | |
1295 | ||
1296 | udelay(uap->rs485_tx_drain_interval); | |
1297 | i++; | |
1298 | } | |
1299 | ||
1300 | if (port->rs485.delay_rts_after_send) | |
1301 | mdelay(port->rs485.delay_rts_after_send); | |
1302 | ||
1303 | cr = pl011_read(uap, REG_CR); | |
1304 | ||
1305 | if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND) | |
1306 | cr &= ~UART011_CR_RTS; | |
1307 | else | |
1308 | cr |= UART011_CR_RTS; | |
1309 | ||
1310 | /* Disable the transmitter and reenable the transceiver */ | |
1311 | cr &= ~UART011_CR_TXE; | |
1312 | cr |= UART011_CR_RXE; | |
1313 | pl011_write(cr, uap, REG_CR); | |
1314 | ||
1315 | uap->rs485_tx_started = false; | |
1316 | } | |
1317 | ||
b129a8cc | 1318 | static void pl011_stop_tx(struct uart_port *port) |
1da177e4 | 1319 | { |
a5820c24 DT |
1320 | struct uart_amba_port *uap = |
1321 | container_of(port, struct uart_amba_port, port); | |
1da177e4 LT |
1322 | |
1323 | uap->im &= ~UART011_TXIM; | |
9f25bc51 | 1324 | pl011_write(uap->im, uap, REG_IMSC); |
68b65f73 | 1325 | pl011_dma_tx_stop(uap); |
8d479237 LS |
1326 | |
1327 | if ((port->rs485.flags & SER_RS485_ENABLED) && uap->rs485_tx_started) | |
1328 | pl011_rs485_tx_stop(uap); | |
1da177e4 LT |
1329 | } |
1330 | ||
7d05587c | 1331 | static bool pl011_tx_chars(struct uart_amba_port *uap, bool from_irq); |
734745ca DM |
1332 | |
1333 | /* Start TX with programmed I/O only (no DMA) */ | |
1334 | static void pl011_start_tx_pio(struct uart_amba_port *uap) | |
1335 | { | |
7d05587c J |
1336 | if (pl011_tx_chars(uap, false)) { |
1337 | uap->im |= UART011_TXIM; | |
1338 | pl011_write(uap->im, uap, REG_IMSC); | |
1339 | } | |
734745ca DM |
1340 | } |
1341 | ||
3b69e32e LS |
1342 | static void pl011_rs485_tx_start(struct uart_amba_port *uap) |
1343 | { | |
1344 | struct uart_port *port = &uap->port; | |
1345 | u32 cr; | |
1346 | ||
1347 | /* Enable transmitter */ | |
1348 | cr = pl011_read(uap, REG_CR); | |
1349 | cr |= UART011_CR_TXE; | |
1350 | ||
1351 | /* Disable receiver if half-duplex */ | |
1352 | if (!(port->rs485.flags & SER_RS485_RX_DURING_TX)) | |
1353 | cr &= ~UART011_CR_RXE; | |
1354 | ||
1355 | if (port->rs485.flags & SER_RS485_RTS_ON_SEND) | |
1356 | cr &= ~UART011_CR_RTS; | |
1357 | else | |
1358 | cr |= UART011_CR_RTS; | |
1359 | ||
1360 | pl011_write(cr, uap, REG_CR); | |
1361 | ||
1362 | if (port->rs485.delay_rts_before_send) | |
1363 | mdelay(port->rs485.delay_rts_before_send); | |
1364 | ||
1365 | uap->rs485_tx_started = true; | |
1366 | } | |
1367 | ||
b129a8cc | 1368 | static void pl011_start_tx(struct uart_port *port) |
1da177e4 | 1369 | { |
a5820c24 DT |
1370 | struct uart_amba_port *uap = |
1371 | container_of(port, struct uart_amba_port, port); | |
1da177e4 | 1372 | |
3b69e32e LS |
1373 | if ((uap->port.rs485.flags & SER_RS485_ENABLED) && |
1374 | !uap->rs485_tx_started) | |
1375 | pl011_rs485_tx_start(uap); | |
1376 | ||
734745ca DM |
1377 | if (!pl011_dma_tx_start(uap)) |
1378 | pl011_start_tx_pio(uap); | |
1da177e4 LT |
1379 | } |
1380 | ||
1381 | static void pl011_stop_rx(struct uart_port *port) | |
1382 | { | |
a5820c24 DT |
1383 | struct uart_amba_port *uap = |
1384 | container_of(port, struct uart_amba_port, port); | |
1da177e4 | 1385 | |
d93ebe0f TL |
1386 | uap->im &= ~(UART011_RXIM | UART011_RTIM | UART011_FEIM | |
1387 | UART011_PEIM | UART011_BEIM | UART011_OEIM); | |
9f25bc51 | 1388 | pl011_write(uap->im, uap, REG_IMSC); |
ead76f32 LW |
1389 | |
1390 | pl011_dma_rx_stop(uap); | |
1da177e4 LT |
1391 | } |
1392 | ||
211565b1 IJ |
1393 | static void pl011_throttle_rx(struct uart_port *port) |
1394 | { | |
1395 | unsigned long flags; | |
1396 | ||
68ca3e72 | 1397 | uart_port_lock_irqsave(port, &flags); |
211565b1 | 1398 | pl011_stop_rx(port); |
68ca3e72 | 1399 | uart_port_unlock_irqrestore(port, flags); |
211565b1 IJ |
1400 | } |
1401 | ||
1da177e4 LT |
1402 | static void pl011_enable_ms(struct uart_port *port) |
1403 | { | |
a5820c24 DT |
1404 | struct uart_amba_port *uap = |
1405 | container_of(port, struct uart_amba_port, port); | |
1da177e4 | 1406 | |
d93ebe0f | 1407 | uap->im |= UART011_RIMIM | UART011_CTSMIM | UART011_DCDMIM | UART011_DSRMIM; |
9f25bc51 | 1408 | pl011_write(uap->im, uap, REG_IMSC); |
1da177e4 LT |
1409 | } |
1410 | ||
7d12e780 | 1411 | static void pl011_rx_chars(struct uart_amba_port *uap) |
b83286bf FE |
1412 | __releases(&uap->port.lock) |
1413 | __acquires(&uap->port.lock) | |
1da177e4 | 1414 | { |
29772c4e | 1415 | pl011_fifo_to_tty(uap); |
1da177e4 | 1416 | |
68ca3e72 | 1417 | uart_port_unlock(&uap->port); |
2e124b4a | 1418 | tty_flip_buffer_push(&uap->port.state->port); |
ead76f32 LW |
1419 | /* |
1420 | * If we were temporarily out of DMA mode for a while, | |
1421 | * attempt to switch back to DMA mode again. | |
1422 | */ | |
1423 | if (pl011_dma_rx_available(uap)) { | |
1424 | if (pl011_dma_rx_trigger_dma(uap)) { | |
fd64ff09 TL |
1425 | dev_dbg(uap->port.dev, |
1426 | "could not trigger RX DMA job fall back to interrupt mode again\n"); | |
ead76f32 | 1427 | uap->im |= UART011_RXIM; |
9f25bc51 | 1428 | pl011_write(uap->im, uap, REG_IMSC); |
cb06ff10 | 1429 | } else { |
89fa28db | 1430 | #ifdef CONFIG_DMA_ENGINE |
cb06ff10 CM |
1431 | /* Start Rx DMA poll */ |
1432 | if (uap->dmarx.poll_rate) { | |
1433 | uap->dmarx.last_jiffies = jiffies; | |
1434 | uap->dmarx.last_residue = PL011_DMA_BUFFER_SIZE; | |
1435 | mod_timer(&uap->dmarx.timer, | |
d93ebe0f | 1436 | jiffies + msecs_to_jiffies(uap->dmarx.poll_rate)); |
cb06ff10 | 1437 | } |
89fa28db | 1438 | #endif |
cb06ff10 | 1439 | } |
ead76f32 | 1440 | } |
68ca3e72 | 1441 | uart_port_lock(&uap->port); |
1da177e4 LT |
1442 | } |
1443 | ||
1e84d223 DM |
1444 | static bool pl011_tx_char(struct uart_amba_port *uap, unsigned char c, |
1445 | bool from_irq) | |
734745ca | 1446 | { |
1e84d223 | 1447 | if (unlikely(!from_irq) && |
9f25bc51 | 1448 | pl011_read(uap, REG_FR) & UART01x_FR_TXFF) |
1e84d223 DM |
1449 | return false; /* unable to transmit character */ |
1450 | ||
9f25bc51 | 1451 | pl011_write(c, uap, REG_DR); |
734745ca DM |
1452 | uap->port.icount.tx++; |
1453 | ||
1e84d223 | 1454 | return true; |
734745ca DM |
1455 | } |
1456 | ||
7d05587c J |
1457 | /* Returns true if tx interrupts have to be (kept) enabled */ |
1458 | static bool pl011_tx_chars(struct uart_amba_port *uap, bool from_irq) | |
1da177e4 | 1459 | { |
ebd2c8f6 | 1460 | struct circ_buf *xmit = &uap->port.state->xmit; |
1e84d223 | 1461 | int count = uap->fifosize >> 1; |
734745ca | 1462 | |
1da177e4 | 1463 | if (uap->port.x_char) { |
1e84d223 | 1464 | if (!pl011_tx_char(uap, uap->port.x_char, from_irq)) |
7d05587c | 1465 | return true; |
1da177e4 | 1466 | uap->port.x_char = 0; |
734745ca | 1467 | --count; |
1da177e4 LT |
1468 | } |
1469 | if (uart_circ_empty(xmit) || uart_tx_stopped(&uap->port)) { | |
b129a8cc | 1470 | pl011_stop_tx(&uap->port); |
7d05587c | 1471 | return false; |
1da177e4 LT |
1472 | } |
1473 | ||
68b65f73 RK |
1474 | /* If we are using DMA mode, try to send some characters. */ |
1475 | if (pl011_dma_tx_irq(uap)) | |
7d05587c | 1476 | return true; |
68b65f73 | 1477 | |
1e84d223 DM |
1478 | do { |
1479 | if (likely(from_irq) && count-- == 0) | |
1da177e4 | 1480 | break; |
1e84d223 DM |
1481 | |
1482 | if (!pl011_tx_char(uap, xmit->buf[xmit->tail], from_irq)) | |
1483 | break; | |
1484 | ||
1485 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); | |
1486 | } while (!uart_circ_empty(xmit)); | |
1da177e4 LT |
1487 | |
1488 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
1489 | uart_write_wakeup(&uap->port); | |
1490 | ||
7d05587c | 1491 | if (uart_circ_empty(xmit)) { |
b129a8cc | 1492 | pl011_stop_tx(&uap->port); |
7d05587c J |
1493 | return false; |
1494 | } | |
1495 | return true; | |
1da177e4 LT |
1496 | } |
1497 | ||
1498 | static void pl011_modem_status(struct uart_amba_port *uap) | |
1499 | { | |
1500 | unsigned int status, delta; | |
1501 | ||
9f25bc51 | 1502 | status = pl011_read(uap, REG_FR) & UART01x_FR_MODEM_ANY; |
1da177e4 LT |
1503 | |
1504 | delta = status ^ uap->old_status; | |
1505 | uap->old_status = status; | |
1506 | ||
1507 | if (!delta) | |
1508 | return; | |
1509 | ||
1510 | if (delta & UART01x_FR_DCD) | |
1511 | uart_handle_dcd_change(&uap->port, status & UART01x_FR_DCD); | |
1512 | ||
0e125a5f | 1513 | if (delta & uap->vendor->fr_dsr) |
1da177e4 LT |
1514 | uap->port.icount.dsr++; |
1515 | ||
0e125a5f SG |
1516 | if (delta & uap->vendor->fr_cts) |
1517 | uart_handle_cts_change(&uap->port, | |
1518 | status & uap->vendor->fr_cts); | |
1da177e4 | 1519 | |
bdc04e31 | 1520 | wake_up_interruptible(&uap->port.state->port.delta_msr_wait); |
1da177e4 LT |
1521 | } |
1522 | ||
9c4ef4b0 AP |
1523 | static void check_apply_cts_event_workaround(struct uart_amba_port *uap) |
1524 | { | |
9c4ef4b0 AP |
1525 | if (!uap->vendor->cts_event_workaround) |
1526 | return; | |
1527 | ||
1528 | /* workaround to make sure that all bits are unlocked.. */ | |
9f25bc51 | 1529 | pl011_write(0x00, uap, REG_ICR); |
9c4ef4b0 AP |
1530 | |
1531 | /* | |
1532 | * WA: introduce 26ns(1 uart clk) delay before W1C; | |
1533 | * single apb access will incur 2 pclk(133.12Mhz) delay, | |
1534 | * so add 2 dummy reads | |
1535 | */ | |
94345aee XW |
1536 | pl011_read(uap, REG_ICR); |
1537 | pl011_read(uap, REG_ICR); | |
9c4ef4b0 AP |
1538 | } |
1539 | ||
7d12e780 | 1540 | static irqreturn_t pl011_int(int irq, void *dev_id) |
1da177e4 LT |
1541 | { |
1542 | struct uart_amba_port *uap = dev_id; | |
963cc981 | 1543 | unsigned long flags; |
1da177e4 LT |
1544 | unsigned int status, pass_counter = AMBA_ISR_PASS_LIMIT; |
1545 | int handled = 0; | |
1546 | ||
68ca3e72 | 1547 | uart_port_lock_irqsave(&uap->port, &flags); |
d3a96c94 | 1548 | status = pl011_read(uap, REG_RIS) & uap->im; |
1da177e4 LT |
1549 | if (status) { |
1550 | do { | |
9c4ef4b0 | 1551 | check_apply_cts_event_workaround(uap); |
f11c9841 | 1552 | |
d93ebe0f | 1553 | pl011_write(status & ~(UART011_TXIS | UART011_RTIS | UART011_RXIS), |
9f25bc51 | 1554 | uap, REG_ICR); |
1da177e4 | 1555 | |
d93ebe0f | 1556 | if (status & (UART011_RTIS | UART011_RXIS)) { |
ead76f32 LW |
1557 | if (pl011_dma_rx_running(uap)) |
1558 | pl011_dma_rx_irq(uap); | |
1559 | else | |
1560 | pl011_rx_chars(uap); | |
1561 | } | |
d93ebe0f TL |
1562 | if (status & (UART011_DSRMIS | UART011_DCDMIS | |
1563 | UART011_CTSMIS | UART011_RIMIS)) | |
1da177e4 | 1564 | pl011_modem_status(uap); |
1e84d223 DM |
1565 | if (status & UART011_TXIS) |
1566 | pl011_tx_chars(uap, true); | |
1da177e4 | 1567 | |
4fd0690b | 1568 | if (pass_counter-- == 0) |
1da177e4 LT |
1569 | break; |
1570 | ||
d3a96c94 | 1571 | status = pl011_read(uap, REG_RIS) & uap->im; |
1da177e4 LT |
1572 | } while (status != 0); |
1573 | handled = 1; | |
1574 | } | |
1575 | ||
68ca3e72 | 1576 | uart_port_unlock_irqrestore(&uap->port, flags); |
1da177e4 LT |
1577 | |
1578 | return IRQ_RETVAL(handled); | |
1579 | } | |
1580 | ||
e643f87f | 1581 | static unsigned int pl011_tx_empty(struct uart_port *port) |
1da177e4 | 1582 | { |
a5820c24 DT |
1583 | struct uart_amba_port *uap = |
1584 | container_of(port, struct uart_amba_port, port); | |
d8a4995b CC |
1585 | |
1586 | /* Allow feature register bits to be inverted to work around errata */ | |
1587 | unsigned int status = pl011_read(uap, REG_FR) ^ uap->vendor->inv_fr; | |
1588 | ||
0e125a5f SG |
1589 | return status & (uap->vendor->fr_busy | UART01x_FR_TXFF) ? |
1590 | 0 : TIOCSER_TEMT; | |
1da177e4 LT |
1591 | } |
1592 | ||
dc00f0cc TL |
1593 | static void pl011_maybe_set_bit(bool cond, unsigned int *ptr, unsigned int mask) |
1594 | { | |
1595 | if (cond) | |
1596 | *ptr |= mask; | |
1597 | } | |
1598 | ||
e643f87f | 1599 | static unsigned int pl011_get_mctrl(struct uart_port *port) |
1da177e4 | 1600 | { |
a5820c24 DT |
1601 | struct uart_amba_port *uap = |
1602 | container_of(port, struct uart_amba_port, port); | |
1da177e4 | 1603 | unsigned int result = 0; |
9f25bc51 | 1604 | unsigned int status = pl011_read(uap, REG_FR); |
1da177e4 | 1605 | |
dc00f0cc TL |
1606 | pl011_maybe_set_bit(status & UART01x_FR_DCD, &result, TIOCM_CAR); |
1607 | pl011_maybe_set_bit(status & uap->vendor->fr_dsr, &result, TIOCM_DSR); | |
1608 | pl011_maybe_set_bit(status & uap->vendor->fr_cts, &result, TIOCM_CTS); | |
1609 | pl011_maybe_set_bit(status & uap->vendor->fr_ri, &result, TIOCM_RNG); | |
1da177e4 | 1610 | |
1da177e4 LT |
1611 | return result; |
1612 | } | |
1613 | ||
dc00f0cc TL |
1614 | static void pl011_assign_bit(bool cond, unsigned int *ptr, unsigned int mask) |
1615 | { | |
1616 | if (cond) | |
1617 | *ptr |= mask; | |
1618 | else | |
1619 | *ptr &= ~mask; | |
1620 | } | |
1621 | ||
1da177e4 LT |
1622 | static void pl011_set_mctrl(struct uart_port *port, unsigned int mctrl) |
1623 | { | |
a5820c24 DT |
1624 | struct uart_amba_port *uap = |
1625 | container_of(port, struct uart_amba_port, port); | |
1da177e4 LT |
1626 | unsigned int cr; |
1627 | ||
9f25bc51 | 1628 | cr = pl011_read(uap, REG_CR); |
1da177e4 | 1629 | |
dc00f0cc TL |
1630 | pl011_assign_bit(mctrl & TIOCM_RTS, &cr, UART011_CR_RTS); |
1631 | pl011_assign_bit(mctrl & TIOCM_DTR, &cr, UART011_CR_DTR); | |
1632 | pl011_assign_bit(mctrl & TIOCM_OUT1, &cr, UART011_CR_OUT1); | |
1633 | pl011_assign_bit(mctrl & TIOCM_OUT2, &cr, UART011_CR_OUT2); | |
1634 | pl011_assign_bit(mctrl & TIOCM_LOOP, &cr, UART011_CR_LBE); | |
3b43816f | 1635 | |
2a76fa28 | 1636 | if (port->status & UPSTAT_AUTORTS) { |
3b43816f | 1637 | /* We need to disable auto-RTS if we want to turn RTS off */ |
dc00f0cc | 1638 | pl011_assign_bit(mctrl & TIOCM_RTS, &cr, UART011_CR_RTSEN); |
3b43816f | 1639 | } |
1da177e4 | 1640 | |
9f25bc51 | 1641 | pl011_write(cr, uap, REG_CR); |
1da177e4 LT |
1642 | } |
1643 | ||
1644 | static void pl011_break_ctl(struct uart_port *port, int break_state) | |
1645 | { | |
a5820c24 DT |
1646 | struct uart_amba_port *uap = |
1647 | container_of(port, struct uart_amba_port, port); | |
1da177e4 LT |
1648 | unsigned long flags; |
1649 | unsigned int lcr_h; | |
1650 | ||
68ca3e72 | 1651 | uart_port_lock_irqsave(&uap->port, &flags); |
e4df9a80 | 1652 | lcr_h = pl011_read(uap, REG_LCRH_TX); |
1da177e4 LT |
1653 | if (break_state == -1) |
1654 | lcr_h |= UART01x_LCRH_BRK; | |
1655 | else | |
1656 | lcr_h &= ~UART01x_LCRH_BRK; | |
e4df9a80 | 1657 | pl011_write(lcr_h, uap, REG_LCRH_TX); |
68ca3e72 | 1658 | uart_port_unlock_irqrestore(&uap->port, flags); |
1da177e4 LT |
1659 | } |
1660 | ||
84b5ae15 | 1661 | #ifdef CONFIG_CONSOLE_POLL |
5c8124a0 AV |
1662 | |
1663 | static void pl011_quiesce_irqs(struct uart_port *port) | |
1664 | { | |
a5820c24 DT |
1665 | struct uart_amba_port *uap = |
1666 | container_of(port, struct uart_amba_port, port); | |
5c8124a0 | 1667 | |
9f25bc51 | 1668 | pl011_write(pl011_read(uap, REG_MIS), uap, REG_ICR); |
5c8124a0 AV |
1669 | /* |
1670 | * There is no way to clear TXIM as this is "ready to transmit IRQ", so | |
1671 | * we simply mask it. start_tx() will unmask it. | |
1672 | * | |
1673 | * Note we can race with start_tx(), and if the race happens, the | |
1674 | * polling user might get another interrupt just after we clear it. | |
1675 | * But it should be OK and can happen even w/o the race, e.g. | |
1676 | * controller immediately got some new data and raised the IRQ. | |
1677 | * | |
1678 | * And whoever uses polling routines assumes that it manages the device | |
1679 | * (including tx queue), so we're also fine with start_tx()'s caller | |
1680 | * side. | |
1681 | */ | |
9f25bc51 RK |
1682 | pl011_write(pl011_read(uap, REG_IMSC) & ~UART011_TXIM, uap, |
1683 | REG_IMSC); | |
5c8124a0 AV |
1684 | } |
1685 | ||
e643f87f | 1686 | static int pl011_get_poll_char(struct uart_port *port) |
84b5ae15 | 1687 | { |
a5820c24 DT |
1688 | struct uart_amba_port *uap = |
1689 | container_of(port, struct uart_amba_port, port); | |
84b5ae15 JW |
1690 | unsigned int status; |
1691 | ||
5c8124a0 AV |
1692 | /* |
1693 | * The caller might need IRQs lowered, e.g. if used with KDB NMI | |
1694 | * debugger. | |
1695 | */ | |
1696 | pl011_quiesce_irqs(port); | |
1697 | ||
9f25bc51 | 1698 | status = pl011_read(uap, REG_FR); |
f5316b4a JW |
1699 | if (status & UART01x_FR_RXFE) |
1700 | return NO_POLL_CHAR; | |
84b5ae15 | 1701 | |
9f25bc51 | 1702 | return pl011_read(uap, REG_DR); |
84b5ae15 JW |
1703 | } |
1704 | ||
d93ebe0f | 1705 | static void pl011_put_poll_char(struct uart_port *port, unsigned char ch) |
84b5ae15 | 1706 | { |
a5820c24 DT |
1707 | struct uart_amba_port *uap = |
1708 | container_of(port, struct uart_amba_port, port); | |
84b5ae15 | 1709 | |
9f25bc51 | 1710 | while (pl011_read(uap, REG_FR) & UART01x_FR_TXFF) |
2f2fd089 | 1711 | cpu_relax(); |
84b5ae15 | 1712 | |
9f25bc51 | 1713 | pl011_write(ch, uap, REG_DR); |
84b5ae15 JW |
1714 | } |
1715 | ||
1716 | #endif /* CONFIG_CONSOLE_POLL */ | |
1717 | ||
b3564c2c | 1718 | static int pl011_hwinit(struct uart_port *port) |
1da177e4 | 1719 | { |
a5820c24 DT |
1720 | struct uart_amba_port *uap = |
1721 | container_of(port, struct uart_amba_port, port); | |
1da177e4 LT |
1722 | int retval; |
1723 | ||
78d80c5a | 1724 | /* Optionaly enable pins to be muxed in and configured */ |
2b996fc5 | 1725 | pinctrl_pm_select_default_state(port->dev); |
78d80c5a | 1726 | |
1da177e4 LT |
1727 | /* |
1728 | * Try to enable the clock producer. | |
1729 | */ | |
1c4c4394 | 1730 | retval = clk_prepare_enable(uap->clk); |
1da177e4 | 1731 | if (retval) |
7f6d942a | 1732 | return retval; |
1da177e4 LT |
1733 | |
1734 | uap->port.uartclk = clk_get_rate(uap->clk); | |
1735 | ||
9b96fbac | 1736 | /* Clear pending error and receive interrupts */ |
75836339 RK |
1737 | pl011_write(UART011_OEIS | UART011_BEIS | UART011_PEIS | |
1738 | UART011_FEIS | UART011_RTIS | UART011_RXIS, | |
9f25bc51 | 1739 | uap, REG_ICR); |
9b96fbac | 1740 | |
b3564c2c AV |
1741 | /* |
1742 | * Save interrupts enable mask, and enable RX interrupts in case if | |
1743 | * the interrupt is used for NMI entry. | |
1744 | */ | |
9f25bc51 RK |
1745 | uap->im = pl011_read(uap, REG_IMSC); |
1746 | pl011_write(UART011_RTIM | UART011_RXIM, uap, REG_IMSC); | |
b3564c2c | 1747 | |
574de559 | 1748 | if (dev_get_platdata(uap->port.dev)) { |
b3564c2c AV |
1749 | struct amba_pl011_data *plat; |
1750 | ||
574de559 | 1751 | plat = dev_get_platdata(uap->port.dev); |
b3564c2c AV |
1752 | if (plat->init) |
1753 | plat->init(); | |
1754 | } | |
1755 | return 0; | |
b3564c2c AV |
1756 | } |
1757 | ||
7fe9a5a9 RK |
1758 | static bool pl011_split_lcrh(const struct uart_amba_port *uap) |
1759 | { | |
e4df9a80 RK |
1760 | return pl011_reg_to_offset(uap, REG_LCRH_RX) != |
1761 | pl011_reg_to_offset(uap, REG_LCRH_TX); | |
7fe9a5a9 RK |
1762 | } |
1763 | ||
b60f2f66 JM |
1764 | static void pl011_write_lcr_h(struct uart_amba_port *uap, unsigned int lcr_h) |
1765 | { | |
e4df9a80 | 1766 | pl011_write(lcr_h, uap, REG_LCRH_RX); |
7fe9a5a9 | 1767 | if (pl011_split_lcrh(uap)) { |
b60f2f66 JM |
1768 | int i; |
1769 | /* | |
1770 | * Wait 10 PCLKs before writing LCRH_TX register, | |
1771 | * to get this delay write read only register 10 times | |
1772 | */ | |
1773 | for (i = 0; i < 10; ++i) | |
9f25bc51 | 1774 | pl011_write(0xff, uap, REG_MIS); |
e4df9a80 | 1775 | pl011_write(lcr_h, uap, REG_LCRH_TX); |
b60f2f66 JM |
1776 | } |
1777 | } | |
1778 | ||
867b8e8e AP |
1779 | static int pl011_allocate_irq(struct uart_amba_port *uap) |
1780 | { | |
9f25bc51 | 1781 | pl011_write(uap->im, uap, REG_IMSC); |
867b8e8e | 1782 | |
94560f61 | 1783 | return request_irq(uap->port.irq, pl011_int, IRQF_SHARED, "uart-pl011", uap); |
867b8e8e AP |
1784 | } |
1785 | ||
1786 | /* | |
1787 | * Enable interrupts, only timeouts when using DMA | |
1788 | * if initial RX DMA job failed, start in interrupt mode | |
1789 | * as well. | |
1790 | */ | |
1791 | static void pl011_enable_interrupts(struct uart_amba_port *uap) | |
1792 | { | |
211565b1 | 1793 | unsigned long flags; |
4a7e625c DM |
1794 | unsigned int i; |
1795 | ||
68ca3e72 | 1796 | uart_port_lock_irqsave(&uap->port, &flags); |
867b8e8e AP |
1797 | |
1798 | /* Clear out any spuriously appearing RX interrupts */ | |
9f25bc51 | 1799 | pl011_write(UART011_RTIS | UART011_RXIS, uap, REG_ICR); |
4a7e625c DM |
1800 | |
1801 | /* | |
1802 | * RXIS is asserted only when the RX FIFO transitions from below | |
1803 | * to above the trigger threshold. If the RX FIFO is already | |
1804 | * full to the threshold this can't happen and RXIS will now be | |
1805 | * stuck off. Drain the RX FIFO explicitly to fix this: | |
1806 | */ | |
1807 | for (i = 0; i < uap->fifosize * 2; ++i) { | |
1808 | if (pl011_read(uap, REG_FR) & UART01x_FR_RXFE) | |
1809 | break; | |
1810 | ||
1811 | pl011_read(uap, REG_DR); | |
1812 | } | |
1813 | ||
867b8e8e AP |
1814 | uap->im = UART011_RTIM; |
1815 | if (!pl011_dma_rx_running(uap)) | |
1816 | uap->im |= UART011_RXIM; | |
9f25bc51 | 1817 | pl011_write(uap->im, uap, REG_IMSC); |
68ca3e72 | 1818 | uart_port_unlock_irqrestore(&uap->port, flags); |
211565b1 IJ |
1819 | } |
1820 | ||
1821 | static void pl011_unthrottle_rx(struct uart_port *port) | |
1822 | { | |
1823 | struct uart_amba_port *uap = container_of(port, struct uart_amba_port, port); | |
032d5a71 | 1824 | unsigned long flags; |
211565b1 | 1825 | |
68ca3e72 | 1826 | uart_port_lock_irqsave(&uap->port, &flags); |
032d5a71 | 1827 | |
1828 | uap->im = UART011_RTIM; | |
1829 | if (!pl011_dma_rx_running(uap)) | |
1830 | uap->im |= UART011_RXIM; | |
1831 | ||
1832 | pl011_write(uap->im, uap, REG_IMSC); | |
1833 | ||
68ca3e72 | 1834 | uart_port_unlock_irqrestore(&uap->port, flags); |
867b8e8e AP |
1835 | } |
1836 | ||
b3564c2c AV |
1837 | static int pl011_startup(struct uart_port *port) |
1838 | { | |
a5820c24 DT |
1839 | struct uart_amba_port *uap = |
1840 | container_of(port, struct uart_amba_port, port); | |
734745ca | 1841 | unsigned int cr; |
b3564c2c AV |
1842 | int retval; |
1843 | ||
1844 | retval = pl011_hwinit(port); | |
1845 | if (retval) | |
1846 | goto clk_dis; | |
1847 | ||
867b8e8e | 1848 | retval = pl011_allocate_irq(uap); |
1da177e4 LT |
1849 | if (retval) |
1850 | goto clk_dis; | |
1851 | ||
9f25bc51 | 1852 | pl011_write(uap->vendor->ifls, uap, REG_IFLS); |
1da177e4 | 1853 | |
68ca3e72 | 1854 | uart_port_lock_irq(&uap->port); |
570d2910 | 1855 | |
49a80424 LW |
1856 | cr = pl011_read(uap, REG_CR); |
1857 | cr &= UART011_CR_RTS | UART011_CR_DTR; | |
8d479237 LS |
1858 | cr |= UART01x_CR_UARTEN | UART011_CR_RXE; |
1859 | ||
2dd8a74f | 1860 | if (!(port->rs485.flags & SER_RS485_ENABLED)) |
8d479237 | 1861 | cr |= UART011_CR_TXE; |
8d479237 | 1862 | |
9f25bc51 | 1863 | pl011_write(cr, uap, REG_CR); |
1da177e4 | 1864 | |
68ca3e72 | 1865 | uart_port_unlock_irq(&uap->port); |
fe433907 | 1866 | |
1da177e4 LT |
1867 | /* |
1868 | * initialise the old status of the modem signals | |
1869 | */ | |
9f25bc51 | 1870 | uap->old_status = pl011_read(uap, REG_FR) & UART01x_FR_MODEM_ANY; |
1da177e4 | 1871 | |
68b65f73 RK |
1872 | /* Startup DMA */ |
1873 | pl011_dma_startup(uap); | |
1874 | ||
867b8e8e | 1875 | pl011_enable_interrupts(uap); |
1da177e4 LT |
1876 | |
1877 | return 0; | |
1878 | ||
1879 | clk_dis: | |
1c4c4394 | 1880 | clk_disable_unprepare(uap->clk); |
1da177e4 LT |
1881 | return retval; |
1882 | } | |
1883 | ||
0dd1e247 AP |
1884 | static int sbsa_uart_startup(struct uart_port *port) |
1885 | { | |
1886 | struct uart_amba_port *uap = | |
1887 | container_of(port, struct uart_amba_port, port); | |
1888 | int retval; | |
1889 | ||
1890 | retval = pl011_hwinit(port); | |
1891 | if (retval) | |
1892 | return retval; | |
1893 | ||
1894 | retval = pl011_allocate_irq(uap); | |
1895 | if (retval) | |
1896 | return retval; | |
1897 | ||
1898 | /* The SBSA UART does not support any modem status lines. */ | |
1899 | uap->old_status = 0; | |
1900 | ||
1901 | pl011_enable_interrupts(uap); | |
1902 | ||
1903 | return 0; | |
1904 | } | |
1905 | ||
d93ebe0f | 1906 | static void pl011_shutdown_channel(struct uart_amba_port *uap, unsigned int lcrh) |
ec489aa8 | 1907 | { |
d93ebe0f | 1908 | unsigned long val; |
ec489aa8 | 1909 | |
d93ebe0f TL |
1910 | val = pl011_read(uap, lcrh); |
1911 | val &= ~(UART01x_LCRH_BRK | UART01x_LCRH_FEN); | |
1912 | pl011_write(val, uap, lcrh); | |
ec489aa8 LW |
1913 | } |
1914 | ||
95166a3f AP |
1915 | /* |
1916 | * disable the port. It should not disable RTS and DTR. | |
1917 | * Also RTS and DTR state should be preserved to restore | |
1918 | * it during startup(). | |
1919 | */ | |
1920 | static void pl011_disable_uart(struct uart_amba_port *uap) | |
1da177e4 | 1921 | { |
d8d8ffa4 | 1922 | unsigned int cr; |
1da177e4 | 1923 | |
2a76fa28 | 1924 | uap->port.status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS); |
68ca3e72 | 1925 | uart_port_lock_irq(&uap->port); |
9f25bc51 | 1926 | cr = pl011_read(uap, REG_CR); |
d8d8ffa4 SKS |
1927 | cr &= UART011_CR_RTS | UART011_CR_DTR; |
1928 | cr |= UART01x_CR_UARTEN | UART011_CR_TXE; | |
9f25bc51 | 1929 | pl011_write(cr, uap, REG_CR); |
68ca3e72 | 1930 | uart_port_unlock_irq(&uap->port); |
1da177e4 LT |
1931 | |
1932 | /* | |
1933 | * disable break condition and fifos | |
1934 | */ | |
e4df9a80 | 1935 | pl011_shutdown_channel(uap, REG_LCRH_RX); |
7fe9a5a9 | 1936 | if (pl011_split_lcrh(uap)) |
e4df9a80 | 1937 | pl011_shutdown_channel(uap, REG_LCRH_TX); |
95166a3f AP |
1938 | } |
1939 | ||
1940 | static void pl011_disable_interrupts(struct uart_amba_port *uap) | |
1941 | { | |
68ca3e72 | 1942 | uart_port_lock_irq(&uap->port); |
95166a3f AP |
1943 | |
1944 | /* mask all interrupts and clear all pending ones */ | |
1945 | uap->im = 0; | |
9f25bc51 RK |
1946 | pl011_write(uap->im, uap, REG_IMSC); |
1947 | pl011_write(0xffff, uap, REG_ICR); | |
95166a3f | 1948 | |
68ca3e72 | 1949 | uart_port_unlock_irq(&uap->port); |
95166a3f AP |
1950 | } |
1951 | ||
1952 | static void pl011_shutdown(struct uart_port *port) | |
1953 | { | |
1954 | struct uart_amba_port *uap = | |
1955 | container_of(port, struct uart_amba_port, port); | |
1956 | ||
1957 | pl011_disable_interrupts(uap); | |
1958 | ||
1959 | pl011_dma_shutdown(uap); | |
1960 | ||
8d479237 LS |
1961 | if ((port->rs485.flags & SER_RS485_ENABLED) && uap->rs485_tx_started) |
1962 | pl011_rs485_tx_stop(uap); | |
1963 | ||
94560f61 | 1964 | free_irq(uap->port.irq, uap); |
95166a3f AP |
1965 | |
1966 | pl011_disable_uart(uap); | |
1da177e4 LT |
1967 | |
1968 | /* | |
1969 | * Shut down the clock producer | |
1970 | */ | |
1c4c4394 | 1971 | clk_disable_unprepare(uap->clk); |
78d80c5a | 1972 | /* Optionally let pins go into sleep states */ |
2b996fc5 | 1973 | pinctrl_pm_select_sleep_state(port->dev); |
c16d51a3 | 1974 | |
574de559 | 1975 | if (dev_get_platdata(uap->port.dev)) { |
c16d51a3 SKS |
1976 | struct amba_pl011_data *plat; |
1977 | ||
574de559 | 1978 | plat = dev_get_platdata(uap->port.dev); |
c16d51a3 SKS |
1979 | if (plat->exit) |
1980 | plat->exit(); | |
1981 | } | |
1982 | ||
36f339d1 PH |
1983 | if (uap->port.ops->flush_buffer) |
1984 | uap->port.ops->flush_buffer(port); | |
1da177e4 LT |
1985 | } |
1986 | ||
0dd1e247 AP |
1987 | static void sbsa_uart_shutdown(struct uart_port *port) |
1988 | { | |
1989 | struct uart_amba_port *uap = | |
1990 | container_of(port, struct uart_amba_port, port); | |
1991 | ||
1992 | pl011_disable_interrupts(uap); | |
1993 | ||
94560f61 | 1994 | free_irq(uap->port.irq, uap); |
0dd1e247 AP |
1995 | |
1996 | if (uap->port.ops->flush_buffer) | |
1997 | uap->port.ops->flush_buffer(port); | |
1998 | } | |
1999 | ||
ef5a9358 AP |
2000 | static void |
2001 | pl011_setup_status_masks(struct uart_port *port, struct ktermios *termios) | |
2002 | { | |
2003 | port->read_status_mask = UART011_DR_OE | 255; | |
2004 | if (termios->c_iflag & INPCK) | |
2005 | port->read_status_mask |= UART011_DR_FE | UART011_DR_PE; | |
2006 | if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) | |
2007 | port->read_status_mask |= UART011_DR_BE; | |
2008 | ||
2009 | /* | |
2010 | * Characters to ignore | |
2011 | */ | |
2012 | port->ignore_status_mask = 0; | |
2013 | if (termios->c_iflag & IGNPAR) | |
2014 | port->ignore_status_mask |= UART011_DR_FE | UART011_DR_PE; | |
2015 | if (termios->c_iflag & IGNBRK) { | |
2016 | port->ignore_status_mask |= UART011_DR_BE; | |
2017 | /* | |
2018 | * If we're ignoring parity and break indicators, | |
2019 | * ignore overruns too (for real raw support). | |
2020 | */ | |
2021 | if (termios->c_iflag & IGNPAR) | |
2022 | port->ignore_status_mask |= UART011_DR_OE; | |
2023 | } | |
2024 | ||
2025 | /* | |
2026 | * Ignore all characters if CREAD is not set. | |
2027 | */ | |
2028 | if ((termios->c_cflag & CREAD) == 0) | |
2029 | port->ignore_status_mask |= UART_DUMMY_DR_RX; | |
2030 | } | |
2031 | ||
1da177e4 | 2032 | static void |
606d099c | 2033 | pl011_set_termios(struct uart_port *port, struct ktermios *termios, |
bec5b814 | 2034 | const struct ktermios *old) |
1da177e4 | 2035 | { |
a5820c24 DT |
2036 | struct uart_amba_port *uap = |
2037 | container_of(port, struct uart_amba_port, port); | |
1da177e4 LT |
2038 | unsigned int lcr_h, old_cr; |
2039 | unsigned long flags; | |
c19f12b5 | 2040 | unsigned int baud, quot, clkdiv; |
8d479237 | 2041 | unsigned int bits; |
c19f12b5 RK |
2042 | |
2043 | if (uap->vendor->oversampling) | |
2044 | clkdiv = 8; | |
2045 | else | |
2046 | clkdiv = 16; | |
1da177e4 LT |
2047 | |
2048 | /* | |
2049 | * Ask the core to calculate the divisor for us. | |
2050 | */ | |
ac3e3fb4 | 2051 | baud = uart_get_baud_rate(port, termios, old, 0, |
c19f12b5 | 2052 | port->uartclk / clkdiv); |
89fa28db | 2053 | #ifdef CONFIG_DMA_ENGINE |
cb06ff10 CM |
2054 | /* |
2055 | * Adjust RX DMA polling rate with baud rate if not specified. | |
2056 | */ | |
2057 | if (uap->dmarx.auto_poll_rate) | |
2058 | uap->dmarx.poll_rate = DIV_ROUND_UP(10000000, baud); | |
89fa28db | 2059 | #endif |
ac3e3fb4 | 2060 | |
d93ebe0f | 2061 | if (baud > port->uartclk / 16) |
ac3e3fb4 LW |
2062 | quot = DIV_ROUND_CLOSEST(port->uartclk * 8, baud); |
2063 | else | |
2064 | quot = DIV_ROUND_CLOSEST(port->uartclk * 4, baud); | |
1da177e4 LT |
2065 | |
2066 | switch (termios->c_cflag & CSIZE) { | |
2067 | case CS5: | |
2068 | lcr_h = UART01x_LCRH_WLEN_5; | |
2069 | break; | |
2070 | case CS6: | |
2071 | lcr_h = UART01x_LCRH_WLEN_6; | |
2072 | break; | |
2073 | case CS7: | |
2074 | lcr_h = UART01x_LCRH_WLEN_7; | |
2075 | break; | |
2076 | default: // CS8 | |
2077 | lcr_h = UART01x_LCRH_WLEN_8; | |
2078 | break; | |
2079 | } | |
2080 | if (termios->c_cflag & CSTOPB) | |
2081 | lcr_h |= UART01x_LCRH_STP2; | |
2082 | if (termios->c_cflag & PARENB) { | |
2083 | lcr_h |= UART01x_LCRH_PEN; | |
2084 | if (!(termios->c_cflag & PARODD)) | |
2085 | lcr_h |= UART01x_LCRH_EPS; | |
bb70002c ES |
2086 | if (termios->c_cflag & CMSPAR) |
2087 | lcr_h |= UART011_LCRH_SPS; | |
1da177e4 | 2088 | } |
ffca2b11 | 2089 | if (uap->fifosize > 1) |
1da177e4 LT |
2090 | lcr_h |= UART01x_LCRH_FEN; |
2091 | ||
8d479237 LS |
2092 | bits = tty_get_frame_size(termios->c_cflag); |
2093 | ||
68ca3e72 | 2094 | uart_port_lock_irqsave(port, &flags); |
1da177e4 LT |
2095 | |
2096 | /* | |
2097 | * Update the per-port timeout. | |
2098 | */ | |
2099 | uart_update_timeout(port, termios->c_cflag, baud); | |
2100 | ||
8d479237 LS |
2101 | /* |
2102 | * Calculate the approximated time it takes to transmit one character | |
2103 | * with the given baud rate. We use this as the poll interval when we | |
2104 | * wait for the tx queue to empty. | |
2105 | */ | |
0e4deb56 | 2106 | uap->rs485_tx_drain_interval = DIV_ROUND_UP(bits * 1000 * 1000, baud); |
8d479237 | 2107 | |
ef5a9358 | 2108 | pl011_setup_status_masks(port, termios); |
1da177e4 LT |
2109 | |
2110 | if (UART_ENABLE_MS(port, termios->c_cflag)) | |
2111 | pl011_enable_ms(port); | |
2112 | ||
8d479237 LS |
2113 | if (port->rs485.flags & SER_RS485_ENABLED) |
2114 | termios->c_cflag &= ~CRTSCTS; | |
2115 | ||
9f25bc51 | 2116 | old_cr = pl011_read(uap, REG_CR); |
1da177e4 | 2117 | |
3b43816f RV |
2118 | if (termios->c_cflag & CRTSCTS) { |
2119 | if (old_cr & UART011_CR_RTS) | |
2120 | old_cr |= UART011_CR_RTSEN; | |
2121 | ||
2122 | old_cr |= UART011_CR_CTSEN; | |
2a76fa28 | 2123 | port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS; |
3b43816f RV |
2124 | } else { |
2125 | old_cr &= ~(UART011_CR_CTSEN | UART011_CR_RTSEN); | |
2a76fa28 | 2126 | port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS); |
3b43816f RV |
2127 | } |
2128 | ||
c19f12b5 RK |
2129 | if (uap->vendor->oversampling) { |
2130 | if (baud > port->uartclk / 16) | |
ac3e3fb4 LW |
2131 | old_cr |= ST_UART011_CR_OVSFACT; |
2132 | else | |
2133 | old_cr &= ~ST_UART011_CR_OVSFACT; | |
2134 | } | |
2135 | ||
c5dd553b LW |
2136 | /* |
2137 | * Workaround for the ST Micro oversampling variants to | |
2138 | * increase the bitrate slightly, by lowering the divisor, | |
2139 | * to avoid delayed sampling of start bit at high speeds, | |
2140 | * else we see data corruption. | |
2141 | */ | |
2142 | if (uap->vendor->oversampling) { | |
28a7ec8c | 2143 | if (baud >= 3000000 && baud < 3250000 && quot > 1) |
c5dd553b | 2144 | quot -= 1; |
28a7ec8c | 2145 | else if (baud > 3250000 && quot > 2) |
c5dd553b LW |
2146 | quot -= 2; |
2147 | } | |
1da177e4 | 2148 | /* Set baud rate */ |
9f25bc51 RK |
2149 | pl011_write(quot & 0x3f, uap, REG_FBRD); |
2150 | pl011_write(quot >> 6, uap, REG_IBRD); | |
1da177e4 LT |
2151 | |
2152 | /* | |
2153 | * ----------v----------v----------v----------v----- | |
e4df9a80 | 2154 | * NOTE: REG_LCRH_TX and REG_LCRH_RX MUST BE WRITTEN AFTER |
9f25bc51 | 2155 | * REG_FBRD & REG_IBRD. |
1da177e4 LT |
2156 | * ----------^----------^----------^----------^----- |
2157 | */ | |
b60f2f66 | 2158 | pl011_write_lcr_h(uap, lcr_h); |
6d8c1fca HX |
2159 | |
2160 | /* | |
2161 | * Receive was disabled by pl011_disable_uart during shutdown. | |
2162 | * Need to reenable receive if you need to use a tty_driver | |
2163 | * returns from tty_find_polling_driver() after a port shutdown. | |
2164 | */ | |
2165 | old_cr |= UART011_CR_RXE; | |
9f25bc51 | 2166 | pl011_write(old_cr, uap, REG_CR); |
1da177e4 | 2167 | |
68ca3e72 | 2168 | uart_port_unlock_irqrestore(port, flags); |
1da177e4 LT |
2169 | } |
2170 | ||
0dd1e247 AP |
2171 | static void |
2172 | sbsa_uart_set_termios(struct uart_port *port, struct ktermios *termios, | |
bec5b814 | 2173 | const struct ktermios *old) |
0dd1e247 AP |
2174 | { |
2175 | struct uart_amba_port *uap = | |
2176 | container_of(port, struct uart_amba_port, port); | |
2177 | unsigned long flags; | |
2178 | ||
2179 | tty_termios_encode_baud_rate(termios, uap->fixed_baud, uap->fixed_baud); | |
2180 | ||
2181 | /* The SBSA UART only supports 8n1 without hardware flow control. */ | |
2182 | termios->c_cflag &= ~(CSIZE | CSTOPB | PARENB | PARODD); | |
2183 | termios->c_cflag &= ~(CMSPAR | CRTSCTS); | |
2184 | termios->c_cflag |= CS8 | CLOCAL; | |
2185 | ||
68ca3e72 | 2186 | uart_port_lock_irqsave(port, &flags); |
0dd1e247 AP |
2187 | uart_update_timeout(port, CS8, uap->fixed_baud); |
2188 | pl011_setup_status_masks(port, termios); | |
68ca3e72 | 2189 | uart_port_unlock_irqrestore(port, flags); |
0dd1e247 AP |
2190 | } |
2191 | ||
1da177e4 LT |
2192 | static const char *pl011_type(struct uart_port *port) |
2193 | { | |
a5820c24 DT |
2194 | struct uart_amba_port *uap = |
2195 | container_of(port, struct uart_amba_port, port); | |
e8a7ba86 | 2196 | return uap->port.type == PORT_AMBA ? uap->type : NULL; |
1da177e4 LT |
2197 | } |
2198 | ||
1da177e4 LT |
2199 | /* |
2200 | * Configure/autoconfigure the port. | |
2201 | */ | |
e643f87f | 2202 | static void pl011_config_port(struct uart_port *port, int flags) |
1da177e4 | 2203 | { |
d1180405 | 2204 | if (flags & UART_CONFIG_TYPE) |
1da177e4 | 2205 | port->type = PORT_AMBA; |
1da177e4 LT |
2206 | } |
2207 | ||
2208 | /* | |
2209 | * verify the new serial_struct (for TIOCSSERIAL). | |
2210 | */ | |
e643f87f | 2211 | static int pl011_verify_port(struct uart_port *port, struct serial_struct *ser) |
1da177e4 LT |
2212 | { |
2213 | int ret = 0; | |
d93ebe0f | 2214 | |
1da177e4 LT |
2215 | if (ser->type != PORT_UNKNOWN && ser->type != PORT_AMBA) |
2216 | ret = -EINVAL; | |
a62c4133 | 2217 | if (ser->irq < 0 || ser->irq >= nr_irqs) |
1da177e4 LT |
2218 | ret = -EINVAL; |
2219 | if (ser->baud_base < 9600) | |
2220 | ret = -EINVAL; | |
d93ebe0f | 2221 | if (port->mapbase != (unsigned long)ser->iomem_base) |
d1180405 | 2222 | ret = -EINVAL; |
1da177e4 LT |
2223 | return ret; |
2224 | } | |
2225 | ||
ae50bb27 | 2226 | static int pl011_rs485_config(struct uart_port *port, struct ktermios *termios, |
8d479237 LS |
2227 | struct serial_rs485 *rs485) |
2228 | { | |
2229 | struct uart_amba_port *uap = | |
2230 | container_of(port, struct uart_amba_port, port); | |
2231 | ||
8d479237 LS |
2232 | if (port->rs485.flags & SER_RS485_ENABLED) |
2233 | pl011_rs485_tx_stop(uap); | |
2234 | ||
8d479237 | 2235 | /* Make sure auto RTS is disabled */ |
a9efa452 | 2236 | if (rs485->flags & SER_RS485_ENABLED) { |
8d479237 LS |
2237 | u32 cr = pl011_read(uap, REG_CR); |
2238 | ||
2239 | cr &= ~UART011_CR_RTSEN; | |
2240 | pl011_write(cr, uap, REG_CR); | |
2241 | port->status &= ~UPSTAT_AUTORTS; | |
2242 | } | |
2243 | ||
2244 | return 0; | |
2245 | } | |
2246 | ||
2331e068 | 2247 | static const struct uart_ops amba_pl011_pops = { |
e643f87f | 2248 | .tx_empty = pl011_tx_empty, |
1da177e4 | 2249 | .set_mctrl = pl011_set_mctrl, |
e643f87f | 2250 | .get_mctrl = pl011_get_mctrl, |
1da177e4 LT |
2251 | .stop_tx = pl011_stop_tx, |
2252 | .start_tx = pl011_start_tx, | |
2253 | .stop_rx = pl011_stop_rx, | |
211565b1 IJ |
2254 | .throttle = pl011_throttle_rx, |
2255 | .unthrottle = pl011_unthrottle_rx, | |
1da177e4 LT |
2256 | .enable_ms = pl011_enable_ms, |
2257 | .break_ctl = pl011_break_ctl, | |
2258 | .startup = pl011_startup, | |
2259 | .shutdown = pl011_shutdown, | |
68b65f73 | 2260 | .flush_buffer = pl011_dma_flush_buffer, |
1da177e4 LT |
2261 | .set_termios = pl011_set_termios, |
2262 | .type = pl011_type, | |
e643f87f LW |
2263 | .config_port = pl011_config_port, |
2264 | .verify_port = pl011_verify_port, | |
84b5ae15 | 2265 | #ifdef CONFIG_CONSOLE_POLL |
b3564c2c | 2266 | .poll_init = pl011_hwinit, |
e643f87f LW |
2267 | .poll_get_char = pl011_get_poll_char, |
2268 | .poll_put_char = pl011_put_poll_char, | |
84b5ae15 | 2269 | #endif |
1da177e4 LT |
2270 | }; |
2271 | ||
0dd1e247 AP |
2272 | static void sbsa_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) |
2273 | { | |
2274 | } | |
2275 | ||
2276 | static unsigned int sbsa_uart_get_mctrl(struct uart_port *port) | |
2277 | { | |
2278 | return 0; | |
2279 | } | |
2280 | ||
2281 | static const struct uart_ops sbsa_uart_pops = { | |
2282 | .tx_empty = pl011_tx_empty, | |
2283 | .set_mctrl = sbsa_uart_set_mctrl, | |
2284 | .get_mctrl = sbsa_uart_get_mctrl, | |
2285 | .stop_tx = pl011_stop_tx, | |
2286 | .start_tx = pl011_start_tx, | |
2287 | .stop_rx = pl011_stop_rx, | |
2288 | .startup = sbsa_uart_startup, | |
2289 | .shutdown = sbsa_uart_shutdown, | |
2290 | .set_termios = sbsa_uart_set_termios, | |
2291 | .type = pl011_type, | |
0dd1e247 AP |
2292 | .config_port = pl011_config_port, |
2293 | .verify_port = pl011_verify_port, | |
2294 | #ifdef CONFIG_CONSOLE_POLL | |
2295 | .poll_init = pl011_hwinit, | |
2296 | .poll_get_char = pl011_get_poll_char, | |
2297 | .poll_put_char = pl011_put_poll_char, | |
2298 | #endif | |
2299 | }; | |
2300 | ||
1da177e4 LT |
2301 | static struct uart_amba_port *amba_ports[UART_NR]; |
2302 | ||
2303 | #ifdef CONFIG_SERIAL_AMBA_PL011_CONSOLE | |
2304 | ||
3f8bab17 | 2305 | static void pl011_console_putchar(struct uart_port *port, unsigned char ch) |
1da177e4 | 2306 | { |
a5820c24 DT |
2307 | struct uart_amba_port *uap = |
2308 | container_of(port, struct uart_amba_port, port); | |
1da177e4 | 2309 | |
9f25bc51 | 2310 | while (pl011_read(uap, REG_FR) & UART01x_FR_TXFF) |
2f2fd089 | 2311 | cpu_relax(); |
9f25bc51 | 2312 | pl011_write(ch, uap, REG_DR); |
1da177e4 LT |
2313 | } |
2314 | ||
2315 | static void | |
2316 | pl011_console_write(struct console *co, const char *s, unsigned int count) | |
2317 | { | |
2318 | struct uart_amba_port *uap = amba_ports[co->index]; | |
2f2fd089 | 2319 | unsigned int old_cr = 0, new_cr; |
ef605fdb RV |
2320 | unsigned long flags; |
2321 | int locked = 1; | |
1da177e4 LT |
2322 | |
2323 | clk_enable(uap->clk); | |
2324 | ||
ef605fdb RV |
2325 | local_irq_save(flags); |
2326 | if (uap->port.sysrq) | |
2327 | locked = 0; | |
2328 | else if (oops_in_progress) | |
68ca3e72 | 2329 | locked = uart_port_trylock(&uap->port); |
ef605fdb | 2330 | else |
68ca3e72 | 2331 | uart_port_lock(&uap->port); |
ef605fdb | 2332 | |
1da177e4 LT |
2333 | /* |
2334 | * First save the CR then disable the interrupts | |
2335 | */ | |
71eec483 | 2336 | if (!uap->vendor->always_enabled) { |
9f25bc51 | 2337 | old_cr = pl011_read(uap, REG_CR); |
71eec483 AP |
2338 | new_cr = old_cr & ~UART011_CR_CTSEN; |
2339 | new_cr |= UART01x_CR_UARTEN | UART011_CR_TXE; | |
9f25bc51 | 2340 | pl011_write(new_cr, uap, REG_CR); |
71eec483 | 2341 | } |
1da177e4 | 2342 | |
d358788f | 2343 | uart_console_write(&uap->port, s, count, pl011_console_putchar); |
1da177e4 LT |
2344 | |
2345 | /* | |
d8a4995b CC |
2346 | * Finally, wait for transmitter to become empty and restore the |
2347 | * TCR. Allow feature register bits to be inverted to work around | |
2348 | * errata. | |
1da177e4 | 2349 | */ |
d8a4995b CC |
2350 | while ((pl011_read(uap, REG_FR) ^ uap->vendor->inv_fr) |
2351 | & uap->vendor->fr_busy) | |
2f2fd089 | 2352 | cpu_relax(); |
71eec483 | 2353 | if (!uap->vendor->always_enabled) |
9f25bc51 | 2354 | pl011_write(old_cr, uap, REG_CR); |
1da177e4 | 2355 | |
ef605fdb | 2356 | if (locked) |
68ca3e72 | 2357 | uart_port_unlock(&uap->port); |
ef605fdb RV |
2358 | local_irq_restore(flags); |
2359 | ||
1da177e4 LT |
2360 | clk_disable(uap->clk); |
2361 | } | |
2362 | ||
27afac93 LW |
2363 | static void pl011_console_get_options(struct uart_amba_port *uap, int *baud, |
2364 | int *parity, int *bits) | |
1da177e4 | 2365 | { |
8ff87406 | 2366 | unsigned int lcr_h, ibrd, fbrd; |
1da177e4 | 2367 | |
8ff87406 TL |
2368 | if (!(pl011_read(uap, REG_CR) & UART01x_CR_UARTEN)) |
2369 | return; | |
1da177e4 | 2370 | |
8ff87406 | 2371 | lcr_h = pl011_read(uap, REG_LCRH_TX); |
1da177e4 | 2372 | |
8ff87406 TL |
2373 | *parity = 'n'; |
2374 | if (lcr_h & UART01x_LCRH_PEN) { | |
2375 | if (lcr_h & UART01x_LCRH_EPS) | |
2376 | *parity = 'e'; | |
1da177e4 | 2377 | else |
8ff87406 TL |
2378 | *parity = 'o'; |
2379 | } | |
1da177e4 | 2380 | |
8ff87406 TL |
2381 | if ((lcr_h & 0x60) == UART01x_LCRH_WLEN_7) |
2382 | *bits = 7; | |
2383 | else | |
2384 | *bits = 8; | |
1da177e4 | 2385 | |
8ff87406 TL |
2386 | ibrd = pl011_read(uap, REG_IBRD); |
2387 | fbrd = pl011_read(uap, REG_FBRD); | |
ac3e3fb4 | 2388 | |
8ff87406 TL |
2389 | *baud = uap->port.uartclk * 4 / (64 * ibrd + fbrd); |
2390 | ||
2391 | if (uap->vendor->oversampling && | |
2392 | (pl011_read(uap, REG_CR) & ST_UART011_CR_OVSFACT)) | |
2393 | *baud *= 2; | |
1da177e4 LT |
2394 | } |
2395 | ||
27afac93 | 2396 | static int pl011_console_setup(struct console *co, char *options) |
1da177e4 LT |
2397 | { |
2398 | struct uart_amba_port *uap; | |
2399 | int baud = 38400; | |
2400 | int bits = 8; | |
2401 | int parity = 'n'; | |
2402 | int flow = 'n'; | |
4b4851c6 | 2403 | int ret; |
1da177e4 LT |
2404 | |
2405 | /* | |
2406 | * Check whether an invalid uart number has been specified, and | |
2407 | * if so, search for the first available port that does have | |
2408 | * console support. | |
2409 | */ | |
2410 | if (co->index >= UART_NR) | |
2411 | co->index = 0; | |
2412 | uap = amba_ports[co->index]; | |
d28122a5 RK |
2413 | if (!uap) |
2414 | return -ENODEV; | |
1da177e4 | 2415 | |
78d80c5a | 2416 | /* Allow pins to be muxed in and configured */ |
2b996fc5 | 2417 | pinctrl_pm_select_default_state(uap->port.dev); |
78d80c5a | 2418 | |
4b4851c6 RK |
2419 | ret = clk_prepare(uap->clk); |
2420 | if (ret) | |
2421 | return ret; | |
2422 | ||
574de559 | 2423 | if (dev_get_platdata(uap->port.dev)) { |
c16d51a3 SKS |
2424 | struct amba_pl011_data *plat; |
2425 | ||
574de559 | 2426 | plat = dev_get_platdata(uap->port.dev); |
c16d51a3 SKS |
2427 | if (plat->init) |
2428 | plat->init(); | |
2429 | } | |
2430 | ||
1da177e4 LT |
2431 | uap->port.uartclk = clk_get_rate(uap->clk); |
2432 | ||
cefc2d1d AP |
2433 | if (uap->vendor->fixed_options) { |
2434 | baud = uap->fixed_baud; | |
2435 | } else { | |
2436 | if (options) | |
2437 | uart_parse_options(options, | |
2438 | &baud, &parity, &bits, &flow); | |
2439 | else | |
2440 | pl011_console_get_options(uap, &baud, &parity, &bits); | |
2441 | } | |
1da177e4 LT |
2442 | |
2443 | return uart_set_options(&uap->port, co, baud, parity, bits, flow); | |
2444 | } | |
2445 | ||
10879ae5 AM |
2446 | /** |
2447 | * pl011_console_match - non-standard console matching | |
2448 | * @co: registering console | |
2449 | * @name: name from console command line | |
2450 | * @idx: index from console command line | |
2451 | * @options: ptr to option string from console command line | |
2452 | * | |
2453 | * Only attempts to match console command lines of the form: | |
2454 | * console=pl011,mmio|mmio32,<addr>[,<options>] | |
2455 | * console=pl011,0x<addr>[,<options>] | |
2456 | * This form is used to register an initial earlycon boot console and | |
2457 | * replace it with the amba_console at pl011 driver init. | |
2458 | * | |
2459 | * Performs console setup for a match (as required by interface) | |
2460 | * If no <options> are specified, then assume the h/w is already setup. | |
2461 | * | |
2462 | * Returns 0 if console matches; otherwise non-zero to use default matching | |
2463 | */ | |
27afac93 LW |
2464 | static int pl011_console_match(struct console *co, char *name, int idx, |
2465 | char *options) | |
10879ae5 AM |
2466 | { |
2467 | unsigned char iotype; | |
2468 | resource_size_t addr; | |
2469 | int i; | |
2470 | ||
37ef38f3 TT |
2471 | /* |
2472 | * Systems affected by the Qualcomm Technologies QDF2400 E44 erratum | |
2473 | * have a distinct console name, so make sure we check for that. | |
2474 | * The actual implementation of the erratum occurs in the probe | |
2475 | * function. | |
2476 | */ | |
2477 | if ((strcmp(name, "qdf2400_e44") != 0) && (strcmp(name, "pl011") != 0)) | |
10879ae5 AM |
2478 | return -ENODEV; |
2479 | ||
2480 | if (uart_parse_earlycon(options, &iotype, &addr, &options)) | |
2481 | return -ENODEV; | |
2482 | ||
2483 | if (iotype != UPIO_MEM && iotype != UPIO_MEM32) | |
2484 | return -ENODEV; | |
2485 | ||
2486 | /* try to match the port specified on the command line */ | |
2487 | for (i = 0; i < ARRAY_SIZE(amba_ports); i++) { | |
2488 | struct uart_port *port; | |
2489 | ||
2490 | if (!amba_ports[i]) | |
2491 | continue; | |
2492 | ||
2493 | port = &amba_ports[i]->port; | |
2494 | ||
2495 | if (port->mapbase != addr) | |
2496 | continue; | |
2497 | ||
2498 | co->index = i; | |
2499 | port->cons = co; | |
2500 | return pl011_console_setup(co, options); | |
2501 | } | |
2502 | ||
2503 | return -ENODEV; | |
2504 | } | |
2505 | ||
2d93486c | 2506 | static struct uart_driver amba_reg; |
1da177e4 LT |
2507 | static struct console amba_console = { |
2508 | .name = "ttyAMA", | |
2509 | .write = pl011_console_write, | |
2510 | .device = uart_console_device, | |
2511 | .setup = pl011_console_setup, | |
10879ae5 | 2512 | .match = pl011_console_match, |
7951ffc9 | 2513 | .flags = CON_PRINTBUFFER | CON_ANYTIME, |
1da177e4 LT |
2514 | .index = -1, |
2515 | .data = &amba_reg, | |
2516 | }; | |
2517 | ||
2518 | #define AMBA_CONSOLE (&amba_console) | |
0d3c673e | 2519 | |
3f8bab17 | 2520 | static void qdf2400_e44_putc(struct uart_port *port, unsigned char c) |
d8a4995b CC |
2521 | { |
2522 | while (readl(port->membase + UART01x_FR) & UART01x_FR_TXFF) | |
2523 | cpu_relax(); | |
2524 | writel(c, port->membase + UART01x_DR); | |
2525 | while (!(readl(port->membase + UART01x_FR) & UART011_FR_TXFE)) | |
2526 | cpu_relax(); | |
2527 | } | |
2528 | ||
826bd77a | 2529 | static void qdf2400_e44_early_write(struct console *con, const char *s, unsigned int n) |
d8a4995b CC |
2530 | { |
2531 | struct earlycon_device *dev = con->data; | |
2532 | ||
2533 | uart_console_write(&dev->port, s, n, qdf2400_e44_putc); | |
2534 | } | |
2535 | ||
3f8bab17 | 2536 | static void pl011_putc(struct uart_port *port, unsigned char c) |
0d3c673e | 2537 | { |
cdf091ca | 2538 | while (readl(port->membase + UART01x_FR) & UART01x_FR_TXFF) |
2f2fd089 | 2539 | cpu_relax(); |
3b78fae7 TT |
2540 | if (port->iotype == UPIO_MEM32) |
2541 | writel(c, port->membase + UART01x_DR); | |
2542 | else | |
2543 | writeb(c, port->membase + UART01x_DR); | |
e06690bf | 2544 | while (readl(port->membase + UART01x_FR) & UART01x_FR_BUSY) |
2f2fd089 | 2545 | cpu_relax(); |
0d3c673e RH |
2546 | } |
2547 | ||
826bd77a | 2548 | static void pl011_early_write(struct console *con, const char *s, unsigned int n) |
0d3c673e RH |
2549 | { |
2550 | struct earlycon_device *dev = con->data; | |
2551 | ||
2552 | uart_console_write(&dev->port, s, n, pl011_putc); | |
2553 | } | |
2554 | ||
195867ff SG |
2555 | #ifdef CONFIG_CONSOLE_POLL |
2556 | static int pl011_getc(struct uart_port *port) | |
2557 | { | |
2558 | if (readl(port->membase + UART01x_FR) & UART01x_FR_RXFE) | |
2559 | return NO_POLL_CHAR; | |
2560 | ||
2561 | if (port->iotype == UPIO_MEM32) | |
2562 | return readl(port->membase + UART01x_DR); | |
2563 | else | |
2564 | return readb(port->membase + UART01x_DR); | |
2565 | } | |
2566 | ||
2567 | static int pl011_early_read(struct console *con, char *s, unsigned int n) | |
2568 | { | |
2569 | struct earlycon_device *dev = con->data; | |
2570 | int ch, num_read = 0; | |
2571 | ||
2572 | while (num_read < n) { | |
2573 | ch = pl011_getc(&dev->port); | |
2574 | if (ch == NO_POLL_CHAR) | |
2575 | break; | |
2576 | ||
2577 | s[num_read++] = ch; | |
2578 | } | |
2579 | ||
2580 | return num_read; | |
2581 | } | |
2582 | #else | |
2583 | #define pl011_early_read NULL | |
2584 | #endif | |
2585 | ||
e53e597f TT |
2586 | /* |
2587 | * On non-ACPI systems, earlycon is enabled by specifying | |
2588 | * "earlycon=pl011,<address>" on the kernel command line. | |
2589 | * | |
2590 | * On ACPI ARM64 systems, an "early" console is enabled via the SPCR table, | |
2591 | * by specifying only "earlycon" on the command line. Because it requires | |
2592 | * SPCR, the console starts after ACPI is parsed, which is later than a | |
2593 | * traditional early console. | |
2594 | * | |
2595 | * To get the traditional early console that starts before ACPI is parsed, | |
2596 | * specify the full "earlycon=pl011,<address>" option. | |
2597 | */ | |
0d3c673e RH |
2598 | static int __init pl011_early_console_setup(struct earlycon_device *device, |
2599 | const char *opt) | |
2600 | { | |
2601 | if (!device->port.membase) | |
2602 | return -ENODEV; | |
2603 | ||
5a0722b8 | 2604 | device->con->write = pl011_early_write; |
195867ff | 2605 | device->con->read = pl011_early_read; |
e53e597f | 2606 | |
0d3c673e RH |
2607 | return 0; |
2608 | } | |
d93ebe0f | 2609 | |
45e0f0f5 | 2610 | OF_EARLYCON_DECLARE(pl011, "arm,pl011", pl011_early_console_setup); |
d93ebe0f | 2611 | |
fcb32159 | 2612 | OF_EARLYCON_DECLARE(pl011, "arm,sbsa-uart", pl011_early_console_setup); |
5a0722b8 TT |
2613 | |
2614 | /* | |
2615 | * On Qualcomm Datacenter Technologies QDF2400 SOCs affected by | |
2616 | * Erratum 44, traditional earlycon can be enabled by specifying | |
2617 | * "earlycon=qdf2400_e44,<address>". Any options are ignored. | |
2618 | * | |
2619 | * Alternatively, you can just specify "earlycon", and the early console | |
2620 | * will be enabled with the information from the SPCR table. In this | |
2621 | * case, the SPCR code will detect the need for the E44 work-around, | |
2622 | * and set the console name to "qdf2400_e44". | |
2623 | */ | |
2624 | static int __init | |
2625 | qdf2400_e44_early_console_setup(struct earlycon_device *device, | |
2626 | const char *opt) | |
2627 | { | |
2628 | if (!device->port.membase) | |
2629 | return -ENODEV; | |
2630 | ||
2631 | device->con->write = qdf2400_e44_early_write; | |
2632 | return 0; | |
2633 | } | |
d93ebe0f | 2634 | |
5a0722b8 | 2635 | EARLYCON_DECLARE(qdf2400_e44, qdf2400_e44_early_console_setup); |
0d3c673e | 2636 | |
1da177e4 LT |
2637 | #else |
2638 | #define AMBA_CONSOLE NULL | |
2639 | #endif | |
2640 | ||
2641 | static struct uart_driver amba_reg = { | |
2642 | .owner = THIS_MODULE, | |
2643 | .driver_name = "ttyAMA", | |
2644 | .dev_name = "ttyAMA", | |
2645 | .major = SERIAL_AMBA_MAJOR, | |
2646 | .minor = SERIAL_AMBA_MINOR, | |
2647 | .nr = UART_NR, | |
2648 | .cons = AMBA_CONSOLE, | |
2649 | }; | |
2650 | ||
32614aad ML |
2651 | static int pl011_probe_dt_alias(int index, struct device *dev) |
2652 | { | |
2653 | struct device_node *np; | |
826bd77a TL |
2654 | static bool seen_dev_with_alias; |
2655 | static bool seen_dev_without_alias; | |
32614aad ML |
2656 | int ret = index; |
2657 | ||
2658 | if (!IS_ENABLED(CONFIG_OF)) | |
2659 | return ret; | |
2660 | ||
2661 | np = dev->of_node; | |
2662 | if (!np) | |
2663 | return ret; | |
2664 | ||
2665 | ret = of_alias_get_id(np, "serial"); | |
287980e4 | 2666 | if (ret < 0) { |
32614aad ML |
2667 | seen_dev_without_alias = true; |
2668 | ret = index; | |
2669 | } else { | |
2670 | seen_dev_with_alias = true; | |
28a7ec8c | 2671 | if (ret >= ARRAY_SIZE(amba_ports) || amba_ports[ret]) { |
32614aad ML |
2672 | dev_warn(dev, "requested serial port %d not available.\n", ret); |
2673 | ret = index; | |
2674 | } | |
2675 | } | |
2676 | ||
2677 | if (seen_dev_with_alias && seen_dev_without_alias) | |
2678 | dev_warn(dev, "aliased and non-aliased serial devices found in device tree. Serial port enumeration may be unpredictable.\n"); | |
2679 | ||
2680 | return ret; | |
2681 | } | |
2682 | ||
49bb3c86 AP |
2683 | /* unregisters the driver also if no more ports are left */ |
2684 | static void pl011_unregister_port(struct uart_amba_port *uap) | |
2685 | { | |
2686 | int i; | |
2687 | bool busy = false; | |
2688 | ||
2689 | for (i = 0; i < ARRAY_SIZE(amba_ports); i++) { | |
2690 | if (amba_ports[i] == uap) | |
2691 | amba_ports[i] = NULL; | |
2692 | else if (amba_ports[i]) | |
2693 | busy = true; | |
2694 | } | |
2695 | pl011_dma_remove(uap); | |
2696 | if (!busy) | |
2697 | uart_unregister_driver(&amba_reg); | |
2698 | } | |
2699 | ||
3873e2d7 | 2700 | static int pl011_find_free_port(void) |
1da177e4 | 2701 | { |
3873e2d7 | 2702 | int i; |
1da177e4 LT |
2703 | |
2704 | for (i = 0; i < ARRAY_SIZE(amba_ports); i++) | |
28a7ec8c | 2705 | if (!amba_ports[i]) |
3873e2d7 | 2706 | return i; |
1da177e4 | 2707 | |
3873e2d7 AP |
2708 | return -EBUSY; |
2709 | } | |
1da177e4 | 2710 | |
8d479237 LS |
2711 | static int pl011_get_rs485_mode(struct uart_amba_port *uap) |
2712 | { | |
2713 | struct uart_port *port = &uap->port; | |
8d479237 LS |
2714 | int ret; |
2715 | ||
2716 | ret = uart_get_rs485_mode(port); | |
2717 | if (ret) | |
2718 | return ret; | |
2719 | ||
8d479237 LS |
2720 | return 0; |
2721 | } | |
2722 | ||
3873e2d7 AP |
2723 | static int pl011_setup_port(struct device *dev, struct uart_amba_port *uap, |
2724 | struct resource *mmiobase, int index) | |
2725 | { | |
2726 | void __iomem *base; | |
8d479237 | 2727 | int ret; |
32614aad | 2728 | |
3873e2d7 | 2729 | base = devm_ioremap_resource(dev, mmiobase); |
97a60eac KK |
2730 | if (IS_ERR(base)) |
2731 | return PTR_ERR(base); | |
1da177e4 | 2732 | |
3873e2d7 | 2733 | index = pl011_probe_dt_alias(index, dev); |
1da177e4 | 2734 | |
3873e2d7 AP |
2735 | uap->port.dev = dev; |
2736 | uap->port.mapbase = mmiobase->start; | |
1da177e4 | 2737 | uap->port.membase = base; |
ffca2b11 | 2738 | uap->port.fifosize = uap->fifosize; |
5f99fca9 | 2739 | uap->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_AMBA_PL011_CONSOLE); |
1da177e4 | 2740 | uap->port.flags = UPF_BOOT_AUTOCONF; |
3873e2d7 | 2741 | uap->port.line = index; |
1da177e4 | 2742 | |
8d479237 LS |
2743 | ret = pl011_get_rs485_mode(uap); |
2744 | if (ret) | |
2745 | return ret; | |
2746 | ||
3873e2d7 | 2747 | amba_ports[index] = uap; |
c3d8b76f | 2748 | |
3873e2d7 AP |
2749 | return 0; |
2750 | } | |
e8a7ba86 | 2751 | |
3873e2d7 AP |
2752 | static int pl011_register_port(struct uart_amba_port *uap) |
2753 | { | |
89efbe70 | 2754 | int ret, i; |
1da177e4 | 2755 | |
3873e2d7 | 2756 | /* Ensure interrupts from this UART are masked and cleared */ |
9f25bc51 RK |
2757 | pl011_write(0, uap, REG_IMSC); |
2758 | pl011_write(0xffff, uap, REG_ICR); | |
ef2889f7 TB |
2759 | |
2760 | if (!amba_reg.state) { | |
2761 | ret = uart_register_driver(&amba_reg); | |
2762 | if (ret < 0) { | |
3873e2d7 | 2763 | dev_err(uap->port.dev, |
1c9be310 | 2764 | "Failed to register AMBA-PL011 driver\n"); |
89efbe70 LW |
2765 | for (i = 0; i < ARRAY_SIZE(amba_ports); i++) |
2766 | if (amba_ports[i] == uap) | |
2767 | amba_ports[i] = NULL; | |
ef2889f7 TB |
2768 | return ret; |
2769 | } | |
2770 | } | |
2771 | ||
1da177e4 | 2772 | ret = uart_add_one_port(&amba_reg, &uap->port); |
49bb3c86 AP |
2773 | if (ret) |
2774 | pl011_unregister_port(uap); | |
7f6d942a | 2775 | |
1da177e4 LT |
2776 | return ret; |
2777 | } | |
2778 | ||
ebe2cf73 IJ |
2779 | static const struct serial_rs485 pl011_rs485_supported = { |
2780 | .flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND | SER_RS485_RTS_AFTER_SEND | | |
2781 | SER_RS485_RX_DURING_TX, | |
2782 | .delay_rts_before_send = 1, | |
2783 | .delay_rts_after_send = 1, | |
2784 | }; | |
2785 | ||
3873e2d7 AP |
2786 | static int pl011_probe(struct amba_device *dev, const struct amba_id *id) |
2787 | { | |
2788 | struct uart_amba_port *uap; | |
2789 | struct vendor_data *vendor = id->data; | |
2790 | int portnr, ret; | |
81db9e8e | 2791 | u32 val; |
3873e2d7 AP |
2792 | |
2793 | portnr = pl011_find_free_port(); | |
2794 | if (portnr < 0) | |
2795 | return portnr; | |
2796 | ||
2797 | uap = devm_kzalloc(&dev->dev, sizeof(struct uart_amba_port), | |
2798 | GFP_KERNEL); | |
2799 | if (!uap) | |
2800 | return -ENOMEM; | |
2801 | ||
2802 | uap->clk = devm_clk_get(&dev->dev, NULL); | |
2803 | if (IS_ERR(uap->clk)) | |
2804 | return PTR_ERR(uap->clk); | |
2805 | ||
439403bd | 2806 | uap->reg_offset = vendor->reg_offset; |
3873e2d7 | 2807 | uap->vendor = vendor; |
3873e2d7 | 2808 | uap->fifosize = vendor->get_fifosize(dev); |
3b78fae7 | 2809 | uap->port.iotype = vendor->access_32b ? UPIO_MEM32 : UPIO_MEM; |
3873e2d7 AP |
2810 | uap->port.irq = dev->irq[0]; |
2811 | uap->port.ops = &amba_pl011_pops; | |
8d479237 | 2812 | uap->port.rs485_config = pl011_rs485_config; |
0139da50 | 2813 | uap->port.rs485_supported = pl011_rs485_supported; |
3873e2d7 AP |
2814 | snprintf(uap->type, sizeof(uap->type), "PL011 rev%u", amba_rev(dev)); |
2815 | ||
81db9e8e SD |
2816 | if (device_property_read_u32(&dev->dev, "reg-io-width", &val) == 0) { |
2817 | switch (val) { | |
2818 | case 1: | |
2819 | uap->port.iotype = UPIO_MEM; | |
2820 | break; | |
2821 | case 4: | |
2822 | uap->port.iotype = UPIO_MEM32; | |
2823 | break; | |
2824 | default: | |
2825 | dev_warn(&dev->dev, "unsupported reg-io-width (%d)\n", | |
2826 | val); | |
2827 | return -EINVAL; | |
2828 | } | |
2829 | } | |
2830 | ||
3873e2d7 AP |
2831 | ret = pl011_setup_port(&dev->dev, uap, &dev->res, portnr); |
2832 | if (ret) | |
2833 | return ret; | |
2834 | ||
2835 | amba_set_drvdata(dev, uap); | |
2836 | ||
2837 | return pl011_register_port(uap); | |
2838 | } | |
2839 | ||
3fd269e7 | 2840 | static void pl011_remove(struct amba_device *dev) |
1da177e4 LT |
2841 | { |
2842 | struct uart_amba_port *uap = amba_get_drvdata(dev); | |
1da177e4 | 2843 | |
1da177e4 | 2844 | uart_remove_one_port(&amba_reg, &uap->port); |
49bb3c86 | 2845 | pl011_unregister_port(uap); |
1da177e4 LT |
2846 | } |
2847 | ||
d0ce850d UH |
2848 | #ifdef CONFIG_PM_SLEEP |
2849 | static int pl011_suspend(struct device *dev) | |
b736b89f | 2850 | { |
d0ce850d | 2851 | struct uart_amba_port *uap = dev_get_drvdata(dev); |
b736b89f LC |
2852 | |
2853 | if (!uap) | |
2854 | return -EINVAL; | |
2855 | ||
2856 | return uart_suspend_port(&amba_reg, &uap->port); | |
2857 | } | |
2858 | ||
d0ce850d | 2859 | static int pl011_resume(struct device *dev) |
b736b89f | 2860 | { |
d0ce850d | 2861 | struct uart_amba_port *uap = dev_get_drvdata(dev); |
b736b89f LC |
2862 | |
2863 | if (!uap) | |
2864 | return -EINVAL; | |
2865 | ||
2866 | return uart_resume_port(&amba_reg, &uap->port); | |
2867 | } | |
2868 | #endif | |
2869 | ||
d0ce850d UH |
2870 | static SIMPLE_DEV_PM_OPS(pl011_dev_pm_ops, pl011_suspend, pl011_resume); |
2871 | ||
a49a8b9d TL |
2872 | #ifdef CONFIG_ACPI_SPCR_TABLE |
2873 | static void qpdf2400_erratum44_workaround(struct device *dev, | |
2874 | struct uart_amba_port *uap) | |
2875 | { | |
2876 | if (!qdf2400_e44_present) | |
2877 | return; | |
2878 | ||
2879 | dev_info(dev, "working around QDF2400 SoC erratum 44\n"); | |
2880 | uap->vendor = &vendor_qdt_qdf2400_e44; | |
2881 | } | |
2882 | #else | |
2883 | static void qpdf2400_erratum44_workaround(struct device *dev, | |
2884 | struct uart_amba_port *uap) | |
2885 | { /* empty */ } | |
2886 | #endif | |
2887 | ||
0dd1e247 AP |
2888 | static int sbsa_uart_probe(struct platform_device *pdev) |
2889 | { | |
2890 | struct uart_amba_port *uap; | |
2891 | struct resource *r; | |
2892 | int portnr, ret; | |
2893 | int baudrate; | |
2894 | ||
2895 | /* | |
2896 | * Check the mandatory baud rate parameter in the DT node early | |
2897 | * so that we can easily exit with the error. | |
2898 | */ | |
2899 | if (pdev->dev.of_node) { | |
2900 | struct device_node *np = pdev->dev.of_node; | |
2901 | ||
2902 | ret = of_property_read_u32(np, "current-speed", &baudrate); | |
2903 | if (ret) | |
2904 | return ret; | |
2905 | } else { | |
2906 | baudrate = 115200; | |
2907 | } | |
2908 | ||
2909 | portnr = pl011_find_free_port(); | |
2910 | if (portnr < 0) | |
2911 | return portnr; | |
2912 | ||
2913 | uap = devm_kzalloc(&pdev->dev, sizeof(struct uart_amba_port), | |
2914 | GFP_KERNEL); | |
2915 | if (!uap) | |
2916 | return -ENOMEM; | |
2917 | ||
394a9e2c | 2918 | ret = platform_get_irq(pdev, 0); |
1df21786 | 2919 | if (ret < 0) |
394a9e2c | 2920 | return ret; |
394a9e2c JS |
2921 | uap->port.irq = ret; |
2922 | ||
a49a8b9d TL |
2923 | uap->vendor = &vendor_sbsa; |
2924 | qpdf2400_erratum44_workaround(&pdev->dev, uap); | |
37ef38f3 TT |
2925 | |
2926 | uap->reg_offset = uap->vendor->reg_offset; | |
0dd1e247 | 2927 | uap->fifosize = 32; |
37ef38f3 | 2928 | uap->port.iotype = uap->vendor->access_32b ? UPIO_MEM32 : UPIO_MEM; |
0dd1e247 AP |
2929 | uap->port.ops = &sbsa_uart_pops; |
2930 | uap->fixed_baud = baudrate; | |
2931 | ||
2932 | snprintf(uap->type, sizeof(uap->type), "SBSA"); | |
2933 | ||
2934 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
2935 | ||
2936 | ret = pl011_setup_port(&pdev->dev, uap, r, portnr); | |
2937 | if (ret) | |
2938 | return ret; | |
2939 | ||
2940 | platform_set_drvdata(pdev, uap); | |
2941 | ||
2942 | return pl011_register_port(uap); | |
2943 | } | |
2944 | ||
788f501a | 2945 | static void sbsa_uart_remove(struct platform_device *pdev) |
0dd1e247 AP |
2946 | { |
2947 | struct uart_amba_port *uap = platform_get_drvdata(pdev); | |
2948 | ||
2949 | uart_remove_one_port(&amba_reg, &uap->port); | |
2950 | pl011_unregister_port(uap); | |
0dd1e247 AP |
2951 | } |
2952 | ||
2953 | static const struct of_device_id sbsa_uart_of_match[] = { | |
2954 | { .compatible = "arm,sbsa-uart", }, | |
2955 | {}, | |
2956 | }; | |
2957 | MODULE_DEVICE_TABLE(of, sbsa_uart_of_match); | |
2958 | ||
7789c1f1 | 2959 | static const struct acpi_device_id __maybe_unused sbsa_uart_acpi_match[] = { |
3db9ab0b | 2960 | { "ARMH0011", 0 }, |
ac442a07 | 2961 | { "ARMHB000", 0 }, |
3db9ab0b GG |
2962 | {}, |
2963 | }; | |
2964 | MODULE_DEVICE_TABLE(acpi, sbsa_uart_acpi_match); | |
2965 | ||
0dd1e247 AP |
2966 | static struct platform_driver arm_sbsa_uart_platform_driver = { |
2967 | .probe = sbsa_uart_probe, | |
788f501a | 2968 | .remove_new = sbsa_uart_remove, |
0dd1e247 AP |
2969 | .driver = { |
2970 | .name = "sbsa-uart", | |
2301ec36 | 2971 | .pm = &pl011_dev_pm_ops, |
0dd1e247 | 2972 | .of_match_table = of_match_ptr(sbsa_uart_of_match), |
3db9ab0b | 2973 | .acpi_match_table = ACPI_PTR(sbsa_uart_acpi_match), |
64609794 | 2974 | .suppress_bind_attrs = IS_BUILTIN(CONFIG_SERIAL_AMBA_PL011), |
0dd1e247 AP |
2975 | }, |
2976 | }; | |
2977 | ||
a704ddc2 | 2978 | static const struct amba_id pl011_ids[] = { |
1da177e4 LT |
2979 | { |
2980 | .id = 0x00041011, | |
2981 | .mask = 0x000fffff, | |
5926a295 AR |
2982 | .data = &vendor_arm, |
2983 | }, | |
2984 | { | |
2985 | .id = 0x00380802, | |
2986 | .mask = 0x00ffffff, | |
2987 | .data = &vendor_st, | |
1da177e4 LT |
2988 | }, |
2989 | { 0, 0 }, | |
2990 | }; | |
2991 | ||
60f7a33b DM |
2992 | MODULE_DEVICE_TABLE(amba, pl011_ids); |
2993 | ||
1da177e4 LT |
2994 | static struct amba_driver pl011_driver = { |
2995 | .drv = { | |
2996 | .name = "uart-pl011", | |
d0ce850d | 2997 | .pm = &pl011_dev_pm_ops, |
64609794 | 2998 | .suppress_bind_attrs = IS_BUILTIN(CONFIG_SERIAL_AMBA_PL011), |
1da177e4 LT |
2999 | }, |
3000 | .id_table = pl011_ids, | |
3001 | .probe = pl011_probe, | |
3002 | .remove = pl011_remove, | |
3003 | }; | |
3004 | ||
3005 | static int __init pl011_init(void) | |
3006 | { | |
826bd77a | 3007 | pr_info("Serial: AMBA PL011 UART driver\n"); |
1da177e4 | 3008 | |
0dd1e247 AP |
3009 | if (platform_driver_register(&arm_sbsa_uart_platform_driver)) |
3010 | pr_warn("could not register SBSA UART platform driver\n"); | |
062a68a5 | 3011 | return amba_driver_register(&pl011_driver); |
1da177e4 LT |
3012 | } |
3013 | ||
3014 | static void __exit pl011_exit(void) | |
3015 | { | |
0dd1e247 | 3016 | platform_driver_unregister(&arm_sbsa_uart_platform_driver); |
1da177e4 | 3017 | amba_driver_unregister(&pl011_driver); |
1da177e4 LT |
3018 | } |
3019 | ||
4dd9e742 AR |
3020 | /* |
3021 | * While this can be a module, if builtin it's most likely the console | |
3022 | * So let's leave module_exit but move module_init to an earlier place | |
3023 | */ | |
3024 | arch_initcall(pl011_init); | |
1da177e4 LT |
3025 | module_exit(pl011_exit); |
3026 | ||
3027 | MODULE_AUTHOR("ARM Ltd/Deep Blue Solutions Ltd"); | |
3028 | MODULE_DESCRIPTION("ARM AMBA serial port driver"); | |
3029 | MODULE_LICENSE("GPL"); |