projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
tty: serial: samsung: Add Exynos850 SoC data
[linux-2.6-block.git] / drivers / tty / serial / amba-pl011.c
CommitLineData
e3b3d0f5 1// SPDX-License-Identifier: GPL-2.0+
1da177e4 2/*
1da177e4
LT		 3 * Driver for AMBA serial ports
4 *
5 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
6 *
7 * Copyright 1999 ARM Limited
8 * Copyright (C) 2000 Deep Blue Solutions Ltd.
68b65f73 9 * Copyright (C) 2010 ST-Ericsson SA
1da177e4 10 *
1da177e4
LT		 11 * This is a generic driver for ARM AMBA-type serial ports. They
12 * have a lot of 16550-like features, but are not register compatible.
13 * Note that although they do have CTS, DCD and DSR inputs, they do
14 * not have an RI input, nor do they have DTR or RTS outputs. If
15 * required, these have to be supplied via some other means (eg, GPIO)
16 * and hooked into this driver.
17 */
1da177e4 18
1da177e4
LT		 19#include <linux/module.h>
20#include <linux/ioport.h>
21#include <linux/init.h>
22#include <linux/console.h>
23#include <linux/sysrq.h>
24#include <linux/device.h>
25#include <linux/tty.h>
26#include <linux/tty_flip.h>
27#include <linux/serial_core.h>
28#include <linux/serial.h>
a62c80e5
RK		 29#include <linux/amba/bus.h>
30#include <linux/amba/serial.h>
f8ce2547 31#include <linux/clk.h>
5a0e3ad6 32#include <linux/slab.h>
68b65f73
RK		 33#include <linux/dmaengine.h>
34#include <linux/dma-mapping.h>
35#include <linux/scatterlist.h>
c16d51a3 36#include <linux/delay.h>
258aea76 37#include <linux/types.h>
32614aad
ML		 38#include <linux/of.h>
39#include <linux/of_device.h>
258e0551 40#include <linux/pinctrl/consumer.h>
cb70706c 41#include <linux/sizes.h>
de609582 42#include <linux/io.h>
3db9ab0b 43#include <linux/acpi.h>
1da177e4 44
9f25bc51
RK		 45#include "amba-pl011.h"
46
1da177e4
LT		 47#define UART_NR 14
48
49#define SERIAL_AMBA_MAJOR 204
50#define SERIAL_AMBA_MINOR 64
51#define SERIAL_AMBA_NR UART_NR
52
53#define AMBA_ISR_PASS_LIMIT 256
54
b63d4f0f
RK		 55#define UART_DR_ERROR (UART011_DR_OE|UART011_DR_BE|UART011_DR_PE|UART011_DR_FE)
56#define UART_DUMMY_DR_RX (1 << 16)
1da177e4 57
debb7f64
RK		 58static u16 pl011_std_offsets[REG_ARRAY_SIZE] = {
59 [REG_DR] = UART01x_DR,
debb7f64 60 [REG_FR] = UART01x_FR,
e4df9a80
RK		 61 [REG_LCRH_RX] = UART011_LCRH,
62 [REG_LCRH_TX] = UART011_LCRH,
debb7f64
RK		 63 [REG_IBRD] = UART011_IBRD,
64 [REG_FBRD] = UART011_FBRD,
debb7f64
RK		 65 [REG_CR] = UART011_CR,
66 [REG_IFLS] = UART011_IFLS,
67 [REG_IMSC] = UART011_IMSC,
68 [REG_RIS] = UART011_RIS,
69 [REG_MIS] = UART011_MIS,
70 [REG_ICR] = UART011_ICR,
71 [REG_DMACR] = UART011_DMACR,
debb7f64
RK		 72};
73
5926a295
AR		 74/* There is by now at least one vendor with differing details, so handle it */
75struct vendor_data {
439403bd 76 const u16 *reg_offset;
5926a295 77 unsigned int ifls;
0e125a5f
SG		 78 unsigned int fr_busy;
79 unsigned int fr_dsr;
80 unsigned int fr_cts;
81 unsigned int fr_ri;
d8a4995b 82 unsigned int inv_fr;
84c3e03b 83 bool access_32b;
ac3e3fb4 84 bool oversampling;
38d62436 85 bool dma_threshold;
4fd0690b 86 bool cts_event_workaround;
71eec483 87 bool always_enabled;
cefc2d1d 88 bool fixed_options;
78506f22 89
ea33640a 90 unsigned int (*get_fifosize)(struct amba_device *dev);
5926a295
AR		 91};
92
ea33640a 93static unsigned int get_fifosize_arm(struct amba_device *dev)
78506f22 94{
ea33640a 95 return amba_rev(dev) < 3 ? 16 : 32;
78506f22
JK		 96}
97
5926a295 98static struct vendor_data vendor_arm = {
439403bd 99 .reg_offset = pl011_std_offsets,
5926a295 100 .ifls = UART011_IFLS_RX4_8|UART011_IFLS_TX4_8,
0e125a5f
SG		 101 .fr_busy = UART01x_FR_BUSY,
102 .fr_dsr = UART01x_FR_DSR,
103 .fr_cts = UART01x_FR_CTS,
104 .fr_ri = UART011_FR_RI,
ac3e3fb4 105 .oversampling = false,
38d62436 106 .dma_threshold = false,
4fd0690b 107 .cts_event_workaround = false,
71eec483 108 .always_enabled = false,
cefc2d1d 109 .fixed_options = false,
78506f22 110 .get_fifosize = get_fifosize_arm,
5926a295
AR		 111};
112
d054b3ac 113static const struct vendor_data vendor_sbsa = {
439403bd 114 .reg_offset = pl011_std_offsets,
0e125a5f
SG		 115 .fr_busy = UART01x_FR_BUSY,
116 .fr_dsr = UART01x_FR_DSR,
117 .fr_cts = UART01x_FR_CTS,
118 .fr_ri = UART011_FR_RI,
1aabf523 119 .access_32b = true,
0dd1e247
AP		 120 .oversampling = false,
121 .dma_threshold = false,
122 .cts_event_workaround = false,
123 .always_enabled = true,
124 .fixed_options = true,
125};
126
37ef38f3 127#ifdef CONFIG_ACPI_SPCR_TABLE
d054b3ac 128static const struct vendor_data vendor_qdt_qdf2400_e44 = {
d8a4995b
CC		 129 .reg_offset = pl011_std_offsets,
130 .fr_busy = UART011_FR_TXFE,
131 .fr_dsr = UART01x_FR_DSR,
132 .fr_cts = UART01x_FR_CTS,
133 .fr_ri = UART011_FR_RI,
134 .inv_fr = UART011_FR_TXFE,
135 .access_32b = true,
136 .oversampling = false,
137 .dma_threshold = false,
138 .cts_event_workaround = false,
139 .always_enabled = true,
140 .fixed_options = true,
141};
37ef38f3 142#endif
d8a4995b 143
bf69ff8a
RK		 144static u16 pl011_st_offsets[REG_ARRAY_SIZE] = {
145 [REG_DR] = UART01x_DR,
146 [REG_ST_DMAWM] = ST_UART011_DMAWM,
147 [REG_ST_TIMEOUT] = ST_UART011_TIMEOUT,
148 [REG_FR] = UART01x_FR,
e4df9a80
RK		 149 [REG_LCRH_RX] = ST_UART011_LCRH_RX,
150 [REG_LCRH_TX] = ST_UART011_LCRH_TX,
bf69ff8a
RK		 151 [REG_IBRD] = UART011_IBRD,
152 [REG_FBRD] = UART011_FBRD,
bf69ff8a
RK		 153 [REG_CR] = UART011_CR,
154 [REG_IFLS] = UART011_IFLS,
155 [REG_IMSC] = UART011_IMSC,
156 [REG_RIS] = UART011_RIS,
157 [REG_MIS] = UART011_MIS,
158 [REG_ICR] = UART011_ICR,
159 [REG_DMACR] = UART011_DMACR,
160 [REG_ST_XFCR] = ST_UART011_XFCR,
161 [REG_ST_XON1] = ST_UART011_XON1,
162 [REG_ST_XON2] = ST_UART011_XON2,
163 [REG_ST_XOFF1] = ST_UART011_XOFF1,
164 [REG_ST_XOFF2] = ST_UART011_XOFF2,
165 [REG_ST_ITCR] = ST_UART011_ITCR,
166 [REG_ST_ITIP] = ST_UART011_ITIP,
167 [REG_ST_ABCR] = ST_UART011_ABCR,
168 [REG_ST_ABIMSC] = ST_UART011_ABIMSC,
169};
170
ea33640a 171static unsigned int get_fifosize_st(struct amba_device *dev)
78506f22
JK		 172{
173 return 64;
174}
175
5926a295 176static struct vendor_data vendor_st = {
bf69ff8a 177 .reg_offset = pl011_st_offsets,
5926a295 178 .ifls = UART011_IFLS_RX_HALF|UART011_IFLS_TX_HALF,
0e125a5f
SG		 179 .fr_busy = UART01x_FR_BUSY,
180 .fr_dsr = UART01x_FR_DSR,
181 .fr_cts = UART01x_FR_CTS,
182 .fr_ri = UART011_FR_RI,
ac3e3fb4 183 .oversampling = true,
38d62436 184 .dma_threshold = true,
4fd0690b 185 .cts_event_workaround = true,
71eec483 186 .always_enabled = false,
cefc2d1d 187 .fixed_options = false,
78506f22 188 .get_fifosize = get_fifosize_st,
1da177e4
LT		 189};
190
7ec75871
RK		 191static const u16 pl011_zte_offsets[REG_ARRAY_SIZE] = {
192 [REG_DR] = ZX_UART011_DR,
193 [REG_FR] = ZX_UART011_FR,
194 [REG_LCRH_RX] = ZX_UART011_LCRH,
195 [REG_LCRH_TX] = ZX_UART011_LCRH,
196 [REG_IBRD] = ZX_UART011_IBRD,
197 [REG_FBRD] = ZX_UART011_FBRD,
198 [REG_CR] = ZX_UART011_CR,
199 [REG_IFLS] = ZX_UART011_IFLS,
200 [REG_IMSC] = ZX_UART011_IMSC,
201 [REG_RIS] = ZX_UART011_RIS,
202 [REG_MIS] = ZX_UART011_MIS,
203 [REG_ICR] = ZX_UART011_ICR,
204 [REG_DMACR] = ZX_UART011_DMACR,
205};
206
9c267ddb
SG		 207static unsigned int get_fifosize_zte(struct amba_device *dev)
208{
209 return 16;
210}
211
2426fbc7 212static struct vendor_data vendor_zte = {
7ec75871
RK		 213 .reg_offset = pl011_zte_offsets,
214 .access_32b = true,
215 .ifls = UART011_IFLS_RX4_8|UART011_IFLS_TX4_8,
0e125a5f
SG		 216 .fr_busy = ZX_UART01x_FR_BUSY,
217 .fr_dsr = ZX_UART01x_FR_DSR,
218 .fr_cts = ZX_UART01x_FR_CTS,
219 .fr_ri = ZX_UART011_FR_RI,
9c267ddb 220 .get_fifosize = get_fifosize_zte,
7ec75871
RK		 221};
222
68b65f73 223/* Deals with DMA transactions */
ead76f32
LW		 224
225struct pl011_sgbuf {
226 struct scatterlist sg;
227 char *buf;
228};
229
230struct pl011_dmarx_data {
231 struct dma_chan *chan;
232 struct completion complete;
233 bool use_buf_b;
234 struct pl011_sgbuf sgbuf_a;
235 struct pl011_sgbuf sgbuf_b;
236 dma_cookie_t cookie;
237 bool running;
cb06ff10
CM		 238 struct timer_list timer;
239 unsigned int last_residue;
240 unsigned long last_jiffies;
241 bool auto_poll_rate;
242 unsigned int poll_rate;
243 unsigned int poll_timeout;
ead76f32
LW		 244};
245
68b65f73
RK		 246struct pl011_dmatx_data {
247 struct dma_chan *chan;
248 struct scatterlist sg;
249 char *buf;
250 bool queued;
251};
252
c19f12b5
RK		 253/*
254 * We wrap our port structure around the generic uart_port.
255 */
256struct uart_amba_port {
257 struct uart_port port;
debb7f64 258 const u16 *reg_offset;
c19f12b5
RK		 259 struct clk *clk;
260 const struct vendor_data *vendor;
68b65f73 261 unsigned int dmacr; /* dma control reg */
c19f12b5
RK		 262 unsigned int im; /* interrupt mask */
263 unsigned int old_status;
ffca2b11 264 unsigned int fifosize; /* vendor-specific */
d8d8ffa4 265 unsigned int old_cr; /* state during shutdown */
cefc2d1d 266 unsigned int fixed_baud; /* vendor-set fixed baud rate */
c19f12b5 267 char type[12];
8d479237
LS		 268 bool rs485_tx_started;
269 unsigned int rs485_tx_drain_interval; /* usecs */
68b65f73
RK		 270#ifdef CONFIG_DMA_ENGINE
271 /* DMA stuff */
ead76f32
LW		 272 bool using_tx_dma;
273 bool using_rx_dma;
274 struct pl011_dmarx_data dmarx;
68b65f73 275 struct pl011_dmatx_data dmatx;
1c9be310 276 bool dma_probed;
68b65f73
RK		 277#endif
278};
279
8d479237
LS		 280static unsigned int pl011_tx_empty(struct uart_port *port);
281
9f25bc51
RK		 282static unsigned int pl011_reg_to_offset(const struct uart_amba_port *uap,
283 unsigned int reg)
284{
debb7f64 285 return uap->reg_offset[reg];
9f25bc51
RK		 286}
287
b2a4e24c
RK		 288static unsigned int pl011_read(const struct uart_amba_port *uap,
289 unsigned int reg)
75836339 290{
84c3e03b
RK		 291 void __iomem *addr = uap->port.membase + pl011_reg_to_offset(uap, reg);
292
3b78fae7
TT		 293 return (uap->port.iotype == UPIO_MEM32) ?
294 readl_relaxed(addr) : readw_relaxed(addr);
75836339
RK		 295}
296
b2a4e24c
RK		 297static void pl011_write(unsigned int val, const struct uart_amba_port *uap,
298 unsigned int reg)
75836339 299{
84c3e03b
RK		 300 void __iomem *addr = uap->port.membase + pl011_reg_to_offset(uap, reg);
301
3b78fae7 302 if (uap->port.iotype == UPIO_MEM32)
f5ce6edd 303 writel_relaxed(val, addr);
84c3e03b 304 else
f5ce6edd 305 writew_relaxed(val, addr);
75836339
RK		 306}
307
29772c4e
LW		 308/*
309 * Reads up to 256 characters from the FIFO or until it's empty and
310 * inserts them into the TTY layer. Returns the number of characters
311 * read from the FIFO.
312 */
313static int pl011_fifo_to_tty(struct uart_amba_port *uap)
314{
e73be92d 315 unsigned int ch, flag, fifotaken;
534cf755
PZ		 316 int sysrq;
317 u16 status;
29772c4e 318
e73be92d 319 for (fifotaken = 0; fifotaken != 256; fifotaken++) {
9f25bc51 320 status = pl011_read(uap, REG_FR);
29772c4e
LW		 321 if (status & UART01x_FR_RXFE)
322 break;
323
324 /* Take chars from the FIFO and update status */
9f25bc51 325 ch = pl011_read(uap, REG_DR) | UART_DUMMY_DR_RX;
29772c4e
LW		 326 flag = TTY_NORMAL;
327 uap->port.icount.rx++;
29772c4e
LW		 328
329 if (unlikely(ch & UART_DR_ERROR)) {
330 if (ch & UART011_DR_BE) {
331 ch &= ~(UART011_DR_FE | UART011_DR_PE);
332 uap->port.icount.brk++;
333 if (uart_handle_break(&uap->port))
334 continue;
335 } else if (ch & UART011_DR_PE)
336 uap->port.icount.parity++;
337 else if (ch & UART011_DR_FE)
338 uap->port.icount.frame++;
339 if (ch & UART011_DR_OE)
340 uap->port.icount.overrun++;
341
342 ch &= uap->port.read_status_mask;
343
344 if (ch & UART011_DR_BE)
345 flag = TTY_BREAK;
346 else if (ch & UART011_DR_PE)
347 flag = TTY_PARITY;
348 else if (ch & UART011_DR_FE)
349 flag = TTY_FRAME;
350 }
351
534cf755
PZ		 352 spin_unlock(&uap->port.lock);
353 sysrq = uart_handle_sysrq_char(&uap->port, ch & 255);
354 spin_lock(&uap->port.lock);
29772c4e 355
534cf755
PZ		 356 if (!sysrq)
357 uart_insert_char(&uap->port, ch, UART011_DR_OE, ch, flag);
29772c4e
LW		 358 }
359
360 return fifotaken;
361}
362
363
68b65f73
RK		 364/*
365 * All the DMA operation mode stuff goes inside this ifdef.
366 * This assumes that you have a generic DMA device interface,
367 * no custom DMA interfaces are supported.
368 */
369#ifdef CONFIG_DMA_ENGINE
370
371#define PL011_DMA_BUFFER_SIZE PAGE_SIZE
372
ead76f32
LW		 373static int pl011_sgbuf_init(struct dma_chan *chan, struct pl011_sgbuf *sg,
374 enum dma_data_direction dir)
375{
cb06ff10
CM		 376 dma_addr_t dma_addr;
377
378 sg->buf = dma_alloc_coherent(chan->device->dev,
379 PL011_DMA_BUFFER_SIZE, &dma_addr, GFP_KERNEL);
ead76f32
LW		 380 if (!sg->buf)
381 return -ENOMEM;
382
cb06ff10
CM		 383 sg_init_table(&sg->sg, 1);
384 sg_set_page(&sg->sg, phys_to_page(dma_addr),
385 PL011_DMA_BUFFER_SIZE, offset_in_page(dma_addr));
386 sg_dma_address(&sg->sg) = dma_addr;
c64be923 387 sg_dma_len(&sg->sg) = PL011_DMA_BUFFER_SIZE;
ead76f32 388
ead76f32
LW		 389 return 0;
390}
391
392static void pl011_sgbuf_free(struct dma_chan *chan, struct pl011_sgbuf *sg,
393 enum dma_data_direction dir)
394{
395 if (sg->buf) {
cb06ff10
CM		 396 dma_free_coherent(chan->device->dev,
397 PL011_DMA_BUFFER_SIZE, sg->buf,
398 sg_dma_address(&sg->sg));
ead76f32
LW		 399 }
400}
401
1c9be310 402static void pl011_dma_probe(struct uart_amba_port *uap)
68b65f73
RK		 403{
404 /* DMA is the sole user of the platform data right now */
574de559 405 struct amba_pl011_data *plat = dev_get_platdata(uap->port.dev);
1c9be310 406 struct device *dev = uap->port.dev;
68b65f73 407 struct dma_slave_config tx_conf = {
9f25bc51
RK		 408 .dst_addr = uap->port.mapbase +
409 pl011_reg_to_offset(uap, REG_DR),
68b65f73 410 .dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
a485df4b 411 .direction = DMA_MEM_TO_DEV,
68b65f73 412 .dst_maxburst = uap->fifosize >> 1,
258aea76 413 .device_fc = false,
68b65f73
RK		 414 };
415 struct dma_chan *chan;
416 dma_cap_mask_t mask;
417
1c9be310 418 uap->dma_probed = true;
61b37b04 419 chan = dma_request_chan(dev, "tx");
1c9be310
JRO		 420 if (IS_ERR(chan)) {
421 if (PTR_ERR(chan) == -EPROBE_DEFER) {
1c9be310
JRO		 422 uap->dma_probed = false;
423 return;
424 }
68b65f73 425
787b0c1f
AB		 426 /* We need platform data */
427 if (!plat || !plat->dma_filter) {
428 dev_info(uap->port.dev, "no DMA platform data\n");
429 return;
430 }
431
432 /* Try to acquire a generic DMA engine slave TX channel */
433 dma_cap_zero(mask);
434 dma_cap_set(DMA_SLAVE, mask);
435
436 chan = dma_request_channel(mask, plat->dma_filter,
437 plat->dma_tx_param);
438 if (!chan) {
439 dev_err(uap->port.dev, "no TX DMA channel!\n");
440 return;
441 }
68b65f73
RK		 442 }
443
444 dmaengine_slave_config(chan, &tx_conf);
445 uap->dmatx.chan = chan;
446
447 dev_info(uap->port.dev, "DMA channel TX %s\n",
448 dma_chan_name(uap->dmatx.chan));
ead76f32
LW		 449
450 /* Optionally make use of an RX channel as well */
787b0c1f 451 chan = dma_request_slave_channel(dev, "rx");
0d3c673e 452
d9e105ca 453 if (!chan && plat && plat->dma_rx_param) {
787b0c1f
AB		 454 chan = dma_request_channel(mask, plat->dma_filter, plat->dma_rx_param);
455
456 if (!chan) {
457 dev_err(uap->port.dev, "no RX DMA channel!\n");
458 return;
459 }
460 }
461
462 if (chan) {
ead76f32 463 struct dma_slave_config rx_conf = {
9f25bc51
RK		 464 .src_addr = uap->port.mapbase +
465 pl011_reg_to_offset(uap, REG_DR),
ead76f32 466 .src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
a485df4b 467 .direction = DMA_DEV_TO_MEM,
b2aeb775 468 .src_maxburst = uap->fifosize >> 2,
258aea76 469 .device_fc = false,
ead76f32 470 };
2d3b7d6e
AJ		 471 struct dma_slave_caps caps;
472
473 /*
474 * Some DMA controllers provide information on their capabilities.
475 * If the controller does, check for suitable residue processing
476 * otherwise assime all is well.
477 */
478 if (0 == dma_get_slave_caps(chan, &caps)) {
479 if (caps.residue_granularity ==
480 DMA_RESIDUE_GRANULARITY_DESCRIPTOR) {
481 dma_release_channel(chan);
482 dev_info(uap->port.dev,
483 "RX DMA disabled - no residue processing\n");
484 return;
485 }
486 }
ead76f32
LW		 487 dmaengine_slave_config(chan, &rx_conf);
488 uap->dmarx.chan = chan;
489
98267d33 490 uap->dmarx.auto_poll_rate = false;
8f898bfd 491 if (plat && plat->dma_rx_poll_enable) {
cb06ff10
CM		 492 /* Set poll rate if specified. */
493 if (plat->dma_rx_poll_rate) {
494 uap->dmarx.auto_poll_rate = false;
495 uap->dmarx.poll_rate = plat->dma_rx_poll_rate;
496 } else {
497 /*
498 * 100 ms defaults to poll rate if not
499 * specified. This will be adjusted with
500 * the baud rate at set_termios.
501 */
502 uap->dmarx.auto_poll_rate = true;
503 uap->dmarx.poll_rate = 100;
504 }
505 /* 3 secs defaults poll_timeout if not specified. */
506 if (plat->dma_rx_poll_timeout)
507 uap->dmarx.poll_timeout =
508 plat->dma_rx_poll_timeout;
509 else
510 uap->dmarx.poll_timeout = 3000;
98267d33
AJ		 511 } else if (!plat && dev->of_node) {
512 uap->dmarx.auto_poll_rate = of_property_read_bool(
513 dev->of_node, "auto-poll");
514 if (uap->dmarx.auto_poll_rate) {
515 u32 x;
516
517 if (0 == of_property_read_u32(dev->of_node,
518 "poll-rate-ms", &x))
519 uap->dmarx.poll_rate = x;
520 else
521 uap->dmarx.poll_rate = 100;
522 if (0 == of_property_read_u32(dev->of_node,
523 "poll-timeout-ms", &x))
524 uap->dmarx.poll_timeout = x;
525 else
526 uap->dmarx.poll_timeout = 3000;
527 }
528 }
ead76f32
LW		 529 dev_info(uap->port.dev, "DMA channel RX %s\n",
530 dma_chan_name(uap->dmarx.chan));
531 }
68b65f73
RK		 532}
533
68b65f73
RK		 534static void pl011_dma_remove(struct uart_amba_port *uap)
535{
68b65f73
RK		 536 if (uap->dmatx.chan)
537 dma_release_channel(uap->dmatx.chan);
ead76f32
LW		 538 if (uap->dmarx.chan)
539 dma_release_channel(uap->dmarx.chan);
68b65f73
RK		 540}
541
734745ca 542/* Forward declare these for the refill routine */
68b65f73 543static int pl011_dma_tx_refill(struct uart_amba_port *uap);
734745ca 544static void pl011_start_tx_pio(struct uart_amba_port *uap);
68b65f73
RK		 545
546/*
547 * The current DMA TX buffer has been sent.
548 * Try to queue up another DMA buffer.
549 */
550static void pl011_dma_tx_callback(void *data)
551{
552 struct uart_amba_port *uap = data;
553 struct pl011_dmatx_data *dmatx = &uap->dmatx;
554 unsigned long flags;
555 u16 dmacr;
556
557 spin_lock_irqsave(&uap->port.lock, flags);
558 if (uap->dmatx.queued)
559 dma_unmap_sg(dmatx->chan->device->dev, &dmatx->sg, 1,
560 DMA_TO_DEVICE);
561
562 dmacr = uap->dmacr;
563 uap->dmacr = dmacr & ~UART011_TXDMAE;
9f25bc51 564 pl011_write(uap->dmacr, uap, REG_DMACR);
68b65f73
RK		 565
566 /*
567 * If TX DMA was disabled, it means that we've stopped the DMA for
568 * some reason (eg, XOFF received, or we want to send an X-char.)
569 *
570 * Note: we need to be careful here of a potential race between DMA
571 * and the rest of the driver - if the driver disables TX DMA while
572 * a TX buffer completing, we must update the tx queued status to
573 * get further refills (hence we check dmacr).
574 */
575 if (!(dmacr & UART011_TXDMAE) || uart_tx_stopped(&uap->port) ||
576 uart_circ_empty(&uap->port.state->xmit)) {
577 uap->dmatx.queued = false;
578 spin_unlock_irqrestore(&uap->port.lock, flags);
579 return;
580 }
581
734745ca 582 if (pl011_dma_tx_refill(uap) <= 0)
68b65f73
RK		 583 /*
584 * We didn't queue a DMA buffer for some reason, but we
585 * have data pending to be sent. Re-enable the TX IRQ.
586 */
734745ca
DM		 587 pl011_start_tx_pio(uap);
588
68b65f73
RK		 589 spin_unlock_irqrestore(&uap->port.lock, flags);
590}
591
592/*
593 * Try to refill the TX DMA buffer.
594 * Locking: called with port lock held and IRQs disabled.
595 * Returns:
596 * 1 if we queued up a TX DMA buffer.
597 * 0 if we didn't want to handle this by DMA
598 * <0 on error
599 */
600static int pl011_dma_tx_refill(struct uart_amba_port *uap)
601{
602 struct pl011_dmatx_data *dmatx = &uap->dmatx;
603 struct dma_chan *chan = dmatx->chan;
604 struct dma_device *dma_dev = chan->device;
605 struct dma_async_tx_descriptor *desc;
606 struct circ_buf *xmit = &uap->port.state->xmit;
607 unsigned int count;
608
609 /*
610 * Try to avoid the overhead involved in using DMA if the
611 * transaction fits in the first half of the FIFO, by using
612 * the standard interrupt handling. This ensures that we
613 * issue a uart_write_wakeup() at the appropriate time.
614 */
615 count = uart_circ_chars_pending(xmit);
616 if (count < (uap->fifosize >> 1)) {
617 uap->dmatx.queued = false;
618 return 0;
619 }
620
621 /*
622 * Bodge: don't send the last character by DMA, as this
623 * will prevent XON from notifying us to restart DMA.
624 */
625 count -= 1;
626
627 /* Else proceed to copy the TX chars to the DMA buffer and fire DMA */
628 if (count > PL011_DMA_BUFFER_SIZE)
629 count = PL011_DMA_BUFFER_SIZE;
630
631 if (xmit->tail < xmit->head)
632 memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], count);
633 else {
634 size_t first = UART_XMIT_SIZE - xmit->tail;
e2a545a6
AJ		 635 size_t second;
636
637 if (first > count)
638 first = count;
639 second = count - first;
68b65f73
RK		 640
641 memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], first);
642 if (second)
643 memcpy(&dmatx->buf[first], &xmit->buf[0], second);
644 }
645
646 dmatx->sg.length = count;
647
648 if (dma_map_sg(dma_dev->dev, &dmatx->sg, 1, DMA_TO_DEVICE) != 1) {
649 uap->dmatx.queued = false;
650 dev_dbg(uap->port.dev, "unable to map TX DMA\n");
651 return -EBUSY;
652 }
653
16052827 654 desc = dmaengine_prep_slave_sg(chan, &dmatx->sg, 1, DMA_MEM_TO_DEV,
68b65f73
RK		 655 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
656 if (!desc) {
657 dma_unmap_sg(dma_dev->dev, &dmatx->sg, 1, DMA_TO_DEVICE);
658 uap->dmatx.queued = false;
659 /*
660 * If DMA cannot be used right now, we complete this
661 * transaction via IRQ and let the TTY layer retry.
662 */
663 dev_dbg(uap->port.dev, "TX DMA busy\n");
664 return -EBUSY;
665 }
666
667 /* Some data to go along to the callback */
668 desc->callback = pl011_dma_tx_callback;
669 desc->callback_param = uap;
670
671 /* All errors should happen at prepare time */
672 dmaengine_submit(desc);
673
674 /* Fire the DMA transaction */
675 dma_dev->device_issue_pending(chan);
676
677 uap->dmacr |= UART011_TXDMAE;
9f25bc51 678 pl011_write(uap->dmacr, uap, REG_DMACR);
68b65f73
RK		 679 uap->dmatx.queued = true;
680
681 /*
682 * Now we know that DMA will fire, so advance the ring buffer
683 * with the stuff we just dispatched.
684 */
685 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
686 uap->port.icount.tx += count;
687
688 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
689 uart_write_wakeup(&uap->port);
690
691 return 1;
692}
693
694/*
695 * We received a transmit interrupt without a pending X-char but with
696 * pending characters.
697 * Locking: called with port lock held and IRQs disabled.
698 * Returns:
699 * false if we want to use PIO to transmit
700 * true if we queued a DMA buffer
701 */
702static bool pl011_dma_tx_irq(struct uart_amba_port *uap)
703{
ead76f32 704 if (!uap->using_tx_dma)
68b65f73
RK		 705 return false;
706
707 /*
708 * If we already have a TX buffer queued, but received a
709 * TX interrupt, it will be because we've just sent an X-char.
710 * Ensure the TX DMA is enabled and the TX IRQ is disabled.
711 */
712 if (uap->dmatx.queued) {
713 uap->dmacr |= UART011_TXDMAE;
9f25bc51 714 pl011_write(uap->dmacr, uap, REG_DMACR);
68b65f73 715 uap->im &= ~UART011_TXIM;
9f25bc51 716 pl011_write(uap->im, uap, REG_IMSC);
68b65f73
RK		 717 return true;
718 }
719
720 /*
721 * We don't have a TX buffer queued, so try to queue one.
25985edc 722 * If we successfully queued a buffer, mask the TX IRQ.
68b65f73
RK		 723 */
724 if (pl011_dma_tx_refill(uap) > 0) {
725 uap->im &= ~UART011_TXIM;
9f25bc51 726 pl011_write(uap->im, uap, REG_IMSC);
68b65f73
RK		 727 return true;
728 }
729 return false;
730}
731
732/*
733 * Stop the DMA transmit (eg, due to received XOFF).
734 * Locking: called with port lock held and IRQs disabled.
735 */
736static inline void pl011_dma_tx_stop(struct uart_amba_port *uap)
737{
738 if (uap->dmatx.queued) {
739 uap->dmacr &= ~UART011_TXDMAE;
9f25bc51 740 pl011_write(uap->dmacr, uap, REG_DMACR);
68b65f73
RK		 741 }
742}
743
744/*
745 * Try to start a DMA transmit, or in the case of an XON/OFF
746 * character queued for send, try to get that character out ASAP.
747 * Locking: called with port lock held and IRQs disabled.
748 * Returns:
749 * false if we want the TX IRQ to be enabled
750 * true if we have a buffer queued
751 */
752static inline bool pl011_dma_tx_start(struct uart_amba_port *uap)
753{
754 u16 dmacr;
755
ead76f32 756 if (!uap->using_tx_dma)
68b65f73
RK		 757 return false;
758
759 if (!uap->port.x_char) {
760 /* no X-char, try to push chars out in DMA mode */
761 bool ret = true;
762
763 if (!uap->dmatx.queued) {
764 if (pl011_dma_tx_refill(uap) > 0) {
765 uap->im &= ~UART011_TXIM;
9f25bc51 766 pl011_write(uap->im, uap, REG_IMSC);
734745ca 767 } else
68b65f73 768 ret = false;
68b65f73
RK		 769 } else if (!(uap->dmacr & UART011_TXDMAE)) {
770 uap->dmacr |= UART011_TXDMAE;
9f25bc51 771 pl011_write(uap->dmacr, uap, REG_DMACR);
68b65f73
RK		 772 }
773 return ret;
774 }
775
776 /*
777 * We have an X-char to send. Disable DMA to prevent it loading
778 * the TX fifo, and then see if we can stuff it into the FIFO.
779 */
780 dmacr = uap->dmacr;
781 uap->dmacr &= ~UART011_TXDMAE;
9f25bc51 782 pl011_write(uap->dmacr, uap, REG_DMACR);
68b65f73 783
9f25bc51 784 if (pl011_read(uap, REG_FR) & UART01x_FR_TXFF) {
68b65f73
RK		 785 /*
786 * No space in the FIFO, so enable the transmit interrupt
787 * so we know when there is space. Note that once we've
788 * loaded the character, we should just re-enable DMA.
789 */
790 return false;
791 }
792
9f25bc51 793 pl011_write(uap->port.x_char, uap, REG_DR);
68b65f73
RK		 794 uap->port.icount.tx++;
795 uap->port.x_char = 0;
796
797 /* Success - restore the DMA state */
798 uap->dmacr = dmacr;
9f25bc51 799 pl011_write(dmacr, uap, REG_DMACR);
68b65f73
RK		 800
801 return true;
802}
803
804/*
805 * Flush the transmit buffer.
806 * Locking: called with port lock held and IRQs disabled.
807 */
808static void pl011_dma_flush_buffer(struct uart_port *port)
b83286bf
FE		 809__releases(&uap->port.lock)
810__acquires(&uap->port.lock)
68b65f73 811{
a5820c24
DT		 812 struct uart_amba_port *uap =
813 container_of(port, struct uart_amba_port, port);
68b65f73 814
ead76f32 815 if (!uap->using_tx_dma)
68b65f73
RK		 816 return;
817
f6a19647
VW		 818 dmaengine_terminate_async(uap->dmatx.chan);
819
68b65f73
RK		 820 if (uap->dmatx.queued) {
821 dma_unmap_sg(uap->dmatx.chan->device->dev, &uap->dmatx.sg, 1,
822 DMA_TO_DEVICE);
823 uap->dmatx.queued = false;
824 uap->dmacr &= ~UART011_TXDMAE;
9f25bc51 825 pl011_write(uap->dmacr, uap, REG_DMACR);
68b65f73
RK		 826 }
827}
828
ead76f32
LW		 829static void pl011_dma_rx_callback(void *data);
830
831static int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap)
832{
833 struct dma_chan *rxchan = uap->dmarx.chan;
ead76f32
LW		 834 struct pl011_dmarx_data *dmarx = &uap->dmarx;
835 struct dma_async_tx_descriptor *desc;
836 struct pl011_sgbuf *sgbuf;
837
838 if (!rxchan)
839 return -EIO;
840
841 /* Start the RX DMA job */
842 sgbuf = uap->dmarx.use_buf_b ?
843 &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a;
16052827 844 desc = dmaengine_prep_slave_sg(rxchan, &sgbuf->sg, 1,
a485df4b 845 DMA_DEV_TO_MEM,
ead76f32
LW		 846 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
847 /*
848 * If the DMA engine is busy and cannot prepare a
849 * channel, no big deal, the driver will fall back
850 * to interrupt mode as a result of this error code.
851 */
852 if (!desc) {
853 uap->dmarx.running = false;
854 dmaengine_terminate_all(rxchan);
855 return -EBUSY;
856 }
857
858 /* Some data to go along to the callback */
859 desc->callback = pl011_dma_rx_callback;
860 desc->callback_param = uap;
861 dmarx->cookie = dmaengine_submit(desc);
862 dma_async_issue_pending(rxchan);
863
864 uap->dmacr |= UART011_RXDMAE;
9f25bc51 865 pl011_write(uap->dmacr, uap, REG_DMACR);
ead76f32
LW		 866 uap->dmarx.running = true;
867
868 uap->im &= ~UART011_RXIM;
9f25bc51 869 pl011_write(uap->im, uap, REG_IMSC);
ead76f32
LW		 870
871 return 0;
872}
873
874/*
875 * This is called when either the DMA job is complete, or
876 * the FIFO timeout interrupt occurred. This must be called
877 * with the port spinlock uap->port.lock held.
878 */
879static void pl011_dma_rx_chars(struct uart_amba_port *uap,
880 u32 pending, bool use_buf_b,
881 bool readfifo)
882{
05c7cd39 883 struct tty_port *port = &uap->port.state->port;
ead76f32
LW		 884 struct pl011_sgbuf *sgbuf = use_buf_b ?
885 &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a;
ead76f32
LW		 886 int dma_count = 0;
887 u32 fifotaken = 0; /* only used for vdbg() */
888
cb06ff10
CM		 889 struct pl011_dmarx_data *dmarx = &uap->dmarx;
890 int dmataken = 0;
891
892 if (uap->dmarx.poll_rate) {
893 /* The data can be taken by polling */
894 dmataken = sgbuf->sg.length - dmarx->last_residue;
895 /* Recalculate the pending size */
896 if (pending >= dmataken)
897 pending -= dmataken;
898 }
899
900 /* Pick the remain data from the DMA */
ead76f32 901 if (pending) {
ead76f32
LW		 902
903 /*
904 * First take all chars in the DMA pipe, then look in the FIFO.
905 * Note that tty_insert_flip_buf() tries to take as many chars
906 * as it can.
907 */
cb06ff10
CM		 908 dma_count = tty_insert_flip_string(port, sgbuf->buf + dmataken,
909 pending);
ead76f32
LW		 910
911 uap->port.icount.rx += dma_count;
912 if (dma_count < pending)
913 dev_warn(uap->port.dev,
914 "couldn't insert all characters (TTY is full?)\n");
915 }
916
cb06ff10
CM		 917 /* Reset the last_residue for Rx DMA poll */
918 if (uap->dmarx.poll_rate)
919 dmarx->last_residue = sgbuf->sg.length;
920
ead76f32
LW		 921 /*
922 * Only continue with trying to read the FIFO if all DMA chars have
923 * been taken first.
924 */
925 if (dma_count == pending && readfifo) {
926 /* Clear any error flags */
75836339 927 pl011_write(UART011_OEIS | UART011_BEIS | UART011_PEIS |
9f25bc51 928 UART011_FEIS, uap, REG_ICR);
ead76f32
LW		 929
930 /*
931 * If we read all the DMA'd characters, and we had an
29772c4e
LW		 932 * incomplete buffer, that could be due to an rx error, or
933 * maybe we just timed out. Read any pending chars and check
934 * the error status.
935 *
936 * Error conditions will only occur in the FIFO, these will
937 * trigger an immediate interrupt and stop the DMA job, so we
938 * will always find the error in the FIFO, never in the DMA
939 * buffer.
ead76f32 940 */
29772c4e 941 fifotaken = pl011_fifo_to_tty(uap);
ead76f32
LW		 942 }
943
ead76f32
LW		 944 dev_vdbg(uap->port.dev,
945 "Took %d chars from DMA buffer and %d chars from the FIFO\n",
946 dma_count, fifotaken);
2e124b4a 947 tty_flip_buffer_push(port);
ead76f32
LW		 948}
949
950static void pl011_dma_rx_irq(struct uart_amba_port *uap)
951{
952 struct pl011_dmarx_data *dmarx = &uap->dmarx;
953 struct dma_chan *rxchan = dmarx->chan;
954 struct pl011_sgbuf *sgbuf = dmarx->use_buf_b ?
955 &dmarx->sgbuf_b : &dmarx->sgbuf_a;
956 size_t pending;
957 struct dma_tx_state state;
958 enum dma_status dmastat;
959
960 /*
961 * Pause the transfer so we can trust the current counter,
962 * do this before we pause the PL011 block, else we may
963 * overflow the FIFO.
964 */
965 if (dmaengine_pause(rxchan))
966 dev_err(uap->port.dev, "unable to pause DMA transfer\n");
967 dmastat = rxchan->device->device_tx_status(rxchan,
968 dmarx->cookie, &state);
969 if (dmastat != DMA_PAUSED)
970 dev_err(uap->port.dev, "unable to pause DMA transfer\n");
971
972 /* Disable RX DMA - incoming data will wait in the FIFO */
973 uap->dmacr &= ~UART011_RXDMAE;
9f25bc51 974 pl011_write(uap->dmacr, uap, REG_DMACR);
ead76f32
LW		 975 uap->dmarx.running = false;
976
977 pending = sgbuf->sg.length - state.residue;
978 BUG_ON(pending > PL011_DMA_BUFFER_SIZE);
979 /* Then we terminate the transfer - we now know our residue */
980 dmaengine_terminate_all(rxchan);
981
982 /*
983 * This will take the chars we have so far and insert
984 * into the framework.
985 */
986 pl011_dma_rx_chars(uap, pending, dmarx->use_buf_b, true);
987
988 /* Switch buffer & re-trigger DMA job */
989 dmarx->use_buf_b = !dmarx->use_buf_b;
990 if (pl011_dma_rx_trigger_dma(uap)) {
991 dev_dbg(uap->port.dev, "could not retrigger RX DMA job "
992 "fall back to interrupt mode\n");
993 uap->im |= UART011_RXIM;
9f25bc51 994 pl011_write(uap->im, uap, REG_IMSC);
ead76f32
LW		 995 }
996}
997
998static void pl011_dma_rx_callback(void *data)
999{
1000 struct uart_amba_port *uap = data;
1001 struct pl011_dmarx_data *dmarx = &uap->dmarx;
6dc01aa6 1002 struct dma_chan *rxchan = dmarx->chan;
ead76f32 1003 bool lastbuf = dmarx->use_buf_b;
6dc01aa6
CM		 1004 struct pl011_sgbuf *sgbuf = dmarx->use_buf_b ?
1005 &dmarx->sgbuf_b : &dmarx->sgbuf_a;
1006 size_t pending;
1007 struct dma_tx_state state;
ead76f32
LW		 1008 int ret;
1009
1010 /*
1011 * This completion interrupt occurs typically when the
1012 * RX buffer is totally stuffed but no timeout has yet
1013 * occurred. When that happens, we just want the RX
1014 * routine to flush out the secondary DMA buffer while
1015 * we immediately trigger the next DMA job.
1016 */
1017 spin_lock_irq(&uap->port.lock);
6dc01aa6
CM		 1018 /*
1019 * Rx data can be taken by the UART interrupts during
1020 * the DMA irq handler. So we check the residue here.
1021 */
1022 rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state);
1023 pending = sgbuf->sg.length - state.residue;
1024 BUG_ON(pending > PL011_DMA_BUFFER_SIZE);
1025 /* Then we terminate the transfer - we now know our residue */
1026 dmaengine_terminate_all(rxchan);
1027
ead76f32
LW		 1028 uap->dmarx.running = false;
1029 dmarx->use_buf_b = !lastbuf;
1030 ret = pl011_dma_rx_trigger_dma(uap);
1031
6dc01aa6 1032 pl011_dma_rx_chars(uap, pending, lastbuf, false);
ead76f32
LW		 1033 spin_unlock_irq(&uap->port.lock);
1034 /*
1035 * Do this check after we picked the DMA chars so we don't
1036 * get some IRQ immediately from RX.
1037 */
1038 if (ret) {
1039 dev_dbg(uap->port.dev, "could not retrigger RX DMA job "
1040 "fall back to interrupt mode\n");
1041 uap->im |= UART011_RXIM;
9f25bc51 1042 pl011_write(uap->im, uap, REG_IMSC);
ead76f32
LW		 1043 }
1044}
1045
1046/*
1047 * Stop accepting received characters, when we're shutting down or
1048 * suspending this port.
1049 * Locking: called with port lock held and IRQs disabled.
1050 */
1051static inline void pl011_dma_rx_stop(struct uart_amba_port *uap)
1052{
1053 /* FIXME. Just disable the DMA enable */
1054 uap->dmacr &= ~UART011_RXDMAE;
9f25bc51 1055 pl011_write(uap->dmacr, uap, REG_DMACR);
ead76f32 1056}
68b65f73 1057
cb06ff10
CM		 1058/*
1059 * Timer handler for Rx DMA polling.
1060 * Every polling, It checks the residue in the dma buffer and transfer
1061 * data to the tty. Also, last_residue is updated for the next polling.
1062 */
f7f73096 1063static void pl011_dma_rx_poll(struct timer_list *t)
cb06ff10 1064{
f7f73096 1065 struct uart_amba_port *uap = from_timer(uap, t, dmarx.timer);
cb06ff10
CM		 1066 struct tty_port *port = &uap->port.state->port;
1067 struct pl011_dmarx_data *dmarx = &uap->dmarx;
1068 struct dma_chan *rxchan = uap->dmarx.chan;
18ee37e1 1069 unsigned long flags;
cb06ff10
CM		 1070 unsigned int dmataken = 0;
1071 unsigned int size = 0;
1072 struct pl011_sgbuf *sgbuf;
1073 int dma_count;
1074 struct dma_tx_state state;
1075
1076 sgbuf = dmarx->use_buf_b ? &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a;
1077 rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state);
1078 if (likely(state.residue < dmarx->last_residue)) {
1079 dmataken = sgbuf->sg.length - dmarx->last_residue;
1080 size = dmarx->last_residue - state.residue;
1081 dma_count = tty_insert_flip_string(port, sgbuf->buf + dmataken,
1082 size);
1083 if (dma_count == size)
1084 dmarx->last_residue = state.residue;
1085 dmarx->last_jiffies = jiffies;
1086 }
1087 tty_flip_buffer_push(port);
1088
1089 /*
1090 * If no data is received in poll_timeout, the driver will fall back
1091 * to interrupt mode. We will retrigger DMA at the first interrupt.
1092 */
1093 if (jiffies_to_msecs(jiffies - dmarx->last_jiffies)
1094 > uap->dmarx.poll_timeout) {
1095
1096 spin_lock_irqsave(&uap->port.lock, flags);
1097 pl011_dma_rx_stop(uap);
c25a1ad7 1098 uap->im |= UART011_RXIM;
9f25bc51 1099 pl011_write(uap->im, uap, REG_IMSC);
cb06ff10
CM		 1100 spin_unlock_irqrestore(&uap->port.lock, flags);
1101
1102 uap->dmarx.running = false;
1103 dmaengine_terminate_all(rxchan);
1104 del_timer(&uap->dmarx.timer);
1105 } else {
1106 mod_timer(&uap->dmarx.timer,
1107 jiffies + msecs_to_jiffies(uap->dmarx.poll_rate));
1108 }
1109}
1110
68b65f73
RK		 1111static void pl011_dma_startup(struct uart_amba_port *uap)
1112{
ead76f32
LW		 1113 int ret;
1114
1c9be310
JRO		 1115 if (!uap->dma_probed)
1116 pl011_dma_probe(uap);
1117
68b65f73
RK		 1118 if (!uap->dmatx.chan)
1119 return;
1120
4c0be45b 1121 uap->dmatx.buf = kmalloc(PL011_DMA_BUFFER_SIZE, GFP_KERNEL | __GFP_DMA);
68b65f73
RK		 1122 if (!uap->dmatx.buf) {
1123 dev_err(uap->port.dev, "no memory for DMA TX buffer\n");
1124 uap->port.fifosize = uap->fifosize;
1125 return;
1126 }
1127
1128 sg_init_one(&uap->dmatx.sg, uap->dmatx.buf, PL011_DMA_BUFFER_SIZE);
1129
1130 /* The DMA buffer is now the FIFO the TTY subsystem can use */
1131 uap->port.fifosize = PL011_DMA_BUFFER_SIZE;
ead76f32
LW		 1132 uap->using_tx_dma = true;
1133
1134 if (!uap->dmarx.chan)
1135 goto skip_rx;
1136
1137 /* Allocate and map DMA RX buffers */
1138 ret = pl011_sgbuf_init(uap->dmarx.chan, &uap->dmarx.sgbuf_a,
1139 DMA_FROM_DEVICE);
1140 if (ret) {
1141 dev_err(uap->port.dev, "failed to init DMA %s: %d\n",
1142 "RX buffer A", ret);
1143 goto skip_rx;
1144 }
68b65f73 1145
ead76f32
LW		 1146 ret = pl011_sgbuf_init(uap->dmarx.chan, &uap->dmarx.sgbuf_b,
1147 DMA_FROM_DEVICE);
1148 if (ret) {
1149 dev_err(uap->port.dev, "failed to init DMA %s: %d\n",
1150 "RX buffer B", ret);
1151 pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_a,
1152 DMA_FROM_DEVICE);
1153 goto skip_rx;
1154 }
1155
1156 uap->using_rx_dma = true;
68b65f73 1157
ead76f32 1158skip_rx:
68b65f73
RK		 1159 /* Turn on DMA error (RX/TX will be enabled on demand) */
1160 uap->dmacr |= UART011_DMAONERR;
9f25bc51 1161 pl011_write(uap->dmacr, uap, REG_DMACR);
38d62436
RK		 1162
1163 /*
1164 * ST Micro variants has some specific dma burst threshold
1165 * compensation. Set this to 16 bytes, so burst will only
1166 * be issued above/below 16 bytes.
1167 */
1168 if (uap->vendor->dma_threshold)
75836339 1169 pl011_write(ST_UART011_DMAWM_RX_16 | ST_UART011_DMAWM_TX_16,
9f25bc51 1170 uap, REG_ST_DMAWM);
ead76f32
LW		 1171
1172 if (uap->using_rx_dma) {
1173 if (pl011_dma_rx_trigger_dma(uap))
1174 dev_dbg(uap->port.dev, "could not trigger initial "
1175 "RX DMA job, fall back to interrupt mode\n");
cb06ff10 1176 if (uap->dmarx.poll_rate) {
f7f73096 1177 timer_setup(&uap->dmarx.timer, pl011_dma_rx_poll, 0);
cb06ff10
CM		 1178 mod_timer(&uap->dmarx.timer,
1179 jiffies +
1180 msecs_to_jiffies(uap->dmarx.poll_rate));
1181 uap->dmarx.last_residue = PL011_DMA_BUFFER_SIZE;
1182 uap->dmarx.last_jiffies = jiffies;
1183 }
ead76f32 1184 }
68b65f73
RK		 1185}
1186
1187static void pl011_dma_shutdown(struct uart_amba_port *uap)
1188{
ead76f32 1189 if (!(uap->using_tx_dma || uap->using_rx_dma))
68b65f73
RK		 1190 return;
1191
1192 /* Disable RX and TX DMA */
0e125a5f 1193 while (pl011_read(uap, REG_FR) & uap->vendor->fr_busy)
2f2fd089 1194 cpu_relax();
68b65f73
RK		 1195
1196 spin_lock_irq(&uap->port.lock);
1197 uap->dmacr &= ~(UART011_DMAONERR | UART011_RXDMAE | UART011_TXDMAE);
9f25bc51 1198 pl011_write(uap->dmacr, uap, REG_DMACR);
68b65f73
RK		 1199 spin_unlock_irq(&uap->port.lock);
1200
ead76f32
LW		 1201 if (uap->using_tx_dma) {
1202 /* In theory, this should already be done by pl011_dma_flush_buffer */
1203 dmaengine_terminate_all(uap->dmatx.chan);
1204 if (uap->dmatx.queued) {
1205 dma_unmap_sg(uap->dmatx.chan->device->dev, &uap->dmatx.sg, 1,
1206 DMA_TO_DEVICE);
1207 uap->dmatx.queued = false;
1208 }
1209
1210 kfree(uap->dmatx.buf);
1211 uap->using_tx_dma = false;
68b65f73
RK		 1212 }
1213
ead76f32
LW		 1214 if (uap->using_rx_dma) {
1215 dmaengine_terminate_all(uap->dmarx.chan);
1216 /* Clean up the RX DMA */
1217 pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_a, DMA_FROM_DEVICE);
1218 pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_b, DMA_FROM_DEVICE);
cb06ff10
CM		 1219 if (uap->dmarx.poll_rate)
1220 del_timer_sync(&uap->dmarx.timer);
ead76f32
LW		 1221 uap->using_rx_dma = false;
1222 }
1223}
68b65f73 1224
ead76f32
LW		 1225static inline bool pl011_dma_rx_available(struct uart_amba_port *uap)
1226{
1227 return uap->using_rx_dma;
68b65f73
RK		 1228}
1229
ead76f32
LW		 1230static inline bool pl011_dma_rx_running(struct uart_amba_port *uap)
1231{
1232 return uap->using_rx_dma && uap->dmarx.running;
1233}
1234
68b65f73
RK		 1235#else
1236/* Blank functions if the DMA engine is not available */
68b65f73
RK		 1237static inline void pl011_dma_remove(struct uart_amba_port *uap)
1238{
1239}
1240
1241static inline void pl011_dma_startup(struct uart_amba_port *uap)
1242{
1243}
1244
1245static inline void pl011_dma_shutdown(struct uart_amba_port *uap)
1246{
1247}
1248
1249static inline bool pl011_dma_tx_irq(struct uart_amba_port *uap)
1250{
1251 return false;
1252}
1253
1254static inline void pl011_dma_tx_stop(struct uart_amba_port *uap)
1255{
1256}
1257
1258static inline bool pl011_dma_tx_start(struct uart_amba_port *uap)
1259{
1260 return false;
1261}
1262
ead76f32
LW		 1263static inline void pl011_dma_rx_irq(struct uart_amba_port *uap)
1264{
1265}
1266
1267static inline void pl011_dma_rx_stop(struct uart_amba_port *uap)
1268{
1269}
1270
1271static inline int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap)
1272{
1273 return -EIO;
1274}
1275
1276static inline bool pl011_dma_rx_available(struct uart_amba_port *uap)
1277{
1278 return false;
1279}
1280
1281static inline bool pl011_dma_rx_running(struct uart_amba_port *uap)
1282{
1283 return false;
1284}
1285
68b65f73
RK		 1286#define pl011_dma_flush_buffer NULL
1287#endif
1288
8d479237
LS		 1289static void pl011_rs485_tx_stop(struct uart_amba_port *uap)
1290{
1291 struct uart_port *port = &uap->port;
1292 int i = 0;
1293 u32 cr;
1294
1295 /* Wait until hardware tx queue is empty */
1296 while (!pl011_tx_empty(port)) {
1297 if (i == port->fifosize) {
1298 dev_warn(port->dev,
1299 "timeout while draining hardware tx queue\n");
1300 break;
1301 }
1302
1303 udelay(uap->rs485_tx_drain_interval);
1304 i++;
1305 }
1306
1307 if (port->rs485.delay_rts_after_send)
1308 mdelay(port->rs485.delay_rts_after_send);
1309
1310 cr = pl011_read(uap, REG_CR);
1311
1312 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND)
1313 cr &= ~UART011_CR_RTS;
1314 else
1315 cr |= UART011_CR_RTS;
1316
1317 /* Disable the transmitter and reenable the transceiver */
1318 cr &= ~UART011_CR_TXE;
1319 cr |= UART011_CR_RXE;
1320 pl011_write(cr, uap, REG_CR);
1321
1322 uap->rs485_tx_started = false;
1323}
1324
b129a8cc 1325static void pl011_stop_tx(struct uart_port *port)
1da177e4 1326{
a5820c24
DT		 1327 struct uart_amba_port *uap =
1328 container_of(port, struct uart_amba_port, port);
1da177e4
LT		 1329
1330 uap->im &= ~UART011_TXIM;
9f25bc51 1331 pl011_write(uap->im, uap, REG_IMSC);
68b65f73 1332 pl011_dma_tx_stop(uap);
8d479237
LS		 1333
1334 if ((port->rs485.flags & SER_RS485_ENABLED) && uap->rs485_tx_started)
1335 pl011_rs485_tx_stop(uap);
1da177e4
LT		 1336}
1337
7d05587c 1338static bool pl011_tx_chars(struct uart_amba_port *uap, bool from_irq);
734745ca
DM		 1339
1340/* Start TX with programmed I/O only (no DMA) */
1341static void pl011_start_tx_pio(struct uart_amba_port *uap)
1342{
7d05587c
J		 1343 if (pl011_tx_chars(uap, false)) {
1344 uap->im |= UART011_TXIM;
1345 pl011_write(uap->im, uap, REG_IMSC);
1346 }
734745ca
DM		 1347}
1348
b129a8cc 1349static void pl011_start_tx(struct uart_port *port)
1da177e4 1350{
a5820c24
DT		 1351 struct uart_amba_port *uap =
1352 container_of(port, struct uart_amba_port, port);
1da177e4 1353
734745ca
DM		 1354 if (!pl011_dma_tx_start(uap))
1355 pl011_start_tx_pio(uap);
1da177e4
LT		 1356}
1357
1358static void pl011_stop_rx(struct uart_port *port)
1359{
a5820c24
DT		 1360 struct uart_amba_port *uap =
1361 container_of(port, struct uart_amba_port, port);
1da177e4
LT		 1362
1363 uap->im &= ~(UART011_RXIM|UART011_RTIM|UART011_FEIM|
1364 UART011_PEIM|UART011_BEIM|UART011_OEIM);
9f25bc51 1365 pl011_write(uap->im, uap, REG_IMSC);
ead76f32
LW		 1366
1367 pl011_dma_rx_stop(uap);
1da177e4
LT		 1368}
1369
1370static void pl011_enable_ms(struct uart_port *port)
1371{
a5820c24
DT		 1372 struct uart_amba_port *uap =
1373 container_of(port, struct uart_amba_port, port);
1da177e4
LT		 1374
1375 uap->im |= UART011_RIMIM|UART011_CTSMIM|UART011_DCDMIM|UART011_DSRMIM;
9f25bc51 1376 pl011_write(uap->im, uap, REG_IMSC);
1da177e4
LT		 1377}
1378
7d12e780 1379static void pl011_rx_chars(struct uart_amba_port *uap)
b83286bf
FE		 1380__releases(&uap->port.lock)
1381__acquires(&uap->port.lock)
1da177e4 1382{
29772c4e 1383 pl011_fifo_to_tty(uap);
1da177e4 1384
2389b272 1385 spin_unlock(&uap->port.lock);
2e124b4a 1386 tty_flip_buffer_push(&uap->port.state->port);
ead76f32
LW		 1387 /*
1388 * If we were temporarily out of DMA mode for a while,
1389 * attempt to switch back to DMA mode again.
1390 */
1391 if (pl011_dma_rx_available(uap)) {
1392 if (pl011_dma_rx_trigger_dma(uap)) {
1393 dev_dbg(uap->port.dev, "could not trigger RX DMA job "
1394 "fall back to interrupt mode again\n");
1395 uap->im |= UART011_RXIM;
9f25bc51 1396 pl011_write(uap->im, uap, REG_IMSC);
cb06ff10 1397 } else {
89fa28db 1398#ifdef CONFIG_DMA_ENGINE
cb06ff10
CM		 1399 /* Start Rx DMA poll */
1400 if (uap->dmarx.poll_rate) {
1401 uap->dmarx.last_jiffies = jiffies;
1402 uap->dmarx.last_residue = PL011_DMA_BUFFER_SIZE;
1403 mod_timer(&uap->dmarx.timer,
1404 jiffies +
1405 msecs_to_jiffies(uap->dmarx.poll_rate));
1406 }
89fa28db 1407#endif
cb06ff10 1408 }
ead76f32 1409 }
2389b272 1410 spin_lock(&uap->port.lock);
1da177e4
LT		 1411}
1412
1e84d223
DM		 1413static bool pl011_tx_char(struct uart_amba_port *uap, unsigned char c,
1414 bool from_irq)
734745ca 1415{
1e84d223 1416 if (unlikely(!from_irq) &&
9f25bc51 1417 pl011_read(uap, REG_FR) & UART01x_FR_TXFF)
1e84d223
DM		 1418 return false; /* unable to transmit character */
1419
9f25bc51 1420 pl011_write(c, uap, REG_DR);
734745ca
DM		 1421 uap->port.icount.tx++;
1422
1e84d223 1423 return true;
734745ca
DM		 1424}
1425
8d479237
LS		 1426static void pl011_rs485_tx_start(struct uart_amba_port *uap)
1427{
1428 struct uart_port *port = &uap->port;
1429 u32 cr;
1430
1431 /* Enable transmitter */
1432 cr = pl011_read(uap, REG_CR);
1433 cr |= UART011_CR_TXE;
1434
1435 /* Disable receiver if half-duplex */
1436 if (!(port->rs485.flags & SER_RS485_RX_DURING_TX))
1437 cr &= ~UART011_CR_RXE;
1438
1439 if (port->rs485.flags & SER_RS485_RTS_ON_SEND)
1440 cr &= ~UART011_CR_RTS;
1441 else
1442 cr |= UART011_CR_RTS;
1443
1444 pl011_write(cr, uap, REG_CR);
1445
1446 if (port->rs485.delay_rts_before_send)
1447 mdelay(port->rs485.delay_rts_before_send);
1448
1449 uap->rs485_tx_started = true;
1450}
1451
7d05587c
J		 1452/* Returns true if tx interrupts have to be (kept) enabled */
1453static bool pl011_tx_chars(struct uart_amba_port *uap, bool from_irq)
1da177e4 1454{
ebd2c8f6 1455 struct circ_buf *xmit = &uap->port.state->xmit;
1e84d223 1456 int count = uap->fifosize >> 1;
734745ca 1457
1da177e4 1458 if (uap->port.x_char) {
1e84d223 1459 if (!pl011_tx_char(uap, uap->port.x_char, from_irq))
7d05587c 1460 return true;
1da177e4 1461 uap->port.x_char = 0;
734745ca 1462 --count;
1da177e4
LT		 1463 }
1464 if (uart_circ_empty(xmit) || uart_tx_stopped(&uap->port)) {
b129a8cc 1465 pl011_stop_tx(&uap->port);
7d05587c 1466 return false;
1da177e4
LT		 1467 }
1468
8d479237
LS		 1469 if ((uap->port.rs485.flags & SER_RS485_ENABLED) &&
1470 !uap->rs485_tx_started)
1471 pl011_rs485_tx_start(uap);
1472
68b65f73
RK		 1473 /* If we are using DMA mode, try to send some characters. */
1474 if (pl011_dma_tx_irq(uap))
7d05587c 1475 return true;
68b65f73 1476
1e84d223
DM		 1477 do {
1478 if (likely(from_irq) && count-- == 0)
1da177e4 1479 break;
1e84d223
DM		 1480
1481 if (!pl011_tx_char(uap, xmit->buf[xmit->tail], from_irq))
1482 break;
1483
1484 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1485 } while (!uart_circ_empty(xmit));
1da177e4
LT		 1486
1487 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1488 uart_write_wakeup(&uap->port);
1489
7d05587c 1490 if (uart_circ_empty(xmit)) {
b129a8cc 1491 pl011_stop_tx(&uap->port);
7d05587c
J		 1492 return false;
1493 }
1494 return true;
1da177e4
LT		 1495}
1496
1497static void pl011_modem_status(struct uart_amba_port *uap)
1498{
1499 unsigned int status, delta;
1500
9f25bc51 1501 status = pl011_read(uap, REG_FR) & UART01x_FR_MODEM_ANY;
1da177e4
LT		 1502
1503 delta = status ^ uap->old_status;
1504 uap->old_status = status;
1505
1506 if (!delta)
1507 return;
1508
1509 if (delta & UART01x_FR_DCD)
1510 uart_handle_dcd_change(&uap->port, status & UART01x_FR_DCD);
1511
0e125a5f 1512 if (delta & uap->vendor->fr_dsr)
1da177e4
LT		 1513 uap->port.icount.dsr++;
1514
0e125a5f
SG		 1515 if (delta & uap->vendor->fr_cts)
1516 uart_handle_cts_change(&uap->port,
1517 status & uap->vendor->fr_cts);
1da177e4 1518
bdc04e31 1519 wake_up_interruptible(&uap->port.state->port.delta_msr_wait);
1da177e4
LT		 1520}
1521
9c4ef4b0
AP		 1522static void check_apply_cts_event_workaround(struct uart_amba_port *uap)
1523{
9c4ef4b0
AP		 1524 if (!uap->vendor->cts_event_workaround)
1525 return;
1526
1527 /* workaround to make sure that all bits are unlocked.. */
9f25bc51 1528 pl011_write(0x00, uap, REG_ICR);
9c4ef4b0
AP		 1529
1530 /*
1531 * WA: introduce 26ns(1 uart clk) delay before W1C;
1532 * single apb access will incur 2 pclk(133.12Mhz) delay,
1533 * so add 2 dummy reads
1534 */
94345aee
XW		 1535 pl011_read(uap, REG_ICR);
1536 pl011_read(uap, REG_ICR);
9c4ef4b0
AP		 1537}
1538
7d12e780 1539static irqreturn_t pl011_int(int irq, void *dev_id)
1da177e4
LT		 1540{
1541 struct uart_amba_port *uap = dev_id;
963cc981 1542 unsigned long flags;
1da177e4
LT		 1543 unsigned int status, pass_counter = AMBA_ISR_PASS_LIMIT;
1544 int handled = 0;
1545
963cc981 1546 spin_lock_irqsave(&uap->port.lock, flags);
d3a96c94 1547 status = pl011_read(uap, REG_RIS) & uap->im;
1da177e4
LT		 1548 if (status) {
1549 do {
9c4ef4b0 1550 check_apply_cts_event_workaround(uap);
f11c9841 1551
75836339
RK		 1552 pl011_write(status & ~(UART011_TXIS|UART011_RTIS|
1553 UART011_RXIS),
9f25bc51 1554 uap, REG_ICR);
1da177e4 1555
ead76f32
LW		 1556 if (status & (UART011_RTIS|UART011_RXIS)) {
1557 if (pl011_dma_rx_running(uap))
1558 pl011_dma_rx_irq(uap);
1559 else
1560 pl011_rx_chars(uap);
1561 }
1da177e4
LT		 1562 if (status & (UART011_DSRMIS|UART011_DCDMIS|
1563 UART011_CTSMIS|UART011_RIMIS))
1564 pl011_modem_status(uap);
1e84d223
DM		 1565 if (status & UART011_TXIS)
1566 pl011_tx_chars(uap, true);
1da177e4 1567
4fd0690b 1568 if (pass_counter-- == 0)
1da177e4
LT		 1569 break;
1570
d3a96c94 1571 status = pl011_read(uap, REG_RIS) & uap->im;
1da177e4
LT		 1572 } while (status != 0);
1573 handled = 1;
1574 }
1575
963cc981 1576 spin_unlock_irqrestore(&uap->port.lock, flags);
1da177e4
LT		 1577
1578 return IRQ_RETVAL(handled);
1579}
1580
e643f87f 1581static unsigned int pl011_tx_empty(struct uart_port *port)
1da177e4 1582{
a5820c24
DT		 1583 struct uart_amba_port *uap =
1584 container_of(port, struct uart_amba_port, port);
d8a4995b
CC		 1585
1586 /* Allow feature register bits to be inverted to work around errata */
1587 unsigned int status = pl011_read(uap, REG_FR) ^ uap->vendor->inv_fr;
1588
0e125a5f
SG		 1589 return status & (uap->vendor->fr_busy | UART01x_FR_TXFF) ?
1590 0 : TIOCSER_TEMT;
1da177e4
LT		 1591}
1592
e643f87f 1593static unsigned int pl011_get_mctrl(struct uart_port *port)
1da177e4 1594{
a5820c24
DT		 1595 struct uart_amba_port *uap =
1596 container_of(port, struct uart_amba_port, port);
1da177e4 1597 unsigned int result = 0;
9f25bc51 1598 unsigned int status = pl011_read(uap, REG_FR);
1da177e4 1599
5159f407 1600#define TIOCMBIT(uartbit, tiocmbit) \
1da177e4
LT		 1601 if (status & uartbit) \
1602 result |= tiocmbit
1603
5159f407 1604 TIOCMBIT(UART01x_FR_DCD, TIOCM_CAR);
0e125a5f
SG		 1605 TIOCMBIT(uap->vendor->fr_dsr, TIOCM_DSR);
1606 TIOCMBIT(uap->vendor->fr_cts, TIOCM_CTS);
1607 TIOCMBIT(uap->vendor->fr_ri, TIOCM_RNG);
5159f407 1608#undef TIOCMBIT
1da177e4
LT		 1609 return result;
1610}
1611
1612static void pl011_set_mctrl(struct uart_port *port, unsigned int mctrl)
1613{
a5820c24
DT		 1614 struct uart_amba_port *uap =
1615 container_of(port, struct uart_amba_port, port);
1da177e4
LT		 1616 unsigned int cr;
1617
8d479237
LS		 1618 if (port->rs485.flags & SER_RS485_ENABLED)
1619 mctrl &= ~TIOCM_RTS;
1620
9f25bc51 1621 cr = pl011_read(uap, REG_CR);
1da177e4 1622
5159f407 1623#define TIOCMBIT(tiocmbit, uartbit) \
1da177e4
LT		 1624 if (mctrl & tiocmbit) \
1625 cr |= uartbit; \
1626 else \
1627 cr &= ~uartbit
1628
5159f407
JS		 1629 TIOCMBIT(TIOCM_RTS, UART011_CR_RTS);
1630 TIOCMBIT(TIOCM_DTR, UART011_CR_DTR);
1631 TIOCMBIT(TIOCM_OUT1, UART011_CR_OUT1);
1632 TIOCMBIT(TIOCM_OUT2, UART011_CR_OUT2);
1633 TIOCMBIT(TIOCM_LOOP, UART011_CR_LBE);
3b43816f 1634
2a76fa28 1635 if (port->status & UPSTAT_AUTORTS) {
3b43816f
RV		 1636 /* We need to disable auto-RTS if we want to turn RTS off */
1637 TIOCMBIT(TIOCM_RTS, UART011_CR_RTSEN);
1638 }
5159f407 1639#undef TIOCMBIT
1da177e4 1640
9f25bc51 1641 pl011_write(cr, uap, REG_CR);
1da177e4
LT		 1642}
1643
1644static void pl011_break_ctl(struct uart_port *port, int break_state)
1645{
a5820c24
DT		 1646 struct uart_amba_port *uap =
1647 container_of(port, struct uart_amba_port, port);
1da177e4
LT		 1648 unsigned long flags;
1649 unsigned int lcr_h;
1650
1651 spin_lock_irqsave(&uap->port.lock, flags);
e4df9a80 1652 lcr_h = pl011_read(uap, REG_LCRH_TX);
1da177e4
LT		 1653 if (break_state == -1)
1654 lcr_h |= UART01x_LCRH_BRK;
1655 else
1656 lcr_h &= ~UART01x_LCRH_BRK;
e4df9a80 1657 pl011_write(lcr_h, uap, REG_LCRH_TX);
1da177e4
LT		 1658 spin_unlock_irqrestore(&uap->port.lock, flags);
1659}
1660
84b5ae15 1661#ifdef CONFIG_CONSOLE_POLL
5c8124a0
AV		 1662
1663static void pl011_quiesce_irqs(struct uart_port *port)
1664{
a5820c24
DT		 1665 struct uart_amba_port *uap =
1666 container_of(port, struct uart_amba_port, port);
5c8124a0 1667
9f25bc51 1668 pl011_write(pl011_read(uap, REG_MIS), uap, REG_ICR);
5c8124a0
AV		 1669 /*
1670 * There is no way to clear TXIM as this is "ready to transmit IRQ", so
1671 * we simply mask it. start_tx() will unmask it.
1672 *
1673 * Note we can race with start_tx(), and if the race happens, the
1674 * polling user might get another interrupt just after we clear it.
1675 * But it should be OK and can happen even w/o the race, e.g.
1676 * controller immediately got some new data and raised the IRQ.
1677 *
1678 * And whoever uses polling routines assumes that it manages the device
1679 * (including tx queue), so we're also fine with start_tx()'s caller
1680 * side.
1681 */
9f25bc51
RK		 1682 pl011_write(pl011_read(uap, REG_IMSC) & ~UART011_TXIM, uap,
1683 REG_IMSC);
5c8124a0
AV		 1684}
1685
e643f87f 1686static int pl011_get_poll_char(struct uart_port *port)
84b5ae15 1687{
a5820c24
DT		 1688 struct uart_amba_port *uap =
1689 container_of(port, struct uart_amba_port, port);
84b5ae15
JW		 1690 unsigned int status;
1691
5c8124a0
AV		 1692 /*
1693 * The caller might need IRQs lowered, e.g. if used with KDB NMI
1694 * debugger.
1695 */
1696 pl011_quiesce_irqs(port);
1697
9f25bc51 1698 status = pl011_read(uap, REG_FR);
f5316b4a
JW		 1699 if (status & UART01x_FR_RXFE)
1700 return NO_POLL_CHAR;
84b5ae15 1701
9f25bc51 1702 return pl011_read(uap, REG_DR);
84b5ae15
JW		 1703}
1704
e643f87f 1705static void pl011_put_poll_char(struct uart_port *port,
84b5ae15
JW		 1706 unsigned char ch)
1707{
a5820c24
DT		 1708 struct uart_amba_port *uap =
1709 container_of(port, struct uart_amba_port, port);
84b5ae15 1710
9f25bc51 1711 while (pl011_read(uap, REG_FR) & UART01x_FR_TXFF)
2f2fd089 1712 cpu_relax();
84b5ae15 1713
9f25bc51 1714 pl011_write(ch, uap, REG_DR);
84b5ae15
JW		 1715}
1716
1717#endif /* CONFIG_CONSOLE_POLL */
1718
b3564c2c 1719static int pl011_hwinit(struct uart_port *port)
1da177e4 1720{
a5820c24
DT		 1721 struct uart_amba_port *uap =
1722 container_of(port, struct uart_amba_port, port);
1da177e4
LT		 1723 int retval;
1724
78d80c5a 1725 /* Optionaly enable pins to be muxed in and configured */
2b996fc5 1726 pinctrl_pm_select_default_state(port->dev);
78d80c5a 1727
1da177e4
LT		 1728 /*
1729 * Try to enable the clock producer.
1730 */
1c4c4394 1731 retval = clk_prepare_enable(uap->clk);
1da177e4 1732 if (retval)
7f6d942a 1733 return retval;
1da177e4
LT		 1734
1735 uap->port.uartclk = clk_get_rate(uap->clk);
1736
9b96fbac 1737 /* Clear pending error and receive interrupts */
75836339
RK		 1738 pl011_write(UART011_OEIS | UART011_BEIS | UART011_PEIS |
1739 UART011_FEIS | UART011_RTIS | UART011_RXIS,
9f25bc51 1740 uap, REG_ICR);
9b96fbac 1741
b3564c2c
AV		 1742 /*
1743 * Save interrupts enable mask, and enable RX interrupts in case if
1744 * the interrupt is used for NMI entry.
1745 */
9f25bc51
RK		 1746 uap->im = pl011_read(uap, REG_IMSC);
1747 pl011_write(UART011_RTIM | UART011_RXIM, uap, REG_IMSC);
b3564c2c 1748
574de559 1749 if (dev_get_platdata(uap->port.dev)) {
b3564c2c
AV		 1750 struct amba_pl011_data *plat;
1751
574de559 1752 plat = dev_get_platdata(uap->port.dev);
b3564c2c
AV		 1753 if (plat->init)
1754 plat->init();
1755 }
1756 return 0;
b3564c2c
AV		 1757}
1758
7fe9a5a9
RK		 1759static bool pl011_split_lcrh(const struct uart_amba_port *uap)
1760{
e4df9a80
RK		 1761 return pl011_reg_to_offset(uap, REG_LCRH_RX) !=
1762 pl011_reg_to_offset(uap, REG_LCRH_TX);
7fe9a5a9
RK		 1763}
1764
b60f2f66
JM		 1765static void pl011_write_lcr_h(struct uart_amba_port *uap, unsigned int lcr_h)
1766{
e4df9a80 1767 pl011_write(lcr_h, uap, REG_LCRH_RX);
7fe9a5a9 1768 if (pl011_split_lcrh(uap)) {
b60f2f66
JM		 1769 int i;
1770 /*
1771 * Wait 10 PCLKs before writing LCRH_TX register,
1772 * to get this delay write read only register 10 times
1773 */
1774 for (i = 0; i < 10; ++i)
9f25bc51 1775 pl011_write(0xff, uap, REG_MIS);
e4df9a80 1776 pl011_write(lcr_h, uap, REG_LCRH_TX);
b60f2f66
JM		 1777 }
1778}
1779
b0819465
BF		 1780static void pl011_release_irq(struct uart_amba_port *uap, unsigned int max_cnt)
1781{
1782 struct amba_device *amba_dev = container_of(uap->port.dev, struct amba_device, dev);
1783 int i;
1784
1785 for (i = 0; i < max_cnt; i++)
1786 if (amba_dev->irq[i])
1787 free_irq(amba_dev->irq[i], uap);
1788}
1789
867b8e8e
AP		 1790static int pl011_allocate_irq(struct uart_amba_port *uap)
1791{
b0819465
BF		 1792 int ret = 0;
1793 int i;
1794 unsigned int virq;
1795 struct amba_device *amba_dev = container_of(uap->port.dev, struct amba_device, dev);
1796
9f25bc51 1797 pl011_write(uap->im, uap, REG_IMSC);
867b8e8e 1798
b0819465
BF		 1799 for (i = 0; i < AMBA_NR_IRQS; i++) {
1800 virq = amba_dev->irq[i];
1801 if (virq == 0)
1802 break;
1803
1804 ret = request_irq(virq, pl011_int, IRQF_SHARED, dev_name(&amba_dev->dev), uap);
1805 if (ret) {
1806 dev_err(uap->port.dev, "request %u interrupt failed\n", virq);
1807 pl011_release_irq(uap, i - 1);
1808 break;
1809 }
1810 }
1811
1812 return ret;
867b8e8e
AP		 1813}
1814
1815/*
1816 * Enable interrupts, only timeouts when using DMA
1817 * if initial RX DMA job failed, start in interrupt mode
1818 * as well.
1819 */
1820static void pl011_enable_interrupts(struct uart_amba_port *uap)
1821{
4a7e625c
DM		 1822 unsigned int i;
1823
867b8e8e
AP		 1824 spin_lock_irq(&uap->port.lock);
1825
1826 /* Clear out any spuriously appearing RX interrupts */
9f25bc51 1827 pl011_write(UART011_RTIS | UART011_RXIS, uap, REG_ICR);
4a7e625c
DM		 1828
1829 /*
1830 * RXIS is asserted only when the RX FIFO transitions from below
1831 * to above the trigger threshold. If the RX FIFO is already
1832 * full to the threshold this can't happen and RXIS will now be
1833 * stuck off. Drain the RX FIFO explicitly to fix this:
1834 */
1835 for (i = 0; i < uap->fifosize * 2; ++i) {
1836 if (pl011_read(uap, REG_FR) & UART01x_FR_RXFE)
1837 break;
1838
1839 pl011_read(uap, REG_DR);
1840 }
1841
867b8e8e
AP		 1842 uap->im = UART011_RTIM;
1843 if (!pl011_dma_rx_running(uap))
1844 uap->im |= UART011_RXIM;
9f25bc51 1845 pl011_write(uap->im, uap, REG_IMSC);
867b8e8e
AP		 1846 spin_unlock_irq(&uap->port.lock);
1847}
1848
b3564c2c
AV		 1849static int pl011_startup(struct uart_port *port)
1850{
a5820c24
DT		 1851 struct uart_amba_port *uap =
1852 container_of(port, struct uart_amba_port, port);
734745ca 1853 unsigned int cr;
b3564c2c
AV		 1854 int retval;
1855
1856 retval = pl011_hwinit(port);
1857 if (retval)
1858 goto clk_dis;
1859
867b8e8e 1860 retval = pl011_allocate_irq(uap);
1da177e4
LT		 1861 if (retval)
1862 goto clk_dis;
1863
9f25bc51 1864 pl011_write(uap->vendor->ifls, uap, REG_IFLS);
1da177e4 1865
734745ca 1866 spin_lock_irq(&uap->port.lock);
570d2910 1867
d8d8ffa4
SKS		 1868 /* restore RTS and DTR */
1869 cr = uap->old_cr & (UART011_CR_RTS | UART011_CR_DTR);
8d479237
LS		 1870 cr |= UART01x_CR_UARTEN | UART011_CR_RXE;
1871
1872 if (port->rs485.flags & SER_RS485_ENABLED) {
1873 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND)
1874 cr &= ~UART011_CR_RTS;
1875 else
1876 cr |= UART011_CR_RTS;
1877 } else {
1878 cr |= UART011_CR_TXE;
1879 }
1880
9f25bc51 1881 pl011_write(cr, uap, REG_CR);
1da177e4 1882
fe433907
JM		 1883 spin_unlock_irq(&uap->port.lock);
1884
1da177e4
LT		 1885 /*
1886 * initialise the old status of the modem signals
1887 */
9f25bc51 1888 uap->old_status = pl011_read(uap, REG_FR) & UART01x_FR_MODEM_ANY;
1da177e4 1889
68b65f73
RK		 1890 /* Startup DMA */
1891 pl011_dma_startup(uap);
1892
867b8e8e 1893 pl011_enable_interrupts(uap);
1da177e4
LT		 1894
1895 return 0;
1896
1897 clk_dis:
1c4c4394 1898 clk_disable_unprepare(uap->clk);
1da177e4
LT		 1899 return retval;
1900}
1901
0dd1e247
AP		 1902static int sbsa_uart_startup(struct uart_port *port)
1903{
1904 struct uart_amba_port *uap =
1905 container_of(port, struct uart_amba_port, port);
1906 int retval;
1907
1908 retval = pl011_hwinit(port);
1909 if (retval)
1910 return retval;
1911
1912 retval = pl011_allocate_irq(uap);
1913 if (retval)
1914 return retval;
1915
1916 /* The SBSA UART does not support any modem status lines. */
1917 uap->old_status = 0;
1918
1919 pl011_enable_interrupts(uap);
1920
1921 return 0;
1922}
1923
ec489aa8
LW		 1924static void pl011_shutdown_channel(struct uart_amba_port *uap,
1925 unsigned int lcrh)
1926{
f11c9841 1927 unsigned long val;
ec489aa8 1928
b2a4e24c 1929 val = pl011_read(uap, lcrh);
f11c9841 1930 val &= ~(UART01x_LCRH_BRK | UART01x_LCRH_FEN);
b2a4e24c 1931 pl011_write(val, uap, lcrh);
ec489aa8
LW		 1932}
1933
95166a3f
AP		 1934/*
1935 * disable the port. It should not disable RTS and DTR.
1936 * Also RTS and DTR state should be preserved to restore
1937 * it during startup().
1938 */
1939static void pl011_disable_uart(struct uart_amba_port *uap)
1da177e4 1940{
d8d8ffa4 1941 unsigned int cr;
1da177e4 1942
2a76fa28 1943 uap->port.status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS);
fe433907 1944 spin_lock_irq(&uap->port.lock);
9f25bc51 1945 cr = pl011_read(uap, REG_CR);
d8d8ffa4
SKS		 1946 uap->old_cr = cr;
1947 cr &= UART011_CR_RTS | UART011_CR_DTR;
1948 cr |= UART01x_CR_UARTEN | UART011_CR_TXE;
9f25bc51 1949 pl011_write(cr, uap, REG_CR);
fe433907 1950 spin_unlock_irq(&uap->port.lock);
1da177e4
LT		 1951
1952 /*
1953 * disable break condition and fifos
1954 */
e4df9a80 1955 pl011_shutdown_channel(uap, REG_LCRH_RX);
7fe9a5a9 1956 if (pl011_split_lcrh(uap))
e4df9a80 1957 pl011_shutdown_channel(uap, REG_LCRH_TX);
95166a3f
AP		 1958}
1959
1960static void pl011_disable_interrupts(struct uart_amba_port *uap)
1961{
1962 spin_lock_irq(&uap->port.lock);
1963
1964 /* mask all interrupts and clear all pending ones */
1965 uap->im = 0;
9f25bc51
RK		 1966 pl011_write(uap->im, uap, REG_IMSC);
1967 pl011_write(0xffff, uap, REG_ICR);
95166a3f
AP		 1968
1969 spin_unlock_irq(&uap->port.lock);
1970}
1971
1972static void pl011_shutdown(struct uart_port *port)
1973{
1974 struct uart_amba_port *uap =
1975 container_of(port, struct uart_amba_port, port);
1976
1977 pl011_disable_interrupts(uap);
1978
1979 pl011_dma_shutdown(uap);
1980
8d479237
LS		 1981 if ((port->rs485.flags & SER_RS485_ENABLED) && uap->rs485_tx_started)
1982 pl011_rs485_tx_stop(uap);
1983
b0819465 1984 pl011_release_irq(uap, AMBA_NR_IRQS);
95166a3f
AP		 1985
1986 pl011_disable_uart(uap);
1da177e4
LT		 1987
1988 /*
1989 * Shut down the clock producer
1990 */
1c4c4394 1991 clk_disable_unprepare(uap->clk);
78d80c5a 1992 /* Optionally let pins go into sleep states */
2b996fc5 1993 pinctrl_pm_select_sleep_state(port->dev);
c16d51a3 1994
574de559 1995 if (dev_get_platdata(uap->port.dev)) {
c16d51a3
SKS		 1996 struct amba_pl011_data *plat;
1997
574de559 1998 plat = dev_get_platdata(uap->port.dev);
c16d51a3
SKS		 1999 if (plat->exit)
2000 plat->exit();
2001 }
2002
36f339d1
PH		 2003 if (uap->port.ops->flush_buffer)
2004 uap->port.ops->flush_buffer(port);
1da177e4
LT		 2005}
2006
0dd1e247
AP		 2007static void sbsa_uart_shutdown(struct uart_port *port)
2008{
2009 struct uart_amba_port *uap =
2010 container_of(port, struct uart_amba_port, port);
2011
2012 pl011_disable_interrupts(uap);
2013
b0819465 2014 pl011_release_irq(uap, AMBA_NR_IRQS);
0dd1e247
AP		 2015
2016 if (uap->port.ops->flush_buffer)
2017 uap->port.ops->flush_buffer(port);
2018}
2019
ef5a9358
AP		 2020static void
2021pl011_setup_status_masks(struct uart_port *port, struct ktermios *termios)
2022{
2023 port->read_status_mask = UART011_DR_OE | 255;
2024 if (termios->c_iflag & INPCK)
2025 port->read_status_mask |= UART011_DR_FE | UART011_DR_PE;
2026 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
2027 port->read_status_mask |= UART011_DR_BE;
2028
2029 /*
2030 * Characters to ignore
2031 */
2032 port->ignore_status_mask = 0;
2033 if (termios->c_iflag & IGNPAR)
2034 port->ignore_status_mask |= UART011_DR_FE | UART011_DR_PE;
2035 if (termios->c_iflag & IGNBRK) {
2036 port->ignore_status_mask |= UART011_DR_BE;
2037 /*
2038 * If we're ignoring parity and break indicators,
2039 * ignore overruns too (for real raw support).
2040 */
2041 if (termios->c_iflag & IGNPAR)
2042 port->ignore_status_mask |= UART011_DR_OE;
2043 }
2044
2045 /*
2046 * Ignore all characters if CREAD is not set.
2047 */
2048 if ((termios->c_cflag & CREAD) == 0)
2049 port->ignore_status_mask |= UART_DUMMY_DR_RX;
2050}
2051
1da177e4 2052static void
606d099c
AC		 2053pl011_set_termios(struct uart_port *port, struct ktermios *termios,
2054 struct ktermios *old)
1da177e4 2055{
a5820c24
DT		 2056 struct uart_amba_port *uap =
2057 container_of(port, struct uart_amba_port, port);
1da177e4
LT		 2058 unsigned int lcr_h, old_cr;
2059 unsigned long flags;
c19f12b5 2060 unsigned int baud, quot, clkdiv;
8d479237 2061 unsigned int bits;
c19f12b5
RK		 2062
2063 if (uap->vendor->oversampling)
2064 clkdiv = 8;
2065 else
2066 clkdiv = 16;
1da177e4
LT		 2067
2068 /*
2069 * Ask the core to calculate the divisor for us.
2070 */
ac3e3fb4 2071 baud = uart_get_baud_rate(port, termios, old, 0,
c19f12b5 2072 port->uartclk / clkdiv);
89fa28db 2073#ifdef CONFIG_DMA_ENGINE
cb06ff10
CM		 2074 /*
2075 * Adjust RX DMA polling rate with baud rate if not specified.
2076 */
2077 if (uap->dmarx.auto_poll_rate)
2078 uap->dmarx.poll_rate = DIV_ROUND_UP(10000000, baud);
89fa28db 2079#endif
ac3e3fb4
LW		 2080
2081 if (baud > port->uartclk/16)
2082 quot = DIV_ROUND_CLOSEST(port->uartclk * 8, baud);
2083 else
2084 quot = DIV_ROUND_CLOSEST(port->uartclk * 4, baud);
1da177e4
LT		 2085
2086 switch (termios->c_cflag & CSIZE) {
2087 case CS5:
2088 lcr_h = UART01x_LCRH_WLEN_5;
2089 break;
2090 case CS6:
2091 lcr_h = UART01x_LCRH_WLEN_6;
2092 break;
2093 case CS7:
2094 lcr_h = UART01x_LCRH_WLEN_7;
2095 break;
2096 default: // CS8
2097 lcr_h = UART01x_LCRH_WLEN_8;
2098 break;
2099 }
2100 if (termios->c_cflag & CSTOPB)
2101 lcr_h |= UART01x_LCRH_STP2;
2102 if (termios->c_cflag & PARENB) {
2103 lcr_h |= UART01x_LCRH_PEN;
2104 if (!(termios->c_cflag & PARODD))
2105 lcr_h |= UART01x_LCRH_EPS;
bb70002c
ES		 2106 if (termios->c_cflag & CMSPAR)
2107 lcr_h |= UART011_LCRH_SPS;
1da177e4 2108 }
ffca2b11 2109 if (uap->fifosize > 1)
1da177e4
LT		 2110 lcr_h |= UART01x_LCRH_FEN;
2111
8d479237
LS		 2112 bits = tty_get_frame_size(termios->c_cflag);
2113
1da177e4
LT		 2114 spin_lock_irqsave(&port->lock, flags);
2115
2116 /*
2117 * Update the per-port timeout.
2118 */
2119 uart_update_timeout(port, termios->c_cflag, baud);
2120
8d479237
LS		 2121 /*
2122 * Calculate the approximated time it takes to transmit one character
2123 * with the given baud rate. We use this as the poll interval when we
2124 * wait for the tx queue to empty.
2125 */
2126 uap->rs485_tx_drain_interval = (bits * 1000 * 1000) / baud;
2127
ef5a9358 2128 pl011_setup_status_masks(port, termios);
1da177e4
LT		 2129
2130 if (UART_ENABLE_MS(port, termios->c_cflag))
2131 pl011_enable_ms(port);
2132
8d479237
LS		 2133 if (port->rs485.flags & SER_RS485_ENABLED)
2134 termios->c_cflag &= ~CRTSCTS;
2135
1da177e4 2136 /* first, disable everything */
9f25bc51
RK		 2137 old_cr = pl011_read(uap, REG_CR);
2138 pl011_write(0, uap, REG_CR);
1da177e4 2139
3b43816f
RV		 2140 if (termios->c_cflag & CRTSCTS) {
2141 if (old_cr & UART011_CR_RTS)
2142 old_cr |= UART011_CR_RTSEN;
2143
2144 old_cr |= UART011_CR_CTSEN;
2a76fa28 2145 port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS;
3b43816f
RV		 2146 } else {
2147 old_cr &= ~(UART011_CR_CTSEN | UART011_CR_RTSEN);
2a76fa28 2148 port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS);
3b43816f
RV		 2149 }
2150
c19f12b5
RK		 2151 if (uap->vendor->oversampling) {
2152 if (baud > port->uartclk / 16)
ac3e3fb4
LW		 2153 old_cr |= ST_UART011_CR_OVSFACT;
2154 else
2155 old_cr &= ~ST_UART011_CR_OVSFACT;
2156 }
2157
c5dd553b
LW		 2158 /*
2159 * Workaround for the ST Micro oversampling variants to
2160 * increase the bitrate slightly, by lowering the divisor,
2161 * to avoid delayed sampling of start bit at high speeds,
2162 * else we see data corruption.
2163 */
2164 if (uap->vendor->oversampling) {
2165 if ((baud >= 3000000) && (baud < 3250000) && (quot > 1))
2166 quot -= 1;
2167 else if ((baud > 3250000) && (quot > 2))
2168 quot -= 2;
2169 }
1da177e4 2170 /* Set baud rate */
9f25bc51
RK		 2171 pl011_write(quot & 0x3f, uap, REG_FBRD);
2172 pl011_write(quot >> 6, uap, REG_IBRD);
1da177e4
LT		 2173
2174 /*
2175 * ----------v----------v----------v----------v-----
e4df9a80 2176 * NOTE: REG_LCRH_TX and REG_LCRH_RX MUST BE WRITTEN AFTER
9f25bc51 2177 * REG_FBRD & REG_IBRD.
1da177e4
LT		 2178 * ----------^----------^----------^----------^-----
2179 */
b60f2f66 2180 pl011_write_lcr_h(uap, lcr_h);
9f25bc51 2181 pl011_write(old_cr, uap, REG_CR);
1da177e4
LT		 2182
2183 spin_unlock_irqrestore(&port->lock, flags);
2184}
2185
0dd1e247
AP		 2186static void
2187sbsa_uart_set_termios(struct uart_port *port, struct ktermios *termios,
2188 struct ktermios *old)
2189{
2190 struct uart_amba_port *uap =
2191 container_of(port, struct uart_amba_port, port);
2192 unsigned long flags;
2193
2194 tty_termios_encode_baud_rate(termios, uap->fixed_baud, uap->fixed_baud);
2195
2196 /* The SBSA UART only supports 8n1 without hardware flow control. */
2197 termios->c_cflag &= ~(CSIZE | CSTOPB | PARENB | PARODD);
2198 termios->c_cflag &= ~(CMSPAR | CRTSCTS);
2199 termios->c_cflag |= CS8 | CLOCAL;
2200
2201 spin_lock_irqsave(&port->lock, flags);
2202 uart_update_timeout(port, CS8, uap->fixed_baud);
2203 pl011_setup_status_masks(port, termios);
2204 spin_unlock_irqrestore(&port->lock, flags);
2205}
2206
1da177e4
LT		 2207static const char *pl011_type(struct uart_port *port)
2208{
a5820c24
DT		 2209 struct uart_amba_port *uap =
2210 container_of(port, struct uart_amba_port, port);
e8a7ba86 2211 return uap->port.type == PORT_AMBA ? uap->type : NULL;
1da177e4
LT		 2212}
2213
2214/*
2215 * Release the memory region(s) being used by 'port'
2216 */
e643f87f 2217static void pl011_release_port(struct uart_port *port)
1da177e4
LT		 2218{
2219 release_mem_region(port->mapbase, SZ_4K);
2220}
2221
2222/*
2223 * Request the memory region(s) being used by 'port'
2224 */
e643f87f 2225static int pl011_request_port(struct uart_port *port)
1da177e4
LT		 2226{
2227 return request_mem_region(port->mapbase, SZ_4K, "uart-pl011")
2228 != NULL ? 0 : -EBUSY;
2229}
2230
2231/*
2232 * Configure/autoconfigure the port.
2233 */
e643f87f 2234static void pl011_config_port(struct uart_port *port, int flags)
1da177e4
LT		 2235{
2236 if (flags & UART_CONFIG_TYPE) {
2237 port->type = PORT_AMBA;
e643f87f 2238 pl011_request_port(port);
1da177e4
LT		 2239 }
2240}
2241
2242/*
2243 * verify the new serial_struct (for TIOCSSERIAL).
2244 */
e643f87f 2245static int pl011_verify_port(struct uart_port *port, struct serial_struct *ser)
1da177e4
LT		 2246{
2247 int ret = 0;
2248 if (ser->type != PORT_UNKNOWN && ser->type != PORT_AMBA)
2249 ret = -EINVAL;
a62c4133 2250 if (ser->irq < 0 || ser->irq >= nr_irqs)
1da177e4
LT		 2251 ret = -EINVAL;
2252 if (ser->baud_base < 9600)
2253 ret = -EINVAL;
2254 return ret;
2255}
2256
8d479237
LS		 2257static int pl011_rs485_config(struct uart_port *port,
2258 struct serial_rs485 *rs485)
2259{
2260 struct uart_amba_port *uap =
2261 container_of(port, struct uart_amba_port, port);
2262
2263 /* pick sane settings if the user hasn't */
2264 if (!(rs485->flags & SER_RS485_RTS_ON_SEND) ==
2265 !(rs485->flags & SER_RS485_RTS_AFTER_SEND)) {
2266 rs485->flags |= SER_RS485_RTS_ON_SEND;
2267 rs485->flags &= ~SER_RS485_RTS_AFTER_SEND;
2268 }
2269 /* clamp the delays to [0, 100ms] */
2270 rs485->delay_rts_before_send = min(rs485->delay_rts_before_send, 100U);
2271 rs485->delay_rts_after_send = min(rs485->delay_rts_after_send, 100U);
2272 memset(rs485->padding, 0, sizeof(rs485->padding));
2273
2274 if (port->rs485.flags & SER_RS485_ENABLED)
2275 pl011_rs485_tx_stop(uap);
2276
2277 /* Set new configuration */
2278 port->rs485 = *rs485;
2279
2280 /* Make sure auto RTS is disabled */
2281 if (port->rs485.flags & SER_RS485_ENABLED) {
2282 u32 cr = pl011_read(uap, REG_CR);
2283
2284 cr &= ~UART011_CR_RTSEN;
2285 pl011_write(cr, uap, REG_CR);
2286 port->status &= ~UPSTAT_AUTORTS;
2287 }
2288
2289 return 0;
2290}
2291
2331e068 2292static const struct uart_ops amba_pl011_pops = {
e643f87f 2293 .tx_empty = pl011_tx_empty,
1da177e4 2294 .set_mctrl = pl011_set_mctrl,
e643f87f 2295 .get_mctrl = pl011_get_mctrl,
1da177e4
LT		 2296 .stop_tx = pl011_stop_tx,
2297 .start_tx = pl011_start_tx,
2298 .stop_rx = pl011_stop_rx,
2299 .enable_ms = pl011_enable_ms,
2300 .break_ctl = pl011_break_ctl,
2301 .startup = pl011_startup,
2302 .shutdown = pl011_shutdown,
68b65f73 2303 .flush_buffer = pl011_dma_flush_buffer,
1da177e4
LT		 2304 .set_termios = pl011_set_termios,
2305 .type = pl011_type,
e643f87f
LW		 2306 .release_port = pl011_release_port,
2307 .request_port = pl011_request_port,
2308 .config_port = pl011_config_port,
2309 .verify_port = pl011_verify_port,
84b5ae15 2310#ifdef CONFIG_CONSOLE_POLL
b3564c2c 2311 .poll_init = pl011_hwinit,
e643f87f
LW		 2312 .poll_get_char = pl011_get_poll_char,
2313 .poll_put_char = pl011_put_poll_char,
84b5ae15 2314#endif
1da177e4
LT		 2315};
2316
0dd1e247
AP		 2317static void sbsa_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
2318{
2319}
2320
2321static unsigned int sbsa_uart_get_mctrl(struct uart_port *port)
2322{
2323 return 0;
2324}
2325
2326static const struct uart_ops sbsa_uart_pops = {
2327 .tx_empty = pl011_tx_empty,
2328 .set_mctrl = sbsa_uart_set_mctrl,
2329 .get_mctrl = sbsa_uart_get_mctrl,
2330 .stop_tx = pl011_stop_tx,
2331 .start_tx = pl011_start_tx,
2332 .stop_rx = pl011_stop_rx,
2333 .startup = sbsa_uart_startup,
2334 .shutdown = sbsa_uart_shutdown,
2335 .set_termios = sbsa_uart_set_termios,
2336 .type = pl011_type,
2337 .release_port = pl011_release_port,
2338 .request_port = pl011_request_port,
2339 .config_port = pl011_config_port,
2340 .verify_port = pl011_verify_port,
2341#ifdef CONFIG_CONSOLE_POLL
2342 .poll_init = pl011_hwinit,
2343 .poll_get_char = pl011_get_poll_char,
2344 .poll_put_char = pl011_put_poll_char,
2345#endif
2346};
2347
1da177e4
LT		 2348static struct uart_amba_port *amba_ports[UART_NR];
2349
2350#ifdef CONFIG_SERIAL_AMBA_PL011_CONSOLE
2351
d358788f 2352static void pl011_console_putchar(struct uart_port *port, int ch)
1da177e4 2353{
a5820c24
DT		 2354 struct uart_amba_port *uap =
2355 container_of(port, struct uart_amba_port, port);
1da177e4 2356
9f25bc51 2357 while (pl011_read(uap, REG_FR) & UART01x_FR_TXFF)
2f2fd089 2358 cpu_relax();
9f25bc51 2359 pl011_write(ch, uap, REG_DR);
1da177e4
LT		 2360}
2361
2362static void
2363pl011_console_write(struct console *co, const char *s, unsigned int count)
2364{
2365 struct uart_amba_port *uap = amba_ports[co->index];
2f2fd089 2366 unsigned int old_cr = 0, new_cr;
ef605fdb
RV		 2367 unsigned long flags;
2368 int locked = 1;
1da177e4
LT		 2369
2370 clk_enable(uap->clk);
2371
ef605fdb
RV		 2372 local_irq_save(flags);
2373 if (uap->port.sysrq)
2374 locked = 0;
2375 else if (oops_in_progress)
2376 locked = spin_trylock(&uap->port.lock);
2377 else
2378 spin_lock(&uap->port.lock);
2379
1da177e4
LT		 2380 /*
2381 * First save the CR then disable the interrupts
2382 */
71eec483 2383 if (!uap->vendor->always_enabled) {
9f25bc51 2384 old_cr = pl011_read(uap, REG_CR);
71eec483
AP		 2385 new_cr = old_cr & ~UART011_CR_CTSEN;
2386 new_cr |= UART01x_CR_UARTEN | UART011_CR_TXE;
9f25bc51 2387 pl011_write(new_cr, uap, REG_CR);
71eec483 2388 }
1da177e4 2389
d358788f 2390 uart_console_write(&uap->port, s, count, pl011_console_putchar);
1da177e4
LT		 2391
2392 /*
d8a4995b
CC		 2393 * Finally, wait for transmitter to become empty and restore the
2394 * TCR. Allow feature register bits to be inverted to work around
2395 * errata.
1da177e4 2396 */
d8a4995b
CC		 2397 while ((pl011_read(uap, REG_FR) ^ uap->vendor->inv_fr)
2398 & uap->vendor->fr_busy)
2f2fd089 2399 cpu_relax();
71eec483 2400 if (!uap->vendor->always_enabled)
9f25bc51 2401 pl011_write(old_cr, uap, REG_CR);
1da177e4 2402
ef605fdb
RV		 2403 if (locked)
2404 spin_unlock(&uap->port.lock);
2405 local_irq_restore(flags);
2406
1da177e4
LT		 2407 clk_disable(uap->clk);
2408}
2409
27afac93
LW		 2410static void pl011_console_get_options(struct uart_amba_port *uap, int *baud,
2411 int *parity, int *bits)
1da177e4 2412{
9f25bc51 2413 if (pl011_read(uap, REG_CR) & UART01x_CR_UARTEN) {
1da177e4
LT		 2414 unsigned int lcr_h, ibrd, fbrd;
2415
e4df9a80 2416 lcr_h = pl011_read(uap, REG_LCRH_TX);
1da177e4
LT		 2417
2418 *parity = 'n';
2419 if (lcr_h & UART01x_LCRH_PEN) {
2420 if (lcr_h & UART01x_LCRH_EPS)
2421 *parity = 'e';
2422 else
2423 *parity = 'o';
2424 }
2425
2426 if ((lcr_h & 0x60) == UART01x_LCRH_WLEN_7)
2427 *bits = 7;
2428 else
2429 *bits = 8;
2430
9f25bc51
RK		 2431 ibrd = pl011_read(uap, REG_IBRD);
2432 fbrd = pl011_read(uap, REG_FBRD);
1da177e4
LT		 2433
2434 *baud = uap->port.uartclk * 4 / (64 * ibrd + fbrd);
ac3e3fb4 2435
c19f12b5 2436 if (uap->vendor->oversampling) {
9f25bc51 2437 if (pl011_read(uap, REG_CR)
ac3e3fb4
LW		 2438 & ST_UART011_CR_OVSFACT)
2439 *baud *= 2;
2440 }
1da177e4
LT		 2441 }
2442}
2443
27afac93 2444static int pl011_console_setup(struct console *co, char *options)
1da177e4
LT		 2445{
2446 struct uart_amba_port *uap;
2447 int baud = 38400;
2448 int bits = 8;
2449 int parity = 'n';
2450 int flow = 'n';
4b4851c6 2451 int ret;
1da177e4
LT		 2452
2453 /*
2454 * Check whether an invalid uart number has been specified, and
2455 * if so, search for the first available port that does have
2456 * console support.
2457 */
2458 if (co->index >= UART_NR)
2459 co->index = 0;
2460 uap = amba_ports[co->index];
d28122a5
RK		 2461 if (!uap)
2462 return -ENODEV;
1da177e4 2463
78d80c5a 2464 /* Allow pins to be muxed in and configured */
2b996fc5 2465 pinctrl_pm_select_default_state(uap->port.dev);
78d80c5a 2466
4b4851c6
RK		 2467 ret = clk_prepare(uap->clk);
2468 if (ret)
2469 return ret;
2470
574de559 2471 if (dev_get_platdata(uap->port.dev)) {
c16d51a3
SKS		 2472 struct amba_pl011_data *plat;
2473
574de559 2474 plat = dev_get_platdata(uap->port.dev);
c16d51a3
SKS		 2475 if (plat->init)
2476 plat->init();
2477 }
2478
1da177e4
LT		 2479 uap->port.uartclk = clk_get_rate(uap->clk);
2480
cefc2d1d
AP		 2481 if (uap->vendor->fixed_options) {
2482 baud = uap->fixed_baud;
2483 } else {
2484 if (options)
2485 uart_parse_options(options,
2486 &baud, &parity, &bits, &flow);
2487 else
2488 pl011_console_get_options(uap, &baud, &parity, &bits);
2489 }
1da177e4
LT		 2490
2491 return uart_set_options(&uap->port, co, baud, parity, bits, flow);
2492}
2493
10879ae5
AM		 2494/**
2495 * pl011_console_match - non-standard console matching
2496 * @co: registering console
2497 * @name: name from console command line
2498 * @idx: index from console command line
2499 * @options: ptr to option string from console command line
2500 *
2501 * Only attempts to match console command lines of the form:
2502 * console=pl011,mmio|mmio32,<addr>[,<options>]
2503 * console=pl011,0x<addr>[,<options>]
2504 * This form is used to register an initial earlycon boot console and
2505 * replace it with the amba_console at pl011 driver init.
2506 *
2507 * Performs console setup for a match (as required by interface)
2508 * If no <options> are specified, then assume the h/w is already setup.
2509 *
2510 * Returns 0 if console matches; otherwise non-zero to use default matching
2511 */
27afac93
LW		 2512static int pl011_console_match(struct console *co, char *name, int idx,
2513 char *options)
10879ae5
AM		 2514{
2515 unsigned char iotype;
2516 resource_size_t addr;
2517 int i;
2518
37ef38f3
TT		 2519 /*
2520 * Systems affected by the Qualcomm Technologies QDF2400 E44 erratum
2521 * have a distinct console name, so make sure we check for that.
2522 * The actual implementation of the erratum occurs in the probe
2523 * function.
2524 */
2525 if ((strcmp(name, "qdf2400_e44") != 0) && (strcmp(name, "pl011") != 0))
10879ae5
AM		 2526 return -ENODEV;
2527
2528 if (uart_parse_earlycon(options, &iotype, &addr, &options))
2529 return -ENODEV;
2530
2531 if (iotype != UPIO_MEM && iotype != UPIO_MEM32)
2532 return -ENODEV;
2533
2534 /* try to match the port specified on the command line */
2535 for (i = 0; i < ARRAY_SIZE(amba_ports); i++) {
2536 struct uart_port *port;
2537
2538 if (!amba_ports[i])
2539 continue;
2540
2541 port = &amba_ports[i]->port;
2542
2543 if (port->mapbase != addr)
2544 continue;
2545
2546 co->index = i;
2547 port->cons = co;
2548 return pl011_console_setup(co, options);
2549 }
2550
2551 return -ENODEV;
2552}
2553
2d93486c 2554static struct uart_driver amba_reg;
1da177e4
LT		 2555static struct console amba_console = {
2556 .name = "ttyAMA",
2557 .write = pl011_console_write,
2558 .device = uart_console_device,
2559 .setup = pl011_console_setup,
10879ae5 2560 .match = pl011_console_match,
7951ffc9 2561 .flags = CON_PRINTBUFFER | CON_ANYTIME,
1da177e4
LT		 2562 .index = -1,
2563 .data = &amba_reg,
2564};
2565
2566#define AMBA_CONSOLE (&amba_console)
0d3c673e 2567
d8a4995b
CC		 2568static void qdf2400_e44_putc(struct uart_port *port, int c)
2569{
2570 while (readl(port->membase + UART01x_FR) & UART01x_FR_TXFF)
2571 cpu_relax();
2572 writel(c, port->membase + UART01x_DR);
2573 while (!(readl(port->membase + UART01x_FR) & UART011_FR_TXFE))
2574 cpu_relax();
2575}
2576
2577static void qdf2400_e44_early_write(struct console *con, const char *s, unsigned n)
2578{
2579 struct earlycon_device *dev = con->data;
2580
2581 uart_console_write(&dev->port, s, n, qdf2400_e44_putc);
2582}
2583
0d3c673e
RH		 2584static void pl011_putc(struct uart_port *port, int c)
2585{
cdf091ca 2586 while (readl(port->membase + UART01x_FR) & UART01x_FR_TXFF)
2f2fd089 2587 cpu_relax();
3b78fae7
TT		 2588 if (port->iotype == UPIO_MEM32)
2589 writel(c, port->membase + UART01x_DR);
2590 else
2591 writeb(c, port->membase + UART01x_DR);
e06690bf 2592 while (readl(port->membase + UART01x_FR) & UART01x_FR_BUSY)
2f2fd089 2593 cpu_relax();
0d3c673e
RH		 2594}
2595
2596static void pl011_early_write(struct console *con, const char *s, unsigned n)
2597{
2598 struct earlycon_device *dev = con->data;
2599
2600 uart_console_write(&dev->port, s, n, pl011_putc);
2601}
2602
195867ff
SG		 2603#ifdef CONFIG_CONSOLE_POLL
2604static int pl011_getc(struct uart_port *port)
2605{
2606 if (readl(port->membase + UART01x_FR) & UART01x_FR_RXFE)
2607 return NO_POLL_CHAR;
2608
2609 if (port->iotype == UPIO_MEM32)
2610 return readl(port->membase + UART01x_DR);
2611 else
2612 return readb(port->membase + UART01x_DR);
2613}
2614
2615static int pl011_early_read(struct console *con, char *s, unsigned int n)
2616{
2617 struct earlycon_device *dev = con->data;
2618 int ch, num_read = 0;
2619
2620 while (num_read < n) {
2621 ch = pl011_getc(&dev->port);
2622 if (ch == NO_POLL_CHAR)
2623 break;
2624
2625 s[num_read++] = ch;
2626 }
2627
2628 return num_read;
2629}
2630#else
2631#define pl011_early_read NULL
2632#endif
2633
e53e597f
TT		 2634/*
2635 * On non-ACPI systems, earlycon is enabled by specifying
2636 * "earlycon=pl011,<address>" on the kernel command line.
2637 *
2638 * On ACPI ARM64 systems, an "early" console is enabled via the SPCR table,
2639 * by specifying only "earlycon" on the command line. Because it requires
2640 * SPCR, the console starts after ACPI is parsed, which is later than a
2641 * traditional early console.
2642 *
2643 * To get the traditional early console that starts before ACPI is parsed,
2644 * specify the full "earlycon=pl011,<address>" option.
2645 */
0d3c673e
RH		 2646static int __init pl011_early_console_setup(struct earlycon_device *device,
2647 const char *opt)
2648{
2649 if (!device->port.membase)
2650 return -ENODEV;
2651
5a0722b8 2652 device->con->write = pl011_early_write;
195867ff 2653 device->con->read = pl011_early_read;
e53e597f 2654
0d3c673e
RH		 2655 return 0;
2656}
45e0f0f5 2657OF_EARLYCON_DECLARE(pl011, "arm,pl011", pl011_early_console_setup);
fcb32159 2658OF_EARLYCON_DECLARE(pl011, "arm,sbsa-uart", pl011_early_console_setup);
5a0722b8
TT		 2659
2660/*
2661 * On Qualcomm Datacenter Technologies QDF2400 SOCs affected by
2662 * Erratum 44, traditional earlycon can be enabled by specifying
2663 * "earlycon=qdf2400_e44,<address>". Any options are ignored.
2664 *
2665 * Alternatively, you can just specify "earlycon", and the early console
2666 * will be enabled with the information from the SPCR table. In this
2667 * case, the SPCR code will detect the need for the E44 work-around,
2668 * and set the console name to "qdf2400_e44".
2669 */
2670static int __init
2671qdf2400_e44_early_console_setup(struct earlycon_device *device,
2672 const char *opt)
2673{
2674 if (!device->port.membase)
2675 return -ENODEV;
2676
2677 device->con->write = qdf2400_e44_early_write;
2678 return 0;
2679}
2680EARLYCON_DECLARE(qdf2400_e44, qdf2400_e44_early_console_setup);
0d3c673e 2681
1da177e4
LT		 2682#else
2683#define AMBA_CONSOLE NULL
2684#endif
2685
2686static struct uart_driver amba_reg = {
2687 .owner = THIS_MODULE,
2688 .driver_name = "ttyAMA",
2689 .dev_name = "ttyAMA",
2690 .major = SERIAL_AMBA_MAJOR,
2691 .minor = SERIAL_AMBA_MINOR,
2692 .nr = UART_NR,
2693 .cons = AMBA_CONSOLE,
2694};
2695
32614aad
ML		 2696static int pl011_probe_dt_alias(int index, struct device *dev)
2697{
2698 struct device_node *np;
2699 static bool seen_dev_with_alias = false;
2700 static bool seen_dev_without_alias = false;
2701 int ret = index;
2702
2703 if (!IS_ENABLED(CONFIG_OF))
2704 return ret;
2705
2706 np = dev->of_node;
2707 if (!np)
2708 return ret;
2709
2710 ret = of_alias_get_id(np, "serial");
287980e4 2711 if (ret < 0) {
32614aad
ML		 2712 seen_dev_without_alias = true;
2713 ret = index;
2714 } else {
2715 seen_dev_with_alias = true;
2716 if (ret >= ARRAY_SIZE(amba_ports) || amba_ports[ret] != NULL) {
2717 dev_warn(dev, "requested serial port %d not available.\n", ret);
2718 ret = index;
2719 }
2720 }
2721
2722 if (seen_dev_with_alias && seen_dev_without_alias)
2723 dev_warn(dev, "aliased and non-aliased serial devices found in device tree. Serial port enumeration may be unpredictable.\n");
2724
2725 return ret;
2726}
2727
49bb3c86
AP		 2728/* unregisters the driver also if no more ports are left */
2729static void pl011_unregister_port(struct uart_amba_port *uap)
2730{
2731 int i;
2732 bool busy = false;
2733
2734 for (i = 0; i < ARRAY_SIZE(amba_ports); i++) {
2735 if (amba_ports[i] == uap)
2736 amba_ports[i] = NULL;
2737 else if (amba_ports[i])
2738 busy = true;
2739 }
2740 pl011_dma_remove(uap);
2741 if (!busy)
2742 uart_unregister_driver(&amba_reg);
2743}
2744
3873e2d7 2745static int pl011_find_free_port(void)
1da177e4 2746{
3873e2d7 2747 int i;
1da177e4
LT		 2748
2749 for (i = 0; i < ARRAY_SIZE(amba_ports); i++)
2750 if (amba_ports[i] == NULL)
3873e2d7 2751 return i;
1da177e4 2752
3873e2d7
AP		 2753 return -EBUSY;
2754}
1da177e4 2755
8d479237
LS		 2756static int pl011_get_rs485_mode(struct uart_amba_port *uap)
2757{
2758 struct uart_port *port = &uap->port;
2759 struct serial_rs485 *rs485 = &port->rs485;
2760 int ret;
2761
2762 ret = uart_get_rs485_mode(port);
2763 if (ret)
2764 return ret;
2765
2766 /* clamp the delays to [0, 100ms] */
2767 rs485->delay_rts_before_send = min(rs485->delay_rts_before_send, 100U);
2768 rs485->delay_rts_after_send = min(rs485->delay_rts_after_send, 100U);
2769
2770 return 0;
2771}
2772
3873e2d7
AP		 2773static int pl011_setup_port(struct device *dev, struct uart_amba_port *uap,
2774 struct resource *mmiobase, int index)
2775{
2776 void __iomem *base;
8d479237 2777 int ret;
32614aad 2778
3873e2d7 2779 base = devm_ioremap_resource(dev, mmiobase);
97a60eac
KK		 2780 if (IS_ERR(base))
2781 return PTR_ERR(base);
1da177e4 2782
3873e2d7 2783 index = pl011_probe_dt_alias(index, dev);
1da177e4 2784
d8d8ffa4 2785 uap->old_cr = 0;
3873e2d7
AP		 2786 uap->port.dev = dev;
2787 uap->port.mapbase = mmiobase->start;
1da177e4 2788 uap->port.membase = base;
ffca2b11 2789 uap->port.fifosize = uap->fifosize;
5f99fca9 2790 uap->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_AMBA_PL011_CONSOLE);
1da177e4 2791 uap->port.flags = UPF_BOOT_AUTOCONF;
3873e2d7 2792 uap->port.line = index;
1da177e4 2793
8d479237
LS		 2794 ret = pl011_get_rs485_mode(uap);
2795 if (ret)
2796 return ret;
2797
3873e2d7 2798 amba_ports[index] = uap;
c3d8b76f 2799
3873e2d7
AP		 2800 return 0;
2801}
e8a7ba86 2802
3873e2d7
AP		 2803static int pl011_register_port(struct uart_amba_port *uap)
2804{
89efbe70 2805 int ret, i;
1da177e4 2806
3873e2d7 2807 /* Ensure interrupts from this UART are masked and cleared */
9f25bc51
RK		 2808 pl011_write(0, uap, REG_IMSC);
2809 pl011_write(0xffff, uap, REG_ICR);
ef2889f7
TB		 2810
2811 if (!amba_reg.state) {
2812 ret = uart_register_driver(&amba_reg);
2813 if (ret < 0) {
3873e2d7 2814 dev_err(uap->port.dev,
1c9be310 2815 "Failed to register AMBA-PL011 driver\n");
89efbe70
LW		 2816 for (i = 0; i < ARRAY_SIZE(amba_ports); i++)
2817 if (amba_ports[i] == uap)
2818 amba_ports[i] = NULL;
ef2889f7
TB		 2819 return ret;
2820 }
2821 }
2822
1da177e4 2823 ret = uart_add_one_port(&amba_reg, &uap->port);
49bb3c86
AP		 2824 if (ret)
2825 pl011_unregister_port(uap);
7f6d942a 2826
1da177e4
LT		 2827 return ret;
2828}
2829
3873e2d7
AP		 2830static int pl011_probe(struct amba_device *dev, const struct amba_id *id)
2831{
2832 struct uart_amba_port *uap;
2833 struct vendor_data *vendor = id->data;
2834 int portnr, ret;
2835
2836 portnr = pl011_find_free_port();
2837 if (portnr < 0)
2838 return portnr;
2839
2840 uap = devm_kzalloc(&dev->dev, sizeof(struct uart_amba_port),
2841 GFP_KERNEL);
2842 if (!uap)
2843 return -ENOMEM;
2844
2845 uap->clk = devm_clk_get(&dev->dev, NULL);
2846 if (IS_ERR(uap->clk))
2847 return PTR_ERR(uap->clk);
2848
439403bd 2849 uap->reg_offset = vendor->reg_offset;
3873e2d7 2850 uap->vendor = vendor;
3873e2d7 2851 uap->fifosize = vendor->get_fifosize(dev);
3b78fae7 2852 uap->port.iotype = vendor->access_32b ? UPIO_MEM32 : UPIO_MEM;
3873e2d7
AP		 2853 uap->port.irq = dev->irq[0];
2854 uap->port.ops = &amba_pl011_pops;
8d479237 2855 uap->port.rs485_config = pl011_rs485_config;
3873e2d7
AP		 2856 snprintf(uap->type, sizeof(uap->type), "PL011 rev%u", amba_rev(dev));
2857
2858 ret = pl011_setup_port(&dev->dev, uap, &dev->res, portnr);
2859 if (ret)
2860 return ret;
2861
2862 amba_set_drvdata(dev, uap);
2863
2864 return pl011_register_port(uap);
2865}
2866
3fd269e7 2867static void pl011_remove(struct amba_device *dev)
1da177e4
LT		 2868{
2869 struct uart_amba_port *uap = amba_get_drvdata(dev);
1da177e4 2870
1da177e4 2871 uart_remove_one_port(&amba_reg, &uap->port);
49bb3c86 2872 pl011_unregister_port(uap);
1da177e4
LT		 2873}
2874
d0ce850d
UH		 2875#ifdef CONFIG_PM_SLEEP
2876static int pl011_suspend(struct device *dev)
b736b89f 2877{
d0ce850d 2878 struct uart_amba_port *uap = dev_get_drvdata(dev);
b736b89f
LC		 2879
2880 if (!uap)
2881 return -EINVAL;
2882
2883 return uart_suspend_port(&amba_reg, &uap->port);
2884}
2885
d0ce850d 2886static int pl011_resume(struct device *dev)
b736b89f 2887{
d0ce850d 2888 struct uart_amba_port *uap = dev_get_drvdata(dev);
b736b89f
LC		 2889
2890 if (!uap)
2891 return -EINVAL;
2892
2893 return uart_resume_port(&amba_reg, &uap->port);
2894}
2895#endif
2896
d0ce850d
UH		 2897static SIMPLE_DEV_PM_OPS(pl011_dev_pm_ops, pl011_suspend, pl011_resume);
2898
0dd1e247
AP		 2899static int sbsa_uart_probe(struct platform_device *pdev)
2900{
2901 struct uart_amba_port *uap;
2902 struct resource *r;
2903 int portnr, ret;
2904 int baudrate;
2905
2906 /*
2907 * Check the mandatory baud rate parameter in the DT node early
2908 * so that we can easily exit with the error.
2909 */
2910 if (pdev->dev.of_node) {
2911 struct device_node *np = pdev->dev.of_node;
2912
2913 ret = of_property_read_u32(np, "current-speed", &baudrate);
2914 if (ret)
2915 return ret;
2916 } else {
2917 baudrate = 115200;
2918 }
2919
2920 portnr = pl011_find_free_port();
2921 if (portnr < 0)
2922 return portnr;
2923
2924 uap = devm_kzalloc(&pdev->dev, sizeof(struct uart_amba_port),
2925 GFP_KERNEL);
2926 if (!uap)
2927 return -ENOMEM;
2928
394a9e2c 2929 ret = platform_get_irq(pdev, 0);
1df21786 2930 if (ret < 0)
394a9e2c 2931 return ret;
394a9e2c
JS		 2932 uap->port.irq = ret;
2933
37ef38f3
TT		 2934#ifdef CONFIG_ACPI_SPCR_TABLE
2935 if (qdf2400_e44_present) {
2936 dev_info(&pdev->dev, "working around QDF2400 SoC erratum 44\n");
2937 uap->vendor = &vendor_qdt_qdf2400_e44;
2938 } else
2939#endif
2940 uap->vendor = &vendor_sbsa;
2941
2942 uap->reg_offset = uap->vendor->reg_offset;
0dd1e247 2943 uap->fifosize = 32;
37ef38f3 2944 uap->port.iotype = uap->vendor->access_32b ? UPIO_MEM32 : UPIO_MEM;
0dd1e247
AP		 2945 uap->port.ops = &sbsa_uart_pops;
2946 uap->fixed_baud = baudrate;
2947
2948 snprintf(uap->type, sizeof(uap->type), "SBSA");
2949
2950 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2951
2952 ret = pl011_setup_port(&pdev->dev, uap, r, portnr);
2953 if (ret)
2954 return ret;
2955
2956 platform_set_drvdata(pdev, uap);
2957
2958 return pl011_register_port(uap);
2959}
2960
2961static int sbsa_uart_remove(struct platform_device *pdev)
2962{
2963 struct uart_amba_port *uap = platform_get_drvdata(pdev);
2964
2965 uart_remove_one_port(&amba_reg, &uap->port);
2966 pl011_unregister_port(uap);
2967 return 0;
2968}
2969
2970static const struct of_device_id sbsa_uart_of_match[] = {
2971 { .compatible = "arm,sbsa-uart", },
2972 {},
2973};
2974MODULE_DEVICE_TABLE(of, sbsa_uart_of_match);
2975
7789c1f1 2976static const struct acpi_device_id __maybe_unused sbsa_uart_acpi_match[] = {
3db9ab0b
GG		 2977 { "ARMH0011", 0 },
2978 {},
2979};
2980MODULE_DEVICE_TABLE(acpi, sbsa_uart_acpi_match);
2981
0dd1e247
AP		 2982static struct platform_driver arm_sbsa_uart_platform_driver = {
2983 .probe = sbsa_uart_probe,
2984 .remove = sbsa_uart_remove,
2985 .driver = {
2986 .name = "sbsa-uart",
2301ec36 2987 .pm = &pl011_dev_pm_ops,
0dd1e247 2988 .of_match_table = of_match_ptr(sbsa_uart_of_match),
3db9ab0b 2989 .acpi_match_table = ACPI_PTR(sbsa_uart_acpi_match),
64609794 2990 .suppress_bind_attrs = IS_BUILTIN(CONFIG_SERIAL_AMBA_PL011),
0dd1e247
AP		 2991 },
2992};
2993
a704ddc2 2994static const struct amba_id pl011_ids[] = {
1da177e4
LT		 2995 {
2996 .id = 0x00041011,
2997 .mask = 0x000fffff,
5926a295
AR		 2998 .data = &vendor_arm,
2999 },
3000 {
3001 .id = 0x00380802,
3002 .mask = 0x00ffffff,
3003 .data = &vendor_st,
1da177e4 3004 },
2426fbc7
SG		 3005 {
3006 .id = AMBA_LINUX_ID(0x00, 0x1, 0xffe),
3007 .mask = 0x00ffffff,
3008 .data = &vendor_zte,
3009 },
1da177e4
LT		 3010 { 0, 0 },
3011};
3012
60f7a33b
DM		 3013MODULE_DEVICE_TABLE(amba, pl011_ids);
3014
1da177e4
LT		 3015static struct amba_driver pl011_driver = {
3016 .drv = {
3017 .name = "uart-pl011",
d0ce850d 3018 .pm = &pl011_dev_pm_ops,
64609794 3019 .suppress_bind_attrs = IS_BUILTIN(CONFIG_SERIAL_AMBA_PL011),
1da177e4
LT		 3020 },
3021 .id_table = pl011_ids,
3022 .probe = pl011_probe,
3023 .remove = pl011_remove,
3024};
3025
3026static int __init pl011_init(void)
3027{
1da177e4
LT		 3028 printk(KERN_INFO "Serial: AMBA PL011 UART driver\n");
3029
0dd1e247
AP		 3030 if (platform_driver_register(&arm_sbsa_uart_platform_driver))
3031 pr_warn("could not register SBSA UART platform driver\n");
062a68a5 3032 return amba_driver_register(&pl011_driver);
1da177e4
LT		 3033}
3034
3035static void __exit pl011_exit(void)
3036{
0dd1e247 3037 platform_driver_unregister(&arm_sbsa_uart_platform_driver);
1da177e4 3038 amba_driver_unregister(&pl011_driver);
1da177e4
LT		 3039}
3040
4dd9e742
AR		 3041/*
3042 * While this can be a module, if builtin it's most likely the console
3043 * So let's leave module_exit but move module_init to an earlier place
3044 */
3045arch_initcall(pl011_init);
1da177e4
LT		 3046module_exit(pl011_exit);
3047
3048MODULE_AUTHOR("ARM Ltd/Deep Blue Solutions Ltd");
3049MODULE_DESCRIPTION("ARM AMBA serial port driver");
3050MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)