projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
tty: serial: jsm: remove redundant pointer ts
[linux-2.6-block.git] / drivers / tty / serial / amba-pl011.c
CommitLineData
1da177e4 1/*
1da177e4
LT		 2 * Driver for AMBA serial ports
3 *
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5 *
6 * Copyright 1999 ARM Limited
7 * Copyright (C) 2000 Deep Blue Solutions Ltd.
68b65f73 8 * Copyright (C) 2010 ST-Ericsson SA
1da177e4
LT		 9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 *
1da177e4
LT		 24 * This is a generic driver for ARM AMBA-type serial ports. They
25 * have a lot of 16550-like features, but are not register compatible.
26 * Note that although they do have CTS, DCD and DSR inputs, they do
27 * not have an RI input, nor do they have DTR or RTS outputs. If
28 * required, these have to be supplied via some other means (eg, GPIO)
29 * and hooked into this driver.
30 */
1da177e4 31
cb06ff10 32
1da177e4
LT		 33#if defined(CONFIG_SERIAL_AMBA_PL011_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
34#define SUPPORT_SYSRQ
35#endif
36
37#include <linux/module.h>
38#include <linux/ioport.h>
39#include <linux/init.h>
40#include <linux/console.h>
41#include <linux/sysrq.h>
42#include <linux/device.h>
43#include <linux/tty.h>
44#include <linux/tty_flip.h>
45#include <linux/serial_core.h>
46#include <linux/serial.h>
a62c80e5
RK		 47#include <linux/amba/bus.h>
48#include <linux/amba/serial.h>
f8ce2547 49#include <linux/clk.h>
5a0e3ad6 50#include <linux/slab.h>
68b65f73
RK		 51#include <linux/dmaengine.h>
52#include <linux/dma-mapping.h>
53#include <linux/scatterlist.h>
c16d51a3 54#include <linux/delay.h>
258aea76 55#include <linux/types.h>
32614aad
ML		 56#include <linux/of.h>
57#include <linux/of_device.h>
258e0551 58#include <linux/pinctrl/consumer.h>
cb70706c 59#include <linux/sizes.h>
de609582 60#include <linux/io.h>
3db9ab0b 61#include <linux/acpi.h>
1da177e4 62
9f25bc51
RK		 63#include "amba-pl011.h"
64
1da177e4
LT		 65#define UART_NR 14
66
67#define SERIAL_AMBA_MAJOR 204
68#define SERIAL_AMBA_MINOR 64
69#define SERIAL_AMBA_NR UART_NR
70
71#define AMBA_ISR_PASS_LIMIT 256
72
b63d4f0f
RK		 73#define UART_DR_ERROR (UART011_DR_OE|UART011_DR_BE|UART011_DR_PE|UART011_DR_FE)
74#define UART_DUMMY_DR_RX (1 << 16)
1da177e4 75
debb7f64
RK		 76static u16 pl011_std_offsets[REG_ARRAY_SIZE] = {
77 [REG_DR] = UART01x_DR,
debb7f64 78 [REG_FR] = UART01x_FR,
e4df9a80
RK		 79 [REG_LCRH_RX] = UART011_LCRH,
80 [REG_LCRH_TX] = UART011_LCRH,
debb7f64
RK		 81 [REG_IBRD] = UART011_IBRD,
82 [REG_FBRD] = UART011_FBRD,
debb7f64
RK		 83 [REG_CR] = UART011_CR,
84 [REG_IFLS] = UART011_IFLS,
85 [REG_IMSC] = UART011_IMSC,
86 [REG_RIS] = UART011_RIS,
87 [REG_MIS] = UART011_MIS,
88 [REG_ICR] = UART011_ICR,
89 [REG_DMACR] = UART011_DMACR,
debb7f64
RK		 90};
91
5926a295
AR		 92/* There is by now at least one vendor with differing details, so handle it */
93struct vendor_data {
439403bd 94 const u16 *reg_offset;
5926a295 95 unsigned int ifls;
0e125a5f
SG		 96 unsigned int fr_busy;
97 unsigned int fr_dsr;
98 unsigned int fr_cts;
99 unsigned int fr_ri;
d8a4995b 100 unsigned int inv_fr;
84c3e03b 101 bool access_32b;
ac3e3fb4 102 bool oversampling;
38d62436 103 bool dma_threshold;
4fd0690b 104 bool cts_event_workaround;
71eec483 105 bool always_enabled;
cefc2d1d 106 bool fixed_options;
78506f22 107
ea33640a 108 unsigned int (*get_fifosize)(struct amba_device *dev);
5926a295
AR		 109};
110
ea33640a 111static unsigned int get_fifosize_arm(struct amba_device *dev)
78506f22 112{
ea33640a 113 return amba_rev(dev) < 3 ? 16 : 32;
78506f22
JK		 114}
115
5926a295 116static struct vendor_data vendor_arm = {
439403bd 117 .reg_offset = pl011_std_offsets,
5926a295 118 .ifls = UART011_IFLS_RX4_8|UART011_IFLS_TX4_8,
0e125a5f
SG		 119 .fr_busy = UART01x_FR_BUSY,
120 .fr_dsr = UART01x_FR_DSR,
121 .fr_cts = UART01x_FR_CTS,
122 .fr_ri = UART011_FR_RI,
ac3e3fb4 123 .oversampling = false,
38d62436 124 .dma_threshold = false,
4fd0690b 125 .cts_event_workaround = false,
71eec483 126 .always_enabled = false,
cefc2d1d 127 .fixed_options = false,
78506f22 128 .get_fifosize = get_fifosize_arm,
5926a295
AR		 129};
130
d054b3ac 131static const struct vendor_data vendor_sbsa = {
439403bd 132 .reg_offset = pl011_std_offsets,
0e125a5f
SG		 133 .fr_busy = UART01x_FR_BUSY,
134 .fr_dsr = UART01x_FR_DSR,
135 .fr_cts = UART01x_FR_CTS,
136 .fr_ri = UART011_FR_RI,
1aabf523 137 .access_32b = true,
0dd1e247
AP		 138 .oversampling = false,
139 .dma_threshold = false,
140 .cts_event_workaround = false,
141 .always_enabled = true,
142 .fixed_options = true,
143};
144
37ef38f3 145#ifdef CONFIG_ACPI_SPCR_TABLE
d054b3ac 146static const struct vendor_data vendor_qdt_qdf2400_e44 = {
d8a4995b
CC		 147 .reg_offset = pl011_std_offsets,
148 .fr_busy = UART011_FR_TXFE,
149 .fr_dsr = UART01x_FR_DSR,
150 .fr_cts = UART01x_FR_CTS,
151 .fr_ri = UART011_FR_RI,
152 .inv_fr = UART011_FR_TXFE,
153 .access_32b = true,
154 .oversampling = false,
155 .dma_threshold = false,
156 .cts_event_workaround = false,
157 .always_enabled = true,
158 .fixed_options = true,
159};
37ef38f3 160#endif
d8a4995b 161
bf69ff8a
RK		 162static u16 pl011_st_offsets[REG_ARRAY_SIZE] = {
163 [REG_DR] = UART01x_DR,
164 [REG_ST_DMAWM] = ST_UART011_DMAWM,
165 [REG_ST_TIMEOUT] = ST_UART011_TIMEOUT,
166 [REG_FR] = UART01x_FR,
e4df9a80
RK		 167 [REG_LCRH_RX] = ST_UART011_LCRH_RX,
168 [REG_LCRH_TX] = ST_UART011_LCRH_TX,
bf69ff8a
RK		 169 [REG_IBRD] = UART011_IBRD,
170 [REG_FBRD] = UART011_FBRD,
bf69ff8a
RK		 171 [REG_CR] = UART011_CR,
172 [REG_IFLS] = UART011_IFLS,
173 [REG_IMSC] = UART011_IMSC,
174 [REG_RIS] = UART011_RIS,
175 [REG_MIS] = UART011_MIS,
176 [REG_ICR] = UART011_ICR,
177 [REG_DMACR] = UART011_DMACR,
178 [REG_ST_XFCR] = ST_UART011_XFCR,
179 [REG_ST_XON1] = ST_UART011_XON1,
180 [REG_ST_XON2] = ST_UART011_XON2,
181 [REG_ST_XOFF1] = ST_UART011_XOFF1,
182 [REG_ST_XOFF2] = ST_UART011_XOFF2,
183 [REG_ST_ITCR] = ST_UART011_ITCR,
184 [REG_ST_ITIP] = ST_UART011_ITIP,
185 [REG_ST_ABCR] = ST_UART011_ABCR,
186 [REG_ST_ABIMSC] = ST_UART011_ABIMSC,
187};
188
ea33640a 189static unsigned int get_fifosize_st(struct amba_device *dev)
78506f22
JK		 190{
191 return 64;
192}
193
5926a295 194static struct vendor_data vendor_st = {
bf69ff8a 195 .reg_offset = pl011_st_offsets,
5926a295 196 .ifls = UART011_IFLS_RX_HALF|UART011_IFLS_TX_HALF,
0e125a5f
SG		 197 .fr_busy = UART01x_FR_BUSY,
198 .fr_dsr = UART01x_FR_DSR,
199 .fr_cts = UART01x_FR_CTS,
200 .fr_ri = UART011_FR_RI,
ac3e3fb4 201 .oversampling = true,
38d62436 202 .dma_threshold = true,
4fd0690b 203 .cts_event_workaround = true,
71eec483 204 .always_enabled = false,
cefc2d1d 205 .fixed_options = false,
78506f22 206 .get_fifosize = get_fifosize_st,
1da177e4
LT		 207};
208
7ec75871
RK		 209static const u16 pl011_zte_offsets[REG_ARRAY_SIZE] = {
210 [REG_DR] = ZX_UART011_DR,
211 [REG_FR] = ZX_UART011_FR,
212 [REG_LCRH_RX] = ZX_UART011_LCRH,
213 [REG_LCRH_TX] = ZX_UART011_LCRH,
214 [REG_IBRD] = ZX_UART011_IBRD,
215 [REG_FBRD] = ZX_UART011_FBRD,
216 [REG_CR] = ZX_UART011_CR,
217 [REG_IFLS] = ZX_UART011_IFLS,
218 [REG_IMSC] = ZX_UART011_IMSC,
219 [REG_RIS] = ZX_UART011_RIS,
220 [REG_MIS] = ZX_UART011_MIS,
221 [REG_ICR] = ZX_UART011_ICR,
222 [REG_DMACR] = ZX_UART011_DMACR,
223};
224
9c267ddb
SG		 225static unsigned int get_fifosize_zte(struct amba_device *dev)
226{
227 return 16;
228}
229
2426fbc7 230static struct vendor_data vendor_zte = {
7ec75871
RK		 231 .reg_offset = pl011_zte_offsets,
232 .access_32b = true,
233 .ifls = UART011_IFLS_RX4_8|UART011_IFLS_TX4_8,
0e125a5f
SG		 234 .fr_busy = ZX_UART01x_FR_BUSY,
235 .fr_dsr = ZX_UART01x_FR_DSR,
236 .fr_cts = ZX_UART01x_FR_CTS,
237 .fr_ri = ZX_UART011_FR_RI,
9c267ddb 238 .get_fifosize = get_fifosize_zte,
7ec75871
RK		 239};
240
68b65f73 241/* Deals with DMA transactions */
ead76f32
LW		 242
243struct pl011_sgbuf {
244 struct scatterlist sg;
245 char *buf;
246};
247
248struct pl011_dmarx_data {
249 struct dma_chan *chan;
250 struct completion complete;
251 bool use_buf_b;
252 struct pl011_sgbuf sgbuf_a;
253 struct pl011_sgbuf sgbuf_b;
254 dma_cookie_t cookie;
255 bool running;
cb06ff10
CM		 256 struct timer_list timer;
257 unsigned int last_residue;
258 unsigned long last_jiffies;
259 bool auto_poll_rate;
260 unsigned int poll_rate;
261 unsigned int poll_timeout;
ead76f32
LW		 262};
263
68b65f73
RK		 264struct pl011_dmatx_data {
265 struct dma_chan *chan;
266 struct scatterlist sg;
267 char *buf;
268 bool queued;
269};
270
c19f12b5
RK		 271/*
272 * We wrap our port structure around the generic uart_port.
273 */
274struct uart_amba_port {
275 struct uart_port port;
debb7f64 276 const u16 *reg_offset;
c19f12b5
RK		 277 struct clk *clk;
278 const struct vendor_data *vendor;
68b65f73 279 unsigned int dmacr; /* dma control reg */
c19f12b5
RK		 280 unsigned int im; /* interrupt mask */
281 unsigned int old_status;
ffca2b11 282 unsigned int fifosize; /* vendor-specific */
d8d8ffa4 283 unsigned int old_cr; /* state during shutdown */
cefc2d1d 284 unsigned int fixed_baud; /* vendor-set fixed baud rate */
c19f12b5 285 char type[12];
68b65f73
RK		 286#ifdef CONFIG_DMA_ENGINE
287 /* DMA stuff */
ead76f32
LW		 288 bool using_tx_dma;
289 bool using_rx_dma;
290 struct pl011_dmarx_data dmarx;
68b65f73 291 struct pl011_dmatx_data dmatx;
1c9be310 292 bool dma_probed;
68b65f73
RK		 293#endif
294};
295
9f25bc51
RK		 296static unsigned int pl011_reg_to_offset(const struct uart_amba_port *uap,
297 unsigned int reg)
298{
debb7f64 299 return uap->reg_offset[reg];
9f25bc51
RK		 300}
301
b2a4e24c
RK		 302static unsigned int pl011_read(const struct uart_amba_port *uap,
303 unsigned int reg)
75836339 304{
84c3e03b
RK		 305 void __iomem *addr = uap->port.membase + pl011_reg_to_offset(uap, reg);
306
3b78fae7
TT		 307 return (uap->port.iotype == UPIO_MEM32) ?
308 readl_relaxed(addr) : readw_relaxed(addr);
75836339
RK		 309}
310
b2a4e24c
RK		 311static void pl011_write(unsigned int val, const struct uart_amba_port *uap,
312 unsigned int reg)
75836339 313{
84c3e03b
RK		 314 void __iomem *addr = uap->port.membase + pl011_reg_to_offset(uap, reg);
315
3b78fae7 316 if (uap->port.iotype == UPIO_MEM32)
f5ce6edd 317 writel_relaxed(val, addr);
84c3e03b 318 else
f5ce6edd 319 writew_relaxed(val, addr);
75836339
RK		 320}
321
29772c4e
LW		 322/*
323 * Reads up to 256 characters from the FIFO or until it's empty and
324 * inserts them into the TTY layer. Returns the number of characters
325 * read from the FIFO.
326 */
327static int pl011_fifo_to_tty(struct uart_amba_port *uap)
328{
71a5cd8a
TT		 329 u16 status;
330 unsigned int ch, flag, max_count = 256;
29772c4e
LW		 331 int fifotaken = 0;
332
333 while (max_count--) {
9f25bc51 334 status = pl011_read(uap, REG_FR);
29772c4e
LW		 335 if (status & UART01x_FR_RXFE)
336 break;
337
338 /* Take chars from the FIFO and update status */
9f25bc51 339 ch = pl011_read(uap, REG_DR) | UART_DUMMY_DR_RX;
29772c4e
LW		 340 flag = TTY_NORMAL;
341 uap->port.icount.rx++;
342 fifotaken++;
343
344 if (unlikely(ch & UART_DR_ERROR)) {
345 if (ch & UART011_DR_BE) {
346 ch &= ~(UART011_DR_FE | UART011_DR_PE);
347 uap->port.icount.brk++;
348 if (uart_handle_break(&uap->port))
349 continue;
350 } else if (ch & UART011_DR_PE)
351 uap->port.icount.parity++;
352 else if (ch & UART011_DR_FE)
353 uap->port.icount.frame++;
354 if (ch & UART011_DR_OE)
355 uap->port.icount.overrun++;
356
357 ch &= uap->port.read_status_mask;
358
359 if (ch & UART011_DR_BE)
360 flag = TTY_BREAK;
361 else if (ch & UART011_DR_PE)
362 flag = TTY_PARITY;
363 else if (ch & UART011_DR_FE)
364 flag = TTY_FRAME;
365 }
366
367 if (uart_handle_sysrq_char(&uap->port, ch & 255))
368 continue;
369
370 uart_insert_char(&uap->port, ch, UART011_DR_OE, ch, flag);
371 }
372
373 return fifotaken;
374}
375
376
68b65f73
RK		 377/*
378 * All the DMA operation mode stuff goes inside this ifdef.
379 * This assumes that you have a generic DMA device interface,
380 * no custom DMA interfaces are supported.
381 */
382#ifdef CONFIG_DMA_ENGINE
383
384#define PL011_DMA_BUFFER_SIZE PAGE_SIZE
385
ead76f32
LW		 386static int pl011_sgbuf_init(struct dma_chan *chan, struct pl011_sgbuf *sg,
387 enum dma_data_direction dir)
388{
cb06ff10
CM		 389 dma_addr_t dma_addr;
390
391 sg->buf = dma_alloc_coherent(chan->device->dev,
392 PL011_DMA_BUFFER_SIZE, &dma_addr, GFP_KERNEL);
ead76f32
LW		 393 if (!sg->buf)
394 return -ENOMEM;
395
cb06ff10
CM		 396 sg_init_table(&sg->sg, 1);
397 sg_set_page(&sg->sg, phys_to_page(dma_addr),
398 PL011_DMA_BUFFER_SIZE, offset_in_page(dma_addr));
399 sg_dma_address(&sg->sg) = dma_addr;
c64be923 400 sg_dma_len(&sg->sg) = PL011_DMA_BUFFER_SIZE;
ead76f32 401
ead76f32
LW		 402 return 0;
403}
404
405static void pl011_sgbuf_free(struct dma_chan *chan, struct pl011_sgbuf *sg,
406 enum dma_data_direction dir)
407{
408 if (sg->buf) {
cb06ff10
CM		 409 dma_free_coherent(chan->device->dev,
410 PL011_DMA_BUFFER_SIZE, sg->buf,
411 sg_dma_address(&sg->sg));
ead76f32
LW		 412 }
413}
414
1c9be310 415static void pl011_dma_probe(struct uart_amba_port *uap)
68b65f73
RK		 416{
417 /* DMA is the sole user of the platform data right now */
574de559 418 struct amba_pl011_data *plat = dev_get_platdata(uap->port.dev);
1c9be310 419 struct device *dev = uap->port.dev;
68b65f73 420 struct dma_slave_config tx_conf = {
9f25bc51
RK		 421 .dst_addr = uap->port.mapbase +
422 pl011_reg_to_offset(uap, REG_DR),
68b65f73 423 .dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
a485df4b 424 .direction = DMA_MEM_TO_DEV,
68b65f73 425 .dst_maxburst = uap->fifosize >> 1,
258aea76 426 .device_fc = false,
68b65f73
RK		 427 };
428 struct dma_chan *chan;
429 dma_cap_mask_t mask;
430
1c9be310
JRO		 431 uap->dma_probed = true;
432 chan = dma_request_slave_channel_reason(dev, "tx");
433 if (IS_ERR(chan)) {
434 if (PTR_ERR(chan) == -EPROBE_DEFER) {
1c9be310
JRO		 435 uap->dma_probed = false;
436 return;
437 }
68b65f73 438
787b0c1f
AB		 439 /* We need platform data */
440 if (!plat || !plat->dma_filter) {
441 dev_info(uap->port.dev, "no DMA platform data\n");
442 return;
443 }
444
445 /* Try to acquire a generic DMA engine slave TX channel */
446 dma_cap_zero(mask);
447 dma_cap_set(DMA_SLAVE, mask);
448
449 chan = dma_request_channel(mask, plat->dma_filter,
450 plat->dma_tx_param);
451 if (!chan) {
452 dev_err(uap->port.dev, "no TX DMA channel!\n");
453 return;
454 }
68b65f73
RK		 455 }
456
457 dmaengine_slave_config(chan, &tx_conf);
458 uap->dmatx.chan = chan;
459
460 dev_info(uap->port.dev, "DMA channel TX %s\n",
461 dma_chan_name(uap->dmatx.chan));
ead76f32
LW		 462
463 /* Optionally make use of an RX channel as well */
787b0c1f 464 chan = dma_request_slave_channel(dev, "rx");
0d3c673e 465
d9e105ca 466 if (!chan && plat && plat->dma_rx_param) {
787b0c1f
AB		 467 chan = dma_request_channel(mask, plat->dma_filter, plat->dma_rx_param);
468
469 if (!chan) {
470 dev_err(uap->port.dev, "no RX DMA channel!\n");
471 return;
472 }
473 }
474
475 if (chan) {
ead76f32 476 struct dma_slave_config rx_conf = {
9f25bc51
RK		 477 .src_addr = uap->port.mapbase +
478 pl011_reg_to_offset(uap, REG_DR),
ead76f32 479 .src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
a485df4b 480 .direction = DMA_DEV_TO_MEM,
b2aeb775 481 .src_maxburst = uap->fifosize >> 2,
258aea76 482 .device_fc = false,
ead76f32 483 };
2d3b7d6e
AJ		 484 struct dma_slave_caps caps;
485
486 /*
487 * Some DMA controllers provide information on their capabilities.
488 * If the controller does, check for suitable residue processing
489 * otherwise assime all is well.
490 */
491 if (0 == dma_get_slave_caps(chan, &caps)) {
492 if (caps.residue_granularity ==
493 DMA_RESIDUE_GRANULARITY_DESCRIPTOR) {
494 dma_release_channel(chan);
495 dev_info(uap->port.dev,
496 "RX DMA disabled - no residue processing\n");
497 return;
498 }
499 }
ead76f32
LW		 500 dmaengine_slave_config(chan, &rx_conf);
501 uap->dmarx.chan = chan;
502
98267d33 503 uap->dmarx.auto_poll_rate = false;
8f898bfd 504 if (plat && plat->dma_rx_poll_enable) {
cb06ff10
CM		 505 /* Set poll rate if specified. */
506 if (plat->dma_rx_poll_rate) {
507 uap->dmarx.auto_poll_rate = false;
508 uap->dmarx.poll_rate = plat->dma_rx_poll_rate;
509 } else {
510 /*
511 * 100 ms defaults to poll rate if not
512 * specified. This will be adjusted with
513 * the baud rate at set_termios.
514 */
515 uap->dmarx.auto_poll_rate = true;
516 uap->dmarx.poll_rate = 100;
517 }
518 /* 3 secs defaults poll_timeout if not specified. */
519 if (plat->dma_rx_poll_timeout)
520 uap->dmarx.poll_timeout =
521 plat->dma_rx_poll_timeout;
522 else
523 uap->dmarx.poll_timeout = 3000;
98267d33
AJ		 524 } else if (!plat && dev->of_node) {
525 uap->dmarx.auto_poll_rate = of_property_read_bool(
526 dev->of_node, "auto-poll");
527 if (uap->dmarx.auto_poll_rate) {
528 u32 x;
529
530 if (0 == of_property_read_u32(dev->of_node,
531 "poll-rate-ms", &x))
532 uap->dmarx.poll_rate = x;
533 else
534 uap->dmarx.poll_rate = 100;
535 if (0 == of_property_read_u32(dev->of_node,
536 "poll-timeout-ms", &x))
537 uap->dmarx.poll_timeout = x;
538 else
539 uap->dmarx.poll_timeout = 3000;
540 }
541 }
ead76f32
LW		 542 dev_info(uap->port.dev, "DMA channel RX %s\n",
543 dma_chan_name(uap->dmarx.chan));
544 }
68b65f73
RK		 545}
546
68b65f73
RK		 547static void pl011_dma_remove(struct uart_amba_port *uap)
548{
68b65f73
RK		 549 if (uap->dmatx.chan)
550 dma_release_channel(uap->dmatx.chan);
ead76f32
LW		 551 if (uap->dmarx.chan)
552 dma_release_channel(uap->dmarx.chan);
68b65f73
RK		 553}
554
734745ca 555/* Forward declare these for the refill routine */
68b65f73 556static int pl011_dma_tx_refill(struct uart_amba_port *uap);
734745ca 557static void pl011_start_tx_pio(struct uart_amba_port *uap);
68b65f73
RK		 558
559/*
560 * The current DMA TX buffer has been sent.
561 * Try to queue up another DMA buffer.
562 */
563static void pl011_dma_tx_callback(void *data)
564{
565 struct uart_amba_port *uap = data;
566 struct pl011_dmatx_data *dmatx = &uap->dmatx;
567 unsigned long flags;
568 u16 dmacr;
569
570 spin_lock_irqsave(&uap->port.lock, flags);
571 if (uap->dmatx.queued)
572 dma_unmap_sg(dmatx->chan->device->dev, &dmatx->sg, 1,
573 DMA_TO_DEVICE);
574
575 dmacr = uap->dmacr;
576 uap->dmacr = dmacr & ~UART011_TXDMAE;
9f25bc51 577 pl011_write(uap->dmacr, uap, REG_DMACR);
68b65f73
RK		 578
579 /*
580 * If TX DMA was disabled, it means that we've stopped the DMA for
581 * some reason (eg, XOFF received, or we want to send an X-char.)
582 *
583 * Note: we need to be careful here of a potential race between DMA
584 * and the rest of the driver - if the driver disables TX DMA while
585 * a TX buffer completing, we must update the tx queued status to
586 * get further refills (hence we check dmacr).
587 */
588 if (!(dmacr & UART011_TXDMAE) || uart_tx_stopped(&uap->port) ||
589 uart_circ_empty(&uap->port.state->xmit)) {
590 uap->dmatx.queued = false;
591 spin_unlock_irqrestore(&uap->port.lock, flags);
592 return;
593 }
594
734745ca 595 if (pl011_dma_tx_refill(uap) <= 0)
68b65f73
RK		 596 /*
597 * We didn't queue a DMA buffer for some reason, but we
598 * have data pending to be sent. Re-enable the TX IRQ.
599 */
734745ca
DM		 600 pl011_start_tx_pio(uap);
601
68b65f73
RK		 602 spin_unlock_irqrestore(&uap->port.lock, flags);
603}
604
605/*
606 * Try to refill the TX DMA buffer.
607 * Locking: called with port lock held and IRQs disabled.
608 * Returns:
609 * 1 if we queued up a TX DMA buffer.
610 * 0 if we didn't want to handle this by DMA
611 * <0 on error
612 */
613static int pl011_dma_tx_refill(struct uart_amba_port *uap)
614{
615 struct pl011_dmatx_data *dmatx = &uap->dmatx;
616 struct dma_chan *chan = dmatx->chan;
617 struct dma_device *dma_dev = chan->device;
618 struct dma_async_tx_descriptor *desc;
619 struct circ_buf *xmit = &uap->port.state->xmit;
620 unsigned int count;
621
622 /*
623 * Try to avoid the overhead involved in using DMA if the
624 * transaction fits in the first half of the FIFO, by using
625 * the standard interrupt handling. This ensures that we
626 * issue a uart_write_wakeup() at the appropriate time.
627 */
628 count = uart_circ_chars_pending(xmit);
629 if (count < (uap->fifosize >> 1)) {
630 uap->dmatx.queued = false;
631 return 0;
632 }
633
634 /*
635 * Bodge: don't send the last character by DMA, as this
636 * will prevent XON from notifying us to restart DMA.
637 */
638 count -= 1;
639
640 /* Else proceed to copy the TX chars to the DMA buffer and fire DMA */
641 if (count > PL011_DMA_BUFFER_SIZE)
642 count = PL011_DMA_BUFFER_SIZE;
643
644 if (xmit->tail < xmit->head)
645 memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], count);
646 else {
647 size_t first = UART_XMIT_SIZE - xmit->tail;
e2a545a6
AJ		 648 size_t second;
649
650 if (first > count)
651 first = count;
652 second = count - first;
68b65f73
RK		 653
654 memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], first);
655 if (second)
656 memcpy(&dmatx->buf[first], &xmit->buf[0], second);
657 }
658
659 dmatx->sg.length = count;
660
661 if (dma_map_sg(dma_dev->dev, &dmatx->sg, 1, DMA_TO_DEVICE) != 1) {
662 uap->dmatx.queued = false;
663 dev_dbg(uap->port.dev, "unable to map TX DMA\n");
664 return -EBUSY;
665 }
666
16052827 667 desc = dmaengine_prep_slave_sg(chan, &dmatx->sg, 1, DMA_MEM_TO_DEV,
68b65f73
RK		 668 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
669 if (!desc) {
670 dma_unmap_sg(dma_dev->dev, &dmatx->sg, 1, DMA_TO_DEVICE);
671 uap->dmatx.queued = false;
672 /*
673 * If DMA cannot be used right now, we complete this
674 * transaction via IRQ and let the TTY layer retry.
675 */
676 dev_dbg(uap->port.dev, "TX DMA busy\n");
677 return -EBUSY;
678 }
679
680 /* Some data to go along to the callback */
681 desc->callback = pl011_dma_tx_callback;
682 desc->callback_param = uap;
683
684 /* All errors should happen at prepare time */
685 dmaengine_submit(desc);
686
687 /* Fire the DMA transaction */
688 dma_dev->device_issue_pending(chan);
689
690 uap->dmacr |= UART011_TXDMAE;
9f25bc51 691 pl011_write(uap->dmacr, uap, REG_DMACR);
68b65f73
RK		 692 uap->dmatx.queued = true;
693
694 /*
695 * Now we know that DMA will fire, so advance the ring buffer
696 * with the stuff we just dispatched.
697 */
698 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
699 uap->port.icount.tx += count;
700
701 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
702 uart_write_wakeup(&uap->port);
703
704 return 1;
705}
706
707/*
708 * We received a transmit interrupt without a pending X-char but with
709 * pending characters.
710 * Locking: called with port lock held and IRQs disabled.
711 * Returns:
712 * false if we want to use PIO to transmit
713 * true if we queued a DMA buffer
714 */
715static bool pl011_dma_tx_irq(struct uart_amba_port *uap)
716{
ead76f32 717 if (!uap->using_tx_dma)
68b65f73
RK		 718 return false;
719
720 /*
721 * If we already have a TX buffer queued, but received a
722 * TX interrupt, it will be because we've just sent an X-char.
723 * Ensure the TX DMA is enabled and the TX IRQ is disabled.
724 */
725 if (uap->dmatx.queued) {
726 uap->dmacr |= UART011_TXDMAE;
9f25bc51 727 pl011_write(uap->dmacr, uap, REG_DMACR);
68b65f73 728 uap->im &= ~UART011_TXIM;
9f25bc51 729 pl011_write(uap->im, uap, REG_IMSC);
68b65f73
RK		 730 return true;
731 }
732
733 /*
734 * We don't have a TX buffer queued, so try to queue one.
25985edc 735 * If we successfully queued a buffer, mask the TX IRQ.
68b65f73
RK		 736 */
737 if (pl011_dma_tx_refill(uap) > 0) {
738 uap->im &= ~UART011_TXIM;
9f25bc51 739 pl011_write(uap->im, uap, REG_IMSC);
68b65f73
RK		 740 return true;
741 }
742 return false;
743}
744
745/*
746 * Stop the DMA transmit (eg, due to received XOFF).
747 * Locking: called with port lock held and IRQs disabled.
748 */
749static inline void pl011_dma_tx_stop(struct uart_amba_port *uap)
750{
751 if (uap->dmatx.queued) {
752 uap->dmacr &= ~UART011_TXDMAE;
9f25bc51 753 pl011_write(uap->dmacr, uap, REG_DMACR);
68b65f73
RK		 754 }
755}
756
757/*
758 * Try to start a DMA transmit, or in the case of an XON/OFF
759 * character queued for send, try to get that character out ASAP.
760 * Locking: called with port lock held and IRQs disabled.
761 * Returns:
762 * false if we want the TX IRQ to be enabled
763 * true if we have a buffer queued
764 */
765static inline bool pl011_dma_tx_start(struct uart_amba_port *uap)
766{
767 u16 dmacr;
768
ead76f32 769 if (!uap->using_tx_dma)
68b65f73
RK		 770 return false;
771
772 if (!uap->port.x_char) {
773 /* no X-char, try to push chars out in DMA mode */
774 bool ret = true;
775
776 if (!uap->dmatx.queued) {
777 if (pl011_dma_tx_refill(uap) > 0) {
778 uap->im &= ~UART011_TXIM;
9f25bc51 779 pl011_write(uap->im, uap, REG_IMSC);
734745ca 780 } else
68b65f73 781 ret = false;
68b65f73
RK		 782 } else if (!(uap->dmacr & UART011_TXDMAE)) {
783 uap->dmacr |= UART011_TXDMAE;
9f25bc51 784 pl011_write(uap->dmacr, uap, REG_DMACR);
68b65f73
RK		 785 }
786 return ret;
787 }
788
789 /*
790 * We have an X-char to send. Disable DMA to prevent it loading
791 * the TX fifo, and then see if we can stuff it into the FIFO.
792 */
793 dmacr = uap->dmacr;
794 uap->dmacr &= ~UART011_TXDMAE;
9f25bc51 795 pl011_write(uap->dmacr, uap, REG_DMACR);
68b65f73 796
9f25bc51 797 if (pl011_read(uap, REG_FR) & UART01x_FR_TXFF) {
68b65f73
RK		 798 /*
799 * No space in the FIFO, so enable the transmit interrupt
800 * so we know when there is space. Note that once we've
801 * loaded the character, we should just re-enable DMA.
802 */
803 return false;
804 }
805
9f25bc51 806 pl011_write(uap->port.x_char, uap, REG_DR);
68b65f73
RK		 807 uap->port.icount.tx++;
808 uap->port.x_char = 0;
809
810 /* Success - restore the DMA state */
811 uap->dmacr = dmacr;
9f25bc51 812 pl011_write(dmacr, uap, REG_DMACR);
68b65f73
RK		 813
814 return true;
815}
816
817/*
818 * Flush the transmit buffer.
819 * Locking: called with port lock held and IRQs disabled.
820 */
821static void pl011_dma_flush_buffer(struct uart_port *port)
b83286bf
FE		 822__releases(&uap->port.lock)
823__acquires(&uap->port.lock)
68b65f73 824{
a5820c24
DT		 825 struct uart_amba_port *uap =
826 container_of(port, struct uart_amba_port, port);
68b65f73 827
ead76f32 828 if (!uap->using_tx_dma)
68b65f73
RK		 829 return;
830
831 /* Avoid deadlock with the DMA engine callback */
832 spin_unlock(&uap->port.lock);
833 dmaengine_terminate_all(uap->dmatx.chan);
834 spin_lock(&uap->port.lock);
835 if (uap->dmatx.queued) {
836 dma_unmap_sg(uap->dmatx.chan->device->dev, &uap->dmatx.sg, 1,
837 DMA_TO_DEVICE);
838 uap->dmatx.queued = false;
839 uap->dmacr &= ~UART011_TXDMAE;
9f25bc51 840 pl011_write(uap->dmacr, uap, REG_DMACR);
68b65f73
RK		 841 }
842}
843
ead76f32
LW		 844static void pl011_dma_rx_callback(void *data);
845
846static int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap)
847{
848 struct dma_chan *rxchan = uap->dmarx.chan;
ead76f32
LW		 849 struct pl011_dmarx_data *dmarx = &uap->dmarx;
850 struct dma_async_tx_descriptor *desc;
851 struct pl011_sgbuf *sgbuf;
852
853 if (!rxchan)
854 return -EIO;
855
856 /* Start the RX DMA job */
857 sgbuf = uap->dmarx.use_buf_b ?
858 &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a;
16052827 859 desc = dmaengine_prep_slave_sg(rxchan, &sgbuf->sg, 1,
a485df4b 860 DMA_DEV_TO_MEM,
ead76f32
LW		 861 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
862 /*
863 * If the DMA engine is busy and cannot prepare a
864 * channel, no big deal, the driver will fall back
865 * to interrupt mode as a result of this error code.
866 */
867 if (!desc) {
868 uap->dmarx.running = false;
869 dmaengine_terminate_all(rxchan);
870 return -EBUSY;
871 }
872
873 /* Some data to go along to the callback */
874 desc->callback = pl011_dma_rx_callback;
875 desc->callback_param = uap;
876 dmarx->cookie = dmaengine_submit(desc);
877 dma_async_issue_pending(rxchan);
878
879 uap->dmacr |= UART011_RXDMAE;
9f25bc51 880 pl011_write(uap->dmacr, uap, REG_DMACR);
ead76f32
LW		 881 uap->dmarx.running = true;
882
883 uap->im &= ~UART011_RXIM;
9f25bc51 884 pl011_write(uap->im, uap, REG_IMSC);
ead76f32
LW		 885
886 return 0;
887}
888
889/*
890 * This is called when either the DMA job is complete, or
891 * the FIFO timeout interrupt occurred. This must be called
892 * with the port spinlock uap->port.lock held.
893 */
894static void pl011_dma_rx_chars(struct uart_amba_port *uap,
895 u32 pending, bool use_buf_b,
896 bool readfifo)
897{
05c7cd39 898 struct tty_port *port = &uap->port.state->port;
ead76f32
LW		 899 struct pl011_sgbuf *sgbuf = use_buf_b ?
900 &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a;
ead76f32
LW		 901 int dma_count = 0;
902 u32 fifotaken = 0; /* only used for vdbg() */
903
cb06ff10
CM		 904 struct pl011_dmarx_data *dmarx = &uap->dmarx;
905 int dmataken = 0;
906
907 if (uap->dmarx.poll_rate) {
908 /* The data can be taken by polling */
909 dmataken = sgbuf->sg.length - dmarx->last_residue;
910 /* Recalculate the pending size */
911 if (pending >= dmataken)
912 pending -= dmataken;
913 }
914
915 /* Pick the remain data from the DMA */
ead76f32 916 if (pending) {
ead76f32
LW		 917
918 /*
919 * First take all chars in the DMA pipe, then look in the FIFO.
920 * Note that tty_insert_flip_buf() tries to take as many chars
921 * as it can.
922 */
cb06ff10
CM		 923 dma_count = tty_insert_flip_string(port, sgbuf->buf + dmataken,
924 pending);
ead76f32
LW		 925
926 uap->port.icount.rx += dma_count;
927 if (dma_count < pending)
928 dev_warn(uap->port.dev,
929 "couldn't insert all characters (TTY is full?)\n");
930 }
931
cb06ff10
CM		 932 /* Reset the last_residue for Rx DMA poll */
933 if (uap->dmarx.poll_rate)
934 dmarx->last_residue = sgbuf->sg.length;
935
ead76f32
LW		 936 /*
937 * Only continue with trying to read the FIFO if all DMA chars have
938 * been taken first.
939 */
940 if (dma_count == pending && readfifo) {
941 /* Clear any error flags */
75836339 942 pl011_write(UART011_OEIS | UART011_BEIS | UART011_PEIS |
9f25bc51 943 UART011_FEIS, uap, REG_ICR);
ead76f32
LW		 944
945 /*
946 * If we read all the DMA'd characters, and we had an
29772c4e
LW		 947 * incomplete buffer, that could be due to an rx error, or
948 * maybe we just timed out. Read any pending chars and check
949 * the error status.
950 *
951 * Error conditions will only occur in the FIFO, these will
952 * trigger an immediate interrupt and stop the DMA job, so we
953 * will always find the error in the FIFO, never in the DMA
954 * buffer.
ead76f32 955 */
29772c4e 956 fifotaken = pl011_fifo_to_tty(uap);
ead76f32
LW		 957 }
958
959 spin_unlock(&uap->port.lock);
960 dev_vdbg(uap->port.dev,
961 "Took %d chars from DMA buffer and %d chars from the FIFO\n",
962 dma_count, fifotaken);
2e124b4a 963 tty_flip_buffer_push(port);
ead76f32
LW		 964 spin_lock(&uap->port.lock);
965}
966
967static void pl011_dma_rx_irq(struct uart_amba_port *uap)
968{
969 struct pl011_dmarx_data *dmarx = &uap->dmarx;
970 struct dma_chan *rxchan = dmarx->chan;
971 struct pl011_sgbuf *sgbuf = dmarx->use_buf_b ?
972 &dmarx->sgbuf_b : &dmarx->sgbuf_a;
973 size_t pending;
974 struct dma_tx_state state;
975 enum dma_status dmastat;
976
977 /*
978 * Pause the transfer so we can trust the current counter,
979 * do this before we pause the PL011 block, else we may
980 * overflow the FIFO.
981 */
982 if (dmaengine_pause(rxchan))
983 dev_err(uap->port.dev, "unable to pause DMA transfer\n");
984 dmastat = rxchan->device->device_tx_status(rxchan,
985 dmarx->cookie, &state);
986 if (dmastat != DMA_PAUSED)
987 dev_err(uap->port.dev, "unable to pause DMA transfer\n");
988
989 /* Disable RX DMA - incoming data will wait in the FIFO */
990 uap->dmacr &= ~UART011_RXDMAE;
9f25bc51 991 pl011_write(uap->dmacr, uap, REG_DMACR);
ead76f32
LW		 992 uap->dmarx.running = false;
993
994 pending = sgbuf->sg.length - state.residue;
995 BUG_ON(pending > PL011_DMA_BUFFER_SIZE);
996 /* Then we terminate the transfer - we now know our residue */
997 dmaengine_terminate_all(rxchan);
998
999 /*
1000 * This will take the chars we have so far and insert
1001 * into the framework.
1002 */
1003 pl011_dma_rx_chars(uap, pending, dmarx->use_buf_b, true);
1004
1005 /* Switch buffer & re-trigger DMA job */
1006 dmarx->use_buf_b = !dmarx->use_buf_b;
1007 if (pl011_dma_rx_trigger_dma(uap)) {
1008 dev_dbg(uap->port.dev, "could not retrigger RX DMA job "
1009 "fall back to interrupt mode\n");
1010 uap->im |= UART011_RXIM;
9f25bc51 1011 pl011_write(uap->im, uap, REG_IMSC);
ead76f32
LW		 1012 }
1013}
1014
1015static void pl011_dma_rx_callback(void *data)
1016{
1017 struct uart_amba_port *uap = data;
1018 struct pl011_dmarx_data *dmarx = &uap->dmarx;
6dc01aa6 1019 struct dma_chan *rxchan = dmarx->chan;
ead76f32 1020 bool lastbuf = dmarx->use_buf_b;
6dc01aa6
CM		 1021 struct pl011_sgbuf *sgbuf = dmarx->use_buf_b ?
1022 &dmarx->sgbuf_b : &dmarx->sgbuf_a;
1023 size_t pending;
1024 struct dma_tx_state state;
ead76f32
LW		 1025 int ret;
1026
1027 /*
1028 * This completion interrupt occurs typically when the
1029 * RX buffer is totally stuffed but no timeout has yet
1030 * occurred. When that happens, we just want the RX
1031 * routine to flush out the secondary DMA buffer while
1032 * we immediately trigger the next DMA job.
1033 */
1034 spin_lock_irq(&uap->port.lock);
6dc01aa6
CM		 1035 /*
1036 * Rx data can be taken by the UART interrupts during
1037 * the DMA irq handler. So we check the residue here.
1038 */
1039 rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state);
1040 pending = sgbuf->sg.length - state.residue;
1041 BUG_ON(pending > PL011_DMA_BUFFER_SIZE);
1042 /* Then we terminate the transfer - we now know our residue */
1043 dmaengine_terminate_all(rxchan);
1044
ead76f32
LW		 1045 uap->dmarx.running = false;
1046 dmarx->use_buf_b = !lastbuf;
1047 ret = pl011_dma_rx_trigger_dma(uap);
1048
6dc01aa6 1049 pl011_dma_rx_chars(uap, pending, lastbuf, false);
ead76f32
LW		 1050 spin_unlock_irq(&uap->port.lock);
1051 /*
1052 * Do this check after we picked the DMA chars so we don't
1053 * get some IRQ immediately from RX.
1054 */
1055 if (ret) {
1056 dev_dbg(uap->port.dev, "could not retrigger RX DMA job "
1057 "fall back to interrupt mode\n");
1058 uap->im |= UART011_RXIM;
9f25bc51 1059 pl011_write(uap->im, uap, REG_IMSC);
ead76f32
LW		 1060 }
1061}
1062
1063/*
1064 * Stop accepting received characters, when we're shutting down or
1065 * suspending this port.
1066 * Locking: called with port lock held and IRQs disabled.
1067 */
1068static inline void pl011_dma_rx_stop(struct uart_amba_port *uap)
1069{
1070 /* FIXME. Just disable the DMA enable */
1071 uap->dmacr &= ~UART011_RXDMAE;
9f25bc51 1072 pl011_write(uap->dmacr, uap, REG_DMACR);
ead76f32 1073}
68b65f73 1074
cb06ff10
CM		 1075/*
1076 * Timer handler for Rx DMA polling.
1077 * Every polling, It checks the residue in the dma buffer and transfer
1078 * data to the tty. Also, last_residue is updated for the next polling.
1079 */
f7f73096 1080static void pl011_dma_rx_poll(struct timer_list *t)
cb06ff10 1081{
f7f73096 1082 struct uart_amba_port *uap = from_timer(uap, t, dmarx.timer);
cb06ff10
CM		 1083 struct tty_port *port = &uap->port.state->port;
1084 struct pl011_dmarx_data *dmarx = &uap->dmarx;
1085 struct dma_chan *rxchan = uap->dmarx.chan;
1086 unsigned long flags = 0;
1087 unsigned int dmataken = 0;
1088 unsigned int size = 0;
1089 struct pl011_sgbuf *sgbuf;
1090 int dma_count;
1091 struct dma_tx_state state;
1092
1093 sgbuf = dmarx->use_buf_b ? &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a;
1094 rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state);
1095 if (likely(state.residue < dmarx->last_residue)) {
1096 dmataken = sgbuf->sg.length - dmarx->last_residue;
1097 size = dmarx->last_residue - state.residue;
1098 dma_count = tty_insert_flip_string(port, sgbuf->buf + dmataken,
1099 size);
1100 if (dma_count == size)
1101 dmarx->last_residue = state.residue;
1102 dmarx->last_jiffies = jiffies;
1103 }
1104 tty_flip_buffer_push(port);
1105
1106 /*
1107 * If no data is received in poll_timeout, the driver will fall back
1108 * to interrupt mode. We will retrigger DMA at the first interrupt.
1109 */
1110 if (jiffies_to_msecs(jiffies - dmarx->last_jiffies)
1111 > uap->dmarx.poll_timeout) {
1112
1113 spin_lock_irqsave(&uap->port.lock, flags);
1114 pl011_dma_rx_stop(uap);
c25a1ad7 1115 uap->im |= UART011_RXIM;
9f25bc51 1116 pl011_write(uap->im, uap, REG_IMSC);
cb06ff10
CM		 1117 spin_unlock_irqrestore(&uap->port.lock, flags);
1118
1119 uap->dmarx.running = false;
1120 dmaengine_terminate_all(rxchan);
1121 del_timer(&uap->dmarx.timer);
1122 } else {
1123 mod_timer(&uap->dmarx.timer,
1124 jiffies + msecs_to_jiffies(uap->dmarx.poll_rate));
1125 }
1126}
1127
68b65f73
RK		 1128static void pl011_dma_startup(struct uart_amba_port *uap)
1129{
ead76f32
LW		 1130 int ret;
1131
1c9be310
JRO		 1132 if (!uap->dma_probed)
1133 pl011_dma_probe(uap);
1134
68b65f73
RK		 1135 if (!uap->dmatx.chan)
1136 return;
1137
4c0be45b 1138 uap->dmatx.buf = kmalloc(PL011_DMA_BUFFER_SIZE, GFP_KERNEL | __GFP_DMA);
68b65f73
RK		 1139 if (!uap->dmatx.buf) {
1140 dev_err(uap->port.dev, "no memory for DMA TX buffer\n");
1141 uap->port.fifosize = uap->fifosize;
1142 return;
1143 }
1144
1145 sg_init_one(&uap->dmatx.sg, uap->dmatx.buf, PL011_DMA_BUFFER_SIZE);
1146
1147 /* The DMA buffer is now the FIFO the TTY subsystem can use */
1148 uap->port.fifosize = PL011_DMA_BUFFER_SIZE;
ead76f32
LW		 1149 uap->using_tx_dma = true;
1150
1151 if (!uap->dmarx.chan)
1152 goto skip_rx;
1153
1154 /* Allocate and map DMA RX buffers */
1155 ret = pl011_sgbuf_init(uap->dmarx.chan, &uap->dmarx.sgbuf_a,
1156 DMA_FROM_DEVICE);
1157 if (ret) {
1158 dev_err(uap->port.dev, "failed to init DMA %s: %d\n",
1159 "RX buffer A", ret);
1160 goto skip_rx;
1161 }
68b65f73 1162
ead76f32
LW		 1163 ret = pl011_sgbuf_init(uap->dmarx.chan, &uap->dmarx.sgbuf_b,
1164 DMA_FROM_DEVICE);
1165 if (ret) {
1166 dev_err(uap->port.dev, "failed to init DMA %s: %d\n",
1167 "RX buffer B", ret);
1168 pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_a,
1169 DMA_FROM_DEVICE);
1170 goto skip_rx;
1171 }
1172
1173 uap->using_rx_dma = true;
68b65f73 1174
ead76f32 1175skip_rx:
68b65f73
RK		 1176 /* Turn on DMA error (RX/TX will be enabled on demand) */
1177 uap->dmacr |= UART011_DMAONERR;
9f25bc51 1178 pl011_write(uap->dmacr, uap, REG_DMACR);
38d62436
RK		 1179
1180 /*
1181 * ST Micro variants has some specific dma burst threshold
1182 * compensation. Set this to 16 bytes, so burst will only
1183 * be issued above/below 16 bytes.
1184 */
1185 if (uap->vendor->dma_threshold)
75836339 1186 pl011_write(ST_UART011_DMAWM_RX_16 | ST_UART011_DMAWM_TX_16,
9f25bc51 1187 uap, REG_ST_DMAWM);
ead76f32
LW		 1188
1189 if (uap->using_rx_dma) {
1190 if (pl011_dma_rx_trigger_dma(uap))
1191 dev_dbg(uap->port.dev, "could not trigger initial "
1192 "RX DMA job, fall back to interrupt mode\n");
cb06ff10 1193 if (uap->dmarx.poll_rate) {
f7f73096 1194 timer_setup(&uap->dmarx.timer, pl011_dma_rx_poll, 0);
cb06ff10
CM		 1195 mod_timer(&uap->dmarx.timer,
1196 jiffies +
1197 msecs_to_jiffies(uap->dmarx.poll_rate));
1198 uap->dmarx.last_residue = PL011_DMA_BUFFER_SIZE;
1199 uap->dmarx.last_jiffies = jiffies;
1200 }
ead76f32 1201 }
68b65f73
RK		 1202}
1203
1204static void pl011_dma_shutdown(struct uart_amba_port *uap)
1205{
ead76f32 1206 if (!(uap->using_tx_dma || uap->using_rx_dma))
68b65f73
RK		 1207 return;
1208
1209 /* Disable RX and TX DMA */
0e125a5f 1210 while (pl011_read(uap, REG_FR) & uap->vendor->fr_busy)
2f2fd089 1211 cpu_relax();
68b65f73
RK		 1212
1213 spin_lock_irq(&uap->port.lock);
1214 uap->dmacr &= ~(UART011_DMAONERR | UART011_RXDMAE | UART011_TXDMAE);
9f25bc51 1215 pl011_write(uap->dmacr, uap, REG_DMACR);
68b65f73
RK		 1216 spin_unlock_irq(&uap->port.lock);
1217
ead76f32
LW		 1218 if (uap->using_tx_dma) {
1219 /* In theory, this should already be done by pl011_dma_flush_buffer */
1220 dmaengine_terminate_all(uap->dmatx.chan);
1221 if (uap->dmatx.queued) {
1222 dma_unmap_sg(uap->dmatx.chan->device->dev, &uap->dmatx.sg, 1,
1223 DMA_TO_DEVICE);
1224 uap->dmatx.queued = false;
1225 }
1226
1227 kfree(uap->dmatx.buf);
1228 uap->using_tx_dma = false;
68b65f73
RK		 1229 }
1230
ead76f32
LW		 1231 if (uap->using_rx_dma) {
1232 dmaengine_terminate_all(uap->dmarx.chan);
1233 /* Clean up the RX DMA */
1234 pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_a, DMA_FROM_DEVICE);
1235 pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_b, DMA_FROM_DEVICE);
cb06ff10
CM		 1236 if (uap->dmarx.poll_rate)
1237 del_timer_sync(&uap->dmarx.timer);
ead76f32
LW		 1238 uap->using_rx_dma = false;
1239 }
1240}
68b65f73 1241
ead76f32
LW		 1242static inline bool pl011_dma_rx_available(struct uart_amba_port *uap)
1243{
1244 return uap->using_rx_dma;
68b65f73
RK		 1245}
1246
ead76f32
LW		 1247static inline bool pl011_dma_rx_running(struct uart_amba_port *uap)
1248{
1249 return uap->using_rx_dma && uap->dmarx.running;
1250}
1251
68b65f73
RK		 1252#else
1253/* Blank functions if the DMA engine is not available */
1c9be310 1254static inline void pl011_dma_probe(struct uart_amba_port *uap)
68b65f73
RK		 1255{
1256}
1257
1258static inline void pl011_dma_remove(struct uart_amba_port *uap)
1259{
1260}
1261
1262static inline void pl011_dma_startup(struct uart_amba_port *uap)
1263{
1264}
1265
1266static inline void pl011_dma_shutdown(struct uart_amba_port *uap)
1267{
1268}
1269
1270static inline bool pl011_dma_tx_irq(struct uart_amba_port *uap)
1271{
1272 return false;
1273}
1274
1275static inline void pl011_dma_tx_stop(struct uart_amba_port *uap)
1276{
1277}
1278
1279static inline bool pl011_dma_tx_start(struct uart_amba_port *uap)
1280{
1281 return false;
1282}
1283
ead76f32
LW		 1284static inline void pl011_dma_rx_irq(struct uart_amba_port *uap)
1285{
1286}
1287
1288static inline void pl011_dma_rx_stop(struct uart_amba_port *uap)
1289{
1290}
1291
1292static inline int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap)
1293{
1294 return -EIO;
1295}
1296
1297static inline bool pl011_dma_rx_available(struct uart_amba_port *uap)
1298{
1299 return false;
1300}
1301
1302static inline bool pl011_dma_rx_running(struct uart_amba_port *uap)
1303{
1304 return false;
1305}
1306
68b65f73
RK		 1307#define pl011_dma_flush_buffer NULL
1308#endif
1309
b129a8cc 1310static void pl011_stop_tx(struct uart_port *port)
1da177e4 1311{
a5820c24
DT		 1312 struct uart_amba_port *uap =
1313 container_of(port, struct uart_amba_port, port);
1da177e4
LT		 1314
1315 uap->im &= ~UART011_TXIM;
9f25bc51 1316 pl011_write(uap->im, uap, REG_IMSC);
68b65f73 1317 pl011_dma_tx_stop(uap);
1da177e4
LT		 1318}
1319
7d05587c 1320static bool pl011_tx_chars(struct uart_amba_port *uap, bool from_irq);
734745ca
DM		 1321
1322/* Start TX with programmed I/O only (no DMA) */
1323static void pl011_start_tx_pio(struct uart_amba_port *uap)
1324{
7d05587c
J		 1325 if (pl011_tx_chars(uap, false)) {
1326 uap->im |= UART011_TXIM;
1327 pl011_write(uap->im, uap, REG_IMSC);
1328 }
734745ca
DM		 1329}
1330
b129a8cc 1331static void pl011_start_tx(struct uart_port *port)
1da177e4 1332{
a5820c24
DT		 1333 struct uart_amba_port *uap =
1334 container_of(port, struct uart_amba_port, port);
1da177e4 1335
734745ca
DM		 1336 if (!pl011_dma_tx_start(uap))
1337 pl011_start_tx_pio(uap);
1da177e4
LT		 1338}
1339
1340static void pl011_stop_rx(struct uart_port *port)
1341{
a5820c24
DT		 1342 struct uart_amba_port *uap =
1343 container_of(port, struct uart_amba_port, port);
1da177e4
LT		 1344
1345 uap->im &= ~(UART011_RXIM|UART011_RTIM|UART011_FEIM|
1346 UART011_PEIM|UART011_BEIM|UART011_OEIM);
9f25bc51 1347 pl011_write(uap->im, uap, REG_IMSC);
ead76f32
LW		 1348
1349 pl011_dma_rx_stop(uap);
1da177e4
LT		 1350}
1351
1352static void pl011_enable_ms(struct uart_port *port)
1353{
a5820c24
DT		 1354 struct uart_amba_port *uap =
1355 container_of(port, struct uart_amba_port, port);
1da177e4
LT		 1356
1357 uap->im |= UART011_RIMIM|UART011_CTSMIM|UART011_DCDMIM|UART011_DSRMIM;
9f25bc51 1358 pl011_write(uap->im, uap, REG_IMSC);
1da177e4
LT		 1359}
1360
7d12e780 1361static void pl011_rx_chars(struct uart_amba_port *uap)
b83286bf
FE		 1362__releases(&uap->port.lock)
1363__acquires(&uap->port.lock)
1da177e4 1364{
29772c4e 1365 pl011_fifo_to_tty(uap);
1da177e4 1366
2389b272 1367 spin_unlock(&uap->port.lock);
2e124b4a 1368 tty_flip_buffer_push(&uap->port.state->port);
ead76f32
LW		 1369 /*
1370 * If we were temporarily out of DMA mode for a while,
1371 * attempt to switch back to DMA mode again.
1372 */
1373 if (pl011_dma_rx_available(uap)) {
1374 if (pl011_dma_rx_trigger_dma(uap)) {
1375 dev_dbg(uap->port.dev, "could not trigger RX DMA job "
1376 "fall back to interrupt mode again\n");
1377 uap->im |= UART011_RXIM;
9f25bc51 1378 pl011_write(uap->im, uap, REG_IMSC);
cb06ff10 1379 } else {
89fa28db 1380#ifdef CONFIG_DMA_ENGINE
cb06ff10
CM		 1381 /* Start Rx DMA poll */
1382 if (uap->dmarx.poll_rate) {
1383 uap->dmarx.last_jiffies = jiffies;
1384 uap->dmarx.last_residue = PL011_DMA_BUFFER_SIZE;
1385 mod_timer(&uap->dmarx.timer,
1386 jiffies +
1387 msecs_to_jiffies(uap->dmarx.poll_rate));
1388 }
89fa28db 1389#endif
cb06ff10 1390 }
ead76f32 1391 }
2389b272 1392 spin_lock(&uap->port.lock);
1da177e4
LT		 1393}
1394
1e84d223
DM		 1395static bool pl011_tx_char(struct uart_amba_port *uap, unsigned char c,
1396 bool from_irq)
734745ca 1397{
1e84d223 1398 if (unlikely(!from_irq) &&
9f25bc51 1399 pl011_read(uap, REG_FR) & UART01x_FR_TXFF)
1e84d223
DM		 1400 return false; /* unable to transmit character */
1401
9f25bc51 1402 pl011_write(c, uap, REG_DR);
734745ca
DM		 1403 uap->port.icount.tx++;
1404
1e84d223 1405 return true;
734745ca
DM		 1406}
1407
7d05587c
J		 1408/* Returns true if tx interrupts have to be (kept) enabled */
1409static bool pl011_tx_chars(struct uart_amba_port *uap, bool from_irq)
1da177e4 1410{
ebd2c8f6 1411 struct circ_buf *xmit = &uap->port.state->xmit;
1e84d223 1412 int count = uap->fifosize >> 1;
734745ca 1413
1da177e4 1414 if (uap->port.x_char) {
1e84d223 1415 if (!pl011_tx_char(uap, uap->port.x_char, from_irq))
7d05587c 1416 return true;
1da177e4 1417 uap->port.x_char = 0;
734745ca 1418 --count;
1da177e4
LT		 1419 }
1420 if (uart_circ_empty(xmit) || uart_tx_stopped(&uap->port)) {
b129a8cc 1421 pl011_stop_tx(&uap->port);
7d05587c 1422 return false;
1da177e4
LT		 1423 }
1424
68b65f73
RK		 1425 /* If we are using DMA mode, try to send some characters. */
1426 if (pl011_dma_tx_irq(uap))
7d05587c 1427 return true;
68b65f73 1428
1e84d223
DM		 1429 do {
1430 if (likely(from_irq) && count-- == 0)
1da177e4 1431 break;
1e84d223
DM		 1432
1433 if (!pl011_tx_char(uap, xmit->buf[xmit->tail], from_irq))
1434 break;
1435
1436 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1437 } while (!uart_circ_empty(xmit));
1da177e4
LT		 1438
1439 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1440 uart_write_wakeup(&uap->port);
1441
7d05587c 1442 if (uart_circ_empty(xmit)) {
b129a8cc 1443 pl011_stop_tx(&uap->port);
7d05587c
J		 1444 return false;
1445 }
1446 return true;
1da177e4
LT		 1447}
1448
1449static void pl011_modem_status(struct uart_amba_port *uap)
1450{
1451 unsigned int status, delta;
1452
9f25bc51 1453 status = pl011_read(uap, REG_FR) & UART01x_FR_MODEM_ANY;
1da177e4
LT		 1454
1455 delta = status ^ uap->old_status;
1456 uap->old_status = status;
1457
1458 if (!delta)
1459 return;
1460
1461 if (delta & UART01x_FR_DCD)
1462 uart_handle_dcd_change(&uap->port, status & UART01x_FR_DCD);
1463
0e125a5f 1464 if (delta & uap->vendor->fr_dsr)
1da177e4
LT		 1465 uap->port.icount.dsr++;
1466
0e125a5f
SG		 1467 if (delta & uap->vendor->fr_cts)
1468 uart_handle_cts_change(&uap->port,
1469 status & uap->vendor->fr_cts);
1da177e4 1470
bdc04e31 1471 wake_up_interruptible(&uap->port.state->port.delta_msr_wait);
1da177e4
LT		 1472}
1473
9c4ef4b0
AP		 1474static void check_apply_cts_event_workaround(struct uart_amba_port *uap)
1475{
1476 unsigned int dummy_read;
1477
1478 if (!uap->vendor->cts_event_workaround)
1479 return;
1480
1481 /* workaround to make sure that all bits are unlocked.. */
9f25bc51 1482 pl011_write(0x00, uap, REG_ICR);
9c4ef4b0
AP		 1483
1484 /*
1485 * WA: introduce 26ns(1 uart clk) delay before W1C;
1486 * single apb access will incur 2 pclk(133.12Mhz) delay,
1487 * so add 2 dummy reads
1488 */
9f25bc51
RK		 1489 dummy_read = pl011_read(uap, REG_ICR);
1490 dummy_read = pl011_read(uap, REG_ICR);
9c4ef4b0
AP		 1491}
1492
7d12e780 1493static irqreturn_t pl011_int(int irq, void *dev_id)
1da177e4
LT		 1494{
1495 struct uart_amba_port *uap = dev_id;
963cc981 1496 unsigned long flags;
1da177e4 1497 unsigned int status, pass_counter = AMBA_ISR_PASS_LIMIT;
075167ed 1498 u16 imsc;
1da177e4
LT		 1499 int handled = 0;
1500
963cc981 1501 spin_lock_irqsave(&uap->port.lock, flags);
9f25bc51
RK		 1502 imsc = pl011_read(uap, REG_IMSC);
1503 status = pl011_read(uap, REG_RIS) & imsc;
1da177e4
LT		 1504 if (status) {
1505 do {
9c4ef4b0 1506 check_apply_cts_event_workaround(uap);
f11c9841 1507
75836339
RK		 1508 pl011_write(status & ~(UART011_TXIS|UART011_RTIS|
1509 UART011_RXIS),
9f25bc51 1510 uap, REG_ICR);
1da177e4 1511
ead76f32
LW		 1512 if (status & (UART011_RTIS|UART011_RXIS)) {
1513 if (pl011_dma_rx_running(uap))
1514 pl011_dma_rx_irq(uap);
1515 else
1516 pl011_rx_chars(uap);
1517 }
1da177e4
LT		 1518 if (status & (UART011_DSRMIS|UART011_DCDMIS|
1519 UART011_CTSMIS|UART011_RIMIS))
1520 pl011_modem_status(uap);
1e84d223
DM		 1521 if (status & UART011_TXIS)
1522 pl011_tx_chars(uap, true);
1da177e4 1523
4fd0690b 1524 if (pass_counter-- == 0)
1da177e4
LT		 1525 break;
1526
9f25bc51 1527 status = pl011_read(uap, REG_RIS) & imsc;
1da177e4
LT		 1528 } while (status != 0);
1529 handled = 1;
1530 }
1531
963cc981 1532 spin_unlock_irqrestore(&uap->port.lock, flags);
1da177e4
LT		 1533
1534 return IRQ_RETVAL(handled);
1535}
1536
e643f87f 1537static unsigned int pl011_tx_empty(struct uart_port *port)
1da177e4 1538{
a5820c24
DT		 1539 struct uart_amba_port *uap =
1540 container_of(port, struct uart_amba_port, port);
d8a4995b
CC		 1541
1542 /* Allow feature register bits to be inverted to work around errata */
1543 unsigned int status = pl011_read(uap, REG_FR) ^ uap->vendor->inv_fr;
1544
0e125a5f
SG		 1545 return status & (uap->vendor->fr_busy | UART01x_FR_TXFF) ?
1546 0 : TIOCSER_TEMT;
1da177e4
LT		 1547}
1548
e643f87f 1549static unsigned int pl011_get_mctrl(struct uart_port *port)
1da177e4 1550{
a5820c24
DT		 1551 struct uart_amba_port *uap =
1552 container_of(port, struct uart_amba_port, port);
1da177e4 1553 unsigned int result = 0;
9f25bc51 1554 unsigned int status = pl011_read(uap, REG_FR);
1da177e4 1555
5159f407 1556#define TIOCMBIT(uartbit, tiocmbit) \
1da177e4
LT		 1557 if (status & uartbit) \
1558 result |= tiocmbit
1559
5159f407 1560 TIOCMBIT(UART01x_FR_DCD, TIOCM_CAR);
0e125a5f
SG		 1561 TIOCMBIT(uap->vendor->fr_dsr, TIOCM_DSR);
1562 TIOCMBIT(uap->vendor->fr_cts, TIOCM_CTS);
1563 TIOCMBIT(uap->vendor->fr_ri, TIOCM_RNG);
5159f407 1564#undef TIOCMBIT
1da177e4
LT		 1565 return result;
1566}
1567
1568static void pl011_set_mctrl(struct uart_port *port, unsigned int mctrl)
1569{
a5820c24
DT		 1570 struct uart_amba_port *uap =
1571 container_of(port, struct uart_amba_port, port);
1da177e4
LT		 1572 unsigned int cr;
1573
9f25bc51 1574 cr = pl011_read(uap, REG_CR);
1da177e4 1575
5159f407 1576#define TIOCMBIT(tiocmbit, uartbit) \
1da177e4
LT		 1577 if (mctrl & tiocmbit) \
1578 cr |= uartbit; \
1579 else \
1580 cr &= ~uartbit
1581
5159f407
JS		 1582 TIOCMBIT(TIOCM_RTS, UART011_CR_RTS);
1583 TIOCMBIT(TIOCM_DTR, UART011_CR_DTR);
1584 TIOCMBIT(TIOCM_OUT1, UART011_CR_OUT1);
1585 TIOCMBIT(TIOCM_OUT2, UART011_CR_OUT2);
1586 TIOCMBIT(TIOCM_LOOP, UART011_CR_LBE);
3b43816f 1587
2a76fa28 1588 if (port->status & UPSTAT_AUTORTS) {
3b43816f
RV		 1589 /* We need to disable auto-RTS if we want to turn RTS off */
1590 TIOCMBIT(TIOCM_RTS, UART011_CR_RTSEN);
1591 }
5159f407 1592#undef TIOCMBIT
1da177e4 1593
9f25bc51 1594 pl011_write(cr, uap, REG_CR);
1da177e4
LT		 1595}
1596
1597static void pl011_break_ctl(struct uart_port *port, int break_state)
1598{
a5820c24
DT		 1599 struct uart_amba_port *uap =
1600 container_of(port, struct uart_amba_port, port);
1da177e4
LT		 1601 unsigned long flags;
1602 unsigned int lcr_h;
1603
1604 spin_lock_irqsave(&uap->port.lock, flags);
e4df9a80 1605 lcr_h = pl011_read(uap, REG_LCRH_TX);
1da177e4
LT		 1606 if (break_state == -1)
1607 lcr_h |= UART01x_LCRH_BRK;
1608 else
1609 lcr_h &= ~UART01x_LCRH_BRK;
e4df9a80 1610 pl011_write(lcr_h, uap, REG_LCRH_TX);
1da177e4
LT		 1611 spin_unlock_irqrestore(&uap->port.lock, flags);
1612}
1613
84b5ae15 1614#ifdef CONFIG_CONSOLE_POLL
5c8124a0
AV		 1615
1616static void pl011_quiesce_irqs(struct uart_port *port)
1617{
a5820c24
DT		 1618 struct uart_amba_port *uap =
1619 container_of(port, struct uart_amba_port, port);
5c8124a0 1620
9f25bc51 1621 pl011_write(pl011_read(uap, REG_MIS), uap, REG_ICR);
5c8124a0
AV		 1622 /*
1623 * There is no way to clear TXIM as this is "ready to transmit IRQ", so
1624 * we simply mask it. start_tx() will unmask it.
1625 *
1626 * Note we can race with start_tx(), and if the race happens, the
1627 * polling user might get another interrupt just after we clear it.
1628 * But it should be OK and can happen even w/o the race, e.g.
1629 * controller immediately got some new data and raised the IRQ.
1630 *
1631 * And whoever uses polling routines assumes that it manages the device
1632 * (including tx queue), so we're also fine with start_tx()'s caller
1633 * side.
1634 */
9f25bc51
RK		 1635 pl011_write(pl011_read(uap, REG_IMSC) & ~UART011_TXIM, uap,
1636 REG_IMSC);
5c8124a0
AV		 1637}
1638
e643f87f 1639static int pl011_get_poll_char(struct uart_port *port)
84b5ae15 1640{
a5820c24
DT		 1641 struct uart_amba_port *uap =
1642 container_of(port, struct uart_amba_port, port);
84b5ae15
JW		 1643 unsigned int status;
1644
5c8124a0
AV		 1645 /*
1646 * The caller might need IRQs lowered, e.g. if used with KDB NMI
1647 * debugger.
1648 */
1649 pl011_quiesce_irqs(port);
1650
9f25bc51 1651 status = pl011_read(uap, REG_FR);
f5316b4a
JW		 1652 if (status & UART01x_FR_RXFE)
1653 return NO_POLL_CHAR;
84b5ae15 1654
9f25bc51 1655 return pl011_read(uap, REG_DR);
84b5ae15
JW		 1656}
1657
e643f87f 1658static void pl011_put_poll_char(struct uart_port *port,
84b5ae15
JW		 1659 unsigned char ch)
1660{
a5820c24
DT		 1661 struct uart_amba_port *uap =
1662 container_of(port, struct uart_amba_port, port);
84b5ae15 1663
9f25bc51 1664 while (pl011_read(uap, REG_FR) & UART01x_FR_TXFF)
2f2fd089 1665 cpu_relax();
84b5ae15 1666
9f25bc51 1667 pl011_write(ch, uap, REG_DR);
84b5ae15
JW		 1668}
1669
1670#endif /* CONFIG_CONSOLE_POLL */
1671
b3564c2c 1672static int pl011_hwinit(struct uart_port *port)
1da177e4 1673{
a5820c24
DT		 1674 struct uart_amba_port *uap =
1675 container_of(port, struct uart_amba_port, port);
1da177e4
LT		 1676 int retval;
1677
78d80c5a 1678 /* Optionaly enable pins to be muxed in and configured */
2b996fc5 1679 pinctrl_pm_select_default_state(port->dev);
78d80c5a 1680
1da177e4
LT		 1681 /*
1682 * Try to enable the clock producer.
1683 */
1c4c4394 1684 retval = clk_prepare_enable(uap->clk);
1da177e4 1685 if (retval)
7f6d942a 1686 return retval;
1da177e4
LT		 1687
1688 uap->port.uartclk = clk_get_rate(uap->clk);
1689
9b96fbac 1690 /* Clear pending error and receive interrupts */
75836339
RK		 1691 pl011_write(UART011_OEIS | UART011_BEIS | UART011_PEIS |
1692 UART011_FEIS | UART011_RTIS | UART011_RXIS,
9f25bc51 1693 uap, REG_ICR);
9b96fbac 1694
b3564c2c
AV		 1695 /*
1696 * Save interrupts enable mask, and enable RX interrupts in case if
1697 * the interrupt is used for NMI entry.
1698 */
9f25bc51
RK		 1699 uap->im = pl011_read(uap, REG_IMSC);
1700 pl011_write(UART011_RTIM | UART011_RXIM, uap, REG_IMSC);
b3564c2c 1701
574de559 1702 if (dev_get_platdata(uap->port.dev)) {
b3564c2c
AV		 1703 struct amba_pl011_data *plat;
1704
574de559 1705 plat = dev_get_platdata(uap->port.dev);
b3564c2c
AV		 1706 if (plat->init)
1707 plat->init();
1708 }
1709 return 0;
b3564c2c
AV		 1710}
1711
7fe9a5a9
RK		 1712static bool pl011_split_lcrh(const struct uart_amba_port *uap)
1713{
e4df9a80
RK		 1714 return pl011_reg_to_offset(uap, REG_LCRH_RX) !=
1715 pl011_reg_to_offset(uap, REG_LCRH_TX);
7fe9a5a9
RK		 1716}
1717
b60f2f66
JM		 1718static void pl011_write_lcr_h(struct uart_amba_port *uap, unsigned int lcr_h)
1719{
e4df9a80 1720 pl011_write(lcr_h, uap, REG_LCRH_RX);
7fe9a5a9 1721 if (pl011_split_lcrh(uap)) {
b60f2f66
JM		 1722 int i;
1723 /*
1724 * Wait 10 PCLKs before writing LCRH_TX register,
1725 * to get this delay write read only register 10 times
1726 */
1727 for (i = 0; i < 10; ++i)
9f25bc51 1728 pl011_write(0xff, uap, REG_MIS);
e4df9a80 1729 pl011_write(lcr_h, uap, REG_LCRH_TX);
b60f2f66
JM		 1730 }
1731}
1732
867b8e8e
AP		 1733static int pl011_allocate_irq(struct uart_amba_port *uap)
1734{
9f25bc51 1735 pl011_write(uap->im, uap, REG_IMSC);
867b8e8e
AP		 1736
1737 return request_irq(uap->port.irq, pl011_int, 0, "uart-pl011", uap);
1738}
1739
1740/*
1741 * Enable interrupts, only timeouts when using DMA
1742 * if initial RX DMA job failed, start in interrupt mode
1743 * as well.
1744 */
1745static void pl011_enable_interrupts(struct uart_amba_port *uap)
1746{
1747 spin_lock_irq(&uap->port.lock);
1748
1749 /* Clear out any spuriously appearing RX interrupts */
9f25bc51 1750 pl011_write(UART011_RTIS | UART011_RXIS, uap, REG_ICR);
867b8e8e
AP		 1751 uap->im = UART011_RTIM;
1752 if (!pl011_dma_rx_running(uap))
1753 uap->im |= UART011_RXIM;
9f25bc51 1754 pl011_write(uap->im, uap, REG_IMSC);
867b8e8e
AP		 1755 spin_unlock_irq(&uap->port.lock);
1756}
1757
b3564c2c
AV		 1758static int pl011_startup(struct uart_port *port)
1759{
a5820c24
DT		 1760 struct uart_amba_port *uap =
1761 container_of(port, struct uart_amba_port, port);
734745ca 1762 unsigned int cr;
b3564c2c
AV		 1763 int retval;
1764
1765 retval = pl011_hwinit(port);
1766 if (retval)
1767 goto clk_dis;
1768
867b8e8e 1769 retval = pl011_allocate_irq(uap);
1da177e4
LT		 1770 if (retval)
1771 goto clk_dis;
1772
9f25bc51 1773 pl011_write(uap->vendor->ifls, uap, REG_IFLS);
1da177e4 1774
734745ca 1775 spin_lock_irq(&uap->port.lock);
570d2910 1776
d8d8ffa4
SKS		 1777 /* restore RTS and DTR */
1778 cr = uap->old_cr & (UART011_CR_RTS | UART011_CR_DTR);
1779 cr |= UART01x_CR_UARTEN | UART011_CR_RXE | UART011_CR_TXE;
9f25bc51 1780 pl011_write(cr, uap, REG_CR);
1da177e4 1781
fe433907
JM		 1782 spin_unlock_irq(&uap->port.lock);
1783
1da177e4
LT		 1784 /*
1785 * initialise the old status of the modem signals
1786 */
9f25bc51 1787 uap->old_status = pl011_read(uap, REG_FR) & UART01x_FR_MODEM_ANY;
1da177e4 1788
68b65f73
RK		 1789 /* Startup DMA */
1790 pl011_dma_startup(uap);
1791
867b8e8e 1792 pl011_enable_interrupts(uap);
1da177e4
LT		 1793
1794 return 0;
1795
1796 clk_dis:
1c4c4394 1797 clk_disable_unprepare(uap->clk);
1da177e4
LT		 1798 return retval;
1799}
1800
0dd1e247
AP		 1801static int sbsa_uart_startup(struct uart_port *port)
1802{
1803 struct uart_amba_port *uap =
1804 container_of(port, struct uart_amba_port, port);
1805 int retval;
1806
1807 retval = pl011_hwinit(port);
1808 if (retval)
1809 return retval;
1810
1811 retval = pl011_allocate_irq(uap);
1812 if (retval)
1813 return retval;
1814
1815 /* The SBSA UART does not support any modem status lines. */
1816 uap->old_status = 0;
1817
1818 pl011_enable_interrupts(uap);
1819
1820 return 0;
1821}
1822
ec489aa8
LW		 1823static void pl011_shutdown_channel(struct uart_amba_port *uap,
1824 unsigned int lcrh)
1825{
f11c9841 1826 unsigned long val;
ec489aa8 1827
b2a4e24c 1828 val = pl011_read(uap, lcrh);
f11c9841 1829 val &= ~(UART01x_LCRH_BRK | UART01x_LCRH_FEN);
b2a4e24c 1830 pl011_write(val, uap, lcrh);
ec489aa8
LW		 1831}
1832
95166a3f
AP		 1833/*
1834 * disable the port. It should not disable RTS and DTR.
1835 * Also RTS and DTR state should be preserved to restore
1836 * it during startup().
1837 */
1838static void pl011_disable_uart(struct uart_amba_port *uap)
1da177e4 1839{
d8d8ffa4 1840 unsigned int cr;
1da177e4 1841
2a76fa28 1842 uap->port.status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS);
fe433907 1843 spin_lock_irq(&uap->port.lock);
9f25bc51 1844 cr = pl011_read(uap, REG_CR);
d8d8ffa4
SKS		 1845 uap->old_cr = cr;
1846 cr &= UART011_CR_RTS | UART011_CR_DTR;
1847 cr |= UART01x_CR_UARTEN | UART011_CR_TXE;
9f25bc51 1848 pl011_write(cr, uap, REG_CR);
fe433907 1849 spin_unlock_irq(&uap->port.lock);
1da177e4
LT		 1850
1851 /*
1852 * disable break condition and fifos
1853 */
e4df9a80 1854 pl011_shutdown_channel(uap, REG_LCRH_RX);
7fe9a5a9 1855 if (pl011_split_lcrh(uap))
e4df9a80 1856 pl011_shutdown_channel(uap, REG_LCRH_TX);
95166a3f
AP		 1857}
1858
1859static void pl011_disable_interrupts(struct uart_amba_port *uap)
1860{
1861 spin_lock_irq(&uap->port.lock);
1862
1863 /* mask all interrupts and clear all pending ones */
1864 uap->im = 0;
9f25bc51
RK		 1865 pl011_write(uap->im, uap, REG_IMSC);
1866 pl011_write(0xffff, uap, REG_ICR);
95166a3f
AP		 1867
1868 spin_unlock_irq(&uap->port.lock);
1869}
1870
1871static void pl011_shutdown(struct uart_port *port)
1872{
1873 struct uart_amba_port *uap =
1874 container_of(port, struct uart_amba_port, port);
1875
1876 pl011_disable_interrupts(uap);
1877
1878 pl011_dma_shutdown(uap);
1879
1880 free_irq(uap->port.irq, uap);
1881
1882 pl011_disable_uart(uap);
1da177e4
LT		 1883
1884 /*
1885 * Shut down the clock producer
1886 */
1c4c4394 1887 clk_disable_unprepare(uap->clk);
78d80c5a 1888 /* Optionally let pins go into sleep states */
2b996fc5 1889 pinctrl_pm_select_sleep_state(port->dev);
c16d51a3 1890
574de559 1891 if (dev_get_platdata(uap->port.dev)) {
c16d51a3
SKS		 1892 struct amba_pl011_data *plat;
1893
574de559 1894 plat = dev_get_platdata(uap->port.dev);
c16d51a3
SKS		 1895 if (plat->exit)
1896 plat->exit();
1897 }
1898
36f339d1
PH		 1899 if (uap->port.ops->flush_buffer)
1900 uap->port.ops->flush_buffer(port);
1da177e4
LT		 1901}
1902
0dd1e247
AP		 1903static void sbsa_uart_shutdown(struct uart_port *port)
1904{
1905 struct uart_amba_port *uap =
1906 container_of(port, struct uart_amba_port, port);
1907
1908 pl011_disable_interrupts(uap);
1909
1910 free_irq(uap->port.irq, uap);
1911
1912 if (uap->port.ops->flush_buffer)
1913 uap->port.ops->flush_buffer(port);
1914}
1915
ef5a9358
AP		 1916static void
1917pl011_setup_status_masks(struct uart_port *port, struct ktermios *termios)
1918{
1919 port->read_status_mask = UART011_DR_OE | 255;
1920 if (termios->c_iflag & INPCK)
1921 port->read_status_mask |= UART011_DR_FE | UART011_DR_PE;
1922 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
1923 port->read_status_mask |= UART011_DR_BE;
1924
1925 /*
1926 * Characters to ignore
1927 */
1928 port->ignore_status_mask = 0;
1929 if (termios->c_iflag & IGNPAR)
1930 port->ignore_status_mask |= UART011_DR_FE | UART011_DR_PE;
1931 if (termios->c_iflag & IGNBRK) {
1932 port->ignore_status_mask |= UART011_DR_BE;
1933 /*
1934 * If we're ignoring parity and break indicators,
1935 * ignore overruns too (for real raw support).
1936 */
1937 if (termios->c_iflag & IGNPAR)
1938 port->ignore_status_mask |= UART011_DR_OE;
1939 }
1940
1941 /*
1942 * Ignore all characters if CREAD is not set.
1943 */
1944 if ((termios->c_cflag & CREAD) == 0)
1945 port->ignore_status_mask |= UART_DUMMY_DR_RX;
1946}
1947
1da177e4 1948static void
606d099c
AC		 1949pl011_set_termios(struct uart_port *port, struct ktermios *termios,
1950 struct ktermios *old)
1da177e4 1951{
a5820c24
DT		 1952 struct uart_amba_port *uap =
1953 container_of(port, struct uart_amba_port, port);
1da177e4
LT		 1954 unsigned int lcr_h, old_cr;
1955 unsigned long flags;
c19f12b5
RK		 1956 unsigned int baud, quot, clkdiv;
1957
1958 if (uap->vendor->oversampling)
1959 clkdiv = 8;
1960 else
1961 clkdiv = 16;
1da177e4
LT		 1962
1963 /*
1964 * Ask the core to calculate the divisor for us.
1965 */
ac3e3fb4 1966 baud = uart_get_baud_rate(port, termios, old, 0,
c19f12b5 1967 port->uartclk / clkdiv);
89fa28db 1968#ifdef CONFIG_DMA_ENGINE
cb06ff10
CM		 1969 /*
1970 * Adjust RX DMA polling rate with baud rate if not specified.
1971 */
1972 if (uap->dmarx.auto_poll_rate)
1973 uap->dmarx.poll_rate = DIV_ROUND_UP(10000000, baud);
89fa28db 1974#endif
ac3e3fb4
LW		 1975
1976 if (baud > port->uartclk/16)
1977 quot = DIV_ROUND_CLOSEST(port->uartclk * 8, baud);
1978 else
1979 quot = DIV_ROUND_CLOSEST(port->uartclk * 4, baud);
1da177e4
LT		 1980
1981 switch (termios->c_cflag & CSIZE) {
1982 case CS5:
1983 lcr_h = UART01x_LCRH_WLEN_5;
1984 break;
1985 case CS6:
1986 lcr_h = UART01x_LCRH_WLEN_6;
1987 break;
1988 case CS7:
1989 lcr_h = UART01x_LCRH_WLEN_7;
1990 break;
1991 default: // CS8
1992 lcr_h = UART01x_LCRH_WLEN_8;
1993 break;
1994 }
1995 if (termios->c_cflag & CSTOPB)
1996 lcr_h |= UART01x_LCRH_STP2;
1997 if (termios->c_cflag & PARENB) {
1998 lcr_h |= UART01x_LCRH_PEN;
1999 if (!(termios->c_cflag & PARODD))
2000 lcr_h |= UART01x_LCRH_EPS;
bb70002c
ES		 2001 if (termios->c_cflag & CMSPAR)
2002 lcr_h |= UART011_LCRH_SPS;
1da177e4 2003 }
ffca2b11 2004 if (uap->fifosize > 1)
1da177e4
LT		 2005 lcr_h |= UART01x_LCRH_FEN;
2006
2007 spin_lock_irqsave(&port->lock, flags);
2008
2009 /*
2010 * Update the per-port timeout.
2011 */
2012 uart_update_timeout(port, termios->c_cflag, baud);
2013
ef5a9358 2014 pl011_setup_status_masks(port, termios);
1da177e4
LT		 2015
2016 if (UART_ENABLE_MS(port, termios->c_cflag))
2017 pl011_enable_ms(port);
2018
2019 /* first, disable everything */
9f25bc51
RK		 2020 old_cr = pl011_read(uap, REG_CR);
2021 pl011_write(0, uap, REG_CR);
1da177e4 2022
3b43816f
RV		 2023 if (termios->c_cflag & CRTSCTS) {
2024 if (old_cr & UART011_CR_RTS)
2025 old_cr |= UART011_CR_RTSEN;
2026
2027 old_cr |= UART011_CR_CTSEN;
2a76fa28 2028 port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS;
3b43816f
RV		 2029 } else {
2030 old_cr &= ~(UART011_CR_CTSEN | UART011_CR_RTSEN);
2a76fa28 2031 port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS);
3b43816f
RV		 2032 }
2033
c19f12b5
RK		 2034 if (uap->vendor->oversampling) {
2035 if (baud > port->uartclk / 16)
ac3e3fb4
LW		 2036 old_cr |= ST_UART011_CR_OVSFACT;
2037 else
2038 old_cr &= ~ST_UART011_CR_OVSFACT;
2039 }
2040
c5dd553b
LW		 2041 /*
2042 * Workaround for the ST Micro oversampling variants to
2043 * increase the bitrate slightly, by lowering the divisor,
2044 * to avoid delayed sampling of start bit at high speeds,
2045 * else we see data corruption.
2046 */
2047 if (uap->vendor->oversampling) {
2048 if ((baud >= 3000000) && (baud < 3250000) && (quot > 1))
2049 quot -= 1;
2050 else if ((baud > 3250000) && (quot > 2))
2051 quot -= 2;
2052 }
1da177e4 2053 /* Set baud rate */
9f25bc51
RK		 2054 pl011_write(quot & 0x3f, uap, REG_FBRD);
2055 pl011_write(quot >> 6, uap, REG_IBRD);
1da177e4
LT		 2056
2057 /*
2058 * ----------v----------v----------v----------v-----
e4df9a80 2059 * NOTE: REG_LCRH_TX and REG_LCRH_RX MUST BE WRITTEN AFTER
9f25bc51 2060 * REG_FBRD & REG_IBRD.
1da177e4
LT		 2061 * ----------^----------^----------^----------^-----
2062 */
b60f2f66 2063 pl011_write_lcr_h(uap, lcr_h);
9f25bc51 2064 pl011_write(old_cr, uap, REG_CR);
1da177e4
LT		 2065
2066 spin_unlock_irqrestore(&port->lock, flags);
2067}
2068
0dd1e247
AP		 2069static void
2070sbsa_uart_set_termios(struct uart_port *port, struct ktermios *termios,
2071 struct ktermios *old)
2072{
2073 struct uart_amba_port *uap =
2074 container_of(port, struct uart_amba_port, port);
2075 unsigned long flags;
2076
2077 tty_termios_encode_baud_rate(termios, uap->fixed_baud, uap->fixed_baud);
2078
2079 /* The SBSA UART only supports 8n1 without hardware flow control. */
2080 termios->c_cflag &= ~(CSIZE | CSTOPB | PARENB | PARODD);
2081 termios->c_cflag &= ~(CMSPAR | CRTSCTS);
2082 termios->c_cflag |= CS8 | CLOCAL;
2083
2084 spin_lock_irqsave(&port->lock, flags);
2085 uart_update_timeout(port, CS8, uap->fixed_baud);
2086 pl011_setup_status_masks(port, termios);
2087 spin_unlock_irqrestore(&port->lock, flags);
2088}
2089
1da177e4
LT		 2090static const char *pl011_type(struct uart_port *port)
2091{
a5820c24
DT		 2092 struct uart_amba_port *uap =
2093 container_of(port, struct uart_amba_port, port);
e8a7ba86 2094 return uap->port.type == PORT_AMBA ? uap->type : NULL;
1da177e4
LT		 2095}
2096
2097/*
2098 * Release the memory region(s) being used by 'port'
2099 */
e643f87f 2100static void pl011_release_port(struct uart_port *port)
1da177e4
LT		 2101{
2102 release_mem_region(port->mapbase, SZ_4K);
2103}
2104
2105/*
2106 * Request the memory region(s) being used by 'port'
2107 */
e643f87f 2108static int pl011_request_port(struct uart_port *port)
1da177e4
LT		 2109{
2110 return request_mem_region(port->mapbase, SZ_4K, "uart-pl011")
2111 != NULL ? 0 : -EBUSY;
2112}
2113
2114/*
2115 * Configure/autoconfigure the port.
2116 */
e643f87f 2117static void pl011_config_port(struct uart_port *port, int flags)
1da177e4
LT		 2118{
2119 if (flags & UART_CONFIG_TYPE) {
2120 port->type = PORT_AMBA;
e643f87f 2121 pl011_request_port(port);
1da177e4
LT		 2122 }
2123}
2124
2125/*
2126 * verify the new serial_struct (for TIOCSSERIAL).
2127 */
e643f87f 2128static int pl011_verify_port(struct uart_port *port, struct serial_struct *ser)
1da177e4
LT		 2129{
2130 int ret = 0;
2131 if (ser->type != PORT_UNKNOWN && ser->type != PORT_AMBA)
2132 ret = -EINVAL;
a62c4133 2133 if (ser->irq < 0 || ser->irq >= nr_irqs)
1da177e4
LT		 2134 ret = -EINVAL;
2135 if (ser->baud_base < 9600)
2136 ret = -EINVAL;
2137 return ret;
2138}
2139
2331e068 2140static const struct uart_ops amba_pl011_pops = {
e643f87f 2141 .tx_empty = pl011_tx_empty,
1da177e4 2142 .set_mctrl = pl011_set_mctrl,
e643f87f 2143 .get_mctrl = pl011_get_mctrl,
1da177e4
LT		 2144 .stop_tx = pl011_stop_tx,
2145 .start_tx = pl011_start_tx,
2146 .stop_rx = pl011_stop_rx,
2147 .enable_ms = pl011_enable_ms,
2148 .break_ctl = pl011_break_ctl,
2149 .startup = pl011_startup,
2150 .shutdown = pl011_shutdown,
68b65f73 2151 .flush_buffer = pl011_dma_flush_buffer,
1da177e4
LT		 2152 .set_termios = pl011_set_termios,
2153 .type = pl011_type,
e643f87f
LW		 2154 .release_port = pl011_release_port,
2155 .request_port = pl011_request_port,
2156 .config_port = pl011_config_port,
2157 .verify_port = pl011_verify_port,
84b5ae15 2158#ifdef CONFIG_CONSOLE_POLL
b3564c2c 2159 .poll_init = pl011_hwinit,
e643f87f
LW		 2160 .poll_get_char = pl011_get_poll_char,
2161 .poll_put_char = pl011_put_poll_char,
84b5ae15 2162#endif
1da177e4
LT		 2163};
2164
0dd1e247
AP		 2165static void sbsa_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
2166{
2167}
2168
2169static unsigned int sbsa_uart_get_mctrl(struct uart_port *port)
2170{
2171 return 0;
2172}
2173
2174static const struct uart_ops sbsa_uart_pops = {
2175 .tx_empty = pl011_tx_empty,
2176 .set_mctrl = sbsa_uart_set_mctrl,
2177 .get_mctrl = sbsa_uart_get_mctrl,
2178 .stop_tx = pl011_stop_tx,
2179 .start_tx = pl011_start_tx,
2180 .stop_rx = pl011_stop_rx,
2181 .startup = sbsa_uart_startup,
2182 .shutdown = sbsa_uart_shutdown,
2183 .set_termios = sbsa_uart_set_termios,
2184 .type = pl011_type,
2185 .release_port = pl011_release_port,
2186 .request_port = pl011_request_port,
2187 .config_port = pl011_config_port,
2188 .verify_port = pl011_verify_port,
2189#ifdef CONFIG_CONSOLE_POLL
2190 .poll_init = pl011_hwinit,
2191 .poll_get_char = pl011_get_poll_char,
2192 .poll_put_char = pl011_put_poll_char,
2193#endif
2194};
2195
1da177e4
LT		 2196static struct uart_amba_port *amba_ports[UART_NR];
2197
2198#ifdef CONFIG_SERIAL_AMBA_PL011_CONSOLE
2199
d358788f 2200static void pl011_console_putchar(struct uart_port *port, int ch)
1da177e4 2201{
a5820c24
DT		 2202 struct uart_amba_port *uap =
2203 container_of(port, struct uart_amba_port, port);
1da177e4 2204
9f25bc51 2205 while (pl011_read(uap, REG_FR) & UART01x_FR_TXFF)
2f2fd089 2206 cpu_relax();
9f25bc51 2207 pl011_write(ch, uap, REG_DR);
1da177e4
LT		 2208}
2209
2210static void
2211pl011_console_write(struct console *co, const char *s, unsigned int count)
2212{
2213 struct uart_amba_port *uap = amba_ports[co->index];
2f2fd089 2214 unsigned int old_cr = 0, new_cr;
ef605fdb
RV		 2215 unsigned long flags;
2216 int locked = 1;
1da177e4
LT		 2217
2218 clk_enable(uap->clk);
2219
ef605fdb
RV		 2220 local_irq_save(flags);
2221 if (uap->port.sysrq)
2222 locked = 0;
2223 else if (oops_in_progress)
2224 locked = spin_trylock(&uap->port.lock);
2225 else
2226 spin_lock(&uap->port.lock);
2227
1da177e4
LT		 2228 /*
2229 * First save the CR then disable the interrupts
2230 */
71eec483 2231 if (!uap->vendor->always_enabled) {
9f25bc51 2232 old_cr = pl011_read(uap, REG_CR);
71eec483
AP		 2233 new_cr = old_cr & ~UART011_CR_CTSEN;
2234 new_cr |= UART01x_CR_UARTEN | UART011_CR_TXE;
9f25bc51 2235 pl011_write(new_cr, uap, REG_CR);
71eec483 2236 }
1da177e4 2237
d358788f 2238 uart_console_write(&uap->port, s, count, pl011_console_putchar);
1da177e4
LT		 2239
2240 /*
d8a4995b
CC		 2241 * Finally, wait for transmitter to become empty and restore the
2242 * TCR. Allow feature register bits to be inverted to work around
2243 * errata.
1da177e4 2244 */
d8a4995b
CC		 2245 while ((pl011_read(uap, REG_FR) ^ uap->vendor->inv_fr)
2246 & uap->vendor->fr_busy)
2f2fd089 2247 cpu_relax();
71eec483 2248 if (!uap->vendor->always_enabled)
9f25bc51 2249 pl011_write(old_cr, uap, REG_CR);
1da177e4 2250
ef605fdb
RV		 2251 if (locked)
2252 spin_unlock(&uap->port.lock);
2253 local_irq_restore(flags);
2254
1da177e4
LT		 2255 clk_disable(uap->clk);
2256}
2257
2258static void __init
2259pl011_console_get_options(struct uart_amba_port *uap, int *baud,
2260 int *parity, int *bits)
2261{
9f25bc51 2262 if (pl011_read(uap, REG_CR) & UART01x_CR_UARTEN) {
1da177e4
LT		 2263 unsigned int lcr_h, ibrd, fbrd;
2264
e4df9a80 2265 lcr_h = pl011_read(uap, REG_LCRH_TX);
1da177e4
LT		 2266
2267 *parity = 'n';
2268 if (lcr_h & UART01x_LCRH_PEN) {
2269 if (lcr_h & UART01x_LCRH_EPS)
2270 *parity = 'e';
2271 else
2272 *parity = 'o';
2273 }
2274
2275 if ((lcr_h & 0x60) == UART01x_LCRH_WLEN_7)
2276 *bits = 7;
2277 else
2278 *bits = 8;
2279
9f25bc51
RK		 2280 ibrd = pl011_read(uap, REG_IBRD);
2281 fbrd = pl011_read(uap, REG_FBRD);
1da177e4
LT		 2282
2283 *baud = uap->port.uartclk * 4 / (64 * ibrd + fbrd);
ac3e3fb4 2284
c19f12b5 2285 if (uap->vendor->oversampling) {
9f25bc51 2286 if (pl011_read(uap, REG_CR)
ac3e3fb4
LW		 2287 & ST_UART011_CR_OVSFACT)
2288 *baud *= 2;
2289 }
1da177e4
LT		 2290 }
2291}
2292
2293static int __init pl011_console_setup(struct console *co, char *options)
2294{
2295 struct uart_amba_port *uap;
2296 int baud = 38400;
2297 int bits = 8;
2298 int parity = 'n';
2299 int flow = 'n';
4b4851c6 2300 int ret;
1da177e4
LT		 2301
2302 /*
2303 * Check whether an invalid uart number has been specified, and
2304 * if so, search for the first available port that does have
2305 * console support.
2306 */
2307 if (co->index >= UART_NR)
2308 co->index = 0;
2309 uap = amba_ports[co->index];
d28122a5
RK		 2310 if (!uap)
2311 return -ENODEV;
1da177e4 2312
78d80c5a 2313 /* Allow pins to be muxed in and configured */
2b996fc5 2314 pinctrl_pm_select_default_state(uap->port.dev);
78d80c5a 2315
4b4851c6
RK		 2316 ret = clk_prepare(uap->clk);
2317 if (ret)
2318 return ret;
2319
574de559 2320 if (dev_get_platdata(uap->port.dev)) {
c16d51a3
SKS		 2321 struct amba_pl011_data *plat;
2322
574de559 2323 plat = dev_get_platdata(uap->port.dev);
c16d51a3
SKS		 2324 if (plat->init)
2325 plat->init();
2326 }
2327
1da177e4
LT		 2328 uap->port.uartclk = clk_get_rate(uap->clk);
2329
cefc2d1d
AP		 2330 if (uap->vendor->fixed_options) {
2331 baud = uap->fixed_baud;
2332 } else {
2333 if (options)
2334 uart_parse_options(options,
2335 &baud, &parity, &bits, &flow);
2336 else
2337 pl011_console_get_options(uap, &baud, &parity, &bits);
2338 }
1da177e4
LT		 2339
2340 return uart_set_options(&uap->port, co, baud, parity, bits, flow);
2341}
2342
10879ae5
AM		 2343/**
2344 * pl011_console_match - non-standard console matching
2345 * @co: registering console
2346 * @name: name from console command line
2347 * @idx: index from console command line
2348 * @options: ptr to option string from console command line
2349 *
2350 * Only attempts to match console command lines of the form:
2351 * console=pl011,mmio|mmio32,<addr>[,<options>]
2352 * console=pl011,0x<addr>[,<options>]
2353 * This form is used to register an initial earlycon boot console and
2354 * replace it with the amba_console at pl011 driver init.
2355 *
2356 * Performs console setup for a match (as required by interface)
2357 * If no <options> are specified, then assume the h/w is already setup.
2358 *
2359 * Returns 0 if console matches; otherwise non-zero to use default matching
2360 */
2361static int __init pl011_console_match(struct console *co, char *name, int idx,
2362 char *options)
2363{
2364 unsigned char iotype;
2365 resource_size_t addr;
2366 int i;
2367
37ef38f3
TT		 2368 /*
2369 * Systems affected by the Qualcomm Technologies QDF2400 E44 erratum
2370 * have a distinct console name, so make sure we check for that.
2371 * The actual implementation of the erratum occurs in the probe
2372 * function.
2373 */
2374 if ((strcmp(name, "qdf2400_e44") != 0) && (strcmp(name, "pl011") != 0))
10879ae5
AM		 2375 return -ENODEV;
2376
2377 if (uart_parse_earlycon(options, &iotype, &addr, &options))
2378 return -ENODEV;
2379
2380 if (iotype != UPIO_MEM && iotype != UPIO_MEM32)
2381 return -ENODEV;
2382
2383 /* try to match the port specified on the command line */
2384 for (i = 0; i < ARRAY_SIZE(amba_ports); i++) {
2385 struct uart_port *port;
2386
2387 if (!amba_ports[i])
2388 continue;
2389
2390 port = &amba_ports[i]->port;
2391
2392 if (port->mapbase != addr)
2393 continue;
2394
2395 co->index = i;
2396 port->cons = co;
2397 return pl011_console_setup(co, options);
2398 }
2399
2400 return -ENODEV;
2401}
2402
2d93486c 2403static struct uart_driver amba_reg;
1da177e4
LT		 2404static struct console amba_console = {
2405 .name = "ttyAMA",
2406 .write = pl011_console_write,
2407 .device = uart_console_device,
2408 .setup = pl011_console_setup,
10879ae5 2409 .match = pl011_console_match,
7951ffc9 2410 .flags = CON_PRINTBUFFER | CON_ANYTIME,
1da177e4
LT		 2411 .index = -1,
2412 .data = &amba_reg,
2413};
2414
2415#define AMBA_CONSOLE (&amba_console)
0d3c673e 2416
d8a4995b
CC		 2417static void qdf2400_e44_putc(struct uart_port *port, int c)
2418{
2419 while (readl(port->membase + UART01x_FR) & UART01x_FR_TXFF)
2420 cpu_relax();
2421 writel(c, port->membase + UART01x_DR);
2422 while (!(readl(port->membase + UART01x_FR) & UART011_FR_TXFE))
2423 cpu_relax();
2424}
2425
2426static void qdf2400_e44_early_write(struct console *con, const char *s, unsigned n)
2427{
2428 struct earlycon_device *dev = con->data;
2429
2430 uart_console_write(&dev->port, s, n, qdf2400_e44_putc);
2431}
2432
0d3c673e
RH		 2433static void pl011_putc(struct uart_port *port, int c)
2434{
cdf091ca 2435 while (readl(port->membase + UART01x_FR) & UART01x_FR_TXFF)
2f2fd089 2436 cpu_relax();
3b78fae7
TT		 2437 if (port->iotype == UPIO_MEM32)
2438 writel(c, port->membase + UART01x_DR);
2439 else
2440 writeb(c, port->membase + UART01x_DR);
e06690bf 2441 while (readl(port->membase + UART01x_FR) & UART01x_FR_BUSY)
2f2fd089 2442 cpu_relax();
0d3c673e
RH		 2443}
2444
2445static void pl011_early_write(struct console *con, const char *s, unsigned n)
2446{
2447 struct earlycon_device *dev = con->data;
2448
2449 uart_console_write(&dev->port, s, n, pl011_putc);
2450}
2451
e53e597f
TT		 2452/*
2453 * On non-ACPI systems, earlycon is enabled by specifying
2454 * "earlycon=pl011,<address>" on the kernel command line.
2455 *
2456 * On ACPI ARM64 systems, an "early" console is enabled via the SPCR table,
2457 * by specifying only "earlycon" on the command line. Because it requires
2458 * SPCR, the console starts after ACPI is parsed, which is later than a
2459 * traditional early console.
2460 *
2461 * To get the traditional early console that starts before ACPI is parsed,
2462 * specify the full "earlycon=pl011,<address>" option.
2463 */
0d3c673e
RH		 2464static int __init pl011_early_console_setup(struct earlycon_device *device,
2465 const char *opt)
2466{
2467 if (!device->port.membase)
2468 return -ENODEV;
2469
5a0722b8 2470 device->con->write = pl011_early_write;
e53e597f 2471
0d3c673e
RH		 2472 return 0;
2473}
45e0f0f5 2474OF_EARLYCON_DECLARE(pl011, "arm,pl011", pl011_early_console_setup);
fcb32159 2475OF_EARLYCON_DECLARE(pl011, "arm,sbsa-uart", pl011_early_console_setup);
5a0722b8
TT		 2476
2477/*
2478 * On Qualcomm Datacenter Technologies QDF2400 SOCs affected by
2479 * Erratum 44, traditional earlycon can be enabled by specifying
2480 * "earlycon=qdf2400_e44,<address>". Any options are ignored.
2481 *
2482 * Alternatively, you can just specify "earlycon", and the early console
2483 * will be enabled with the information from the SPCR table. In this
2484 * case, the SPCR code will detect the need for the E44 work-around,
2485 * and set the console name to "qdf2400_e44".
2486 */
2487static int __init
2488qdf2400_e44_early_console_setup(struct earlycon_device *device,
2489 const char *opt)
2490{
2491 if (!device->port.membase)
2492 return -ENODEV;
2493
2494 device->con->write = qdf2400_e44_early_write;
2495 return 0;
2496}
2497EARLYCON_DECLARE(qdf2400_e44, qdf2400_e44_early_console_setup);
0d3c673e 2498
1da177e4
LT		 2499#else
2500#define AMBA_CONSOLE NULL
2501#endif
2502
2503static struct uart_driver amba_reg = {
2504 .owner = THIS_MODULE,
2505 .driver_name = "ttyAMA",
2506 .dev_name = "ttyAMA",
2507 .major = SERIAL_AMBA_MAJOR,
2508 .minor = SERIAL_AMBA_MINOR,
2509 .nr = UART_NR,
2510 .cons = AMBA_CONSOLE,
2511};
2512
32614aad
ML		 2513static int pl011_probe_dt_alias(int index, struct device *dev)
2514{
2515 struct device_node *np;
2516 static bool seen_dev_with_alias = false;
2517 static bool seen_dev_without_alias = false;
2518 int ret = index;
2519
2520 if (!IS_ENABLED(CONFIG_OF))
2521 return ret;
2522
2523 np = dev->of_node;
2524 if (!np)
2525 return ret;
2526
2527 ret = of_alias_get_id(np, "serial");
287980e4 2528 if (ret < 0) {
32614aad
ML		 2529 seen_dev_without_alias = true;
2530 ret = index;
2531 } else {
2532 seen_dev_with_alias = true;
2533 if (ret >= ARRAY_SIZE(amba_ports) || amba_ports[ret] != NULL) {
2534 dev_warn(dev, "requested serial port %d not available.\n", ret);
2535 ret = index;
2536 }
2537 }
2538
2539 if (seen_dev_with_alias && seen_dev_without_alias)
2540 dev_warn(dev, "aliased and non-aliased serial devices found in device tree. Serial port enumeration may be unpredictable.\n");
2541
2542 return ret;
2543}
2544
49bb3c86
AP		 2545/* unregisters the driver also if no more ports are left */
2546static void pl011_unregister_port(struct uart_amba_port *uap)
2547{
2548 int i;
2549 bool busy = false;
2550
2551 for (i = 0; i < ARRAY_SIZE(amba_ports); i++) {
2552 if (amba_ports[i] == uap)
2553 amba_ports[i] = NULL;
2554 else if (amba_ports[i])
2555 busy = true;
2556 }
2557 pl011_dma_remove(uap);
2558 if (!busy)
2559 uart_unregister_driver(&amba_reg);
2560}
2561
3873e2d7 2562static int pl011_find_free_port(void)
1da177e4 2563{
3873e2d7 2564 int i;
1da177e4
LT		 2565
2566 for (i = 0; i < ARRAY_SIZE(amba_ports); i++)
2567 if (amba_ports[i] == NULL)
3873e2d7 2568 return i;
1da177e4 2569
3873e2d7
AP		 2570 return -EBUSY;
2571}
1da177e4 2572
3873e2d7
AP		 2573static int pl011_setup_port(struct device *dev, struct uart_amba_port *uap,
2574 struct resource *mmiobase, int index)
2575{
2576 void __iomem *base;
32614aad 2577
3873e2d7 2578 base = devm_ioremap_resource(dev, mmiobase);
97a60eac
KK		 2579 if (IS_ERR(base))
2580 return PTR_ERR(base);
1da177e4 2581
3873e2d7 2582 index = pl011_probe_dt_alias(index, dev);
1da177e4 2583
d8d8ffa4 2584 uap->old_cr = 0;
3873e2d7
AP		 2585 uap->port.dev = dev;
2586 uap->port.mapbase = mmiobase->start;
1da177e4 2587 uap->port.membase = base;
ffca2b11 2588 uap->port.fifosize = uap->fifosize;
1da177e4 2589 uap->port.flags = UPF_BOOT_AUTOCONF;
3873e2d7 2590 uap->port.line = index;
1da177e4 2591
3873e2d7 2592 amba_ports[index] = uap;
c3d8b76f 2593
3873e2d7
AP		 2594 return 0;
2595}
e8a7ba86 2596
3873e2d7
AP		 2597static int pl011_register_port(struct uart_amba_port *uap)
2598{
2599 int ret;
1da177e4 2600
3873e2d7 2601 /* Ensure interrupts from this UART are masked and cleared */
9f25bc51
RK		 2602 pl011_write(0, uap, REG_IMSC);
2603 pl011_write(0xffff, uap, REG_ICR);
ef2889f7
TB		 2604
2605 if (!amba_reg.state) {
2606 ret = uart_register_driver(&amba_reg);
2607 if (ret < 0) {
3873e2d7 2608 dev_err(uap->port.dev,
1c9be310 2609 "Failed to register AMBA-PL011 driver\n");
ef2889f7
TB		 2610 return ret;
2611 }
2612 }
2613
1da177e4 2614 ret = uart_add_one_port(&amba_reg, &uap->port);
49bb3c86
AP		 2615 if (ret)
2616 pl011_unregister_port(uap);
7f6d942a 2617
1da177e4
LT		 2618 return ret;
2619}
2620
3873e2d7
AP		 2621static int pl011_probe(struct amba_device *dev, const struct amba_id *id)
2622{
2623 struct uart_amba_port *uap;
2624 struct vendor_data *vendor = id->data;
2625 int portnr, ret;
2626
2627 portnr = pl011_find_free_port();
2628 if (portnr < 0)
2629 return portnr;
2630
2631 uap = devm_kzalloc(&dev->dev, sizeof(struct uart_amba_port),
2632 GFP_KERNEL);
2633 if (!uap)
2634 return -ENOMEM;
2635
2636 uap->clk = devm_clk_get(&dev->dev, NULL);
2637 if (IS_ERR(uap->clk))
2638 return PTR_ERR(uap->clk);
2639
439403bd 2640 uap->reg_offset = vendor->reg_offset;
3873e2d7 2641 uap->vendor = vendor;
3873e2d7 2642 uap->fifosize = vendor->get_fifosize(dev);
3b78fae7 2643 uap->port.iotype = vendor->access_32b ? UPIO_MEM32 : UPIO_MEM;
3873e2d7
AP		 2644 uap->port.irq = dev->irq[0];
2645 uap->port.ops = &amba_pl011_pops;
2646
2647 snprintf(uap->type, sizeof(uap->type), "PL011 rev%u", amba_rev(dev));
2648
2649 ret = pl011_setup_port(&dev->dev, uap, &dev->res, portnr);
2650 if (ret)
2651 return ret;
2652
2653 amba_set_drvdata(dev, uap);
2654
2655 return pl011_register_port(uap);
2656}
2657
1da177e4
LT		 2658static int pl011_remove(struct amba_device *dev)
2659{
2660 struct uart_amba_port *uap = amba_get_drvdata(dev);
1da177e4 2661
1da177e4 2662 uart_remove_one_port(&amba_reg, &uap->port);
49bb3c86 2663 pl011_unregister_port(uap);
1da177e4
LT		 2664 return 0;
2665}
2666
d0ce850d
UH		 2667#ifdef CONFIG_PM_SLEEP
2668static int pl011_suspend(struct device *dev)
b736b89f 2669{
d0ce850d 2670 struct uart_amba_port *uap = dev_get_drvdata(dev);
b736b89f
LC		 2671
2672 if (!uap)
2673 return -EINVAL;
2674
2675 return uart_suspend_port(&amba_reg, &uap->port);
2676}
2677
d0ce850d 2678static int pl011_resume(struct device *dev)
b736b89f 2679{
d0ce850d 2680 struct uart_amba_port *uap = dev_get_drvdata(dev);
b736b89f
LC		 2681
2682 if (!uap)
2683 return -EINVAL;
2684
2685 return uart_resume_port(&amba_reg, &uap->port);
2686}
2687#endif
2688
d0ce850d
UH		 2689static SIMPLE_DEV_PM_OPS(pl011_dev_pm_ops, pl011_suspend, pl011_resume);
2690
0dd1e247
AP		 2691static int sbsa_uart_probe(struct platform_device *pdev)
2692{
2693 struct uart_amba_port *uap;
2694 struct resource *r;
2695 int portnr, ret;
2696 int baudrate;
2697
2698 /*
2699 * Check the mandatory baud rate parameter in the DT node early
2700 * so that we can easily exit with the error.
2701 */
2702 if (pdev->dev.of_node) {
2703 struct device_node *np = pdev->dev.of_node;
2704
2705 ret = of_property_read_u32(np, "current-speed", &baudrate);
2706 if (ret)
2707 return ret;
2708 } else {
2709 baudrate = 115200;
2710 }
2711
2712 portnr = pl011_find_free_port();
2713 if (portnr < 0)
2714 return portnr;
2715
2716 uap = devm_kzalloc(&pdev->dev, sizeof(struct uart_amba_port),
2717 GFP_KERNEL);
2718 if (!uap)
2719 return -ENOMEM;
2720
394a9e2c
JS		 2721 ret = platform_get_irq(pdev, 0);
2722 if (ret < 0) {
35aa33cf
KW		 2723 if (ret != -EPROBE_DEFER)
2724 dev_err(&pdev->dev, "cannot obtain irq\n");
394a9e2c
JS		 2725 return ret;
2726 }
2727 uap->port.irq = ret;
2728
37ef38f3
TT		 2729#ifdef CONFIG_ACPI_SPCR_TABLE
2730 if (qdf2400_e44_present) {
2731 dev_info(&pdev->dev, "working around QDF2400 SoC erratum 44\n");
2732 uap->vendor = &vendor_qdt_qdf2400_e44;
2733 } else
2734#endif
2735 uap->vendor = &vendor_sbsa;
2736
2737 uap->reg_offset = uap->vendor->reg_offset;
0dd1e247 2738 uap->fifosize = 32;
37ef38f3 2739 uap->port.iotype = uap->vendor->access_32b ? UPIO_MEM32 : UPIO_MEM;
0dd1e247
AP		 2740 uap->port.ops = &sbsa_uart_pops;
2741 uap->fixed_baud = baudrate;
2742
2743 snprintf(uap->type, sizeof(uap->type), "SBSA");
2744
2745 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2746
2747 ret = pl011_setup_port(&pdev->dev, uap, r, portnr);
2748 if (ret)
2749 return ret;
2750
2751 platform_set_drvdata(pdev, uap);
2752
2753 return pl011_register_port(uap);
2754}
2755
2756static int sbsa_uart_remove(struct platform_device *pdev)
2757{
2758 struct uart_amba_port *uap = platform_get_drvdata(pdev);
2759
2760 uart_remove_one_port(&amba_reg, &uap->port);
2761 pl011_unregister_port(uap);
2762 return 0;
2763}
2764
2765static const struct of_device_id sbsa_uart_of_match[] = {
2766 { .compatible = "arm,sbsa-uart", },
2767 {},
2768};
2769MODULE_DEVICE_TABLE(of, sbsa_uart_of_match);
2770
3db9ab0b
GG		 2771static const struct acpi_device_id sbsa_uart_acpi_match[] = {
2772 { "ARMH0011", 0 },
2773 {},
2774};
2775MODULE_DEVICE_TABLE(acpi, sbsa_uart_acpi_match);
2776
0dd1e247
AP		 2777static struct platform_driver arm_sbsa_uart_platform_driver = {
2778 .probe = sbsa_uart_probe,
2779 .remove = sbsa_uart_remove,
2780 .driver = {
2781 .name = "sbsa-uart",
2782 .of_match_table = of_match_ptr(sbsa_uart_of_match),
3db9ab0b 2783 .acpi_match_table = ACPI_PTR(sbsa_uart_acpi_match),
0dd1e247
AP		 2784 },
2785};
2786
a704ddc2 2787static const struct amba_id pl011_ids[] = {
1da177e4
LT		 2788 {
2789 .id = 0x00041011,
2790 .mask = 0x000fffff,
5926a295
AR		 2791 .data = &vendor_arm,
2792 },
2793 {
2794 .id = 0x00380802,
2795 .mask = 0x00ffffff,
2796 .data = &vendor_st,
1da177e4 2797 },
2426fbc7
SG		 2798 {
2799 .id = AMBA_LINUX_ID(0x00, 0x1, 0xffe),
2800 .mask = 0x00ffffff,
2801 .data = &vendor_zte,
2802 },
1da177e4
LT		 2803 { 0, 0 },
2804};
2805
60f7a33b
DM		 2806MODULE_DEVICE_TABLE(amba, pl011_ids);
2807
1da177e4
LT		 2808static struct amba_driver pl011_driver = {
2809 .drv = {
2810 .name = "uart-pl011",
d0ce850d 2811 .pm = &pl011_dev_pm_ops,
1da177e4
LT		 2812 },
2813 .id_table = pl011_ids,
2814 .probe = pl011_probe,
2815 .remove = pl011_remove,
2816};
2817
2818static int __init pl011_init(void)
2819{
1da177e4
LT		 2820 printk(KERN_INFO "Serial: AMBA PL011 UART driver\n");
2821
0dd1e247
AP		 2822 if (platform_driver_register(&arm_sbsa_uart_platform_driver))
2823 pr_warn("could not register SBSA UART platform driver\n");
062a68a5 2824 return amba_driver_register(&pl011_driver);
1da177e4
LT		 2825}
2826
2827static void __exit pl011_exit(void)
2828{
0dd1e247 2829 platform_driver_unregister(&arm_sbsa_uart_platform_driver);
1da177e4 2830 amba_driver_unregister(&pl011_driver);
1da177e4
LT		 2831}
2832
4dd9e742
AR		 2833/*
2834 * While this can be a module, if builtin it's most likely the console
2835 * So let's leave module_exit but move module_init to an earlier place
2836 */
2837arch_initcall(pl011_init);
1da177e4
LT		 2838module_exit(pl011_exit);
2839
2840MODULE_AUTHOR("ARM Ltd/Deep Blue Solutions Ltd");
2841MODULE_DESCRIPTION("ARM AMBA serial port driver");
2842MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)