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1da177e4 LT |
1 | /* |
2 | * linux/drivers/char/amba.c | |
3 | * | |
4 | * Driver for AMBA serial ports | |
5 | * | |
6 | * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. | |
7 | * | |
8 | * Copyright 1999 ARM Limited | |
9 | * Copyright (C) 2000 Deep Blue Solutions Ltd. | |
68b65f73 | 10 | * Copyright (C) 2010 ST-Ericsson SA |
1da177e4 LT |
11 | * |
12 | * This program is free software; you can redistribute it and/or modify | |
13 | * it under the terms of the GNU General Public License as published by | |
14 | * the Free Software Foundation; either version 2 of the License, or | |
15 | * (at your option) any later version. | |
16 | * | |
17 | * This program is distributed in the hope that it will be useful, | |
18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | * GNU General Public License for more details. | |
21 | * | |
22 | * You should have received a copy of the GNU General Public License | |
23 | * along with this program; if not, write to the Free Software | |
24 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
25 | * | |
1da177e4 LT |
26 | * This is a generic driver for ARM AMBA-type serial ports. They |
27 | * have a lot of 16550-like features, but are not register compatible. | |
28 | * Note that although they do have CTS, DCD and DSR inputs, they do | |
29 | * not have an RI input, nor do they have DTR or RTS outputs. If | |
30 | * required, these have to be supplied via some other means (eg, GPIO) | |
31 | * and hooked into this driver. | |
32 | */ | |
1da177e4 LT |
33 | |
34 | #if defined(CONFIG_SERIAL_AMBA_PL011_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) | |
35 | #define SUPPORT_SYSRQ | |
36 | #endif | |
37 | ||
38 | #include <linux/module.h> | |
39 | #include <linux/ioport.h> | |
40 | #include <linux/init.h> | |
41 | #include <linux/console.h> | |
42 | #include <linux/sysrq.h> | |
43 | #include <linux/device.h> | |
44 | #include <linux/tty.h> | |
45 | #include <linux/tty_flip.h> | |
46 | #include <linux/serial_core.h> | |
47 | #include <linux/serial.h> | |
a62c80e5 RK |
48 | #include <linux/amba/bus.h> |
49 | #include <linux/amba/serial.h> | |
f8ce2547 | 50 | #include <linux/clk.h> |
5a0e3ad6 | 51 | #include <linux/slab.h> |
68b65f73 RK |
52 | #include <linux/dmaengine.h> |
53 | #include <linux/dma-mapping.h> | |
54 | #include <linux/scatterlist.h> | |
1da177e4 LT |
55 | |
56 | #include <asm/io.h> | |
c6b8fdad | 57 | #include <asm/sizes.h> |
1da177e4 LT |
58 | |
59 | #define UART_NR 14 | |
60 | ||
61 | #define SERIAL_AMBA_MAJOR 204 | |
62 | #define SERIAL_AMBA_MINOR 64 | |
63 | #define SERIAL_AMBA_NR UART_NR | |
64 | ||
65 | #define AMBA_ISR_PASS_LIMIT 256 | |
66 | ||
b63d4f0f RK |
67 | #define UART_DR_ERROR (UART011_DR_OE|UART011_DR_BE|UART011_DR_PE|UART011_DR_FE) |
68 | #define UART_DUMMY_DR_RX (1 << 16) | |
1da177e4 | 69 | |
5926a295 AR |
70 | /* There is by now at least one vendor with differing details, so handle it */ |
71 | struct vendor_data { | |
72 | unsigned int ifls; | |
73 | unsigned int fifosize; | |
ec489aa8 LW |
74 | unsigned int lcrh_tx; |
75 | unsigned int lcrh_rx; | |
ac3e3fb4 | 76 | bool oversampling; |
38d62436 | 77 | bool dma_threshold; |
5926a295 AR |
78 | }; |
79 | ||
80 | static struct vendor_data vendor_arm = { | |
81 | .ifls = UART011_IFLS_RX4_8|UART011_IFLS_TX4_8, | |
82 | .fifosize = 16, | |
ec489aa8 LW |
83 | .lcrh_tx = UART011_LCRH, |
84 | .lcrh_rx = UART011_LCRH, | |
ac3e3fb4 | 85 | .oversampling = false, |
38d62436 | 86 | .dma_threshold = false, |
5926a295 AR |
87 | }; |
88 | ||
89 | static struct vendor_data vendor_st = { | |
90 | .ifls = UART011_IFLS_RX_HALF|UART011_IFLS_TX_HALF, | |
91 | .fifosize = 64, | |
ec489aa8 LW |
92 | .lcrh_tx = ST_UART011_LCRH_TX, |
93 | .lcrh_rx = ST_UART011_LCRH_RX, | |
ac3e3fb4 | 94 | .oversampling = true, |
38d62436 | 95 | .dma_threshold = true, |
1da177e4 LT |
96 | }; |
97 | ||
68b65f73 | 98 | /* Deals with DMA transactions */ |
ead76f32 LW |
99 | |
100 | struct pl011_sgbuf { | |
101 | struct scatterlist sg; | |
102 | char *buf; | |
103 | }; | |
104 | ||
105 | struct pl011_dmarx_data { | |
106 | struct dma_chan *chan; | |
107 | struct completion complete; | |
108 | bool use_buf_b; | |
109 | struct pl011_sgbuf sgbuf_a; | |
110 | struct pl011_sgbuf sgbuf_b; | |
111 | dma_cookie_t cookie; | |
112 | bool running; | |
113 | }; | |
114 | ||
68b65f73 RK |
115 | struct pl011_dmatx_data { |
116 | struct dma_chan *chan; | |
117 | struct scatterlist sg; | |
118 | char *buf; | |
119 | bool queued; | |
120 | }; | |
121 | ||
c19f12b5 RK |
122 | /* |
123 | * We wrap our port structure around the generic uart_port. | |
124 | */ | |
125 | struct uart_amba_port { | |
126 | struct uart_port port; | |
127 | struct clk *clk; | |
128 | const struct vendor_data *vendor; | |
68b65f73 | 129 | unsigned int dmacr; /* dma control reg */ |
c19f12b5 RK |
130 | unsigned int im; /* interrupt mask */ |
131 | unsigned int old_status; | |
ffca2b11 | 132 | unsigned int fifosize; /* vendor-specific */ |
c19f12b5 RK |
133 | unsigned int lcrh_tx; /* vendor-specific */ |
134 | unsigned int lcrh_rx; /* vendor-specific */ | |
135 | bool autorts; | |
136 | char type[12]; | |
68b65f73 RK |
137 | #ifdef CONFIG_DMA_ENGINE |
138 | /* DMA stuff */ | |
ead76f32 LW |
139 | bool using_tx_dma; |
140 | bool using_rx_dma; | |
141 | struct pl011_dmarx_data dmarx; | |
68b65f73 RK |
142 | struct pl011_dmatx_data dmatx; |
143 | #endif | |
144 | }; | |
145 | ||
29772c4e LW |
146 | /* |
147 | * Reads up to 256 characters from the FIFO or until it's empty and | |
148 | * inserts them into the TTY layer. Returns the number of characters | |
149 | * read from the FIFO. | |
150 | */ | |
151 | static int pl011_fifo_to_tty(struct uart_amba_port *uap) | |
152 | { | |
153 | u16 status, ch; | |
154 | unsigned int flag, max_count = 256; | |
155 | int fifotaken = 0; | |
156 | ||
157 | while (max_count--) { | |
158 | status = readw(uap->port.membase + UART01x_FR); | |
159 | if (status & UART01x_FR_RXFE) | |
160 | break; | |
161 | ||
162 | /* Take chars from the FIFO and update status */ | |
163 | ch = readw(uap->port.membase + UART01x_DR) | | |
164 | UART_DUMMY_DR_RX; | |
165 | flag = TTY_NORMAL; | |
166 | uap->port.icount.rx++; | |
167 | fifotaken++; | |
168 | ||
169 | if (unlikely(ch & UART_DR_ERROR)) { | |
170 | if (ch & UART011_DR_BE) { | |
171 | ch &= ~(UART011_DR_FE | UART011_DR_PE); | |
172 | uap->port.icount.brk++; | |
173 | if (uart_handle_break(&uap->port)) | |
174 | continue; | |
175 | } else if (ch & UART011_DR_PE) | |
176 | uap->port.icount.parity++; | |
177 | else if (ch & UART011_DR_FE) | |
178 | uap->port.icount.frame++; | |
179 | if (ch & UART011_DR_OE) | |
180 | uap->port.icount.overrun++; | |
181 | ||
182 | ch &= uap->port.read_status_mask; | |
183 | ||
184 | if (ch & UART011_DR_BE) | |
185 | flag = TTY_BREAK; | |
186 | else if (ch & UART011_DR_PE) | |
187 | flag = TTY_PARITY; | |
188 | else if (ch & UART011_DR_FE) | |
189 | flag = TTY_FRAME; | |
190 | } | |
191 | ||
192 | if (uart_handle_sysrq_char(&uap->port, ch & 255)) | |
193 | continue; | |
194 | ||
195 | uart_insert_char(&uap->port, ch, UART011_DR_OE, ch, flag); | |
196 | } | |
197 | ||
198 | return fifotaken; | |
199 | } | |
200 | ||
201 | ||
68b65f73 RK |
202 | /* |
203 | * All the DMA operation mode stuff goes inside this ifdef. | |
204 | * This assumes that you have a generic DMA device interface, | |
205 | * no custom DMA interfaces are supported. | |
206 | */ | |
207 | #ifdef CONFIG_DMA_ENGINE | |
208 | ||
209 | #define PL011_DMA_BUFFER_SIZE PAGE_SIZE | |
210 | ||
ead76f32 LW |
211 | static int pl011_sgbuf_init(struct dma_chan *chan, struct pl011_sgbuf *sg, |
212 | enum dma_data_direction dir) | |
213 | { | |
214 | sg->buf = kmalloc(PL011_DMA_BUFFER_SIZE, GFP_KERNEL); | |
215 | if (!sg->buf) | |
216 | return -ENOMEM; | |
217 | ||
218 | sg_init_one(&sg->sg, sg->buf, PL011_DMA_BUFFER_SIZE); | |
219 | ||
220 | if (dma_map_sg(chan->device->dev, &sg->sg, 1, dir) != 1) { | |
221 | kfree(sg->buf); | |
222 | return -EINVAL; | |
223 | } | |
224 | return 0; | |
225 | } | |
226 | ||
227 | static void pl011_sgbuf_free(struct dma_chan *chan, struct pl011_sgbuf *sg, | |
228 | enum dma_data_direction dir) | |
229 | { | |
230 | if (sg->buf) { | |
231 | dma_unmap_sg(chan->device->dev, &sg->sg, 1, dir); | |
232 | kfree(sg->buf); | |
233 | } | |
234 | } | |
235 | ||
68b65f73 RK |
236 | static void pl011_dma_probe_initcall(struct uart_amba_port *uap) |
237 | { | |
238 | /* DMA is the sole user of the platform data right now */ | |
239 | struct amba_pl011_data *plat = uap->port.dev->platform_data; | |
240 | struct dma_slave_config tx_conf = { | |
241 | .dst_addr = uap->port.mapbase + UART01x_DR, | |
242 | .dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE, | |
243 | .direction = DMA_TO_DEVICE, | |
244 | .dst_maxburst = uap->fifosize >> 1, | |
245 | }; | |
246 | struct dma_chan *chan; | |
247 | dma_cap_mask_t mask; | |
248 | ||
249 | /* We need platform data */ | |
250 | if (!plat || !plat->dma_filter) { | |
251 | dev_info(uap->port.dev, "no DMA platform data\n"); | |
252 | return; | |
253 | } | |
254 | ||
ead76f32 | 255 | /* Try to acquire a generic DMA engine slave TX channel */ |
68b65f73 RK |
256 | dma_cap_zero(mask); |
257 | dma_cap_set(DMA_SLAVE, mask); | |
258 | ||
259 | chan = dma_request_channel(mask, plat->dma_filter, plat->dma_tx_param); | |
260 | if (!chan) { | |
261 | dev_err(uap->port.dev, "no TX DMA channel!\n"); | |
262 | return; | |
263 | } | |
264 | ||
265 | dmaengine_slave_config(chan, &tx_conf); | |
266 | uap->dmatx.chan = chan; | |
267 | ||
268 | dev_info(uap->port.dev, "DMA channel TX %s\n", | |
269 | dma_chan_name(uap->dmatx.chan)); | |
ead76f32 LW |
270 | |
271 | /* Optionally make use of an RX channel as well */ | |
272 | if (plat->dma_rx_param) { | |
273 | struct dma_slave_config rx_conf = { | |
274 | .src_addr = uap->port.mapbase + UART01x_DR, | |
275 | .src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE, | |
276 | .direction = DMA_FROM_DEVICE, | |
277 | .src_maxburst = uap->fifosize >> 1, | |
278 | }; | |
279 | ||
280 | chan = dma_request_channel(mask, plat->dma_filter, plat->dma_rx_param); | |
281 | if (!chan) { | |
282 | dev_err(uap->port.dev, "no RX DMA channel!\n"); | |
283 | return; | |
284 | } | |
285 | ||
286 | dmaengine_slave_config(chan, &rx_conf); | |
287 | uap->dmarx.chan = chan; | |
288 | ||
289 | dev_info(uap->port.dev, "DMA channel RX %s\n", | |
290 | dma_chan_name(uap->dmarx.chan)); | |
291 | } | |
68b65f73 RK |
292 | } |
293 | ||
294 | #ifndef MODULE | |
295 | /* | |
296 | * Stack up the UARTs and let the above initcall be done at device | |
297 | * initcall time, because the serial driver is called as an arch | |
298 | * initcall, and at this time the DMA subsystem is not yet registered. | |
299 | * At this point the driver will switch over to using DMA where desired. | |
300 | */ | |
301 | struct dma_uap { | |
302 | struct list_head node; | |
303 | struct uart_amba_port *uap; | |
c19f12b5 RK |
304 | }; |
305 | ||
68b65f73 RK |
306 | static LIST_HEAD(pl011_dma_uarts); |
307 | ||
308 | static int __init pl011_dma_initcall(void) | |
309 | { | |
310 | struct list_head *node, *tmp; | |
311 | ||
312 | list_for_each_safe(node, tmp, &pl011_dma_uarts) { | |
313 | struct dma_uap *dmau = list_entry(node, struct dma_uap, node); | |
314 | pl011_dma_probe_initcall(dmau->uap); | |
315 | list_del(node); | |
316 | kfree(dmau); | |
317 | } | |
318 | return 0; | |
319 | } | |
320 | ||
321 | device_initcall(pl011_dma_initcall); | |
322 | ||
323 | static void pl011_dma_probe(struct uart_amba_port *uap) | |
324 | { | |
325 | struct dma_uap *dmau = kzalloc(sizeof(struct dma_uap), GFP_KERNEL); | |
326 | if (dmau) { | |
327 | dmau->uap = uap; | |
328 | list_add_tail(&dmau->node, &pl011_dma_uarts); | |
329 | } | |
330 | } | |
331 | #else | |
332 | static void pl011_dma_probe(struct uart_amba_port *uap) | |
333 | { | |
334 | pl011_dma_probe_initcall(uap); | |
335 | } | |
336 | #endif | |
337 | ||
338 | static void pl011_dma_remove(struct uart_amba_port *uap) | |
339 | { | |
340 | /* TODO: remove the initcall if it has not yet executed */ | |
341 | if (uap->dmatx.chan) | |
342 | dma_release_channel(uap->dmatx.chan); | |
ead76f32 LW |
343 | if (uap->dmarx.chan) |
344 | dma_release_channel(uap->dmarx.chan); | |
68b65f73 RK |
345 | } |
346 | ||
68b65f73 RK |
347 | /* Forward declare this for the refill routine */ |
348 | static int pl011_dma_tx_refill(struct uart_amba_port *uap); | |
349 | ||
350 | /* | |
351 | * The current DMA TX buffer has been sent. | |
352 | * Try to queue up another DMA buffer. | |
353 | */ | |
354 | static void pl011_dma_tx_callback(void *data) | |
355 | { | |
356 | struct uart_amba_port *uap = data; | |
357 | struct pl011_dmatx_data *dmatx = &uap->dmatx; | |
358 | unsigned long flags; | |
359 | u16 dmacr; | |
360 | ||
361 | spin_lock_irqsave(&uap->port.lock, flags); | |
362 | if (uap->dmatx.queued) | |
363 | dma_unmap_sg(dmatx->chan->device->dev, &dmatx->sg, 1, | |
364 | DMA_TO_DEVICE); | |
365 | ||
366 | dmacr = uap->dmacr; | |
367 | uap->dmacr = dmacr & ~UART011_TXDMAE; | |
368 | writew(uap->dmacr, uap->port.membase + UART011_DMACR); | |
369 | ||
370 | /* | |
371 | * If TX DMA was disabled, it means that we've stopped the DMA for | |
372 | * some reason (eg, XOFF received, or we want to send an X-char.) | |
373 | * | |
374 | * Note: we need to be careful here of a potential race between DMA | |
375 | * and the rest of the driver - if the driver disables TX DMA while | |
376 | * a TX buffer completing, we must update the tx queued status to | |
377 | * get further refills (hence we check dmacr). | |
378 | */ | |
379 | if (!(dmacr & UART011_TXDMAE) || uart_tx_stopped(&uap->port) || | |
380 | uart_circ_empty(&uap->port.state->xmit)) { | |
381 | uap->dmatx.queued = false; | |
382 | spin_unlock_irqrestore(&uap->port.lock, flags); | |
383 | return; | |
384 | } | |
385 | ||
386 | if (pl011_dma_tx_refill(uap) <= 0) { | |
387 | /* | |
388 | * We didn't queue a DMA buffer for some reason, but we | |
389 | * have data pending to be sent. Re-enable the TX IRQ. | |
390 | */ | |
391 | uap->im |= UART011_TXIM; | |
392 | writew(uap->im, uap->port.membase + UART011_IMSC); | |
393 | } | |
394 | spin_unlock_irqrestore(&uap->port.lock, flags); | |
395 | } | |
396 | ||
397 | /* | |
398 | * Try to refill the TX DMA buffer. | |
399 | * Locking: called with port lock held and IRQs disabled. | |
400 | * Returns: | |
401 | * 1 if we queued up a TX DMA buffer. | |
402 | * 0 if we didn't want to handle this by DMA | |
403 | * <0 on error | |
404 | */ | |
405 | static int pl011_dma_tx_refill(struct uart_amba_port *uap) | |
406 | { | |
407 | struct pl011_dmatx_data *dmatx = &uap->dmatx; | |
408 | struct dma_chan *chan = dmatx->chan; | |
409 | struct dma_device *dma_dev = chan->device; | |
410 | struct dma_async_tx_descriptor *desc; | |
411 | struct circ_buf *xmit = &uap->port.state->xmit; | |
412 | unsigned int count; | |
413 | ||
414 | /* | |
415 | * Try to avoid the overhead involved in using DMA if the | |
416 | * transaction fits in the first half of the FIFO, by using | |
417 | * the standard interrupt handling. This ensures that we | |
418 | * issue a uart_write_wakeup() at the appropriate time. | |
419 | */ | |
420 | count = uart_circ_chars_pending(xmit); | |
421 | if (count < (uap->fifosize >> 1)) { | |
422 | uap->dmatx.queued = false; | |
423 | return 0; | |
424 | } | |
425 | ||
426 | /* | |
427 | * Bodge: don't send the last character by DMA, as this | |
428 | * will prevent XON from notifying us to restart DMA. | |
429 | */ | |
430 | count -= 1; | |
431 | ||
432 | /* Else proceed to copy the TX chars to the DMA buffer and fire DMA */ | |
433 | if (count > PL011_DMA_BUFFER_SIZE) | |
434 | count = PL011_DMA_BUFFER_SIZE; | |
435 | ||
436 | if (xmit->tail < xmit->head) | |
437 | memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], count); | |
438 | else { | |
439 | size_t first = UART_XMIT_SIZE - xmit->tail; | |
440 | size_t second = xmit->head; | |
441 | ||
442 | memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], first); | |
443 | if (second) | |
444 | memcpy(&dmatx->buf[first], &xmit->buf[0], second); | |
445 | } | |
446 | ||
447 | dmatx->sg.length = count; | |
448 | ||
449 | if (dma_map_sg(dma_dev->dev, &dmatx->sg, 1, DMA_TO_DEVICE) != 1) { | |
450 | uap->dmatx.queued = false; | |
451 | dev_dbg(uap->port.dev, "unable to map TX DMA\n"); | |
452 | return -EBUSY; | |
453 | } | |
454 | ||
455 | desc = dma_dev->device_prep_slave_sg(chan, &dmatx->sg, 1, DMA_TO_DEVICE, | |
456 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
457 | if (!desc) { | |
458 | dma_unmap_sg(dma_dev->dev, &dmatx->sg, 1, DMA_TO_DEVICE); | |
459 | uap->dmatx.queued = false; | |
460 | /* | |
461 | * If DMA cannot be used right now, we complete this | |
462 | * transaction via IRQ and let the TTY layer retry. | |
463 | */ | |
464 | dev_dbg(uap->port.dev, "TX DMA busy\n"); | |
465 | return -EBUSY; | |
466 | } | |
467 | ||
468 | /* Some data to go along to the callback */ | |
469 | desc->callback = pl011_dma_tx_callback; | |
470 | desc->callback_param = uap; | |
471 | ||
472 | /* All errors should happen at prepare time */ | |
473 | dmaengine_submit(desc); | |
474 | ||
475 | /* Fire the DMA transaction */ | |
476 | dma_dev->device_issue_pending(chan); | |
477 | ||
478 | uap->dmacr |= UART011_TXDMAE; | |
479 | writew(uap->dmacr, uap->port.membase + UART011_DMACR); | |
480 | uap->dmatx.queued = true; | |
481 | ||
482 | /* | |
483 | * Now we know that DMA will fire, so advance the ring buffer | |
484 | * with the stuff we just dispatched. | |
485 | */ | |
486 | xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1); | |
487 | uap->port.icount.tx += count; | |
488 | ||
489 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
490 | uart_write_wakeup(&uap->port); | |
491 | ||
492 | return 1; | |
493 | } | |
494 | ||
495 | /* | |
496 | * We received a transmit interrupt without a pending X-char but with | |
497 | * pending characters. | |
498 | * Locking: called with port lock held and IRQs disabled. | |
499 | * Returns: | |
500 | * false if we want to use PIO to transmit | |
501 | * true if we queued a DMA buffer | |
502 | */ | |
503 | static bool pl011_dma_tx_irq(struct uart_amba_port *uap) | |
504 | { | |
ead76f32 | 505 | if (!uap->using_tx_dma) |
68b65f73 RK |
506 | return false; |
507 | ||
508 | /* | |
509 | * If we already have a TX buffer queued, but received a | |
510 | * TX interrupt, it will be because we've just sent an X-char. | |
511 | * Ensure the TX DMA is enabled and the TX IRQ is disabled. | |
512 | */ | |
513 | if (uap->dmatx.queued) { | |
514 | uap->dmacr |= UART011_TXDMAE; | |
515 | writew(uap->dmacr, uap->port.membase + UART011_DMACR); | |
516 | uap->im &= ~UART011_TXIM; | |
517 | writew(uap->im, uap->port.membase + UART011_IMSC); | |
518 | return true; | |
519 | } | |
520 | ||
521 | /* | |
522 | * We don't have a TX buffer queued, so try to queue one. | |
25985edc | 523 | * If we successfully queued a buffer, mask the TX IRQ. |
68b65f73 RK |
524 | */ |
525 | if (pl011_dma_tx_refill(uap) > 0) { | |
526 | uap->im &= ~UART011_TXIM; | |
527 | writew(uap->im, uap->port.membase + UART011_IMSC); | |
528 | return true; | |
529 | } | |
530 | return false; | |
531 | } | |
532 | ||
533 | /* | |
534 | * Stop the DMA transmit (eg, due to received XOFF). | |
535 | * Locking: called with port lock held and IRQs disabled. | |
536 | */ | |
537 | static inline void pl011_dma_tx_stop(struct uart_amba_port *uap) | |
538 | { | |
539 | if (uap->dmatx.queued) { | |
540 | uap->dmacr &= ~UART011_TXDMAE; | |
541 | writew(uap->dmacr, uap->port.membase + UART011_DMACR); | |
542 | } | |
543 | } | |
544 | ||
545 | /* | |
546 | * Try to start a DMA transmit, or in the case of an XON/OFF | |
547 | * character queued for send, try to get that character out ASAP. | |
548 | * Locking: called with port lock held and IRQs disabled. | |
549 | * Returns: | |
550 | * false if we want the TX IRQ to be enabled | |
551 | * true if we have a buffer queued | |
552 | */ | |
553 | static inline bool pl011_dma_tx_start(struct uart_amba_port *uap) | |
554 | { | |
555 | u16 dmacr; | |
556 | ||
ead76f32 | 557 | if (!uap->using_tx_dma) |
68b65f73 RK |
558 | return false; |
559 | ||
560 | if (!uap->port.x_char) { | |
561 | /* no X-char, try to push chars out in DMA mode */ | |
562 | bool ret = true; | |
563 | ||
564 | if (!uap->dmatx.queued) { | |
565 | if (pl011_dma_tx_refill(uap) > 0) { | |
566 | uap->im &= ~UART011_TXIM; | |
567 | ret = true; | |
568 | } else { | |
569 | uap->im |= UART011_TXIM; | |
570 | ret = false; | |
571 | } | |
572 | writew(uap->im, uap->port.membase + UART011_IMSC); | |
573 | } else if (!(uap->dmacr & UART011_TXDMAE)) { | |
574 | uap->dmacr |= UART011_TXDMAE; | |
575 | writew(uap->dmacr, | |
576 | uap->port.membase + UART011_DMACR); | |
577 | } | |
578 | return ret; | |
579 | } | |
580 | ||
581 | /* | |
582 | * We have an X-char to send. Disable DMA to prevent it loading | |
583 | * the TX fifo, and then see if we can stuff it into the FIFO. | |
584 | */ | |
585 | dmacr = uap->dmacr; | |
586 | uap->dmacr &= ~UART011_TXDMAE; | |
587 | writew(uap->dmacr, uap->port.membase + UART011_DMACR); | |
588 | ||
589 | if (readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF) { | |
590 | /* | |
591 | * No space in the FIFO, so enable the transmit interrupt | |
592 | * so we know when there is space. Note that once we've | |
593 | * loaded the character, we should just re-enable DMA. | |
594 | */ | |
595 | return false; | |
596 | } | |
597 | ||
598 | writew(uap->port.x_char, uap->port.membase + UART01x_DR); | |
599 | uap->port.icount.tx++; | |
600 | uap->port.x_char = 0; | |
601 | ||
602 | /* Success - restore the DMA state */ | |
603 | uap->dmacr = dmacr; | |
604 | writew(dmacr, uap->port.membase + UART011_DMACR); | |
605 | ||
606 | return true; | |
607 | } | |
608 | ||
609 | /* | |
610 | * Flush the transmit buffer. | |
611 | * Locking: called with port lock held and IRQs disabled. | |
612 | */ | |
613 | static void pl011_dma_flush_buffer(struct uart_port *port) | |
614 | { | |
615 | struct uart_amba_port *uap = (struct uart_amba_port *)port; | |
616 | ||
ead76f32 | 617 | if (!uap->using_tx_dma) |
68b65f73 RK |
618 | return; |
619 | ||
620 | /* Avoid deadlock with the DMA engine callback */ | |
621 | spin_unlock(&uap->port.lock); | |
622 | dmaengine_terminate_all(uap->dmatx.chan); | |
623 | spin_lock(&uap->port.lock); | |
624 | if (uap->dmatx.queued) { | |
625 | dma_unmap_sg(uap->dmatx.chan->device->dev, &uap->dmatx.sg, 1, | |
626 | DMA_TO_DEVICE); | |
627 | uap->dmatx.queued = false; | |
628 | uap->dmacr &= ~UART011_TXDMAE; | |
629 | writew(uap->dmacr, uap->port.membase + UART011_DMACR); | |
630 | } | |
631 | } | |
632 | ||
ead76f32 LW |
633 | static void pl011_dma_rx_callback(void *data); |
634 | ||
635 | static int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap) | |
636 | { | |
637 | struct dma_chan *rxchan = uap->dmarx.chan; | |
638 | struct dma_device *dma_dev; | |
639 | struct pl011_dmarx_data *dmarx = &uap->dmarx; | |
640 | struct dma_async_tx_descriptor *desc; | |
641 | struct pl011_sgbuf *sgbuf; | |
642 | ||
643 | if (!rxchan) | |
644 | return -EIO; | |
645 | ||
646 | /* Start the RX DMA job */ | |
647 | sgbuf = uap->dmarx.use_buf_b ? | |
648 | &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a; | |
649 | dma_dev = rxchan->device; | |
650 | desc = rxchan->device->device_prep_slave_sg(rxchan, &sgbuf->sg, 1, | |
651 | DMA_FROM_DEVICE, | |
652 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
653 | /* | |
654 | * If the DMA engine is busy and cannot prepare a | |
655 | * channel, no big deal, the driver will fall back | |
656 | * to interrupt mode as a result of this error code. | |
657 | */ | |
658 | if (!desc) { | |
659 | uap->dmarx.running = false; | |
660 | dmaengine_terminate_all(rxchan); | |
661 | return -EBUSY; | |
662 | } | |
663 | ||
664 | /* Some data to go along to the callback */ | |
665 | desc->callback = pl011_dma_rx_callback; | |
666 | desc->callback_param = uap; | |
667 | dmarx->cookie = dmaengine_submit(desc); | |
668 | dma_async_issue_pending(rxchan); | |
669 | ||
670 | uap->dmacr |= UART011_RXDMAE; | |
671 | writew(uap->dmacr, uap->port.membase + UART011_DMACR); | |
672 | uap->dmarx.running = true; | |
673 | ||
674 | uap->im &= ~UART011_RXIM; | |
675 | writew(uap->im, uap->port.membase + UART011_IMSC); | |
676 | ||
677 | return 0; | |
678 | } | |
679 | ||
680 | /* | |
681 | * This is called when either the DMA job is complete, or | |
682 | * the FIFO timeout interrupt occurred. This must be called | |
683 | * with the port spinlock uap->port.lock held. | |
684 | */ | |
685 | static void pl011_dma_rx_chars(struct uart_amba_port *uap, | |
686 | u32 pending, bool use_buf_b, | |
687 | bool readfifo) | |
688 | { | |
689 | struct tty_struct *tty = uap->port.state->port.tty; | |
690 | struct pl011_sgbuf *sgbuf = use_buf_b ? | |
691 | &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a; | |
692 | struct device *dev = uap->dmarx.chan->device->dev; | |
ead76f32 LW |
693 | int dma_count = 0; |
694 | u32 fifotaken = 0; /* only used for vdbg() */ | |
695 | ||
696 | /* Pick everything from the DMA first */ | |
697 | if (pending) { | |
698 | /* Sync in buffer */ | |
699 | dma_sync_sg_for_cpu(dev, &sgbuf->sg, 1, DMA_FROM_DEVICE); | |
700 | ||
701 | /* | |
702 | * First take all chars in the DMA pipe, then look in the FIFO. | |
703 | * Note that tty_insert_flip_buf() tries to take as many chars | |
704 | * as it can. | |
705 | */ | |
706 | dma_count = tty_insert_flip_string(uap->port.state->port.tty, | |
707 | sgbuf->buf, pending); | |
708 | ||
709 | /* Return buffer to device */ | |
710 | dma_sync_sg_for_device(dev, &sgbuf->sg, 1, DMA_FROM_DEVICE); | |
711 | ||
712 | uap->port.icount.rx += dma_count; | |
713 | if (dma_count < pending) | |
714 | dev_warn(uap->port.dev, | |
715 | "couldn't insert all characters (TTY is full?)\n"); | |
716 | } | |
717 | ||
718 | /* | |
719 | * Only continue with trying to read the FIFO if all DMA chars have | |
720 | * been taken first. | |
721 | */ | |
722 | if (dma_count == pending && readfifo) { | |
723 | /* Clear any error flags */ | |
724 | writew(UART011_OEIS | UART011_BEIS | UART011_PEIS | UART011_FEIS, | |
725 | uap->port.membase + UART011_ICR); | |
726 | ||
727 | /* | |
728 | * If we read all the DMA'd characters, and we had an | |
29772c4e LW |
729 | * incomplete buffer, that could be due to an rx error, or |
730 | * maybe we just timed out. Read any pending chars and check | |
731 | * the error status. | |
732 | * | |
733 | * Error conditions will only occur in the FIFO, these will | |
734 | * trigger an immediate interrupt and stop the DMA job, so we | |
735 | * will always find the error in the FIFO, never in the DMA | |
736 | * buffer. | |
ead76f32 | 737 | */ |
29772c4e | 738 | fifotaken = pl011_fifo_to_tty(uap); |
ead76f32 LW |
739 | } |
740 | ||
741 | spin_unlock(&uap->port.lock); | |
742 | dev_vdbg(uap->port.dev, | |
743 | "Took %d chars from DMA buffer and %d chars from the FIFO\n", | |
744 | dma_count, fifotaken); | |
745 | tty_flip_buffer_push(tty); | |
746 | spin_lock(&uap->port.lock); | |
747 | } | |
748 | ||
749 | static void pl011_dma_rx_irq(struct uart_amba_port *uap) | |
750 | { | |
751 | struct pl011_dmarx_data *dmarx = &uap->dmarx; | |
752 | struct dma_chan *rxchan = dmarx->chan; | |
753 | struct pl011_sgbuf *sgbuf = dmarx->use_buf_b ? | |
754 | &dmarx->sgbuf_b : &dmarx->sgbuf_a; | |
755 | size_t pending; | |
756 | struct dma_tx_state state; | |
757 | enum dma_status dmastat; | |
758 | ||
759 | /* | |
760 | * Pause the transfer so we can trust the current counter, | |
761 | * do this before we pause the PL011 block, else we may | |
762 | * overflow the FIFO. | |
763 | */ | |
764 | if (dmaengine_pause(rxchan)) | |
765 | dev_err(uap->port.dev, "unable to pause DMA transfer\n"); | |
766 | dmastat = rxchan->device->device_tx_status(rxchan, | |
767 | dmarx->cookie, &state); | |
768 | if (dmastat != DMA_PAUSED) | |
769 | dev_err(uap->port.dev, "unable to pause DMA transfer\n"); | |
770 | ||
771 | /* Disable RX DMA - incoming data will wait in the FIFO */ | |
772 | uap->dmacr &= ~UART011_RXDMAE; | |
773 | writew(uap->dmacr, uap->port.membase + UART011_DMACR); | |
774 | uap->dmarx.running = false; | |
775 | ||
776 | pending = sgbuf->sg.length - state.residue; | |
777 | BUG_ON(pending > PL011_DMA_BUFFER_SIZE); | |
778 | /* Then we terminate the transfer - we now know our residue */ | |
779 | dmaengine_terminate_all(rxchan); | |
780 | ||
781 | /* | |
782 | * This will take the chars we have so far and insert | |
783 | * into the framework. | |
784 | */ | |
785 | pl011_dma_rx_chars(uap, pending, dmarx->use_buf_b, true); | |
786 | ||
787 | /* Switch buffer & re-trigger DMA job */ | |
788 | dmarx->use_buf_b = !dmarx->use_buf_b; | |
789 | if (pl011_dma_rx_trigger_dma(uap)) { | |
790 | dev_dbg(uap->port.dev, "could not retrigger RX DMA job " | |
791 | "fall back to interrupt mode\n"); | |
792 | uap->im |= UART011_RXIM; | |
793 | writew(uap->im, uap->port.membase + UART011_IMSC); | |
794 | } | |
795 | } | |
796 | ||
797 | static void pl011_dma_rx_callback(void *data) | |
798 | { | |
799 | struct uart_amba_port *uap = data; | |
800 | struct pl011_dmarx_data *dmarx = &uap->dmarx; | |
801 | bool lastbuf = dmarx->use_buf_b; | |
802 | int ret; | |
803 | ||
804 | /* | |
805 | * This completion interrupt occurs typically when the | |
806 | * RX buffer is totally stuffed but no timeout has yet | |
807 | * occurred. When that happens, we just want the RX | |
808 | * routine to flush out the secondary DMA buffer while | |
809 | * we immediately trigger the next DMA job. | |
810 | */ | |
811 | spin_lock_irq(&uap->port.lock); | |
812 | uap->dmarx.running = false; | |
813 | dmarx->use_buf_b = !lastbuf; | |
814 | ret = pl011_dma_rx_trigger_dma(uap); | |
815 | ||
816 | pl011_dma_rx_chars(uap, PL011_DMA_BUFFER_SIZE, lastbuf, false); | |
817 | spin_unlock_irq(&uap->port.lock); | |
818 | /* | |
819 | * Do this check after we picked the DMA chars so we don't | |
820 | * get some IRQ immediately from RX. | |
821 | */ | |
822 | if (ret) { | |
823 | dev_dbg(uap->port.dev, "could not retrigger RX DMA job " | |
824 | "fall back to interrupt mode\n"); | |
825 | uap->im |= UART011_RXIM; | |
826 | writew(uap->im, uap->port.membase + UART011_IMSC); | |
827 | } | |
828 | } | |
829 | ||
830 | /* | |
831 | * Stop accepting received characters, when we're shutting down or | |
832 | * suspending this port. | |
833 | * Locking: called with port lock held and IRQs disabled. | |
834 | */ | |
835 | static inline void pl011_dma_rx_stop(struct uart_amba_port *uap) | |
836 | { | |
837 | /* FIXME. Just disable the DMA enable */ | |
838 | uap->dmacr &= ~UART011_RXDMAE; | |
839 | writew(uap->dmacr, uap->port.membase + UART011_DMACR); | |
840 | } | |
68b65f73 RK |
841 | |
842 | static void pl011_dma_startup(struct uart_amba_port *uap) | |
843 | { | |
ead76f32 LW |
844 | int ret; |
845 | ||
68b65f73 RK |
846 | if (!uap->dmatx.chan) |
847 | return; | |
848 | ||
849 | uap->dmatx.buf = kmalloc(PL011_DMA_BUFFER_SIZE, GFP_KERNEL); | |
850 | if (!uap->dmatx.buf) { | |
851 | dev_err(uap->port.dev, "no memory for DMA TX buffer\n"); | |
852 | uap->port.fifosize = uap->fifosize; | |
853 | return; | |
854 | } | |
855 | ||
856 | sg_init_one(&uap->dmatx.sg, uap->dmatx.buf, PL011_DMA_BUFFER_SIZE); | |
857 | ||
858 | /* The DMA buffer is now the FIFO the TTY subsystem can use */ | |
859 | uap->port.fifosize = PL011_DMA_BUFFER_SIZE; | |
ead76f32 LW |
860 | uap->using_tx_dma = true; |
861 | ||
862 | if (!uap->dmarx.chan) | |
863 | goto skip_rx; | |
864 | ||
865 | /* Allocate and map DMA RX buffers */ | |
866 | ret = pl011_sgbuf_init(uap->dmarx.chan, &uap->dmarx.sgbuf_a, | |
867 | DMA_FROM_DEVICE); | |
868 | if (ret) { | |
869 | dev_err(uap->port.dev, "failed to init DMA %s: %d\n", | |
870 | "RX buffer A", ret); | |
871 | goto skip_rx; | |
872 | } | |
68b65f73 | 873 | |
ead76f32 LW |
874 | ret = pl011_sgbuf_init(uap->dmarx.chan, &uap->dmarx.sgbuf_b, |
875 | DMA_FROM_DEVICE); | |
876 | if (ret) { | |
877 | dev_err(uap->port.dev, "failed to init DMA %s: %d\n", | |
878 | "RX buffer B", ret); | |
879 | pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_a, | |
880 | DMA_FROM_DEVICE); | |
881 | goto skip_rx; | |
882 | } | |
883 | ||
884 | uap->using_rx_dma = true; | |
68b65f73 | 885 | |
ead76f32 | 886 | skip_rx: |
68b65f73 RK |
887 | /* Turn on DMA error (RX/TX will be enabled on demand) */ |
888 | uap->dmacr |= UART011_DMAONERR; | |
889 | writew(uap->dmacr, uap->port.membase + UART011_DMACR); | |
38d62436 RK |
890 | |
891 | /* | |
892 | * ST Micro variants has some specific dma burst threshold | |
893 | * compensation. Set this to 16 bytes, so burst will only | |
894 | * be issued above/below 16 bytes. | |
895 | */ | |
896 | if (uap->vendor->dma_threshold) | |
897 | writew(ST_UART011_DMAWM_RX_16 | ST_UART011_DMAWM_TX_16, | |
898 | uap->port.membase + ST_UART011_DMAWM); | |
ead76f32 LW |
899 | |
900 | if (uap->using_rx_dma) { | |
901 | if (pl011_dma_rx_trigger_dma(uap)) | |
902 | dev_dbg(uap->port.dev, "could not trigger initial " | |
903 | "RX DMA job, fall back to interrupt mode\n"); | |
904 | } | |
68b65f73 RK |
905 | } |
906 | ||
907 | static void pl011_dma_shutdown(struct uart_amba_port *uap) | |
908 | { | |
ead76f32 | 909 | if (!(uap->using_tx_dma || uap->using_rx_dma)) |
68b65f73 RK |
910 | return; |
911 | ||
912 | /* Disable RX and TX DMA */ | |
913 | while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_BUSY) | |
914 | barrier(); | |
915 | ||
916 | spin_lock_irq(&uap->port.lock); | |
917 | uap->dmacr &= ~(UART011_DMAONERR | UART011_RXDMAE | UART011_TXDMAE); | |
918 | writew(uap->dmacr, uap->port.membase + UART011_DMACR); | |
919 | spin_unlock_irq(&uap->port.lock); | |
920 | ||
ead76f32 LW |
921 | if (uap->using_tx_dma) { |
922 | /* In theory, this should already be done by pl011_dma_flush_buffer */ | |
923 | dmaengine_terminate_all(uap->dmatx.chan); | |
924 | if (uap->dmatx.queued) { | |
925 | dma_unmap_sg(uap->dmatx.chan->device->dev, &uap->dmatx.sg, 1, | |
926 | DMA_TO_DEVICE); | |
927 | uap->dmatx.queued = false; | |
928 | } | |
929 | ||
930 | kfree(uap->dmatx.buf); | |
931 | uap->using_tx_dma = false; | |
68b65f73 RK |
932 | } |
933 | ||
ead76f32 LW |
934 | if (uap->using_rx_dma) { |
935 | dmaengine_terminate_all(uap->dmarx.chan); | |
936 | /* Clean up the RX DMA */ | |
937 | pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_a, DMA_FROM_DEVICE); | |
938 | pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_b, DMA_FROM_DEVICE); | |
939 | uap->using_rx_dma = false; | |
940 | } | |
941 | } | |
68b65f73 | 942 | |
ead76f32 LW |
943 | static inline bool pl011_dma_rx_available(struct uart_amba_port *uap) |
944 | { | |
945 | return uap->using_rx_dma; | |
68b65f73 RK |
946 | } |
947 | ||
ead76f32 LW |
948 | static inline bool pl011_dma_rx_running(struct uart_amba_port *uap) |
949 | { | |
950 | return uap->using_rx_dma && uap->dmarx.running; | |
951 | } | |
952 | ||
953 | ||
68b65f73 RK |
954 | #else |
955 | /* Blank functions if the DMA engine is not available */ | |
956 | static inline void pl011_dma_probe(struct uart_amba_port *uap) | |
957 | { | |
958 | } | |
959 | ||
960 | static inline void pl011_dma_remove(struct uart_amba_port *uap) | |
961 | { | |
962 | } | |
963 | ||
964 | static inline void pl011_dma_startup(struct uart_amba_port *uap) | |
965 | { | |
966 | } | |
967 | ||
968 | static inline void pl011_dma_shutdown(struct uart_amba_port *uap) | |
969 | { | |
970 | } | |
971 | ||
972 | static inline bool pl011_dma_tx_irq(struct uart_amba_port *uap) | |
973 | { | |
974 | return false; | |
975 | } | |
976 | ||
977 | static inline void pl011_dma_tx_stop(struct uart_amba_port *uap) | |
978 | { | |
979 | } | |
980 | ||
981 | static inline bool pl011_dma_tx_start(struct uart_amba_port *uap) | |
982 | { | |
983 | return false; | |
984 | } | |
985 | ||
ead76f32 LW |
986 | static inline void pl011_dma_rx_irq(struct uart_amba_port *uap) |
987 | { | |
988 | } | |
989 | ||
990 | static inline void pl011_dma_rx_stop(struct uart_amba_port *uap) | |
991 | { | |
992 | } | |
993 | ||
994 | static inline int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap) | |
995 | { | |
996 | return -EIO; | |
997 | } | |
998 | ||
999 | static inline bool pl011_dma_rx_available(struct uart_amba_port *uap) | |
1000 | { | |
1001 | return false; | |
1002 | } | |
1003 | ||
1004 | static inline bool pl011_dma_rx_running(struct uart_amba_port *uap) | |
1005 | { | |
1006 | return false; | |
1007 | } | |
1008 | ||
68b65f73 RK |
1009 | #define pl011_dma_flush_buffer NULL |
1010 | #endif | |
1011 | ||
1012 | ||
b129a8cc | 1013 | static void pl011_stop_tx(struct uart_port *port) |
1da177e4 LT |
1014 | { |
1015 | struct uart_amba_port *uap = (struct uart_amba_port *)port; | |
1016 | ||
1017 | uap->im &= ~UART011_TXIM; | |
1018 | writew(uap->im, uap->port.membase + UART011_IMSC); | |
68b65f73 | 1019 | pl011_dma_tx_stop(uap); |
1da177e4 LT |
1020 | } |
1021 | ||
b129a8cc | 1022 | static void pl011_start_tx(struct uart_port *port) |
1da177e4 LT |
1023 | { |
1024 | struct uart_amba_port *uap = (struct uart_amba_port *)port; | |
1025 | ||
68b65f73 RK |
1026 | if (!pl011_dma_tx_start(uap)) { |
1027 | uap->im |= UART011_TXIM; | |
1028 | writew(uap->im, uap->port.membase + UART011_IMSC); | |
1029 | } | |
1da177e4 LT |
1030 | } |
1031 | ||
1032 | static void pl011_stop_rx(struct uart_port *port) | |
1033 | { | |
1034 | struct uart_amba_port *uap = (struct uart_amba_port *)port; | |
1035 | ||
1036 | uap->im &= ~(UART011_RXIM|UART011_RTIM|UART011_FEIM| | |
1037 | UART011_PEIM|UART011_BEIM|UART011_OEIM); | |
1038 | writew(uap->im, uap->port.membase + UART011_IMSC); | |
ead76f32 LW |
1039 | |
1040 | pl011_dma_rx_stop(uap); | |
1da177e4 LT |
1041 | } |
1042 | ||
1043 | static void pl011_enable_ms(struct uart_port *port) | |
1044 | { | |
1045 | struct uart_amba_port *uap = (struct uart_amba_port *)port; | |
1046 | ||
1047 | uap->im |= UART011_RIMIM|UART011_CTSMIM|UART011_DCDMIM|UART011_DSRMIM; | |
1048 | writew(uap->im, uap->port.membase + UART011_IMSC); | |
1049 | } | |
1050 | ||
7d12e780 | 1051 | static void pl011_rx_chars(struct uart_amba_port *uap) |
1da177e4 | 1052 | { |
ebd2c8f6 | 1053 | struct tty_struct *tty = uap->port.state->port.tty; |
1da177e4 | 1054 | |
29772c4e | 1055 | pl011_fifo_to_tty(uap); |
1da177e4 | 1056 | |
2389b272 | 1057 | spin_unlock(&uap->port.lock); |
1da177e4 | 1058 | tty_flip_buffer_push(tty); |
ead76f32 LW |
1059 | /* |
1060 | * If we were temporarily out of DMA mode for a while, | |
1061 | * attempt to switch back to DMA mode again. | |
1062 | */ | |
1063 | if (pl011_dma_rx_available(uap)) { | |
1064 | if (pl011_dma_rx_trigger_dma(uap)) { | |
1065 | dev_dbg(uap->port.dev, "could not trigger RX DMA job " | |
1066 | "fall back to interrupt mode again\n"); | |
1067 | uap->im |= UART011_RXIM; | |
1068 | } else | |
1069 | uap->im &= ~UART011_RXIM; | |
1070 | writew(uap->im, uap->port.membase + UART011_IMSC); | |
1071 | } | |
2389b272 | 1072 | spin_lock(&uap->port.lock); |
1da177e4 LT |
1073 | } |
1074 | ||
1075 | static void pl011_tx_chars(struct uart_amba_port *uap) | |
1076 | { | |
ebd2c8f6 | 1077 | struct circ_buf *xmit = &uap->port.state->xmit; |
1da177e4 LT |
1078 | int count; |
1079 | ||
1080 | if (uap->port.x_char) { | |
1081 | writew(uap->port.x_char, uap->port.membase + UART01x_DR); | |
1082 | uap->port.icount.tx++; | |
1083 | uap->port.x_char = 0; | |
1084 | return; | |
1085 | } | |
1086 | if (uart_circ_empty(xmit) || uart_tx_stopped(&uap->port)) { | |
b129a8cc | 1087 | pl011_stop_tx(&uap->port); |
1da177e4 LT |
1088 | return; |
1089 | } | |
1090 | ||
68b65f73 RK |
1091 | /* If we are using DMA mode, try to send some characters. */ |
1092 | if (pl011_dma_tx_irq(uap)) | |
1093 | return; | |
1094 | ||
ffca2b11 | 1095 | count = uap->fifosize >> 1; |
1da177e4 LT |
1096 | do { |
1097 | writew(xmit->buf[xmit->tail], uap->port.membase + UART01x_DR); | |
1098 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); | |
1099 | uap->port.icount.tx++; | |
1100 | if (uart_circ_empty(xmit)) | |
1101 | break; | |
1102 | } while (--count > 0); | |
1103 | ||
1104 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
1105 | uart_write_wakeup(&uap->port); | |
1106 | ||
1107 | if (uart_circ_empty(xmit)) | |
b129a8cc | 1108 | pl011_stop_tx(&uap->port); |
1da177e4 LT |
1109 | } |
1110 | ||
1111 | static void pl011_modem_status(struct uart_amba_port *uap) | |
1112 | { | |
1113 | unsigned int status, delta; | |
1114 | ||
1115 | status = readw(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY; | |
1116 | ||
1117 | delta = status ^ uap->old_status; | |
1118 | uap->old_status = status; | |
1119 | ||
1120 | if (!delta) | |
1121 | return; | |
1122 | ||
1123 | if (delta & UART01x_FR_DCD) | |
1124 | uart_handle_dcd_change(&uap->port, status & UART01x_FR_DCD); | |
1125 | ||
1126 | if (delta & UART01x_FR_DSR) | |
1127 | uap->port.icount.dsr++; | |
1128 | ||
1129 | if (delta & UART01x_FR_CTS) | |
1130 | uart_handle_cts_change(&uap->port, status & UART01x_FR_CTS); | |
1131 | ||
bdc04e31 | 1132 | wake_up_interruptible(&uap->port.state->port.delta_msr_wait); |
1da177e4 LT |
1133 | } |
1134 | ||
7d12e780 | 1135 | static irqreturn_t pl011_int(int irq, void *dev_id) |
1da177e4 LT |
1136 | { |
1137 | struct uart_amba_port *uap = dev_id; | |
963cc981 | 1138 | unsigned long flags; |
1da177e4 LT |
1139 | unsigned int status, pass_counter = AMBA_ISR_PASS_LIMIT; |
1140 | int handled = 0; | |
1141 | ||
963cc981 | 1142 | spin_lock_irqsave(&uap->port.lock, flags); |
1da177e4 LT |
1143 | |
1144 | status = readw(uap->port.membase + UART011_MIS); | |
1145 | if (status) { | |
1146 | do { | |
1147 | writew(status & ~(UART011_TXIS|UART011_RTIS| | |
1148 | UART011_RXIS), | |
1149 | uap->port.membase + UART011_ICR); | |
1150 | ||
ead76f32 LW |
1151 | if (status & (UART011_RTIS|UART011_RXIS)) { |
1152 | if (pl011_dma_rx_running(uap)) | |
1153 | pl011_dma_rx_irq(uap); | |
1154 | else | |
1155 | pl011_rx_chars(uap); | |
1156 | } | |
1da177e4 LT |
1157 | if (status & (UART011_DSRMIS|UART011_DCDMIS| |
1158 | UART011_CTSMIS|UART011_RIMIS)) | |
1159 | pl011_modem_status(uap); | |
1160 | if (status & UART011_TXIS) | |
1161 | pl011_tx_chars(uap); | |
1162 | ||
1163 | if (pass_counter-- == 0) | |
1164 | break; | |
1165 | ||
1166 | status = readw(uap->port.membase + UART011_MIS); | |
1167 | } while (status != 0); | |
1168 | handled = 1; | |
1169 | } | |
1170 | ||
963cc981 | 1171 | spin_unlock_irqrestore(&uap->port.lock, flags); |
1da177e4 LT |
1172 | |
1173 | return IRQ_RETVAL(handled); | |
1174 | } | |
1175 | ||
1176 | static unsigned int pl01x_tx_empty(struct uart_port *port) | |
1177 | { | |
1178 | struct uart_amba_port *uap = (struct uart_amba_port *)port; | |
1179 | unsigned int status = readw(uap->port.membase + UART01x_FR); | |
1180 | return status & (UART01x_FR_BUSY|UART01x_FR_TXFF) ? 0 : TIOCSER_TEMT; | |
1181 | } | |
1182 | ||
1183 | static unsigned int pl01x_get_mctrl(struct uart_port *port) | |
1184 | { | |
1185 | struct uart_amba_port *uap = (struct uart_amba_port *)port; | |
1186 | unsigned int result = 0; | |
1187 | unsigned int status = readw(uap->port.membase + UART01x_FR); | |
1188 | ||
5159f407 | 1189 | #define TIOCMBIT(uartbit, tiocmbit) \ |
1da177e4 LT |
1190 | if (status & uartbit) \ |
1191 | result |= tiocmbit | |
1192 | ||
5159f407 JS |
1193 | TIOCMBIT(UART01x_FR_DCD, TIOCM_CAR); |
1194 | TIOCMBIT(UART01x_FR_DSR, TIOCM_DSR); | |
1195 | TIOCMBIT(UART01x_FR_CTS, TIOCM_CTS); | |
1196 | TIOCMBIT(UART011_FR_RI, TIOCM_RNG); | |
1197 | #undef TIOCMBIT | |
1da177e4 LT |
1198 | return result; |
1199 | } | |
1200 | ||
1201 | static void pl011_set_mctrl(struct uart_port *port, unsigned int mctrl) | |
1202 | { | |
1203 | struct uart_amba_port *uap = (struct uart_amba_port *)port; | |
1204 | unsigned int cr; | |
1205 | ||
1206 | cr = readw(uap->port.membase + UART011_CR); | |
1207 | ||
5159f407 | 1208 | #define TIOCMBIT(tiocmbit, uartbit) \ |
1da177e4 LT |
1209 | if (mctrl & tiocmbit) \ |
1210 | cr |= uartbit; \ | |
1211 | else \ | |
1212 | cr &= ~uartbit | |
1213 | ||
5159f407 JS |
1214 | TIOCMBIT(TIOCM_RTS, UART011_CR_RTS); |
1215 | TIOCMBIT(TIOCM_DTR, UART011_CR_DTR); | |
1216 | TIOCMBIT(TIOCM_OUT1, UART011_CR_OUT1); | |
1217 | TIOCMBIT(TIOCM_OUT2, UART011_CR_OUT2); | |
1218 | TIOCMBIT(TIOCM_LOOP, UART011_CR_LBE); | |
3b43816f RV |
1219 | |
1220 | if (uap->autorts) { | |
1221 | /* We need to disable auto-RTS if we want to turn RTS off */ | |
1222 | TIOCMBIT(TIOCM_RTS, UART011_CR_RTSEN); | |
1223 | } | |
5159f407 | 1224 | #undef TIOCMBIT |
1da177e4 LT |
1225 | |
1226 | writew(cr, uap->port.membase + UART011_CR); | |
1227 | } | |
1228 | ||
1229 | static void pl011_break_ctl(struct uart_port *port, int break_state) | |
1230 | { | |
1231 | struct uart_amba_port *uap = (struct uart_amba_port *)port; | |
1232 | unsigned long flags; | |
1233 | unsigned int lcr_h; | |
1234 | ||
1235 | spin_lock_irqsave(&uap->port.lock, flags); | |
ec489aa8 | 1236 | lcr_h = readw(uap->port.membase + uap->lcrh_tx); |
1da177e4 LT |
1237 | if (break_state == -1) |
1238 | lcr_h |= UART01x_LCRH_BRK; | |
1239 | else | |
1240 | lcr_h &= ~UART01x_LCRH_BRK; | |
ec489aa8 | 1241 | writew(lcr_h, uap->port.membase + uap->lcrh_tx); |
1da177e4 LT |
1242 | spin_unlock_irqrestore(&uap->port.lock, flags); |
1243 | } | |
1244 | ||
84b5ae15 JW |
1245 | #ifdef CONFIG_CONSOLE_POLL |
1246 | static int pl010_get_poll_char(struct uart_port *port) | |
1247 | { | |
1248 | struct uart_amba_port *uap = (struct uart_amba_port *)port; | |
1249 | unsigned int status; | |
1250 | ||
f5316b4a JW |
1251 | status = readw(uap->port.membase + UART01x_FR); |
1252 | if (status & UART01x_FR_RXFE) | |
1253 | return NO_POLL_CHAR; | |
84b5ae15 JW |
1254 | |
1255 | return readw(uap->port.membase + UART01x_DR); | |
1256 | } | |
1257 | ||
1258 | static void pl010_put_poll_char(struct uart_port *port, | |
1259 | unsigned char ch) | |
1260 | { | |
1261 | struct uart_amba_port *uap = (struct uart_amba_port *)port; | |
1262 | ||
1263 | while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF) | |
1264 | barrier(); | |
1265 | ||
1266 | writew(ch, uap->port.membase + UART01x_DR); | |
1267 | } | |
1268 | ||
1269 | #endif /* CONFIG_CONSOLE_POLL */ | |
1270 | ||
1da177e4 LT |
1271 | static int pl011_startup(struct uart_port *port) |
1272 | { | |
1273 | struct uart_amba_port *uap = (struct uart_amba_port *)port; | |
1274 | unsigned int cr; | |
1275 | int retval; | |
1276 | ||
1277 | /* | |
1278 | * Try to enable the clock producer. | |
1279 | */ | |
1280 | retval = clk_enable(uap->clk); | |
1281 | if (retval) | |
1282 | goto out; | |
1283 | ||
1284 | uap->port.uartclk = clk_get_rate(uap->clk); | |
1285 | ||
1286 | /* | |
1287 | * Allocate the IRQ | |
1288 | */ | |
1289 | retval = request_irq(uap->port.irq, pl011_int, 0, "uart-pl011", uap); | |
1290 | if (retval) | |
1291 | goto clk_dis; | |
1292 | ||
c19f12b5 | 1293 | writew(uap->vendor->ifls, uap->port.membase + UART011_IFLS); |
1da177e4 LT |
1294 | |
1295 | /* | |
1296 | * Provoke TX FIFO interrupt into asserting. | |
1297 | */ | |
1298 | cr = UART01x_CR_UARTEN | UART011_CR_TXE | UART011_CR_LBE; | |
1299 | writew(cr, uap->port.membase + UART011_CR); | |
1300 | writew(0, uap->port.membase + UART011_FBRD); | |
1301 | writew(1, uap->port.membase + UART011_IBRD); | |
ec489aa8 LW |
1302 | writew(0, uap->port.membase + uap->lcrh_rx); |
1303 | if (uap->lcrh_tx != uap->lcrh_rx) { | |
1304 | int i; | |
1305 | /* | |
1306 | * Wait 10 PCLKs before writing LCRH_TX register, | |
1307 | * to get this delay write read only register 10 times | |
1308 | */ | |
1309 | for (i = 0; i < 10; ++i) | |
1310 | writew(0xff, uap->port.membase + UART011_MIS); | |
1311 | writew(0, uap->port.membase + uap->lcrh_tx); | |
1312 | } | |
1da177e4 LT |
1313 | writew(0, uap->port.membase + UART01x_DR); |
1314 | while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_BUSY) | |
1315 | barrier(); | |
1316 | ||
1317 | cr = UART01x_CR_UARTEN | UART011_CR_RXE | UART011_CR_TXE; | |
1318 | writew(cr, uap->port.membase + UART011_CR); | |
1319 | ||
5063e2c5 RK |
1320 | /* Clear pending error interrupts */ |
1321 | writew(UART011_OEIS | UART011_BEIS | UART011_PEIS | UART011_FEIS, | |
1322 | uap->port.membase + UART011_ICR); | |
1323 | ||
1da177e4 LT |
1324 | /* |
1325 | * initialise the old status of the modem signals | |
1326 | */ | |
1327 | uap->old_status = readw(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY; | |
1328 | ||
68b65f73 RK |
1329 | /* Startup DMA */ |
1330 | pl011_dma_startup(uap); | |
1331 | ||
1da177e4 | 1332 | /* |
ead76f32 LW |
1333 | * Finally, enable interrupts, only timeouts when using DMA |
1334 | * if initial RX DMA job failed, start in interrupt mode | |
1335 | * as well. | |
1da177e4 LT |
1336 | */ |
1337 | spin_lock_irq(&uap->port.lock); | |
ead76f32 LW |
1338 | uap->im = UART011_RTIM; |
1339 | if (!pl011_dma_rx_running(uap)) | |
1340 | uap->im |= UART011_RXIM; | |
1da177e4 LT |
1341 | writew(uap->im, uap->port.membase + UART011_IMSC); |
1342 | spin_unlock_irq(&uap->port.lock); | |
1343 | ||
1344 | return 0; | |
1345 | ||
1346 | clk_dis: | |
1347 | clk_disable(uap->clk); | |
1348 | out: | |
1349 | return retval; | |
1350 | } | |
1351 | ||
ec489aa8 LW |
1352 | static void pl011_shutdown_channel(struct uart_amba_port *uap, |
1353 | unsigned int lcrh) | |
1354 | { | |
1355 | unsigned long val; | |
1356 | ||
1357 | val = readw(uap->port.membase + lcrh); | |
1358 | val &= ~(UART01x_LCRH_BRK | UART01x_LCRH_FEN); | |
1359 | writew(val, uap->port.membase + lcrh); | |
1360 | } | |
1361 | ||
1da177e4 LT |
1362 | static void pl011_shutdown(struct uart_port *port) |
1363 | { | |
1364 | struct uart_amba_port *uap = (struct uart_amba_port *)port; | |
1da177e4 LT |
1365 | |
1366 | /* | |
1367 | * disable all interrupts | |
1368 | */ | |
1369 | spin_lock_irq(&uap->port.lock); | |
1370 | uap->im = 0; | |
1371 | writew(uap->im, uap->port.membase + UART011_IMSC); | |
1372 | writew(0xffff, uap->port.membase + UART011_ICR); | |
1373 | spin_unlock_irq(&uap->port.lock); | |
1374 | ||
68b65f73 RK |
1375 | pl011_dma_shutdown(uap); |
1376 | ||
1da177e4 LT |
1377 | /* |
1378 | * Free the interrupt | |
1379 | */ | |
1380 | free_irq(uap->port.irq, uap); | |
1381 | ||
1382 | /* | |
1383 | * disable the port | |
1384 | */ | |
3b43816f | 1385 | uap->autorts = false; |
1da177e4 LT |
1386 | writew(UART01x_CR_UARTEN | UART011_CR_TXE, uap->port.membase + UART011_CR); |
1387 | ||
1388 | /* | |
1389 | * disable break condition and fifos | |
1390 | */ | |
ec489aa8 LW |
1391 | pl011_shutdown_channel(uap, uap->lcrh_rx); |
1392 | if (uap->lcrh_rx != uap->lcrh_tx) | |
1393 | pl011_shutdown_channel(uap, uap->lcrh_tx); | |
1da177e4 LT |
1394 | |
1395 | /* | |
1396 | * Shut down the clock producer | |
1397 | */ | |
1398 | clk_disable(uap->clk); | |
1399 | } | |
1400 | ||
1401 | static void | |
606d099c AC |
1402 | pl011_set_termios(struct uart_port *port, struct ktermios *termios, |
1403 | struct ktermios *old) | |
1da177e4 | 1404 | { |
3b43816f | 1405 | struct uart_amba_port *uap = (struct uart_amba_port *)port; |
1da177e4 LT |
1406 | unsigned int lcr_h, old_cr; |
1407 | unsigned long flags; | |
c19f12b5 RK |
1408 | unsigned int baud, quot, clkdiv; |
1409 | ||
1410 | if (uap->vendor->oversampling) | |
1411 | clkdiv = 8; | |
1412 | else | |
1413 | clkdiv = 16; | |
1da177e4 LT |
1414 | |
1415 | /* | |
1416 | * Ask the core to calculate the divisor for us. | |
1417 | */ | |
ac3e3fb4 | 1418 | baud = uart_get_baud_rate(port, termios, old, 0, |
c19f12b5 | 1419 | port->uartclk / clkdiv); |
ac3e3fb4 LW |
1420 | |
1421 | if (baud > port->uartclk/16) | |
1422 | quot = DIV_ROUND_CLOSEST(port->uartclk * 8, baud); | |
1423 | else | |
1424 | quot = DIV_ROUND_CLOSEST(port->uartclk * 4, baud); | |
1da177e4 LT |
1425 | |
1426 | switch (termios->c_cflag & CSIZE) { | |
1427 | case CS5: | |
1428 | lcr_h = UART01x_LCRH_WLEN_5; | |
1429 | break; | |
1430 | case CS6: | |
1431 | lcr_h = UART01x_LCRH_WLEN_6; | |
1432 | break; | |
1433 | case CS7: | |
1434 | lcr_h = UART01x_LCRH_WLEN_7; | |
1435 | break; | |
1436 | default: // CS8 | |
1437 | lcr_h = UART01x_LCRH_WLEN_8; | |
1438 | break; | |
1439 | } | |
1440 | if (termios->c_cflag & CSTOPB) | |
1441 | lcr_h |= UART01x_LCRH_STP2; | |
1442 | if (termios->c_cflag & PARENB) { | |
1443 | lcr_h |= UART01x_LCRH_PEN; | |
1444 | if (!(termios->c_cflag & PARODD)) | |
1445 | lcr_h |= UART01x_LCRH_EPS; | |
1446 | } | |
ffca2b11 | 1447 | if (uap->fifosize > 1) |
1da177e4 LT |
1448 | lcr_h |= UART01x_LCRH_FEN; |
1449 | ||
1450 | spin_lock_irqsave(&port->lock, flags); | |
1451 | ||
1452 | /* | |
1453 | * Update the per-port timeout. | |
1454 | */ | |
1455 | uart_update_timeout(port, termios->c_cflag, baud); | |
1456 | ||
b63d4f0f | 1457 | port->read_status_mask = UART011_DR_OE | 255; |
1da177e4 | 1458 | if (termios->c_iflag & INPCK) |
b63d4f0f | 1459 | port->read_status_mask |= UART011_DR_FE | UART011_DR_PE; |
1da177e4 | 1460 | if (termios->c_iflag & (BRKINT | PARMRK)) |
b63d4f0f | 1461 | port->read_status_mask |= UART011_DR_BE; |
1da177e4 LT |
1462 | |
1463 | /* | |
1464 | * Characters to ignore | |
1465 | */ | |
1466 | port->ignore_status_mask = 0; | |
1467 | if (termios->c_iflag & IGNPAR) | |
b63d4f0f | 1468 | port->ignore_status_mask |= UART011_DR_FE | UART011_DR_PE; |
1da177e4 | 1469 | if (termios->c_iflag & IGNBRK) { |
b63d4f0f | 1470 | port->ignore_status_mask |= UART011_DR_BE; |
1da177e4 LT |
1471 | /* |
1472 | * If we're ignoring parity and break indicators, | |
1473 | * ignore overruns too (for real raw support). | |
1474 | */ | |
1475 | if (termios->c_iflag & IGNPAR) | |
b63d4f0f | 1476 | port->ignore_status_mask |= UART011_DR_OE; |
1da177e4 LT |
1477 | } |
1478 | ||
1479 | /* | |
1480 | * Ignore all characters if CREAD is not set. | |
1481 | */ | |
1482 | if ((termios->c_cflag & CREAD) == 0) | |
b63d4f0f | 1483 | port->ignore_status_mask |= UART_DUMMY_DR_RX; |
1da177e4 LT |
1484 | |
1485 | if (UART_ENABLE_MS(port, termios->c_cflag)) | |
1486 | pl011_enable_ms(port); | |
1487 | ||
1488 | /* first, disable everything */ | |
1489 | old_cr = readw(port->membase + UART011_CR); | |
1490 | writew(0, port->membase + UART011_CR); | |
1491 | ||
3b43816f RV |
1492 | if (termios->c_cflag & CRTSCTS) { |
1493 | if (old_cr & UART011_CR_RTS) | |
1494 | old_cr |= UART011_CR_RTSEN; | |
1495 | ||
1496 | old_cr |= UART011_CR_CTSEN; | |
1497 | uap->autorts = true; | |
1498 | } else { | |
1499 | old_cr &= ~(UART011_CR_CTSEN | UART011_CR_RTSEN); | |
1500 | uap->autorts = false; | |
1501 | } | |
1502 | ||
c19f12b5 RK |
1503 | if (uap->vendor->oversampling) { |
1504 | if (baud > port->uartclk / 16) | |
ac3e3fb4 LW |
1505 | old_cr |= ST_UART011_CR_OVSFACT; |
1506 | else | |
1507 | old_cr &= ~ST_UART011_CR_OVSFACT; | |
1508 | } | |
1509 | ||
1da177e4 LT |
1510 | /* Set baud rate */ |
1511 | writew(quot & 0x3f, port->membase + UART011_FBRD); | |
1512 | writew(quot >> 6, port->membase + UART011_IBRD); | |
1513 | ||
1514 | /* | |
1515 | * ----------v----------v----------v----------v----- | |
1516 | * NOTE: MUST BE WRITTEN AFTER UARTLCR_M & UARTLCR_L | |
1517 | * ----------^----------^----------^----------^----- | |
1518 | */ | |
ec489aa8 LW |
1519 | writew(lcr_h, port->membase + uap->lcrh_rx); |
1520 | if (uap->lcrh_rx != uap->lcrh_tx) { | |
1521 | int i; | |
1522 | /* | |
1523 | * Wait 10 PCLKs before writing LCRH_TX register, | |
1524 | * to get this delay write read only register 10 times | |
1525 | */ | |
1526 | for (i = 0; i < 10; ++i) | |
1527 | writew(0xff, uap->port.membase + UART011_MIS); | |
1528 | writew(lcr_h, port->membase + uap->lcrh_tx); | |
1529 | } | |
1da177e4 LT |
1530 | writew(old_cr, port->membase + UART011_CR); |
1531 | ||
1532 | spin_unlock_irqrestore(&port->lock, flags); | |
1533 | } | |
1534 | ||
1535 | static const char *pl011_type(struct uart_port *port) | |
1536 | { | |
e8a7ba86 RK |
1537 | struct uart_amba_port *uap = (struct uart_amba_port *)port; |
1538 | return uap->port.type == PORT_AMBA ? uap->type : NULL; | |
1da177e4 LT |
1539 | } |
1540 | ||
1541 | /* | |
1542 | * Release the memory region(s) being used by 'port' | |
1543 | */ | |
1544 | static void pl010_release_port(struct uart_port *port) | |
1545 | { | |
1546 | release_mem_region(port->mapbase, SZ_4K); | |
1547 | } | |
1548 | ||
1549 | /* | |
1550 | * Request the memory region(s) being used by 'port' | |
1551 | */ | |
1552 | static int pl010_request_port(struct uart_port *port) | |
1553 | { | |
1554 | return request_mem_region(port->mapbase, SZ_4K, "uart-pl011") | |
1555 | != NULL ? 0 : -EBUSY; | |
1556 | } | |
1557 | ||
1558 | /* | |
1559 | * Configure/autoconfigure the port. | |
1560 | */ | |
1561 | static void pl010_config_port(struct uart_port *port, int flags) | |
1562 | { | |
1563 | if (flags & UART_CONFIG_TYPE) { | |
1564 | port->type = PORT_AMBA; | |
1565 | pl010_request_port(port); | |
1566 | } | |
1567 | } | |
1568 | ||
1569 | /* | |
1570 | * verify the new serial_struct (for TIOCSSERIAL). | |
1571 | */ | |
1572 | static int pl010_verify_port(struct uart_port *port, struct serial_struct *ser) | |
1573 | { | |
1574 | int ret = 0; | |
1575 | if (ser->type != PORT_UNKNOWN && ser->type != PORT_AMBA) | |
1576 | ret = -EINVAL; | |
a62c4133 | 1577 | if (ser->irq < 0 || ser->irq >= nr_irqs) |
1da177e4 LT |
1578 | ret = -EINVAL; |
1579 | if (ser->baud_base < 9600) | |
1580 | ret = -EINVAL; | |
1581 | return ret; | |
1582 | } | |
1583 | ||
1584 | static struct uart_ops amba_pl011_pops = { | |
1585 | .tx_empty = pl01x_tx_empty, | |
1586 | .set_mctrl = pl011_set_mctrl, | |
1587 | .get_mctrl = pl01x_get_mctrl, | |
1588 | .stop_tx = pl011_stop_tx, | |
1589 | .start_tx = pl011_start_tx, | |
1590 | .stop_rx = pl011_stop_rx, | |
1591 | .enable_ms = pl011_enable_ms, | |
1592 | .break_ctl = pl011_break_ctl, | |
1593 | .startup = pl011_startup, | |
1594 | .shutdown = pl011_shutdown, | |
68b65f73 | 1595 | .flush_buffer = pl011_dma_flush_buffer, |
1da177e4 LT |
1596 | .set_termios = pl011_set_termios, |
1597 | .type = pl011_type, | |
1598 | .release_port = pl010_release_port, | |
1599 | .request_port = pl010_request_port, | |
1600 | .config_port = pl010_config_port, | |
1601 | .verify_port = pl010_verify_port, | |
84b5ae15 JW |
1602 | #ifdef CONFIG_CONSOLE_POLL |
1603 | .poll_get_char = pl010_get_poll_char, | |
1604 | .poll_put_char = pl010_put_poll_char, | |
1605 | #endif | |
1da177e4 LT |
1606 | }; |
1607 | ||
1608 | static struct uart_amba_port *amba_ports[UART_NR]; | |
1609 | ||
1610 | #ifdef CONFIG_SERIAL_AMBA_PL011_CONSOLE | |
1611 | ||
d358788f | 1612 | static void pl011_console_putchar(struct uart_port *port, int ch) |
1da177e4 | 1613 | { |
d358788f | 1614 | struct uart_amba_port *uap = (struct uart_amba_port *)port; |
1da177e4 | 1615 | |
d358788f RK |
1616 | while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF) |
1617 | barrier(); | |
1da177e4 LT |
1618 | writew(ch, uap->port.membase + UART01x_DR); |
1619 | } | |
1620 | ||
1621 | static void | |
1622 | pl011_console_write(struct console *co, const char *s, unsigned int count) | |
1623 | { | |
1624 | struct uart_amba_port *uap = amba_ports[co->index]; | |
1625 | unsigned int status, old_cr, new_cr; | |
1da177e4 LT |
1626 | |
1627 | clk_enable(uap->clk); | |
1628 | ||
1629 | /* | |
1630 | * First save the CR then disable the interrupts | |
1631 | */ | |
1632 | old_cr = readw(uap->port.membase + UART011_CR); | |
1633 | new_cr = old_cr & ~UART011_CR_CTSEN; | |
1634 | new_cr |= UART01x_CR_UARTEN | UART011_CR_TXE; | |
1635 | writew(new_cr, uap->port.membase + UART011_CR); | |
1636 | ||
d358788f | 1637 | uart_console_write(&uap->port, s, count, pl011_console_putchar); |
1da177e4 LT |
1638 | |
1639 | /* | |
1640 | * Finally, wait for transmitter to become empty | |
1641 | * and restore the TCR | |
1642 | */ | |
1643 | do { | |
1644 | status = readw(uap->port.membase + UART01x_FR); | |
1645 | } while (status & UART01x_FR_BUSY); | |
1646 | writew(old_cr, uap->port.membase + UART011_CR); | |
1647 | ||
1648 | clk_disable(uap->clk); | |
1649 | } | |
1650 | ||
1651 | static void __init | |
1652 | pl011_console_get_options(struct uart_amba_port *uap, int *baud, | |
1653 | int *parity, int *bits) | |
1654 | { | |
1655 | if (readw(uap->port.membase + UART011_CR) & UART01x_CR_UARTEN) { | |
1656 | unsigned int lcr_h, ibrd, fbrd; | |
1657 | ||
ec489aa8 | 1658 | lcr_h = readw(uap->port.membase + uap->lcrh_tx); |
1da177e4 LT |
1659 | |
1660 | *parity = 'n'; | |
1661 | if (lcr_h & UART01x_LCRH_PEN) { | |
1662 | if (lcr_h & UART01x_LCRH_EPS) | |
1663 | *parity = 'e'; | |
1664 | else | |
1665 | *parity = 'o'; | |
1666 | } | |
1667 | ||
1668 | if ((lcr_h & 0x60) == UART01x_LCRH_WLEN_7) | |
1669 | *bits = 7; | |
1670 | else | |
1671 | *bits = 8; | |
1672 | ||
1673 | ibrd = readw(uap->port.membase + UART011_IBRD); | |
1674 | fbrd = readw(uap->port.membase + UART011_FBRD); | |
1675 | ||
1676 | *baud = uap->port.uartclk * 4 / (64 * ibrd + fbrd); | |
ac3e3fb4 | 1677 | |
c19f12b5 | 1678 | if (uap->vendor->oversampling) { |
ac3e3fb4 LW |
1679 | if (readw(uap->port.membase + UART011_CR) |
1680 | & ST_UART011_CR_OVSFACT) | |
1681 | *baud *= 2; | |
1682 | } | |
1da177e4 LT |
1683 | } |
1684 | } | |
1685 | ||
1686 | static int __init pl011_console_setup(struct console *co, char *options) | |
1687 | { | |
1688 | struct uart_amba_port *uap; | |
1689 | int baud = 38400; | |
1690 | int bits = 8; | |
1691 | int parity = 'n'; | |
1692 | int flow = 'n'; | |
1693 | ||
1694 | /* | |
1695 | * Check whether an invalid uart number has been specified, and | |
1696 | * if so, search for the first available port that does have | |
1697 | * console support. | |
1698 | */ | |
1699 | if (co->index >= UART_NR) | |
1700 | co->index = 0; | |
1701 | uap = amba_ports[co->index]; | |
d28122a5 RK |
1702 | if (!uap) |
1703 | return -ENODEV; | |
1da177e4 LT |
1704 | |
1705 | uap->port.uartclk = clk_get_rate(uap->clk); | |
1706 | ||
1707 | if (options) | |
1708 | uart_parse_options(options, &baud, &parity, &bits, &flow); | |
1709 | else | |
1710 | pl011_console_get_options(uap, &baud, &parity, &bits); | |
1711 | ||
1712 | return uart_set_options(&uap->port, co, baud, parity, bits, flow); | |
1713 | } | |
1714 | ||
2d93486c | 1715 | static struct uart_driver amba_reg; |
1da177e4 LT |
1716 | static struct console amba_console = { |
1717 | .name = "ttyAMA", | |
1718 | .write = pl011_console_write, | |
1719 | .device = uart_console_device, | |
1720 | .setup = pl011_console_setup, | |
1721 | .flags = CON_PRINTBUFFER, | |
1722 | .index = -1, | |
1723 | .data = &amba_reg, | |
1724 | }; | |
1725 | ||
1726 | #define AMBA_CONSOLE (&amba_console) | |
1727 | #else | |
1728 | #define AMBA_CONSOLE NULL | |
1729 | #endif | |
1730 | ||
1731 | static struct uart_driver amba_reg = { | |
1732 | .owner = THIS_MODULE, | |
1733 | .driver_name = "ttyAMA", | |
1734 | .dev_name = "ttyAMA", | |
1735 | .major = SERIAL_AMBA_MAJOR, | |
1736 | .minor = SERIAL_AMBA_MINOR, | |
1737 | .nr = UART_NR, | |
1738 | .cons = AMBA_CONSOLE, | |
1739 | }; | |
1740 | ||
aa25afad | 1741 | static int pl011_probe(struct amba_device *dev, const struct amba_id *id) |
1da177e4 LT |
1742 | { |
1743 | struct uart_amba_port *uap; | |
5926a295 | 1744 | struct vendor_data *vendor = id->data; |
1da177e4 LT |
1745 | void __iomem *base; |
1746 | int i, ret; | |
1747 | ||
1748 | for (i = 0; i < ARRAY_SIZE(amba_ports); i++) | |
1749 | if (amba_ports[i] == NULL) | |
1750 | break; | |
1751 | ||
1752 | if (i == ARRAY_SIZE(amba_ports)) { | |
1753 | ret = -EBUSY; | |
1754 | goto out; | |
1755 | } | |
1756 | ||
dd00cc48 | 1757 | uap = kzalloc(sizeof(struct uart_amba_port), GFP_KERNEL); |
1da177e4 LT |
1758 | if (uap == NULL) { |
1759 | ret = -ENOMEM; | |
1760 | goto out; | |
1761 | } | |
1762 | ||
dc890c2d | 1763 | base = ioremap(dev->res.start, resource_size(&dev->res)); |
1da177e4 LT |
1764 | if (!base) { |
1765 | ret = -ENOMEM; | |
1766 | goto free; | |
1767 | } | |
1768 | ||
ee569c43 | 1769 | uap->clk = clk_get(&dev->dev, NULL); |
1da177e4 LT |
1770 | if (IS_ERR(uap->clk)) { |
1771 | ret = PTR_ERR(uap->clk); | |
1772 | goto unmap; | |
1773 | } | |
1774 | ||
c19f12b5 | 1775 | uap->vendor = vendor; |
ec489aa8 LW |
1776 | uap->lcrh_rx = vendor->lcrh_rx; |
1777 | uap->lcrh_tx = vendor->lcrh_tx; | |
ffca2b11 | 1778 | uap->fifosize = vendor->fifosize; |
1da177e4 LT |
1779 | uap->port.dev = &dev->dev; |
1780 | uap->port.mapbase = dev->res.start; | |
1781 | uap->port.membase = base; | |
1782 | uap->port.iotype = UPIO_MEM; | |
1783 | uap->port.irq = dev->irq[0]; | |
ffca2b11 | 1784 | uap->port.fifosize = uap->fifosize; |
1da177e4 LT |
1785 | uap->port.ops = &amba_pl011_pops; |
1786 | uap->port.flags = UPF_BOOT_AUTOCONF; | |
1787 | uap->port.line = i; | |
68b65f73 | 1788 | pl011_dma_probe(uap); |
1da177e4 | 1789 | |
e8a7ba86 RK |
1790 | snprintf(uap->type, sizeof(uap->type), "PL011 rev%u", amba_rev(dev)); |
1791 | ||
1da177e4 LT |
1792 | amba_ports[i] = uap; |
1793 | ||
1794 | amba_set_drvdata(dev, uap); | |
1795 | ret = uart_add_one_port(&amba_reg, &uap->port); | |
1796 | if (ret) { | |
1797 | amba_set_drvdata(dev, NULL); | |
1798 | amba_ports[i] = NULL; | |
68b65f73 | 1799 | pl011_dma_remove(uap); |
1da177e4 LT |
1800 | clk_put(uap->clk); |
1801 | unmap: | |
1802 | iounmap(base); | |
1803 | free: | |
1804 | kfree(uap); | |
1805 | } | |
1806 | out: | |
1807 | return ret; | |
1808 | } | |
1809 | ||
1810 | static int pl011_remove(struct amba_device *dev) | |
1811 | { | |
1812 | struct uart_amba_port *uap = amba_get_drvdata(dev); | |
1813 | int i; | |
1814 | ||
1815 | amba_set_drvdata(dev, NULL); | |
1816 | ||
1817 | uart_remove_one_port(&amba_reg, &uap->port); | |
1818 | ||
1819 | for (i = 0; i < ARRAY_SIZE(amba_ports); i++) | |
1820 | if (amba_ports[i] == uap) | |
1821 | amba_ports[i] = NULL; | |
1822 | ||
68b65f73 | 1823 | pl011_dma_remove(uap); |
1da177e4 | 1824 | iounmap(uap->port.membase); |
1da177e4 LT |
1825 | clk_put(uap->clk); |
1826 | kfree(uap); | |
1827 | return 0; | |
1828 | } | |
1829 | ||
b736b89f LC |
1830 | #ifdef CONFIG_PM |
1831 | static int pl011_suspend(struct amba_device *dev, pm_message_t state) | |
1832 | { | |
1833 | struct uart_amba_port *uap = amba_get_drvdata(dev); | |
1834 | ||
1835 | if (!uap) | |
1836 | return -EINVAL; | |
1837 | ||
1838 | return uart_suspend_port(&amba_reg, &uap->port); | |
1839 | } | |
1840 | ||
1841 | static int pl011_resume(struct amba_device *dev) | |
1842 | { | |
1843 | struct uart_amba_port *uap = amba_get_drvdata(dev); | |
1844 | ||
1845 | if (!uap) | |
1846 | return -EINVAL; | |
1847 | ||
1848 | return uart_resume_port(&amba_reg, &uap->port); | |
1849 | } | |
1850 | #endif | |
1851 | ||
2c39c9e1 | 1852 | static struct amba_id pl011_ids[] = { |
1da177e4 LT |
1853 | { |
1854 | .id = 0x00041011, | |
1855 | .mask = 0x000fffff, | |
5926a295 AR |
1856 | .data = &vendor_arm, |
1857 | }, | |
1858 | { | |
1859 | .id = 0x00380802, | |
1860 | .mask = 0x00ffffff, | |
1861 | .data = &vendor_st, | |
1da177e4 LT |
1862 | }, |
1863 | { 0, 0 }, | |
1864 | }; | |
1865 | ||
1866 | static struct amba_driver pl011_driver = { | |
1867 | .drv = { | |
1868 | .name = "uart-pl011", | |
1869 | }, | |
1870 | .id_table = pl011_ids, | |
1871 | .probe = pl011_probe, | |
1872 | .remove = pl011_remove, | |
b736b89f LC |
1873 | #ifdef CONFIG_PM |
1874 | .suspend = pl011_suspend, | |
1875 | .resume = pl011_resume, | |
1876 | #endif | |
1da177e4 LT |
1877 | }; |
1878 | ||
1879 | static int __init pl011_init(void) | |
1880 | { | |
1881 | int ret; | |
1882 | printk(KERN_INFO "Serial: AMBA PL011 UART driver\n"); | |
1883 | ||
1884 | ret = uart_register_driver(&amba_reg); | |
1885 | if (ret == 0) { | |
1886 | ret = amba_driver_register(&pl011_driver); | |
1887 | if (ret) | |
1888 | uart_unregister_driver(&amba_reg); | |
1889 | } | |
1890 | return ret; | |
1891 | } | |
1892 | ||
1893 | static void __exit pl011_exit(void) | |
1894 | { | |
1895 | amba_driver_unregister(&pl011_driver); | |
1896 | uart_unregister_driver(&amba_reg); | |
1897 | } | |
1898 | ||
4dd9e742 AR |
1899 | /* |
1900 | * While this can be a module, if builtin it's most likely the console | |
1901 | * So let's leave module_exit but move module_init to an earlier place | |
1902 | */ | |
1903 | arch_initcall(pl011_init); | |
1da177e4 LT |
1904 | module_exit(pl011_exit); |
1905 | ||
1906 | MODULE_AUTHOR("ARM Ltd/Deep Blue Solutions Ltd"); | |
1907 | MODULE_DESCRIPTION("ARM AMBA serial port driver"); | |
1908 | MODULE_LICENSE("GPL"); |