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Merge tag 'drm-msm-next-2018-06-04' of git://people.freedesktop.org/~robclark/linux...
[linux-2.6-block.git] / drivers / tty / serial / amba-pl011.c
CommitLineData
e3b3d0f5 1// SPDX-License-Identifier: GPL-2.0+
1da177e4 2/*
1da177e4
LT		 3 * Driver for AMBA serial ports
4 *
5 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
6 *
7 * Copyright 1999 ARM Limited
8 * Copyright (C) 2000 Deep Blue Solutions Ltd.
68b65f73 9 * Copyright (C) 2010 ST-Ericsson SA
1da177e4 10 *
1da177e4
LT		 11 * This is a generic driver for ARM AMBA-type serial ports. They
12 * have a lot of 16550-like features, but are not register compatible.
13 * Note that although they do have CTS, DCD and DSR inputs, they do
14 * not have an RI input, nor do they have DTR or RTS outputs. If
15 * required, these have to be supplied via some other means (eg, GPIO)
16 * and hooked into this driver.
17 */
1da177e4 18
cb06ff10 19
1da177e4
LT		 20#if defined(CONFIG_SERIAL_AMBA_PL011_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
21#define SUPPORT_SYSRQ
22#endif
23
24#include <linux/module.h>
25#include <linux/ioport.h>
26#include <linux/init.h>
27#include <linux/console.h>
28#include <linux/sysrq.h>
29#include <linux/device.h>
30#include <linux/tty.h>
31#include <linux/tty_flip.h>
32#include <linux/serial_core.h>
33#include <linux/serial.h>
a62c80e5
RK		 34#include <linux/amba/bus.h>
35#include <linux/amba/serial.h>
f8ce2547 36#include <linux/clk.h>
5a0e3ad6 37#include <linux/slab.h>
68b65f73
RK		 38#include <linux/dmaengine.h>
39#include <linux/dma-mapping.h>
40#include <linux/scatterlist.h>
c16d51a3 41#include <linux/delay.h>
258aea76 42#include <linux/types.h>
32614aad
ML		 43#include <linux/of.h>
44#include <linux/of_device.h>
258e0551 45#include <linux/pinctrl/consumer.h>
cb70706c 46#include <linux/sizes.h>
de609582 47#include <linux/io.h>
3db9ab0b 48#include <linux/acpi.h>
1da177e4 49
9f25bc51
RK		 50#include "amba-pl011.h"
51
1da177e4
LT		 52#define UART_NR 14
53
54#define SERIAL_AMBA_MAJOR 204
55#define SERIAL_AMBA_MINOR 64
56#define SERIAL_AMBA_NR UART_NR
57
58#define AMBA_ISR_PASS_LIMIT 256
59
b63d4f0f
RK		 60#define UART_DR_ERROR (UART011_DR_OE|UART011_DR_BE|UART011_DR_PE|UART011_DR_FE)
61#define UART_DUMMY_DR_RX (1 << 16)
1da177e4 62
debb7f64
RK		 63static u16 pl011_std_offsets[REG_ARRAY_SIZE] = {
64 [REG_DR] = UART01x_DR,
debb7f64 65 [REG_FR] = UART01x_FR,
e4df9a80
RK		 66 [REG_LCRH_RX] = UART011_LCRH,
67 [REG_LCRH_TX] = UART011_LCRH,
debb7f64
RK		 68 [REG_IBRD] = UART011_IBRD,
69 [REG_FBRD] = UART011_FBRD,
debb7f64
RK		 70 [REG_CR] = UART011_CR,
71 [REG_IFLS] = UART011_IFLS,
72 [REG_IMSC] = UART011_IMSC,
73 [REG_RIS] = UART011_RIS,
74 [REG_MIS] = UART011_MIS,
75 [REG_ICR] = UART011_ICR,
76 [REG_DMACR] = UART011_DMACR,
debb7f64
RK		 77};
78
5926a295
AR		 79/* There is by now at least one vendor with differing details, so handle it */
80struct vendor_data {
439403bd 81 const u16 *reg_offset;
5926a295 82 unsigned int ifls;
0e125a5f
SG		 83 unsigned int fr_busy;
84 unsigned int fr_dsr;
85 unsigned int fr_cts;
86 unsigned int fr_ri;
d8a4995b 87 unsigned int inv_fr;
84c3e03b 88 bool access_32b;
ac3e3fb4 89 bool oversampling;
38d62436 90 bool dma_threshold;
4fd0690b 91 bool cts_event_workaround;
71eec483 92 bool always_enabled;
cefc2d1d 93 bool fixed_options;
78506f22 94
ea33640a 95 unsigned int (*get_fifosize)(struct amba_device *dev);
5926a295
AR		 96};
97
ea33640a 98static unsigned int get_fifosize_arm(struct amba_device *dev)
78506f22 99{
ea33640a 100 return amba_rev(dev) < 3 ? 16 : 32;
78506f22
JK		 101}
102
5926a295 103static struct vendor_data vendor_arm = {
439403bd 104 .reg_offset = pl011_std_offsets,
5926a295 105 .ifls = UART011_IFLS_RX4_8|UART011_IFLS_TX4_8,
0e125a5f
SG		 106 .fr_busy = UART01x_FR_BUSY,
107 .fr_dsr = UART01x_FR_DSR,
108 .fr_cts = UART01x_FR_CTS,
109 .fr_ri = UART011_FR_RI,
ac3e3fb4 110 .oversampling = false,
38d62436 111 .dma_threshold = false,
4fd0690b 112 .cts_event_workaround = false,
71eec483 113 .always_enabled = false,
cefc2d1d 114 .fixed_options = false,
78506f22 115 .get_fifosize = get_fifosize_arm,
5926a295
AR		 116};
117
d054b3ac 118static const struct vendor_data vendor_sbsa = {
439403bd 119 .reg_offset = pl011_std_offsets,
0e125a5f
SG		 120 .fr_busy = UART01x_FR_BUSY,
121 .fr_dsr = UART01x_FR_DSR,
122 .fr_cts = UART01x_FR_CTS,
123 .fr_ri = UART011_FR_RI,
1aabf523 124 .access_32b = true,
0dd1e247
AP		 125 .oversampling = false,
126 .dma_threshold = false,
127 .cts_event_workaround = false,
128 .always_enabled = true,
129 .fixed_options = true,
130};
131
37ef38f3 132#ifdef CONFIG_ACPI_SPCR_TABLE
d054b3ac 133static const struct vendor_data vendor_qdt_qdf2400_e44 = {
d8a4995b
CC		 134 .reg_offset = pl011_std_offsets,
135 .fr_busy = UART011_FR_TXFE,
136 .fr_dsr = UART01x_FR_DSR,
137 .fr_cts = UART01x_FR_CTS,
138 .fr_ri = UART011_FR_RI,
139 .inv_fr = UART011_FR_TXFE,
140 .access_32b = true,
141 .oversampling = false,
142 .dma_threshold = false,
143 .cts_event_workaround = false,
144 .always_enabled = true,
145 .fixed_options = true,
146};
37ef38f3 147#endif
d8a4995b 148
bf69ff8a
RK		 149static u16 pl011_st_offsets[REG_ARRAY_SIZE] = {
150 [REG_DR] = UART01x_DR,
151 [REG_ST_DMAWM] = ST_UART011_DMAWM,
152 [REG_ST_TIMEOUT] = ST_UART011_TIMEOUT,
153 [REG_FR] = UART01x_FR,
e4df9a80
RK		 154 [REG_LCRH_RX] = ST_UART011_LCRH_RX,
155 [REG_LCRH_TX] = ST_UART011_LCRH_TX,
bf69ff8a
RK		 156 [REG_IBRD] = UART011_IBRD,
157 [REG_FBRD] = UART011_FBRD,
bf69ff8a
RK		 158 [REG_CR] = UART011_CR,
159 [REG_IFLS] = UART011_IFLS,
160 [REG_IMSC] = UART011_IMSC,
161 [REG_RIS] = UART011_RIS,
162 [REG_MIS] = UART011_MIS,
163 [REG_ICR] = UART011_ICR,
164 [REG_DMACR] = UART011_DMACR,
165 [REG_ST_XFCR] = ST_UART011_XFCR,
166 [REG_ST_XON1] = ST_UART011_XON1,
167 [REG_ST_XON2] = ST_UART011_XON2,
168 [REG_ST_XOFF1] = ST_UART011_XOFF1,
169 [REG_ST_XOFF2] = ST_UART011_XOFF2,
170 [REG_ST_ITCR] = ST_UART011_ITCR,
171 [REG_ST_ITIP] = ST_UART011_ITIP,
172 [REG_ST_ABCR] = ST_UART011_ABCR,
173 [REG_ST_ABIMSC] = ST_UART011_ABIMSC,
174};
175
ea33640a 176static unsigned int get_fifosize_st(struct amba_device *dev)
78506f22
JK		 177{
178 return 64;
179}
180
5926a295 181static struct vendor_data vendor_st = {
bf69ff8a 182 .reg_offset = pl011_st_offsets,
5926a295 183 .ifls = UART011_IFLS_RX_HALF|UART011_IFLS_TX_HALF,
0e125a5f
SG		 184 .fr_busy = UART01x_FR_BUSY,
185 .fr_dsr = UART01x_FR_DSR,
186 .fr_cts = UART01x_FR_CTS,
187 .fr_ri = UART011_FR_RI,
ac3e3fb4 188 .oversampling = true,
38d62436 189 .dma_threshold = true,
4fd0690b 190 .cts_event_workaround = true,
71eec483 191 .always_enabled = false,
cefc2d1d 192 .fixed_options = false,
78506f22 193 .get_fifosize = get_fifosize_st,
1da177e4
LT		 194};
195
7ec75871
RK		 196static const u16 pl011_zte_offsets[REG_ARRAY_SIZE] = {
197 [REG_DR] = ZX_UART011_DR,
198 [REG_FR] = ZX_UART011_FR,
199 [REG_LCRH_RX] = ZX_UART011_LCRH,
200 [REG_LCRH_TX] = ZX_UART011_LCRH,
201 [REG_IBRD] = ZX_UART011_IBRD,
202 [REG_FBRD] = ZX_UART011_FBRD,
203 [REG_CR] = ZX_UART011_CR,
204 [REG_IFLS] = ZX_UART011_IFLS,
205 [REG_IMSC] = ZX_UART011_IMSC,
206 [REG_RIS] = ZX_UART011_RIS,
207 [REG_MIS] = ZX_UART011_MIS,
208 [REG_ICR] = ZX_UART011_ICR,
209 [REG_DMACR] = ZX_UART011_DMACR,
210};
211
9c267ddb
SG		 212static unsigned int get_fifosize_zte(struct amba_device *dev)
213{
214 return 16;
215}
216
2426fbc7 217static struct vendor_data vendor_zte = {
7ec75871
RK		 218 .reg_offset = pl011_zte_offsets,
219 .access_32b = true,
220 .ifls = UART011_IFLS_RX4_8|UART011_IFLS_TX4_8,
0e125a5f
SG		 221 .fr_busy = ZX_UART01x_FR_BUSY,
222 .fr_dsr = ZX_UART01x_FR_DSR,
223 .fr_cts = ZX_UART01x_FR_CTS,
224 .fr_ri = ZX_UART011_FR_RI,
9c267ddb 225 .get_fifosize = get_fifosize_zte,
7ec75871
RK		 226};
227
68b65f73 228/* Deals with DMA transactions */
ead76f32
LW		 229
230struct pl011_sgbuf {
231 struct scatterlist sg;
232 char *buf;
233};
234
235struct pl011_dmarx_data {
236 struct dma_chan *chan;
237 struct completion complete;
238 bool use_buf_b;
239 struct pl011_sgbuf sgbuf_a;
240 struct pl011_sgbuf sgbuf_b;
241 dma_cookie_t cookie;
242 bool running;
cb06ff10
CM		 243 struct timer_list timer;
244 unsigned int last_residue;
245 unsigned long last_jiffies;
246 bool auto_poll_rate;
247 unsigned int poll_rate;
248 unsigned int poll_timeout;
ead76f32
LW		 249};
250
68b65f73
RK		 251struct pl011_dmatx_data {
252 struct dma_chan *chan;
253 struct scatterlist sg;
254 char *buf;
255 bool queued;
256};
257
c19f12b5
RK		 258/*
259 * We wrap our port structure around the generic uart_port.
260 */
261struct uart_amba_port {
262 struct uart_port port;
debb7f64 263 const u16 *reg_offset;
c19f12b5
RK		 264 struct clk *clk;
265 const struct vendor_data *vendor;
68b65f73 266 unsigned int dmacr; /* dma control reg */
c19f12b5
RK		 267 unsigned int im; /* interrupt mask */
268 unsigned int old_status;
ffca2b11 269 unsigned int fifosize; /* vendor-specific */
d8d8ffa4 270 unsigned int old_cr; /* state during shutdown */
cefc2d1d 271 unsigned int fixed_baud; /* vendor-set fixed baud rate */
c19f12b5 272 char type[12];
68b65f73
RK		 273#ifdef CONFIG_DMA_ENGINE
274 /* DMA stuff */
ead76f32
LW		 275 bool using_tx_dma;
276 bool using_rx_dma;
277 struct pl011_dmarx_data dmarx;
68b65f73 278 struct pl011_dmatx_data dmatx;
1c9be310 279 bool dma_probed;
68b65f73
RK		 280#endif
281};
282
9f25bc51
RK		 283static unsigned int pl011_reg_to_offset(const struct uart_amba_port *uap,
284 unsigned int reg)
285{
debb7f64 286 return uap->reg_offset[reg];
9f25bc51
RK		 287}
288
b2a4e24c
RK		 289static unsigned int pl011_read(const struct uart_amba_port *uap,
290 unsigned int reg)
75836339 291{
84c3e03b
RK		 292 void __iomem *addr = uap->port.membase + pl011_reg_to_offset(uap, reg);
293
3b78fae7
TT		 294 return (uap->port.iotype == UPIO_MEM32) ?
295 readl_relaxed(addr) : readw_relaxed(addr);
75836339
RK		 296}
297
b2a4e24c
RK		 298static void pl011_write(unsigned int val, const struct uart_amba_port *uap,
299 unsigned int reg)
75836339 300{
84c3e03b
RK		 301 void __iomem *addr = uap->port.membase + pl011_reg_to_offset(uap, reg);
302
3b78fae7 303 if (uap->port.iotype == UPIO_MEM32)
f5ce6edd 304 writel_relaxed(val, addr);
84c3e03b 305 else
f5ce6edd 306 writew_relaxed(val, addr);
75836339
RK		 307}
308
29772c4e
LW		 309/*
310 * Reads up to 256 characters from the FIFO or until it's empty and
311 * inserts them into the TTY layer. Returns the number of characters
312 * read from the FIFO.
313 */
314static int pl011_fifo_to_tty(struct uart_amba_port *uap)
315{
71a5cd8a 316 u16 status;
e73be92d 317 unsigned int ch, flag, fifotaken;
29772c4e 318
e73be92d 319 for (fifotaken = 0; fifotaken != 256; fifotaken++) {
9f25bc51 320 status = pl011_read(uap, REG_FR);
29772c4e
LW		 321 if (status & UART01x_FR_RXFE)
322 break;
323
324 /* Take chars from the FIFO and update status */
9f25bc51 325 ch = pl011_read(uap, REG_DR) | UART_DUMMY_DR_RX;
29772c4e
LW		 326 flag = TTY_NORMAL;
327 uap->port.icount.rx++;
29772c4e
LW		 328
329 if (unlikely(ch & UART_DR_ERROR)) {
330 if (ch & UART011_DR_BE) {
331 ch &= ~(UART011_DR_FE | UART011_DR_PE);
332 uap->port.icount.brk++;
333 if (uart_handle_break(&uap->port))
334 continue;
335 } else if (ch & UART011_DR_PE)
336 uap->port.icount.parity++;
337 else if (ch & UART011_DR_FE)
338 uap->port.icount.frame++;
339 if (ch & UART011_DR_OE)
340 uap->port.icount.overrun++;
341
342 ch &= uap->port.read_status_mask;
343
344 if (ch & UART011_DR_BE)
345 flag = TTY_BREAK;
346 else if (ch & UART011_DR_PE)
347 flag = TTY_PARITY;
348 else if (ch & UART011_DR_FE)
349 flag = TTY_FRAME;
350 }
351
352 if (uart_handle_sysrq_char(&uap->port, ch & 255))
353 continue;
354
355 uart_insert_char(&uap->port, ch, UART011_DR_OE, ch, flag);
356 }
357
358 return fifotaken;
359}
360
361
68b65f73
RK		 362/*
363 * All the DMA operation mode stuff goes inside this ifdef.
364 * This assumes that you have a generic DMA device interface,
365 * no custom DMA interfaces are supported.
366 */
367#ifdef CONFIG_DMA_ENGINE
368
369#define PL011_DMA_BUFFER_SIZE PAGE_SIZE
370
ead76f32
LW		 371static int pl011_sgbuf_init(struct dma_chan *chan, struct pl011_sgbuf *sg,
372 enum dma_data_direction dir)
373{
cb06ff10
CM		 374 dma_addr_t dma_addr;
375
376 sg->buf = dma_alloc_coherent(chan->device->dev,
377 PL011_DMA_BUFFER_SIZE, &dma_addr, GFP_KERNEL);
ead76f32
LW		 378 if (!sg->buf)
379 return -ENOMEM;
380
cb06ff10
CM		 381 sg_init_table(&sg->sg, 1);
382 sg_set_page(&sg->sg, phys_to_page(dma_addr),
383 PL011_DMA_BUFFER_SIZE, offset_in_page(dma_addr));
384 sg_dma_address(&sg->sg) = dma_addr;
c64be923 385 sg_dma_len(&sg->sg) = PL011_DMA_BUFFER_SIZE;
ead76f32 386
ead76f32
LW		 387 return 0;
388}
389
390static void pl011_sgbuf_free(struct dma_chan *chan, struct pl011_sgbuf *sg,
391 enum dma_data_direction dir)
392{
393 if (sg->buf) {
cb06ff10
CM		 394 dma_free_coherent(chan->device->dev,
395 PL011_DMA_BUFFER_SIZE, sg->buf,
396 sg_dma_address(&sg->sg));
ead76f32
LW		 397 }
398}
399
1c9be310 400static void pl011_dma_probe(struct uart_amba_port *uap)
68b65f73
RK		 401{
402 /* DMA is the sole user of the platform data right now */
574de559 403 struct amba_pl011_data *plat = dev_get_platdata(uap->port.dev);
1c9be310 404 struct device *dev = uap->port.dev;
68b65f73 405 struct dma_slave_config tx_conf = {
9f25bc51
RK		 406 .dst_addr = uap->port.mapbase +
407 pl011_reg_to_offset(uap, REG_DR),
68b65f73 408 .dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
a485df4b 409 .direction = DMA_MEM_TO_DEV,
68b65f73 410 .dst_maxburst = uap->fifosize >> 1,
258aea76 411 .device_fc = false,
68b65f73
RK		 412 };
413 struct dma_chan *chan;
414 dma_cap_mask_t mask;
415
1c9be310
JRO		 416 uap->dma_probed = true;
417 chan = dma_request_slave_channel_reason(dev, "tx");
418 if (IS_ERR(chan)) {
419 if (PTR_ERR(chan) == -EPROBE_DEFER) {
1c9be310
JRO		 420 uap->dma_probed = false;
421 return;
422 }
68b65f73 423
787b0c1f
AB		 424 /* We need platform data */
425 if (!plat || !plat->dma_filter) {
426 dev_info(uap->port.dev, "no DMA platform data\n");
427 return;
428 }
429
430 /* Try to acquire a generic DMA engine slave TX channel */
431 dma_cap_zero(mask);
432 dma_cap_set(DMA_SLAVE, mask);
433
434 chan = dma_request_channel(mask, plat->dma_filter,
435 plat->dma_tx_param);
436 if (!chan) {
437 dev_err(uap->port.dev, "no TX DMA channel!\n");
438 return;
439 }
68b65f73
RK		 440 }
441
442 dmaengine_slave_config(chan, &tx_conf);
443 uap->dmatx.chan = chan;
444
445 dev_info(uap->port.dev, "DMA channel TX %s\n",
446 dma_chan_name(uap->dmatx.chan));
ead76f32
LW		 447
448 /* Optionally make use of an RX channel as well */
787b0c1f 449 chan = dma_request_slave_channel(dev, "rx");
0d3c673e 450
d9e105ca 451 if (!chan && plat && plat->dma_rx_param) {
787b0c1f
AB		 452 chan = dma_request_channel(mask, plat->dma_filter, plat->dma_rx_param);
453
454 if (!chan) {
455 dev_err(uap->port.dev, "no RX DMA channel!\n");
456 return;
457 }
458 }
459
460 if (chan) {
ead76f32 461 struct dma_slave_config rx_conf = {
9f25bc51
RK		 462 .src_addr = uap->port.mapbase +
463 pl011_reg_to_offset(uap, REG_DR),
ead76f32 464 .src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
a485df4b 465 .direction = DMA_DEV_TO_MEM,
b2aeb775 466 .src_maxburst = uap->fifosize >> 2,
258aea76 467 .device_fc = false,
ead76f32 468 };
2d3b7d6e
AJ		 469 struct dma_slave_caps caps;
470
471 /*
472 * Some DMA controllers provide information on their capabilities.
473 * If the controller does, check for suitable residue processing
474 * otherwise assime all is well.
475 */
476 if (0 == dma_get_slave_caps(chan, &caps)) {
477 if (caps.residue_granularity ==
478 DMA_RESIDUE_GRANULARITY_DESCRIPTOR) {
479 dma_release_channel(chan);
480 dev_info(uap->port.dev,
481 "RX DMA disabled - no residue processing\n");
482 return;
483 }
484 }
ead76f32
LW		 485 dmaengine_slave_config(chan, &rx_conf);
486 uap->dmarx.chan = chan;
487
98267d33 488 uap->dmarx.auto_poll_rate = false;
8f898bfd 489 if (plat && plat->dma_rx_poll_enable) {
cb06ff10
CM		 490 /* Set poll rate if specified. */
491 if (plat->dma_rx_poll_rate) {
492 uap->dmarx.auto_poll_rate = false;
493 uap->dmarx.poll_rate = plat->dma_rx_poll_rate;
494 } else {
495 /*
496 * 100 ms defaults to poll rate if not
497 * specified. This will be adjusted with
498 * the baud rate at set_termios.
499 */
500 uap->dmarx.auto_poll_rate = true;
501 uap->dmarx.poll_rate = 100;
502 }
503 /* 3 secs defaults poll_timeout if not specified. */
504 if (plat->dma_rx_poll_timeout)
505 uap->dmarx.poll_timeout =
506 plat->dma_rx_poll_timeout;
507 else
508 uap->dmarx.poll_timeout = 3000;
98267d33
AJ		 509 } else if (!plat && dev->of_node) {
510 uap->dmarx.auto_poll_rate = of_property_read_bool(
511 dev->of_node, "auto-poll");
512 if (uap->dmarx.auto_poll_rate) {
513 u32 x;
514
515 if (0 == of_property_read_u32(dev->of_node,
516 "poll-rate-ms", &x))
517 uap->dmarx.poll_rate = x;
518 else
519 uap->dmarx.poll_rate = 100;
520 if (0 == of_property_read_u32(dev->of_node,
521 "poll-timeout-ms", &x))
522 uap->dmarx.poll_timeout = x;
523 else
524 uap->dmarx.poll_timeout = 3000;
525 }
526 }
ead76f32
LW		 527 dev_info(uap->port.dev, "DMA channel RX %s\n",
528 dma_chan_name(uap->dmarx.chan));
529 }
68b65f73
RK		 530}
531
68b65f73
RK		 532static void pl011_dma_remove(struct uart_amba_port *uap)
533{
68b65f73
RK		 534 if (uap->dmatx.chan)
535 dma_release_channel(uap->dmatx.chan);
ead76f32
LW		 536 if (uap->dmarx.chan)
537 dma_release_channel(uap->dmarx.chan);
68b65f73
RK		 538}
539
734745ca 540/* Forward declare these for the refill routine */
68b65f73 541static int pl011_dma_tx_refill(struct uart_amba_port *uap);
734745ca 542static void pl011_start_tx_pio(struct uart_amba_port *uap);
68b65f73
RK		 543
544/*
545 * The current DMA TX buffer has been sent.
546 * Try to queue up another DMA buffer.
547 */
548static void pl011_dma_tx_callback(void *data)
549{
550 struct uart_amba_port *uap = data;
551 struct pl011_dmatx_data *dmatx = &uap->dmatx;
552 unsigned long flags;
553 u16 dmacr;
554
555 spin_lock_irqsave(&uap->port.lock, flags);
556 if (uap->dmatx.queued)
557 dma_unmap_sg(dmatx->chan->device->dev, &dmatx->sg, 1,
558 DMA_TO_DEVICE);
559
560 dmacr = uap->dmacr;
561 uap->dmacr = dmacr & ~UART011_TXDMAE;
9f25bc51 562 pl011_write(uap->dmacr, uap, REG_DMACR);
68b65f73
RK		 563
564 /*
565 * If TX DMA was disabled, it means that we've stopped the DMA for
566 * some reason (eg, XOFF received, or we want to send an X-char.)
567 *
568 * Note: we need to be careful here of a potential race between DMA
569 * and the rest of the driver - if the driver disables TX DMA while
570 * a TX buffer completing, we must update the tx queued status to
571 * get further refills (hence we check dmacr).
572 */
573 if (!(dmacr & UART011_TXDMAE) || uart_tx_stopped(&uap->port) ||
574 uart_circ_empty(&uap->port.state->xmit)) {
575 uap->dmatx.queued = false;
576 spin_unlock_irqrestore(&uap->port.lock, flags);
577 return;
578 }
579
734745ca 580 if (pl011_dma_tx_refill(uap) <= 0)
68b65f73
RK		 581 /*
582 * We didn't queue a DMA buffer for some reason, but we
583 * have data pending to be sent. Re-enable the TX IRQ.
584 */
734745ca
DM		 585 pl011_start_tx_pio(uap);
586
68b65f73
RK		 587 spin_unlock_irqrestore(&uap->port.lock, flags);
588}
589
590/*
591 * Try to refill the TX DMA buffer.
592 * Locking: called with port lock held and IRQs disabled.
593 * Returns:
594 * 1 if we queued up a TX DMA buffer.
595 * 0 if we didn't want to handle this by DMA
596 * <0 on error
597 */
598static int pl011_dma_tx_refill(struct uart_amba_port *uap)
599{
600 struct pl011_dmatx_data *dmatx = &uap->dmatx;
601 struct dma_chan *chan = dmatx->chan;
602 struct dma_device *dma_dev = chan->device;
603 struct dma_async_tx_descriptor *desc;
604 struct circ_buf *xmit = &uap->port.state->xmit;
605 unsigned int count;
606
607 /*
608 * Try to avoid the overhead involved in using DMA if the
609 * transaction fits in the first half of the FIFO, by using
610 * the standard interrupt handling. This ensures that we
611 * issue a uart_write_wakeup() at the appropriate time.
612 */
613 count = uart_circ_chars_pending(xmit);
614 if (count < (uap->fifosize >> 1)) {
615 uap->dmatx.queued = false;
616 return 0;
617 }
618
619 /*
620 * Bodge: don't send the last character by DMA, as this
621 * will prevent XON from notifying us to restart DMA.
622 */
623 count -= 1;
624
625 /* Else proceed to copy the TX chars to the DMA buffer and fire DMA */
626 if (count > PL011_DMA_BUFFER_SIZE)
627 count = PL011_DMA_BUFFER_SIZE;
628
629 if (xmit->tail < xmit->head)
630 memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], count);
631 else {
632 size_t first = UART_XMIT_SIZE - xmit->tail;
e2a545a6
AJ		 633 size_t second;
634
635 if (first > count)
636 first = count;
637 second = count - first;
68b65f73
RK		 638
639 memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], first);
640 if (second)
641 memcpy(&dmatx->buf[first], &xmit->buf[0], second);
642 }
643
644 dmatx->sg.length = count;
645
646 if (dma_map_sg(dma_dev->dev, &dmatx->sg, 1, DMA_TO_DEVICE) != 1) {
647 uap->dmatx.queued = false;
648 dev_dbg(uap->port.dev, "unable to map TX DMA\n");
649 return -EBUSY;
650 }
651
16052827 652 desc = dmaengine_prep_slave_sg(chan, &dmatx->sg, 1, DMA_MEM_TO_DEV,
68b65f73
RK		 653 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
654 if (!desc) {
655 dma_unmap_sg(dma_dev->dev, &dmatx->sg, 1, DMA_TO_DEVICE);
656 uap->dmatx.queued = false;
657 /*
658 * If DMA cannot be used right now, we complete this
659 * transaction via IRQ and let the TTY layer retry.
660 */
661 dev_dbg(uap->port.dev, "TX DMA busy\n");
662 return -EBUSY;
663 }
664
665 /* Some data to go along to the callback */
666 desc->callback = pl011_dma_tx_callback;
667 desc->callback_param = uap;
668
669 /* All errors should happen at prepare time */
670 dmaengine_submit(desc);
671
672 /* Fire the DMA transaction */
673 dma_dev->device_issue_pending(chan);
674
675 uap->dmacr |= UART011_TXDMAE;
9f25bc51 676 pl011_write(uap->dmacr, uap, REG_DMACR);
68b65f73
RK		 677 uap->dmatx.queued = true;
678
679 /*
680 * Now we know that DMA will fire, so advance the ring buffer
681 * with the stuff we just dispatched.
682 */
683 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
684 uap->port.icount.tx += count;
685
686 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
687 uart_write_wakeup(&uap->port);
688
689 return 1;
690}
691
692/*
693 * We received a transmit interrupt without a pending X-char but with
694 * pending characters.
695 * Locking: called with port lock held and IRQs disabled.
696 * Returns:
697 * false if we want to use PIO to transmit
698 * true if we queued a DMA buffer
699 */
700static bool pl011_dma_tx_irq(struct uart_amba_port *uap)
701{
ead76f32 702 if (!uap->using_tx_dma)
68b65f73
RK		 703 return false;
704
705 /*
706 * If we already have a TX buffer queued, but received a
707 * TX interrupt, it will be because we've just sent an X-char.
708 * Ensure the TX DMA is enabled and the TX IRQ is disabled.
709 */
710 if (uap->dmatx.queued) {
711 uap->dmacr |= UART011_TXDMAE;
9f25bc51 712 pl011_write(uap->dmacr, uap, REG_DMACR);
68b65f73 713 uap->im &= ~UART011_TXIM;
9f25bc51 714 pl011_write(uap->im, uap, REG_IMSC);
68b65f73
RK		 715 return true;
716 }
717
718 /*
719 * We don't have a TX buffer queued, so try to queue one.
25985edc 720 * If we successfully queued a buffer, mask the TX IRQ.
68b65f73
RK		 721 */
722 if (pl011_dma_tx_refill(uap) > 0) {
723 uap->im &= ~UART011_TXIM;
9f25bc51 724 pl011_write(uap->im, uap, REG_IMSC);
68b65f73
RK		 725 return true;
726 }
727 return false;
728}
729
730/*
731 * Stop the DMA transmit (eg, due to received XOFF).
732 * Locking: called with port lock held and IRQs disabled.
733 */
734static inline void pl011_dma_tx_stop(struct uart_amba_port *uap)
735{
736 if (uap->dmatx.queued) {
737 uap->dmacr &= ~UART011_TXDMAE;
9f25bc51 738 pl011_write(uap->dmacr, uap, REG_DMACR);
68b65f73
RK		 739 }
740}
741
742/*
743 * Try to start a DMA transmit, or in the case of an XON/OFF
744 * character queued for send, try to get that character out ASAP.
745 * Locking: called with port lock held and IRQs disabled.
746 * Returns:
747 * false if we want the TX IRQ to be enabled
748 * true if we have a buffer queued
749 */
750static inline bool pl011_dma_tx_start(struct uart_amba_port *uap)
751{
752 u16 dmacr;
753
ead76f32 754 if (!uap->using_tx_dma)
68b65f73
RK		 755 return false;
756
757 if (!uap->port.x_char) {
758 /* no X-char, try to push chars out in DMA mode */
759 bool ret = true;
760
761 if (!uap->dmatx.queued) {
762 if (pl011_dma_tx_refill(uap) > 0) {
763 uap->im &= ~UART011_TXIM;
9f25bc51 764 pl011_write(uap->im, uap, REG_IMSC);
734745ca 765 } else
68b65f73 766 ret = false;
68b65f73
RK		 767 } else if (!(uap->dmacr & UART011_TXDMAE)) {
768 uap->dmacr |= UART011_TXDMAE;
9f25bc51 769 pl011_write(uap->dmacr, uap, REG_DMACR);
68b65f73
RK		 770 }
771 return ret;
772 }
773
774 /*
775 * We have an X-char to send. Disable DMA to prevent it loading
776 * the TX fifo, and then see if we can stuff it into the FIFO.
777 */
778 dmacr = uap->dmacr;
779 uap->dmacr &= ~UART011_TXDMAE;
9f25bc51 780 pl011_write(uap->dmacr, uap, REG_DMACR);
68b65f73 781
9f25bc51 782 if (pl011_read(uap, REG_FR) & UART01x_FR_TXFF) {
68b65f73
RK		 783 /*
784 * No space in the FIFO, so enable the transmit interrupt
785 * so we know when there is space. Note that once we've
786 * loaded the character, we should just re-enable DMA.
787 */
788 return false;
789 }
790
9f25bc51 791 pl011_write(uap->port.x_char, uap, REG_DR);
68b65f73
RK		 792 uap->port.icount.tx++;
793 uap->port.x_char = 0;
794
795 /* Success - restore the DMA state */
796 uap->dmacr = dmacr;
9f25bc51 797 pl011_write(dmacr, uap, REG_DMACR);
68b65f73
RK		 798
799 return true;
800}
801
802/*
803 * Flush the transmit buffer.
804 * Locking: called with port lock held and IRQs disabled.
805 */
806static void pl011_dma_flush_buffer(struct uart_port *port)
b83286bf
FE		 807__releases(&uap->port.lock)
808__acquires(&uap->port.lock)
68b65f73 809{
a5820c24
DT		 810 struct uart_amba_port *uap =
811 container_of(port, struct uart_amba_port, port);
68b65f73 812
ead76f32 813 if (!uap->using_tx_dma)
68b65f73
RK		 814 return;
815
816 /* Avoid deadlock with the DMA engine callback */
817 spin_unlock(&uap->port.lock);
818 dmaengine_terminate_all(uap->dmatx.chan);
819 spin_lock(&uap->port.lock);
820 if (uap->dmatx.queued) {
821 dma_unmap_sg(uap->dmatx.chan->device->dev, &uap->dmatx.sg, 1,
822 DMA_TO_DEVICE);
823 uap->dmatx.queued = false;
824 uap->dmacr &= ~UART011_TXDMAE;
9f25bc51 825 pl011_write(uap->dmacr, uap, REG_DMACR);
68b65f73
RK		 826 }
827}
828
ead76f32
LW		 829static void pl011_dma_rx_callback(void *data);
830
831static int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap)
832{
833 struct dma_chan *rxchan = uap->dmarx.chan;
ead76f32
LW		 834 struct pl011_dmarx_data *dmarx = &uap->dmarx;
835 struct dma_async_tx_descriptor *desc;
836 struct pl011_sgbuf *sgbuf;
837
838 if (!rxchan)
839 return -EIO;
840
841 /* Start the RX DMA job */
842 sgbuf = uap->dmarx.use_buf_b ?
843 &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a;
16052827 844 desc = dmaengine_prep_slave_sg(rxchan, &sgbuf->sg, 1,
a485df4b 845 DMA_DEV_TO_MEM,
ead76f32
LW		 846 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
847 /*
848 * If the DMA engine is busy and cannot prepare a
849 * channel, no big deal, the driver will fall back
850 * to interrupt mode as a result of this error code.
851 */
852 if (!desc) {
853 uap->dmarx.running = false;
854 dmaengine_terminate_all(rxchan);
855 return -EBUSY;
856 }
857
858 /* Some data to go along to the callback */
859 desc->callback = pl011_dma_rx_callback;
860 desc->callback_param = uap;
861 dmarx->cookie = dmaengine_submit(desc);
862 dma_async_issue_pending(rxchan);
863
864 uap->dmacr |= UART011_RXDMAE;
9f25bc51 865 pl011_write(uap->dmacr, uap, REG_DMACR);
ead76f32
LW		 866 uap->dmarx.running = true;
867
868 uap->im &= ~UART011_RXIM;
9f25bc51 869 pl011_write(uap->im, uap, REG_IMSC);
ead76f32
LW		 870
871 return 0;
872}
873
874/*
875 * This is called when either the DMA job is complete, or
876 * the FIFO timeout interrupt occurred. This must be called
877 * with the port spinlock uap->port.lock held.
878 */
879static void pl011_dma_rx_chars(struct uart_amba_port *uap,
880 u32 pending, bool use_buf_b,
881 bool readfifo)
882{
05c7cd39 883 struct tty_port *port = &uap->port.state->port;
ead76f32
LW		 884 struct pl011_sgbuf *sgbuf = use_buf_b ?
885 &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a;
ead76f32
LW		 886 int dma_count = 0;
887 u32 fifotaken = 0; /* only used for vdbg() */
888
cb06ff10
CM		 889 struct pl011_dmarx_data *dmarx = &uap->dmarx;
890 int dmataken = 0;
891
892 if (uap->dmarx.poll_rate) {
893 /* The data can be taken by polling */
894 dmataken = sgbuf->sg.length - dmarx->last_residue;
895 /* Recalculate the pending size */
896 if (pending >= dmataken)
897 pending -= dmataken;
898 }
899
900 /* Pick the remain data from the DMA */
ead76f32 901 if (pending) {
ead76f32
LW		 902
903 /*
904 * First take all chars in the DMA pipe, then look in the FIFO.
905 * Note that tty_insert_flip_buf() tries to take as many chars
906 * as it can.
907 */
cb06ff10
CM		 908 dma_count = tty_insert_flip_string(port, sgbuf->buf + dmataken,
909 pending);
ead76f32
LW		 910
911 uap->port.icount.rx += dma_count;
912 if (dma_count < pending)
913 dev_warn(uap->port.dev,
914 "couldn't insert all characters (TTY is full?)\n");
915 }
916
cb06ff10
CM		 917 /* Reset the last_residue for Rx DMA poll */
918 if (uap->dmarx.poll_rate)
919 dmarx->last_residue = sgbuf->sg.length;
920
ead76f32
LW		 921 /*
922 * Only continue with trying to read the FIFO if all DMA chars have
923 * been taken first.
924 */
925 if (dma_count == pending && readfifo) {
926 /* Clear any error flags */
75836339 927 pl011_write(UART011_OEIS | UART011_BEIS | UART011_PEIS |
9f25bc51 928 UART011_FEIS, uap, REG_ICR);
ead76f32
LW		 929
930 /*
931 * If we read all the DMA'd characters, and we had an
29772c4e
LW		 932 * incomplete buffer, that could be due to an rx error, or
933 * maybe we just timed out. Read any pending chars and check
934 * the error status.
935 *
936 * Error conditions will only occur in the FIFO, these will
937 * trigger an immediate interrupt and stop the DMA job, so we
938 * will always find the error in the FIFO, never in the DMA
939 * buffer.
ead76f32 940 */
29772c4e 941 fifotaken = pl011_fifo_to_tty(uap);
ead76f32
LW		 942 }
943
944 spin_unlock(&uap->port.lock);
945 dev_vdbg(uap->port.dev,
946 "Took %d chars from DMA buffer and %d chars from the FIFO\n",
947 dma_count, fifotaken);
2e124b4a 948 tty_flip_buffer_push(port);
ead76f32
LW		 949 spin_lock(&uap->port.lock);
950}
951
952static void pl011_dma_rx_irq(struct uart_amba_port *uap)
953{
954 struct pl011_dmarx_data *dmarx = &uap->dmarx;
955 struct dma_chan *rxchan = dmarx->chan;
956 struct pl011_sgbuf *sgbuf = dmarx->use_buf_b ?
957 &dmarx->sgbuf_b : &dmarx->sgbuf_a;
958 size_t pending;
959 struct dma_tx_state state;
960 enum dma_status dmastat;
961
962 /*
963 * Pause the transfer so we can trust the current counter,
964 * do this before we pause the PL011 block, else we may
965 * overflow the FIFO.
966 */
967 if (dmaengine_pause(rxchan))
968 dev_err(uap->port.dev, "unable to pause DMA transfer\n");
969 dmastat = rxchan->device->device_tx_status(rxchan,
970 dmarx->cookie, &state);
971 if (dmastat != DMA_PAUSED)
972 dev_err(uap->port.dev, "unable to pause DMA transfer\n");
973
974 /* Disable RX DMA - incoming data will wait in the FIFO */
975 uap->dmacr &= ~UART011_RXDMAE;
9f25bc51 976 pl011_write(uap->dmacr, uap, REG_DMACR);
ead76f32
LW		 977 uap->dmarx.running = false;
978
979 pending = sgbuf->sg.length - state.residue;
980 BUG_ON(pending > PL011_DMA_BUFFER_SIZE);
981 /* Then we terminate the transfer - we now know our residue */
982 dmaengine_terminate_all(rxchan);
983
984 /*
985 * This will take the chars we have so far and insert
986 * into the framework.
987 */
988 pl011_dma_rx_chars(uap, pending, dmarx->use_buf_b, true);
989
990 /* Switch buffer & re-trigger DMA job */
991 dmarx->use_buf_b = !dmarx->use_buf_b;
992 if (pl011_dma_rx_trigger_dma(uap)) {
993 dev_dbg(uap->port.dev, "could not retrigger RX DMA job "
994 "fall back to interrupt mode\n");
995 uap->im |= UART011_RXIM;
9f25bc51 996 pl011_write(uap->im, uap, REG_IMSC);
ead76f32
LW		 997 }
998}
999
1000static void pl011_dma_rx_callback(void *data)
1001{
1002 struct uart_amba_port *uap = data;
1003 struct pl011_dmarx_data *dmarx = &uap->dmarx;
6dc01aa6 1004 struct dma_chan *rxchan = dmarx->chan;
ead76f32 1005 bool lastbuf = dmarx->use_buf_b;
6dc01aa6
CM		 1006 struct pl011_sgbuf *sgbuf = dmarx->use_buf_b ?
1007 &dmarx->sgbuf_b : &dmarx->sgbuf_a;
1008 size_t pending;
1009 struct dma_tx_state state;
ead76f32
LW		 1010 int ret;
1011
1012 /*
1013 * This completion interrupt occurs typically when the
1014 * RX buffer is totally stuffed but no timeout has yet
1015 * occurred. When that happens, we just want the RX
1016 * routine to flush out the secondary DMA buffer while
1017 * we immediately trigger the next DMA job.
1018 */
1019 spin_lock_irq(&uap->port.lock);
6dc01aa6
CM		 1020 /*
1021 * Rx data can be taken by the UART interrupts during
1022 * the DMA irq handler. So we check the residue here.
1023 */
1024 rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state);
1025 pending = sgbuf->sg.length - state.residue;
1026 BUG_ON(pending > PL011_DMA_BUFFER_SIZE);
1027 /* Then we terminate the transfer - we now know our residue */
1028 dmaengine_terminate_all(rxchan);
1029
ead76f32
LW		 1030 uap->dmarx.running = false;
1031 dmarx->use_buf_b = !lastbuf;
1032 ret = pl011_dma_rx_trigger_dma(uap);
1033
6dc01aa6 1034 pl011_dma_rx_chars(uap, pending, lastbuf, false);
ead76f32
LW		 1035 spin_unlock_irq(&uap->port.lock);
1036 /*
1037 * Do this check after we picked the DMA chars so we don't
1038 * get some IRQ immediately from RX.
1039 */
1040 if (ret) {
1041 dev_dbg(uap->port.dev, "could not retrigger RX DMA job "
1042 "fall back to interrupt mode\n");
1043 uap->im |= UART011_RXIM;
9f25bc51 1044 pl011_write(uap->im, uap, REG_IMSC);
ead76f32
LW		 1045 }
1046}
1047
1048/*
1049 * Stop accepting received characters, when we're shutting down or
1050 * suspending this port.
1051 * Locking: called with port lock held and IRQs disabled.
1052 */
1053static inline void pl011_dma_rx_stop(struct uart_amba_port *uap)
1054{
1055 /* FIXME. Just disable the DMA enable */
1056 uap->dmacr &= ~UART011_RXDMAE;
9f25bc51 1057 pl011_write(uap->dmacr, uap, REG_DMACR);
ead76f32 1058}
68b65f73 1059
cb06ff10
CM		 1060/*
1061 * Timer handler for Rx DMA polling.
1062 * Every polling, It checks the residue in the dma buffer and transfer
1063 * data to the tty. Also, last_residue is updated for the next polling.
1064 */
f7f73096 1065static void pl011_dma_rx_poll(struct timer_list *t)
cb06ff10 1066{
f7f73096 1067 struct uart_amba_port *uap = from_timer(uap, t, dmarx.timer);
cb06ff10
CM		 1068 struct tty_port *port = &uap->port.state->port;
1069 struct pl011_dmarx_data *dmarx = &uap->dmarx;
1070 struct dma_chan *rxchan = uap->dmarx.chan;
1071 unsigned long flags = 0;
1072 unsigned int dmataken = 0;
1073 unsigned int size = 0;
1074 struct pl011_sgbuf *sgbuf;
1075 int dma_count;
1076 struct dma_tx_state state;
1077
1078 sgbuf = dmarx->use_buf_b ? &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a;
1079 rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state);
1080 if (likely(state.residue < dmarx->last_residue)) {
1081 dmataken = sgbuf->sg.length - dmarx->last_residue;
1082 size = dmarx->last_residue - state.residue;
1083 dma_count = tty_insert_flip_string(port, sgbuf->buf + dmataken,
1084 size);
1085 if (dma_count == size)
1086 dmarx->last_residue = state.residue;
1087 dmarx->last_jiffies = jiffies;
1088 }
1089 tty_flip_buffer_push(port);
1090
1091 /*
1092 * If no data is received in poll_timeout, the driver will fall back
1093 * to interrupt mode. We will retrigger DMA at the first interrupt.
1094 */
1095 if (jiffies_to_msecs(jiffies - dmarx->last_jiffies)
1096 > uap->dmarx.poll_timeout) {
1097
1098 spin_lock_irqsave(&uap->port.lock, flags);
1099 pl011_dma_rx_stop(uap);
c25a1ad7 1100 uap->im |= UART011_RXIM;
9f25bc51 1101 pl011_write(uap->im, uap, REG_IMSC);
cb06ff10
CM		 1102 spin_unlock_irqrestore(&uap->port.lock, flags);
1103
1104 uap->dmarx.running = false;
1105 dmaengine_terminate_all(rxchan);
1106 del_timer(&uap->dmarx.timer);
1107 } else {
1108 mod_timer(&uap->dmarx.timer,
1109 jiffies + msecs_to_jiffies(uap->dmarx.poll_rate));
1110 }
1111}
1112
68b65f73
RK		 1113static void pl011_dma_startup(struct uart_amba_port *uap)
1114{
ead76f32
LW		 1115 int ret;
1116
1c9be310
JRO		 1117 if (!uap->dma_probed)
1118 pl011_dma_probe(uap);
1119
68b65f73
RK		 1120 if (!uap->dmatx.chan)
1121 return;
1122
4c0be45b 1123 uap->dmatx.buf = kmalloc(PL011_DMA_BUFFER_SIZE, GFP_KERNEL | __GFP_DMA);
68b65f73
RK		 1124 if (!uap->dmatx.buf) {
1125 dev_err(uap->port.dev, "no memory for DMA TX buffer\n");
1126 uap->port.fifosize = uap->fifosize;
1127 return;
1128 }
1129
1130 sg_init_one(&uap->dmatx.sg, uap->dmatx.buf, PL011_DMA_BUFFER_SIZE);
1131
1132 /* The DMA buffer is now the FIFO the TTY subsystem can use */
1133 uap->port.fifosize = PL011_DMA_BUFFER_SIZE;
ead76f32
LW		 1134 uap->using_tx_dma = true;
1135
1136 if (!uap->dmarx.chan)
1137 goto skip_rx;
1138
1139 /* Allocate and map DMA RX buffers */
1140 ret = pl011_sgbuf_init(uap->dmarx.chan, &uap->dmarx.sgbuf_a,
1141 DMA_FROM_DEVICE);
1142 if (ret) {
1143 dev_err(uap->port.dev, "failed to init DMA %s: %d\n",
1144 "RX buffer A", ret);
1145 goto skip_rx;
1146 }
68b65f73 1147
ead76f32
LW		 1148 ret = pl011_sgbuf_init(uap->dmarx.chan, &uap->dmarx.sgbuf_b,
1149 DMA_FROM_DEVICE);
1150 if (ret) {
1151 dev_err(uap->port.dev, "failed to init DMA %s: %d\n",
1152 "RX buffer B", ret);
1153 pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_a,
1154 DMA_FROM_DEVICE);
1155 goto skip_rx;
1156 }
1157
1158 uap->using_rx_dma = true;
68b65f73 1159
ead76f32 1160skip_rx:
68b65f73
RK		 1161 /* Turn on DMA error (RX/TX will be enabled on demand) */
1162 uap->dmacr |= UART011_DMAONERR;
9f25bc51 1163 pl011_write(uap->dmacr, uap, REG_DMACR);
38d62436
RK		 1164
1165 /*
1166 * ST Micro variants has some specific dma burst threshold
1167 * compensation. Set this to 16 bytes, so burst will only
1168 * be issued above/below 16 bytes.
1169 */
1170 if (uap->vendor->dma_threshold)
75836339 1171 pl011_write(ST_UART011_DMAWM_RX_16 | ST_UART011_DMAWM_TX_16,
9f25bc51 1172 uap, REG_ST_DMAWM);
ead76f32
LW		 1173
1174 if (uap->using_rx_dma) {
1175 if (pl011_dma_rx_trigger_dma(uap))
1176 dev_dbg(uap->port.dev, "could not trigger initial "
1177 "RX DMA job, fall back to interrupt mode\n");
cb06ff10 1178 if (uap->dmarx.poll_rate) {
f7f73096 1179 timer_setup(&uap->dmarx.timer, pl011_dma_rx_poll, 0);
cb06ff10
CM		 1180 mod_timer(&uap->dmarx.timer,
1181 jiffies +
1182 msecs_to_jiffies(uap->dmarx.poll_rate));
1183 uap->dmarx.last_residue = PL011_DMA_BUFFER_SIZE;
1184 uap->dmarx.last_jiffies = jiffies;
1185 }
ead76f32 1186 }
68b65f73
RK		 1187}
1188
1189static void pl011_dma_shutdown(struct uart_amba_port *uap)
1190{
ead76f32 1191 if (!(uap->using_tx_dma || uap->using_rx_dma))
68b65f73
RK		 1192 return;
1193
1194 /* Disable RX and TX DMA */
0e125a5f 1195 while (pl011_read(uap, REG_FR) & uap->vendor->fr_busy)
2f2fd089 1196 cpu_relax();
68b65f73
RK		 1197
1198 spin_lock_irq(&uap->port.lock);
1199 uap->dmacr &= ~(UART011_DMAONERR | UART011_RXDMAE | UART011_TXDMAE);
9f25bc51 1200 pl011_write(uap->dmacr, uap, REG_DMACR);
68b65f73
RK		 1201 spin_unlock_irq(&uap->port.lock);
1202
ead76f32
LW		 1203 if (uap->using_tx_dma) {
1204 /* In theory, this should already be done by pl011_dma_flush_buffer */
1205 dmaengine_terminate_all(uap->dmatx.chan);
1206 if (uap->dmatx.queued) {
1207 dma_unmap_sg(uap->dmatx.chan->device->dev, &uap->dmatx.sg, 1,
1208 DMA_TO_DEVICE);
1209 uap->dmatx.queued = false;
1210 }
1211
1212 kfree(uap->dmatx.buf);
1213 uap->using_tx_dma = false;
68b65f73
RK		 1214 }
1215
ead76f32
LW		 1216 if (uap->using_rx_dma) {
1217 dmaengine_terminate_all(uap->dmarx.chan);
1218 /* Clean up the RX DMA */
1219 pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_a, DMA_FROM_DEVICE);
1220 pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_b, DMA_FROM_DEVICE);
cb06ff10
CM		 1221 if (uap->dmarx.poll_rate)
1222 del_timer_sync(&uap->dmarx.timer);
ead76f32
LW		 1223 uap->using_rx_dma = false;
1224 }
1225}
68b65f73 1226
ead76f32
LW		 1227static inline bool pl011_dma_rx_available(struct uart_amba_port *uap)
1228{
1229 return uap->using_rx_dma;
68b65f73
RK		 1230}
1231
ead76f32
LW		 1232static inline bool pl011_dma_rx_running(struct uart_amba_port *uap)
1233{
1234 return uap->using_rx_dma && uap->dmarx.running;
1235}
1236
68b65f73
RK		 1237#else
1238/* Blank functions if the DMA engine is not available */
1c9be310 1239static inline void pl011_dma_probe(struct uart_amba_port *uap)
68b65f73
RK		 1240{
1241}
1242
1243static inline void pl011_dma_remove(struct uart_amba_port *uap)
1244{
1245}
1246
1247static inline void pl011_dma_startup(struct uart_amba_port *uap)
1248{
1249}
1250
1251static inline void pl011_dma_shutdown(struct uart_amba_port *uap)
1252{
1253}
1254
1255static inline bool pl011_dma_tx_irq(struct uart_amba_port *uap)
1256{
1257 return false;
1258}
1259
1260static inline void pl011_dma_tx_stop(struct uart_amba_port *uap)
1261{
1262}
1263
1264static inline bool pl011_dma_tx_start(struct uart_amba_port *uap)
1265{
1266 return false;
1267}
1268
ead76f32
LW		 1269static inline void pl011_dma_rx_irq(struct uart_amba_port *uap)
1270{
1271}
1272
1273static inline void pl011_dma_rx_stop(struct uart_amba_port *uap)
1274{
1275}
1276
1277static inline int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap)
1278{
1279 return -EIO;
1280}
1281
1282static inline bool pl011_dma_rx_available(struct uart_amba_port *uap)
1283{
1284 return false;
1285}
1286
1287static inline bool pl011_dma_rx_running(struct uart_amba_port *uap)
1288{
1289 return false;
1290}
1291
68b65f73
RK		 1292#define pl011_dma_flush_buffer NULL
1293#endif
1294
b129a8cc 1295static void pl011_stop_tx(struct uart_port *port)
1da177e4 1296{
a5820c24
DT		 1297 struct uart_amba_port *uap =
1298 container_of(port, struct uart_amba_port, port);
1da177e4
LT		 1299
1300 uap->im &= ~UART011_TXIM;
9f25bc51 1301 pl011_write(uap->im, uap, REG_IMSC);
68b65f73 1302 pl011_dma_tx_stop(uap);
1da177e4
LT		 1303}
1304
7d05587c 1305static bool pl011_tx_chars(struct uart_amba_port *uap, bool from_irq);
734745ca
DM		 1306
1307/* Start TX with programmed I/O only (no DMA) */
1308static void pl011_start_tx_pio(struct uart_amba_port *uap)
1309{
7d05587c
J		 1310 if (pl011_tx_chars(uap, false)) {
1311 uap->im |= UART011_TXIM;
1312 pl011_write(uap->im, uap, REG_IMSC);
1313 }
734745ca
DM		 1314}
1315
b129a8cc 1316static void pl011_start_tx(struct uart_port *port)
1da177e4 1317{
a5820c24
DT		 1318 struct uart_amba_port *uap =
1319 container_of(port, struct uart_amba_port, port);
1da177e4 1320
734745ca
DM		 1321 if (!pl011_dma_tx_start(uap))
1322 pl011_start_tx_pio(uap);
1da177e4
LT		 1323}
1324
1325static void pl011_stop_rx(struct uart_port *port)
1326{
a5820c24
DT		 1327 struct uart_amba_port *uap =
1328 container_of(port, struct uart_amba_port, port);
1da177e4
LT		 1329
1330 uap->im &= ~(UART011_RXIM|UART011_RTIM|UART011_FEIM|
1331 UART011_PEIM|UART011_BEIM|UART011_OEIM);
9f25bc51 1332 pl011_write(uap->im, uap, REG_IMSC);
ead76f32
LW		 1333
1334 pl011_dma_rx_stop(uap);
1da177e4
LT		 1335}
1336
1337static void pl011_enable_ms(struct uart_port *port)
1338{
a5820c24
DT		 1339 struct uart_amba_port *uap =
1340 container_of(port, struct uart_amba_port, port);
1da177e4
LT		 1341
1342 uap->im |= UART011_RIMIM|UART011_CTSMIM|UART011_DCDMIM|UART011_DSRMIM;
9f25bc51 1343 pl011_write(uap->im, uap, REG_IMSC);
1da177e4
LT		 1344}
1345
7d12e780 1346static void pl011_rx_chars(struct uart_amba_port *uap)
b83286bf
FE		 1347__releases(&uap->port.lock)
1348__acquires(&uap->port.lock)
1da177e4 1349{
29772c4e 1350 pl011_fifo_to_tty(uap);
1da177e4 1351
2389b272 1352 spin_unlock(&uap->port.lock);
2e124b4a 1353 tty_flip_buffer_push(&uap->port.state->port);
ead76f32
LW		 1354 /*
1355 * If we were temporarily out of DMA mode for a while,
1356 * attempt to switch back to DMA mode again.
1357 */
1358 if (pl011_dma_rx_available(uap)) {
1359 if (pl011_dma_rx_trigger_dma(uap)) {
1360 dev_dbg(uap->port.dev, "could not trigger RX DMA job "
1361 "fall back to interrupt mode again\n");
1362 uap->im |= UART011_RXIM;
9f25bc51 1363 pl011_write(uap->im, uap, REG_IMSC);
cb06ff10 1364 } else {
89fa28db 1365#ifdef CONFIG_DMA_ENGINE
cb06ff10
CM		 1366 /* Start Rx DMA poll */
1367 if (uap->dmarx.poll_rate) {
1368 uap->dmarx.last_jiffies = jiffies;
1369 uap->dmarx.last_residue = PL011_DMA_BUFFER_SIZE;
1370 mod_timer(&uap->dmarx.timer,
1371 jiffies +
1372 msecs_to_jiffies(uap->dmarx.poll_rate));
1373 }
89fa28db 1374#endif
cb06ff10 1375 }
ead76f32 1376 }
2389b272 1377 spin_lock(&uap->port.lock);
1da177e4
LT		 1378}
1379
1e84d223
DM		 1380static bool pl011_tx_char(struct uart_amba_port *uap, unsigned char c,
1381 bool from_irq)
734745ca 1382{
1e84d223 1383 if (unlikely(!from_irq) &&
9f25bc51 1384 pl011_read(uap, REG_FR) & UART01x_FR_TXFF)
1e84d223
DM		 1385 return false; /* unable to transmit character */
1386
9f25bc51 1387 pl011_write(c, uap, REG_DR);
734745ca
DM		 1388 uap->port.icount.tx++;
1389
1e84d223 1390 return true;
734745ca
DM		 1391}
1392
7d05587c
J		 1393/* Returns true if tx interrupts have to be (kept) enabled */
1394static bool pl011_tx_chars(struct uart_amba_port *uap, bool from_irq)
1da177e4 1395{
ebd2c8f6 1396 struct circ_buf *xmit = &uap->port.state->xmit;
1e84d223 1397 int count = uap->fifosize >> 1;
734745ca 1398
1da177e4 1399 if (uap->port.x_char) {
1e84d223 1400 if (!pl011_tx_char(uap, uap->port.x_char, from_irq))
7d05587c 1401 return true;
1da177e4 1402 uap->port.x_char = 0;
734745ca 1403 --count;
1da177e4
LT		 1404 }
1405 if (uart_circ_empty(xmit) || uart_tx_stopped(&uap->port)) {
b129a8cc 1406 pl011_stop_tx(&uap->port);
7d05587c 1407 return false;
1da177e4
LT		 1408 }
1409
68b65f73
RK		 1410 /* If we are using DMA mode, try to send some characters. */
1411 if (pl011_dma_tx_irq(uap))
7d05587c 1412 return true;
68b65f73 1413
1e84d223
DM		 1414 do {
1415 if (likely(from_irq) && count-- == 0)
1da177e4 1416 break;
1e84d223
DM		 1417
1418 if (!pl011_tx_char(uap, xmit->buf[xmit->tail], from_irq))
1419 break;
1420
1421 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1422 } while (!uart_circ_empty(xmit));
1da177e4
LT		 1423
1424 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1425 uart_write_wakeup(&uap->port);
1426
7d05587c 1427 if (uart_circ_empty(xmit)) {
b129a8cc 1428 pl011_stop_tx(&uap->port);
7d05587c
J		 1429 return false;
1430 }
1431 return true;
1da177e4
LT		 1432}
1433
1434static void pl011_modem_status(struct uart_amba_port *uap)
1435{
1436 unsigned int status, delta;
1437
9f25bc51 1438 status = pl011_read(uap, REG_FR) & UART01x_FR_MODEM_ANY;
1da177e4
LT		 1439
1440 delta = status ^ uap->old_status;
1441 uap->old_status = status;
1442
1443 if (!delta)
1444 return;
1445
1446 if (delta & UART01x_FR_DCD)
1447 uart_handle_dcd_change(&uap->port, status & UART01x_FR_DCD);
1448
0e125a5f 1449 if (delta & uap->vendor->fr_dsr)
1da177e4
LT		 1450 uap->port.icount.dsr++;
1451
0e125a5f
SG		 1452 if (delta & uap->vendor->fr_cts)
1453 uart_handle_cts_change(&uap->port,
1454 status & uap->vendor->fr_cts);
1da177e4 1455
bdc04e31 1456 wake_up_interruptible(&uap->port.state->port.delta_msr_wait);
1da177e4
LT		 1457}
1458
9c4ef4b0
AP		 1459static void check_apply_cts_event_workaround(struct uart_amba_port *uap)
1460{
1461 unsigned int dummy_read;
1462
1463 if (!uap->vendor->cts_event_workaround)
1464 return;
1465
1466 /* workaround to make sure that all bits are unlocked.. */
9f25bc51 1467 pl011_write(0x00, uap, REG_ICR);
9c4ef4b0
AP		 1468
1469 /*
1470 * WA: introduce 26ns(1 uart clk) delay before W1C;
1471 * single apb access will incur 2 pclk(133.12Mhz) delay,
1472 * so add 2 dummy reads
1473 */
9f25bc51
RK		 1474 dummy_read = pl011_read(uap, REG_ICR);
1475 dummy_read = pl011_read(uap, REG_ICR);
9c4ef4b0
AP		 1476}
1477
7d12e780 1478static irqreturn_t pl011_int(int irq, void *dev_id)
1da177e4
LT		 1479{
1480 struct uart_amba_port *uap = dev_id;
963cc981 1481 unsigned long flags;
1da177e4
LT		 1482 unsigned int status, pass_counter = AMBA_ISR_PASS_LIMIT;
1483 int handled = 0;
1484
963cc981 1485 spin_lock_irqsave(&uap->port.lock, flags);
d3a96c94 1486 status = pl011_read(uap, REG_RIS) & uap->im;
1da177e4
LT		 1487 if (status) {
1488 do {
9c4ef4b0 1489 check_apply_cts_event_workaround(uap);
f11c9841 1490
75836339
RK		 1491 pl011_write(status & ~(UART011_TXIS|UART011_RTIS|
1492 UART011_RXIS),
9f25bc51 1493 uap, REG_ICR);
1da177e4 1494
ead76f32
LW		 1495 if (status & (UART011_RTIS|UART011_RXIS)) {
1496 if (pl011_dma_rx_running(uap))
1497 pl011_dma_rx_irq(uap);
1498 else
1499 pl011_rx_chars(uap);
1500 }
1da177e4
LT		 1501 if (status & (UART011_DSRMIS|UART011_DCDMIS|
1502 UART011_CTSMIS|UART011_RIMIS))
1503 pl011_modem_status(uap);
1e84d223
DM		 1504 if (status & UART011_TXIS)
1505 pl011_tx_chars(uap, true);
1da177e4 1506
4fd0690b 1507 if (pass_counter-- == 0)
1da177e4
LT		 1508 break;
1509
d3a96c94 1510 status = pl011_read(uap, REG_RIS) & uap->im;
1da177e4
LT		 1511 } while (status != 0);
1512 handled = 1;
1513 }
1514
963cc981 1515 spin_unlock_irqrestore(&uap->port.lock, flags);
1da177e4
LT		 1516
1517 return IRQ_RETVAL(handled);
1518}
1519
e643f87f 1520static unsigned int pl011_tx_empty(struct uart_port *port)
1da177e4 1521{
a5820c24
DT		 1522 struct uart_amba_port *uap =
1523 container_of(port, struct uart_amba_port, port);
d8a4995b
CC		 1524
1525 /* Allow feature register bits to be inverted to work around errata */
1526 unsigned int status = pl011_read(uap, REG_FR) ^ uap->vendor->inv_fr;
1527
0e125a5f
SG		 1528 return status & (uap->vendor->fr_busy | UART01x_FR_TXFF) ?
1529 0 : TIOCSER_TEMT;
1da177e4
LT		 1530}
1531
e643f87f 1532static unsigned int pl011_get_mctrl(struct uart_port *port)
1da177e4 1533{
a5820c24
DT		 1534 struct uart_amba_port *uap =
1535 container_of(port, struct uart_amba_port, port);
1da177e4 1536 unsigned int result = 0;
9f25bc51 1537 unsigned int status = pl011_read(uap, REG_FR);
1da177e4 1538
5159f407 1539#define TIOCMBIT(uartbit, tiocmbit) \
1da177e4
LT		 1540 if (status & uartbit) \
1541 result |= tiocmbit
1542
5159f407 1543 TIOCMBIT(UART01x_FR_DCD, TIOCM_CAR);
0e125a5f
SG		 1544 TIOCMBIT(uap->vendor->fr_dsr, TIOCM_DSR);
1545 TIOCMBIT(uap->vendor->fr_cts, TIOCM_CTS);
1546 TIOCMBIT(uap->vendor->fr_ri, TIOCM_RNG);
5159f407 1547#undef TIOCMBIT
1da177e4
LT		 1548 return result;
1549}
1550
1551static void pl011_set_mctrl(struct uart_port *port, unsigned int mctrl)
1552{
a5820c24
DT		 1553 struct uart_amba_port *uap =
1554 container_of(port, struct uart_amba_port, port);
1da177e4
LT		 1555 unsigned int cr;
1556
9f25bc51 1557 cr = pl011_read(uap, REG_CR);
1da177e4 1558
5159f407 1559#define TIOCMBIT(tiocmbit, uartbit) \
1da177e4
LT		 1560 if (mctrl & tiocmbit) \
1561 cr |= uartbit; \
1562 else \
1563 cr &= ~uartbit
1564
5159f407
JS		 1565 TIOCMBIT(TIOCM_RTS, UART011_CR_RTS);
1566 TIOCMBIT(TIOCM_DTR, UART011_CR_DTR);
1567 TIOCMBIT(TIOCM_OUT1, UART011_CR_OUT1);
1568 TIOCMBIT(TIOCM_OUT2, UART011_CR_OUT2);
1569 TIOCMBIT(TIOCM_LOOP, UART011_CR_LBE);
3b43816f 1570
2a76fa28 1571 if (port->status & UPSTAT_AUTORTS) {
3b43816f
RV		 1572 /* We need to disable auto-RTS if we want to turn RTS off */
1573 TIOCMBIT(TIOCM_RTS, UART011_CR_RTSEN);
1574 }
5159f407 1575#undef TIOCMBIT
1da177e4 1576
9f25bc51 1577 pl011_write(cr, uap, REG_CR);
1da177e4
LT		 1578}
1579
1580static void pl011_break_ctl(struct uart_port *port, int break_state)
1581{
a5820c24
DT		 1582 struct uart_amba_port *uap =
1583 container_of(port, struct uart_amba_port, port);
1da177e4
LT		 1584 unsigned long flags;
1585 unsigned int lcr_h;
1586
1587 spin_lock_irqsave(&uap->port.lock, flags);
e4df9a80 1588 lcr_h = pl011_read(uap, REG_LCRH_TX);
1da177e4
LT		 1589 if (break_state == -1)
1590 lcr_h |= UART01x_LCRH_BRK;
1591 else
1592 lcr_h &= ~UART01x_LCRH_BRK;
e4df9a80 1593 pl011_write(lcr_h, uap, REG_LCRH_TX);
1da177e4
LT		 1594 spin_unlock_irqrestore(&uap->port.lock, flags);
1595}
1596
84b5ae15 1597#ifdef CONFIG_CONSOLE_POLL
5c8124a0
AV		 1598
1599static void pl011_quiesce_irqs(struct uart_port *port)
1600{
a5820c24
DT		 1601 struct uart_amba_port *uap =
1602 container_of(port, struct uart_amba_port, port);
5c8124a0 1603
9f25bc51 1604 pl011_write(pl011_read(uap, REG_MIS), uap, REG_ICR);
5c8124a0
AV		 1605 /*
1606 * There is no way to clear TXIM as this is "ready to transmit IRQ", so
1607 * we simply mask it. start_tx() will unmask it.
1608 *
1609 * Note we can race with start_tx(), and if the race happens, the
1610 * polling user might get another interrupt just after we clear it.
1611 * But it should be OK and can happen even w/o the race, e.g.
1612 * controller immediately got some new data and raised the IRQ.
1613 *
1614 * And whoever uses polling routines assumes that it manages the device
1615 * (including tx queue), so we're also fine with start_tx()'s caller
1616 * side.
1617 */
9f25bc51
RK		 1618 pl011_write(pl011_read(uap, REG_IMSC) & ~UART011_TXIM, uap,
1619 REG_IMSC);
5c8124a0
AV		 1620}
1621
e643f87f 1622static int pl011_get_poll_char(struct uart_port *port)
84b5ae15 1623{
a5820c24
DT		 1624 struct uart_amba_port *uap =
1625 container_of(port, struct uart_amba_port, port);
84b5ae15
JW		 1626 unsigned int status;
1627
5c8124a0
AV		 1628 /*
1629 * The caller might need IRQs lowered, e.g. if used with KDB NMI
1630 * debugger.
1631 */
1632 pl011_quiesce_irqs(port);
1633
9f25bc51 1634 status = pl011_read(uap, REG_FR);
f5316b4a
JW		 1635 if (status & UART01x_FR_RXFE)
1636 return NO_POLL_CHAR;
84b5ae15 1637
9f25bc51 1638 return pl011_read(uap, REG_DR);
84b5ae15
JW		 1639}
1640
e643f87f 1641static void pl011_put_poll_char(struct uart_port *port,
84b5ae15
JW		 1642 unsigned char ch)
1643{
a5820c24
DT		 1644 struct uart_amba_port *uap =
1645 container_of(port, struct uart_amba_port, port);
84b5ae15 1646
9f25bc51 1647 while (pl011_read(uap, REG_FR) & UART01x_FR_TXFF)
2f2fd089 1648 cpu_relax();
84b5ae15 1649
9f25bc51 1650 pl011_write(ch, uap, REG_DR);
84b5ae15
JW		 1651}
1652
1653#endif /* CONFIG_CONSOLE_POLL */
1654
b3564c2c 1655static int pl011_hwinit(struct uart_port *port)
1da177e4 1656{
a5820c24
DT		 1657 struct uart_amba_port *uap =
1658 container_of(port, struct uart_amba_port, port);
1da177e4
LT		 1659 int retval;
1660
78d80c5a 1661 /* Optionaly enable pins to be muxed in and configured */
2b996fc5 1662 pinctrl_pm_select_default_state(port->dev);
78d80c5a 1663
1da177e4
LT		 1664 /*
1665 * Try to enable the clock producer.
1666 */
1c4c4394 1667 retval = clk_prepare_enable(uap->clk);
1da177e4 1668 if (retval)
7f6d942a 1669 return retval;
1da177e4
LT		 1670
1671 uap->port.uartclk = clk_get_rate(uap->clk);
1672
9b96fbac 1673 /* Clear pending error and receive interrupts */
75836339
RK		 1674 pl011_write(UART011_OEIS | UART011_BEIS | UART011_PEIS |
1675 UART011_FEIS | UART011_RTIS | UART011_RXIS,
9f25bc51 1676 uap, REG_ICR);
9b96fbac 1677
b3564c2c
AV		 1678 /*
1679 * Save interrupts enable mask, and enable RX interrupts in case if
1680 * the interrupt is used for NMI entry.
1681 */
9f25bc51
RK		 1682 uap->im = pl011_read(uap, REG_IMSC);
1683 pl011_write(UART011_RTIM | UART011_RXIM, uap, REG_IMSC);
b3564c2c 1684
574de559 1685 if (dev_get_platdata(uap->port.dev)) {
b3564c2c
AV		 1686 struct amba_pl011_data *plat;
1687
574de559 1688 plat = dev_get_platdata(uap->port.dev);
b3564c2c
AV		 1689 if (plat->init)
1690 plat->init();
1691 }
1692 return 0;
b3564c2c
AV		 1693}
1694
7fe9a5a9
RK		 1695static bool pl011_split_lcrh(const struct uart_amba_port *uap)
1696{
e4df9a80
RK		 1697 return pl011_reg_to_offset(uap, REG_LCRH_RX) !=
1698 pl011_reg_to_offset(uap, REG_LCRH_TX);
7fe9a5a9
RK		 1699}
1700
b60f2f66
JM		 1701static void pl011_write_lcr_h(struct uart_amba_port *uap, unsigned int lcr_h)
1702{
e4df9a80 1703 pl011_write(lcr_h, uap, REG_LCRH_RX);
7fe9a5a9 1704 if (pl011_split_lcrh(uap)) {
b60f2f66
JM		 1705 int i;
1706 /*
1707 * Wait 10 PCLKs before writing LCRH_TX register,
1708 * to get this delay write read only register 10 times
1709 */
1710 for (i = 0; i < 10; ++i)
9f25bc51 1711 pl011_write(0xff, uap, REG_MIS);
e4df9a80 1712 pl011_write(lcr_h, uap, REG_LCRH_TX);
b60f2f66
JM		 1713 }
1714}
1715
867b8e8e
AP		 1716static int pl011_allocate_irq(struct uart_amba_port *uap)
1717{
9f25bc51 1718 pl011_write(uap->im, uap, REG_IMSC);
867b8e8e
AP		 1719
1720 return request_irq(uap->port.irq, pl011_int, 0, "uart-pl011", uap);
1721}
1722
1723/*
1724 * Enable interrupts, only timeouts when using DMA
1725 * if initial RX DMA job failed, start in interrupt mode
1726 * as well.
1727 */
1728static void pl011_enable_interrupts(struct uart_amba_port *uap)
1729{
1730 spin_lock_irq(&uap->port.lock);
1731
1732 /* Clear out any spuriously appearing RX interrupts */
9f25bc51 1733 pl011_write(UART011_RTIS | UART011_RXIS, uap, REG_ICR);
867b8e8e
AP		 1734 uap->im = UART011_RTIM;
1735 if (!pl011_dma_rx_running(uap))
1736 uap->im |= UART011_RXIM;
9f25bc51 1737 pl011_write(uap->im, uap, REG_IMSC);
867b8e8e
AP		 1738 spin_unlock_irq(&uap->port.lock);
1739}
1740
b3564c2c
AV		 1741static int pl011_startup(struct uart_port *port)
1742{
a5820c24
DT		 1743 struct uart_amba_port *uap =
1744 container_of(port, struct uart_amba_port, port);
734745ca 1745 unsigned int cr;
b3564c2c
AV		 1746 int retval;
1747
1748 retval = pl011_hwinit(port);
1749 if (retval)
1750 goto clk_dis;
1751
867b8e8e 1752 retval = pl011_allocate_irq(uap);
1da177e4
LT		 1753 if (retval)
1754 goto clk_dis;
1755
9f25bc51 1756 pl011_write(uap->vendor->ifls, uap, REG_IFLS);
1da177e4 1757
734745ca 1758 spin_lock_irq(&uap->port.lock);
570d2910 1759
d8d8ffa4
SKS		 1760 /* restore RTS and DTR */
1761 cr = uap->old_cr & (UART011_CR_RTS | UART011_CR_DTR);
1762 cr |= UART01x_CR_UARTEN | UART011_CR_RXE | UART011_CR_TXE;
9f25bc51 1763 pl011_write(cr, uap, REG_CR);
1da177e4 1764
fe433907
JM		 1765 spin_unlock_irq(&uap->port.lock);
1766
1da177e4
LT		 1767 /*
1768 * initialise the old status of the modem signals
1769 */
9f25bc51 1770 uap->old_status = pl011_read(uap, REG_FR) & UART01x_FR_MODEM_ANY;
1da177e4 1771
68b65f73
RK		 1772 /* Startup DMA */
1773 pl011_dma_startup(uap);
1774
867b8e8e 1775 pl011_enable_interrupts(uap);
1da177e4
LT		 1776
1777 return 0;
1778
1779 clk_dis:
1c4c4394 1780 clk_disable_unprepare(uap->clk);
1da177e4
LT		 1781 return retval;
1782}
1783
0dd1e247
AP		 1784static int sbsa_uart_startup(struct uart_port *port)
1785{
1786 struct uart_amba_port *uap =
1787 container_of(port, struct uart_amba_port, port);
1788 int retval;
1789
1790 retval = pl011_hwinit(port);
1791 if (retval)
1792 return retval;
1793
1794 retval = pl011_allocate_irq(uap);
1795 if (retval)
1796 return retval;
1797
1798 /* The SBSA UART does not support any modem status lines. */
1799 uap->old_status = 0;
1800
1801 pl011_enable_interrupts(uap);
1802
1803 return 0;
1804}
1805
ec489aa8
LW		 1806static void pl011_shutdown_channel(struct uart_amba_port *uap,
1807 unsigned int lcrh)
1808{
f11c9841 1809 unsigned long val;
ec489aa8 1810
b2a4e24c 1811 val = pl011_read(uap, lcrh);
f11c9841 1812 val &= ~(UART01x_LCRH_BRK | UART01x_LCRH_FEN);
b2a4e24c 1813 pl011_write(val, uap, lcrh);
ec489aa8
LW		 1814}
1815
95166a3f
AP		 1816/*
1817 * disable the port. It should not disable RTS and DTR.
1818 * Also RTS and DTR state should be preserved to restore
1819 * it during startup().
1820 */
1821static void pl011_disable_uart(struct uart_amba_port *uap)
1da177e4 1822{
d8d8ffa4 1823 unsigned int cr;
1da177e4 1824
2a76fa28 1825 uap->port.status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS);
fe433907 1826 spin_lock_irq(&uap->port.lock);
9f25bc51 1827 cr = pl011_read(uap, REG_CR);
d8d8ffa4
SKS		 1828 uap->old_cr = cr;
1829 cr &= UART011_CR_RTS | UART011_CR_DTR;
1830 cr |= UART01x_CR_UARTEN | UART011_CR_TXE;
9f25bc51 1831 pl011_write(cr, uap, REG_CR);
fe433907 1832 spin_unlock_irq(&uap->port.lock);
1da177e4
LT		 1833
1834 /*
1835 * disable break condition and fifos
1836 */
e4df9a80 1837 pl011_shutdown_channel(uap, REG_LCRH_RX);
7fe9a5a9 1838 if (pl011_split_lcrh(uap))
e4df9a80 1839 pl011_shutdown_channel(uap, REG_LCRH_TX);
95166a3f
AP		 1840}
1841
1842static void pl011_disable_interrupts(struct uart_amba_port *uap)
1843{
1844 spin_lock_irq(&uap->port.lock);
1845
1846 /* mask all interrupts and clear all pending ones */
1847 uap->im = 0;
9f25bc51
RK		 1848 pl011_write(uap->im, uap, REG_IMSC);
1849 pl011_write(0xffff, uap, REG_ICR);
95166a3f
AP		 1850
1851 spin_unlock_irq(&uap->port.lock);
1852}
1853
1854static void pl011_shutdown(struct uart_port *port)
1855{
1856 struct uart_amba_port *uap =
1857 container_of(port, struct uart_amba_port, port);
1858
1859 pl011_disable_interrupts(uap);
1860
1861 pl011_dma_shutdown(uap);
1862
1863 free_irq(uap->port.irq, uap);
1864
1865 pl011_disable_uart(uap);
1da177e4
LT		 1866
1867 /*
1868 * Shut down the clock producer
1869 */
1c4c4394 1870 clk_disable_unprepare(uap->clk);
78d80c5a 1871 /* Optionally let pins go into sleep states */
2b996fc5 1872 pinctrl_pm_select_sleep_state(port->dev);
c16d51a3 1873
574de559 1874 if (dev_get_platdata(uap->port.dev)) {
c16d51a3
SKS		 1875 struct amba_pl011_data *plat;
1876
574de559 1877 plat = dev_get_platdata(uap->port.dev);
c16d51a3
SKS		 1878 if (plat->exit)
1879 plat->exit();
1880 }
1881
36f339d1
PH		 1882 if (uap->port.ops->flush_buffer)
1883 uap->port.ops->flush_buffer(port);
1da177e4
LT		 1884}
1885
0dd1e247
AP		 1886static void sbsa_uart_shutdown(struct uart_port *port)
1887{
1888 struct uart_amba_port *uap =
1889 container_of(port, struct uart_amba_port, port);
1890
1891 pl011_disable_interrupts(uap);
1892
1893 free_irq(uap->port.irq, uap);
1894
1895 if (uap->port.ops->flush_buffer)
1896 uap->port.ops->flush_buffer(port);
1897}
1898
ef5a9358
AP		 1899static void
1900pl011_setup_status_masks(struct uart_port *port, struct ktermios *termios)
1901{
1902 port->read_status_mask = UART011_DR_OE | 255;
1903 if (termios->c_iflag & INPCK)
1904 port->read_status_mask |= UART011_DR_FE | UART011_DR_PE;
1905 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
1906 port->read_status_mask |= UART011_DR_BE;
1907
1908 /*
1909 * Characters to ignore
1910 */
1911 port->ignore_status_mask = 0;
1912 if (termios->c_iflag & IGNPAR)
1913 port->ignore_status_mask |= UART011_DR_FE | UART011_DR_PE;
1914 if (termios->c_iflag & IGNBRK) {
1915 port->ignore_status_mask |= UART011_DR_BE;
1916 /*
1917 * If we're ignoring parity and break indicators,
1918 * ignore overruns too (for real raw support).
1919 */
1920 if (termios->c_iflag & IGNPAR)
1921 port->ignore_status_mask |= UART011_DR_OE;
1922 }
1923
1924 /*
1925 * Ignore all characters if CREAD is not set.
1926 */
1927 if ((termios->c_cflag & CREAD) == 0)
1928 port->ignore_status_mask |= UART_DUMMY_DR_RX;
1929}
1930
1da177e4 1931static void
606d099c
AC		 1932pl011_set_termios(struct uart_port *port, struct ktermios *termios,
1933 struct ktermios *old)
1da177e4 1934{
a5820c24
DT		 1935 struct uart_amba_port *uap =
1936 container_of(port, struct uart_amba_port, port);
1da177e4
LT		 1937 unsigned int lcr_h, old_cr;
1938 unsigned long flags;
c19f12b5
RK		 1939 unsigned int baud, quot, clkdiv;
1940
1941 if (uap->vendor->oversampling)
1942 clkdiv = 8;
1943 else
1944 clkdiv = 16;
1da177e4
LT		 1945
1946 /*
1947 * Ask the core to calculate the divisor for us.
1948 */
ac3e3fb4 1949 baud = uart_get_baud_rate(port, termios, old, 0,
c19f12b5 1950 port->uartclk / clkdiv);
89fa28db 1951#ifdef CONFIG_DMA_ENGINE
cb06ff10
CM		 1952 /*
1953 * Adjust RX DMA polling rate with baud rate if not specified.
1954 */
1955 if (uap->dmarx.auto_poll_rate)
1956 uap->dmarx.poll_rate = DIV_ROUND_UP(10000000, baud);
89fa28db 1957#endif
ac3e3fb4
LW		 1958
1959 if (baud > port->uartclk/16)
1960 quot = DIV_ROUND_CLOSEST(port->uartclk * 8, baud);
1961 else
1962 quot = DIV_ROUND_CLOSEST(port->uartclk * 4, baud);
1da177e4
LT		 1963
1964 switch (termios->c_cflag & CSIZE) {
1965 case CS5:
1966 lcr_h = UART01x_LCRH_WLEN_5;
1967 break;
1968 case CS6:
1969 lcr_h = UART01x_LCRH_WLEN_6;
1970 break;
1971 case CS7:
1972 lcr_h = UART01x_LCRH_WLEN_7;
1973 break;
1974 default: // CS8
1975 lcr_h = UART01x_LCRH_WLEN_8;
1976 break;
1977 }
1978 if (termios->c_cflag & CSTOPB)
1979 lcr_h |= UART01x_LCRH_STP2;
1980 if (termios->c_cflag & PARENB) {
1981 lcr_h |= UART01x_LCRH_PEN;
1982 if (!(termios->c_cflag & PARODD))
1983 lcr_h |= UART01x_LCRH_EPS;
bb70002c
ES		 1984 if (termios->c_cflag & CMSPAR)
1985 lcr_h |= UART011_LCRH_SPS;
1da177e4 1986 }
ffca2b11 1987 if (uap->fifosize > 1)
1da177e4
LT		 1988 lcr_h |= UART01x_LCRH_FEN;
1989
1990 spin_lock_irqsave(&port->lock, flags);
1991
1992 /*
1993 * Update the per-port timeout.
1994 */
1995 uart_update_timeout(port, termios->c_cflag, baud);
1996
ef5a9358 1997 pl011_setup_status_masks(port, termios);
1da177e4
LT		 1998
1999 if (UART_ENABLE_MS(port, termios->c_cflag))
2000 pl011_enable_ms(port);
2001
2002 /* first, disable everything */
9f25bc51
RK		 2003 old_cr = pl011_read(uap, REG_CR);
2004 pl011_write(0, uap, REG_CR);
1da177e4 2005
3b43816f
RV		 2006 if (termios->c_cflag & CRTSCTS) {
2007 if (old_cr & UART011_CR_RTS)
2008 old_cr |= UART011_CR_RTSEN;
2009
2010 old_cr |= UART011_CR_CTSEN;
2a76fa28 2011 port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS;
3b43816f
RV		 2012 } else {
2013 old_cr &= ~(UART011_CR_CTSEN | UART011_CR_RTSEN);
2a76fa28 2014 port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS);
3b43816f
RV		 2015 }
2016
c19f12b5
RK		 2017 if (uap->vendor->oversampling) {
2018 if (baud > port->uartclk / 16)
ac3e3fb4
LW		 2019 old_cr |= ST_UART011_CR_OVSFACT;
2020 else
2021 old_cr &= ~ST_UART011_CR_OVSFACT;
2022 }
2023
c5dd553b
LW		 2024 /*
2025 * Workaround for the ST Micro oversampling variants to
2026 * increase the bitrate slightly, by lowering the divisor,
2027 * to avoid delayed sampling of start bit at high speeds,
2028 * else we see data corruption.
2029 */
2030 if (uap->vendor->oversampling) {
2031 if ((baud >= 3000000) && (baud < 3250000) && (quot > 1))
2032 quot -= 1;
2033 else if ((baud > 3250000) && (quot > 2))
2034 quot -= 2;
2035 }
1da177e4 2036 /* Set baud rate */
9f25bc51
RK		 2037 pl011_write(quot & 0x3f, uap, REG_FBRD);
2038 pl011_write(quot >> 6, uap, REG_IBRD);
1da177e4
LT		 2039
2040 /*
2041 * ----------v----------v----------v----------v-----
e4df9a80 2042 * NOTE: REG_LCRH_TX and REG_LCRH_RX MUST BE WRITTEN AFTER
9f25bc51 2043 * REG_FBRD & REG_IBRD.
1da177e4
LT		 2044 * ----------^----------^----------^----------^-----
2045 */
b60f2f66 2046 pl011_write_lcr_h(uap, lcr_h);
9f25bc51 2047 pl011_write(old_cr, uap, REG_CR);
1da177e4
LT		 2048
2049 spin_unlock_irqrestore(&port->lock, flags);
2050}
2051
0dd1e247
AP		 2052static void
2053sbsa_uart_set_termios(struct uart_port *port, struct ktermios *termios,
2054 struct ktermios *old)
2055{
2056 struct uart_amba_port *uap =
2057 container_of(port, struct uart_amba_port, port);
2058 unsigned long flags;
2059
2060 tty_termios_encode_baud_rate(termios, uap->fixed_baud, uap->fixed_baud);
2061
2062 /* The SBSA UART only supports 8n1 without hardware flow control. */
2063 termios->c_cflag &= ~(CSIZE | CSTOPB | PARENB | PARODD);
2064 termios->c_cflag &= ~(CMSPAR | CRTSCTS);
2065 termios->c_cflag |= CS8 | CLOCAL;
2066
2067 spin_lock_irqsave(&port->lock, flags);
2068 uart_update_timeout(port, CS8, uap->fixed_baud);
2069 pl011_setup_status_masks(port, termios);
2070 spin_unlock_irqrestore(&port->lock, flags);
2071}
2072
1da177e4
LT		 2073static const char *pl011_type(struct uart_port *port)
2074{
a5820c24
DT		 2075 struct uart_amba_port *uap =
2076 container_of(port, struct uart_amba_port, port);
e8a7ba86 2077 return uap->port.type == PORT_AMBA ? uap->type : NULL;
1da177e4
LT		 2078}
2079
2080/*
2081 * Release the memory region(s) being used by 'port'
2082 */
e643f87f 2083static void pl011_release_port(struct uart_port *port)
1da177e4
LT		 2084{
2085 release_mem_region(port->mapbase, SZ_4K);
2086}
2087
2088/*
2089 * Request the memory region(s) being used by 'port'
2090 */
e643f87f 2091static int pl011_request_port(struct uart_port *port)
1da177e4
LT		 2092{
2093 return request_mem_region(port->mapbase, SZ_4K, "uart-pl011")
2094 != NULL ? 0 : -EBUSY;
2095}
2096
2097/*
2098 * Configure/autoconfigure the port.
2099 */
e643f87f 2100static void pl011_config_port(struct uart_port *port, int flags)
1da177e4
LT		 2101{
2102 if (flags & UART_CONFIG_TYPE) {
2103 port->type = PORT_AMBA;
e643f87f 2104 pl011_request_port(port);
1da177e4
LT		 2105 }
2106}
2107
2108/*
2109 * verify the new serial_struct (for TIOCSSERIAL).
2110 */
e643f87f 2111static int pl011_verify_port(struct uart_port *port, struct serial_struct *ser)
1da177e4
LT		 2112{
2113 int ret = 0;
2114 if (ser->type != PORT_UNKNOWN && ser->type != PORT_AMBA)
2115 ret = -EINVAL;
a62c4133 2116 if (ser->irq < 0 || ser->irq >= nr_irqs)
1da177e4
LT		 2117 ret = -EINVAL;
2118 if (ser->baud_base < 9600)
2119 ret = -EINVAL;
2120 return ret;
2121}
2122
2331e068 2123static const struct uart_ops amba_pl011_pops = {
e643f87f 2124 .tx_empty = pl011_tx_empty,
1da177e4 2125 .set_mctrl = pl011_set_mctrl,
e643f87f 2126 .get_mctrl = pl011_get_mctrl,
1da177e4
LT		 2127 .stop_tx = pl011_stop_tx,
2128 .start_tx = pl011_start_tx,
2129 .stop_rx = pl011_stop_rx,
2130 .enable_ms = pl011_enable_ms,
2131 .break_ctl = pl011_break_ctl,
2132 .startup = pl011_startup,
2133 .shutdown = pl011_shutdown,
68b65f73 2134 .flush_buffer = pl011_dma_flush_buffer,
1da177e4
LT		 2135 .set_termios = pl011_set_termios,
2136 .type = pl011_type,
e643f87f
LW		 2137 .release_port = pl011_release_port,
2138 .request_port = pl011_request_port,
2139 .config_port = pl011_config_port,
2140 .verify_port = pl011_verify_port,
84b5ae15 2141#ifdef CONFIG_CONSOLE_POLL
b3564c2c 2142 .poll_init = pl011_hwinit,
e643f87f
LW		 2143 .poll_get_char = pl011_get_poll_char,
2144 .poll_put_char = pl011_put_poll_char,
84b5ae15 2145#endif
1da177e4
LT		 2146};
2147
0dd1e247
AP		 2148static void sbsa_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
2149{
2150}
2151
2152static unsigned int sbsa_uart_get_mctrl(struct uart_port *port)
2153{
2154 return 0;
2155}
2156
2157static const struct uart_ops sbsa_uart_pops = {
2158 .tx_empty = pl011_tx_empty,
2159 .set_mctrl = sbsa_uart_set_mctrl,
2160 .get_mctrl = sbsa_uart_get_mctrl,
2161 .stop_tx = pl011_stop_tx,
2162 .start_tx = pl011_start_tx,
2163 .stop_rx = pl011_stop_rx,
2164 .startup = sbsa_uart_startup,
2165 .shutdown = sbsa_uart_shutdown,
2166 .set_termios = sbsa_uart_set_termios,
2167 .type = pl011_type,
2168 .release_port = pl011_release_port,
2169 .request_port = pl011_request_port,
2170 .config_port = pl011_config_port,
2171 .verify_port = pl011_verify_port,
2172#ifdef CONFIG_CONSOLE_POLL
2173 .poll_init = pl011_hwinit,
2174 .poll_get_char = pl011_get_poll_char,
2175 .poll_put_char = pl011_put_poll_char,
2176#endif
2177};
2178
1da177e4
LT		 2179static struct uart_amba_port *amba_ports[UART_NR];
2180
2181#ifdef CONFIG_SERIAL_AMBA_PL011_CONSOLE
2182
d358788f 2183static void pl011_console_putchar(struct uart_port *port, int ch)
1da177e4 2184{
a5820c24
DT		 2185 struct uart_amba_port *uap =
2186 container_of(port, struct uart_amba_port, port);
1da177e4 2187
9f25bc51 2188 while (pl011_read(uap, REG_FR) & UART01x_FR_TXFF)
2f2fd089 2189 cpu_relax();
9f25bc51 2190 pl011_write(ch, uap, REG_DR);
1da177e4
LT		 2191}
2192
2193static void
2194pl011_console_write(struct console *co, const char *s, unsigned int count)
2195{
2196 struct uart_amba_port *uap = amba_ports[co->index];
2f2fd089 2197 unsigned int old_cr = 0, new_cr;
ef605fdb
RV		 2198 unsigned long flags;
2199 int locked = 1;
1da177e4
LT		 2200
2201 clk_enable(uap->clk);
2202
ef605fdb
RV		 2203 local_irq_save(flags);
2204 if (uap->port.sysrq)
2205 locked = 0;
2206 else if (oops_in_progress)
2207 locked = spin_trylock(&uap->port.lock);
2208 else
2209 spin_lock(&uap->port.lock);
2210
1da177e4
LT		 2211 /*
2212 * First save the CR then disable the interrupts
2213 */
71eec483 2214 if (!uap->vendor->always_enabled) {
9f25bc51 2215 old_cr = pl011_read(uap, REG_CR);
71eec483
AP		 2216 new_cr = old_cr & ~UART011_CR_CTSEN;
2217 new_cr |= UART01x_CR_UARTEN | UART011_CR_TXE;
9f25bc51 2218 pl011_write(new_cr, uap, REG_CR);
71eec483 2219 }
1da177e4 2220
d358788f 2221 uart_console_write(&uap->port, s, count, pl011_console_putchar);
1da177e4
LT		 2222
2223 /*
d8a4995b
CC		 2224 * Finally, wait for transmitter to become empty and restore the
2225 * TCR. Allow feature register bits to be inverted to work around
2226 * errata.
1da177e4 2227 */
d8a4995b
CC		 2228 while ((pl011_read(uap, REG_FR) ^ uap->vendor->inv_fr)
2229 & uap->vendor->fr_busy)
2f2fd089 2230 cpu_relax();
71eec483 2231 if (!uap->vendor->always_enabled)
9f25bc51 2232 pl011_write(old_cr, uap, REG_CR);
1da177e4 2233
ef605fdb
RV		 2234 if (locked)
2235 spin_unlock(&uap->port.lock);
2236 local_irq_restore(flags);
2237
1da177e4
LT		 2238 clk_disable(uap->clk);
2239}
2240
2241static void __init
2242pl011_console_get_options(struct uart_amba_port *uap, int *baud,
2243 int *parity, int *bits)
2244{
9f25bc51 2245 if (pl011_read(uap, REG_CR) & UART01x_CR_UARTEN) {
1da177e4
LT		 2246 unsigned int lcr_h, ibrd, fbrd;
2247
e4df9a80 2248 lcr_h = pl011_read(uap, REG_LCRH_TX);
1da177e4
LT		 2249
2250 *parity = 'n';
2251 if (lcr_h & UART01x_LCRH_PEN) {
2252 if (lcr_h & UART01x_LCRH_EPS)
2253 *parity = 'e';
2254 else
2255 *parity = 'o';
2256 }
2257
2258 if ((lcr_h & 0x60) == UART01x_LCRH_WLEN_7)
2259 *bits = 7;
2260 else
2261 *bits = 8;
2262
9f25bc51
RK		 2263 ibrd = pl011_read(uap, REG_IBRD);
2264 fbrd = pl011_read(uap, REG_FBRD);
1da177e4
LT		 2265
2266 *baud = uap->port.uartclk * 4 / (64 * ibrd + fbrd);
ac3e3fb4 2267
c19f12b5 2268 if (uap->vendor->oversampling) {
9f25bc51 2269 if (pl011_read(uap, REG_CR)
ac3e3fb4
LW		 2270 & ST_UART011_CR_OVSFACT)
2271 *baud *= 2;
2272 }
1da177e4
LT		 2273 }
2274}
2275
2276static int __init pl011_console_setup(struct console *co, char *options)
2277{
2278 struct uart_amba_port *uap;
2279 int baud = 38400;
2280 int bits = 8;
2281 int parity = 'n';
2282 int flow = 'n';
4b4851c6 2283 int ret;
1da177e4
LT		 2284
2285 /*
2286 * Check whether an invalid uart number has been specified, and
2287 * if so, search for the first available port that does have
2288 * console support.
2289 */
2290 if (co->index >= UART_NR)
2291 co->index = 0;
2292 uap = amba_ports[co->index];
d28122a5
RK		 2293 if (!uap)
2294 return -ENODEV;
1da177e4 2295
78d80c5a 2296 /* Allow pins to be muxed in and configured */
2b996fc5 2297 pinctrl_pm_select_default_state(uap->port.dev);
78d80c5a 2298
4b4851c6
RK		 2299 ret = clk_prepare(uap->clk);
2300 if (ret)
2301 return ret;
2302
574de559 2303 if (dev_get_platdata(uap->port.dev)) {
c16d51a3
SKS		 2304 struct amba_pl011_data *plat;
2305
574de559 2306 plat = dev_get_platdata(uap->port.dev);
c16d51a3
SKS		 2307 if (plat->init)
2308 plat->init();
2309 }
2310
1da177e4
LT		 2311 uap->port.uartclk = clk_get_rate(uap->clk);
2312
cefc2d1d
AP		 2313 if (uap->vendor->fixed_options) {
2314 baud = uap->fixed_baud;
2315 } else {
2316 if (options)
2317 uart_parse_options(options,
2318 &baud, &parity, &bits, &flow);
2319 else
2320 pl011_console_get_options(uap, &baud, &parity, &bits);
2321 }
1da177e4
LT		 2322
2323 return uart_set_options(&uap->port, co, baud, parity, bits, flow);
2324}
2325
10879ae5
AM		 2326/**
2327 * pl011_console_match - non-standard console matching
2328 * @co: registering console
2329 * @name: name from console command line
2330 * @idx: index from console command line
2331 * @options: ptr to option string from console command line
2332 *
2333 * Only attempts to match console command lines of the form:
2334 * console=pl011,mmio|mmio32,<addr>[,<options>]
2335 * console=pl011,0x<addr>[,<options>]
2336 * This form is used to register an initial earlycon boot console and
2337 * replace it with the amba_console at pl011 driver init.
2338 *
2339 * Performs console setup for a match (as required by interface)
2340 * If no <options> are specified, then assume the h/w is already setup.
2341 *
2342 * Returns 0 if console matches; otherwise non-zero to use default matching
2343 */
2344static int __init pl011_console_match(struct console *co, char *name, int idx,
2345 char *options)
2346{
2347 unsigned char iotype;
2348 resource_size_t addr;
2349 int i;
2350
37ef38f3
TT		 2351 /*
2352 * Systems affected by the Qualcomm Technologies QDF2400 E44 erratum
2353 * have a distinct console name, so make sure we check for that.
2354 * The actual implementation of the erratum occurs in the probe
2355 * function.
2356 */
2357 if ((strcmp(name, "qdf2400_e44") != 0) && (strcmp(name, "pl011") != 0))
10879ae5
AM		 2358 return -ENODEV;
2359
2360 if (uart_parse_earlycon(options, &iotype, &addr, &options))
2361 return -ENODEV;
2362
2363 if (iotype != UPIO_MEM && iotype != UPIO_MEM32)
2364 return -ENODEV;
2365
2366 /* try to match the port specified on the command line */
2367 for (i = 0; i < ARRAY_SIZE(amba_ports); i++) {
2368 struct uart_port *port;
2369
2370 if (!amba_ports[i])
2371 continue;
2372
2373 port = &amba_ports[i]->port;
2374
2375 if (port->mapbase != addr)
2376 continue;
2377
2378 co->index = i;
2379 port->cons = co;
2380 return pl011_console_setup(co, options);
2381 }
2382
2383 return -ENODEV;
2384}
2385
2d93486c 2386static struct uart_driver amba_reg;
1da177e4
LT		 2387static struct console amba_console = {
2388 .name = "ttyAMA",
2389 .write = pl011_console_write,
2390 .device = uart_console_device,
2391 .setup = pl011_console_setup,
10879ae5 2392 .match = pl011_console_match,
7951ffc9 2393 .flags = CON_PRINTBUFFER | CON_ANYTIME,
1da177e4
LT		 2394 .index = -1,
2395 .data = &amba_reg,
2396};
2397
2398#define AMBA_CONSOLE (&amba_console)
0d3c673e 2399
d8a4995b
CC		 2400static void qdf2400_e44_putc(struct uart_port *port, int c)
2401{
2402 while (readl(port->membase + UART01x_FR) & UART01x_FR_TXFF)
2403 cpu_relax();
2404 writel(c, port->membase + UART01x_DR);
2405 while (!(readl(port->membase + UART01x_FR) & UART011_FR_TXFE))
2406 cpu_relax();
2407}
2408
2409static void qdf2400_e44_early_write(struct console *con, const char *s, unsigned n)
2410{
2411 struct earlycon_device *dev = con->data;
2412
2413 uart_console_write(&dev->port, s, n, qdf2400_e44_putc);
2414}
2415
0d3c673e
RH		 2416static void pl011_putc(struct uart_port *port, int c)
2417{
cdf091ca 2418 while (readl(port->membase + UART01x_FR) & UART01x_FR_TXFF)
2f2fd089 2419 cpu_relax();
3b78fae7
TT		 2420 if (port->iotype == UPIO_MEM32)
2421 writel(c, port->membase + UART01x_DR);
2422 else
2423 writeb(c, port->membase + UART01x_DR);
e06690bf 2424 while (readl(port->membase + UART01x_FR) & UART01x_FR_BUSY)
2f2fd089 2425 cpu_relax();
0d3c673e
RH		 2426}
2427
2428static void pl011_early_write(struct console *con, const char *s, unsigned n)
2429{
2430 struct earlycon_device *dev = con->data;
2431
2432 uart_console_write(&dev->port, s, n, pl011_putc);
2433}
2434
e53e597f
TT		 2435/*
2436 * On non-ACPI systems, earlycon is enabled by specifying
2437 * "earlycon=pl011,<address>" on the kernel command line.
2438 *
2439 * On ACPI ARM64 systems, an "early" console is enabled via the SPCR table,
2440 * by specifying only "earlycon" on the command line. Because it requires
2441 * SPCR, the console starts after ACPI is parsed, which is later than a
2442 * traditional early console.
2443 *
2444 * To get the traditional early console that starts before ACPI is parsed,
2445 * specify the full "earlycon=pl011,<address>" option.
2446 */
0d3c673e
RH		 2447static int __init pl011_early_console_setup(struct earlycon_device *device,
2448 const char *opt)
2449{
2450 if (!device->port.membase)
2451 return -ENODEV;
2452
5a0722b8 2453 device->con->write = pl011_early_write;
e53e597f 2454
0d3c673e
RH		 2455 return 0;
2456}
45e0f0f5 2457OF_EARLYCON_DECLARE(pl011, "arm,pl011", pl011_early_console_setup);
fcb32159 2458OF_EARLYCON_DECLARE(pl011, "arm,sbsa-uart", pl011_early_console_setup);
5a0722b8
TT		 2459
2460/*
2461 * On Qualcomm Datacenter Technologies QDF2400 SOCs affected by
2462 * Erratum 44, traditional earlycon can be enabled by specifying
2463 * "earlycon=qdf2400_e44,<address>". Any options are ignored.
2464 *
2465 * Alternatively, you can just specify "earlycon", and the early console
2466 * will be enabled with the information from the SPCR table. In this
2467 * case, the SPCR code will detect the need for the E44 work-around,
2468 * and set the console name to "qdf2400_e44".
2469 */
2470static int __init
2471qdf2400_e44_early_console_setup(struct earlycon_device *device,
2472 const char *opt)
2473{
2474 if (!device->port.membase)
2475 return -ENODEV;
2476
2477 device->con->write = qdf2400_e44_early_write;
2478 return 0;
2479}
2480EARLYCON_DECLARE(qdf2400_e44, qdf2400_e44_early_console_setup);
0d3c673e 2481
1da177e4
LT		 2482#else
2483#define AMBA_CONSOLE NULL
2484#endif
2485
2486static struct uart_driver amba_reg = {
2487 .owner = THIS_MODULE,
2488 .driver_name = "ttyAMA",
2489 .dev_name = "ttyAMA",
2490 .major = SERIAL_AMBA_MAJOR,
2491 .minor = SERIAL_AMBA_MINOR,
2492 .nr = UART_NR,
2493 .cons = AMBA_CONSOLE,
2494};
2495
32614aad
ML		 2496static int pl011_probe_dt_alias(int index, struct device *dev)
2497{
2498 struct device_node *np;
2499 static bool seen_dev_with_alias = false;
2500 static bool seen_dev_without_alias = false;
2501 int ret = index;
2502
2503 if (!IS_ENABLED(CONFIG_OF))
2504 return ret;
2505
2506 np = dev->of_node;
2507 if (!np)
2508 return ret;
2509
2510 ret = of_alias_get_id(np, "serial");
287980e4 2511 if (ret < 0) {
32614aad
ML		 2512 seen_dev_without_alias = true;
2513 ret = index;
2514 } else {
2515 seen_dev_with_alias = true;
2516 if (ret >= ARRAY_SIZE(amba_ports) || amba_ports[ret] != NULL) {
2517 dev_warn(dev, "requested serial port %d not available.\n", ret);
2518 ret = index;
2519 }
2520 }
2521
2522 if (seen_dev_with_alias && seen_dev_without_alias)
2523 dev_warn(dev, "aliased and non-aliased serial devices found in device tree. Serial port enumeration may be unpredictable.\n");
2524
2525 return ret;
2526}
2527
49bb3c86
AP		 2528/* unregisters the driver also if no more ports are left */
2529static void pl011_unregister_port(struct uart_amba_port *uap)
2530{
2531 int i;
2532 bool busy = false;
2533
2534 for (i = 0; i < ARRAY_SIZE(amba_ports); i++) {
2535 if (amba_ports[i] == uap)
2536 amba_ports[i] = NULL;
2537 else if (amba_ports[i])
2538 busy = true;
2539 }
2540 pl011_dma_remove(uap);
2541 if (!busy)
2542 uart_unregister_driver(&amba_reg);
2543}
2544
3873e2d7 2545static int pl011_find_free_port(void)
1da177e4 2546{
3873e2d7 2547 int i;
1da177e4
LT		 2548
2549 for (i = 0; i < ARRAY_SIZE(amba_ports); i++)
2550 if (amba_ports[i] == NULL)
3873e2d7 2551 return i;
1da177e4 2552
3873e2d7
AP		 2553 return -EBUSY;
2554}
1da177e4 2555
3873e2d7
AP		 2556static int pl011_setup_port(struct device *dev, struct uart_amba_port *uap,
2557 struct resource *mmiobase, int index)
2558{
2559 void __iomem *base;
32614aad 2560
3873e2d7 2561 base = devm_ioremap_resource(dev, mmiobase);
97a60eac
KK		 2562 if (IS_ERR(base))
2563 return PTR_ERR(base);
1da177e4 2564
3873e2d7 2565 index = pl011_probe_dt_alias(index, dev);
1da177e4 2566
d8d8ffa4 2567 uap->old_cr = 0;
3873e2d7
AP		 2568 uap->port.dev = dev;
2569 uap->port.mapbase = mmiobase->start;
1da177e4 2570 uap->port.membase = base;
ffca2b11 2571 uap->port.fifosize = uap->fifosize;
1da177e4 2572 uap->port.flags = UPF_BOOT_AUTOCONF;
3873e2d7 2573 uap->port.line = index;
1da177e4 2574
3873e2d7 2575 amba_ports[index] = uap;
c3d8b76f 2576
3873e2d7
AP		 2577 return 0;
2578}
e8a7ba86 2579
3873e2d7
AP		 2580static int pl011_register_port(struct uart_amba_port *uap)
2581{
2582 int ret;
1da177e4 2583
3873e2d7 2584 /* Ensure interrupts from this UART are masked and cleared */
9f25bc51
RK		 2585 pl011_write(0, uap, REG_IMSC);
2586 pl011_write(0xffff, uap, REG_ICR);
ef2889f7
TB		 2587
2588 if (!amba_reg.state) {
2589 ret = uart_register_driver(&amba_reg);
2590 if (ret < 0) {
3873e2d7 2591 dev_err(uap->port.dev,
1c9be310 2592 "Failed to register AMBA-PL011 driver\n");
ef2889f7
TB		 2593 return ret;
2594 }
2595 }
2596
1da177e4 2597 ret = uart_add_one_port(&amba_reg, &uap->port);
49bb3c86
AP		 2598 if (ret)
2599 pl011_unregister_port(uap);
7f6d942a 2600
1da177e4
LT		 2601 return ret;
2602}
2603
3873e2d7
AP		 2604static int pl011_probe(struct amba_device *dev, const struct amba_id *id)
2605{
2606 struct uart_amba_port *uap;
2607 struct vendor_data *vendor = id->data;
2608 int portnr, ret;
2609
2610 portnr = pl011_find_free_port();
2611 if (portnr < 0)
2612 return portnr;
2613
2614 uap = devm_kzalloc(&dev->dev, sizeof(struct uart_amba_port),
2615 GFP_KERNEL);
2616 if (!uap)
2617 return -ENOMEM;
2618
2619 uap->clk = devm_clk_get(&dev->dev, NULL);
2620 if (IS_ERR(uap->clk))
2621 return PTR_ERR(uap->clk);
2622
439403bd 2623 uap->reg_offset = vendor->reg_offset;
3873e2d7 2624 uap->vendor = vendor;
3873e2d7 2625 uap->fifosize = vendor->get_fifosize(dev);
3b78fae7 2626 uap->port.iotype = vendor->access_32b ? UPIO_MEM32 : UPIO_MEM;
3873e2d7
AP		 2627 uap->port.irq = dev->irq[0];
2628 uap->port.ops = &amba_pl011_pops;
2629
2630 snprintf(uap->type, sizeof(uap->type), "PL011 rev%u", amba_rev(dev));
2631
2632 ret = pl011_setup_port(&dev->dev, uap, &dev->res, portnr);
2633 if (ret)
2634 return ret;
2635
2636 amba_set_drvdata(dev, uap);
2637
2638 return pl011_register_port(uap);
2639}
2640
1da177e4
LT		 2641static int pl011_remove(struct amba_device *dev)
2642{
2643 struct uart_amba_port *uap = amba_get_drvdata(dev);
1da177e4 2644
1da177e4 2645 uart_remove_one_port(&amba_reg, &uap->port);
49bb3c86 2646 pl011_unregister_port(uap);
1da177e4
LT		 2647 return 0;
2648}
2649
d0ce850d
UH		 2650#ifdef CONFIG_PM_SLEEP
2651static int pl011_suspend(struct device *dev)
b736b89f 2652{
d0ce850d 2653 struct uart_amba_port *uap = dev_get_drvdata(dev);
b736b89f
LC		 2654
2655 if (!uap)
2656 return -EINVAL;
2657
2658 return uart_suspend_port(&amba_reg, &uap->port);
2659}
2660
d0ce850d 2661static int pl011_resume(struct device *dev)
b736b89f 2662{
d0ce850d 2663 struct uart_amba_port *uap = dev_get_drvdata(dev);
b736b89f
LC		 2664
2665 if (!uap)
2666 return -EINVAL;
2667
2668 return uart_resume_port(&amba_reg, &uap->port);
2669}
2670#endif
2671
d0ce850d
UH		 2672static SIMPLE_DEV_PM_OPS(pl011_dev_pm_ops, pl011_suspend, pl011_resume);
2673
0dd1e247
AP		 2674static int sbsa_uart_probe(struct platform_device *pdev)
2675{
2676 struct uart_amba_port *uap;
2677 struct resource *r;
2678 int portnr, ret;
2679 int baudrate;
2680
2681 /*
2682 * Check the mandatory baud rate parameter in the DT node early
2683 * so that we can easily exit with the error.
2684 */
2685 if (pdev->dev.of_node) {
2686 struct device_node *np = pdev->dev.of_node;
2687
2688 ret = of_property_read_u32(np, "current-speed", &baudrate);
2689 if (ret)
2690 return ret;
2691 } else {
2692 baudrate = 115200;
2693 }
2694
2695 portnr = pl011_find_free_port();
2696 if (portnr < 0)
2697 return portnr;
2698
2699 uap = devm_kzalloc(&pdev->dev, sizeof(struct uart_amba_port),
2700 GFP_KERNEL);
2701 if (!uap)
2702 return -ENOMEM;
2703
394a9e2c
JS		 2704 ret = platform_get_irq(pdev, 0);
2705 if (ret < 0) {
35aa33cf
KW		 2706 if (ret != -EPROBE_DEFER)
2707 dev_err(&pdev->dev, "cannot obtain irq\n");
394a9e2c
JS		 2708 return ret;
2709 }
2710 uap->port.irq = ret;
2711
37ef38f3
TT		 2712#ifdef CONFIG_ACPI_SPCR_TABLE
2713 if (qdf2400_e44_present) {
2714 dev_info(&pdev->dev, "working around QDF2400 SoC erratum 44\n");
2715 uap->vendor = &vendor_qdt_qdf2400_e44;
2716 } else
2717#endif
2718 uap->vendor = &vendor_sbsa;
2719
2720 uap->reg_offset = uap->vendor->reg_offset;
0dd1e247 2721 uap->fifosize = 32;
37ef38f3 2722 uap->port.iotype = uap->vendor->access_32b ? UPIO_MEM32 : UPIO_MEM;
0dd1e247
AP		 2723 uap->port.ops = &sbsa_uart_pops;
2724 uap->fixed_baud = baudrate;
2725
2726 snprintf(uap->type, sizeof(uap->type), "SBSA");
2727
2728 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2729
2730 ret = pl011_setup_port(&pdev->dev, uap, r, portnr);
2731 if (ret)
2732 return ret;
2733
2734 platform_set_drvdata(pdev, uap);
2735
2736 return pl011_register_port(uap);
2737}
2738
2739static int sbsa_uart_remove(struct platform_device *pdev)
2740{
2741 struct uart_amba_port *uap = platform_get_drvdata(pdev);
2742
2743 uart_remove_one_port(&amba_reg, &uap->port);
2744 pl011_unregister_port(uap);
2745 return 0;
2746}
2747
2748static const struct of_device_id sbsa_uart_of_match[] = {
2749 { .compatible = "arm,sbsa-uart", },
2750 {},
2751};
2752MODULE_DEVICE_TABLE(of, sbsa_uart_of_match);
2753
3db9ab0b
GG		 2754static const struct acpi_device_id sbsa_uart_acpi_match[] = {
2755 { "ARMH0011", 0 },
2756 {},
2757};
2758MODULE_DEVICE_TABLE(acpi, sbsa_uart_acpi_match);
2759
0dd1e247
AP		 2760static struct platform_driver arm_sbsa_uart_platform_driver = {
2761 .probe = sbsa_uart_probe,
2762 .remove = sbsa_uart_remove,
2763 .driver = {
2764 .name = "sbsa-uart",
2765 .of_match_table = of_match_ptr(sbsa_uart_of_match),
3db9ab0b 2766 .acpi_match_table = ACPI_PTR(sbsa_uart_acpi_match),
0dd1e247
AP		 2767 },
2768};
2769
a704ddc2 2770static const struct amba_id pl011_ids[] = {
1da177e4
LT		 2771 {
2772 .id = 0x00041011,
2773 .mask = 0x000fffff,
5926a295
AR		 2774 .data = &vendor_arm,
2775 },
2776 {
2777 .id = 0x00380802,
2778 .mask = 0x00ffffff,
2779 .data = &vendor_st,
1da177e4 2780 },
2426fbc7
SG		 2781 {
2782 .id = AMBA_LINUX_ID(0x00, 0x1, 0xffe),
2783 .mask = 0x00ffffff,
2784 .data = &vendor_zte,
2785 },
1da177e4
LT		 2786 { 0, 0 },
2787};
2788
60f7a33b
DM		 2789MODULE_DEVICE_TABLE(amba, pl011_ids);
2790
1da177e4
LT		 2791static struct amba_driver pl011_driver = {
2792 .drv = {
2793 .name = "uart-pl011",
d0ce850d 2794 .pm = &pl011_dev_pm_ops,
1da177e4
LT		 2795 },
2796 .id_table = pl011_ids,
2797 .probe = pl011_probe,
2798 .remove = pl011_remove,
2799};
2800
2801static int __init pl011_init(void)
2802{
1da177e4
LT		 2803 printk(KERN_INFO "Serial: AMBA PL011 UART driver\n");
2804
0dd1e247
AP		 2805 if (platform_driver_register(&arm_sbsa_uart_platform_driver))
2806 pr_warn("could not register SBSA UART platform driver\n");
062a68a5 2807 return amba_driver_register(&pl011_driver);
1da177e4
LT		 2808}
2809
2810static void __exit pl011_exit(void)
2811{
0dd1e247 2812 platform_driver_unregister(&arm_sbsa_uart_platform_driver);
1da177e4 2813 amba_driver_unregister(&pl011_driver);
1da177e4
LT		 2814}
2815
4dd9e742
AR		 2816/*
2817 * While this can be a module, if builtin it's most likely the console
2818 * So let's leave module_exit but move module_init to an earlier place
2819 */
2820arch_initcall(pl011_init);
1da177e4
LT		 2821module_exit(pl011_exit);
2822
2823MODULE_AUTHOR("ARM Ltd/Deep Blue Solutions Ltd");
2824MODULE_DESCRIPTION("ARM AMBA serial port driver");
2825MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)