Commit | Line | Data |
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e3b3d0f5 | 1 | // SPDX-License-Identifier: GPL-2.0+ |
1da177e4 | 2 | /* |
1da177e4 LT |
3 | * Driver for AMBA serial ports |
4 | * | |
5 | * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. | |
6 | * | |
7 | * Copyright 1999 ARM Limited | |
8 | * Copyright (C) 2000 Deep Blue Solutions Ltd. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; either version 2 of the License, or | |
13 | * (at your option) any later version. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | * GNU General Public License for more details. | |
19 | * | |
20 | * You should have received a copy of the GNU General Public License | |
21 | * along with this program; if not, write to the Free Software | |
22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
23 | * | |
1da177e4 LT |
24 | * This is a generic driver for ARM AMBA-type serial ports. They |
25 | * have a lot of 16550-like features, but are not register compatible. | |
26 | * Note that although they do have CTS, DCD and DSR inputs, they do | |
27 | * not have an RI input, nor do they have DTR or RTS outputs. If | |
28 | * required, these have to be supplied via some other means (eg, GPIO) | |
29 | * and hooked into this driver. | |
30 | */ | |
1da177e4 LT |
31 | |
32 | #if defined(CONFIG_SERIAL_AMBA_PL010_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) | |
33 | #define SUPPORT_SYSRQ | |
34 | #endif | |
35 | ||
36 | #include <linux/module.h> | |
37 | #include <linux/ioport.h> | |
38 | #include <linux/init.h> | |
39 | #include <linux/console.h> | |
40 | #include <linux/sysrq.h> | |
41 | #include <linux/device.h> | |
42 | #include <linux/tty.h> | |
43 | #include <linux/tty_flip.h> | |
44 | #include <linux/serial_core.h> | |
45 | #include <linux/serial.h> | |
a62c80e5 RK |
46 | #include <linux/amba/bus.h> |
47 | #include <linux/amba/serial.h> | |
ed519ded | 48 | #include <linux/clk.h> |
5a0e3ad6 | 49 | #include <linux/slab.h> |
44acd260 | 50 | #include <linux/io.h> |
1da177e4 | 51 | |
4faf4e0e | 52 | #define UART_NR 8 |
1da177e4 LT |
53 | |
54 | #define SERIAL_AMBA_MAJOR 204 | |
55 | #define SERIAL_AMBA_MINOR 16 | |
56 | #define SERIAL_AMBA_NR UART_NR | |
57 | ||
58 | #define AMBA_ISR_PASS_LIMIT 256 | |
59 | ||
1da177e4 LT |
60 | #define UART_RX_DATA(s) (((s) & UART01x_FR_RXFE) == 0) |
61 | #define UART_TX_READY(s) (((s) & UART01x_FR_TXFF) == 0) | |
1da177e4 | 62 | |
fbb18a27 | 63 | #define UART_DUMMY_RSR_RX 256 |
1da177e4 LT |
64 | #define UART_PORT_SIZE 64 |
65 | ||
1da177e4 LT |
66 | /* |
67 | * We wrap our port structure around the generic uart_port. | |
68 | */ | |
69 | struct uart_amba_port { | |
70 | struct uart_port port; | |
ed519ded | 71 | struct clk *clk; |
fbb18a27 RK |
72 | struct amba_device *dev; |
73 | struct amba_pl010_data *data; | |
1da177e4 LT |
74 | unsigned int old_status; |
75 | }; | |
76 | ||
b129a8cc | 77 | static void pl010_stop_tx(struct uart_port *port) |
1da177e4 | 78 | { |
b70e5e9d FF |
79 | struct uart_amba_port *uap = |
80 | container_of(port, struct uart_amba_port, port); | |
1da177e4 LT |
81 | unsigned int cr; |
82 | ||
1b0646a0 | 83 | cr = readb(uap->port.membase + UART010_CR); |
1da177e4 | 84 | cr &= ~UART010_CR_TIE; |
1b0646a0 | 85 | writel(cr, uap->port.membase + UART010_CR); |
1da177e4 LT |
86 | } |
87 | ||
b129a8cc | 88 | static void pl010_start_tx(struct uart_port *port) |
1da177e4 | 89 | { |
b70e5e9d FF |
90 | struct uart_amba_port *uap = |
91 | container_of(port, struct uart_amba_port, port); | |
1da177e4 LT |
92 | unsigned int cr; |
93 | ||
1b0646a0 | 94 | cr = readb(uap->port.membase + UART010_CR); |
1da177e4 | 95 | cr |= UART010_CR_TIE; |
1b0646a0 | 96 | writel(cr, uap->port.membase + UART010_CR); |
1da177e4 LT |
97 | } |
98 | ||
99 | static void pl010_stop_rx(struct uart_port *port) | |
100 | { | |
b70e5e9d FF |
101 | struct uart_amba_port *uap = |
102 | container_of(port, struct uart_amba_port, port); | |
1da177e4 LT |
103 | unsigned int cr; |
104 | ||
1b0646a0 | 105 | cr = readb(uap->port.membase + UART010_CR); |
1da177e4 | 106 | cr &= ~(UART010_CR_RIE | UART010_CR_RTIE); |
1b0646a0 | 107 | writel(cr, uap->port.membase + UART010_CR); |
1da177e4 LT |
108 | } |
109 | ||
cab68f89 PH |
110 | static void pl010_disable_ms(struct uart_port *port) |
111 | { | |
112 | struct uart_amba_port *uap = (struct uart_amba_port *)port; | |
113 | unsigned int cr; | |
114 | ||
115 | cr = readb(uap->port.membase + UART010_CR); | |
116 | cr &= ~UART010_CR_MSIE; | |
117 | writel(cr, uap->port.membase + UART010_CR); | |
118 | } | |
119 | ||
1da177e4 LT |
120 | static void pl010_enable_ms(struct uart_port *port) |
121 | { | |
b70e5e9d FF |
122 | struct uart_amba_port *uap = |
123 | container_of(port, struct uart_amba_port, port); | |
1da177e4 LT |
124 | unsigned int cr; |
125 | ||
1b0646a0 | 126 | cr = readb(uap->port.membase + UART010_CR); |
1da177e4 | 127 | cr |= UART010_CR_MSIE; |
1b0646a0 | 128 | writel(cr, uap->port.membase + UART010_CR); |
1da177e4 LT |
129 | } |
130 | ||
1b0646a0 | 131 | static void pl010_rx_chars(struct uart_amba_port *uap) |
1da177e4 | 132 | { |
1da177e4 LT |
133 | unsigned int status, ch, flag, rsr, max_count = 256; |
134 | ||
1b0646a0 | 135 | status = readb(uap->port.membase + UART01x_FR); |
1da177e4 | 136 | while (UART_RX_DATA(status) && max_count--) { |
1b0646a0 | 137 | ch = readb(uap->port.membase + UART01x_DR); |
1da177e4 LT |
138 | flag = TTY_NORMAL; |
139 | ||
1b0646a0 | 140 | uap->port.icount.rx++; |
1da177e4 LT |
141 | |
142 | /* | |
143 | * Note that the error handling code is | |
144 | * out of the main execution path | |
145 | */ | |
1b0646a0 | 146 | rsr = readb(uap->port.membase + UART01x_RSR) | UART_DUMMY_RSR_RX; |
45849282 | 147 | if (unlikely(rsr & UART01x_RSR_ANY)) { |
1b0646a0 | 148 | writel(0, uap->port.membase + UART01x_ECR); |
a4ed06ad | 149 | |
1da177e4 LT |
150 | if (rsr & UART01x_RSR_BE) { |
151 | rsr &= ~(UART01x_RSR_FE | UART01x_RSR_PE); | |
1b0646a0 RK |
152 | uap->port.icount.brk++; |
153 | if (uart_handle_break(&uap->port)) | |
1da177e4 LT |
154 | goto ignore_char; |
155 | } else if (rsr & UART01x_RSR_PE) | |
1b0646a0 | 156 | uap->port.icount.parity++; |
1da177e4 | 157 | else if (rsr & UART01x_RSR_FE) |
1b0646a0 | 158 | uap->port.icount.frame++; |
1da177e4 | 159 | if (rsr & UART01x_RSR_OE) |
1b0646a0 | 160 | uap->port.icount.overrun++; |
1da177e4 | 161 | |
1b0646a0 | 162 | rsr &= uap->port.read_status_mask; |
1da177e4 LT |
163 | |
164 | if (rsr & UART01x_RSR_BE) | |
165 | flag = TTY_BREAK; | |
166 | else if (rsr & UART01x_RSR_PE) | |
167 | flag = TTY_PARITY; | |
168 | else if (rsr & UART01x_RSR_FE) | |
169 | flag = TTY_FRAME; | |
170 | } | |
171 | ||
1b0646a0 | 172 | if (uart_handle_sysrq_char(&uap->port, ch)) |
1da177e4 LT |
173 | goto ignore_char; |
174 | ||
1b0646a0 | 175 | uart_insert_char(&uap->port, rsr, UART01x_RSR_OE, ch, flag); |
05ab3014 | 176 | |
1da177e4 | 177 | ignore_char: |
1b0646a0 | 178 | status = readb(uap->port.membase + UART01x_FR); |
1da177e4 | 179 | } |
db002b85 | 180 | spin_unlock(&uap->port.lock); |
2e124b4a | 181 | tty_flip_buffer_push(&uap->port.state->port); |
db002b85 | 182 | spin_lock(&uap->port.lock); |
1da177e4 LT |
183 | } |
184 | ||
1b0646a0 | 185 | static void pl010_tx_chars(struct uart_amba_port *uap) |
1da177e4 | 186 | { |
ebd2c8f6 | 187 | struct circ_buf *xmit = &uap->port.state->xmit; |
1da177e4 LT |
188 | int count; |
189 | ||
1b0646a0 RK |
190 | if (uap->port.x_char) { |
191 | writel(uap->port.x_char, uap->port.membase + UART01x_DR); | |
192 | uap->port.icount.tx++; | |
193 | uap->port.x_char = 0; | |
1da177e4 LT |
194 | return; |
195 | } | |
1b0646a0 RK |
196 | if (uart_circ_empty(xmit) || uart_tx_stopped(&uap->port)) { |
197 | pl010_stop_tx(&uap->port); | |
1da177e4 LT |
198 | return; |
199 | } | |
200 | ||
1b0646a0 | 201 | count = uap->port.fifosize >> 1; |
1da177e4 | 202 | do { |
1b0646a0 | 203 | writel(xmit->buf[xmit->tail], uap->port.membase + UART01x_DR); |
1da177e4 | 204 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); |
1b0646a0 | 205 | uap->port.icount.tx++; |
1da177e4 LT |
206 | if (uart_circ_empty(xmit)) |
207 | break; | |
208 | } while (--count > 0); | |
209 | ||
210 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
1b0646a0 | 211 | uart_write_wakeup(&uap->port); |
1da177e4 LT |
212 | |
213 | if (uart_circ_empty(xmit)) | |
1b0646a0 | 214 | pl010_stop_tx(&uap->port); |
1da177e4 LT |
215 | } |
216 | ||
1b0646a0 | 217 | static void pl010_modem_status(struct uart_amba_port *uap) |
1da177e4 | 218 | { |
1da177e4 LT |
219 | unsigned int status, delta; |
220 | ||
98639a67 | 221 | writel(0, uap->port.membase + UART010_ICR); |
1da177e4 | 222 | |
98639a67 | 223 | status = readb(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY; |
1da177e4 LT |
224 | |
225 | delta = status ^ uap->old_status; | |
226 | uap->old_status = status; | |
227 | ||
228 | if (!delta) | |
229 | return; | |
230 | ||
231 | if (delta & UART01x_FR_DCD) | |
232 | uart_handle_dcd_change(&uap->port, status & UART01x_FR_DCD); | |
233 | ||
234 | if (delta & UART01x_FR_DSR) | |
235 | uap->port.icount.dsr++; | |
236 | ||
237 | if (delta & UART01x_FR_CTS) | |
238 | uart_handle_cts_change(&uap->port, status & UART01x_FR_CTS); | |
239 | ||
bdc04e31 | 240 | wake_up_interruptible(&uap->port.state->port.delta_msr_wait); |
1da177e4 LT |
241 | } |
242 | ||
7d12e780 | 243 | static irqreturn_t pl010_int(int irq, void *dev_id) |
1da177e4 | 244 | { |
1b0646a0 | 245 | struct uart_amba_port *uap = dev_id; |
1da177e4 LT |
246 | unsigned int status, pass_counter = AMBA_ISR_PASS_LIMIT; |
247 | int handled = 0; | |
248 | ||
1b0646a0 | 249 | spin_lock(&uap->port.lock); |
1da177e4 | 250 | |
1b0646a0 | 251 | status = readb(uap->port.membase + UART010_IIR); |
1da177e4 LT |
252 | if (status) { |
253 | do { | |
254 | if (status & (UART010_IIR_RTIS | UART010_IIR_RIS)) | |
1b0646a0 | 255 | pl010_rx_chars(uap); |
1da177e4 | 256 | if (status & UART010_IIR_MIS) |
1b0646a0 | 257 | pl010_modem_status(uap); |
1da177e4 | 258 | if (status & UART010_IIR_TIS) |
1b0646a0 | 259 | pl010_tx_chars(uap); |
1da177e4 LT |
260 | |
261 | if (pass_counter-- == 0) | |
262 | break; | |
263 | ||
1b0646a0 | 264 | status = readb(uap->port.membase + UART010_IIR); |
1da177e4 LT |
265 | } while (status & (UART010_IIR_RTIS | UART010_IIR_RIS | |
266 | UART010_IIR_TIS)); | |
267 | handled = 1; | |
268 | } | |
269 | ||
1b0646a0 | 270 | spin_unlock(&uap->port.lock); |
1da177e4 LT |
271 | |
272 | return IRQ_RETVAL(handled); | |
273 | } | |
274 | ||
275 | static unsigned int pl010_tx_empty(struct uart_port *port) | |
276 | { | |
b70e5e9d FF |
277 | struct uart_amba_port *uap = |
278 | container_of(port, struct uart_amba_port, port); | |
1b0646a0 RK |
279 | unsigned int status = readb(uap->port.membase + UART01x_FR); |
280 | return status & UART01x_FR_BUSY ? 0 : TIOCSER_TEMT; | |
1da177e4 LT |
281 | } |
282 | ||
283 | static unsigned int pl010_get_mctrl(struct uart_port *port) | |
284 | { | |
b70e5e9d FF |
285 | struct uart_amba_port *uap = |
286 | container_of(port, struct uart_amba_port, port); | |
1da177e4 LT |
287 | unsigned int result = 0; |
288 | unsigned int status; | |
289 | ||
1b0646a0 | 290 | status = readb(uap->port.membase + UART01x_FR); |
1da177e4 LT |
291 | if (status & UART01x_FR_DCD) |
292 | result |= TIOCM_CAR; | |
293 | if (status & UART01x_FR_DSR) | |
294 | result |= TIOCM_DSR; | |
295 | if (status & UART01x_FR_CTS) | |
296 | result |= TIOCM_CTS; | |
297 | ||
298 | return result; | |
299 | } | |
300 | ||
301 | static void pl010_set_mctrl(struct uart_port *port, unsigned int mctrl) | |
302 | { | |
b70e5e9d FF |
303 | struct uart_amba_port *uap = |
304 | container_of(port, struct uart_amba_port, port); | |
1da177e4 | 305 | |
fbb18a27 RK |
306 | if (uap->data) |
307 | uap->data->set_mctrl(uap->dev, uap->port.membase, mctrl); | |
1da177e4 LT |
308 | } |
309 | ||
310 | static void pl010_break_ctl(struct uart_port *port, int break_state) | |
311 | { | |
b70e5e9d FF |
312 | struct uart_amba_port *uap = |
313 | container_of(port, struct uart_amba_port, port); | |
1da177e4 LT |
314 | unsigned long flags; |
315 | unsigned int lcr_h; | |
316 | ||
1b0646a0 RK |
317 | spin_lock_irqsave(&uap->port.lock, flags); |
318 | lcr_h = readb(uap->port.membase + UART010_LCRH); | |
1da177e4 LT |
319 | if (break_state == -1) |
320 | lcr_h |= UART01x_LCRH_BRK; | |
321 | else | |
322 | lcr_h &= ~UART01x_LCRH_BRK; | |
1b0646a0 RK |
323 | writel(lcr_h, uap->port.membase + UART010_LCRH); |
324 | spin_unlock_irqrestore(&uap->port.lock, flags); | |
1da177e4 LT |
325 | } |
326 | ||
327 | static int pl010_startup(struct uart_port *port) | |
328 | { | |
b70e5e9d FF |
329 | struct uart_amba_port *uap = |
330 | container_of(port, struct uart_amba_port, port); | |
1da177e4 LT |
331 | int retval; |
332 | ||
ed519ded RK |
333 | /* |
334 | * Try to enable the clock producer. | |
335 | */ | |
1c4c4394 | 336 | retval = clk_prepare_enable(uap->clk); |
ed519ded | 337 | if (retval) |
1c4c4394 | 338 | goto out; |
ed519ded RK |
339 | |
340 | uap->port.uartclk = clk_get_rate(uap->clk); | |
341 | ||
1da177e4 LT |
342 | /* |
343 | * Allocate the IRQ | |
344 | */ | |
1b0646a0 | 345 | retval = request_irq(uap->port.irq, pl010_int, 0, "uart-pl010", uap); |
1da177e4 | 346 | if (retval) |
ed519ded | 347 | goto clk_dis; |
1da177e4 LT |
348 | |
349 | /* | |
350 | * initialise the old status of the modem signals | |
351 | */ | |
1b0646a0 | 352 | uap->old_status = readb(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY; |
1da177e4 LT |
353 | |
354 | /* | |
355 | * Finally, enable interrupts | |
356 | */ | |
98639a67 | 357 | writel(UART01x_CR_UARTEN | UART010_CR_RIE | UART010_CR_RTIE, |
1b0646a0 | 358 | uap->port.membase + UART010_CR); |
1da177e4 LT |
359 | |
360 | return 0; | |
ed519ded RK |
361 | |
362 | clk_dis: | |
1c4c4394 | 363 | clk_disable_unprepare(uap->clk); |
ed519ded RK |
364 | out: |
365 | return retval; | |
1da177e4 LT |
366 | } |
367 | ||
368 | static void pl010_shutdown(struct uart_port *port) | |
369 | { | |
b70e5e9d FF |
370 | struct uart_amba_port *uap = |
371 | container_of(port, struct uart_amba_port, port); | |
1b0646a0 | 372 | |
1da177e4 LT |
373 | /* |
374 | * Free the interrupt | |
375 | */ | |
1b0646a0 | 376 | free_irq(uap->port.irq, uap); |
1da177e4 LT |
377 | |
378 | /* | |
379 | * disable all interrupts, disable the port | |
380 | */ | |
1b0646a0 | 381 | writel(0, uap->port.membase + UART010_CR); |
1da177e4 LT |
382 | |
383 | /* disable break condition and fifos */ | |
1b0646a0 | 384 | writel(readb(uap->port.membase + UART010_LCRH) & |
98639a67 | 385 | ~(UART01x_LCRH_BRK | UART01x_LCRH_FEN), |
1b0646a0 | 386 | uap->port.membase + UART010_LCRH); |
ed519ded RK |
387 | |
388 | /* | |
389 | * Shut down the clock producer | |
390 | */ | |
1c4c4394 | 391 | clk_disable_unprepare(uap->clk); |
1da177e4 LT |
392 | } |
393 | ||
394 | static void | |
606d099c AC |
395 | pl010_set_termios(struct uart_port *port, struct ktermios *termios, |
396 | struct ktermios *old) | |
1da177e4 | 397 | { |
b70e5e9d FF |
398 | struct uart_amba_port *uap = |
399 | container_of(port, struct uart_amba_port, port); | |
1da177e4 LT |
400 | unsigned int lcr_h, old_cr; |
401 | unsigned long flags; | |
402 | unsigned int baud, quot; | |
403 | ||
404 | /* | |
405 | * Ask the core to calculate the divisor for us. | |
406 | */ | |
1b0646a0 | 407 | baud = uart_get_baud_rate(port, termios, old, 0, uap->port.uartclk/16); |
1da177e4 LT |
408 | quot = uart_get_divisor(port, baud); |
409 | ||
410 | switch (termios->c_cflag & CSIZE) { | |
411 | case CS5: | |
412 | lcr_h = UART01x_LCRH_WLEN_5; | |
413 | break; | |
414 | case CS6: | |
415 | lcr_h = UART01x_LCRH_WLEN_6; | |
416 | break; | |
417 | case CS7: | |
418 | lcr_h = UART01x_LCRH_WLEN_7; | |
419 | break; | |
420 | default: // CS8 | |
421 | lcr_h = UART01x_LCRH_WLEN_8; | |
422 | break; | |
423 | } | |
424 | if (termios->c_cflag & CSTOPB) | |
425 | lcr_h |= UART01x_LCRH_STP2; | |
426 | if (termios->c_cflag & PARENB) { | |
427 | lcr_h |= UART01x_LCRH_PEN; | |
428 | if (!(termios->c_cflag & PARODD)) | |
429 | lcr_h |= UART01x_LCRH_EPS; | |
430 | } | |
1b0646a0 | 431 | if (uap->port.fifosize > 1) |
1da177e4 LT |
432 | lcr_h |= UART01x_LCRH_FEN; |
433 | ||
1b0646a0 | 434 | spin_lock_irqsave(&uap->port.lock, flags); |
1da177e4 LT |
435 | |
436 | /* | |
437 | * Update the per-port timeout. | |
438 | */ | |
439 | uart_update_timeout(port, termios->c_cflag, baud); | |
440 | ||
1b0646a0 | 441 | uap->port.read_status_mask = UART01x_RSR_OE; |
1da177e4 | 442 | if (termios->c_iflag & INPCK) |
1b0646a0 | 443 | uap->port.read_status_mask |= UART01x_RSR_FE | UART01x_RSR_PE; |
ef8b9ddc | 444 | if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) |
1b0646a0 | 445 | uap->port.read_status_mask |= UART01x_RSR_BE; |
1da177e4 LT |
446 | |
447 | /* | |
448 | * Characters to ignore | |
449 | */ | |
1b0646a0 | 450 | uap->port.ignore_status_mask = 0; |
1da177e4 | 451 | if (termios->c_iflag & IGNPAR) |
1b0646a0 | 452 | uap->port.ignore_status_mask |= UART01x_RSR_FE | UART01x_RSR_PE; |
1da177e4 | 453 | if (termios->c_iflag & IGNBRK) { |
1b0646a0 | 454 | uap->port.ignore_status_mask |= UART01x_RSR_BE; |
1da177e4 LT |
455 | /* |
456 | * If we're ignoring parity and break indicators, | |
457 | * ignore overruns too (for real raw support). | |
458 | */ | |
459 | if (termios->c_iflag & IGNPAR) | |
1b0646a0 | 460 | uap->port.ignore_status_mask |= UART01x_RSR_OE; |
1da177e4 LT |
461 | } |
462 | ||
463 | /* | |
464 | * Ignore all characters if CREAD is not set. | |
465 | */ | |
466 | if ((termios->c_cflag & CREAD) == 0) | |
1b0646a0 | 467 | uap->port.ignore_status_mask |= UART_DUMMY_RSR_RX; |
1da177e4 LT |
468 | |
469 | /* first, disable everything */ | |
1b0646a0 | 470 | old_cr = readb(uap->port.membase + UART010_CR) & ~UART010_CR_MSIE; |
1da177e4 LT |
471 | |
472 | if (UART_ENABLE_MS(port, termios->c_cflag)) | |
473 | old_cr |= UART010_CR_MSIE; | |
474 | ||
1b0646a0 | 475 | writel(0, uap->port.membase + UART010_CR); |
1da177e4 LT |
476 | |
477 | /* Set baud rate */ | |
478 | quot -= 1; | |
1b0646a0 RK |
479 | writel((quot & 0xf00) >> 8, uap->port.membase + UART010_LCRM); |
480 | writel(quot & 0xff, uap->port.membase + UART010_LCRL); | |
1da177e4 LT |
481 | |
482 | /* | |
483 | * ----------v----------v----------v----------v----- | |
484 | * NOTE: MUST BE WRITTEN AFTER UARTLCR_M & UARTLCR_L | |
485 | * ----------^----------^----------^----------^----- | |
486 | */ | |
1b0646a0 RK |
487 | writel(lcr_h, uap->port.membase + UART010_LCRH); |
488 | writel(old_cr, uap->port.membase + UART010_CR); | |
1da177e4 | 489 | |
1b0646a0 | 490 | spin_unlock_irqrestore(&uap->port.lock, flags); |
1da177e4 LT |
491 | } |
492 | ||
732a84a0 | 493 | static void pl010_set_ldisc(struct uart_port *port, struct ktermios *termios) |
7ed63d5e | 494 | { |
732a84a0 | 495 | if (termios->c_line == N_PPS) { |
7ed63d5e | 496 | port->flags |= UPF_HARDPPS_CD; |
d41510ce | 497 | spin_lock_irq(&port->lock); |
7ed63d5e | 498 | pl010_enable_ms(port); |
d41510ce | 499 | spin_unlock_irq(&port->lock); |
cab68f89 | 500 | } else { |
7ed63d5e | 501 | port->flags &= ~UPF_HARDPPS_CD; |
cab68f89 PH |
502 | if (!UART_ENABLE_MS(port, termios->c_cflag)) { |
503 | spin_lock_irq(&port->lock); | |
504 | pl010_disable_ms(port); | |
505 | spin_unlock_irq(&port->lock); | |
506 | } | |
507 | } | |
7ed63d5e RG |
508 | } |
509 | ||
1da177e4 LT |
510 | static const char *pl010_type(struct uart_port *port) |
511 | { | |
512 | return port->type == PORT_AMBA ? "AMBA" : NULL; | |
513 | } | |
514 | ||
515 | /* | |
516 | * Release the memory region(s) being used by 'port' | |
517 | */ | |
518 | static void pl010_release_port(struct uart_port *port) | |
519 | { | |
520 | release_mem_region(port->mapbase, UART_PORT_SIZE); | |
521 | } | |
522 | ||
523 | /* | |
524 | * Request the memory region(s) being used by 'port' | |
525 | */ | |
526 | static int pl010_request_port(struct uart_port *port) | |
527 | { | |
528 | return request_mem_region(port->mapbase, UART_PORT_SIZE, "uart-pl010") | |
529 | != NULL ? 0 : -EBUSY; | |
530 | } | |
531 | ||
532 | /* | |
533 | * Configure/autoconfigure the port. | |
534 | */ | |
535 | static void pl010_config_port(struct uart_port *port, int flags) | |
536 | { | |
537 | if (flags & UART_CONFIG_TYPE) { | |
538 | port->type = PORT_AMBA; | |
539 | pl010_request_port(port); | |
540 | } | |
541 | } | |
542 | ||
543 | /* | |
544 | * verify the new serial_struct (for TIOCSSERIAL). | |
545 | */ | |
546 | static int pl010_verify_port(struct uart_port *port, struct serial_struct *ser) | |
547 | { | |
548 | int ret = 0; | |
549 | if (ser->type != PORT_UNKNOWN && ser->type != PORT_AMBA) | |
550 | ret = -EINVAL; | |
a62c4133 | 551 | if (ser->irq < 0 || ser->irq >= nr_irqs) |
1da177e4 LT |
552 | ret = -EINVAL; |
553 | if (ser->baud_base < 9600) | |
554 | ret = -EINVAL; | |
555 | return ret; | |
556 | } | |
557 | ||
2331e068 | 558 | static const struct uart_ops amba_pl010_pops = { |
1da177e4 LT |
559 | .tx_empty = pl010_tx_empty, |
560 | .set_mctrl = pl010_set_mctrl, | |
561 | .get_mctrl = pl010_get_mctrl, | |
562 | .stop_tx = pl010_stop_tx, | |
563 | .start_tx = pl010_start_tx, | |
564 | .stop_rx = pl010_stop_rx, | |
565 | .enable_ms = pl010_enable_ms, | |
566 | .break_ctl = pl010_break_ctl, | |
567 | .startup = pl010_startup, | |
568 | .shutdown = pl010_shutdown, | |
569 | .set_termios = pl010_set_termios, | |
7ed63d5e | 570 | .set_ldisc = pl010_set_ldisc, |
1da177e4 LT |
571 | .type = pl010_type, |
572 | .release_port = pl010_release_port, | |
573 | .request_port = pl010_request_port, | |
574 | .config_port = pl010_config_port, | |
575 | .verify_port = pl010_verify_port, | |
576 | }; | |
577 | ||
fbb18a27 | 578 | static struct uart_amba_port *amba_ports[UART_NR]; |
1da177e4 LT |
579 | |
580 | #ifdef CONFIG_SERIAL_AMBA_PL010_CONSOLE | |
581 | ||
d358788f RK |
582 | static void pl010_console_putchar(struct uart_port *port, int ch) |
583 | { | |
b70e5e9d FF |
584 | struct uart_amba_port *uap = |
585 | container_of(port, struct uart_amba_port, port); | |
98639a67 RK |
586 | unsigned int status; |
587 | ||
588 | do { | |
1b0646a0 | 589 | status = readb(uap->port.membase + UART01x_FR); |
d358788f | 590 | barrier(); |
98639a67 | 591 | } while (!UART_TX_READY(status)); |
1b0646a0 | 592 | writel(ch, uap->port.membase + UART01x_DR); |
d358788f RK |
593 | } |
594 | ||
1da177e4 LT |
595 | static void |
596 | pl010_console_write(struct console *co, const char *s, unsigned int count) | |
597 | { | |
1b0646a0 | 598 | struct uart_amba_port *uap = amba_ports[co->index]; |
1da177e4 | 599 | unsigned int status, old_cr; |
1da177e4 | 600 | |
ed519ded RK |
601 | clk_enable(uap->clk); |
602 | ||
1da177e4 LT |
603 | /* |
604 | * First save the CR then disable the interrupts | |
605 | */ | |
1b0646a0 RK |
606 | old_cr = readb(uap->port.membase + UART010_CR); |
607 | writel(UART01x_CR_UARTEN, uap->port.membase + UART010_CR); | |
1da177e4 | 608 | |
1b0646a0 | 609 | uart_console_write(&uap->port, s, count, pl010_console_putchar); |
1da177e4 LT |
610 | |
611 | /* | |
612 | * Finally, wait for transmitter to become empty | |
613 | * and restore the TCR | |
614 | */ | |
615 | do { | |
1b0646a0 | 616 | status = readb(uap->port.membase + UART01x_FR); |
98639a67 | 617 | barrier(); |
1da177e4 | 618 | } while (status & UART01x_FR_BUSY); |
1b0646a0 | 619 | writel(old_cr, uap->port.membase + UART010_CR); |
ed519ded RK |
620 | |
621 | clk_disable(uap->clk); | |
1da177e4 LT |
622 | } |
623 | ||
624 | static void __init | |
1b0646a0 | 625 | pl010_console_get_options(struct uart_amba_port *uap, int *baud, |
1da177e4 LT |
626 | int *parity, int *bits) |
627 | { | |
1b0646a0 | 628 | if (readb(uap->port.membase + UART010_CR) & UART01x_CR_UARTEN) { |
1da177e4 | 629 | unsigned int lcr_h, quot; |
1b0646a0 | 630 | lcr_h = readb(uap->port.membase + UART010_LCRH); |
1da177e4 LT |
631 | |
632 | *parity = 'n'; | |
633 | if (lcr_h & UART01x_LCRH_PEN) { | |
634 | if (lcr_h & UART01x_LCRH_EPS) | |
635 | *parity = 'e'; | |
636 | else | |
637 | *parity = 'o'; | |
638 | } | |
639 | ||
640 | if ((lcr_h & 0x60) == UART01x_LCRH_WLEN_7) | |
641 | *bits = 7; | |
642 | else | |
643 | *bits = 8; | |
644 | ||
1b0646a0 RK |
645 | quot = readb(uap->port.membase + UART010_LCRL) | |
646 | readb(uap->port.membase + UART010_LCRM) << 8; | |
647 | *baud = uap->port.uartclk / (16 * (quot + 1)); | |
1da177e4 LT |
648 | } |
649 | } | |
650 | ||
651 | static int __init pl010_console_setup(struct console *co, char *options) | |
652 | { | |
1b0646a0 | 653 | struct uart_amba_port *uap; |
1da177e4 LT |
654 | int baud = 38400; |
655 | int bits = 8; | |
656 | int parity = 'n'; | |
657 | int flow = 'n'; | |
36b8f1e2 | 658 | int ret; |
1da177e4 LT |
659 | |
660 | /* | |
661 | * Check whether an invalid uart number has been specified, and | |
662 | * if so, search for the first available port that does have | |
663 | * console support. | |
664 | */ | |
665 | if (co->index >= UART_NR) | |
666 | co->index = 0; | |
1b0646a0 RK |
667 | uap = amba_ports[co->index]; |
668 | if (!uap) | |
d28122a5 | 669 | return -ENODEV; |
1da177e4 | 670 | |
36b8f1e2 RK |
671 | ret = clk_prepare(uap->clk); |
672 | if (ret) | |
673 | return ret; | |
674 | ||
ed519ded RK |
675 | uap->port.uartclk = clk_get_rate(uap->clk); |
676 | ||
1da177e4 LT |
677 | if (options) |
678 | uart_parse_options(options, &baud, &parity, &bits, &flow); | |
679 | else | |
1b0646a0 | 680 | pl010_console_get_options(uap, &baud, &parity, &bits); |
1da177e4 | 681 | |
1b0646a0 | 682 | return uart_set_options(&uap->port, co, baud, parity, bits, flow); |
1da177e4 LT |
683 | } |
684 | ||
2d93486c | 685 | static struct uart_driver amba_reg; |
1da177e4 LT |
686 | static struct console amba_console = { |
687 | .name = "ttyAM", | |
688 | .write = pl010_console_write, | |
689 | .device = uart_console_device, | |
690 | .setup = pl010_console_setup, | |
691 | .flags = CON_PRINTBUFFER, | |
692 | .index = -1, | |
693 | .data = &amba_reg, | |
694 | }; | |
695 | ||
1da177e4 LT |
696 | #define AMBA_CONSOLE &amba_console |
697 | #else | |
698 | #define AMBA_CONSOLE NULL | |
699 | #endif | |
700 | ||
bd8766b1 | 701 | static DEFINE_MUTEX(amba_reg_lock); |
1da177e4 LT |
702 | static struct uart_driver amba_reg = { |
703 | .owner = THIS_MODULE, | |
704 | .driver_name = "ttyAM", | |
705 | .dev_name = "ttyAM", | |
706 | .major = SERIAL_AMBA_MAJOR, | |
707 | .minor = SERIAL_AMBA_MINOR, | |
708 | .nr = UART_NR, | |
709 | .cons = AMBA_CONSOLE, | |
710 | }; | |
711 | ||
aa25afad | 712 | static int pl010_probe(struct amba_device *dev, const struct amba_id *id) |
1da177e4 | 713 | { |
1b0646a0 | 714 | struct uart_amba_port *uap; |
fbb18a27 RK |
715 | void __iomem *base; |
716 | int i, ret; | |
1da177e4 | 717 | |
fbb18a27 RK |
718 | for (i = 0; i < ARRAY_SIZE(amba_ports); i++) |
719 | if (amba_ports[i] == NULL) | |
720 | break; | |
1da177e4 | 721 | |
44acd260 TB |
722 | if (i == ARRAY_SIZE(amba_ports)) |
723 | return -EBUSY; | |
1da177e4 | 724 | |
44acd260 TB |
725 | uap = devm_kzalloc(&dev->dev, sizeof(struct uart_amba_port), |
726 | GFP_KERNEL); | |
727 | if (!uap) | |
728 | return -ENOMEM; | |
fbb18a27 | 729 | |
44acd260 TB |
730 | base = devm_ioremap(&dev->dev, dev->res.start, |
731 | resource_size(&dev->res)); | |
732 | if (!base) | |
733 | return -ENOMEM; | |
fbb18a27 | 734 | |
44acd260 TB |
735 | uap->clk = devm_clk_get(&dev->dev, NULL); |
736 | if (IS_ERR(uap->clk)) | |
737 | return PTR_ERR(uap->clk); | |
ed519ded | 738 | |
1b0646a0 RK |
739 | uap->port.dev = &dev->dev; |
740 | uap->port.mapbase = dev->res.start; | |
741 | uap->port.membase = base; | |
742 | uap->port.iotype = UPIO_MEM; | |
743 | uap->port.irq = dev->irq[0]; | |
1b0646a0 RK |
744 | uap->port.fifosize = 16; |
745 | uap->port.ops = &amba_pl010_pops; | |
746 | uap->port.flags = UPF_BOOT_AUTOCONF; | |
747 | uap->port.line = i; | |
748 | uap->dev = dev; | |
574de559 | 749 | uap->data = dev_get_platdata(&dev->dev); |
1b0646a0 RK |
750 | |
751 | amba_ports[i] = uap; | |
752 | ||
753 | amba_set_drvdata(dev, uap); | |
bd8766b1 SS |
754 | |
755 | mutex_lock(&amba_reg_lock); | |
756 | if (!amba_reg.state) { | |
757 | ret = uart_register_driver(&amba_reg); | |
758 | if (ret < 0) { | |
759 | mutex_unlock(&amba_reg_lock); | |
760 | dev_err(uap->port.dev, | |
761 | "Failed to register AMBA-PL010 driver\n"); | |
762 | return ret; | |
763 | } | |
764 | } | |
765 | mutex_unlock(&amba_reg_lock); | |
766 | ||
1b0646a0 | 767 | ret = uart_add_one_port(&amba_reg, &uap->port); |
44acd260 | 768 | if (ret) |
fbb18a27 | 769 | amba_ports[i] = NULL; |
44acd260 | 770 | |
fbb18a27 | 771 | return ret; |
1da177e4 LT |
772 | } |
773 | ||
774 | static int pl010_remove(struct amba_device *dev) | |
775 | { | |
1b0646a0 | 776 | struct uart_amba_port *uap = amba_get_drvdata(dev); |
fbb18a27 | 777 | int i; |
bd8766b1 | 778 | bool busy = false; |
1da177e4 | 779 | |
1b0646a0 | 780 | uart_remove_one_port(&amba_reg, &uap->port); |
fbb18a27 RK |
781 | |
782 | for (i = 0; i < ARRAY_SIZE(amba_ports); i++) | |
1b0646a0 | 783 | if (amba_ports[i] == uap) |
fbb18a27 | 784 | amba_ports[i] = NULL; |
bd8766b1 SS |
785 | else if (amba_ports[i]) |
786 | busy = true; | |
787 | ||
788 | if (!busy) | |
789 | uart_unregister_driver(&amba_reg); | |
fbb18a27 | 790 | |
1da177e4 LT |
791 | return 0; |
792 | } | |
793 | ||
95468240 UH |
794 | #ifdef CONFIG_PM_SLEEP |
795 | static int pl010_suspend(struct device *dev) | |
1da177e4 | 796 | { |
95468240 | 797 | struct uart_amba_port *uap = dev_get_drvdata(dev); |
1da177e4 LT |
798 | |
799 | if (uap) | |
800 | uart_suspend_port(&amba_reg, &uap->port); | |
801 | ||
802 | return 0; | |
803 | } | |
804 | ||
95468240 | 805 | static int pl010_resume(struct device *dev) |
1da177e4 | 806 | { |
95468240 | 807 | struct uart_amba_port *uap = dev_get_drvdata(dev); |
1da177e4 LT |
808 | |
809 | if (uap) | |
810 | uart_resume_port(&amba_reg, &uap->port); | |
811 | ||
812 | return 0; | |
813 | } | |
95468240 UH |
814 | #endif |
815 | ||
816 | static SIMPLE_DEV_PM_OPS(pl010_dev_pm_ops, pl010_suspend, pl010_resume); | |
1da177e4 | 817 | |
5337e549 | 818 | static const struct amba_id pl010_ids[] = { |
1da177e4 LT |
819 | { |
820 | .id = 0x00041010, | |
821 | .mask = 0x000fffff, | |
822 | }, | |
823 | { 0, 0 }, | |
824 | }; | |
825 | ||
a664a119 DM |
826 | MODULE_DEVICE_TABLE(amba, pl010_ids); |
827 | ||
1da177e4 LT |
828 | static struct amba_driver pl010_driver = { |
829 | .drv = { | |
830 | .name = "uart-pl010", | |
95468240 | 831 | .pm = &pl010_dev_pm_ops, |
1da177e4 LT |
832 | }, |
833 | .id_table = pl010_ids, | |
834 | .probe = pl010_probe, | |
835 | .remove = pl010_remove, | |
1da177e4 LT |
836 | }; |
837 | ||
838 | static int __init pl010_init(void) | |
839 | { | |
d87a6d95 | 840 | printk(KERN_INFO "Serial: AMBA driver\n"); |
1da177e4 | 841 | |
bd8766b1 | 842 | return amba_driver_register(&pl010_driver); |
1da177e4 LT |
843 | } |
844 | ||
845 | static void __exit pl010_exit(void) | |
846 | { | |
847 | amba_driver_unregister(&pl010_driver); | |
1da177e4 LT |
848 | } |
849 | ||
850 | module_init(pl010_init); | |
851 | module_exit(pl010_exit); | |
852 | ||
853 | MODULE_AUTHOR("ARM Ltd/Deep Blue Solutions Ltd"); | |
d87a6d95 | 854 | MODULE_DESCRIPTION("ARM AMBA serial port driver"); |
1da177e4 | 855 | MODULE_LICENSE("GPL"); |