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clk: amba-clcd: convert to clk_prepare()/clk_unprepare()
[linux-2.6-block.git] / drivers / tty / serial / amba-pl010.c
CommitLineData
1da177e4 1/*
1da177e4
LT		 2 * Driver for AMBA serial ports
3 *
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5 *
6 * Copyright 1999 ARM Limited
7 * Copyright (C) 2000 Deep Blue Solutions Ltd.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 *
1da177e4
LT		 23 * This is a generic driver for ARM AMBA-type serial ports. They
24 * have a lot of 16550-like features, but are not register compatible.
25 * Note that although they do have CTS, DCD and DSR inputs, they do
26 * not have an RI input, nor do they have DTR or RTS outputs. If
27 * required, these have to be supplied via some other means (eg, GPIO)
28 * and hooked into this driver.
29 */
1da177e4
LT		 30
31#if defined(CONFIG_SERIAL_AMBA_PL010_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
32#define SUPPORT_SYSRQ
33#endif
34
35#include <linux/module.h>
36#include <linux/ioport.h>
37#include <linux/init.h>
38#include <linux/console.h>
39#include <linux/sysrq.h>
40#include <linux/device.h>
41#include <linux/tty.h>
42#include <linux/tty_flip.h>
43#include <linux/serial_core.h>
44#include <linux/serial.h>
a62c80e5
RK		 45#include <linux/amba/bus.h>
46#include <linux/amba/serial.h>
ed519ded 47#include <linux/clk.h>
5a0e3ad6 48#include <linux/slab.h>
1da177e4
LT		 49
50#include <asm/io.h>
1da177e4 51
4faf4e0e 52#define UART_NR 8
1da177e4
LT		 53
54#define SERIAL_AMBA_MAJOR 204
55#define SERIAL_AMBA_MINOR 16
56#define SERIAL_AMBA_NR UART_NR
57
58#define AMBA_ISR_PASS_LIMIT 256
59
1da177e4
LT		 60#define UART_RX_DATA(s) (((s) & UART01x_FR_RXFE) == 0)
61#define UART_TX_READY(s) (((s) & UART01x_FR_TXFF) == 0)
1da177e4 62
fbb18a27 63#define UART_DUMMY_RSR_RX 256
1da177e4
LT		 64#define UART_PORT_SIZE 64
65
1da177e4
LT		 66/*
67 * We wrap our port structure around the generic uart_port.
68 */
69struct uart_amba_port {
70 struct uart_port port;
ed519ded 71 struct clk *clk;
fbb18a27
RK		 72 struct amba_device *dev;
73 struct amba_pl010_data *data;
1da177e4
LT		 74 unsigned int old_status;
75};
76
b129a8cc 77static void pl010_stop_tx(struct uart_port *port)
1da177e4 78{
1b0646a0 79 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1da177e4
LT		 80 unsigned int cr;
81
1b0646a0 82 cr = readb(uap->port.membase + UART010_CR);
1da177e4 83 cr &= ~UART010_CR_TIE;
1b0646a0 84 writel(cr, uap->port.membase + UART010_CR);
1da177e4
LT		 85}
86
b129a8cc 87static void pl010_start_tx(struct uart_port *port)
1da177e4 88{
1b0646a0 89 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1da177e4
LT		 90 unsigned int cr;
91
1b0646a0 92 cr = readb(uap->port.membase + UART010_CR);
1da177e4 93 cr |= UART010_CR_TIE;
1b0646a0 94 writel(cr, uap->port.membase + UART010_CR);
1da177e4
LT		 95}
96
97static void pl010_stop_rx(struct uart_port *port)
98{
1b0646a0 99 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1da177e4
LT		 100 unsigned int cr;
101
1b0646a0 102 cr = readb(uap->port.membase + UART010_CR);
1da177e4 103 cr &= ~(UART010_CR_RIE | UART010_CR_RTIE);
1b0646a0 104 writel(cr, uap->port.membase + UART010_CR);
1da177e4
LT		 105}
106
107static void pl010_enable_ms(struct uart_port *port)
108{
1b0646a0 109 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1da177e4
LT		 110 unsigned int cr;
111
1b0646a0 112 cr = readb(uap->port.membase + UART010_CR);
1da177e4 113 cr |= UART010_CR_MSIE;
1b0646a0 114 writel(cr, uap->port.membase + UART010_CR);
1da177e4
LT		 115}
116
1b0646a0 117static void pl010_rx_chars(struct uart_amba_port *uap)
1da177e4 118{
ebd2c8f6 119 struct tty_struct *tty = uap->port.state->port.tty;
1da177e4
LT		 120 unsigned int status, ch, flag, rsr, max_count = 256;
121
1b0646a0 122 status = readb(uap->port.membase + UART01x_FR);
1da177e4 123 while (UART_RX_DATA(status) && max_count--) {
1b0646a0 124 ch = readb(uap->port.membase + UART01x_DR);
1da177e4
LT		 125 flag = TTY_NORMAL;
126
1b0646a0 127 uap->port.icount.rx++;
1da177e4
LT		 128
129 /*
130 * Note that the error handling code is
131 * out of the main execution path
132 */
1b0646a0 133 rsr = readb(uap->port.membase + UART01x_RSR) | UART_DUMMY_RSR_RX;
45849282 134 if (unlikely(rsr & UART01x_RSR_ANY)) {
1b0646a0 135 writel(0, uap->port.membase + UART01x_ECR);
a4ed06ad 136
1da177e4
LT		 137 if (rsr & UART01x_RSR_BE) {
138 rsr &= ~(UART01x_RSR_FE | UART01x_RSR_PE);
1b0646a0
RK		 139 uap->port.icount.brk++;
140 if (uart_handle_break(&uap->port))
1da177e4
LT		 141 goto ignore_char;
142 } else if (rsr & UART01x_RSR_PE)
1b0646a0 143 uap->port.icount.parity++;
1da177e4 144 else if (rsr & UART01x_RSR_FE)
1b0646a0 145 uap->port.icount.frame++;
1da177e4 146 if (rsr & UART01x_RSR_OE)
1b0646a0 147 uap->port.icount.overrun++;
1da177e4 148
1b0646a0 149 rsr &= uap->port.read_status_mask;
1da177e4
LT		 150
151 if (rsr & UART01x_RSR_BE)
152 flag = TTY_BREAK;
153 else if (rsr & UART01x_RSR_PE)
154 flag = TTY_PARITY;
155 else if (rsr & UART01x_RSR_FE)
156 flag = TTY_FRAME;
157 }
158
1b0646a0 159 if (uart_handle_sysrq_char(&uap->port, ch))
1da177e4
LT		 160 goto ignore_char;
161
1b0646a0 162 uart_insert_char(&uap->port, rsr, UART01x_RSR_OE, ch, flag);
05ab3014 163
1da177e4 164 ignore_char:
1b0646a0 165 status = readb(uap->port.membase + UART01x_FR);
1da177e4 166 }
db002b85 167 spin_unlock(&uap->port.lock);
1da177e4 168 tty_flip_buffer_push(tty);
db002b85 169 spin_lock(&uap->port.lock);
1da177e4
LT		 170}
171
1b0646a0 172static void pl010_tx_chars(struct uart_amba_port *uap)
1da177e4 173{
ebd2c8f6 174 struct circ_buf *xmit = &uap->port.state->xmit;
1da177e4
LT		 175 int count;
176
1b0646a0
RK		 177 if (uap->port.x_char) {
178 writel(uap->port.x_char, uap->port.membase + UART01x_DR);
179 uap->port.icount.tx++;
180 uap->port.x_char = 0;
1da177e4
LT		 181 return;
182 }
1b0646a0
RK		 183 if (uart_circ_empty(xmit) || uart_tx_stopped(&uap->port)) {
184 pl010_stop_tx(&uap->port);
1da177e4
LT		 185 return;
186 }
187
1b0646a0 188 count = uap->port.fifosize >> 1;
1da177e4 189 do {
1b0646a0 190 writel(xmit->buf[xmit->tail], uap->port.membase + UART01x_DR);
1da177e4 191 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1b0646a0 192 uap->port.icount.tx++;
1da177e4
LT		 193 if (uart_circ_empty(xmit))
194 break;
195 } while (--count > 0);
196
197 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1b0646a0 198 uart_write_wakeup(&uap->port);
1da177e4
LT		 199
200 if (uart_circ_empty(xmit))
1b0646a0 201 pl010_stop_tx(&uap->port);
1da177e4
LT		 202}
203
1b0646a0 204static void pl010_modem_status(struct uart_amba_port *uap)
1da177e4 205{
1da177e4
LT		 206 unsigned int status, delta;
207
98639a67 208 writel(0, uap->port.membase + UART010_ICR);
1da177e4 209
98639a67 210 status = readb(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY;
1da177e4
LT		 211
212 delta = status ^ uap->old_status;
213 uap->old_status = status;
214
215 if (!delta)
216 return;
217
218 if (delta & UART01x_FR_DCD)
219 uart_handle_dcd_change(&uap->port, status & UART01x_FR_DCD);
220
221 if (delta & UART01x_FR_DSR)
222 uap->port.icount.dsr++;
223
224 if (delta & UART01x_FR_CTS)
225 uart_handle_cts_change(&uap->port, status & UART01x_FR_CTS);
226
bdc04e31 227 wake_up_interruptible(&uap->port.state->port.delta_msr_wait);
1da177e4
LT		 228}
229
7d12e780 230static irqreturn_t pl010_int(int irq, void *dev_id)
1da177e4 231{
1b0646a0 232 struct uart_amba_port *uap = dev_id;
1da177e4
LT		 233 unsigned int status, pass_counter = AMBA_ISR_PASS_LIMIT;
234 int handled = 0;
235
1b0646a0 236 spin_lock(&uap->port.lock);
1da177e4 237
1b0646a0 238 status = readb(uap->port.membase + UART010_IIR);
1da177e4
LT		 239 if (status) {
240 do {
241 if (status & (UART010_IIR_RTIS | UART010_IIR_RIS))
1b0646a0 242 pl010_rx_chars(uap);
1da177e4 243 if (status & UART010_IIR_MIS)
1b0646a0 244 pl010_modem_status(uap);
1da177e4 245 if (status & UART010_IIR_TIS)
1b0646a0 246 pl010_tx_chars(uap);
1da177e4
LT		 247
248 if (pass_counter-- == 0)
249 break;
250
1b0646a0 251 status = readb(uap->port.membase + UART010_IIR);
1da177e4
LT		 252 } while (status & (UART010_IIR_RTIS | UART010_IIR_RIS |
253 UART010_IIR_TIS));
254 handled = 1;
255 }
256
1b0646a0 257 spin_unlock(&uap->port.lock);
1da177e4
LT		 258
259 return IRQ_RETVAL(handled);
260}
261
262static unsigned int pl010_tx_empty(struct uart_port *port)
263{
1b0646a0
RK		 264 struct uart_amba_port *uap = (struct uart_amba_port *)port;
265 unsigned int status = readb(uap->port.membase + UART01x_FR);
266 return status & UART01x_FR_BUSY ? 0 : TIOCSER_TEMT;
1da177e4
LT		 267}
268
269static unsigned int pl010_get_mctrl(struct uart_port *port)
270{
1b0646a0 271 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1da177e4
LT		 272 unsigned int result = 0;
273 unsigned int status;
274
1b0646a0 275 status = readb(uap->port.membase + UART01x_FR);
1da177e4
LT		 276 if (status & UART01x_FR_DCD)
277 result |= TIOCM_CAR;
278 if (status & UART01x_FR_DSR)
279 result |= TIOCM_DSR;
280 if (status & UART01x_FR_CTS)
281 result |= TIOCM_CTS;
282
283 return result;
284}
285
286static void pl010_set_mctrl(struct uart_port *port, unsigned int mctrl)
287{
288 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1da177e4 289
fbb18a27
RK		 290 if (uap->data)
291 uap->data->set_mctrl(uap->dev, uap->port.membase, mctrl);
1da177e4
LT		 292}
293
294static void pl010_break_ctl(struct uart_port *port, int break_state)
295{
1b0646a0 296 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1da177e4
LT		 297 unsigned long flags;
298 unsigned int lcr_h;
299
1b0646a0
RK		 300 spin_lock_irqsave(&uap->port.lock, flags);
301 lcr_h = readb(uap->port.membase + UART010_LCRH);
1da177e4
LT		 302 if (break_state == -1)
303 lcr_h |= UART01x_LCRH_BRK;
304 else
305 lcr_h &= ~UART01x_LCRH_BRK;
1b0646a0
RK		 306 writel(lcr_h, uap->port.membase + UART010_LCRH);
307 spin_unlock_irqrestore(&uap->port.lock, flags);
1da177e4
LT		 308}
309
310static int pl010_startup(struct uart_port *port)
311{
312 struct uart_amba_port *uap = (struct uart_amba_port *)port;
313 int retval;
314
ed519ded
RK		 315 /*
316 * Try to enable the clock producer.
317 */
318 retval = clk_enable(uap->clk);
319 if (retval)
320 goto out;
321
322 uap->port.uartclk = clk_get_rate(uap->clk);
323
1da177e4
LT		 324 /*
325 * Allocate the IRQ
326 */
1b0646a0 327 retval = request_irq(uap->port.irq, pl010_int, 0, "uart-pl010", uap);
1da177e4 328 if (retval)
ed519ded 329 goto clk_dis;
1da177e4
LT		 330
331 /*
332 * initialise the old status of the modem signals
333 */
1b0646a0 334 uap->old_status = readb(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY;
1da177e4
LT		 335
336 /*
337 * Finally, enable interrupts
338 */
98639a67 339 writel(UART01x_CR_UARTEN | UART010_CR_RIE | UART010_CR_RTIE,
1b0646a0 340 uap->port.membase + UART010_CR);
1da177e4
LT		 341
342 return 0;
ed519ded
RK		 343
344 clk_dis:
345 clk_disable(uap->clk);
346 out:
347 return retval;
1da177e4
LT		 348}
349
350static void pl010_shutdown(struct uart_port *port)
351{
1b0646a0
RK		 352 struct uart_amba_port *uap = (struct uart_amba_port *)port;
353
1da177e4
LT		 354 /*
355 * Free the interrupt
356 */
1b0646a0 357 free_irq(uap->port.irq, uap);
1da177e4
LT		 358
359 /*
360 * disable all interrupts, disable the port
361 */
1b0646a0 362 writel(0, uap->port.membase + UART010_CR);
1da177e4
LT		 363
364 /* disable break condition and fifos */
1b0646a0 365 writel(readb(uap->port.membase + UART010_LCRH) &
98639a67 366 ~(UART01x_LCRH_BRK | UART01x_LCRH_FEN),
1b0646a0 367 uap->port.membase + UART010_LCRH);
ed519ded
RK		 368
369 /*
370 * Shut down the clock producer
371 */
372 clk_disable(uap->clk);
1da177e4
LT		 373}
374
375static void
606d099c
AC		 376pl010_set_termios(struct uart_port *port, struct ktermios *termios,
377 struct ktermios *old)
1da177e4 378{
1b0646a0 379 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1da177e4
LT		 380 unsigned int lcr_h, old_cr;
381 unsigned long flags;
382 unsigned int baud, quot;
383
384 /*
385 * Ask the core to calculate the divisor for us.
386 */
1b0646a0 387 baud = uart_get_baud_rate(port, termios, old, 0, uap->port.uartclk/16);
1da177e4
LT		 388 quot = uart_get_divisor(port, baud);
389
390 switch (termios->c_cflag & CSIZE) {
391 case CS5:
392 lcr_h = UART01x_LCRH_WLEN_5;
393 break;
394 case CS6:
395 lcr_h = UART01x_LCRH_WLEN_6;
396 break;
397 case CS7:
398 lcr_h = UART01x_LCRH_WLEN_7;
399 break;
400 default: // CS8
401 lcr_h = UART01x_LCRH_WLEN_8;
402 break;
403 }
404 if (termios->c_cflag & CSTOPB)
405 lcr_h |= UART01x_LCRH_STP2;
406 if (termios->c_cflag & PARENB) {
407 lcr_h |= UART01x_LCRH_PEN;
408 if (!(termios->c_cflag & PARODD))
409 lcr_h |= UART01x_LCRH_EPS;
410 }
1b0646a0 411 if (uap->port.fifosize > 1)
1da177e4
LT		 412 lcr_h |= UART01x_LCRH_FEN;
413
1b0646a0 414 spin_lock_irqsave(&uap->port.lock, flags);
1da177e4
LT		 415
416 /*
417 * Update the per-port timeout.
418 */
419 uart_update_timeout(port, termios->c_cflag, baud);
420
1b0646a0 421 uap->port.read_status_mask = UART01x_RSR_OE;
1da177e4 422 if (termios->c_iflag & INPCK)
1b0646a0 423 uap->port.read_status_mask |= UART01x_RSR_FE | UART01x_RSR_PE;
1da177e4 424 if (termios->c_iflag & (BRKINT | PARMRK))
1b0646a0 425 uap->port.read_status_mask |= UART01x_RSR_BE;
1da177e4
LT		 426
427 /*
428 * Characters to ignore
429 */
1b0646a0 430 uap->port.ignore_status_mask = 0;
1da177e4 431 if (termios->c_iflag & IGNPAR)
1b0646a0 432 uap->port.ignore_status_mask |= UART01x_RSR_FE | UART01x_RSR_PE;
1da177e4 433 if (termios->c_iflag & IGNBRK) {
1b0646a0 434 uap->port.ignore_status_mask |= UART01x_RSR_BE;
1da177e4
LT		 435 /*
436 * If we're ignoring parity and break indicators,
437 * ignore overruns too (for real raw support).
438 */
439 if (termios->c_iflag & IGNPAR)
1b0646a0 440 uap->port.ignore_status_mask |= UART01x_RSR_OE;
1da177e4
LT		 441 }
442
443 /*
444 * Ignore all characters if CREAD is not set.
445 */
446 if ((termios->c_cflag & CREAD) == 0)
1b0646a0 447 uap->port.ignore_status_mask |= UART_DUMMY_RSR_RX;
1da177e4
LT		 448
449 /* first, disable everything */
1b0646a0 450 old_cr = readb(uap->port.membase + UART010_CR) & ~UART010_CR_MSIE;
1da177e4
LT		 451
452 if (UART_ENABLE_MS(port, termios->c_cflag))
453 old_cr |= UART010_CR_MSIE;
454
1b0646a0 455 writel(0, uap->port.membase + UART010_CR);
1da177e4
LT		 456
457 /* Set baud rate */
458 quot -= 1;
1b0646a0
RK		 459 writel((quot & 0xf00) >> 8, uap->port.membase + UART010_LCRM);
460 writel(quot & 0xff, uap->port.membase + UART010_LCRL);
1da177e4
LT		 461
462 /*
463 * ----------v----------v----------v----------v-----
464 * NOTE: MUST BE WRITTEN AFTER UARTLCR_M & UARTLCR_L
465 * ----------^----------^----------^----------^-----
466 */
1b0646a0
RK		 467 writel(lcr_h, uap->port.membase + UART010_LCRH);
468 writel(old_cr, uap->port.membase + UART010_CR);
1da177e4 469
1b0646a0 470 spin_unlock_irqrestore(&uap->port.lock, flags);
1da177e4
LT		 471}
472
476f771c 473static void pl010_set_ldisc(struct uart_port *port, int new)
7ed63d5e 474{
476f771c 475 if (new == N_PPS) {
7ed63d5e
RG		 476 port->flags |= UPF_HARDPPS_CD;
477 pl010_enable_ms(port);
478 } else
479 port->flags &= ~UPF_HARDPPS_CD;
480}
481
1da177e4
LT		 482static const char *pl010_type(struct uart_port *port)
483{
484 return port->type == PORT_AMBA ? "AMBA" : NULL;
485}
486
487/*
488 * Release the memory region(s) being used by 'port'
489 */
490static void pl010_release_port(struct uart_port *port)
491{
492 release_mem_region(port->mapbase, UART_PORT_SIZE);
493}
494
495/*
496 * Request the memory region(s) being used by 'port'
497 */
498static int pl010_request_port(struct uart_port *port)
499{
500 return request_mem_region(port->mapbase, UART_PORT_SIZE, "uart-pl010")
501 != NULL ? 0 : -EBUSY;
502}
503
504/*
505 * Configure/autoconfigure the port.
506 */
507static void pl010_config_port(struct uart_port *port, int flags)
508{
509 if (flags & UART_CONFIG_TYPE) {
510 port->type = PORT_AMBA;
511 pl010_request_port(port);
512 }
513}
514
515/*
516 * verify the new serial_struct (for TIOCSSERIAL).
517 */
518static int pl010_verify_port(struct uart_port *port, struct serial_struct *ser)
519{
520 int ret = 0;
521 if (ser->type != PORT_UNKNOWN && ser->type != PORT_AMBA)
522 ret = -EINVAL;
a62c4133 523 if (ser->irq < 0 || ser->irq >= nr_irqs)
1da177e4
LT		 524 ret = -EINVAL;
525 if (ser->baud_base < 9600)
526 ret = -EINVAL;
527 return ret;
528}
529
530static struct uart_ops amba_pl010_pops = {
531 .tx_empty = pl010_tx_empty,
532 .set_mctrl = pl010_set_mctrl,
533 .get_mctrl = pl010_get_mctrl,
534 .stop_tx = pl010_stop_tx,
535 .start_tx = pl010_start_tx,
536 .stop_rx = pl010_stop_rx,
537 .enable_ms = pl010_enable_ms,
538 .break_ctl = pl010_break_ctl,
539 .startup = pl010_startup,
540 .shutdown = pl010_shutdown,
541 .set_termios = pl010_set_termios,
7ed63d5e 542 .set_ldisc = pl010_set_ldisc,
1da177e4
LT		 543 .type = pl010_type,
544 .release_port = pl010_release_port,
545 .request_port = pl010_request_port,
546 .config_port = pl010_config_port,
547 .verify_port = pl010_verify_port,
548};
549
fbb18a27 550static struct uart_amba_port *amba_ports[UART_NR];
1da177e4
LT		 551
552#ifdef CONFIG_SERIAL_AMBA_PL010_CONSOLE
553
d358788f
RK		 554static void pl010_console_putchar(struct uart_port *port, int ch)
555{
1b0646a0 556 struct uart_amba_port *uap = (struct uart_amba_port *)port;
98639a67
RK		 557 unsigned int status;
558
559 do {
1b0646a0 560 status = readb(uap->port.membase + UART01x_FR);
d358788f 561 barrier();
98639a67 562 } while (!UART_TX_READY(status));
1b0646a0 563 writel(ch, uap->port.membase + UART01x_DR);
d358788f
RK		 564}
565
1da177e4
LT		 566static void
567pl010_console_write(struct console *co, const char *s, unsigned int count)
568{
1b0646a0 569 struct uart_amba_port *uap = amba_ports[co->index];
1da177e4 570 unsigned int status, old_cr;
1da177e4 571
ed519ded
RK		 572 clk_enable(uap->clk);
573
1da177e4
LT		 574 /*
575 * First save the CR then disable the interrupts
576 */
1b0646a0
RK		 577 old_cr = readb(uap->port.membase + UART010_CR);
578 writel(UART01x_CR_UARTEN, uap->port.membase + UART010_CR);
1da177e4 579
1b0646a0 580 uart_console_write(&uap->port, s, count, pl010_console_putchar);
1da177e4
LT		 581
582 /*
583 * Finally, wait for transmitter to become empty
584 * and restore the TCR
585 */
586 do {
1b0646a0 587 status = readb(uap->port.membase + UART01x_FR);
98639a67 588 barrier();
1da177e4 589 } while (status & UART01x_FR_BUSY);
1b0646a0 590 writel(old_cr, uap->port.membase + UART010_CR);
ed519ded
RK		 591
592 clk_disable(uap->clk);
1da177e4
LT		 593}
594
595static void __init
1b0646a0 596pl010_console_get_options(struct uart_amba_port *uap, int *baud,
1da177e4
LT		 597 int *parity, int *bits)
598{
1b0646a0 599 if (readb(uap->port.membase + UART010_CR) & UART01x_CR_UARTEN) {
1da177e4 600 unsigned int lcr_h, quot;
1b0646a0 601 lcr_h = readb(uap->port.membase + UART010_LCRH);
1da177e4
LT		 602
603 *parity = 'n';
604 if (lcr_h & UART01x_LCRH_PEN) {
605 if (lcr_h & UART01x_LCRH_EPS)
606 *parity = 'e';
607 else
608 *parity = 'o';
609 }
610
611 if ((lcr_h & 0x60) == UART01x_LCRH_WLEN_7)
612 *bits = 7;
613 else
614 *bits = 8;
615
1b0646a0
RK		 616 quot = readb(uap->port.membase + UART010_LCRL) |
617 readb(uap->port.membase + UART010_LCRM) << 8;
618 *baud = uap->port.uartclk / (16 * (quot + 1));
1da177e4
LT		 619 }
620}
621
622static int __init pl010_console_setup(struct console *co, char *options)
623{
1b0646a0 624 struct uart_amba_port *uap;
1da177e4
LT		 625 int baud = 38400;
626 int bits = 8;
627 int parity = 'n';
628 int flow = 'n';
629
630 /*
631 * Check whether an invalid uart number has been specified, and
632 * if so, search for the first available port that does have
633 * console support.
634 */
635 if (co->index >= UART_NR)
636 co->index = 0;
1b0646a0
RK		 637 uap = amba_ports[co->index];
638 if (!uap)
d28122a5 639 return -ENODEV;
1da177e4 640
ed519ded
RK		 641 uap->port.uartclk = clk_get_rate(uap->clk);
642
1da177e4
LT		 643 if (options)
644 uart_parse_options(options, &baud, &parity, &bits, &flow);
645 else
1b0646a0 646 pl010_console_get_options(uap, &baud, &parity, &bits);
1da177e4 647
1b0646a0 648 return uart_set_options(&uap->port, co, baud, parity, bits, flow);
1da177e4
LT		 649}
650
2d93486c 651static struct uart_driver amba_reg;
1da177e4
LT		 652static struct console amba_console = {
653 .name = "ttyAM",
654 .write = pl010_console_write,
655 .device = uart_console_device,
656 .setup = pl010_console_setup,
657 .flags = CON_PRINTBUFFER,
658 .index = -1,
659 .data = &amba_reg,
660};
661
1da177e4
LT		 662#define AMBA_CONSOLE &amba_console
663#else
664#define AMBA_CONSOLE NULL
665#endif
666
667static struct uart_driver amba_reg = {
668 .owner = THIS_MODULE,
669 .driver_name = "ttyAM",
670 .dev_name = "ttyAM",
671 .major = SERIAL_AMBA_MAJOR,
672 .minor = SERIAL_AMBA_MINOR,
673 .nr = UART_NR,
674 .cons = AMBA_CONSOLE,
675};
676
aa25afad 677static int pl010_probe(struct amba_device *dev, const struct amba_id *id)
1da177e4 678{
1b0646a0 679 struct uart_amba_port *uap;
fbb18a27
RK		 680 void __iomem *base;
681 int i, ret;
1da177e4 682
fbb18a27
RK		 683 for (i = 0; i < ARRAY_SIZE(amba_ports); i++)
684 if (amba_ports[i] == NULL)
685 break;
1da177e4 686
fbb18a27
RK		 687 if (i == ARRAY_SIZE(amba_ports)) {
688 ret = -EBUSY;
689 goto out;
1da177e4
LT		 690 }
691
1b0646a0
RK		 692 uap = kzalloc(sizeof(struct uart_amba_port), GFP_KERNEL);
693 if (!uap) {
fbb18a27
RK		 694 ret = -ENOMEM;
695 goto out;
696 }
697
dc890c2d 698 base = ioremap(dev->res.start, resource_size(&dev->res));
fbb18a27
RK		 699 if (!base) {
700 ret = -ENOMEM;
701 goto free;
702 }
703
ee569c43 704 uap->clk = clk_get(&dev->dev, NULL);
ed519ded
RK		 705 if (IS_ERR(uap->clk)) {
706 ret = PTR_ERR(uap->clk);
707 goto unmap;
708 }
709
1b0646a0
RK		 710 uap->port.dev = &dev->dev;
711 uap->port.mapbase = dev->res.start;
712 uap->port.membase = base;
713 uap->port.iotype = UPIO_MEM;
714 uap->port.irq = dev->irq[0];
1b0646a0
RK		 715 uap->port.fifosize = 16;
716 uap->port.ops = &amba_pl010_pops;
717 uap->port.flags = UPF_BOOT_AUTOCONF;
718 uap->port.line = i;
719 uap->dev = dev;
720 uap->data = dev->dev.platform_data;
721
722 amba_ports[i] = uap;
723
724 amba_set_drvdata(dev, uap);
725 ret = uart_add_one_port(&amba_reg, &uap->port);
fbb18a27
RK		 726 if (ret) {
727 amba_set_drvdata(dev, NULL);
728 amba_ports[i] = NULL;
ed519ded
RK		 729 clk_put(uap->clk);
730 unmap:
fbb18a27
RK		 731 iounmap(base);
732 free:
1b0646a0 733 kfree(uap);
fbb18a27 734 }
fbb18a27
RK		 735 out:
736 return ret;
1da177e4
LT		 737}
738
739static int pl010_remove(struct amba_device *dev)
740{
1b0646a0 741 struct uart_amba_port *uap = amba_get_drvdata(dev);
fbb18a27 742 int i;
1da177e4
LT		 743
744 amba_set_drvdata(dev, NULL);
745
1b0646a0 746 uart_remove_one_port(&amba_reg, &uap->port);
fbb18a27
RK		 747
748 for (i = 0; i < ARRAY_SIZE(amba_ports); i++)
1b0646a0 749 if (amba_ports[i] == uap)
fbb18a27
RK		 750 amba_ports[i] = NULL;
751
1b0646a0 752 iounmap(uap->port.membase);
ed519ded 753 clk_put(uap->clk);
1b0646a0 754 kfree(uap);
1da177e4
LT		 755 return 0;
756}
757
0370affe 758static int pl010_suspend(struct amba_device *dev, pm_message_t state)
1da177e4
LT		 759{
760 struct uart_amba_port *uap = amba_get_drvdata(dev);
761
762 if (uap)
763 uart_suspend_port(&amba_reg, &uap->port);
764
765 return 0;
766}
767
768static int pl010_resume(struct amba_device *dev)
769{
770 struct uart_amba_port *uap = amba_get_drvdata(dev);
771
772 if (uap)
773 uart_resume_port(&amba_reg, &uap->port);
774
775 return 0;
776}
777
2c39c9e1 778static struct amba_id pl010_ids[] = {
1da177e4
LT		 779 {
780 .id = 0x00041010,
781 .mask = 0x000fffff,
782 },
783 { 0, 0 },
784};
785
786static struct amba_driver pl010_driver = {
787 .drv = {
788 .name = "uart-pl010",
789 },
790 .id_table = pl010_ids,
791 .probe = pl010_probe,
792 .remove = pl010_remove,
793 .suspend = pl010_suspend,
794 .resume = pl010_resume,
795};
796
797static int __init pl010_init(void)
798{
799 int ret;
800
d87a6d95 801 printk(KERN_INFO "Serial: AMBA driver\n");
1da177e4
LT		 802
803 ret = uart_register_driver(&amba_reg);
804 if (ret == 0) {
805 ret = amba_driver_register(&pl010_driver);
806 if (ret)
807 uart_unregister_driver(&amba_reg);
808 }
809 return ret;
810}
811
812static void __exit pl010_exit(void)
813{
814 amba_driver_unregister(&pl010_driver);
815 uart_unregister_driver(&amba_reg);
816}
817
818module_init(pl010_init);
819module_exit(pl010_exit);
820
821MODULE_AUTHOR("ARM Ltd/Deep Blue Solutions Ltd");
d87a6d95 822MODULE_DESCRIPTION("ARM AMBA serial port driver");
1da177e4 823MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)