Commit | Line | Data |
---|---|---|
e3b3d0f5 | 1 | // SPDX-License-Identifier: GPL-2.0+ |
1da177e4 | 2 | /* |
1da177e4 LT |
3 | * Driver for AMBA serial ports |
4 | * | |
5 | * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. | |
6 | * | |
7 | * Copyright 1999 ARM Limited | |
8 | * Copyright (C) 2000 Deep Blue Solutions Ltd. | |
9 | * | |
1da177e4 LT |
10 | * This is a generic driver for ARM AMBA-type serial ports. They |
11 | * have a lot of 16550-like features, but are not register compatible. | |
12 | * Note that although they do have CTS, DCD and DSR inputs, they do | |
13 | * not have an RI input, nor do they have DTR or RTS outputs. If | |
14 | * required, these have to be supplied via some other means (eg, GPIO) | |
15 | * and hooked into this driver. | |
16 | */ | |
1da177e4 LT |
17 | |
18 | #if defined(CONFIG_SERIAL_AMBA_PL010_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) | |
19 | #define SUPPORT_SYSRQ | |
20 | #endif | |
21 | ||
22 | #include <linux/module.h> | |
23 | #include <linux/ioport.h> | |
24 | #include <linux/init.h> | |
25 | #include <linux/console.h> | |
26 | #include <linux/sysrq.h> | |
27 | #include <linux/device.h> | |
28 | #include <linux/tty.h> | |
29 | #include <linux/tty_flip.h> | |
30 | #include <linux/serial_core.h> | |
31 | #include <linux/serial.h> | |
a62c80e5 RK |
32 | #include <linux/amba/bus.h> |
33 | #include <linux/amba/serial.h> | |
ed519ded | 34 | #include <linux/clk.h> |
5a0e3ad6 | 35 | #include <linux/slab.h> |
44acd260 | 36 | #include <linux/io.h> |
1da177e4 | 37 | |
4faf4e0e | 38 | #define UART_NR 8 |
1da177e4 LT |
39 | |
40 | #define SERIAL_AMBA_MAJOR 204 | |
41 | #define SERIAL_AMBA_MINOR 16 | |
42 | #define SERIAL_AMBA_NR UART_NR | |
43 | ||
44 | #define AMBA_ISR_PASS_LIMIT 256 | |
45 | ||
1da177e4 LT |
46 | #define UART_RX_DATA(s) (((s) & UART01x_FR_RXFE) == 0) |
47 | #define UART_TX_READY(s) (((s) & UART01x_FR_TXFF) == 0) | |
1da177e4 | 48 | |
fbb18a27 | 49 | #define UART_DUMMY_RSR_RX 256 |
1da177e4 LT |
50 | #define UART_PORT_SIZE 64 |
51 | ||
1da177e4 LT |
52 | /* |
53 | * We wrap our port structure around the generic uart_port. | |
54 | */ | |
55 | struct uart_amba_port { | |
56 | struct uart_port port; | |
ed519ded | 57 | struct clk *clk; |
fbb18a27 RK |
58 | struct amba_device *dev; |
59 | struct amba_pl010_data *data; | |
1da177e4 LT |
60 | unsigned int old_status; |
61 | }; | |
62 | ||
b129a8cc | 63 | static void pl010_stop_tx(struct uart_port *port) |
1da177e4 | 64 | { |
b70e5e9d FF |
65 | struct uart_amba_port *uap = |
66 | container_of(port, struct uart_amba_port, port); | |
1da177e4 LT |
67 | unsigned int cr; |
68 | ||
1b0646a0 | 69 | cr = readb(uap->port.membase + UART010_CR); |
1da177e4 | 70 | cr &= ~UART010_CR_TIE; |
1b0646a0 | 71 | writel(cr, uap->port.membase + UART010_CR); |
1da177e4 LT |
72 | } |
73 | ||
b129a8cc | 74 | static void pl010_start_tx(struct uart_port *port) |
1da177e4 | 75 | { |
b70e5e9d FF |
76 | struct uart_amba_port *uap = |
77 | container_of(port, struct uart_amba_port, port); | |
1da177e4 LT |
78 | unsigned int cr; |
79 | ||
1b0646a0 | 80 | cr = readb(uap->port.membase + UART010_CR); |
1da177e4 | 81 | cr |= UART010_CR_TIE; |
1b0646a0 | 82 | writel(cr, uap->port.membase + UART010_CR); |
1da177e4 LT |
83 | } |
84 | ||
85 | static void pl010_stop_rx(struct uart_port *port) | |
86 | { | |
b70e5e9d FF |
87 | struct uart_amba_port *uap = |
88 | container_of(port, struct uart_amba_port, port); | |
1da177e4 LT |
89 | unsigned int cr; |
90 | ||
1b0646a0 | 91 | cr = readb(uap->port.membase + UART010_CR); |
1da177e4 | 92 | cr &= ~(UART010_CR_RIE | UART010_CR_RTIE); |
1b0646a0 | 93 | writel(cr, uap->port.membase + UART010_CR); |
1da177e4 LT |
94 | } |
95 | ||
cab68f89 PH |
96 | static void pl010_disable_ms(struct uart_port *port) |
97 | { | |
98 | struct uart_amba_port *uap = (struct uart_amba_port *)port; | |
99 | unsigned int cr; | |
100 | ||
101 | cr = readb(uap->port.membase + UART010_CR); | |
102 | cr &= ~UART010_CR_MSIE; | |
103 | writel(cr, uap->port.membase + UART010_CR); | |
104 | } | |
105 | ||
1da177e4 LT |
106 | static void pl010_enable_ms(struct uart_port *port) |
107 | { | |
b70e5e9d FF |
108 | struct uart_amba_port *uap = |
109 | container_of(port, struct uart_amba_port, port); | |
1da177e4 LT |
110 | unsigned int cr; |
111 | ||
1b0646a0 | 112 | cr = readb(uap->port.membase + UART010_CR); |
1da177e4 | 113 | cr |= UART010_CR_MSIE; |
1b0646a0 | 114 | writel(cr, uap->port.membase + UART010_CR); |
1da177e4 LT |
115 | } |
116 | ||
1b0646a0 | 117 | static void pl010_rx_chars(struct uart_amba_port *uap) |
1da177e4 | 118 | { |
1da177e4 LT |
119 | unsigned int status, ch, flag, rsr, max_count = 256; |
120 | ||
1b0646a0 | 121 | status = readb(uap->port.membase + UART01x_FR); |
1da177e4 | 122 | while (UART_RX_DATA(status) && max_count--) { |
1b0646a0 | 123 | ch = readb(uap->port.membase + UART01x_DR); |
1da177e4 LT |
124 | flag = TTY_NORMAL; |
125 | ||
1b0646a0 | 126 | uap->port.icount.rx++; |
1da177e4 LT |
127 | |
128 | /* | |
129 | * Note that the error handling code is | |
130 | * out of the main execution path | |
131 | */ | |
1b0646a0 | 132 | rsr = readb(uap->port.membase + UART01x_RSR) | UART_DUMMY_RSR_RX; |
45849282 | 133 | if (unlikely(rsr & UART01x_RSR_ANY)) { |
1b0646a0 | 134 | writel(0, uap->port.membase + UART01x_ECR); |
a4ed06ad | 135 | |
1da177e4 LT |
136 | if (rsr & UART01x_RSR_BE) { |
137 | rsr &= ~(UART01x_RSR_FE | UART01x_RSR_PE); | |
1b0646a0 RK |
138 | uap->port.icount.brk++; |
139 | if (uart_handle_break(&uap->port)) | |
1da177e4 LT |
140 | goto ignore_char; |
141 | } else if (rsr & UART01x_RSR_PE) | |
1b0646a0 | 142 | uap->port.icount.parity++; |
1da177e4 | 143 | else if (rsr & UART01x_RSR_FE) |
1b0646a0 | 144 | uap->port.icount.frame++; |
1da177e4 | 145 | if (rsr & UART01x_RSR_OE) |
1b0646a0 | 146 | uap->port.icount.overrun++; |
1da177e4 | 147 | |
1b0646a0 | 148 | rsr &= uap->port.read_status_mask; |
1da177e4 LT |
149 | |
150 | if (rsr & UART01x_RSR_BE) | |
151 | flag = TTY_BREAK; | |
152 | else if (rsr & UART01x_RSR_PE) | |
153 | flag = TTY_PARITY; | |
154 | else if (rsr & UART01x_RSR_FE) | |
155 | flag = TTY_FRAME; | |
156 | } | |
157 | ||
1b0646a0 | 158 | if (uart_handle_sysrq_char(&uap->port, ch)) |
1da177e4 LT |
159 | goto ignore_char; |
160 | ||
1b0646a0 | 161 | uart_insert_char(&uap->port, rsr, UART01x_RSR_OE, ch, flag); |
05ab3014 | 162 | |
1da177e4 | 163 | ignore_char: |
1b0646a0 | 164 | status = readb(uap->port.membase + UART01x_FR); |
1da177e4 | 165 | } |
db002b85 | 166 | spin_unlock(&uap->port.lock); |
2e124b4a | 167 | tty_flip_buffer_push(&uap->port.state->port); |
db002b85 | 168 | spin_lock(&uap->port.lock); |
1da177e4 LT |
169 | } |
170 | ||
1b0646a0 | 171 | static void pl010_tx_chars(struct uart_amba_port *uap) |
1da177e4 | 172 | { |
ebd2c8f6 | 173 | struct circ_buf *xmit = &uap->port.state->xmit; |
1da177e4 LT |
174 | int count; |
175 | ||
1b0646a0 RK |
176 | if (uap->port.x_char) { |
177 | writel(uap->port.x_char, uap->port.membase + UART01x_DR); | |
178 | uap->port.icount.tx++; | |
179 | uap->port.x_char = 0; | |
1da177e4 LT |
180 | return; |
181 | } | |
1b0646a0 RK |
182 | if (uart_circ_empty(xmit) || uart_tx_stopped(&uap->port)) { |
183 | pl010_stop_tx(&uap->port); | |
1da177e4 LT |
184 | return; |
185 | } | |
186 | ||
1b0646a0 | 187 | count = uap->port.fifosize >> 1; |
1da177e4 | 188 | do { |
1b0646a0 | 189 | writel(xmit->buf[xmit->tail], uap->port.membase + UART01x_DR); |
1da177e4 | 190 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); |
1b0646a0 | 191 | uap->port.icount.tx++; |
1da177e4 LT |
192 | if (uart_circ_empty(xmit)) |
193 | break; | |
194 | } while (--count > 0); | |
195 | ||
196 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
1b0646a0 | 197 | uart_write_wakeup(&uap->port); |
1da177e4 LT |
198 | |
199 | if (uart_circ_empty(xmit)) | |
1b0646a0 | 200 | pl010_stop_tx(&uap->port); |
1da177e4 LT |
201 | } |
202 | ||
1b0646a0 | 203 | static void pl010_modem_status(struct uart_amba_port *uap) |
1da177e4 | 204 | { |
1da177e4 LT |
205 | unsigned int status, delta; |
206 | ||
98639a67 | 207 | writel(0, uap->port.membase + UART010_ICR); |
1da177e4 | 208 | |
98639a67 | 209 | status = readb(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY; |
1da177e4 LT |
210 | |
211 | delta = status ^ uap->old_status; | |
212 | uap->old_status = status; | |
213 | ||
214 | if (!delta) | |
215 | return; | |
216 | ||
217 | if (delta & UART01x_FR_DCD) | |
218 | uart_handle_dcd_change(&uap->port, status & UART01x_FR_DCD); | |
219 | ||
220 | if (delta & UART01x_FR_DSR) | |
221 | uap->port.icount.dsr++; | |
222 | ||
223 | if (delta & UART01x_FR_CTS) | |
224 | uart_handle_cts_change(&uap->port, status & UART01x_FR_CTS); | |
225 | ||
bdc04e31 | 226 | wake_up_interruptible(&uap->port.state->port.delta_msr_wait); |
1da177e4 LT |
227 | } |
228 | ||
7d12e780 | 229 | static irqreturn_t pl010_int(int irq, void *dev_id) |
1da177e4 | 230 | { |
1b0646a0 | 231 | struct uart_amba_port *uap = dev_id; |
1da177e4 LT |
232 | unsigned int status, pass_counter = AMBA_ISR_PASS_LIMIT; |
233 | int handled = 0; | |
234 | ||
1b0646a0 | 235 | spin_lock(&uap->port.lock); |
1da177e4 | 236 | |
1b0646a0 | 237 | status = readb(uap->port.membase + UART010_IIR); |
1da177e4 LT |
238 | if (status) { |
239 | do { | |
240 | if (status & (UART010_IIR_RTIS | UART010_IIR_RIS)) | |
1b0646a0 | 241 | pl010_rx_chars(uap); |
1da177e4 | 242 | if (status & UART010_IIR_MIS) |
1b0646a0 | 243 | pl010_modem_status(uap); |
1da177e4 | 244 | if (status & UART010_IIR_TIS) |
1b0646a0 | 245 | pl010_tx_chars(uap); |
1da177e4 LT |
246 | |
247 | if (pass_counter-- == 0) | |
248 | break; | |
249 | ||
1b0646a0 | 250 | status = readb(uap->port.membase + UART010_IIR); |
1da177e4 LT |
251 | } while (status & (UART010_IIR_RTIS | UART010_IIR_RIS | |
252 | UART010_IIR_TIS)); | |
253 | handled = 1; | |
254 | } | |
255 | ||
1b0646a0 | 256 | spin_unlock(&uap->port.lock); |
1da177e4 LT |
257 | |
258 | return IRQ_RETVAL(handled); | |
259 | } | |
260 | ||
261 | static unsigned int pl010_tx_empty(struct uart_port *port) | |
262 | { | |
b70e5e9d FF |
263 | struct uart_amba_port *uap = |
264 | container_of(port, struct uart_amba_port, port); | |
1b0646a0 RK |
265 | unsigned int status = readb(uap->port.membase + UART01x_FR); |
266 | return status & UART01x_FR_BUSY ? 0 : TIOCSER_TEMT; | |
1da177e4 LT |
267 | } |
268 | ||
269 | static unsigned int pl010_get_mctrl(struct uart_port *port) | |
270 | { | |
b70e5e9d FF |
271 | struct uart_amba_port *uap = |
272 | container_of(port, struct uart_amba_port, port); | |
1da177e4 LT |
273 | unsigned int result = 0; |
274 | unsigned int status; | |
275 | ||
1b0646a0 | 276 | status = readb(uap->port.membase + UART01x_FR); |
1da177e4 LT |
277 | if (status & UART01x_FR_DCD) |
278 | result |= TIOCM_CAR; | |
279 | if (status & UART01x_FR_DSR) | |
280 | result |= TIOCM_DSR; | |
281 | if (status & UART01x_FR_CTS) | |
282 | result |= TIOCM_CTS; | |
283 | ||
284 | return result; | |
285 | } | |
286 | ||
287 | static void pl010_set_mctrl(struct uart_port *port, unsigned int mctrl) | |
288 | { | |
b70e5e9d FF |
289 | struct uart_amba_port *uap = |
290 | container_of(port, struct uart_amba_port, port); | |
1da177e4 | 291 | |
fbb18a27 RK |
292 | if (uap->data) |
293 | uap->data->set_mctrl(uap->dev, uap->port.membase, mctrl); | |
1da177e4 LT |
294 | } |
295 | ||
296 | static void pl010_break_ctl(struct uart_port *port, int break_state) | |
297 | { | |
b70e5e9d FF |
298 | struct uart_amba_port *uap = |
299 | container_of(port, struct uart_amba_port, port); | |
1da177e4 LT |
300 | unsigned long flags; |
301 | unsigned int lcr_h; | |
302 | ||
1b0646a0 RK |
303 | spin_lock_irqsave(&uap->port.lock, flags); |
304 | lcr_h = readb(uap->port.membase + UART010_LCRH); | |
1da177e4 LT |
305 | if (break_state == -1) |
306 | lcr_h |= UART01x_LCRH_BRK; | |
307 | else | |
308 | lcr_h &= ~UART01x_LCRH_BRK; | |
1b0646a0 RK |
309 | writel(lcr_h, uap->port.membase + UART010_LCRH); |
310 | spin_unlock_irqrestore(&uap->port.lock, flags); | |
1da177e4 LT |
311 | } |
312 | ||
313 | static int pl010_startup(struct uart_port *port) | |
314 | { | |
b70e5e9d FF |
315 | struct uart_amba_port *uap = |
316 | container_of(port, struct uart_amba_port, port); | |
1da177e4 LT |
317 | int retval; |
318 | ||
ed519ded RK |
319 | /* |
320 | * Try to enable the clock producer. | |
321 | */ | |
1c4c4394 | 322 | retval = clk_prepare_enable(uap->clk); |
ed519ded | 323 | if (retval) |
1c4c4394 | 324 | goto out; |
ed519ded RK |
325 | |
326 | uap->port.uartclk = clk_get_rate(uap->clk); | |
327 | ||
1da177e4 LT |
328 | /* |
329 | * Allocate the IRQ | |
330 | */ | |
1b0646a0 | 331 | retval = request_irq(uap->port.irq, pl010_int, 0, "uart-pl010", uap); |
1da177e4 | 332 | if (retval) |
ed519ded | 333 | goto clk_dis; |
1da177e4 LT |
334 | |
335 | /* | |
336 | * initialise the old status of the modem signals | |
337 | */ | |
1b0646a0 | 338 | uap->old_status = readb(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY; |
1da177e4 LT |
339 | |
340 | /* | |
341 | * Finally, enable interrupts | |
342 | */ | |
98639a67 | 343 | writel(UART01x_CR_UARTEN | UART010_CR_RIE | UART010_CR_RTIE, |
1b0646a0 | 344 | uap->port.membase + UART010_CR); |
1da177e4 LT |
345 | |
346 | return 0; | |
ed519ded RK |
347 | |
348 | clk_dis: | |
1c4c4394 | 349 | clk_disable_unprepare(uap->clk); |
ed519ded RK |
350 | out: |
351 | return retval; | |
1da177e4 LT |
352 | } |
353 | ||
354 | static void pl010_shutdown(struct uart_port *port) | |
355 | { | |
b70e5e9d FF |
356 | struct uart_amba_port *uap = |
357 | container_of(port, struct uart_amba_port, port); | |
1b0646a0 | 358 | |
1da177e4 LT |
359 | /* |
360 | * Free the interrupt | |
361 | */ | |
1b0646a0 | 362 | free_irq(uap->port.irq, uap); |
1da177e4 LT |
363 | |
364 | /* | |
365 | * disable all interrupts, disable the port | |
366 | */ | |
1b0646a0 | 367 | writel(0, uap->port.membase + UART010_CR); |
1da177e4 LT |
368 | |
369 | /* disable break condition and fifos */ | |
1b0646a0 | 370 | writel(readb(uap->port.membase + UART010_LCRH) & |
98639a67 | 371 | ~(UART01x_LCRH_BRK | UART01x_LCRH_FEN), |
1b0646a0 | 372 | uap->port.membase + UART010_LCRH); |
ed519ded RK |
373 | |
374 | /* | |
375 | * Shut down the clock producer | |
376 | */ | |
1c4c4394 | 377 | clk_disable_unprepare(uap->clk); |
1da177e4 LT |
378 | } |
379 | ||
380 | static void | |
606d099c AC |
381 | pl010_set_termios(struct uart_port *port, struct ktermios *termios, |
382 | struct ktermios *old) | |
1da177e4 | 383 | { |
b70e5e9d FF |
384 | struct uart_amba_port *uap = |
385 | container_of(port, struct uart_amba_port, port); | |
1da177e4 LT |
386 | unsigned int lcr_h, old_cr; |
387 | unsigned long flags; | |
388 | unsigned int baud, quot; | |
389 | ||
390 | /* | |
391 | * Ask the core to calculate the divisor for us. | |
392 | */ | |
1b0646a0 | 393 | baud = uart_get_baud_rate(port, termios, old, 0, uap->port.uartclk/16); |
1da177e4 LT |
394 | quot = uart_get_divisor(port, baud); |
395 | ||
396 | switch (termios->c_cflag & CSIZE) { | |
397 | case CS5: | |
398 | lcr_h = UART01x_LCRH_WLEN_5; | |
399 | break; | |
400 | case CS6: | |
401 | lcr_h = UART01x_LCRH_WLEN_6; | |
402 | break; | |
403 | case CS7: | |
404 | lcr_h = UART01x_LCRH_WLEN_7; | |
405 | break; | |
406 | default: // CS8 | |
407 | lcr_h = UART01x_LCRH_WLEN_8; | |
408 | break; | |
409 | } | |
410 | if (termios->c_cflag & CSTOPB) | |
411 | lcr_h |= UART01x_LCRH_STP2; | |
412 | if (termios->c_cflag & PARENB) { | |
413 | lcr_h |= UART01x_LCRH_PEN; | |
414 | if (!(termios->c_cflag & PARODD)) | |
415 | lcr_h |= UART01x_LCRH_EPS; | |
416 | } | |
1b0646a0 | 417 | if (uap->port.fifosize > 1) |
1da177e4 LT |
418 | lcr_h |= UART01x_LCRH_FEN; |
419 | ||
1b0646a0 | 420 | spin_lock_irqsave(&uap->port.lock, flags); |
1da177e4 LT |
421 | |
422 | /* | |
423 | * Update the per-port timeout. | |
424 | */ | |
425 | uart_update_timeout(port, termios->c_cflag, baud); | |
426 | ||
1b0646a0 | 427 | uap->port.read_status_mask = UART01x_RSR_OE; |
1da177e4 | 428 | if (termios->c_iflag & INPCK) |
1b0646a0 | 429 | uap->port.read_status_mask |= UART01x_RSR_FE | UART01x_RSR_PE; |
ef8b9ddc | 430 | if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) |
1b0646a0 | 431 | uap->port.read_status_mask |= UART01x_RSR_BE; |
1da177e4 LT |
432 | |
433 | /* | |
434 | * Characters to ignore | |
435 | */ | |
1b0646a0 | 436 | uap->port.ignore_status_mask = 0; |
1da177e4 | 437 | if (termios->c_iflag & IGNPAR) |
1b0646a0 | 438 | uap->port.ignore_status_mask |= UART01x_RSR_FE | UART01x_RSR_PE; |
1da177e4 | 439 | if (termios->c_iflag & IGNBRK) { |
1b0646a0 | 440 | uap->port.ignore_status_mask |= UART01x_RSR_BE; |
1da177e4 LT |
441 | /* |
442 | * If we're ignoring parity and break indicators, | |
443 | * ignore overruns too (for real raw support). | |
444 | */ | |
445 | if (termios->c_iflag & IGNPAR) | |
1b0646a0 | 446 | uap->port.ignore_status_mask |= UART01x_RSR_OE; |
1da177e4 LT |
447 | } |
448 | ||
449 | /* | |
450 | * Ignore all characters if CREAD is not set. | |
451 | */ | |
452 | if ((termios->c_cflag & CREAD) == 0) | |
1b0646a0 | 453 | uap->port.ignore_status_mask |= UART_DUMMY_RSR_RX; |
1da177e4 LT |
454 | |
455 | /* first, disable everything */ | |
1b0646a0 | 456 | old_cr = readb(uap->port.membase + UART010_CR) & ~UART010_CR_MSIE; |
1da177e4 LT |
457 | |
458 | if (UART_ENABLE_MS(port, termios->c_cflag)) | |
459 | old_cr |= UART010_CR_MSIE; | |
460 | ||
1b0646a0 | 461 | writel(0, uap->port.membase + UART010_CR); |
1da177e4 LT |
462 | |
463 | /* Set baud rate */ | |
464 | quot -= 1; | |
1b0646a0 RK |
465 | writel((quot & 0xf00) >> 8, uap->port.membase + UART010_LCRM); |
466 | writel(quot & 0xff, uap->port.membase + UART010_LCRL); | |
1da177e4 LT |
467 | |
468 | /* | |
469 | * ----------v----------v----------v----------v----- | |
470 | * NOTE: MUST BE WRITTEN AFTER UARTLCR_M & UARTLCR_L | |
471 | * ----------^----------^----------^----------^----- | |
472 | */ | |
1b0646a0 RK |
473 | writel(lcr_h, uap->port.membase + UART010_LCRH); |
474 | writel(old_cr, uap->port.membase + UART010_CR); | |
1da177e4 | 475 | |
1b0646a0 | 476 | spin_unlock_irqrestore(&uap->port.lock, flags); |
1da177e4 LT |
477 | } |
478 | ||
732a84a0 | 479 | static void pl010_set_ldisc(struct uart_port *port, struct ktermios *termios) |
7ed63d5e | 480 | { |
732a84a0 | 481 | if (termios->c_line == N_PPS) { |
7ed63d5e | 482 | port->flags |= UPF_HARDPPS_CD; |
d41510ce | 483 | spin_lock_irq(&port->lock); |
7ed63d5e | 484 | pl010_enable_ms(port); |
d41510ce | 485 | spin_unlock_irq(&port->lock); |
cab68f89 | 486 | } else { |
7ed63d5e | 487 | port->flags &= ~UPF_HARDPPS_CD; |
cab68f89 PH |
488 | if (!UART_ENABLE_MS(port, termios->c_cflag)) { |
489 | spin_lock_irq(&port->lock); | |
490 | pl010_disable_ms(port); | |
491 | spin_unlock_irq(&port->lock); | |
492 | } | |
493 | } | |
7ed63d5e RG |
494 | } |
495 | ||
1da177e4 LT |
496 | static const char *pl010_type(struct uart_port *port) |
497 | { | |
498 | return port->type == PORT_AMBA ? "AMBA" : NULL; | |
499 | } | |
500 | ||
501 | /* | |
502 | * Release the memory region(s) being used by 'port' | |
503 | */ | |
504 | static void pl010_release_port(struct uart_port *port) | |
505 | { | |
506 | release_mem_region(port->mapbase, UART_PORT_SIZE); | |
507 | } | |
508 | ||
509 | /* | |
510 | * Request the memory region(s) being used by 'port' | |
511 | */ | |
512 | static int pl010_request_port(struct uart_port *port) | |
513 | { | |
514 | return request_mem_region(port->mapbase, UART_PORT_SIZE, "uart-pl010") | |
515 | != NULL ? 0 : -EBUSY; | |
516 | } | |
517 | ||
518 | /* | |
519 | * Configure/autoconfigure the port. | |
520 | */ | |
521 | static void pl010_config_port(struct uart_port *port, int flags) | |
522 | { | |
523 | if (flags & UART_CONFIG_TYPE) { | |
524 | port->type = PORT_AMBA; | |
525 | pl010_request_port(port); | |
526 | } | |
527 | } | |
528 | ||
529 | /* | |
530 | * verify the new serial_struct (for TIOCSSERIAL). | |
531 | */ | |
532 | static int pl010_verify_port(struct uart_port *port, struct serial_struct *ser) | |
533 | { | |
534 | int ret = 0; | |
535 | if (ser->type != PORT_UNKNOWN && ser->type != PORT_AMBA) | |
536 | ret = -EINVAL; | |
a62c4133 | 537 | if (ser->irq < 0 || ser->irq >= nr_irqs) |
1da177e4 LT |
538 | ret = -EINVAL; |
539 | if (ser->baud_base < 9600) | |
540 | ret = -EINVAL; | |
541 | return ret; | |
542 | } | |
543 | ||
2331e068 | 544 | static const struct uart_ops amba_pl010_pops = { |
1da177e4 LT |
545 | .tx_empty = pl010_tx_empty, |
546 | .set_mctrl = pl010_set_mctrl, | |
547 | .get_mctrl = pl010_get_mctrl, | |
548 | .stop_tx = pl010_stop_tx, | |
549 | .start_tx = pl010_start_tx, | |
550 | .stop_rx = pl010_stop_rx, | |
551 | .enable_ms = pl010_enable_ms, | |
552 | .break_ctl = pl010_break_ctl, | |
553 | .startup = pl010_startup, | |
554 | .shutdown = pl010_shutdown, | |
555 | .set_termios = pl010_set_termios, | |
7ed63d5e | 556 | .set_ldisc = pl010_set_ldisc, |
1da177e4 LT |
557 | .type = pl010_type, |
558 | .release_port = pl010_release_port, | |
559 | .request_port = pl010_request_port, | |
560 | .config_port = pl010_config_port, | |
561 | .verify_port = pl010_verify_port, | |
562 | }; | |
563 | ||
fbb18a27 | 564 | static struct uart_amba_port *amba_ports[UART_NR]; |
1da177e4 LT |
565 | |
566 | #ifdef CONFIG_SERIAL_AMBA_PL010_CONSOLE | |
567 | ||
d358788f RK |
568 | static void pl010_console_putchar(struct uart_port *port, int ch) |
569 | { | |
b70e5e9d FF |
570 | struct uart_amba_port *uap = |
571 | container_of(port, struct uart_amba_port, port); | |
98639a67 RK |
572 | unsigned int status; |
573 | ||
574 | do { | |
1b0646a0 | 575 | status = readb(uap->port.membase + UART01x_FR); |
d358788f | 576 | barrier(); |
98639a67 | 577 | } while (!UART_TX_READY(status)); |
1b0646a0 | 578 | writel(ch, uap->port.membase + UART01x_DR); |
d358788f RK |
579 | } |
580 | ||
1da177e4 LT |
581 | static void |
582 | pl010_console_write(struct console *co, const char *s, unsigned int count) | |
583 | { | |
1b0646a0 | 584 | struct uart_amba_port *uap = amba_ports[co->index]; |
1da177e4 | 585 | unsigned int status, old_cr; |
1da177e4 | 586 | |
ed519ded RK |
587 | clk_enable(uap->clk); |
588 | ||
1da177e4 LT |
589 | /* |
590 | * First save the CR then disable the interrupts | |
591 | */ | |
1b0646a0 RK |
592 | old_cr = readb(uap->port.membase + UART010_CR); |
593 | writel(UART01x_CR_UARTEN, uap->port.membase + UART010_CR); | |
1da177e4 | 594 | |
1b0646a0 | 595 | uart_console_write(&uap->port, s, count, pl010_console_putchar); |
1da177e4 LT |
596 | |
597 | /* | |
598 | * Finally, wait for transmitter to become empty | |
599 | * and restore the TCR | |
600 | */ | |
601 | do { | |
1b0646a0 | 602 | status = readb(uap->port.membase + UART01x_FR); |
98639a67 | 603 | barrier(); |
1da177e4 | 604 | } while (status & UART01x_FR_BUSY); |
1b0646a0 | 605 | writel(old_cr, uap->port.membase + UART010_CR); |
ed519ded RK |
606 | |
607 | clk_disable(uap->clk); | |
1da177e4 LT |
608 | } |
609 | ||
610 | static void __init | |
1b0646a0 | 611 | pl010_console_get_options(struct uart_amba_port *uap, int *baud, |
1da177e4 LT |
612 | int *parity, int *bits) |
613 | { | |
1b0646a0 | 614 | if (readb(uap->port.membase + UART010_CR) & UART01x_CR_UARTEN) { |
1da177e4 | 615 | unsigned int lcr_h, quot; |
1b0646a0 | 616 | lcr_h = readb(uap->port.membase + UART010_LCRH); |
1da177e4 LT |
617 | |
618 | *parity = 'n'; | |
619 | if (lcr_h & UART01x_LCRH_PEN) { | |
620 | if (lcr_h & UART01x_LCRH_EPS) | |
621 | *parity = 'e'; | |
622 | else | |
623 | *parity = 'o'; | |
624 | } | |
625 | ||
626 | if ((lcr_h & 0x60) == UART01x_LCRH_WLEN_7) | |
627 | *bits = 7; | |
628 | else | |
629 | *bits = 8; | |
630 | ||
1b0646a0 RK |
631 | quot = readb(uap->port.membase + UART010_LCRL) | |
632 | readb(uap->port.membase + UART010_LCRM) << 8; | |
633 | *baud = uap->port.uartclk / (16 * (quot + 1)); | |
1da177e4 LT |
634 | } |
635 | } | |
636 | ||
637 | static int __init pl010_console_setup(struct console *co, char *options) | |
638 | { | |
1b0646a0 | 639 | struct uart_amba_port *uap; |
1da177e4 LT |
640 | int baud = 38400; |
641 | int bits = 8; | |
642 | int parity = 'n'; | |
643 | int flow = 'n'; | |
36b8f1e2 | 644 | int ret; |
1da177e4 LT |
645 | |
646 | /* | |
647 | * Check whether an invalid uart number has been specified, and | |
648 | * if so, search for the first available port that does have | |
649 | * console support. | |
650 | */ | |
651 | if (co->index >= UART_NR) | |
652 | co->index = 0; | |
1b0646a0 RK |
653 | uap = amba_ports[co->index]; |
654 | if (!uap) | |
d28122a5 | 655 | return -ENODEV; |
1da177e4 | 656 | |
36b8f1e2 RK |
657 | ret = clk_prepare(uap->clk); |
658 | if (ret) | |
659 | return ret; | |
660 | ||
ed519ded RK |
661 | uap->port.uartclk = clk_get_rate(uap->clk); |
662 | ||
1da177e4 LT |
663 | if (options) |
664 | uart_parse_options(options, &baud, &parity, &bits, &flow); | |
665 | else | |
1b0646a0 | 666 | pl010_console_get_options(uap, &baud, &parity, &bits); |
1da177e4 | 667 | |
1b0646a0 | 668 | return uart_set_options(&uap->port, co, baud, parity, bits, flow); |
1da177e4 LT |
669 | } |
670 | ||
2d93486c | 671 | static struct uart_driver amba_reg; |
1da177e4 LT |
672 | static struct console amba_console = { |
673 | .name = "ttyAM", | |
674 | .write = pl010_console_write, | |
675 | .device = uart_console_device, | |
676 | .setup = pl010_console_setup, | |
677 | .flags = CON_PRINTBUFFER, | |
678 | .index = -1, | |
679 | .data = &amba_reg, | |
680 | }; | |
681 | ||
1da177e4 LT |
682 | #define AMBA_CONSOLE &amba_console |
683 | #else | |
684 | #define AMBA_CONSOLE NULL | |
685 | #endif | |
686 | ||
bd8766b1 | 687 | static DEFINE_MUTEX(amba_reg_lock); |
1da177e4 LT |
688 | static struct uart_driver amba_reg = { |
689 | .owner = THIS_MODULE, | |
690 | .driver_name = "ttyAM", | |
691 | .dev_name = "ttyAM", | |
692 | .major = SERIAL_AMBA_MAJOR, | |
693 | .minor = SERIAL_AMBA_MINOR, | |
694 | .nr = UART_NR, | |
695 | .cons = AMBA_CONSOLE, | |
696 | }; | |
697 | ||
aa25afad | 698 | static int pl010_probe(struct amba_device *dev, const struct amba_id *id) |
1da177e4 | 699 | { |
1b0646a0 | 700 | struct uart_amba_port *uap; |
fbb18a27 RK |
701 | void __iomem *base; |
702 | int i, ret; | |
1da177e4 | 703 | |
fbb18a27 RK |
704 | for (i = 0; i < ARRAY_SIZE(amba_ports); i++) |
705 | if (amba_ports[i] == NULL) | |
706 | break; | |
1da177e4 | 707 | |
44acd260 TB |
708 | if (i == ARRAY_SIZE(amba_ports)) |
709 | return -EBUSY; | |
1da177e4 | 710 | |
44acd260 TB |
711 | uap = devm_kzalloc(&dev->dev, sizeof(struct uart_amba_port), |
712 | GFP_KERNEL); | |
713 | if (!uap) | |
714 | return -ENOMEM; | |
fbb18a27 | 715 | |
44acd260 TB |
716 | base = devm_ioremap(&dev->dev, dev->res.start, |
717 | resource_size(&dev->res)); | |
718 | if (!base) | |
719 | return -ENOMEM; | |
fbb18a27 | 720 | |
44acd260 TB |
721 | uap->clk = devm_clk_get(&dev->dev, NULL); |
722 | if (IS_ERR(uap->clk)) | |
723 | return PTR_ERR(uap->clk); | |
ed519ded | 724 | |
1b0646a0 RK |
725 | uap->port.dev = &dev->dev; |
726 | uap->port.mapbase = dev->res.start; | |
727 | uap->port.membase = base; | |
728 | uap->port.iotype = UPIO_MEM; | |
729 | uap->port.irq = dev->irq[0]; | |
1b0646a0 RK |
730 | uap->port.fifosize = 16; |
731 | uap->port.ops = &amba_pl010_pops; | |
732 | uap->port.flags = UPF_BOOT_AUTOCONF; | |
733 | uap->port.line = i; | |
734 | uap->dev = dev; | |
574de559 | 735 | uap->data = dev_get_platdata(&dev->dev); |
1b0646a0 RK |
736 | |
737 | amba_ports[i] = uap; | |
738 | ||
739 | amba_set_drvdata(dev, uap); | |
bd8766b1 SS |
740 | |
741 | mutex_lock(&amba_reg_lock); | |
742 | if (!amba_reg.state) { | |
743 | ret = uart_register_driver(&amba_reg); | |
744 | if (ret < 0) { | |
745 | mutex_unlock(&amba_reg_lock); | |
746 | dev_err(uap->port.dev, | |
747 | "Failed to register AMBA-PL010 driver\n"); | |
748 | return ret; | |
749 | } | |
750 | } | |
751 | mutex_unlock(&amba_reg_lock); | |
752 | ||
1b0646a0 | 753 | ret = uart_add_one_port(&amba_reg, &uap->port); |
44acd260 | 754 | if (ret) |
fbb18a27 | 755 | amba_ports[i] = NULL; |
44acd260 | 756 | |
fbb18a27 | 757 | return ret; |
1da177e4 LT |
758 | } |
759 | ||
760 | static int pl010_remove(struct amba_device *dev) | |
761 | { | |
1b0646a0 | 762 | struct uart_amba_port *uap = amba_get_drvdata(dev); |
fbb18a27 | 763 | int i; |
bd8766b1 | 764 | bool busy = false; |
1da177e4 | 765 | |
1b0646a0 | 766 | uart_remove_one_port(&amba_reg, &uap->port); |
fbb18a27 RK |
767 | |
768 | for (i = 0; i < ARRAY_SIZE(amba_ports); i++) | |
1b0646a0 | 769 | if (amba_ports[i] == uap) |
fbb18a27 | 770 | amba_ports[i] = NULL; |
bd8766b1 SS |
771 | else if (amba_ports[i]) |
772 | busy = true; | |
773 | ||
774 | if (!busy) | |
775 | uart_unregister_driver(&amba_reg); | |
fbb18a27 | 776 | |
1da177e4 LT |
777 | return 0; |
778 | } | |
779 | ||
95468240 UH |
780 | #ifdef CONFIG_PM_SLEEP |
781 | static int pl010_suspend(struct device *dev) | |
1da177e4 | 782 | { |
95468240 | 783 | struct uart_amba_port *uap = dev_get_drvdata(dev); |
1da177e4 LT |
784 | |
785 | if (uap) | |
786 | uart_suspend_port(&amba_reg, &uap->port); | |
787 | ||
788 | return 0; | |
789 | } | |
790 | ||
95468240 | 791 | static int pl010_resume(struct device *dev) |
1da177e4 | 792 | { |
95468240 | 793 | struct uart_amba_port *uap = dev_get_drvdata(dev); |
1da177e4 LT |
794 | |
795 | if (uap) | |
796 | uart_resume_port(&amba_reg, &uap->port); | |
797 | ||
798 | return 0; | |
799 | } | |
95468240 UH |
800 | #endif |
801 | ||
802 | static SIMPLE_DEV_PM_OPS(pl010_dev_pm_ops, pl010_suspend, pl010_resume); | |
1da177e4 | 803 | |
5337e549 | 804 | static const struct amba_id pl010_ids[] = { |
1da177e4 LT |
805 | { |
806 | .id = 0x00041010, | |
807 | .mask = 0x000fffff, | |
808 | }, | |
809 | { 0, 0 }, | |
810 | }; | |
811 | ||
a664a119 DM |
812 | MODULE_DEVICE_TABLE(amba, pl010_ids); |
813 | ||
1da177e4 LT |
814 | static struct amba_driver pl010_driver = { |
815 | .drv = { | |
816 | .name = "uart-pl010", | |
95468240 | 817 | .pm = &pl010_dev_pm_ops, |
1da177e4 LT |
818 | }, |
819 | .id_table = pl010_ids, | |
820 | .probe = pl010_probe, | |
821 | .remove = pl010_remove, | |
1da177e4 LT |
822 | }; |
823 | ||
824 | static int __init pl010_init(void) | |
825 | { | |
d87a6d95 | 826 | printk(KERN_INFO "Serial: AMBA driver\n"); |
1da177e4 | 827 | |
bd8766b1 | 828 | return amba_driver_register(&pl010_driver); |
1da177e4 LT |
829 | } |
830 | ||
831 | static void __exit pl010_exit(void) | |
832 | { | |
833 | amba_driver_unregister(&pl010_driver); | |
1da177e4 LT |
834 | } |
835 | ||
836 | module_init(pl010_init); | |
837 | module_exit(pl010_exit); | |
838 | ||
839 | MODULE_AUTHOR("ARM Ltd/Deep Blue Solutions Ltd"); | |
d87a6d95 | 840 | MODULE_DESCRIPTION("ARM AMBA serial port driver"); |
1da177e4 | 841 | MODULE_LICENSE("GPL"); |